DsPIC33 EP64 GS502 Datasheet

dsPIC33EPXXGS50X FAMILY
16-Bit Digital Signal Controllers for Digital Power Applications with

Interconnected High-Speed PWM, ADC, PGA and Comparators
Operating Conditions Advanced Analog Features

• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS • High-Speed ADC module:
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS - 12-bit with 4 dedicated SAR ADC cores and
one shared SAR ADC core
Flash Architecture - Configurable resolution (up to 12-bit) for each
• Dual Partition Flash Program Memory with ADC core
Live Update (64-Kbyte devices): - Up to 3.25 Msps conversion rate per channel
- Supports programming while operating at 12-bit resolution
- Supports partition soft swap - 12 to 22 single-ended inputs
- Dedicated result buffer for each analog channel
Core: 16-Bit dsPIC33E CPU - Flexible and independent ADC trigger sources
• Code-Efficient (C and Assembly) Architecture - Two digital comparators
• Two 40-Bit Wide Accumulators - Two oversampling filters for increased
• Single-Cycle (MAC/MPY) with Dual Data Fetch resolution
• Single-Cycle Mixed-Sign MUL Plus • Four Rail-to-Rail Comparators with Hysteresis:
Hardware Divide - Dedicated 12-bit Digital-to-Analog Converter
• 32-Bit Multiply Support (DAC) for each analog comparator
• Two Additional Working Register Sets (reduces - Up to two DAC reference outputs
context switching) - Up to two external reference inputs
• Two Programmable Gain Amplifiers:
Clock Management
- Single-ended or independent ground reference
• ±0.9% Internal Oscillator
- Five selectable gains (4x, 8x, 16x, 32x and 64x)
• Programmable PLLs and Oscillator Clock Sources
- 40 MHz gain bandwidth
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT) Interconnected SMPS Peripherals
• Fast Wake-up and Start-up
• Reduces CPU Interaction to Improve Performance
Power Management • Flexible PWM Trigger Options for
ADC Conversions
• Low-Power Management modes (Sleep,
Idle, Doze) • High-Speed Comparator Truncates PWM
(15 ns typical):
• Integrated Power-on Reset and Brown-out Reset
- Supports Cycle-by-Cycle Current mode control
• 0.5 mA/MHz Dynamic Current (typical)
- Current Reset mode (variable frequency)
• 10 μA IPD Current (typical)
High-Speed PWM Timers/Output Compare/Input Capture

• Five PWM Generators (two outputs per generator) • Five 16-Bit and up to Two 32-Bit Timers/Counters
• Individual Time Base and Duty Cycle for each PWM • Four Output Compare (OC) modules, Configurable
as Timers/Counters
• 1.04 ns PWM Resolution (frequency, duty cycle,
dead time and phase) • Four Input Capture (IC) modules
• Supports Center-Aligned, Redundant, Complementary
and True Independent Output modes
• Independent Fault and Current-Limit Inputs
• Output Override Control
• PWM Support for AC/DC, DC/DC, Inverters, PFC
and Lighting
 2013-2017 Microchip Technology Inc. DS70005127D-page 1

Communication Interfaces Qualification and Class B Support
• Two UART modules (15 Mbps): • AEC-Q100 REVG (Grade 1, -40°C to +125°C)
- Supports LIN/J2602 protocols and IrDA® • Class B Safety Library, IEC 60730
• Two 4-Wire SPI modules (15 Mbps) • The 6x6x0.5 mm UQFN Package is Designed and
• Two I2C modules (up to 1 Mbaud) with SMBus Optimized to ease IPC9592B 2nd Level
Support Temperature Cycle Qualification
Input/Output Debugger Development Support

• Constant-Current Source (10 µA nominal) • In-Circuit and In-Application Programming
• Sink/Source up to 12mA/15mA, respectively; • Five Program and Three Complex
Pin-Specific for Standard VOH/VOL Data Breakpoints
• 5V Tolerant Pins • IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Selectable, Open-Drain Pull-ups and Pull-Downs • Trace and Run-Time Watch
• External Interrupts on All I/O Pins
• Peripheral Pin Select (PPS) to allow Function
Remap with Six Virtual I/Os
General Purpose I/O (GPIO)
12-Bit
Remappable Peripherals
Constant-Current Source
Program Memory Bytes
ADC
Analog Comparator
External Interrupts(3)
RAM (Bytes)
DAC Output
Packages
Output Compare
Reference Clock
Analog Inputs
Input Capture
S&H Circuits
PGA
Pins
I2C
Timers(1)
Device
PWM(2)
UART
SPI
dsPIC33EP16GS502 28 16K 2K 21 5 4 4 2 2 5x2 3 1 2 12 5 2 4 1 1 SOIC,

dsPIC33EP32GS502 28 32K 4K 21 5 4 4 2 2 5x2 3 1 2 12 5 2 4 1 1 QFN-S,
dsPIC33EP64GS502 28 64K 8K 21 5 4 4 2 2 5x2 3 1 2 12 5 2 4 1 1 UQFN
dsPIC33EP16GS504 44 16K 2K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1

QFN,
dsPIC33EP32GS504 44 32K 4K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1
TQFP
dsPIC33EP64GS504 44 64K 8K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1
dsPIC33EP16GS505 48 16K 2K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1
dsPIC33EP32GS505 48 32K 4K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1 TQFP
dsPIC33EP64GS505 48 64K 8K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1
dsPIC33EP16GS506 64 16K 2K 53 5 4 4 2 2 5x2 4 1 2 22 5 2 4 2 1
dsPIC33EP32GS506 64 32K 4K 53 5 4 4 2 2 5x2 4 1 2 22 5 2 4 2 1 TQFP
dsPIC33EP64GS506 64 64K 8K 53 5 4 4 2 2 5x2 4 1 2 22 5 2 4 2 1
Note 1: The external clock for Timer1, Timer2 and Timer3 is remappable.
2: PWM4 and PWM5 are remappable on all devices except the 64-pin devices.
3: External interrupts, INT0 and INT4, are not remappable.
DS70005127D-page 2  2013-2017 Microchip Technology Inc.

Pin Diagrams
28-Pin SOIC
MCLR 1 28 AVDD
RA0 2 27 AVSS
RA1 3 26 RA3
RA2 4 25 RA4
dsPIC33EPXXGS502
RB0 5 24 RB14
RB9 6 23 RB13
RB10 7 22 RB12
VSS 8 21 RB11
RB1 9 20 VCAP
RB2 10 19 VSS
RB3 11 18 RB7
RB4 12 17 RB6
VDD 13 16 RB5
RB8 14 15 RB15
Pin Pin Function Pin Pin Function
1 MCLR 15 PGEC3/SCL2/RP47/RB15
2 AN0/PGA1P1/CMP1A/RA0 16 TDO/AN19/PGA2N2/RP37/RB5
3 AN1/PGA1P2/PGA2P1/CMP1B/RA1 17 PGED1/TDI/AN20/SCL1/RP38/RB6
4 AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2 18 PGEC1/AN21/SDA1/RP39/RB7
5 AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0 19 VSS
6 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9 20 VCAP
7 AN5/CMP2D/CMP3B/ISRC3/RP42/RB10 21 TMS/PWM3H/RP43/RB11
8 Vss 22 TCK/PWM3L/RP44/RB12
9 OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1 23 PWM2H/RP45/RB13
10 OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2 24 PWM2L/RP46/RB14
11 PGED2/AN18/DACOUT1/INT0/RP35/RB3 25 PWM1H/RA4
12 PGEC2/ADTRG31/EXTREF1/RP36/RB4 26 PWM1L/RA3
13 VDD 27 AVSS
14 PGED3/SDA2/FLT31/RP40/RB8 28 AVDD
Legend: Shaded pins are up to 5 VDC tolerant.

RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.

Pin Diagrams (Continued)
28-Pin QFN-S, UQFN
MCLR
AVDD
AVSS
RA1
RA0
RA3
RA4
28
27
26
25
24
23
22
RA2 1 21 RB14
RB0 2 20 RB13
RB9 3 19 RB12
RB10 4 dsPIC33EPXXGS502 18 RB11
VSS 5 17 VCAP
RB1 6 16 VSS
RB2 7 15 RB7
10
12
13
14
11
8
9
RB4
RB3
VDD
RB8
RB15
RB5
RB6
1 AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2 15 PGEC1/AN21/SDA1/RP39/RB7
2 AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0 16 VSS
3 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9 17 VCAP
4 AN5/CMP2D/CMP3B/ISRC3/RP42/RB10 18 TMS/PWM3H/RP43/RB11
5 Vss 19 TCK/PWM3L/RP44/RB12
6 OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1 20 PWM2H/RP45/RB13
7 OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2 21 PWM2L/RP46/RB14
8 PGED2/AN18/DACOUT1/INT0/RP35/RB3 22 PWM1H/RA4
9 PGEC2/ADTRG31/EXTREF1/RP36/RB4 23 PWM1L/RA3
10 VDD 24 AVSS
11 PGED3/SDA2/FLT31/RP40/RB8 25 AVDD
12 PGEC3/SCL2/RP47/RB15 26 MCLR
13 TDO/AN19/PGA2N2/RP37/RB5 27 AN0/PGA1P1/CMP1A/RA0
14 PGED1/TDI/AN20/SCL1/RP38/RB6 28 AN1/PGA1P2/PGA2P1/CMP1B/RA1


44-Pin QFN
RB15
RC8
RC7
RC2
RB6
RB5
RB8
RB4
RB3
VDD
VSS
39
44
43
42
41
40
38
37
36
35
34
RB7 1 33 RB2
RC4 2 32 RB1
RC5 3 31 RC1
RC6 4 30 VSS
RC3 5 29 VDD
dsPIC33EPXXGS504
VSS 6 28 RC10
VCAP 7 27 RC9
RB11 8 26 RB10
RB12 9 25 RB9
RB13 10 24 RB0
RB14 11 23 RA2
12
13
14
15
16
17
18
19
20
21
22
RA4
RA3
RC0
RC13
AVDD
RC11
RC12
RA0
RA1
MCLR
AVSS

1 PGEC1/AN21/SDA1/RP39/RB7 23 AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2
2 AN1ALT/RP52/RC4 24 AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0
3 AN0ALT/RP53/RC5 25 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
4 AN17/RP54/RC6 26 AN5/CMP2D/CMP3B/ISRC3/RP42/RB10
5 RP51/RC3 27 AN11/PGA1N3/RP57/RC9
6 VSS 28 AN10/PGA1P4/EXTREF2/RP58/RC10
7 VCAP 29 VDD
8 TMS/PWM3H/RP43/RB11 30 VSS
9 TCK/PWM3L/RP44/RB12 31 AN8/PGA2P4/CMP4C/RP49/RC1
10 PWM2H/RP45/RB13 32 OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
11 PWM2L/RP46/RB14 33 OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2
12 PWM1H/RA4 34 PGED2/AN18/DACOUT1/INT0/RP35/RB3
13 PWM1L/RA3 35 PGEC2/ADTRG31/RP36/RB4
14 FLT12/RP48/RC0 36 AN9/CMP4D/EXTREF1/RP50 /RC2
15 FLT11/RP61/RC13 37 ASDA1/RP55/RC7
16 AVSS 38 ASCL1/RP56/RC8
17 AVDD 39 VSS
18 MCLR 40 VDD
19 AN12/ISRC1/RP59/RC11 41 PGED3/SDA2/FLT31/RP40/RB8
20 AN14/PGA2N3/RP60/RC12 42 PGEC3/SCL2/RP47/RB15


44-Pin TQFP
RB15
RC8
RC7
RC2
RB6
RB5
RB8
RB4
RB3
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
RB7 1 33 RB2
RC4 2 32 RB1
RC5 3 31 RC1
RC6 4 30 VSS
RC3 5 29 VDD
VSS 6 dsPIC33EPXXGS504 28 RC10
VCAP 7 27 RC9
RB11 8 26 RB10
RB12 9 25 RB9
RB13 10 24 RB0
RB14 11 23 RA2
12
13
14
15
16
17
18
19
20
21
22
MCLR
AVSS
RA4
RA3
RC0
RC13
AVDD
RC11
RC12
RA0
RA1

7 VCAP 29 VDD
8 TMS/PWM3H/RP43/RB11 30 VSS
16 AVSS 38 ASCL1/RP56/RC8
17 AVDD 39 VSS
18 MCLR 40 VDD


48-Pin TQFP
RB15
RC8
RC7
RC2
RB6
RB5
RB8
RB4
RB3
VDD
VSS
N/C
48
47
46
45
44
43
42
41
40
39
38
37
RB7 1 36 RB2
RC4 2 35 RB1
RC5 3 34 RC1
RC6 4 33 N/C
RC3 5 32 Vss
VSS 6 dsPIC33EPXXGS505 31 VDD
VCAP 7 30 RC10
N/C 8 29 RC9
RB11 9 28 RB10
RB12 10 27 RB9
RB13 11 26 RB0
RB14 12 25 RA2
13
14
15
16
17
18
19
20
21
22
23
24
RA4
RA3
RC0
RC13
RC11
RC12
RA0
RA1
N/C
MCLR
AVSS
AVDD

7 VCAP 31 VDD
8 N/C 32 VSS
9 TMS/PWM3H/RP43/RB11 33 N/C
17 N/C 41 ASCL1/RP56/RC8
18 AVSS 42 VSS
19 AVDD 43 VDD
20 MCLR 44 N/C


RD15
RB14
RB13
RB12
RB11
VCAP
RD1
RD4
RC3
RD6
RD5
RC6
RC5
RC4
RB7
VDD
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RD3 1 48 RB6
RA4 2 47 RD0
RA3 3 46 RB5
RC0 4 45 RD11
RC13 5 44 RB15
RD10 6 43 RB8
MCLR 7 42 RD8
RD12 8 41 Vss
VSS 9
dsPIC33EPXXGS506 40 RD9
VDD 10 39 RD14
RC11 11 38 VDD
RC12 12 37 RC8
RA0 13 36 RC7
RA1 14 35 RC2
RA2 15 34 RC14
RB0 16 33 RB4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVSS
VSS
RB9
RB10
AVDD
RD7
RD13
RC9
RC10
VDD
RC1
RB1
RB2
RD2
RC15
RB3
1 PWM4L/RD3 33 PGEC2/ADTRG31/RP36/RB4
2 PWM1H/RA4 34 RP62/RC14
3 PWM1L/RA3 35 AN9/CMP4D/EXTREF1/RP50/RC2
5 FLT11/RP61/RC13 37 ASCL1/RP56/RC8
6 FLT10/RD10 38 VDD
7 MCLR 39 RD14
8 FLT9/T5CK/RD12 40 RD9
9 VSS 41 VSS
10 VDD 42 RD8
13 AN0/PGA1P1/CMP1A/RA0 45 INT4/RD11
14 AN1/PGA1P2/PGA2P1/CMP1B/RA1 46 TDO/AN19/PGA2N2/RP37/RB5
15 AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2 47 T4CK/RD0
16 AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0 48 PGED1/TDI/AN20/SCL1/RP38/RB6
17 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9 49 PGEC1/AN21/SDA1/RP39/RB7
18 AN5/CMP2D/CMP3B/ISRC3/RP42/RB10 50 AN1ALT/RP52/RC4
19 AVDD 51 AN0ALT/RP53/RC5
20 AVSS 52 AN17/RP54/RC6
21 AN15/RD7 53 RD5
22 AN13/DACOUT2/RD13 54 PWM5H/RD6
23 AN11/PGA1N3/RP57/RC9 55 PWM5L/RP51/RC3
24 AN10/PGA1P4/EXTREF2/RP58/RC10 56 VCAP
25 VSS 57 VDD
26 VDD 58 RD4
27 AN8/PGA2P4/CMP4C/RP49/RC1 59 RD15
28 OSC1/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1 60 TMS/PWM3H/RP43/RB11
29 OSC2/CLKO/AN7/PGA1N2/CMP3D/CMP4B/RP34/RB2 61 TCK/PWM3L/RP44/RB12
30 AN16/RD2 62 PWM2H/RP45/RB13
31 ASDA2/RP63/RC15 63 PWM2L/RP46/RB14
32 PGED2/AN18/DACOUT1/ASCL2/INT0/RP35/RB3 64 PWM4H/RD1


Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 15
3.0 CPU............................................................................................................................................................................................ 21
4.0 Memory Organization ................................................................................................................................................................. 31
5.0 Flash Program Memory.............................................................................................................................................................. 77
6.0 Resets ....................................................................................................................................................................................... 85
7.0 Interrupt Controller ..................................................................................................................................................................... 89
8.0 Oscillator Configuration ............................................................................................................................................................ 103
9.0 Power-Saving Features............................................................................................................................................................ 115
10.0 I/O Ports ................................................................................................................................................................................... 125
11.0 Timer1 ...................................................................................................................................................................................... 163
12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 167
13.0 Input Capture............................................................................................................................................................................ 171
14.0 Output Compare....................................................................................................................................................................... 175
15.0 High-Speed PWM..................................................................................................................................................................... 181
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 207
17.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 215
18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 223
19.0 High-Speed, 12-Bit Analog-to-Digital Converter (ADC)............................................................................................................ 229
20.0 High-Speed Analog Comparator .............................................................................................................................................. 263
21.0 Programmable Gain Amplifier (PGA) ....................................................................................................................................... 271
22.0 Constant-Current Source ......................................................................................................................................................... 275
23.0 Special Features ...................................................................................................................................................................... 277
24.0 Instruction Set Summary .......................................................................................................................................................... 289
25.0 Development Support............................................................................................................................................................... 299
26.0 Electrical Characteristics .......................................................................................................................................................... 303
27.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 349
28.0 Packaging Information.............................................................................................................................................................. 353
Appendix A: Revision History............................................................................................................................................................. 377
Index ................................................................................................................................................................................................. 379
The Microchip Web Site ..................................................................................................................................................................... 385
Customer Change Notification Service .............................................................................................................................................. 385
Customer Support .............................................................................................................................................................................. 385
Product Identification System ............................................................................................................................................................ 387

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1.0 DEVICE OVERVIEW This document contains device-specific information for
the dsPIC33EPXXGS50X Digital Signal Controller (DSC)
Note 1: This data sheet summarizes the features devices.
of the dsPIC33EPXXGS50X family of dsPIC33EPXXGS50X devices contain extensive
devices. It is not intended to be a com- Digital Signal Processor (DSP) functionality with a
prehensive resource. To complement the high-performance, 16-bit MCU architecture.
information in this data sheet, refer to the
related section of the “dsPIC33/PIC24 Figure 1-1 shows a general block diagram of the core
Family Reference Manual”, which is and peripheral modules. Table 1-1 lists the functions of
available from the Microchip web site the various pins shown in the pinout diagrams.
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific
register and bit information.
FIGURE 1-1: dsPIC33EPXXGS50X FAMILY BLOCK DIAGRAM
CPU
Refer to Figure 3-1 for CPU diagram details.
PORTA
16
Power-up
Timer PORTB
Timing Oscillator
Start-up 16
Generation
Timer
OSC1/CLKI
POR/BOR PORTC
MCLR
Watchdog
Timer
VDD, VSS
AVDD, AVSS
Peripheral Modules PORTD
Input Output
PGA1, I2C1,
ADC Captures Compares
PGA2 I2C2
1-4 1-4
Remappable
Pins
Constant Analog Ports

PWMs Timers SPI1, UART1,
Current Comparators
Source 5x2 1-5 SPI2 UART2
1-4

TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Buffer
Pin Name(1) PPS Description
Type Type
AN0-AN21 I Analog No Analog input channels.
AN0ALT-AN1ALT I Analog No Alternate analog input channels.
CLKI I ST/ No External clock source input. Always associated with OSC1 pin function.
CMOS Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
CLKO O — No Always associated with OSC2 pin function.
OSC1 I ST/ No Oscillator crystal input. ST buffer when configured in RC mode; CMOS
CMOS otherwise.
OSC2 I/O — No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
REFCLKO O — Yes Reference clock output.
IC1-IC4 I ST Yes Capture Inputs 1 through 4.
OCFA I ST Yes Compare Fault A input (for compare channels).
OC1-OC4 O — Yes Compare Outputs 1 through 4.
INT0 I ST No External Interrupt 0.
INT1 I ST Yes External Interrupt 1.
INT2 I ST Yes External Interrupt 2.
INT4 I ST No External Interrupt 4.
RA0-RA4 I/O ST No PORTA is a bidirectional I/O port.
RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.
RC0-RC15 I/O ST No PORTC is a bidirectional I/O port.
RD0-RD15 I/O ST No PORTD is a bidirectional I/O port.
T1CK I ST Yes Timer1 external clock input.
T4CK I ST No Timer4 external clock input.
T5CK I ST No Timer5 external clock input.
U1CTS I ST Yes UART1 Clear-to-Send.
U1RTS O — Yes UART1 Request-to-Send.
U1RX I ST Yes UART1 receive.
U1TX O — Yes UART1 transmit.
BCLK1 O ST Yes UART1 IrDA® baud clock output.
U2CTS I ST Yes UART2 Clear-to-Send.
U2RTS O — Yes UART2 Request-to-Send.
U2RX I ST Yes UART2 receive.
U2TX O — Yes UART2 transmit.
BCLK2 O ST Yes UART2 IrDA baud clock output.
SCK1 I/O ST Yes Synchronous serial clock input/output for SPI1.
SDI1 I ST Yes SPI1 data in.
SDO1 O — Yes SPI1 data out.
SS1 I/O ST Yes SPI1 slave synchronization or frame pulse I/O.
SCK2 I/O ST Yes Synchronous serial clock input/output for SPI2.
SDI2 I ST Yes SPI2 data in.
SDO2 O — Yes SPI2 data out.
SS2 I/O ST Yes SPI2 slave synchronization or frame pulse I/O.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select TTL = TTL input buffer
1: Not all pins are available in all packages variants. See the “Pin Diagrams” section for pin availability.
2: These pins are dedicated on 64-pin devices.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer
Type Type
SCL1 I/O ST No Synchronous serial clock input/output for I2C1.
SDA1 I/O ST No Synchronous serial data input/output for I2C1.
ASCL1 I/O ST No Alternate synchronous serial clock input/output for I2C1.
ASDA1 I/O ST No Alternate synchronous serial data input/output for I2C1.
SCL2 I/O ST No Synchronous serial clock input/output for I2C2.
SDA2 I/O ST No Synchronous serial data input/output for I2C2.
ASCL2 I/O ST No Alternate synchronous serial clock input/output for I2C2.
ASDA2 I/O ST No Alternate synchronous serial data input/output for I2C2.
TMS I ST No JTAG Test mode select pin.
TCK I ST No JTAG test clock input pin.
TDI I ST No JTAG test data input pin.
TDO O — No JTAG test data output pin.
FLT1-FLT8 I ST Yes PWM Fault Inputs 1 through 8.
FLT9-FLT12 I ST No PWM Fault Inputs 9 through 12.
FLT31 I ST No PWM Fault Input 31 (Class B Fault).
PWM1L-PWM3L O — No PWM Low Outputs 1 through 3.
PWM1H-PWM3H O — No PWM High Outputs 1 through 3.
PWM4L-PWM5L(2) O — Yes PWM Low Outputs 4 and 5.
PWM4H-PWM5H(2) O — Yes PWM High Outputs 4 and 5.
SYNCI1, SYNCI2 I ST Yes PWM Synchronization Inputs 1 and 2.
SYNCO1, SYNCO2 O — Yes PWM Synchronization Outputs 1 and 2.
CMP1A-CMP4A I Analog No Comparator Channels 1 through 4 A input.
CMP1B-CMP4B I Analog No Comparator Channels 1 through 4 B input.
CMP1C-CMP4C I Analog No Comparator Channels 1 through 4 C input.
CMP1D-CMP4D I Analog No Comparator Channels 1 through 4 D input.
DACOUT1, DACOUT2 O — No DAC Output Voltages 1 and 2.
EXTREF1, EXTREF2 I Analog No External Voltage Reference Inputs 1 and 2 for the reference DACs.
ISRC1-ISRC4 O Analog No Constant-Current Outputs 1 through 4.
PGA1P1-PGA1P4 I Analog No PGA1 Positive Inputs 1 through 4.
PGA1N1-PGA1N3 I Analog No PGA1 Negative Inputs 1 through 3.
PGA2P1-PGA2P4 I Analog No PGA2 Positive Inputs 1 through 4.
PGA2N1-PGA2N3 I Analog No PGA2 Negative Inputs 1 through 3.
ADTRG31 I ST No External ADC trigger source.
PGED1 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 1.
PGEC1 I ST No Clock input pin for Programming/Debugging Communication Channel 1.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer
Type Type
MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD P P No Positive supply for analog modules. This pin must be connected at all
times.
AVSS P P No Ground reference for analog modules. This pin must be connected at
all times.
VDD P — No Positive supply for peripheral logic and I/O pins.
VCAP P — No CPU logic filter capacitor connection.
VSS P — No Ground reference for logic and I/O pins.

2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors
STARTED WITH 16-BIT DIGITAL The use of decoupling capacitors on every pair of
SIGNAL CONTROLLERS power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Note 1: This data sheet summarizes the features
Consider the following criteria when using decoupling
of the dsPIC33EPXXGS50X family of
capacitors:
devices. It is not intended to be a
comprehensive reference source. To • Value and type of capacitor: Recommendation
complement the information in this data of 0.1 µF (100 nF), 10-20V. This capacitor should
sheet, refer to the related section of be a low-ESR and have resonance frequency in
the “dsPIC33/PIC24 Family Reference the range of 20 MHz and higher. It is
Manual”, which is available from the recommended to use ceramic capacitors.
Microchip web site (www.microchip.com). • Placement on the printed circuit board: The
2: Some registers and associated bits decoupling capacitors should be placed as close
described in this section may not be to the pins as possible. It is recommended to
available on all devices. Refer to place the capacitors on the same side of the
Section 4.0 “Memory Organization” in board as the device. If space is constricted, the
this data sheet for device-specific register capacitor can be placed on another layer on the
and bit information. PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
2.1 Basic Connection Requirements
• Handling high-frequency noise: If the board is
Getting started with the dsPIC33EPXXGS50X family experiencing high-frequency noise, above tens of
requires attention to a minimal set of device pin MHz, add a second ceramic-type capacitor in
connections before proceeding with development. The parallel to the above described decoupling
following is a list of pin names which must always be capacitor. The value of the second capacitor can
connected: be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
• All VDD and VSS pins
capacitor. In high-speed circuit designs, consider
(see Section 2.2 “Decoupling Capacitors”)
implementing a decade pair of capacitances as
• All AVDD and AVSS pins close to the power and ground pins as possible.
regardless if ADC module is not used (see For example, 0.1 µF in parallel with 0.001 µF.
Section 2.2 “Decoupling Capacitors”)
• Maximizing performance: On the board layout
• VCAP from the power supply circuit, run the power and
(see Section 2.3 “CPU Logic Filter Capacitor return traces to the decoupling capacitors first,
Connection (VCAP)”) and then to the device pins. This ensures that the
• MCLR pin decoupling capacitors are first in the power chain.
(see Section 2.4 “Master Clear (MCLR) Pin”) Equally important is to keep the trace length
• PGECx/PGEDx pins between the capacitor and the power pins to a
used for In-Circuit Serial Programming™ (ICSP™) minimum, thereby reducing PCB track
and debugging purposes (see Section 2.5 “ICSP inductance.
Pins”)
• OSC1 and OSC2 pins
when external oscillator source is used (see
Section 2.6 “External Oscillator Pins”)

FIGURE 2-1: RECOMMENDED The placement of this capacitor should be close to the
MINIMUM CONNECTION VCAP pin. It is recommended that the trace length not
exceeds one-quarter inch (6 mm). See Section 23.4
“On-Chip Voltage Regulator” for details.
10 µF 0.1 µF
VDD Tantalum Ceramic
2.4 Master Clear (MCLR) Pin
VDD
VCAP
VSS
R
R1
The MCLR pin provides two specific device
MCLR functions:
• Device Reset
C
• Device Programming and Debugging.
dsPIC33EP
During device programming and debugging, the
VSS VDD
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
VDD VSS
0.1 µF 0.1 µF debuggers drive the MCLR pin. Consequently,
AVDD
AVSS
Ceramic
VDD
VSS
Ceramic specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
0.1 µF 0.1 µF specific values of R and C will need to be adjusted
Ceramic Ceramic
based on the application and PCB requirements.
L1(1)
For example, as shown in Figure 2-2, it is
Note 1: As an option, instead of a hard-wired connection, an recommended that the capacitor C, be isolated from
inductor (L1) can be substituted between VDD and the MCLR pin during programming and debugging
AVDD to improve ADC noise rejection. The inductor operations.
impedance should be less than 1 and the inductor
capacity greater than 10 mA. Place the components as shown in Figure 2-2 within
Where: one-quarter inch (6 mm) from the MCLR pin.
F CNV
f = -------------- (i.e., ADC Conversion Rate/2) FIGURE 2-2: EXAMPLE OF MCLR PIN
2
CONNECTIONS
1
f = -----------------------
 2 LC 
VDD
2
L =  ----------------------
1
  2f C  R(1)
R1(2)
MCLR
2.2.1 TANK CAPACITORS
JP
On boards with power traces running longer than six dsPIC33EP
inches in length, it is suggested to use a tank capacitor C
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
Note 1: R  10 k is recommended. A suggested
nects the power supply source to the device and the
starting value is 10 k. Ensure that the
maximum current drawn by the device in the applica- MCLR pin VIH and VIL specifications are met.
tion. In other words, select the tank capacitor so that it 2: R1  470 will limit any current flowing into
meets the acceptable voltage sag at the device. Typical MCLR from the external capacitor, C, in the
values range from 4.7 µF to 47 µF. event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
2.3 CPU Logic Filter Capacitor Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
Connection (VCAP)
A low-ESR (<0.5 Ω) capacitor is required on the VCAP
pin, which is used to stabilize the voltage regulator
output voltage. The VCAP pin must not be connected to
VDD and must have a capacitor greater than 4.7 µF
(10 µF is recommended), 16V connected to ground.
The type can be ceramic or tantalum. See
Section 26.0 “Electrical Characteristics” for
additional information.

2.5 ICSP Pins 2.6 External Oscillator Pins
The PGECx and PGEDx pins are used for ICSP and Many DSCs have options for at least two oscillators: a
debugging purposes. It is recommended to keep the high-frequency primary oscillator and a low-frequency
trace length between the ICSP connector and the ICSP secondary oscillator. For details, see Section 8.0
pins on the device as short as possible. If the ICSP con- “Oscillator Configuration” for details.
nector is expected to experience an ESD event, a The oscillator circuit should be placed on the same
series resistor is recommended, with the value in the side of the board as the device. Also, place the
range of a few tens of Ohms, not to exceed 100 Ohms. oscillator circuit close to the respective oscillator pins,
Pull-up resistors, series diodes and capacitors on the not exceeding one-half inch (12 mm) distance
PGECx and PGEDx pins are not recommended as they between them. The load capacitors should be placed
will interfere with the programmer/debugger communi- next to the oscillator itself, on the same side of the
cations to the device. If such discrete components are board. Use a grounded copper pour around the
an application requirement, they should be removed oscillator circuit to isolate them from surrounding
from the circuit during programming and debugging. circuits. The grounded copper pour should be routed
Alternatively, refer to the AC/DC characteristics and directly to the MCU ground. Do not run any signal
timing requirements information in the respective traces or power traces inside the ground pour. Also, if
device Flash programming specification for information using a two-sided board, avoid any traces on the
on capacitive loading limits and pin Voltage Input High other side of the board where the crystal is placed. A
(VIH) and Voltage Input Low (VIL) requirements. suggested layout is shown in Figure 2-3.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device FIGURE 2-3: SUGGESTED PLACEMENT
matches the physical connections for the ICSP OF THE OSCILLATOR
to MPLAB® PICkit™ 3, MPLAB ICD 3, or MPLAB CIRCUIT
REAL ICE™.
For more information on MPLAB ICD 2, MPLAB ICD 3 Main Oscillator
and REAL ICE connection requirements, refer to the
following documents that are available on the Guard Ring
Microchip web site.
• “Using MPLAB® ICD 3” (poster) DS51765 Guard Trace
• “Multi-Tool Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s Oscillator Pins
Guide” DS51616
• “Using MPLAB® REAL ICE™ In-Circuit Emulator”
(poster) DS51749

2.7 Oscillator Value Conditions on 2.9 Targeted Applications
Device Start-up • Power Factor Correction (PFC)
If the PLL of the target device is enabled and - Interleaved PFC
configured for the device start-up oscillator, the - Critical Conduction PFC
maximum oscillator source frequency must be limited - Bridgeless PFC
to 3 MHz < FIN < 5.5 MHz to comply with device PLL
• DC/DC Converters
start-up conditions. This means that if the external
oscillator frequency is outside this range, the - Buck, Boost, Forward, Flyback, Push-Pull
application must start-up in the FRC mode first. The - Half/Full-Bridge
default PLL settings after a POR with an oscillator - Phase-Shift Full-Bridge
frequency outside this range will violate the device - Resonant Converters
operating speed. • DC/AC
Once the device powers up, the application firmware - Half/Full-Bridge Inverter
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
- Resonant Inverter
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching Examples of typical application connections are shown
must be enabled in the device Configuration Word. in Figure 2-4 through Figure 2-6.
2.8 Unused I/Os

Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor between VSS
and unused pins and drive the output to logic low.
FIGURE 2-4: INTERLEAVED PFC
VOUT+
|VAC|
k1 k2
k4 VAC k3
VOUT-
FET FET
Driver Driver
PGA/ADC Channel PWM PGA/ADC PWM PGA/ADC ADC

Channel Channel Channel
dsPIC33EPXXGS50X
ADC Channel

FIGURE 2-5: PHASE-SHIFTED FULL-BRIDGE CONVERTER
VIN+
Gate 6
Gate 3
Gate 1
VOUT+
S1 S3
VOUT-
Gate 2
Gate 4 Gate 5
VIN-
Gate 5
Gate 6
FET k2
Driver
k1
Analog
Gate 1 Ground
FET PWM PGA/ADC PWM ADC

Driver Channel Channel
S1
Gate 3
FET dsPIC33EPXXGS50X
Driver
S3 PWM
Gate 2
Gate 4

FIGURE 2-6: OFF-LINE UPS
VDC
Push-Pull Converter Full-Bridge Inverter
VOUT+
VBAT +
VOUT-
GND
GND
FET FET FET FET FET FET

Driver Driver k2 k1 Driver Driver Driver Driver k4 k5
PWM PWM PGA/ADC ADC PWM PWM PWM PWM

or
Analog Comp.
k3 ADC
dsPIC33EPXXGS50X
ADC ADC
ADC PWM
FET
k6 Driver
Battery Charger

3.0 CPU 3.2 Instruction Set
The instruction set for dsPIC33EPXXGS50X devices
has two classes of instructions: the MCU class of
instructions and the DSP class of instructions. These
devices. It is not intended to be a compre-
two instruction classes are seamlessly integrated into the
hensive reference source. To complement
architecture and execute from a single execution unit.
the information in this data sheet, refer to
The instruction set includes many addressing modes and
“CPU” (DS70359) in the “dsPIC33/PIC24
was designed for optimum C compiler efficiency.
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com). 3.3 Data Space Addressing
2: Some registers and associated bits The base Data Space can be addressed as up to
described in this section may not be 4K words or 8 Kbytes, and is split into two blocks,
available on all devices. Refer to referred to as X and Y data memory. Each memory block
Section 4.0 “Memory Organization” in has its own independent Address Generation Unit
this data sheet for device-specific register (AGU). The MCU class of instructions operates solely
and bit information. through the X memory AGU, which accesses the entire
memory map as one linear Data Space. Certain DSP
The dsPIC33EPXXGS50X family CPU has a 16-bit instructions operate through the X and Y AGUs to sup-
(data) modified Harvard architecture with an enhanced port dual operand reads, which splits the data address
instruction set, including significant support for Digital space into two parts. The X and Y Data Space boundary
Signal Processing (DSP). The CPU has a 24-bit is device-specific.
instruction word with a variable length opcode field.
The Program Counter (PC) is 23 bits wide and The upper 32 Kbytes of the Data Space memory map
addresses up to 4M x 24 bits of user program memory can optionally be mapped into Program Space (PS) at
space. any 16K program word boundary. The program-to-Data
Space mapping feature, known as Program Space
An instruction prefetch mechanism helps maintain Visibility (PSV), lets any instruction access Program
throughput and provides predictable execution. Most Space as if it were Data Space. Refer to “Data
instructions execute in a single-cycle effective execu- Memory” (DS70595) in the “dsPIC33/PIC24 Family
tion rate, with the exception of instructions that change Reference Manual” for more details on PSV and table
the program flow, the double-word move (MOV.D) accesses.
instruction, PSV accesses and the table instructions.
Overhead-free program loop constructs are supported On dsPIC33EPXXGS50X devices, overhead-free
using the DO and REPEAT instructions, both of which circular buffers (Modulo Addressing) are supported in
are interruptible at any point. both X and Y address spaces. The Modulo Addressing
removes the software boundary checking overhead for
3.1 Registers DSP algorithms. The X AGU Circular Addressing can
be used with any of the MCU class of instructions. The
The dsPIC33EPXXGS50X devices have sixteen, 16-bit X AGU also supports Bit-Reversed Addressing to
Working registers in the programmer’s model. Each of the greatly simplify input or output data re-ordering for
Working registers can act as a data, address or address radix-2 FFT algorithms.
offset register. The 16th Working register (W15) operates
as a Software Stack Pointer for interrupts and calls. 3.4 Addressing Modes
In addition, the dsPIC33EPXXGS50X devices include
two Alternate Working register sets which consist of W0 The CPU supports these addressing modes:
through W14. The Alternate registers can be made per- • Inherent (no operand)
sistent to help reduce the saving and restoring of register • Relative
content during Interrupt Service Routines (ISRs). The • Literal
Alternate Working registers can be assigned to a specific
• Memory Direct
Interrupt Priority Level (IPL1 through IPL6) by configuring
the CTXTx<2:0> bits in the FALTREG Configuration • Register Direct
register. The Alternate Working registers can also be • Register Indirect
accessed manually by using the CTXTSWP instruction. Each instruction is associated with a predefined
The CCTXI<2:0> and MCTXI<2:0> bits in the CTXTSTAT addressing mode group, depending upon its functional
register can be used to identify the current and most requirements. As many as six addressing modes are
recent, manually selected Working register sets. supported for each instruction.

FIGURE 3-1: dsPIC33EPXXGS50X FAMILY CPU BLOCK DIAGRAM
X Address Bus
Y Data Bus
X Data Bus
16 16 16
16
Interrupt Data Latch Data Latch

PSV and Table
Controller Data Access Y Data X Data
8 16
24 Control Block RAM RAM
Address Address 16 24
24 Latch Latch
16 16
Y Address Bus
24
PCU PCH PCL X RAGU
Program Counter 16 X WAGU
Stack Loop
Control Control
Address Latch Logic Logic
Y AGU
Program Memory
16 EA MUX
Data Latch
16
ROM Latch
16 24
IR
24
Literal Data
16
16-Bit
Working Register Arrays 16
16 16
Divide
DSP Support
Engine
16-Bit ALU
Control Signals Instruction

Decode and 16 16
to Various Blocks
Control
Power, Reset Ports

and Oscillator
Modules
Peripheral
Modules

3.5 Programmer’s Model In addition to the registers contained in the programmer’s
model, the dsPIC33EPXXGS50X devices contain control
The programmer’s model for the dsPIC33EPXXGS50X registers for Modulo Addressing, Bit-Reversed
family is shown in Figure 3-2. All registers in the Addressing and interrupts. These registers are
programmer’s model are memory-mapped and can be described in subsequent sections of this document.
manipulated directly by instructions. Table 3-1 lists a
description of each register. All registers associated with the programmer’s model
are memory-mapped, as shown in Table 3-1.
TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

Register(s) Name Description
W0 through W15(1) Working Register Array
W0 through W14(1) Alternate 1 Working Register Array
W0 through W14(1) Alternate 2 Working Register Array
ACCA, ACCB 40-Bit DSP Accumulators
PC 23-Bit Program Counter
SR ALU and DSP Engine STATUS Register
SPLIM Stack Pointer Limit Value Register
TBLPAG Table Memory Page Address Register
DSRPAG Extended Data Space (EDS) Read Page Register
RCOUNT REPEAT Loop Counter Register
DCOUNT DO Loop Counter Register
DOSTARTH(2), DOSTARTL(2) DO Loop Start Address Register (High and Low)
DOENDH, DOENDL DO Loop End Address Register (High and Low)
CORCON Contains DSP Engine, DO Loop Control and Trap Status bits
Note 1: Memory-mapped W0 through W14 represent the value of the register in the currently active CPU context.
2: The DOSTARTH and DOSTARTL registers are read-only.

FIGURE 3-2: PROGRAMMER’S MODEL
D15 D0
D15 D0
D15 D0
W0 (WREG) W0 W0
W0-W3 W1 W1 W1
W2 W2 W2
W3 W3 W3
W4 W4 W4
DSP Operand W5 W5 W5 Alternate
Registers W6 Working/Address
W6 W6
W7 W7 W7 Registers
Working/Address
Registers W8 W8
W8
DSP Address W9 W9 W9
Registers
W10 W10 W10
W11 W11 W11
W12 W12 W12
W13 W13 W13
Frame Pointer/W14 W14 W14
Stack Pointer/W15 0
PUSH.s and POP.s Shadows

SPLIM 0 Stack Pointer Limit
Nested DO Stack
AD39 AD31 AD15 AD0
DSP ACCA
Accumulators(1) ACCB
PC23 PC0
0 0 Program Counter
7 0
TBLPAG Data Table Page Address
9 0
DSRPAG X Data Space Read Page Address
15 0
RCOUNT REPEAT Loop Counter
15 0
DCOUNT DO Loop Counter and Stack
23 0
0 DOSTART 0 DO Loop Start Address and Stack
23 0
0 DOEND 0 DO Loop End Address and Stack
15 0
CORCON CPU Core Control Register
SRL
OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register

3.6 CPU Resources 3.6.1 KEY RESOURCES
Many useful resources are provided on the main prod- • Code Samples
uct page of the Microchip web site for the devices listed • Application Notes
in this data sheet. This product page contains the latest • Software Libraries
updates and additional information. • Webinars
• All related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools

3.7 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0
OA OB SA(3) SB(3) OAB SAB DA DC
bit 15 bit 8
R/W-0(2) R/W-0(2) R/W-0(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0

(1) (1)
IPL2 IPL1 IPL0(1) RA N OV Z C
bit 7 bit 0
Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow Status bit

1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(3)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(3)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulators A or B are saturated or have been saturated at some time
0 = Neither Accumulator A or B are saturated
bit 9 DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8 DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
2: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.

REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop is in progress
0 = REPEAT loop is not in progress
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1 Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
IPL<3> = 1.
3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.

REGISTER 3-2: CORCON: CORE CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
VAR — US1 US0 EDT(1) DL2 DL1 DL0
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3(2) SFA RND IF
bit 7 bit 0

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 VAR: Variable Exception Processing Latency Control bit

1 = Variable exception processing is enabled
0 = Fixed exception processing is enabled
bit 14 Unimplemented: Read as ‘0’
bit 13-12 US<1:0>: DSP Multiply Unsigned/Signed Control bits
11 = Reserved
10 = DSP engine multiplies are mixed-sign
01 = DSP engine multiplies are unsigned
00 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit(1)
1 = Terminates executing DO loop at the end of current loop iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops are active
•
•
•
001 = 1 DO loop is active
000 = 0 DO loops are active
bit 7 SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
bit 6 SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data Space write saturation is enabled
0 = Data Space write saturation is disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: This bit is always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED)
bit 2 SFA: Stack Frame Active Status bit
1 = Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG
0 = Stack frame is not active; W14 and W15 address the base Data Space
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode is enabled for DSP multiply
0 = Fractional mode is enabled for DSP multiply
Note 1: This bit is always read as ‘0’.

REGISTER 3-3: CTXTSTAT: CPU W REGISTER CONTEXT STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — — CCTXI2 CCTXI1 CCTXI0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

— — — — — MCTXI2 MCTXI1 MCTXI0
bit 7 bit 0
Legend:
bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 CCTXI<2:0>: Current (W Register) Context Identifier bits
111 = Reserved
•
•
•
011 = Reserved
010 = Alternate Working Register Set 2 is currently in use
001 = Alternate Working Register Set 1 is currently in use
000 = Default register set is currently in use
bit 2-0 MCTXI<2:0>: Manual (W Register) Context Identifier bits
111 = Reserved
•
•
•
011 = Reserved
010 = Alternate Working Register Set 2 was most recently manually selected
001 = Alternate Working Register Set 1 was most recently manually selected
000 = Default register set was most recently manually selected

3.8 Arithmetic Logic Unit (ALU) 3.9 DSP Engine
The dsPIC33EPXXGS50X family ALU is 16 bits wide The DSP engine consists of a high-speed 17-bit x 17-bit
and is capable of addition, subtraction, bit shifts and logic multiplier, a 40-bit barrel shifter and a 40-bit adder/
operations. Unless otherwise mentioned, arithmetic subtracter (with two target accumulators, round and
operations are two’s complement in nature. Depending saturation logic).
on the operation, the ALU can affect the values of the The DSP engine can also perform inherent accumulator-
Carry (C), Zero (Z), Negative (N), Overflow (OV) and to-accumulator operations that require no additional
Digit Carry (DC) Status bits in the SR register. The C data. These instructions are, ADD, SUB and NEG.
and DC Status bits operate as Borrow and Digit Borrow
bits, respectively, for subtraction operations. The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
The ALU can perform 8-bit or 16-bit operations, below:
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W • Fractional or integer DSP multiply (IF)
register array or data memory, depending on the • Signed, unsigned or mixed-sign DSP multiply
addressing mode of the instruction. Likewise, output (USx)
data from the ALU can be written to the W register array • Conventional or convergent rounding (RND)
or a data memory location. • Automatic saturation on/off for ACCA (SATA)
Refer to the “16-bit MCU and DSC Programmer’s • Automatic saturation on/off for ACCB (SATB)
Reference Manual” (DS70157) for information on the • Automatic saturation on/off for writes to data
SR bits affected by each instruction. memory (SATDW)
The core CPU incorporates hardware support for both • Accumulator Saturation mode selection
multiplication and division. This includes a dedicated (ACCSAT)
hardware multiplier and support hardware for 16-bit
divisor division. TABLE 3-2: DSP INSTRUCTIONS
3.8.1 MULTIPLIER SUMMARY
Using the high-speed 17-bit x 17-bit multiplier, the ALU Algebraic ACC
Instruction
supports unsigned, signed, or mixed-sign operation in Operation Write-Back
several MCU multiplication modes: CLR A=0 Yes
• 16-bit x 16-bit signed ED A = (x – y)2 No
• 16-bit x 16-bit unsigned EDAC A = A + (x – y) 2
No
• 16-bit signed x 5-bit (literal) unsigned MAC A = A + (x • y) Yes
• 16-bit signed x 16-bit unsigned MAC A=A+ x2 No
• 16-bit unsigned x 5-bit (literal) unsigned
MOVSAC No change in A Yes
• 16-bit unsigned x 16-bit signed
MPY A=x•y No
• 8-bit unsigned x 8-bit unsigned
MPY A = x2 No
3.8.2 DIVIDER MPY.N A=–x•y No
The divide block supports 32-bit/16-bit and 16-bit/16-bit MSC A=A–x•y Yes
signed and unsigned integer divide operations with the
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both
the 16-bit divisor (Wn) and any W register (aligned)
pair (W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.

4.0 MEMORY ORGANIZATION 4.2 Unique Device Identifier (UDID)
Note: This data sheet summarizes the features All (16-bit devices) family devices are individually
of the dsPIC33EPXXGS50X family of encoded during final manufacturing with a Unique
devices. It is not intended to be a Device Identifier or UDID. This feature allows for
comprehensive reference source. To com- manufacturing traceability of Microchip Technology
plement the information in this data sheet, devices in applications where this is a requirement. It
refer to “dsPIC33E/PIC24E Program may also be used by the application manufacturer
Memory” (DS70000613) in the “dsPIC33/ for any number of things that may require unique
PIC24 Family Reference Manual”, which is identification, such as:
available from the Microchip web site • Tracking the device
(www.microchip.com). • Unique serial number
The dsPIC33EPXXGS50X family architecture features • Unique security key
separate program and data memory spaces, and The UDID comprises five 24-bit program words.
buses. This architecture also allows the direct access When taken together, these fields form a unique
of program memory from the Data Space (DS) during 120-bit identifier.
code execution.
The UDID is stored in five read-only locations,
located between 800F00h and 800F08h in the
4.1 Program Address Space device configuration space. Table 4-1 lists the
The program address memory space of the addresses of the identifier words and shows their
dsPIC33EPXXGS50X family devices is 4M contents.
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit PC during program TABLE 4-1: UDID ADDRESSES
execution, or from table operation or Data Space Name Address Bits 23:16 Bits 15:8 Bits 7:0
remapping, as described in Section 4.9 “Interfacing
Program and Data Memory Spaces”. UDID1 800F00 UDID Word 1
User application access to the program memory space UDID2 800F02 UDID Word 2
is restricted to the lower half of the address range UDID3 800F04 UDID Word 3
(0x000000 to 0x7FFFFF). The exception is the use of UDID4 800F06 UDID Word 4
TBLRD operations, which use TBLPAG<7> to permit
UDID5 800F08 UDID Word 5
access to calibration data and Device ID sections of the
configuration memory space.
The program memory maps for the dsPIC33EP16/
32GS50X and dsPIC33EP64GS50X devices not
operating in Dual Partition mode, are shown in
Figure 4-1 through Figure 4-3.
The dsPIC33EP64GS50X devices can operate in a
Dual Partition Flash Program Memory mode, where
the user program Flash memory is arranged as two
separate address spaces, one for each of the Flash
partitions. The Active Partition always starts at
address, 0x000000, and contains half of the avail-
able Flash memory (32K). The Inactive Partition
always starts at address, 0x400000, and implements
the remaining half of Flash memory. As shown in
Figure 4-4, the Active and Inactive Partitions are
identical and both contain unique copies of the Reset
vector, Interrupt Vector Tables (IVT and AIVT if
enabled) and the Flash Configuration Words.

FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EP16GS50X DEVICES
GOTO Instruction 0x000000

Reset Address 0x000002
0x000004
Interrupt Vector Table 0x0001FE
0x000200
User Memory Space

User Program
Flash Memory
(5312 instructions)
0x002B7E
0x002B80
Device Configuration
0x002BFE
0x002C00
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
Reserved
0x800EFE
0x800F00
Configuration Memory Space
UDID
0x800F08
0x800F0A
Reserved
0x800F7E
0x800F80
User OTP Memory
0x800FFC
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID
0xFF0002
0xFF0004
Reserved
0xFFFFFE
Note: Memory areas are not shown to scale.


0x000004
User Memory Space

0x000200
User Program
Flash Memory
(10,944 instructions)
0x00577E
0x005780
0x0057FE
0x005800
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
Reserved
0x800EFE
0x800F00
UDID
0x800F08
0x800F0A
Reserved
0x800F7E
0x800F80
User OTP Memory
0x800FFC
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID 0xFF0002
0xFF0004
Reserved
0xFFFFFE


0x000004
User Memory Space

0x000200
User Program
Flash Memory
(22,207 instructions) 0x00AF7E
0x00AF80
0x00AFFE
0x00B000
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
Reserved
0x800EFE
0x800F00
UDID
0x800F08
0x800F0A
Reserved
0x800F7E
0x800F80
User OTP Memory
0x800FFC
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID
0xFF0002
0xFF0004
Reserved
0xFFFFFE

FIGURE 4-4: PROGRAM MEMORY MAP FOR dsPIC33EP64GS50X DEVICES (DUAL PARTITION)
0x000000
GOTO Instruction
0x000002
Reset Address
0x000004
Interrupt Vector Table
0x0001FE
Active Program 0x000200
Flash Memory
(10,944 instructions) Active Partition
0x00577E
0x005780
0x0057FE
0x005800
User Memory Space
Unimplemented
(Read ‘0’s)
0x3FFFFE
0x400000
GOTO Instruction
0x400002
Reset Address
0x400004
Interrupt Vector Table
0x4001FE
0x400200 Inactive Partition
Inactive Program
Flash Memory
(10,944 instructions)
0x40577E
0x405780
0x4057FE
Unimplemented 0x405800
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
Reserved
0x800EFE
0x800F00
UDID
0x800F08
0x800F0A
Reserved
0x800F7E
0x800F80
User OTP Memory
0x800FFC
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID 0xFF0002
0xFF0004
Reserved
0xFFFFFE

4.2.1 PROGRAM MEMORY 4.2.2 INTERRUPT AND TRAP VECTORS
ORGANIZATION All dsPIC33EPXXGS50X family devices reserve the
The program memory space is organized in word- addresses between 0x000000 and 0x000200 for hard-
addressable blocks. Although it is treated as 24 bits coded program execution vectors. A hardware Reset
wide, it is more appropriate to think of each address of vector is provided to redirect code execution from the
the program memory as a lower and upper word, with default value of the PC on device Reset to the actual
the upper byte of the upper word being unimplemented. start of code. A GOTO instruction is programmed by the
The lower word always has an even address, while the user application at address, 0x000000, of Flash
upper word has an odd address (Figure 4-5). memory, with the actual address for the start of code at
address, 0x000002, of Flash memory.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented, or A more detailed discussion of the Interrupt Vector
decremented, by two, during code execution. This Tables (IVTs) is provided in Section 7.1 “Interrupt
arrangement provides compatibility with data memory Vector Table”.
space addressing and makes data in the program
memory space accessible.
FIGURE 4-5: PROGRAM MEMORY ORGANIZATION
msw most significant word least significant word PC Address

Address (lsw Address)
23 16 8 0
0x000001 00000000 0x000000
0x000003 00000000 0x000002
0x000005 00000000 0x000004
0x000007 00000000 0x000006
Program Memory
Instruction Width
‘Phantom’ Byte
(read as ‘0’)

4.3 Data Address Space All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
The dsPIC33EPXXGS50X family CPU has a separate care must be taken when mixing byte and word
16-bit wide data memory space. The Data Space is operations, or translating from 8-bit MCU code. If a
accessed using separate Address Generation Units misaligned read or write is attempted, an address error
(AGUs) for read and write operations. The data trap is generated. If the error occurred on a read, the
memory maps are shown in Figure 4-6 through instruction underway is completed. If the error occurred
Figure 4-8. on a write, the instruction is executed but the write does
All Effective Addresses (EAs) in the data memory space not occur. In either case, a trap is then executed,
are 16 bits wide and point to bytes within the Data allowing the system and/or user application to examine
Space. This arrangement gives a base Data Space the machine state prior to execution of the address
address range of 64 Kbytes or 32K words. Fault.
The lower half of the data memory space (i.e., when All byte loads into any W register are loaded into the
EA<15> = 0) is used for implemented memory LSB; the MSB is not modified.
addresses, while the upper half (EA<15> = 1) is A Sign-Extend (SE) instruction is provided to allow user
reserved for the Program Space Visibility (PSV). applications to translate 8-bit signed data to 16-bit
dsPIC33EPXXGS50X family devices implement up to signed values. Alternatively, for 16-bit unsigned data,
12 Kbytes of data memory. If an EA points to a location user applications can clear the MSB of any W register
outside of this area, an all-zero word or byte is returned. by executing a Zero-Extend (ZE) instruction on the
appropriate address.
4.3.1 DATA SPACE WIDTH
4.3.3 SFR SPACE
The data memory space is organized in byte-
addressable, 16-bit wide blocks. Data is aligned in data The first 4 Kbytes of the Near Data Space, from 0x0000
memory and registers as 16-bit words, but all Data to 0x0FFF, is primarily occupied by Special Function
Space EAs resolve to bytes. The Least Significant Registers (SFRs). These are used by the
Bytes (LSBs) of each word have even addresses, while dsPIC33EPXXGS50X family core and peripheral
the Most Significant Bytes (MSBs) have odd modules for controlling the operation of the device.
addresses. SFRs are distributed among the modules that they
control, and are generally grouped together by module.
4.3.2 DATA MEMORY ORGANIZATION Much of the SFR space contains unused addresses;
AND ALIGNMENT these are read as ‘0’.
To maintain backward compatibility with PIC ® MCU
Note: The actual set of peripheral features and
devices and improve Data Space memory usage
interrupts varies by the device. Refer to
efficiency, the dsPIC33EPXXGS50X family instruc-
the corresponding device tables and
tion set supports both word and byte operations. As a
pinout diagrams for device-specific
consequence of byte accessibility, all Effective Address
information.
calculations are internally scaled to step through word-
aligned memory. For example, the core recognizes that
4.3.4 NEAR DATA SPACE
Post-Modified Register Indirect Addressing mode
[Ws++] results in a value of Ws + 1 for byte operations The 8-Kbyte area, between 0x0000 and 0x1FFF, is
and Ws + 2 for word operations. referred to as the Near Data Space. Locations in this
space are directly addressable through a 13-bit absolute
A data byte read, reads the complete word that
address field within all memory direct instructions. Addi-
contains the byte, using the LSb of any EA to determine
tionally, the whole Data Space is addressable using MOV
which byte to select. The selected byte is placed onto
instructions, which support Memory Direct Addressing
the LSB of the data path. That is, data memory and
mode with a 16-bit address field, or by using Indirect
registers are organized as two parallel, byte-wide
Addressing mode using a Working register as an
entities with shared (word) address decode, but
Address Pointer.
separate write lines. Data byte writes only write to the
corresponding side of the array or register that matches
the byte address.

FIGURE 4-6: DATA MEMORY MAP FOR dsPIC33EP16GS50X DEVICES
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE
0x0FFF
0x1001 0x1000
X Data RAM (X)
8-Kbyte
2-Kbyte 0x13FF 0x13FE Near
SRAM Space 0x1401 0x1400 Data Space
Y Data RAM (Y)
0x17FF 0x17FE
0x1801 0x1800
0x1FFF 0x1FFE
0x2001 0x2000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF 0xFFFE

MSB LSB
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE
0x0FFF
0x1001 0x1000
X Data RAM (X)

8-Kbyte
Near
4-Kbyte 0x17FF 0x17FE Data Space
SRAM Space 0x1801 0x1800
Y Data RAM (Y)
0x1FFF 0x1FFE
0x2001 0x2000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF 0xFFFE

MSB LSB
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE
0x0FFF
0x1001 0x1000
8-Kbyte
Near
X Data RAM (X) Data Space
8-Kbyte 0x1FFF 0x1FFE

SRAM Space 0x2001 0x2000
Y Data RAM (Y)
0x2FFF 0x2FFE
0x3001 0x3000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF 0xFFFE

4.3.5 X AND Y DATA SPACES 4.4 Memory Resources
The dsPIC33EPXXGS50X core has two Data Spaces, X Many useful resources are provided on the main
and Y. These Data Spaces can be considered either product page of the Microchip web site for the devices
separate (for some DSP instructions) or as one unified listed in this data sheet. This product page contains the
linear address range (for MCU instructions). The Data latest updates and additional information.
Spaces are accessed using two Address Generation
Units (AGUs) and separate data paths. This feature 4.4.1 KEY RESOURCES
allows certain instructions to concurrently fetch two
• Code Samples
words from RAM, thereby enabling efficient execution of
DSP algorithms, such as Finite Impulse Response (FIR) • Application Notes
filtering and Fast Fourier Transform (FFT). • Software Libraries
The X Data Space is used by all instructions and • Webinars
supports all addressing modes. X Data Space has • All Related “dsPIC33/PIC24 Family Reference
separate read and write data buses. The X read data Manual” Sections
bus is the read data path for all instructions that view • Development Tools
Data Space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y Data Space is used in concert with the X Data
Space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide
two concurrent data read paths.
Both the X and Y Data Spaces support Modulo Address-
ing mode for all instructions, subject to addressing mode
restrictions. Bit-Reversed Addressing mode is only
supported for writes to X Data Space.
All data memory writes, including in DSP instructions,
view Data Space as combined X and Y address space.
The boundary between the X and Y Data Spaces is
device-dependent and is not user-programmable.

4.5 Special Function Register Maps
DS70005127D-page 42
TABLE 4-2: CPU CORE REGISTER MAP
SFR All
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
W0 0000 W0 (WREG) xxxx

W1 0002 W1 xxxx
W2 0004 W2 xxxx
W3 0006 W3 xxxx
W4 0008 W4 xxxx
W5 000A W5 xxxx
W6 000C W6 xxxx
W7 000E W7 xxxx
W8 0010 W8 xxxx
W9 0012 W9 xxxx
W10 0014 W10 xxxx
W11 0016 W11 xxxx
W12 0018 W12 xxxx
W13 001A W13 xxxx
W14 001C W14 xxxx
W15 001E W15 xxxx
SPLIM 0020 SPLIM 0000
ACCAL 0022 ACCAL 0000
ACCAH 0024 ACCAH 0000
ACCAU 0026 Sign Extension of ACCA<39> ACCAU 0000
ACCBL 0028 ACCBL 0000
ACCBH 002A ACCBH 0000
ACCBU 002C Sign Extension of ACCB<39> ACCBU 0000
 2013-2017 Microchip Technology Inc.
PCL 002E PCL<15:1> — 0000

PCH 0030 — — — — — — — — — PCH<6:0> 0000
DSRPAG 0032 — — — — — — Extended Data Space (EDS) Read Page Register (DSRPAG<9:0>) 0001
DSWPAG(1) 0034 — — — — — — — Extended Data Space (EDS) Write Page Register (DSWPAG8:0>)(1) 0001
RCOUNT 0036 RCOUNT<15:0> 0000
DCOUNT 0038 DO Loop Count Register (DCOUNT<15:0>) 0000
DOSTARTL 003A DO Start Address Register Low (DOSTARTL<15:1>) — 0000
DOSTARTH 003C — — — — — — — — — — DO Start Address Register High (DOSTARTH<5:0>) 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: The contents of this register should never be modified. The DSWPAG must always point to the first page.
TABLE 4-2: CPU CORE REGISTER MAP (CONTINUED)

SFR All
Name Resets
DOENDL 003E DO Loop End Address Register Low (DOENDL<15:1>) — 0000

DOENDH 0040 — — — — — — — — — — DO Loop End Address Register High (DOENDH<5:0>) 0000
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 VAR — US1 US0 EDT DL2 DL1 DL0 SATA SATB SATDW ACCSAT IPL3 SFA RND IF 0020
MODCON 0046 XMODEN YMODEN — — BWM3 BWM2 BWM1 BWM0 YWM3 YWM2 YWM1 YWM0 XWM3 XWM2 XWM1 XWM0 0000
XMODSRT 0048 X Mode Start Address Register (XMODSRT<15:1>) — 0000
XMODEND 004A X Mode End Address Register (XMODEND<15:1>) — 0001
YMODSRT 004C Y Mode Start Address Register (YMODSRT<15:1>) — 0000
YMODEND 004E Y Mode End Address Register (YMODEND<15:1>) — 0001
XBREV 0050 BREN XBREV<14:0> 0000
DISICNT 0052 — — DISICNT<13:0> 0000
TBLPAG 0054 — — — — — — — — TBLPAG<7:0> 0000
CTXTSTAT 005A — — — — — CCTXI2 CCTXI1 CCTXI0 — — — — — MCTXI2 MCTXI1 MCTXI0 0000
Note 1: The contents of this register should never be modified. The DSWPAG must always point to the first page.
DS70005127D-page 43
DS70005127D-page 44
TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP
SFR All
Name Resets
IFS0 0800 NVMIF — ADCIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000
IFS1 0802 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF — — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF 0000
IFS2 0804 — — — — — — — — — IC4IF IC3IF — — — SPI2IF SPI2EIF 0000
IFS3 0806 — — — — — — PSEMIF — — INT4IF — — — MI2C2IF SI2C2IF — 0000
IFS4 0808 — — — — — — PSESIF — — — — — — U2EIF U1EIF — 0000
IFS5 080A PWM2IF PWM1IF — — — — — — — — — — — — — 0000
IFS6 080C ADCAN1IF ADCAN0IF — — — — AC4IF AC3IF AC2IF — — — — PWM5IF PWM4IF PWM3IF 0000
IFS7 080E — — — — — — — — — — ADCAN7IF ADCAN6IF ADCAN5IF ADCAN4IF ADCAN3IF ADCAN2IF 0000
IFS8 0810 JTAGIF ICDIF — — — — — — — — — — — — — — 0000
IFS9 0812 ADCAN16IF(1) ADCAN15IF(1) ADCAN14IF(2) ADCAN13IF(1) ADCAN12IF(2) ADCAN11IF(2) ADCAN10IF(2) ADCAN9IF(2) ADCAN8IF(2) — — — — — — — 0000
IFS10 0814 — I2C2BCIF I2C1BCIF — — — — — — — — ADCAN21IF ADCAN20IF ADCAN19IF ADCAN18IF ADCAN17IF(2) 0000
IFS11 0816 — — — — — — — — — — — ADFLTR1IF ADFLTR0IF ADCMP1IF ADCMP0IF — 0000
IEC0 0820 NVMIE — ADCIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000
IEC1 0822 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE — — — — INT1IE CNIE AC1IF MI2C1IE SI2C1IE 0000
IEC2 0824 — — — — — — — — — IC4IE IC3IE — — — SPI2IE SPI2EIE 0000
IEC3 0826 — — — — — — PSEMIE — — INT4IE — — — MI2C2IE SI2C2IE — 0000
IEC4 0828 — — — — — — PSESIE — — — — — — U2EIE U1EIE — 0000
IEC5 082A PWM2IE PWM1IE — — — — — — — — — — — — — — 0000
IEC6 082C ADCAN1IE ADCAN0IE — — — — AC4IE AC3IE AC2IE — — — — PWM5IE PWM4IE PWM3IE 0000
IEC7 082E — — — — — — — — — — ADCAN7IE ADCAN6IE ADCAN5IE ADCAN4IE ADCAN3IE ADCAN2IE 0000
IEC8 0830 JTAGIE ICDIE — — — — — — — — — — — — — — 0000
IEC9 0832 ADCAN16IE(1) ADCAN15IE(1) ADCAN14IE(2) ADCAN13IE(1) ADCAN12IE(2) ADCAN11IE(2) ADCAN10IE(2) ADCAN9IE(2) ADCAN8IE(2) — — — — — — — 0000
IEC10 0834 — I2C2BCIE I2C1BCIE — — — — — — — — ADCAN21IE ADCAN20IE ADCAN19IE ADCAN18IE ADCAN17IE(2) 0000
IEC11 0836 — — — — — — — — — — — ADFLTR1IE ADFLTR0IE ADCMP1IE ADCMP0IE — 0000
IPC0 0840 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444
IPC1 0842 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — — — — 4440
IPC2 0844 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — SPI1EIP2 SPI1EIP1 SPI1EIP0 — T3IP2 T3IP1 T3IP0 4444
IPC3 0846 — NVMIP2 NVMIP1 NVMIP0 — — — — — ADCIP2 ADCIP1 ADCIP0 — U1TXIP2 U1TXIP1 U1TXIP0 4044
IPC4 0848 — CNIP2 CNIP1 CNIP0 — AC1IP2 AC1IP1 AC1IP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444
IPC5 084A — — — — — — — — — — — — — INT1IP2 INT1IP1 INT1IP0 0004
IPC6 084C — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — — — — 4440
IPC7 084E — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444
IPC8 0850 — — — — — — — — — SPI2IP2 SPI2IP1 SPI2IP0 — SPI2EIP2 SPI2EIP1 SPI2EIP0 0044
IPC9 0852 — — — — — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — — — — 0440
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Only available on dsPIC33EPXXGS506 devices.
2: Only available on dsPIC33EPXXGS504/505 and dsPIC33EPXXGS506 devices.
TABLE 4-3: INTERRUPT CONTROLLER REGISTER MAP (CONTINUED)

SFR All
Name Resets
IPC12 0858 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440

IPC13 085A — — — — — INT4IP2 INT4IP1 INT4IP0 — — — — — — — — 0400
IPC14 085C — — — — — — — — — PSEMIP2 PSEMIP1 PSEMIP0 — — — — 0040
IPC16 0860 — — — — — U2EIP2 U2EIP1 U2EIP0 — U1EIP2 U1EIP1 U1EIP0 — — — — 0440
IPC18 0864 — — — — — — — — — PSESIP2 PSESIP1 PSESIP0 — — — — 0040
IPC23 086E — PWM2IP2 PWM2IP1 PWM2IP0 — PWM1IP2 PWM1IP1 PWM1IP0 — — — — — — — — 4400
IPC24 0870 — — — — — PWM5IP2 PWM5IP1 PWM5IP0 — PWM4IP2 PWM4IP1 PWM4IP0 — PWM3IP2 PWM3IP1 PWM3IP0 0444
IPC25 0872 — AC2IP2 AC2IP1 AC2IP0 — — — — — — — — — — — — 4000
IPC26 0874 — — — — — — — — — AC4IP2 AC4IP1 AC4IP0 — AC3IP2 AC3IP1 AC3IP0 0044
IPC27 0876 — ADCAN1IP2 ADCAN1IP1 ADCAN1IP0 — ADCAN0IP2 ADCAN0IP1 ADCAN0IP0 — — — — — — — — 4400
IPC28 0878 — ADCAN5IP2 ADCAN5IP1 ADCAN5IP0 — ADCAN4IP2 ADCAN4IP1 ADCAN4IP0 — ADCAN3IP2 ADCAN3IP1 ADCAN3IP0 — ADCAN2IP2 ADCAN2IP1 ADCAN2IP0 4444
IPC29 087A — — — — — — — — — ADCAN7IP2 ADCAN7IP1 ADCAN7IP0 — ADCAN6IP2 ADCAN6IP1 ADCAN6IP0 0044
IPC35 0886 — JTAGIP2 JTAGIP1 JTAGIP0 — ICDIP2 ICDIP1 ICDIP0 — — — — — — — — 4400
IPC37 088A — ADCAN8IP2(2) ADCAN8IP1(2) ADCAN8IP0(2) — — — — — — — — — — — — 4000
IPC38 088C — ADCAN12IP2(2) ADCAN12IP1(2) ADCAN12IP0(2) — ADCAN11IP2(2) ADCAN11IP1(2) ADCAN11IP0(2) — ADCAN10IP2(2) ADCAN10IP1(2) ADCAN10IP0(2) — ADCAN9IP2(2) ADCAN9IP1(2) ADCAN9IP0(2) 4444
IPC39 088E — ADCAN16IP2(1) ADCAN16IP1(1) ADCAN16IP0(1) — ADCAN15IP2(1) ADCAN15IP1(1) ADCAN15IP0(1) — ADCAN14IP2(2) ADCAN14IP1(2) ADCAN14IP0(2) — ADCAN13IP2(1) ADCAN13IP1 ADCAN13IP0 4444
IPC40 0890 — ADCAN20IP2 ADCAN20IP1 ADCAN20IP0 — ADCAN19IP2 ADCAN19IP1 ADCAN19IP0 — ADCAN18IP2 ADCAN18IP1 ADCAN18IP0 — ADCAN17IP2(2) ADCAN17IP1(2) ADCAN17IP0(2) 4444
IPC41 0892 — — — — — — — — — — — — — ADCAN21IP2 ADCAN21IP1 ADCAN21IP0 0004
IPC43 0896 — — — — — I2C2BCIP2 I2C2BCIP1 I2C2BCIP0 — I2C1BCIP2 I2C1BCIP1 I2C1BCIP0 — — — — 0440
IPC44 0898 — ADFLTR0IP2 ADFLTR0IP1 ADFLTR0IP0 — ADCMP1IP2 ADCMP1IP1 ADCMP1IP0 — ADCMP0IP2 ADCMP0IP1 ADCMP0IP0 — — — — 4440
IPC45 089A — — — — — — — — — — — — — ADFLTR1IP2 ADFLTR1IP1 ADFLTR1IP0 0004
INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — 0000
INTCON2 08C2 GIE DISI SWTRAP — — — — AIVTEN — — — INT4EP — INT2EP INT1EP INT0EP 8000
INTCON3 08C4 — — — — — — — NAE — — — DOOVR — — — APLL 0000
INTCON4 08C6 — — — — — — — — — — — — — — — SGHT 0000
INTTREG 08C8 — — — — ILR3 ILR2 ILR1 ILR0 VECNUM7 VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000
Note 1: Only available on dsPIC33EPXXGS506 devices.
2: Only available on dsPIC33EPXXGS504/505 and dsPIC33EPXXGS506 devices.
DS70005127D-page 45
DS70005127D-page 46
TABLE 4-4: TIMER1 THROUGH TIMER5 REGISTER MAP
SFR All
Name Resets
TMR1 0100 Timer1 Register xxxx

PR1 0102 Period Register 1 FFFF
T1CON 0104 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only) xxxx
TMR3 010A Timer3 Register xxxx
PR2 010C Period Register 2 FFFF
PR3 010E Period Register 3 FFFF
T2CON 0110 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000
T3CON 0112 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000
TMR5HLD 0116 Timer5 Holding Register (for 32-bit operations only) xxxx
PR4 011A Period Register 4 FFFF
PR5 011C Period Register 5 FFFF
T4CON 011E TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000
T5CON 0120 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — — TCS — 0000
TABLE 4-5: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 4 REGISTER MAP

SFR All
Name Resets
IC1CON1 0140 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000
IC1CON2 0142 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC1BUF 0144 Input Capture 1 Buffer Register xxxx
IC1TMR 0146 Input Capture 1 Timer Register 0000
IC2CON2 014A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC2BUF 014C Input Capture 2 Buffer Register xxxx
IC2TMR 014E Input Capture 2 Timer Register 0000
IC3CON2 0152 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC3BUF 0154 Input Capture 3 Buffer Register xxxx
IC3TMR 0156 Input Capture 3 Timer Register 0000
IC4CON2 015A — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D
IC4BUF 015C Input Capture 4 Buffer Register xxxx
IC4TMR 015E Input Capture 4 Timer Register 0000
DS70005127D-page 47
DS70005127D-page 48
TABLE 4-6: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 4 REGISTER MAP
SFR All
Name Resets
OC1CON1 0900 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0 0000
OC1CON2 0902 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC1RS 0904 Output Compare 1 Secondary Register xxxx
OC1R 0906 Output Compare 1 Register xxxx
OC1TMR 0908 Timer Value 1 Register xxxx
OC2CON1 090A — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0 0000
OC2CON2 090C FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C
OC2RS 090E Output Compare 2 Secondary Register xxxx
OC3CON1 0914 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0 0000
OC3R 091A Output Compare 3 Register xxxx
OC3TMR 091C Timer Value 3 Register xxxx
OC4CON1 091E — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0 0000
TABLE 4-7: PWM REGISTER MAP

SFR All
Name Resets
PTCON 0C00 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0 0000
PTCON2 0C02 — — — — — — — — — — — — — PCLKDIV<2:0> 0000
PTPER 0C04 PWMx Primary Master Time Base Period Register (PTPER<15:0>) FFF8
SEVTCMP 0C06 PWMx Special Event Compare Register (SEVTCMP12:0>) — — — 0000
MDC 0C0A PWMx Master Duty Cycle Register (MDC<15:0>) 0000
STCON 0C0E — — — SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0 0000
STCON2 0C10 — — — — — — — — — — — — — PCLKDIV<2:0> 0000
STPER 0C12 PWMx Secondary Master Time Base Period Register (STPER<15:0>) FFF8
SSEVTCMP 0C14 PWMx Secondary Special Event Compare Register (SSEVTCMP<12:0>) — — — 0000
CHOP 0C1A CHPCLKEN — — — — — CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0 — — — 0000
PWMKEY 0C1E PWMx Protection Lock/Unlock Key Register (PWMKEY<15:0>) 0000
TABLE 4-8: PWM GENERATOR 1 REGISTER MAP

SFR All
Name Resets
PWMCON1 0C20 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 — — MTBS CAM XPRES IUE 0000
IOCON1 0C22 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC C000
FCLCON1 0C24 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 00F8
PDC1 0C26 PWM1 Generator Duty Cycle Register (PDC1<15:0>) 0000
PHASE1 0C28 PWM1 Primary Phase-Shift or Independent Time Base Period Register (PHASE1<15:0>) 0000
DTR1 0C2A — — PWM1 Dead-Time Register (DTR1<13:0>) 0000
ALTDTR1 0C2C — — PWM1 Alternate Dead-Time Register (ALTDTR1<13:0>) 0000
SDC1 0C2E PWM1 Secondary Duty Cycle Register (SDC1<15:0>) 0000
SPHASE1 0C30 PWM1 Secondary Phase-Shift Register (SPHASE1<15:0>) 0000
TRIG1 0C32 PWM1 Primary Trigger Compare Value Register (TRGCMP<12:0>) — — — 0000
TRGCON1 0C34 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
STRIG1 0C36 PWM1 Secondary Trigger Compare Value Register (STRGCMP<12:0>) — — — 0000
DS70005127D-page 49
PWMCAP1 0C38 PWM1 Primary Time Base Capture Register (PWMCAP<12:0>) — — — 0000
LEBCON1 0C3A PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000
LEBDLY1 0C3C — — — — PWM1 Leading-Edge Blanking Delay Register (LEB<8:0>) — — — 0000
AUXCON1 0C3E HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000
DS70005127D-page 50
SFR All
Name Resets

SFR All
Name Resets


SFR All
Name Resets

SFR All
Name Resets
PWMCON5 0CA0 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN ITB MDCS DTC1 DTC0 — — MTBS CAM XPRES IUE 0000
IOCON5 0CA2 PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC C000
FCLCON5 0CA4 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL CLMOD FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL FLTMOD1 FLTMOD0 00F8
PDC5 0CA6 PWM5 Generator Duty Cycle Register (PDC5<15:0>) 0000
PHASE5 0CA8 PWM5 Primary Phase-Shift or Independent Time Base Period Register (PHASE5<15:0>) 0000
DTR5 0CAA — — PWM5 Dead-Time Register (DTR5<13:0>) 0000
ALTDTR5 0CAC — — PWM5 Alternate Dead-Time Register (ALTDTR5<13:0>) 0000
SDC5 0CAE PWM5 Secondary Duty Cycle Register (SDC5<15:0>) 0000
SPHASE5 0CB0 PWM5 Secondary Phase-Shift Register (SPHASE5<15:0>) 0000
TRIG5 0CB2 PWM5 Primary Trigger Compare Value Register (TRGCMP<12:0>) — — — 0000
DS70005127D-page 51
TRGCON5 0CB4 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — DTM — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0 0000
STRIG5 0CB6 PWM5 Secondary Trigger Compare Value Register (STRGCMP<12:0>) — — — 0000
PWMCAP5 0CB8 PWM5 Primary Time Base Capture Register (PWMCAP<12:0>) — — — 0000
LEBCON5 0CBA PHR PHF PLR PLF FLTLEBEN CLLEBEN — — — — BCH BCL BPHH BPHL BPLH BPLL 0000
LEBDLY5 0CBC — — — — PWM5 Leading-Edge Blanking Delay Register (LEB<8:0>) — — — 0000
AUXCON5 0CBE HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 — — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN 0000
DS70005127D-page 52
TABLE 4-13: I2C1 AND I2C2 REGISTER MAP
SFR All
Name Resets
I2C1CONL 0200 I2CEN — I2CSIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C1CONH 0202 — — — — — — — — — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000
I2C1STAT 0204 ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000
I2C1ADD 0206 — — — — — — I2C1 Address Register 0000
I2C1MSK 0208 — — — — — — I2C1 Slave Mode Address Mask Register 0000
I2C1BRG 020A Baud Rate Generator Register 0000
I2C1TRN 020C — — — — — — — — I2C1 Transmit Register 00FF
I2C1RCV 020E — — — — — — — — I2C1 Receive Register 0000
I2C2CON1 0210 I2CEN — I2CSIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
I2C2CON2 0212 — — — — — — — — — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000
I2C2STAT 0214 ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF 0000
I2C2ADD 0216 — — — — — — I2C2 Address Register 0000
I2C2MSK 0218 — — — — — — I2C2 Slave Mode Address Mask Register 0000
I2C2BRG 021A Baud Rate Generator Register 0000
I2C2TRN 021C — — — — — — — — I2C2 Transmit Register 00FF
I2C2RCV 021E — — — — — — — — I2C2 Receive Register 0000
TABLE 4-14: UART1 AND UART2 REGISTER MAP

SFR All
Name Resets
U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U1TXREG 0224 — — — — — — — UART1 Transmit Register xxxx

U1RXREG 0226 — — — — — — — UART1 Receive Register 0000
U1BRG 0228 Baud Rate Generator Prescaler Register 0000
U2MODE 0230 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000
U2STA 0232 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110
U2TXREG 0234 — — — — — — — UART2 Transmit Register xxxx
U2RXREG 0236 — — — — — — — UART2 Receive Register 0000
U2BRG 0238 Baud Rate Generator Prescaler Register 0000
TABLE 4-15: SPI1 AND SPI2 REGISTER MAP

SFR All
Name Resets
SPI1STAT 0240 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000
SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000
SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000
SPI2STAT 0260 SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000
SPI2CON1 0262 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000
SPI2CON2 0264 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY SPIBEN 0000
SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register 0000
DS70005127D-page 53
DS70005127D-page 54
TABLE 4-16: ADC REGISTER MAP
SFR All
Name Resets
ADCON1L 0300 ADON — ADSIDL — — — — — — — — — — — — — 0000

ADCON1H 0302 — — — — — — — — FORM SHRRES1 SHRRES0 — — — — — 0060
ADCON2L 0304 REFCIE REFERCIE — EIEN — SHREISEL2 SHREISEL1 SHREISEL0 — SHRADCS6 SHRADCS5 SHRADCS4 SHRADCS3 SHRADCS2 SHRADCS1 SHRADCS0 0000
ADCON2H 0306 REFRDY REFERR — — — — SHRSAMC9 SHRSAMC8 SHRSAMC7 SHRSAMC6 SHRSAMC5 SHRSAMC4 SHRSAMC3 SHRSAMC2 SHRSAMC1 SHRSAMC0 0000
ADCON3L 0308 REFSEL2 REFSEL1 REFSEL0 SUSPEND SUSPCIE SUSPRDY SHRSAMP CNVRTCH SWLCTRG SWCTRG CNVCHSEL5 CNVCHSEL4 CNVCHSEL3 CNVCHSEL2 CNVCHSEL1 CNVCHSEL0 0000
ADCON3H 030A CLKSEL1 CLKSEL0 CLKDIV5 CLKDIV4 CLKDIV3 CLKDIV2 CLKDIV1 CLKDIV0 SHREN — — — C3EN C2EN C1EN C0EN 0000
ADCON4L 030C — — — — SYNCTRG3 SYNCTRG2 SYNCTRG1 SYNCTRG0 — — — — SAMC3EN SAMC2EN SAMC1EN SAMC0EN 0000
ADCON4H 030E — — — — — — — — C3CHS1 C3CHS0 C2CHS1 C2CHS0 C1CHS1 C1CHS0 C0CHS1 C0CHS0 0000
ADMOD0L 0310 DIFF7 SIGN7 DIFF6 SIGN6 DIFF5 SIGN5 DIFF3 SIGN4 DIFF3 SIGN3 DIFF2 SIGN2 DIFF1 SIGN1 DIFF0 SIGN0 0000
ADMOD0H 0312 DIFF15(1) SIGN15(1) DIFF14(2) SIGN14(2) DIFF13(1) SIGN13(1) DIFF12(2) SIGN12(2) DIFF11(2) SIGN11(2) DIFF10(2) SIGN10(2) DIFF9(2) SIGN9(2) DIFF8(2) SIGN8(2) 0000
ADMOD1L 0314 — — — — DIFF21 SIGN21 DIFF20 SIGN20 DIFF19 SIGN19 DIFF18 SIGN18 DIFF17(2) SIGN17(2) DIFF16(1) SIGN16(1) 0000
ADIEL 0320 IE15(1) IE14(2) IE13(1) IE12(2) IE11(2) IE10(2) IE9(2) IE8(2) IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 0000
ADIEH 0322 — — — — — — — — — — IE21 IE20 IE19 IE18 IE17(2) IE16(1) 0000
ADSTATL 0330 AN15RDY(1) AN14RDY(2) AN13RDY(1) AN12RDY(2) AN11RDY(2) AN10RDY(2) AN9RDY(2) AN8RDY(2) AN7RDY AN6RDY AN5RDY AN4RDY AN3RDY AN2RDY AN1RDY AN0RDY 0000
ADSTATH 0332 — — — — — — — — — — AN21RDY AN20RDY AN19RDY AN18RDY AN17RDY(2) AN16RDY(1) 0000
ADCMP0ENL 0338 CMPEN15(1) CMPEN14(2) CMPEN13(1) CMPEN12(2) CMPEN11(2) CMPEN10(2) CMPEN9(2) CMPEN8(2) CMPEN7 CMPEN6 CMPEN5 CMPEN4 CMPEN3 CMPEN2 CMPEN1 CMPEN0 0000
ADCMP0ENH 033A — — — — — — — — — — CMPEN21 CMPEN20 CMPEN19 CMPEN18 CMPEN17(2) CMPEN16(1) 0000
ADCMP0LO 033C ADC Comparator 0 Low Value Register 0000
ADCMP0HI 033E ADC Comparator 0 High Value Register 0000
ADCMP1ENL 0340 CMPEN15(1) CMPEN14(2) CMPEN13(1) CMPEN12(2) CMPEN11(2) CMPEN10(2) CMPEN9(2) CMPEN8(2) CMPEN7 CMPEN6 CMPEN5 CMPEN4 CMPEN3 CMPEN2 CMPEN1 CMPEN0 0000
ADCMP1ENH 0342 — — — — — — — — — — CMPEN21 CMPEN20 CMPEN19 CMPEN18 CMPEN17(2) CMPEN16(1) 0000
ADCMP1LO 0344 ADC Comparator 1 Low Value Register 0000
ADCMP1HI 0346 ADC Comparator 1 High Value Register 0000
ADFLDAT 0368 ADC Filter 0 Results Data Register 0000
ADFL1CON 036A FLEN MODE1 MODE0 OVRSAM2 OVRSAM1 OVRSAM0 IE RDY — — — FLCHSEL4 FLCHSEL3 FLCHSEL2 FLCHSEL1 FLCHSEL0 0000
ADFL1DAT 0368 ADC Filter 1 Results Data Register 0000
ADFL0CON 036A FLEN MODE1 MODE0 OVRSAM2 OVRSAM1 OVRSAM0 IE RDY — — — FLCHSEL4 FLCHSEL3 FLCHSEL2 FLCHSEL1 FLCHSEL0 0000
ADTRIG0L 0380 — — — TRGSRC1<4:0> — — — TRGSRC0<4:0> 0000
ADTRIG0H 0382 — — — TRGSRC3<4:0> — — — TRGSRC2<4:0> 0000
ADTRIG1L 0384 — — — TRGSRC5<4:0> — — — TRGSRC4<4:0>
0000
ADTRIG2H 038A — — — TRGSRC11<4:0> — — — TRGSRC10<4:0> 0000
ADTRIG3L 038C — — — TRGSRC13<4:0> — — — TRGSRC12<4:0> 0000
ADTRIG3H 038E — — — TRGSRC15<4:0> — — — TRGSRC14<4:0> 0000
ADCMP0CON 03A0 — — — CHNL4 CHNL3 CHNL2 CHNL1 CHNL0 CMPEN IE STAT BTWN HIHI HILO LOHI LOLO 0000
ADCMP1CON 03A4 — — — CHNL4 CHNL3 CHNL2 CHNL1 CHNL0 CMPEN IE STAT BTWN HIHI HILO LOHI LOLO 0000
Note 1: Implemented on dsPIC33EPXXGS506 devices only.
2: Implemented on dsPIC33EPXXGS504/505 and dsPIC33EPXXGS506 devices only.
TABLE 4-16: ADC REGISTER MAP (CONTINUED)
SFR All
Name Resets
ADLVLTRGL 03D0 LVLEN15(1) LVLEN14 LVLEN13(1) LVLEN12(2) LVLEN11(2) LVLEN10(2) LVLEN9(2) LVLEN8(2) LVLEN7 LVLEN6 LVLEN5 LVLEN4 LVLEN3 LVLEN2 LVLEN1 LVLEN0 0000
ADLVLTRGH 03D2 — — — — — — — — — — LVLEN21 LVLEN20 LVLEN19 LVLEN18 LVLEN17(2) LVLEN16(1) 0000
ADCORE0L 03D4 — — — — — — SAMC<9:0> 0000
ADCORE0H 03D6 — — — EISEL2 EISEL1 EISEL0 RES1 RES0 — ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000
ADCORE1L 03D8 — — — — — — SAMC<9:0> 0000
ADCORE1H 03DA — — — EISEL2 EISEL1 EISEL0 RES1 RES0 — ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000
ADCORE2L 03DC — — — — — — SAMC<9:0> 0000
ADCORE2H 03DE — — — EISEL2 EISEL1 EISEL0 RES1 RES0 — ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000
ADCORE3L 03E0 — — — — — — SAMC<9:0> 0000
ADCORE3H 03E2 — — — EISEL2 EISEL1 EISEL0 RES1 RES0 — ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000
ADEIEL 03F0 EIEN15(1) EIEN14(2) EIEN13(1) EIEN12(2) EIEN11(2) EIEN10(2) EIEN9(2) EIEN8(2) EIEN7 EIEN6 EIEN5 EIEN4 EIEN3 EIEN2 EIEN1 EIEN0 0000
ADEIEH 03F2 — — — — — — — — — — EIEN21 EIEN20 EIEN19 EIEN18 EIEN17(2) EIEN16(1) 0000
ADEISTATL 03F8 EISTAT15(1) EISTAT14(2) EISTAT13(1) EISTAT12(2) EISTAT11(2) EISTAT10(2) EISTAT9(2) EISTAT8(2) EISTAT7 EISTAT6 EISTAT5 EISTAT4 EISTAT3 EISTAT2 EISTAT1 EISTAT0 0000
ADEISTATH 03FA — — — — — — — — — — EISTAT21 EISTAT20 EISTAT19 EISTAT18 EISTAT17(2) EISTAT16(1) 0000
ADCON5L 0400 SHRRDY — — — C3RDY C2RDY C1RDY C0RDY SHRPWR — — — C3PWR C2PWR C1PWR C0PWR 0000
ADCON5H 0402 — — — — WARMTIME3 WARMTIME2 WARMTIME1 WARMTIME0 SHRCIE — — — C3CIE C2CIE C1CIE C0CIE 0000
ADCAL0L 0404 CAL1RDY — — — — CAL1DIFF CAL1EN CAL1RUN CAL0RDY — — — — CAL0DIFF CAL0EN CAL0RUN 0000
ADCAL0H 0406 CAL3RDY — — — — CAL3DIFF CAL3EN CAL3RUN CAL2RDY — — — — CAL2DIFF CAL2EN CAL2RUN 0000
ADCAL1H 040A CSHRRDY — — — — CSHRDIFF CSHREN CSHRRUN — — — — — — — — 0000
ADCBUF0 040C ADC Data Buffer 0 0000
ADCBUF1 040E ADC Data Buffer 1 0000
ADCBUF2 0410 ADC Data Buffer 2 0000
ADCBUF6 041B ADC Data Buffer 6 0000
ADCBUF7 041A ADC Data Buffer 7 0000
ADCBUF15 042A ADC Data Buffer 15 0000
DS70005127D-page 55

Note 1: Implemented on dsPIC33EPXXGS506 devices only.
2: Implemented on dsPIC33EPXXGS504/505 and dsPIC33EPXXGS506 devices only.
DS70005127D-page 56
TABLE 4-17: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXGS502 DEVICES
SFR All
Name Resets
RPOR0 0670 — — RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0 — — RP32R5 RP32R4 RP32R3 RP32R2 RP32R1 RP32R0 0000
RPOR5 067A — — RP43R5 RP43R4 RP43R3 RP43R2 RP43R1 RP43R0 — — RP42R5 RP42R4 RP42R3 RP42R2 RP42R1 RP42R0 0000
RPOR6 067C — — RP45R5 RP45R4 RP45R3 RP45R2 RP45R1 RP45R0 — — RP44R5 RP44R4 RP44R3 RP44R2 RP44R1 RP44R0 0000
RPOR7 067E — — RP47R5 RP47R4 RP47R3 RP47R2 RP47R1 RP47R0 — — RP46R5 RP46R4 RP46R3 RP46R2 RP46R1 RP46R0 0000
TABLE 4-18: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXGS504/505 DEVICES
SFR All
Name Resets
TABLE 4-19: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXGS506 DEVICES
SFR All
Name Resets
DS70005127D-page 57
DS70005127D-page 58
TABLE 4-20: PERIPHERAL PIN SELECT INPUT REGISTER MAP
SFR All
Name Resets
RPINR0 06A0 INT1R<7:0> — — — — — — — — 0000

RPINR1 06A2 — — — — — — — — INT2R<7:0> 0000
RPINR2 06A4 T1CKR<7:0> — — — — — — — — 0000
RPINR3 06A6 T3CKR7 T3CKR6 T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 T2CKR7 T2CKR6 T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 0000
RPINR7 06AE IC2R7 IC2R6 IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 IC1R7 IC1R6 IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 0000
RPINR8 06B0 IC4R7 IC4R6 IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 IC3R7 IC3R6 IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 0000
RPINR11 06B6 — — — — — — — — OCFAR<7:0> 0000
RPINR12 06B8 FLT2R7 FLT2R6 FLT2R5 FLT2R4 FLT2R3 FLT2R2 FLT2R1 FLT2R0 FLT1R7 FLT1R6 FLT1R5 FLT1R4 FLT1R3 FLT1R2 FLT1R1 FLT1R0 0000
RPINR13 06BA FLT4R7 FLT4R6 FLT4R5 FLT4R4 FLT4R3 FLT4R2 FLT4R1 FLT4R0 FLT3R7 FLT3R6 FLT3R5 FLT3R4 FLT3R3 FLT3R2 FLT3R1 FLT3R0 0000
RPINR18 06C4 U1CTSR7 U1CTSR6 U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTS0 U1RXR7 U1RXR6 U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 0000
RPINR19 06C6 U2CTSR7 U2CTSR6 U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 U2RXR7 U2RXR6 U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 0000
RPINR20 06C8 SCK1INR7 SCK1INR6 SCK1INR5 SCK1INR4 SCK1INR3 SCK1INR2 SCK1INR1 SCK1INR0 SDI1R7 SDI1R6 SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 0000
RPINR21 06CA — — — — — — — — SS1R<7:0> 0000
RPINR22 06CC SCK2INR7 SCK2INR6 SCK2INR5 SCK2INR4 SCK2INR3 SCK2INR2 SCK2INR1 SCK2INR0 SDI2R7 SDI2R6 SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 0000
RPINR23 06CE — — — — — — — — SS2R<7:0> 0000
RPINR37 06EA SYNCI1R<7:0> — — — — — — — — 0000
RPINR38 06EC — — — — — — — — SYNCI2R<7:0> 0000
RPINR42 06F4 FLT6R7 FLT6R6 FLT6R5 FLT6R4 FLT6R3 FLT6R2 FLT6R1 FLT6R0 FLT5R7 FLT5R6 FLT5R5 FLT5R4 FLT5R3 FLT5R2 FLT5R1 FLT5R0 0000
RPINR43 06F6 FLT8R7 FLT8R6 FLT8R5 FLT8R4 FLT8R3 FLT8R2 FLT8R1 FLT8R0 FLT7R7 FLT7R6 FLT7R5 FLT7R4 FLT7R3 FLT7R2 FLT7R1 FLT7R0 0000
TABLE 4-21: NVM REGISTER MAP

SFR All
Name Resets
NVMCON 0728 WR WREN WRERR NVMSIDL SFTSWP P2ACTIV RPDF URERR — — — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000
NVMADR 072A NVMADR<15:0> 0000
NVMADRU 072C — — — — — — — — NVMADR<23:16> 0000
NVMKEY 072E — — — — — — — — NVMKEY<7:0> 0000
NVMSRCADR 0730 NVM Source Data Address Register, Lower Word (NVMSRCADR<15:0>) 0000
NVMSRCADRH 0732 — — — — — — — — NVM Source Data Address Register, Upper Byte (NVMSRCADR<23:16> 0000
TABLE 4-22: SYSTEM CONTROL REGISTER MAP

SFR All
Name Resets
RCON 0740 TRAPR IOPUWR — — VREGSF — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note 1
OSCCON 0742 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF — — OSWEN Note 2
CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN FRCDIV2 FRCDIV1 FRCDIV0 PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 3040
PLLFBD 0746 — — — — — — — PLLDIV<8:0> 0030
OSCTUN 0748 — — — — — — — — — — TUN<5:0> 0000
LFSR 074C — LFSR<14:0> 0000
REFOCON 074E ROON — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000
ACLKCON 0750 ENAPLL APLLCK SELACLK — — APSTSCLR2 APSTSCLR1 APSTSCLR0 ASRCSEL FRCSEL — — — — — — 2740
Note 1: RCON register Reset values are dependent on the type of Reset.
2: OSCCON register Reset values are dependent on the Configuration fuses.
DS70005127D-page 59
DS70005127D-page 60
TABLE 4-23: PMD REGISTER MAP
SFR All
Name Resets
PMD1 0760 T5MD T4MD T3MD T2MD T1MD — PWMMD — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADCMD 0000
PMD2 0762 — — — — IC4MD IC3MD IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000
PMD3 0764 — — — — — CMPMD — — — — — — — — I2C2MD — 0000
PMD4 0766 — — — — — — — — — — — — REFOMD — — — 0000
PMD6 076A — — — PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD — — — — — — — — 0000
PMD7 076C — — — — CMP4MD CMP3MD CMP2MD CMP1MD — — — — — — PGA1MD — 0000
PMD8 076E — — — — — PGA2MD ABGMD — — — — — — — CCSMD — 0000
TABLE 4-24: CONSTANT-CURRENT SOURCE REGISTER MAP

SFR All
Name Resets
ISRCCON 0500 ISRCEN — — — — OUTSEL2 OUTSEL1 OUTSEL0 — — ISRCCAL5 ISRCCAL4 ISRCCAL3 ISRCCAL2 ISRCCAL1 ISRCCAL0 0000
TABLE 4-25: PROGRAMMABLE GAIN AMPLIFIER REGISTER MAP

SFR All
Name Resets
PGA1CON 0504 PGAEN PGAOEN SELPI2 SELPI1 SELPI0 SELNI2 SELNI1 SELNI0 — — — — — GAIN2 GAIN1 GAIN0 0000
PGA1CAL 0506 — — — — — — — — — — PGACAL<5:0> 0000
PGA2CON 0508 PGAEN PGAOEN SELPI2 SELPI1 SELPI0 SELNI2 SELNI1 SELNI0 — — — — — GAIN2 GAIN1 GAIN0 0000
PGA2CAL 050A — — — — — — — — — — PGACAL<5:0> 0000
TABLE 4-26: ANALOG COMPARATOR REGISTER MAP

SFR All
Name Resets
CMP1CON 0540 CMPON — CMPSIDL HYSSEL1 HYSSEL0 FLTREN FCLKSEL DACOE INSEL1 INSEL0 EXTREF HYSPOL CMPSTAT ALTINP CMPPOL RANGE 0000
CMP1DAC 0542 — — — — CMREF<11:0> 0000
CMP2DAC 0546 — — — — CMREF<11:0> 0000
CMP3DAC 054A — — — — CMREF<11:0> 0000
CMP4CON 054C CMPON — CMPSIDL HYSSEL1 HYSSEL0 FLTREN FCLKSEL DACOE INSEL1 INSEL0 EXTREF HYSPOL CMPSTAT ALTINP CMPPOL RANGE 0000
CMP4DAC 054E — — — — CMREF<11:0> 0000
TABLE 4-27: JTAG INTERFACE REGISTER MAP
SFR All
Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Resets
JDATAH 0FF0 — — — — JDATAH<11:0> xxxx

JDATAL 0FF2 JDATAL<15:0> 0000
DS70005127D-page 61
DS70005127D-page 62
TABLE 4-28: PORTA REGISTER MAP FOR dsPIC33EPXXGS502 DEVICES
SFR All
Name Resets
TRISA 0E00 — — — — — — — — — — — TRISA<4:0> 001F

PORTA 0E02 — — — — — — — — — — — RA<4:0> 0000
LATA 0E04 — — — — — — — — — — — LATA<4:0> 0000
ODCA 0E06 — — — — — — — — — — — ODCA<4:0> 0000
CNENA 0E08 — — — — — — — — — — — CNIEA<4:0> 0000
CNPUA 0E0A — — — — — — — — — — — CNPUA<4:0> 0000
CNPDA 0E0C — — — — — — — — — — — CNPDA<4:0> 0000
ANSELA 0E0E — — — — — — — — — — — — — ANSA<2:0> 0007
TABLE 4-29: PORTB REGISTER MAP FOR dsPIC33EPXXGS502 DEVICES

SFR All
Name Resets
TRISB 0E10 TRISB<15:0> FFFF

PORTB 0E12 RB<15:0> xxxx
LATB 0E14 LATB<15:0> xxxx
ODCB 0E16 ODCB<15:0> 0000
CNENB 0E18 CNIEB<15:0> 0000
CNPUB 0E1A CNPUB<15:0> 0000
CNPDB 0E1C CNPDB<15:0> 0000
ANSELB 0E1E — — — — — ANSB<10:9> — ANSB<7:0> 06FF
TABLE 4-30: PORTA REGISTER MAP FOR dsPIC33EPXXGS504/505 DEVICES

SFR All
Name Resets
TRISA 0E00 — — — — — — — — — — — TRISA<4:0> 001F

PORTA 0E02 — — — — — — — — — — — RA<4:0> 0000
LATA 0E04 — — — — — — — — — — — LATA<4:0> 0000
ODCA 0E06 — — — — — — — — — — — ODCA<4:0> 0000
CNENA 0E08 — — — — — — — — — — — CNIEA<4:0> 0000
CNPUA 0E0A — — — — — — — — — — — CNPUA<4:0> 0000
CNPDA 0E0C — — — — — — — — — — — CNPDA<4:0> 0000
ANSELA 0E0E — — — — — — — — — — — — — ANSA<2:0> 0007
TABLE 4-31: PORTB REGISTER MAP FOR dsPIC33EPXXGS504/505 DEVICES
SFR All
Name Resets

ODCB 0E16 ODCB<15:0> 0000
ANSELB 0E1E — — — — — ANSB<10:9> — ANSB<7:5> — ANSB<3:0> 06EF
TABLE 4-32: PORTC REGISTER MAP FOR dsPIC33EPXXGS504/505 DEVICES

SFR All
Name Resets
TRISC 0E20 — — TRISC<13:0> 3FFF

PORTC 0E22 — — RC<13:0> xxxx
DS70005127D-page 63
LATC 0E24 — — LATC<13:0> xxxx

ODCC 0E26 — — ODCC<13:0> 0000
CNENC 0E28 — — CNIEC<13:0> 0000
CNPUC 0E2A — — CNPUC<13:0> 0000
CNPDC 0E2C — — CNPDC<13:0> 0000
ANSELC 0E2E — — — ANSC<12:9> — — ANSC<6:4> — ANSC<2:0> 1E77
DS70005127D-page 64
TABLE 4-33: PORTA REGISTER MAP FOR dsPIC33EPXXGS506 DEVICES
SFR All
Name Resets
TRISA 0E00 — — — — — — — — — — — TRISA<4:0> 001F

PORTA 0E02 — — — — — — — — — — — RA<4:0> 0000
LATA 0E04 — — — — — — — — — — — LATA<4:0> 0000
ODCA 0E06 — — — — — — — — — — — ODCA<4:0> 0000
CNENA 0E08 — — — — — — — — — — — CNIEA<4:0> 0000
CNPUA 0E0A — — — — — — — — — — — CNPUA<4:0> 0000
CNPDA 0E0C — — — — — — — — — — — CNPDA<4:0> 0000
ANSELA 0E0E — — — — — — — — — — — — — ANSA<2:0> 0007
TABLE 4-34: PORTB REGISTER MAP FOR dsPIC33EPXXGS506 DEVICES

SFR All
Name Resets

ODCB 0E16 ODCB<15:0> 0000
ANSELB 0E1E — — — — — ANSB<10:9> — ANSB<7:5> — ANSB<3:0> 06EF
TABLE 4-35: PORTC REGISTER MAP FOR dsPIC33EPXXGS506 DEVICES

SFR All
Name Resets
TRISC 0E20 TRISC<15:0> FFFF

PORTC 0E22 RC<15:0> xxxx
LATC 0E24 LATC<15:0> xxxx
ODCC 0E26 ODCC<15:0> 0000
CNENC 0E28 CNIEC<15:0> 0000
CNPUC 0E2A CNPUC<15:0> 0000
CNPDC 0E2C CNPDC<15:0> 0000
ANSELC 0E2E — — — ANSC<12:9> — — ANSC<6:4> — ANSC<2:0> 1E77
TABLE 4-36: PORTD REGISTER MAP FOR dsPIC33EPXXGS506 DEVICES

SFR All
Name Resets
TRISD 0E30 TRISD<15:0> FFFF

PORTD 0E32 RD<15:0> xxxx
LATD 0E34 LATD<15:0> xxxx
ODCD 0E36 ODCD<15:0> 0000
CNEND 0E38 CNIED<15:0> 0000
CNPUD 0E3A CNPUD<15:0> 0000
CNPDD 0E3C CNPDD<15:0> 0000
ANSELD 0E3E — — ANSD13 — — — — — ANSD7 — — — — ANSD2 — — 6084
DS70005127D-page 65
4.5.1 PAGED MEMORY SCHEME The paged memory scheme provides access to
multiple 32-Kbyte windows in the PSV memory. The
The dsPIC33EPXXGS50X architecture extends the
Data Space Page (DSRPAG) register, in combination
available Data Space through a paging scheme,
with the upper half of the Data Space address, can
which allows the available Data Space to be
provide up to 8 Mbytes of PSV address space. The
accessed using MOV instructions in a linear fashion
paged data memory space is shown in Figure 4-10.
for pre- and post-modified Effective Addresses (EAs).
The upper half of the base Data Space address is The Program Space (PS) can be accessed with a
used in conjunction with the Data Space Page DSRPAG of 0x200 or greater. Only reads from PS are
(DSRPAG) register to form the Program Space supported using the DSRPAG.
Visibility (PSV) address.
The Data Space Page (DSRPAG) register is located
in the SFR space. Construction of the PSV address is
shown in Figure 4-9. When DSRPAG<9> = 1 and the
base address bit, EA<15> = 1, the DSRPAG<8:0> bits
are concatenated onto EA<14:0> to form the 24-bit
PSV read address.
FIGURE 4-9: PROGRAM SPACE VISIBILITY (PSV) READ ADDRESS GENERATION
Byte
16-Bit DS EA Select
EA<15> = 0 No EDS Access 0 EA

(DSRPAG = don’t care)
EA<15>
DSRPAG<9> 1 EA
=1
Select
DSRPAG
Generate
PSV Address 1 DSRPAG<8:0>
9 Bits 15 Bits
24-Bit PSV EA Byte

Select
Note: DS read access when DSRPAG = 0x000 will force an address error trap.

FIGURE 4-10: PAGED DATA MEMORY SPACE
Program Space Table Address Space

(Instruction & Data) (TBLPAG<7:0>)
DS_Addr<15:0>
0x0000
(TBLPAG = 0x00)
lsw Using
Program Memory TBLRDL/TBLWTL,
DS_Addr<14:0> (lsw – <15:0>) MSB Using
0x00_0000 TBLRDH/TBLWTH
0x0000 0xFFFF
(DSRPAG = 0x200)
Local Data Space No Writes Allowed
DS_Addr<15:0> 0x7FFF
PSV
0x0000
Program
SFR Registers Memory
0x0FFF (lsw) 0x0000
0x1000 0x0000 (TBLPAG = 0x7F)
(DSRPAG = 0x2FF) lsw Using
Up to 8-Kbyte TBLRDL/TBLWTL,
No Writes Allowed 0x7F_FFFF
RAM MSB Using
0x7FFF
0x0000 TBLRDH/TBLWTH
0x2FFF 0xFFFF
0x3000 (DSRPAG = 0x300)
0x7FFF No Writes Allowed Program Memory
0x8000 0x7FFF (MSB – <23:16>)
32-Kbyte PSV 0x00_0000
PSV Window Program
0xFFFF Memory
(MSB)
0x0000
(DSRPAG = 0x3FF)
No Writes Allowed
0x7FFF
DS70005127D-page 67
0x7F_FFFF
When a PSV page overflow or underflow occurs, address within the PSV window. This creates a linear
EA<15> is cleared as a result of the register indirect EA PSV address space, but only when using Register
calculation. An overflow or underflow of the EA in the Indirect Addressing modes.
PSV pages can occur at the page boundaries when: Exceptions to the operation described above arise
• The initial address, prior to modification, when entering and exiting the boundaries of Page 0
addresses the PSV page and PSV spaces. Table 4-37 lists the effects of overflow
• The EA calculation uses Pre- or Post-Modified and underflow scenarios at different boundaries.
Register Indirect Addressing; however, this does In the following cases, when overflow or underflow
not include Register Offset Addressing occurs, the EA<15> bit is set and the DSRPAG is not
In general, when an overflow is detected, the DSRPAG modified; therefore, the EA will wrap to the beginning of
register is incremented and the EA<15> bit is set to keep the current page:
the base address within the PSV window. When an • Register Indirect with Register Offset Addressing
underflow is detected, the DSRPAG register is • Modulo Addressing
decremented and the EA<15> bit is set to keep the base
• Bit-Reversed Addressing
TABLE 4-37: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0 AND

PSV SPACE BOUNDARIES(2,3,4)
Before After
O/U,
Operation DS Page DS Page
R/W DSxPAG DSxPAG
EA<15> Description EA<15> Description
O, DSRPAG = 0x2FF 1 PSV: Last lsw DSRPAG = 0x300 1 PSV: First MSB
Read [++Wn] page page
or
O, [Wn++] DSRPAG = 0x3FF 1 PSV: Last MSB DSRPAG = 0x3FF 0 See Note 1
Read page
U, DSRPAG = 0x001 1 PSV page DSRPAG = 0x001 0 See Note 1
Read
[--Wn]
U, DSRPAG = 0x200 1 PSV: First lsw DSRPAG = 0x200 0 See Note 1
or
Read page
[Wn--]
U, DSRPAG = 0x300 1 PSV: First MSB DSRPAG = 0x2FF 1 PSV: Last lsw
Read page page
Legend: O = Overflow, U = Underflow, R = Read, W = Write
Note 1: The Register Indirect Addressing now addresses a location in the base Data Space (0x0000-0x7FFF).
2: An EDS access, with DSRPAG = 0x000, will generate an address error trap.
3: Only reads from PS are supported using DSRPAG.
4: Pseudolinear Addressing is not supported for large offsets.

4.5.2 EXTENDED X DATA SPACE When the PC is pushed onto the stack, PC<15:0> are
pushed onto the first available stack word, then
The lower portion of the base address space range,
PC<22:16> are pushed into the second available stack
between 0x0000 and 0x7FFF, is always accessible,
location. For a PC push during any CALL instruction,
regardless of the contents of the Data Space Page reg-
the MSB of the PC is zero-extended before the push,
ister. It is indirectly addressable through the register
as shown in Figure 4-11. During exception processing,
indirect instructions. It can be regarded as being
the MSB of the PC is concatenated with the lower 8 bits
located in the default EDS Page 0 (i.e., EDS address
of the CPU STATUS Register, SR. This allows the
range of 0x000000 to 0x007FFF with the base address
contents of SRL to be preserved automatically during
bit, EA<15> = 0, for this address range). However,
interrupt processing.
Page 0 cannot be accessed through the upper
32 Kbytes, 0x8000 to 0xFFFF, of base Data Space in Note 1: To maintain system Stack Pointer (W15)
combination with DSRPAG = 0x00. Consequently, coherency, W15 is never subject to
DSRPAG is initialized to 0x001 at Reset. (EDS) paging, and is therefore, restricted
to an address range of 0x0000 to
Note 1: DSRPAG should not be used to access
0xFFFF. The same applies to the W14
Page 0. An EDS access with DSRPAG
when used as a Stack Frame Pointer
set to 0x000 will generate an address
(SFA = 1).
error trap.
2: As the stack can be placed in, and can
2: Clearing the DSRPAG in software has no
access X and Y spaces, care must be
effect.
taken regarding its use, particularly with
The remaining PSV pages are only accessible using regard to local automatic variables in a C
the DSRPAG register in combination with the upper development environment
32 Kbytes, 0x8000 to 0xFFFF, of the base address,
where base address bit, EA<15> = 1.
FIGURE 4-11: CALL STACK FRAME
4.5.3 SOFTWARE STACK
0x0000 15 0
The W15 register serves as a dedicated Software
CALL SUBR
Stack Pointer (SSP), and is automatically modified by
exception processing, subroutine calls and returns;
however, W15 can be referenced by any instruction in
Stack Grows Toward
Higher Address
the same manner as all other W registers. This simpli-

fies reading, writing and manipulating the Stack Pointer
PC<15:1> W15 (before CALL)
(for example, creating stack frames).
b‘000000000’ PC<22:16>
Note: To protect against misaligned stack <Free Word> W15 (after CALL)
accesses, W15<0> is fixed to ‘0’ by the
hardware.
W15 is initialized to 0x1000 during all Resets. This
address ensures that the SSP points to valid RAM in all
dsPIC33EPXXGS50X devices and permits stack avail-
ability for non-maskable trap exceptions. These can
occur before the SSP is initialized by the user software.
You can reprogram the SSP during initialization to any
location within Data Space.
The Software Stack Pointer always points to the first
available free word and fills the software stack,
working from lower toward higher addresses.
Figure 4-11 illustrates how it pre-decrements for a
stack pop (read) and post-increments for a stack push
(writes).

4.6 Instruction Addressing Modes 4.6.2 MCU INSTRUCTIONS
The addressing modes shown in Table 4-38 form the The three-operand MCU instructions are of the form:
basis of the addressing modes optimized to support the Operand 3 = Operand 1 <function> Operand 2
specific features of individual instructions. The
where Operand 1 is always a Working register (that is,
addressing modes provided in the MAC class of
the addressing mode can only be Register Direct),
instructions differ from those in the other instruction
which is referred to as Wb. Operand 2 can be a W
types.
register fetched from data memory or a 5-bit literal. The
result location can either be a W register or a data
4.6.1 FILE REGISTER INSTRUCTIONS
memory location. The following addressing modes are
Most file register instructions use a 13-bit address field supported by MCU instructions:
(f) to directly address data present in the first
• Register Direct
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a Working register, W0, • Register Indirect
which is denoted as WREG in these instructions. The • Register Indirect Post-Modified
destination is typically either the same file register or • Register Indirect Pre-Modified
WREG (with the exception of the MUL instruction), • 5-Bit or 10-Bit Literal
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can Note: Not all instructions support all the
access the entire Data Space. addressing modes given above. Individ-
ual instructions can support different
subsets of these addressing modes.
TABLE 4-38: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn form the Effective Address (EA).
Register Indirect Post-Modified The contents of Wn form the EA. Wn is post-modified (incremented
or decremented) by a constant value.
Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.

4.6.3 MOVE AND ACCUMULATOR 4.6.4 MAC INSTRUCTIONS
INSTRUCTIONS The dual source operand DSP instructions (CLR, ED,
Move instructions, and the DSP accumulator class EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
of instructions, provide a greater degree of address- to as MAC instructions, use a simplified set of addressing
ing flexibility than other instructions. In addition to the modes to allow the user application to effectively
addressing modes supported by most MCU manipulate the Data Pointers through register indirect
instructions, move and accumulator instructions also tables.
support Register Indirect with Register Offset The two-source operand prefetch registers must be
Addressing mode, also referred to as Register Indexed members of the set {W8, W9, W10, W11}. For data
mode. reads, W8 and W9 are always directed to the X RAGU,
Note: For the MOV instructions, the addressing and W10 and W11 are always directed to the Y AGU.
mode specified in the instruction can differ The Effective Addresses generated (before and after
for the source and destination EA. How- modification) must therefore, be valid addresses within
ever, the 4-bit Wb (Register Offset) field is X Data Space for W8 and W9, and Y Data Space for
shared by both source and destination (but W10 and W11.
typically only used by one). Note: Register Indirect with Register Offset
In summary, the following addressing modes are Addressing mode is available only for W9
supported by move and accumulator instructions: (in X space) and W11 (in Y space).
• Register Direct In summary, the following addressing modes are

• Register Indirect supported by the MAC class of instructions:
• Register Indirect Post-modified • Register Indirect
• Register Indirect Pre-modified • Register Indirect Post-Modified by 2
• Register Indirect with Register Offset (Indexed) • Register Indirect Post-Modified by 4
• Register Indirect with Literal Offset • Register Indirect Post-Modified by 6
• 8-Bit Literal • Register Indirect with Register Offset (Indexed)
• 16-Bit Literal
4.6.5 OTHER INSTRUCTIONS
Note: Not all instructions support all the
addressing modes given above. Individual Besides the addressing modes outlined previously,
instructions may support different subsets some instructions use literal constants of various sizes.
of these addressing modes. For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ULNK, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as a NOP, do not have
any operands.

4.7 Modulo Addressing 4.7.1 START AND END ADDRESS
Modulo Addressing mode is a method of providing an The Modulo Addressing scheme requires that a
automated means to support circular data buffers using starting and ending address be specified and loaded
hardware. The objective is to remove the need for into the 16-bit Modulo Buffer Address registers:
software to perform data address boundary checks XMODSRT, XMODEND, YMODSRT and YMODEND
when executing tightly looped code, as is typical in (see Table 4-2).
many DSP algorithms. Note: Y space Modulo Addressing EA calcula-
Modulo Addressing can operate in either Data or tions assume word-sized data (LSb of
Program Space (since the Data Pointer mechanism is every EA is always clear).
essentially the same for both). One circular buffer can be
The length of a circular buffer is not directly specified. It is
supported in each of the X (which also provides the point-
determined by the difference between the corresponding
ers into Program Space) and Y Data Spaces. Modulo
start and end addresses. The maximum possible length of
Addressing can operate on any W Register Pointer. How-
the circular buffer is 32K words (64 Kbytes).
ever, it is not advisable to use W14 or W15 for Modulo
Addressing since these two registers are used as the 4.7.2 W ADDRESS REGISTER SELECTION
Stack Frame Pointer and Stack Pointer, respectively.
The Modulo and Bit-Reversed Addressing Control
In general, any particular circular buffer can be config- register, MODCON<15:0>, contains enable flags, as well
ured to operate in only one direction, as there are certain as a W register field to specify the W Address registers.
restrictions on the buffer start address (for incrementing The XWM and YWM fields select the registers that
buffers) or end address (for decrementing buffers), operate with Modulo Addressing:
based upon the direction of the buffer.
• If XWM = 1111, X RAGU and X WAGU Modulo
The only exception to the usage restrictions is for Addressing is disabled
buffers that have a power-of-two length. As these
• If YWM = 1111, Y AGU Modulo Addressing is
buffers satisfy the start and end address criteria, they
disabled
can operate in a Bidirectional mode (that is, address
boundary checks are performed on both the lower and The X Address Space Pointer W (XWM) register, to
upper address boundaries). which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 4-2). Modulo Addressing is
enabled for X Data Space when XWM is set to any
value other than ‘1111’ and the XMODEN bit is set
(MODCON<15>).
The Y Address Space Pointer W (YWM) register, to
which Modulo Addressing is to be applied, is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
Data Space when YWM is set to any value other than
‘1111’ and the YMODEN bit (MODCON<14>) is set.
FIGURE 4-12: MODULO ADDRESSING OPERATION EXAMPLE

Byte MOV #0x1100, W0
Address MOV W0, XMODSRT ;set modulo start address
0x1100 MOV #0x1163, W0
MOV W0, MODEND ;set modulo end address
MOV #0x8001, W0
MOV W0, MODCON ;enable W1, X AGU for modulo
MOV #0x0000, W0 ;W0 holds buffer fill value
MOV #0x1110, W1 ;point W1 to buffer

0x1163
DO AGAIN, #0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
Start Addr = 0x1100 AGAIN: INC W0, W0 ;increment the fill value
End Addr = 0x1163
Length = 0x0032 words

4.7.3 MODULO ADDRESSING 4.8.1 BIT-REVERSED ADDRESSING
APPLICABILITY IMPLEMENTATION
Modulo Addressing can be applied to the Effective Bit-Reversed Addressing mode is enabled when all of
Address (EA) calculation associated with any W these situations are met:
register. Address boundaries check for addresses • BWMx bits (W register selection) in the MODCON
equal to: register are any value other than ‘1111’ (the stack
• The upper boundary addresses for incrementing cannot be accessed using Bit-Reversed
buffers Addressing)
• The lower boundary addresses for decrementing • The BREN bit is set in the XBREV register
buffers • The addressing mode used is Register Indirect
It is important to realize that the address boundaries with Pre-Increment or Post-Increment
check for addresses less than or greater than the upper If the length of a bit-reversed buffer is M = 2N bytes,
(for incrementing buffers) and lower (for decrementing the last ‘N’ bits of the data buffer start address must
buffers) boundary addresses (not just equal to). be zeros.
Address changes can, therefore, jump beyond
XB<14:0> is the Bit-Reversed Addressing modifier, or
boundaries and still be adjusted correctly.
‘pivot point’, which is typically a constant. In the case of
Note: The modulo corrected Effective Address an FFT computation, its value is equal to half of the FFT
is written back to the register only when data buffer size.
Pre-Modify or Post-Modify Addressing
Note: All bit-reversed EA calculations assume
mode is used to compute the Effective
word-sized data (LSb of every EA is
Address. When an address offset (such as
always clear). The XB value is scaled
[W7 + W2]) is used, Modulo Addressing
accordingly to generate compatible (byte)
correction is performed, but the contents of
addresses.
the register remain unchanged.
When enabled, Bit-Reversed Addressing is executed
4.8 Bit-Reversed Addressing only for Register Indirect with Pre-Increment or Post-
Increment Addressing and word-sized data writes. It
Bit-Reversed Addressing mode is intended to simplify does not function for any other addressing mode or for
data reordering for radix-2 FFT algorithms. It is byte-sized data and normal addresses are generated
supported by the X AGU for data writes only. instead. When Bit-Reversed Addressing is active, the
The modifier, which can be a constant value or register W Address Pointer is always added to the address
contents, is regarded as having its bit order reversed. modifier (XB) and the offset associated with the
The address source and destination are kept in normal Register Indirect Addressing mode is ignored. In addi-
order. Thus, the only operand requiring reversal is the tion, as word-sized data is a requirement, the LSb of
modifier. the EA is ignored (and always clear).
Note: Modulo Addressing and Bit-Reversed
Addressing can be enabled simultaneously
using the same W register, but Bit-
Reversed Addressing operation will always
take precedence for data writes when
enabled.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the Bit-Reversed Pointer.

FIGURE 4-13: BIT-REVERSED ADDRESSING EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0
Bit Locations Swapped Left-to-Right

Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0

Bit-Reversed Address
Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer
TABLE 4-39: BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY)

Normal Address Bit-Reversed Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 0 0 8
0 0 1 0 2 0 1 0 0 4
0 0 1 1 3 1 1 0 0 12
0 1 0 0 4 0 0 1 0 2
0 1 0 1 5 1 0 1 0 10
0 1 1 0 6 0 1 1 0 6
0 1 1 1 7 1 1 1 0 14
1 0 0 0 8 0 0 0 1 1
1 0 0 1 9 1 0 0 1 9
1 0 1 0 10 0 1 0 1 5
1 0 1 1 11 1 1 0 1 13
1 1 0 0 12 0 0 1 1 3
1 1 0 1 13 1 0 1 1 11
1 1 1 0 14 0 1 1 1 7
1 1 1 1 15 1 1 1 1 15

4.9 Interfacing Program and Data Table instructions allow an application to read or write
Memory Spaces to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
The dsPIC33EPXXGS50X family architecture uses a need to be updated periodically. It also allows access
24-bit wide Program Space (PS) and a 16-bit wide Data to all bytes of the program word. The remapping
Space (DS). The architecture is also a modified method allows an application to access a large block of
Harvard scheme, meaning that data can also be data on a read-only basis, which is ideal for look-ups
present in the Program Space. To use this data suc- from a large table of static data. The application can
cessfully, it must be accessed in a way that preserves only access the least significant word of the program
the alignment of information in both spaces. word.
Aside from normal execution, the architecture of the
dsPIC33EPXXGS50X family devices provides two
methods by which Program Space can be accessed
during operation:
• Using table instructions to access individual bytes
or words anywhere in the Program Space
• Remapping a portion of the Program Space into
the Data Space (Program Space Visibility)
TABLE 4-40: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Program Space Address
Access Type
Space <23> <22:16> <15> <14:1> <0>
Instruction Access User 0 PC<22:1> 0
(Code Execution) 0xxx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0>
(Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0> Data EA<15:0>
1xxx xxxx xxxx xxxx xxxx xxxx
FIGURE 4-14: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1) 0 Program Counter 0
23 Bits
EA 1/0
Table Operations(2) 1/0 TBLPAG
8 Bits 16 Bits
24 Bits
User/Configuration Byte Select

Space Select
Note 1: The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain
word alignment of data in the Program and Data Spaces.
2: Table operations are not required to be word-aligned. Table Read operations are permitted in the
configuration memory space.

4.9.1 DATA ACCESS FROM PROGRAM • TBLRDH (Table Read High):
MEMORY USING TABLE - In Word mode, this instruction maps the entire
INSTRUCTIONS upper word of a program address (P<23:16>)
to a data address. The ‘phantom’ byte
The TBLRDL and TBLWTL instructions offer a direct
(D<15:8>) is always ‘0’.
method of reading or writing the lower word of any
address within the Program Space without going - In Byte mode, this instruction maps the upper
through Data Space. The TBLRDH and TBLWTH or lower byte of the program word to D<7:0>
instructions are the only method to read or write the of the data address in the TBLRDL instruc-
upper 8 bits of a Program Space word as data. tion. The data is always ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
The PC is incremented by two for each successive
24-bit program word. This allows program memory In a similar fashion, two table instructions, TBLWTH
addresses to directly map to Data Space addresses. and TBLWTL, are used to write individual bytes or
Program memory can thus be regarded as two 16-bit words to a Program Space address. The details of
wide word address spaces, residing side by side, each their operation are explained in Section 5.0 “Flash
with the same address range. TBLRDL and TBLWTL Program Memory”.
access the space that contains the least significant For all table operations, the area of program memory
data word. TBLRDH and TBLWTH access the space that space to be accessed is determined by the Table Page
contains the upper data byte. register (TBLPAG). TBLPAG covers the entire program
Two table instructions are provided to move byte or memory space of the device, including user application
word-sized (16-bit) data to and from Program Space. and configuration spaces. When TBLPAG<7> = 0, the
Both function as either byte or word operations. table page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
• TBLRDL (Table Read Low): space.
- In Word mode, this instruction maps the lower
word of the Program Space location (P<15:0>)
to a data address (D<15:0>)
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
FIGURE 4-15: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space
TBLPAG
02
23 15 0
0x000000 23 16 8 0
00000000
00000000
0x020000 00000000
0x030000 00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
0x800000
the user memory area.

5.0 FLASH PROGRAM MEMORY device just before shipping the product. This also
allows the most recent firmware or a custom firmware
Note 1: This data sheet summarizes the features to be programmed.
of the dsPIC33EPXXGS50X family of Enhanced In-Circuit Serial Programming uses an
devices. It is not intended to be a compre- on-board bootloader, known as the Program Executive,
hensive reference source. To complement to manage the programming process. Using an SPI data
the information in this data sheet, refer to frame format, the Program Executive can erase,
“Flash Programming” (DS70005156) in program and verify program memory. For more informa-
the “dsPIC33/PIC24 Family Reference tion on Enhanced ICSP, see the device programming
Manual”, which is available from the specification.
Microchip web site (www.microchip.com)
RTSP is accomplished using TBLRD (Table Read) and
2: Some registers and associated bits TBLWT (Table Write) instructions. With RTSP, the user
described in this section may not be application can write program memory data with a
available on all devices. Refer to single program memory word and erase program mem-
Section 4.0 “Memory Organization” in ory in blocks or ‘pages’ of 512 instructions (1536 bytes)
this data sheet for device-specific register at a time.
and bit information.
The dsPIC33EPXXGS50X family devices contain 5.1 Table Instructions and Flash
internal Flash program memory for storing and Programming
executing application code. The memory is readable,
Regardless of the method used, all programming of
writable and erasable during normal operation over the
Flash memory is done with the Table Read and Table
entire VDD range.
Write instructions. These allow direct read and write
Flash memory can be programmed in three ways: access to the program memory space from the data
• In-Circuit Serial Programming™ (ICSP™) memory while the device is in normal operating mode.
programming capability The 24-bit target address in the program memory is
formed using bits<7:0> of the TBLPAG register and the
• Enhanced In-Circuit Serial Programming
Effective Address (EA) from a W register, specified in
(Enhanced ICSP)
the table instruction, as shown in Figure 5-1. The
• Run-Time Self-Programming (RTSP) TBLRDL and the TBLWTL instructions are used to read
ICSP allows for a dsPIC33EPXXGS50X family device or write to bits<15:0> of program memory. TBLRDL and
to be serially programmed while in the end application TBLWTL can access program memory in both Word
circuit. This is done with a programming clock and pro- and Byte modes. The TBLRDH and TBLWTH
gramming data (PGECx/PGEDx) line, and three other instructions are used to read or write to bits<23:16> of
lines for power (VDD), ground (VSS) and Master Clear program memory. TBLRDH and TBLWTH can also
(MCLR). This allows customers to manufacture boards access program memory in Word or Byte mode.
with unprogrammed devices and then program the
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
0 Program Counter 0
Program Counter
Working Reg EA
Using
1/0 TBLPAG Reg
Table Instruction
8 Bits 16 Bits
User/Configuration Byte
Space Select 24-Bit EA Select

5.2 RTSP Operation FIGURE 5-2: UNCOMPRESSED/
COMPRESSED FORMAT
The dsPIC33EPXXGS50X family Flash program
memory array is organized into rows of 64 instructions 15 7 0
or 192 bytes. RTSP allows the user application to erase Even Byte
a single page (8 rows or 512 instructions) of memory at LSW1
Address
Increasing
a time and to program one row at a time. It is possible 0x00 MSB1
Address
to program two instructions at a time as well.
LSW2
The page erase and single row write blocks are edge-
aligned, from the beginning of program memory, on 0x00 MSB2
boundaries of 1536 bytes and 192 bytes, respec-
tively. Figure 26-14 in Section 26.0 “Electrical UNCOMPRESSED FORMAT (RPDF = 0)
Characteristics” lists the typical erase and
programming times.
Row programming is performed by loading 192 bytes 15 7 0
into data memory and then loading the address of the Even Byte
LSW1
Increasing
first byte in that row into the NVMSRCADR register. Address
Address
Once the write has been initiated, the device will MSB2 MSB1
automatically load the write latches and increment the
NVMSRCADR and the NVMADR(U) registers until all LSW2
bytes have been programmed. The RPDF bit
(NVMCON<9>) selects the format of the stored data in COMPRESSED FORMAT (RPDF = 1)
RAM to be either compressed or uncompressed. See
Figure 5-2 for data formatting. Compressed data helps
to reduce the amount of required RAM by using the 5.3 Programming Operations
upper byte of the second word for the MSB of the
A complete programming sequence is necessary for
second instruction.
programming or erasing the internal Flash in RTSP
The basic sequence for RTSP word programming is to mode. The processor stalls (waits) until the program-
use the TBLWTL and TBLWTH instructions to load two of ming operation is finished. Setting the WR bit
the 24-bit instructions into the write latches found in (NVMCON<15>) starts the operation and the WR bit is
configuration memory space. Refer to Figure 4-1 automatically cleared when the operation is finished.
through Figure 4-4 for write latch addresses. Program-
ming is performed by unlocking and setting the control 5.3.1 PROGRAMMING ALGORITHM FOR
bits in the NVMCON register. FLASH PROGRAM MEMORY
All erase and program operations may optionally use Programmers can program two adjacent words
the NVM interrupt to signal the successful completion (24 bits x 2) of program Flash memory at a time on every
of the operation. For example, when performing Flash other word address boundary (0x000000, 0x000004,
write operations on the Inactive Partition in Dual 0x000008, etc.). To do this, it is necessary to erase the
Partition mode, where the CPU remains running, it is page that contains the desired address of the location
necessary to wait for the NVM interrupt before the user wants to change. For protection against
programming the next block of Flash program memory. accidental operations, the write initiate sequence for
NVMKEY must be used to allow any erase or program
operation to proceed. After the programming command
has been executed, the user application must wait for
the programming time until programming is complete.
The two instructions following the start of the
programming sequence should be NOPs.

5.4 Dual Partition Flash Configuration For robustness of operation, in order to execute the
BOOTSWP instruction, it is necessary to execute the
For dsPIC33EP64GS50X devices operating in Dual NVM unlocking sequence as follows:
Partition Flash Program Memory modes, the Inactive
Partition can be erased and programmed without stall- 1. Write 0x55 to NVMKEY.
ing the processor. The same programming algorithms 2. Write 0xAA to NVMKEY.
are used for programming and erasing the Flash in the 3. Execute the BOOTSWP instruction.
Inactive Partition, as described in Section 5.2 “RTSP If the unlocking sequence is not performed, the
Operation”. On top of the page erase option, the entire BOOTSWP instruction will be executed as a forced NOP
Flash memory of the Inactive Partition can be erased and a GOTO instruction, following the BOOTSWP instruc-
by configuring the NVMOP<3:0> bits in the NVMCON tion, will be executed, causing the PC to jump to that
register. location in the current operating partition.
Note 1: The application software to be loaded The SFTSWP and P2ACTIV bits in the NVMCON
into the Inactive Partition will have the register are used to determine a successful swap of the
address of the Active Partition. The Active and Inactive Partitions, as well as which partition
bootloader firmware will need to offset is active. After the BOOTSWP and GOTO instructions, the
the address by 0x400000 in order to write SFTSWP bit should be polled to verify the partition
to the Inactive Partition. swap has occurred and then cleared for the next panel
swap event.
5.4.1 FLASH PARTITION SWAPPING
The Boot Sequence Number is used for determining 5.4.2 DUAL PARTITION MODES
the Active Partition at start-up and is encoded within While operating in Dual Partition mode,
the FBTSEQ Configuration register bits. Unlike most dsPIC33EP64GS50X family devices have the option for
Configuration registers, which only utilize the lower both partitions to have their own defined security seg-
16 bits of the program memory, FBTSEQ is a 24-bit ments, as shown in Figure 23-4. Alternatively, the device
Configuration Word. The Boot Sequence Number can operate in Protected Dual Partition mode, where
(BSEQ) is a 12-bit value and is stored in FBTSEQ Partition 1 becomes permanently erase/write-protected.
twice. The true value is stored in bits, FBTSEQ<11:0>, Protected Dual Partition mode allows for a “Factory
and its complement is stored in bits, FBTSEQ<23:12>. Default” mode, which provides a fail-safe backup image
At device Reset, the sequence numbers are read and to be stored in Partition 1.
the partition with the lowest sequence number dsPIC33EP64GS50X family devices can also operate
becomes the Active Partition. If one of the Boot in Privileged Dual Partition mode, where additional
Sequence Numbers is invalid, the device will select the security protections are implemented to allow for pro-
partition with the valid Boot Sequence Number, or tection of intellectual property when multiple parties
default to Partition 1 if both sequence numbers are have software within the device. In Privileged Dual Par-
invalid. See Section 23.0 “Special Features” for more tition mode, both partitions place additional restrictions
information. on the BSLIM register. These prevent changes to the
The BOOTSWP instruction provides an alternative size of the Boot Segment and General Segment,
means of swapping the Active and Inactive Partitions ensuring that neither segment will be altered.
(soft swap) without the need for a device Reset. The
BOOTSWP must always be followed by a GOTO instruc- 5.5 Flash Memory Resources
tion. The BOOTSWP instruction swaps the Active and
Inactive Partitions, and the PC vectors to the location Many useful resources are provided on the main
specified by the GOTO instruction in the newly Active product page of the Microchip web site for the devices
Partition. listed in this data sheet. This product page contains the
latest updates and additional information.
It is important to note that interrupts should temporarily
be disabled while performing the soft swap sequence 5.5.1 KEY RESOURCES
and that after the partition swap, all peripherals and
interrupts which were enabled remain enabled. Addi- • Code Samples
tionally, the RAM and stack will maintain state after the • Application Notes
switch. As a result, it is recommended that applications • Software Libraries
using soft swaps jump to a routine that will reinitialize • Webinars
the device in order to ensure the firmware runs as
• All Related “dsPIC33/PIC24 Family Reference
expected. The Configuration registers will have no
Manual” Sections
effect during a soft swap.

5.6 Control Registers There are two NVM Address registers: NVMADRU and
NVMADR. These two registers, when concatenated,
Five SFRs are used to write and erase the program form the 24-bit Effective Address (EA) of the selected
Flash memory: NVMCON, NVMKEY, NVMADR, word/row for programming operations, or the selected
NVMADRU and NVMSRCADR/H. page for erase operations. The NVMADRU register is
The NVMCON register (Register 5-1) selects the used to hold the upper 8 bits of the EA, while the
operation to be performed (page erase, word/row NVMADR register is used to hold the lower 16 bits of
program, Inactive Partition erase), initiates the program the EA.
or erase cycle and is used to determine the Active For row programming operation, data to be written to
Partition in Dual Partition modes. program Flash memory is written into data memory
NVMKEY (Register 5-4) is a write-only register that is space (RAM) at an address defined by the
used for write protection. To start a programming or NVMSRCADR register (location of first element in row
erase sequence, the user application must programming data).
consecutively write 0x55 and 0xAA to the NVMKEY
register.

REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER
R/SO-0(1) R/W-0(1) R/W-0(1) R/W-0 R/C-0 R-0 R/W-0 R/C-0
WR WREN WRERR NVMSIDL(2) SFTSWP (6)
P2ACTIV (6)
RPDF URERR
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1)

(3,4) (3,4) (3,4)
— — — — NVMOP3 NVMOP2 NVMOP1 NVMOP0(3,4)
bit 7 bit 0
Legend: C = Clearable bit SO = Settable Only bit

bit 15 WR: Write Control bit(1)

1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit(1)
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12 NVMSIDL: NVM Stop in Idle Control bit(2)
1 = Flash voltage regulator goes into Standby mode during Idle mode
0 = Flash voltage regulator is active during Idle mode
bit 11 SFTSWP: Partition Soft Swap Status bit(6)
1 = Partitions have been successfully swapped using the BOOTSWP instruction (soft swap)
0 = Awaiting successful partition swap using the BOOTSWP instruction or a device Reset will determine
the Active Partition based on FBTSEQ
bit 10 P2ACTIV: Partition 2 Active Status bit(6)
1 = Partition 2 Flash is mapped into the active region
0 = Partition 1 Flash is mapped into the active region
bit 9 RPDF: Row Programming Data Format bit
1 = Row data to be stored in RAM in compressed format
0 = Row data to be stored in RAM in uncompressed format
Note 1: These bits can only be reset on a POR.

2: If this bit is set, power consumption will be further reduced (IIDLE) and upon exiting Idle mode, there is a
delay (TVREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.
6: Only available on dsPIC33EP64GS50X devices operating in Dual Partition mode. For all other devices,
this bit is reserved.
7: The specific Boot mode depends on bits<1:0> of the programmed data:
11 = Single Partition Flash mode
10 = Dual Partition Flash mode
01 = Protected Dual Partition Flash mode
00 = Reserved

REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER (CONTINUED)
bit 8 URERR: Row Programming Data Underrun Error bit
1 = Indicates row programming operation has been terminated
0 = No data underrun error is detected
bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,3,4)
1111 = Reserved
1110 = User memory Bulk Erase operation
1010 = Reserved
1001 = Reserved
1000 = Boot memory Double-Word Program operation in a Dual Partition Flash mode(7)
0101 = Reserved
0100 = Inactive Partition Memory Erase operation
0011 = Memory Page Erase operation
0010 = Memory Row Program operation
0001 = Memory Double-Word Program operation(5)
0000 = Reserved
Note 1: These bits can only be reset on a POR.

2: If this bit is set, power consumption will be further reduced (IIDLE) and upon exiting Idle mode, there is a
delay (TVREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.
6: Only available on dsPIC33EP64GS50X devices operating in Dual Partition mode. For all other devices,
this bit is reserved.
7: The specific Boot mode depends on bits<1:0> of the programmed data:
11 = Single Partition Flash mode
10 = Dual Partition Flash mode
01 = Protected Dual Partition Flash mode
00 = Reserved

REGISTER 5-2: NVMADR: NONVOLATILE MEMORY LOWER ADDRESS REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
NVMADR<15:8>
bit 15 bit 8

NVMADR<7:0>
bit 7 bit 0
Legend:
bit 15-0 NVMADR<15:0>: Nonvolatile Memory Lower Write Address bits

Selects the lower 16 bits of the location to program or erase in program Flash memory. This register
may be read or written to by the user application.
REGISTER 5-3: NVMADRU: NONVOLATILE MEMORY UPPER ADDRESS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

NVMADRU<23:16>
bit 7 bit 0
Legend:

bit 7-0 NVMADRU<23:16>: Nonvolatile Memory Upper Write Address bits
Selects the upper 8 bits of the location to program or erase in program Flash memory. This register
may be read or written to by the user application.

REGISTER 5-4: NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<7:0>
bit 7 bit 0
Legend:

bit 7-0 NVMKEY<7:0>: NVM Key Register bits (write-only)
REGISTER 5-5: NVMSRCADR: NVM SOURCE DATA ADDRESS REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADR<15:8>
bit 15 bit 8

NVMSRCADR<7:0>
bit 7 bit 0
Legend:
bit 15-0 NVMSRCADR<15:0>: NVM Source Data Address bits

The RAM address of the data to be programmed into Flash when the NVMOP<3:0> bits are set to row
programming.

6.0 RESETS A simplified block diagram of the Reset module is
shown in Figure 6-1.
Note 1: This data sheet summarizes the Any active source of Reset will make the SYSRST
features of the dsPIC33EPXXGS50X signal active. On system Reset, some of the registers
family of devices. It is not intended to be associated with the CPU and peripherals are forced to
a comprehensive reference source. To a known Reset state, and some are unaffected.
complement the information in this data
sheet, refer to “Reset” (DS70602) in the Note: Refer to the specific peripheral section or
“dsPIC33/PIC24 Family Reference Man- Section 4.0 “Memory Organization” of
ual”, which is available from the Microchip this manual for register Reset states.
web site (www.microchip.com)
All types of device Reset set a corresponding status bit
2: Some registers and associated bits in the RCON register to indicate the type of Reset (see
described in this section may not be Register 6-1).
A POR clears all the bits, except for the BOR and POR
bits (RCON<1:0>) that are set. The user application
this data sheet for device-specific register
can set or clear any bit, at any time, during code
execution. The RCON bits only serve as status bits.
The Reset module combines all Reset sources and Setting a particular Reset status bit in software does
controls the device Master Reset Signal, SYSRST. The not cause a device Reset to occur.
following is a list of device Reset sources: The RCON register also has other bits associated with
• POR: Power-on Reset the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
• BOR: Brown-out Reset
of this manual.
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction Note: The status bits in the RCON register
should be cleared after they are read so
• WDTO: Watchdog Timer Time-out Reset
that the next RCON register value after a
• CM: Configuration Mismatch Reset device Reset is meaningful.
• TRAPR: Trap Conflict Reset
For all Resets, the default clock source is determined
• IOPUWR: Illegal Condition Device Reset
by the FNOSC<2:0> bits in the FOSCSEL Configura-
- Illegal Opcode Reset tion register. The value of the FNOSCx bits is loaded
- Uninitialized W Register Reset into the NOSC<2:0> (OSCCON<10:8>) bits on Reset,
- Security Reset which in turn, initializes the system clock.
FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator SYSRST
VDD
VDD Rise POR

Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
Security Reset
Configuration Mismatch

6.1 Reset Resources 6.1.1 KEY RESOURCES
Many useful resources are provided on the main • “Reset” (DS70602) in the “dsPIC33/PIC24 Family
product page of the Microchip web site for the devices Reference Manual”
listed in this data sheet. This product page contains the • Code Samples
latest updates and additional information. • Application Notes
• Software Libraries
• Webinars
Manual” Sections

REGISTER 6-1: RCON: RESET CONTROL REGISTER(1)
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0
TRAPR IOPUWR — — VREGSF — CM VREGS
bit 15 bit 8

(2)
EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend:
bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or Uninitialized W register Reset has not occurred
bit 11 VREGSF: Flash Voltage Regulator Standby During Sleep bit
1 = Flash voltage regulator is active during Sleep
0 = Flash voltage regulator goes into Standby mode during Sleep
bit 9 CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has occurred.
0 = A Configuration Mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
bit 7 EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software RESET (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the WDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.

REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 3 SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up from Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the WDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.

7.0 INTERRUPT CONTROLLER 7.1.1 ALTERNATE INTERRUPT VECTOR
TABLE
Note 1: This data sheet summarizes the
The Alternate Interrupt Vector Table (AIVT), shown in
features of the dsPIC33EPXXGS50X
Figure 7-2, is available only when the Boot Segment is
family of devices. It is not intended to be a
defined and the AIVT has been enabled. To enable the
comprehensive reference source. To com-
Alternate Interrupt Vector Table, the Configuration bit,
plement the information in this data sheet,
AIVTDIS in the FSEC register, must be programmed
refer to “Interrupts” (DS70000600) in the
and the AIVTEN bit must be set (INTCON2<8> = 1).
“dsPIC33/PIC24 Family Reference Man-
When the AIVT is enabled, all interrupt and exception
ual”, which is available from the Microchip
processes use the alternate vectors instead of the
web site (www.microchip.com).
default vectors. The AIVT begins at the start of the last
2: Some registers and associated bits page of the Boot Segment, defined by BSLIM<12:0>.
described in this section may not be The second half of the page is no longer usable space.
available on all devices. Refer to The Boot Segment must be at least 2 pages to enable
Section 4.0 “Memory Organization” in the AIVT.
and bit information. Note: Although the Boot Segment must be
enabled in order to enable the AIVT,
The dsPIC33EPXXGS50X family interrupt controller application code does not need to be
reduces the numerous peripheral interrupt request present inside of the Boot Segment. The
signals to a single interrupt request signal to the AIVT (and IVT) will inherit the Boot
dsPIC33EPXXGS50X family CPU. Segment code protection.
The interrupt controller has the following features: The AIVT supports debugging by providing a means to
• Six processor exceptions and software traps switch between an application and a support environ-
• Seven user-selectable priority levels ment without requiring the interrupt vectors to be
reprogrammed. This feature also enables switching
• Interrupt Vector Table (IVT) with a unique vector
between applications for evaluation of different
for each interrupt or exception source
software algorithms at run time.
• Fixed priority within a specified user priority level
• Fixed interrupt entry and return latencies 7.2 Reset Sequence
• Alternate Interrupt Vector Table (AIVT) for debug
support A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33EPXXGS50X family devices clear their
7.1 Interrupt Vector Table
registers in response to a Reset, which forces the PC
The dsPIC33EPXXGS50X family Interrupt Vector to zero. The device then begins program execution at
Table (IVT), shown in Figure 7-1, resides in program location, 0x000000. A GOTO instruction at the Reset
memory, starting at location, 000004h. The IVT address can redirect program execution to the
contains six non-maskable trap vectors and up to appropriate start-up routine.
246 sources of interrupts. In general, each interrupt
Note: Any unimplemented or unused vector
source has its own vector. Each interrupt vector
locations in the IVT should be
contains a 24-bit wide address. The value programmed
programmed with the address of a default
into each interrupt vector location is the starting
interrupt handler routine that contains a
address of the associated Interrupt Service Routine
RESET instruction.
(ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 takes priority over interrupts at any other
vector address.

FIGURE 7-1: dsPIC33EPXXGS50X FAMILY INTERRUPT VECTOR TABLE
Decreasing Natural Order Priority Reset – GOTO Instruction 0x000000

Reset – GOTO Address 0x000002
Oscillator Fail Trap Vector 0x000004
Address Error Trap Vector 0x000006
Generic Hard Trap Vector 0x000008
Stack Error Trap Vector 0x00000A
Math Error Trap Vector 0x00000C
Reserved 0x00000E
Generic Soft Trap Vector 0x000010
Reserved 0x000012
Interrupt Vector 0 0x000014
: :
: :
: :
Interrupt Vector 52 0x00007C
IVT
Interrupt Vector 53 0x00007E

Interrupt Vector 54 0x000080 See Table 7-1 for
: : Interrupt Vector Details
: :
: :
Interrupt Vector 116 0x0000FC
Interrupt Vector 117 0x0000FE
: :
: :
: :
Interrupt Vector 244 0x0001FC
Interrupt Vector 245 0x0001FE
START OF CODE 0x000200
Note: In Dual Partition modes, each partition has a dedicated Interrupt Vector Table.

FIGURE 7-2: dsPIC33EPXXGS50X ALTERNATE INTERRUPT VECTOR TABLE(2)
Reserved BSLIM<12:0>(1) + 0x000000

Decreasing Natural Order Priority Reserved BSLIM<12:0>(1) + 0x000002
Oscillator Fail Trap Vector BSLIM<12:0>(1) + 0x000004
Address Error Trap Vector BSLIM<12:0>(1) + 0x000006
Generic Hard Trap Vector BSLIM<12:0>(1) + 0x000008
Stack Error Trap Vector BSLIM<12:0>(1) + 0x00000A
Math Error Trap Vector BSLIM<12:0>(1) + 0x00000C
Reserved BSLIM<12:0>(1) + 0x00000E
Generic Soft Trap Vector BSLIM<12:0>(1) + 0x000010
Reserved BSLIM<12:0>(1) + 0x000012
Interrupt Vector 0 BSLIM<12:0>(1) + 0x000014
: :
: :
: :
AIVT
Interrupt Vector 52 BSLIM<12:0>(1) + 0x00007C

Interrupt Vector 53 BSLIM<12:0>(1) + 0x00007E
Interrupt Vector 54 BSLIM<12:0>(1) + 0x000080 See Table 7-1 for
: : Interrupt Vector Details
: :
: :
Interrupt Vector 116 BSLIM<12:0>(1) + 0x0000FC
Interrupt Vector 117 BSLIM<12:0>(1) + 0x0000FE
: :
: :
: :
Interrupt Vector 244 BSLIM<12:0>(1) + 0x0001FC
Interrupt Vector 245 BSLIM<12:0>(1) + 0x0001FE
Note 1: The address depends on the size of the Boot Segment defined by BSLIM<12:0>.
[(BSLIM<12:0> – 1) x 0x400] + Offset.
2: In Dual Partition modes, each partition has a dedicated Alternate Interrupt Vector Table (if
enabled).

TABLE 7-1: INTERRUPT VECTOR DETAILS
Vector IRQ Interrupt Bit Location
Interrupt Source IVT Address
# # Flag Enable Priority
Highest Natural Order Priority
INT0 – External Interrupt 0 8 0 0x000014 IFS0<0> IEC0<0> IPC0<2:0>
IC1 – Input Capture 1 9 1 0x000016 IFS0<1> IEC0<1> IPC0<6:4>
OC1 – Output Compare 1 10 2 0x000018 IFS0<2> IEC0<2> IPC0<10:8>
T1 – Timer1 11 3 0x00001A IFS0<3> IEC0<3> IPC0<14:12>
Reserved 12 4 0x00001C — — —
IC2 – Input Capture 2 13 5 0x00001E IFS0<5> IEC0<5> IPC1<6:4>
T2 – Timer2 15 7 0x000022 IFS0<7> IEC0<7> IPC1<14:12>
T3 – Timer3 16 8 0x000024 IFS0<8> IEC0<8> IPC2<2:0>
SPI1E – SPI1 Error 17 9 0x000026 IFS0<9> IEC0<9> IPC2<6:4>
SPI1 – SPI1 Transfer Done 18 10 0x000028 IFS0<10> IEC0<10> IPC2<10:8>
U1RX – UART1 Receiver 19 11 0x00002A IFS0<11> IEC0<11> IPC2<14:12>
U1TX – UART1 Transmitter 20 12 0x00002C IFS0<12> IEC0<12> IPC3<2:0>
ADC – ADC Global Convert Done 21 13 0x00002E IFS0<13> IEC0<13> IPC3<6:4>
Reserved 22 14 0x000030 — — —
NVM – NVM Write Complete 23 15 0x000032 IFS0<15> IEC0<15> IPC3<14:12>
SI2C1 – I2C1 Slave Event 24 16 0x000034 IFS1<0> IEC1<0> IPC4<2:0>
MI2C1 – I2C1 Master Event 25 17 0x000036 IFS1<1> IEC1<1> IPC4<6:4>
CMP1 – Analog Comparator 1 Interrupt 26 18 0x000038 IFS1<2> IEC1<2> IPC4<10:8>
CN – Input Change Interrupt 27 19 0x00003A IFS1<3> IEC1<3> IPC4<14:12>
INT1 – External Interrupt 1 28 20 0x00003C IFS1<4> IEC1<4> IPC5<2:0>
Reserved 29-32 21-24 0x00003E-0x000044 — — —
T4 – Timer4 35 27 0x00004A IFS1<11> IEC1<11> IPC6<14:12>
T5 – Timer5 36 28 0x00004C IFS1<12> IEC1<12> IPC7<2:0>
INT2 – External Interrupt 2 37 29 0x00004E IFS1<13> IEC1<13> IPC7<6:4>
U2RX – UART2 Receiver 38 30 0x000050 IFS1<14> IEC1<14> IPC7<10:8>
U2TX – UART2 Transmitter 39 31 0x000052 IFS1<15> IEC1<15> IPC7<14:12>
SPI2E – SPI2 Error 40 32 0x000054 IFS2<0> IEC2<0> IPC8<2:0>
SPI2 – SPI2 Transfer Done 41 33 0x000056 IFS2<1> IEC2<1> IPC8<6:4>
Reserved 42-44 34-36 0x000058-0x00005C — — —
IC3 – Input Capture 3 45 37 0x00005E IFS2<5> IEC2<5> IPC9<6:4>
IC4 – Input Capture 4 46 38 0x000060 IFS2<6> IEC2<6> IPC9<10:8>
Reserved 47-56 39-48 0x000062-0x000074 — — —
SI2C2 – I2C2 Slave Event 57 49 0x000076 IFS3<1> IEC3<1> IPC12<6:4>
MI2C2 – I2C2 Master Event 58 50 0x000078 IFS3<2> IEC3<2> IPC12<10:8>
Reserved 59-61 51-53 0x00007A-0x00007E — — —
INT4 – External Interrupt 4 62 54 0x000080 IFS3<6> IEC3<6> IPC13<10:8>
Reserved 63-64 55-54 0x000082-0x000084 — — —
PSEM – PWM Special Event Match 65 57 0x000086 IFS3<9> IEC3<9> IPC14<6:4>
Reserved 66-72 58-64 0x000088-0x000094 — — —
U1E – UART1 Error Interrupt 73 65 0x000096 IFS4<1> IEC4<1> IPC16<6:4>
U2E – UART2 Error Interrupt 74 66 0x000098 IFS4<2> IEC4<2> IPC16<10:8>
Reserved 75-80 67-72 0x00009A-0x0000A4 — — —

TABLE 7-1: INTERRUPT VECTOR DETAILS (CONTINUED)
Vector IRQ Interrupt Bit Location
Interrupt Source IVT Address
# # Flag Enable Priority
PWM Secondary Special Event Match 81 73 0x0000A6 IFS4<9> IEC4<9> IPC18<6:4>
Reserved 82-101 74-93 0x0000A8-0x0000CE — — —
PWM1 – PWM1 Interrupt 102 94 0x0000D0 IFS5<14> IEC5<14> IPC23<10:8>
Reserved 106-110 99-102 0x0000DA-0x0000E0 — — —
CMP2 – Analog Comparator 2 Interrupt 111 103 0x0000E2 IFS6<7> IEC6<7> IPC25<14:12>
Reserved 114-117 106-109 0x0000E8-0x0000EE — — —
AN0 Conversion Done 118 110 0x0000F0 IFS6<14> IEC6<14> IPC27<10:8>
AN5 Conversion Done 123 115 0x0000FA IFS7<3> IEC7<3> IPC28<14:12>
AN6 Conversion Done 124 116 0x0000FC IFS7<4> IEC7<4> IPC29<2:0>
AN7 Conversion Done 125 117 0x0000FE IFS7<5> IEC7<5> IPC29<6:4>
Reserved 126-149 118-141 0x000100-0x00012E — — —
ICD – ICD Application 150 142 0x000130 IFS8<14> IEC8<14> IPC35<10:8>
JTAG – JTAG Programming 151 143 0x000132 IFS8<15> IEC8<15> IPC35<14:12>
Reserved 152-158 144-150 0x000134-0x000140 — — —
AN8 Conversion Done 159 151 0x000142 IFS9<7> IEC9<7> IPC37<14:12>
AN12 Conversion Done 163 155 0x00014A IFS9<11> IEC9<11> IPC38<14:12>
AN13 Conversion Done 164 156 0x00014C IFS9<12> IEC9<12> IPC39<2:0>
AN14 Conversion Done 165 157 0x00014E IFS9<13> IEC9<13> IPC39<6:4>
AN20 Conversion Done 171 163 0x00015A IFS10<3> IEC10<3> IPC40<14:12>
AN21 Conversion Done 172 164 0x00015C IFS10<4> IEC10<4> IPC41<2:0>
Reserved 173-180 165-172 0x00015C-0x00016C — — —
I2C1 – I2C1 Bus Collision 181 173 0x00016E IFS10<13> IEC10<13> IPC43<6:4>
I2C2 – I2C2 Bus Collision 182 174 0x000170 IFS10<14> IEC10<14> IPC43<10:8>
Reserved 183-184 175-176 0x000172-0x000174 — — —
ADCMP0 – ADC Digital Comparator 0 185 177 0x000176 IFS11<1> IEC11<1> IPC44<6:4>
ADCMP1 – ADC Digital Comparator 1 186 178 0x000178 IFS11<2> IEC11<2> IPC44<10:8>
ADFLTR0 – ADC Filter 0 187 179 0x00017A IFS11<3> IEC11<3> IPC44<14:12>
ADFLTR1 – ADC Filter 1 188 180 0x00017C IFS11<4> IEC11<4> IPC45<2:0>
Reserved 189-253 181-245 0x00017E-0x0001FE — — —

7.3 Interrupt Resources 7.4.3 IECx
Many useful resources are provided on the main prod- The IECx registers maintain all of the interrupt enable
uct page of the Microchip web site for the devices listed bits. These control bits are used to individually enable
in this data sheet. This product page contains the latest interrupts from the peripherals or external signals.
updates and additional information.
7.4.4 IPCx
7.3.1 KEY RESOURCES The IPCx registers are used to set the Interrupt Priority
• “Interrupts” (DS70000600) in the “dsPIC33/ Level (IPL) for each source of interrupt. Each user
PIC24 Family Reference Manual” interrupt sources can be assigned to one of seven
priority levels.
• Code Samples
• Application Notes 7.4.5 INTTREG
The INTTREG register contains the associated
• Webinars interrupt vector number and the new CPU Interrupt
• All Related “dsPIC33/PIC24 Family Reference Priority Level, which are latched into the Vector
Manual” Sections Number (VECNUM<7:0>) and Interrupt Level bits
• Development Tools (ILR<3:0>) fields in the INTTREG register. The new
Interrupt Priority Level is the priority of the pending
7.4 Interrupt Control and Status interrupt.
Registers The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence as they are
dsPIC33EPXXGS50X family devices implement the listed in Table 7-1. For example, the INT0 (External
following registers for the interrupt controller: Interrupt 0) is shown as having Vector Number 8 and a
• INTCON1 natural order priority of 0. Thus, the INT0IF bit is found
• INTCON2 in IFS0<0>, the INT0IE bit in IEC0<0> and the
INT0IP<2:0> bits in the first position of IPC0
• INTCON3
(IPC0<2:0>).
• INTCON4
• INTTREG 7.4.6 STATUS/CONTROL REGISTERS
Although these registers are not specifically part of the
7.4.1 INTCON1 THROUGH INTCON4
interrupt control hardware, two of the CPU Control
Global interrupt control functions are controlled from registers contain bits that control interrupt functionality.
INTCON1, INTCON2, INTCON3 and INTCON4. For more information on these registers refer to
INTCON1 contains the Interrupt Nesting Disable bit “CPU” (DS70359) in the “dsPIC33/PIC24 Family
(NSTDIS), as well as the control and status flags for the Reference Manual”.
processor trap sources. • The CPU STATUS Register, SR, contains the
The INTCON2 register controls external interrupt IPL<2:0> bits (SR<7:5>). These bits indicate the
request signal behavior, contains the Global Interrupt current CPU Interrupt Priority Level. The user
Enable bit (GIE) and the Alternate Interrupt Vector Table software can change the current CPU Interrupt
Enable bit (AIVTEN). Priority Level by writing to the IPLx bits.
INTCON3 contains the status flags for the Auxiliary • The CORCON register contains the IPL3 bit
PLL and DO stack overflow status trap sources. which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
The INTCON4 register contains the Software so that trap events cannot be masked by the user
Generated Hard Trap Status bit (SGHT). software.
7.4.2 IFSx All Interrupt registers are described in Register 7-3
through Register 7-7 in the following pages.
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.

REGISTER 7-1: SR: CPU STATUS REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0
OA OB SA SB OAB SAB DA DC
bit 15 bit 8
R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL2(2) IPL1 (2)
IPL0(2) RA N OV Z C
bit 7 bit 0

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
Note 1: For complete register details, see Register 3-1.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
IPL<3> = 1.

REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1)
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
VAR — US1 US0 EDT DL2 DL1 DL0
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3(2) SFA RND IF
bit 7 bit 0

bit 15 VAR: Variable Exception Processing Latency Control bit

1 = Variable exception processing is enabled
0 = Fixed exception processing is enabled
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: For complete register details, see Register 3-2.


REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1
NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —
bit 7 bit 0
Legend:
bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14 OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13 OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10 OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap is disabled
bit 9 OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
bit 8 COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B is enabled
bit 7 SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6 DIV0ERR: Divide-by-Zero Error Status bit
1 = Math error trap was caused by a divide-by-zero
0 = Math error trap was not caused by a divide-by-zero
bit 4 MATHERR: Math Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred

REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred

R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0
GIE DISI SWTRAP — — — — AIVTEN
bit 15 bit 8
U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

— — — INT4EP — INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
bit 15 GIE: Global Interrupt Enable bit

1 = Interrupts and associated IE bits are enabled
0 = Interrupts are disabled, but traps are still enabled
bit 14 DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13 SWTRAP: Software Trap Status bit
1 = Software trap is enabled
0 = Software trap is disabled
bit 8 AIVTEN: Alternate Interrupt Vector Table Enable
1 = Uses Alternate Interrupt Vector Table
0 = Uses standard Interrupt Vector Table
bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — NAE
bit 15 bit 8
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0

— — — DOOVR — — — APLL
bit 7 bit 0
Legend:

bit 8 NAE: NVM Address Error Soft Trap Status bit
1 = NVM address error soft trap has occurred
0 = NVM address error soft trap has not occurred
bit 4 DOOVR: DO Stack Overflow Soft Trap Status bit
1 = DO stack overflow soft trap has occurred
0 = DO stack overflow soft trap has not occurred
bit 0 APLL: Auxiliary PLL Loss of Lock Soft Trap Status bit
1 = APLL lock soft trap has occurred
0 = APLL lock soft trap has not occurred

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — SGHT
bit 7 bit 0
Legend:

bit 0 SGHT: Software Generated Hard Trap Status bit
1 = Software generated hard trap has occurred
0 = Software generated hard trap has not occurred

REGISTER 7-7: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — ILR3 ILR2 ILR1 ILR0
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VECNUM7 VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0
bit 7 bit 0
Legend:

bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
bit 7-0 VECNUM<7:0>: Vector Number of Pending Interrupt bits
11111111 = 255, Reserved; do not use
•
•
•
00001001 = 9, IC1 – Input Capture 1
00001000 = 8, INT0 – External Interrupt 0
00000110 = 6, Generic soft error trap
00000100 = 4, Math error trap
00000011 = 3, Stack error trap
00000010 = 2, Generic hard trap
00000001 = 1, Address error trap
00000000 = 0, Oscillator fail trap

NOTES:

8.0 OSCILLATOR CONFIGURATION The dsPIC33EPXXGS50X family oscillator system
provides:
• On-chip Phase-Locked Loop (PLL) to boost
internal operating frequency on select internal and
devices. It is not intended to be a compre-
external oscillator sources
hensive reference source. To complement
the information in this data sheet, refer • On-the-fly clock switching between various clock
to “Oscillator Module” (DS70005131) in sources
the “dsPIC33/PIC24 Family Reference • Doze mode for system power savings
Manual”, which is available from the • Fail-Safe Clock Monitor (FSCM) that detects clock
Microchip web site (www.microchip.com). failure and permits safe application recovery or
2: Some registers and associated bits shutdown
described in this section may not be • Configuration bits for clock source selection
available on all devices. Refer to • Auxiliary PLL for ADC and PWM
A simplified diagram of the oscillator system is shown
in Figure 8-1.

FIGURE 8-1: OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator (POSC)

DOZE<2:0>
OSC1
POSCCLK XT, HS, EC
S2
XTPLL, HSPLL,
S3 FPLLO ECPLL, FRCPLL
S1/S3
DOZE
FCY(2)
S1 PLL
F VCO(1)
OSC2
POSCMD<1:0>
FP(2)
÷2
FRCDIV
FRC FRCCLK FRCDIVN FOSC
S7
Oscillator
REFERENCE CLOCK OUTPUT

TUN<5:0> FRCDIV<2:0>
FRCDIV16 POSCCLK REFCLKO
÷ 16 S6
÷N
FRC FOSC RPn
S0
RODIV<3:0>
LPRC LPRC ROSEL
S5
Oscillator
Clock Fail Clock Switch Reset
S0 NOSC<2:0> FNOSC<2:0>
WDT, PWRT,
FSCM
AUXILIARY CLOCK GENERATOR CIRCUIT BLOCK DIAGRAM
FRCCLK FVCO(1)
1 0
ACLK PWM/ADC
POSCCLK 1 APLL x 16 1 ÷N
to LFSR
0 1
GND 0 0
ASRCSEL FRCSEL ENAPLL SELACLK APSTSCLR<2:0>(4)
Note 1: See Figure 8-2 for the source of the FVCO signal.
2: FP refers to the clock source for all the peripherals, while FCY (or MIPS) refers to the clock source for the CPU.
Throughout this document, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will
be different when Doze mode is used in any ratio other than 1:1.
3: The auxiliary clock postscaler must be configured to divide-by-1 (APSTSCLR<2:0> = 111) for proper operation of
the PWM and ADC modules.

8.1 CPU Clocking System Instruction execution speed or device operating
frequency, FCY, is given by Equation 8-1.
The dsPIC33EPXXGS50X family of devices provides
six system clock options: EQUATION 8-1: DEVICE OPERATING
• Fast RC (FRC) Oscillator FREQUENCY
• FRC Oscillator with Phase-Locked Loop FCY = FOSC/2
(FRCPLL)
• FRC Oscillator with Postscaler Figure 8-2 is a block diagram of the PLL module.
• Primary (XT, HS or EC) Oscillator Equation 8-2 provides the relationship between Input
• Primary Oscillator with PLL Frequency (FIN) and Output Frequency (FPLLO).
Equation 8-3 provides the relationship between Input
• Low-Power RC (LPRC) Oscillator
Frequency (FIN) and VCO Frequency (FVCO).
FIGURE 8-2: PLL BLOCK DIAGRAM
0.8 MHz < FPLLI(1) < 8.0 MHz FPLLO(1)  120 MHz @ +125ºC
120 MHZ < FVCO(1) < 340 MHZ FPLLO(1)  140 MHz @ +85ºC
FIN FPLLI
÷ N1 FVCO FOSC
PFD VCO ÷ N2
PLLPRE<4:0>
PLLPOST<1:0>
÷M
PLLDIV<8:0>
Note 1: This frequency range must be met at all times.
EQUATION 8-2: FPLLO CALCULATION
M PLLDIV<8:0> + 2
FPLLO = FIN  ( N1 ) (
= FIN  (PLLPRE<4:0> + 2) 2(PLLPOST<1:0> + 1) )
Where:
N1 = PLLPRE<4:0> + 2
N2 = 2 x (PLLPOST<1:0> + 1)
M = PLLDIV<8:0> + 2
EQUATION 8-3: FVCO CALCULATION
M PLLDIV<8:0> + 2
FVCO = FIN  ()
N1 (
= FIN  (PLLPRE<4:0> + 2) )

TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
See
Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0>
Notes
Fast RC Oscillator with Divide-by-n (FRCDIVN) Internal xx 111 1, 2
Fast RC Oscillator with Divide-by-16 Internal xx 110 1
Low-Power RC Oscillator (LPRC) Internal xx 101 1
Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011
Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011
Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1
Primary Oscillator (HS) Primary 10 010
Primary Oscillator (XT) Primary 01 010
Primary Oscillator (EC) Primary 00 010 1
Fast RC Oscillator (FRC) with Divide-by-N and Internal xx 001 1
PLL (FRCPLL)
Fast RC Oscillator (FRC) Internal xx 000 1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
8.2 Auxiliary Clock Generation 8.3 Reference Clock Generation

The auxiliary clock generation is used for peripherals The reference clock output logic provides the user with
that need to operate at a frequency unrelated to the the ability to output a clock signal based on the system
system clock, such as PWM or ADC. clock or the crystal oscillator on a device pin. The user
The primary oscillator and internal FRC oscillator application can specify a wide range of clock scaling
sources can be used with an Auxiliary PLL (APLL) to prior to outputting the reference clock.
obtain the auxiliary clock. The Auxiliary PLL has a fixed
16x multiplication factor. 8.4 Oscillator Resources
The auxiliary clock has the following configuration Many useful resources are provided on the main prod-
restrictions: uct page of the Microchip web site for the devices listed
• For proper PWM operation, auxiliary clock in this data sheet. This product page contains the latest
generation must be configured for 120 MHz (see updates and additional information.
Parameter OS56 in Section 26.0 “Electrical Char-
acteristics”). If a slower frequency is desired, the 8.4.1 KEY RESOURCES
PWM Input Clock Prescaler (Divider) Select bits • Code Samples
(PCLKDIV<2:0>) should be used. • Application Notes
• To achieve 1.04 ns PWM resolution, the auxiliary • Software Libraries
clock must use the 16x Auxiliary PLL (APLL). All • Webinars
other clock sources will have a minimum PWM
resolution of 8 ns.
Manual” Sections
• If the primary PLL is used as a source for the
auxiliary clock, the primary PLL should be config-
ured up to a maximum operation of 30 MIPS or
less.

8.5 Oscillator Control Registers
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1)
U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y
— COSC2 COSC1 COSC0 — NOSC2(2) NOSC1(2) NOSC0(2)
bit 15 bit 8
R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0

CLKLOCK IOLOCK LOCK — CF(3) — — OSWEN
bit 7 bit 0
Legend: y = Value set from Configuration bits on POR


bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Reserved
011 = Primary Oscillator (XT, HS, EC) with PLL
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
100 = Reserved
011 = Primary Oscillator (XT, HS, EC) with PLL
001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
bit 7 CLKLOCK: Clock Lock Enable bit
1 = If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and
PLL configurations may be modified
0 = Clock and PLL selections are not locked, configurations may be modified
bit 6 IOLOCK: I/O Lock Enable bit
1 = I/O lock is active
0 = I/O lock is not active
bit 5 LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Note 1: Writes to this register require an unlock sequence.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and will trigger an oscillator failure trap.

REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
bit 3 CF: Clock Fail Detect bit(3)
1 = FSCM has detected a clock failure
0 = FSCM has not detected a clock failure
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Requests oscillator switch to the selection specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
Note 1: Writes to this register require an unlock sequence.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and will trigger an oscillator failure trap.

REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER
ROI DOZE2(1) DOZE1(1) DOZE0(1) DOZEN(2,3) FRCDIV2 FRCDIV1 FRCDIV0
bit 15 bit 8
R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0
bit 7 bit 0
Legend:
bit 15 ROI: Recover on Interrupt bit

1 = Interrupts will clear the DOZEN bit and the processor clock, and the peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits(1)
111 = FCY divided by 128
011 = FCY divided by 8 (default)
bit 11 DOZEN: Doze Mode Enable bit(2,3)
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock and peripheral clock ratio is forced to 1:1
bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divided by 256
000 = FRC divided by 1 (default)
bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output divided by 8
10 = Reserved
01 = Output divided by 4 (default)
00 = Output divided by 2
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.

REGISTER 8-2: CLKDIV: CLOCK DIVISOR REGISTER (CONTINUED)
bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input divided by 33
•
•
•
00001 = Input divided by 3
00000 = Input divided by 2 (default)
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — PLLDIV8
bit 15 bit 8

PLLDIV<7:0>
bit 7 bit 0
Legend:

bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111 = 513
•
•
•
000110000 = 50 (default)
•
•
•
000000010 = 4
000000001 = 3
000000000 = 2

REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN<5:0>
bit 7 bit 0
Legend:

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits
011111 = Maximum frequency deviation of 1.457% (7.477 MHz)
011110 = Center frequency + 1.41% (7.474 MHz)
•
•
•
000001 = Center frequency + 0.047% (7.373 MHz)
000000 = Center frequency (7.37 MHz nominal)
111111 = Center frequency – 0.047% (7.367 MHz)
•
•
•
100001 = Center frequency – 1.457% (7.263 MHz)
100000 = Minimum frequency deviation of -1.5% (7.259 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.

REGISTER 8-5: ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER
R/W-0 R-0 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1
ENAPLL APLLCK SELACLK — — APSTSCLR2 APSTSCLR1 APSTSCLR0
bit 15 bit 8
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

ASRCSEL FRCSEL — — — — — —
bit 7 bit 0
Legend:
bit 15 ENAPLL: Auxiliary PLL Enable bit

1 = APLL is enabled
0 = APLL is disabled
bit 14 APLLCK: APLL Locked Status bit (read-only)
1 = Indicates that Auxiliary PLL is in lock
0 = Indicates that Auxiliary PLL is not in lock
bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1 = Auxiliary oscillators provide the source clock for the auxiliary clock divider
0 = Primary PLL (FVCO) provides the source clock for the auxiliary clock divider
bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider bits
111 = Divided by 1
110 = Divided by 2
101 = Divided by 4
100 = Divided by 8
011 = Divided by 16
010 = Divided by 32
001 = Divided by 64
000 = Divided by 256
bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit
1 = Primary oscillator is the clock source
0 = No clock input is selected
bit 6 FRCSEL: Select Reference Clock Source for Auxiliary PLL bit
1 = Selects the FRC clock for Auxiliary PLL
0 = Input clock source is determined by the ASRCSEL bit setting

REGISTER 8-6: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROON — ROSSLP ROSEL RODIV3(1) RODIV2(1) RODIV1(1) RODIV0(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15 ROON: Reference Oscillator Output Enable bit

1 = Reference oscillator output is enabled on the RPn pin(2)
0 = Reference oscillator output is disabled
bit 13 ROSSLP: Reference Oscillator Run in Sleep bit
1 = Reference oscillator output continues to run in Sleep
0 = Reference oscillator output is disabled in Sleep
bit 12 ROSEL: Reference Oscillator Source Select bit
1 = Oscillator crystal is used as the reference clock
0 = System clock is used as the reference clock
bit 11-8 RODIV<3:0>: Reference Oscillator Divider bits(1)
1111 = Reference clock divided by 32,768
1001 = Reference clock divided by 512
0000 = Reference clock
Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
2: This pin is remappable. See Section 10.4 “Peripheral Pin Select (PPS)” for more information.

REGISTER 8-7: LFSR: LINEAR FEEDBACK SHIFT REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— LFSR<14:8>
bit 15 bit 8

LFSR<7:0>
bit 7 bit 0
Legend:

bit 14-0 LFSR<14:0>: Pseudorandom Data bits

9.0 POWER-SAVING FEATURES 9.1 Clock Frequency and Clock
Switching
features of the dsPIC33EPXXGS50X The dsPIC33EPXXGS50X family devices allow a wide
family of devices. It is not intended to be range of clock frequencies to be selected under appli-
a comprehensive reference source. To cation control. If the system clock configuration is not
complement the information in this data locked, users can choose low-power or high-precision
sheet, refer to “Watchdog Timer and oscillators by simply changing the NOSCx bits
Power-Saving Modes” (DS70615) in (OSCCON<10:8>). The process of changing a system
the “dsPIC33/PIC24 Family Reference clock during operation, as well as limitations to the
Manual”, which is available from the process, are discussed in more detail in Section 8.0
Microchip web site (www.microchip.com). “Oscillator Configuration”.
described in this section may not be 9.2 Instruction-Based Power-Saving
available on all devices. Refer to Modes
The dsPIC33EPXXGS50X family devices have two
special power-saving modes that are entered
through the execution of a special PWRSAV instruc-
The dsPIC33EPXXGS50X family devices provide the tion. Sleep mode stops clock operation and halts all
ability to manage power consumption by selectively code execution. Idle mode halts the CPU and code
managing clocking to the CPU and the peripherals. execution, but allows peripheral modules to continue
In general, a lower clock frequency and a reduction operation. The assembler syntax of the PWRSAV
in the number of peripherals being clocked instruction is shown in Example 9-1.
constitutes lower consumed power. Note: SLEEP_MODE and IDLE_MODE are con-
dsPIC33EPXXGS50X family devices can manage stants defined in the assembler include
power consumption in four ways: file for the selected device.
• Clock Frequency Sleep and Idle modes can be exited as a result of an
• Instruction-Based Sleep and Idle modes enabled interrupt, WDT time-out or a device Reset. When
• Software-Controlled Doze mode the device exits these modes, it is said to “wake-up”.
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
EXAMPLE 9-1: PWRSAV INSTRUCTION SYNTAX

PWRSAV #SLEEP_MODE ; Put the device into Sleep mode
PWRSAV #IDLE_MODE ; Put the device into Idle mode

9.2.1 SLEEP MODE 9.2.2 IDLE MODE
The following occurs in Sleep mode: The following occurs in Idle mode:
• The system clock source is shut down. If an • The CPU stops executing instructions.
on-chip oscillator is used, it is turned off. • The WDT is automatically cleared.
• The device current consumption is reduced to a • The system clock source remains active. By
minimum, provided that no I/O pin is sourcing default, all peripheral modules continue to operate
current. normally from the system clock source, but can
• The Fail-Safe Clock Monitor does not operate, also be selectively disabled (see Section 9.4
since the system clock source is disabled. “Peripheral Module Disable”).
• The LPRC clock continues to run in Sleep mode if • If the WDT or FSCM is enabled, the LPRC also
the WDT is enabled. remains active.
• The WDT, if enabled, is automatically cleared The device wakes from Idle mode on any of these
prior to entering Sleep mode. events:
• Some device features or peripherals can continue • Any interrupt that is individually enabled
to operate. This includes items such as the Input • Any device Reset
Change Notification on the I/O ports or peripherals
• A WDT time-out
that use an external clock input.
• Any peripheral that requires the system clock On wake-up from Idle mode, the clock is reapplied to
source for its operation is disabled. the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the instruction following the
The device wakes up from Sleep mode on any of the PWRSAV instruction or the first instruction in the ISR.
these events:
All peripherals also have the option to discontinue
• Any interrupt source that is individually enabled operation when Idle mode is entered to allow for
• Any form of device Reset increased power savings. This option is selectable in
• A WDT time-out the control register of each peripheral (for example, the
On wake-up from Sleep mode, the processor restarts TSIDL bit in the Timer1 Control register (T1CON<13>).
with the same clock source that was active when Sleep
9.2.3 INTERRUPTS COINCIDENT WITH
mode was entered.
POWER SAVE INSTRUCTIONS
For optimal power savings, the internal regulator and
the Flash regulator can be configured to go into stand- Any interrupt that coincides with the execution of a
by when Sleep mode is entered by clearing the VREGS PWRSAV instruction is held off until entry into Sleep or
(RCON<8>) and VREGSF (RCON<11>) bits (default Idle mode has completed. The device then wakes up
configuration). from Sleep or Idle mode.
If the application requires a faster wake-up time, and

can accept higher current requirements, the VREGS
(RCON<8>) and VREGSF (RCON<11>) bits can be set
to keep the internal regulator and the Flash regulator
active during Sleep mode.

9.3 Doze Mode 9.4 Peripheral Module Disable
The preferred strategies for reducing power consump- The Peripheral Module Disable (PMD) registers
tion are changing clock speed and invoking one of the provide a method to disable a peripheral module by
power-saving modes. In some circumstances, this stopping all clock sources supplied to that module.
cannot be practical. For example, it may be necessary When a peripheral is disabled using the appropriate
for an application to maintain uninterrupted synchro- PMD control bit, the peripheral is in a minimum power
nous communication, even while it is doing nothing consumption state. The control and status registers
else. Reducing system clock speed can introduce associated with the peripheral are also disabled, so
communication errors, while using a power-saving writes to those registers do not have any effect and
mode can stop communications completely. read values are invalid.
Doze mode is a simple and effective alternative method A peripheral module is enabled only if both the associ-
to reduce power consumption while the device is still ated bit in the PMD register is cleared and the peripheral
executing code. In this mode, the system clock is supported by the specific dsPIC® DSC variant. If the
continues to operate from the same source and at the peripheral is present in the device, it is enabled in the
same speed. Peripheral modules continue to be PMD register by default.
clocked at the same speed, while the CPU clock speed
Note: If a PMD bit is set, the corresponding
is reduced. Synchronization between the two clock
module is disabled after a delay of one
domains is maintained, allowing the peripherals to
instruction cycle. Similarly, if a PMD bit is
access the SFRs while the CPU executes code at a
cleared, the corresponding module is
slower rate.
enabled after a delay of one instruction
Doze mode is enabled by setting the DOZEN bit cycle (assuming the module control regis-
(CLKDIV<11>). The ratio between peripheral and core ters are already configured to enable
clock speed is determined by the DOZE<2:0> bits module operation).
(CLKDIV<14:12>). There are eight possible configu-
rations, from 1:1 to 1:128, with 1:1 being the default
setting.
9.5 Power-Saving Resources
Programs can use Doze mode to selectively reduce Many useful resources are provided on the main prod-
power consumption in event-driven applications. This uct page of the Microchip web site for the devices listed
allows clock-sensitive functions, such as synchronous in this data sheet. This product page contains the latest
communications, to continue without interruption while updates and additional information.
the CPU Idles, waiting for something to invoke an inter-
rupt routine. An automatic return to full-speed CPU 9.5.1 KEY RESOURCES
operation on interrupts can be enabled by setting the • “Watchdog Timer and Power-Saving Modes”
ROI bit (CLKDIV<15>). By default, interrupt events (DS70615) in the “dsPIC33/PIC24 Family
have no effect on Doze mode operation. Reference Manual”
• Code Samples
• Application Notes
• Webinars
• All related “dsPIC33/PIC24 Family Reference
Manual” Sections

REGISTER 9-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
T5MD T4MD T3MD T2MD T1MD — PWMMD —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0

I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADCMD
bit 7 bit 0
Legend:
bit 15 T5MD: Timer5 Module Disable bit

1 = Timer5 module is disabled
0 = Timer5 module is enabled
bit 9 PWMMD: PWMx Module Disable bit
1 = PWMx module is disabled
0 = PWMx module is enabled
bit 7 I2C1MD: I2C1 Module Disable bit
1 = I2C1 module is disabled
0 = I2C1 module is enabled
bit 6 U2MD: UART2 Module Disable bit
1 = UART2 module is disabled
0 = UART2 module is enabled
bit 5 U1MD: UART1 Module Disable bit
1 = UART1 module is disabled
0 = UART1 module is enabled
bit 4 SPI2MD: SPI2 Module Disable bit
1 = SPI2 module is disabled
0 = SPI2 module is enabled
bit 3 SPI1MD: SPI1 Module Disable bit
1 = SPI1 module is disabled
0 = SPI1 module is enabled
bit 0 ADCMD: ADC Module Disable bit
1 = ADC module is disabled
0 = ADC module is enabled

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — IC4MD IC3MD IC2MD IC1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — OC4MD OC3MD OC2MD OC1MD
bit 7 bit 0
Legend:

bit 11 IC4MD: Input Capture 4 Module Disable bit
1 = Input Capture 4 module is disabled
0 = Input Capture 4 module is enabled
bit 3 OC4MD: Output Compare 4 Module Disable bit
1 = Output Compare 4 module is disabled
0 = Output Compare 4 module is enabled

U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0
— — — — — CMPMD — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — I2C2MD —
bit 7 bit 0
Legend:

bit 10 CMPMD: Comparator Module Disable bit
1 = Comparator module is disabled
0 = Comparator module is enabled
bit 1 I2C2MD: I2C2 Module Disable bit
1 = I2C2 module is disabled
0 = I2C2 module is enabled

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0

— — — — REFOMD — — —
bit 7 bit 0
Legend:

bit 3 REFOMD: Reference Clock Module Disable bit
1 = Reference clock module is disabled
0 = Reference clock module is enabled

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:

bit 12 PWM5MD: PWM5 Module Disable bit
1 = PWM5 module is disabled
0 = PWM5 module is enabled

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — CMP4MD CMP3MD CMP2MD CMP1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — PGA1MD —
bit 7 bit 0
Legend:

bit 11 CMP4MD: CMP4 Module Disable bit
1 = CMP4 module is disabled
0 = CMP4 module is enabled
bit 1 PGA1MD: PGA1 Module Disable bit
1 = PGA1 module is disabled
0 = PGA1 module is enabled

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0
— — — — — PGA2MD ABGMD —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — CCSMD —
bit 7 bit 0
Legend:

bit 10 PGA2MD: PGA2 Module Disable bit
1 = PGA2 module is disabled
0 = PGA2 module is enabled
bit 9 ABGMD: Band Gap Reference Voltage Disable bit
1 = Band gap reference voltage is disabled
0 = Band gap reference voltage is enabled
bit 1 CCSMD: Constant-Current Source Module Disable bit
1 = Constant-current source module is disabled
0 = Constant-current source module is enabled

NOTES:

10.0 I/O PORTS the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
Note 1: This data sheet summarizes the features peripheral that shares the same pin. Figure 10-1 illus-
of the dsPIC33EPXXGS50X family of trates how ports are shared with other peripherals and
devices. It is not intended to be a compre- the associated I/O pin to which they are connected.
hensive reference source. To complement When a peripheral is enabled and the peripheral is
the information in this data sheet, refer actively driving an associated pin, the use of the pin as a
to “I/O Ports” (DS70000598) in the general purpose output pin is disabled. The I/O pin can
“dsPIC33/PIC24 Family Reference Man- be read, but the output driver for the parallel port bit is
ual”, which is available from the Microchip disabled. If a peripheral is enabled, but the peripheral is
web site (www.microchip.com). not actively driving a pin, that pin can be driven by a port.
2: Some registers and associated bits All port pins have eight registers directly associated with
described in this section may not be their operation as digital I/Os. The Data Direction register
available on all devices. Refer to (TRISx) determines whether the pin is an input or an out-
Section 4.0 “Memory Organization” in put. If the data direction bit is a ‘1’, then the pin is an input.
this data sheet for device-specific register All port pins are defined as inputs after a Reset. Reads
and bit information. from the latch (LATx), read the latch. Writes to the latch,
Many of the device pins are shared among the peripher- write the latch. Reads from the port (PORTx), read the
als and the Parallel I/O ports. All I/O input ports feature port pins, while writes to the port pins, write the latch.
Schmitt Trigger inputs for improved noise immunity. Any bit and its associated data and control registers
that are not valid for a particular device are disabled.
10.1 Parallel I/O (PIO) Ports This means the corresponding LATx and TRISx
registers, and the port pin are read as zeros.
Generally, a Parallel I/O port that shares a pin with a
When a pin is shared with another peripheral or func-
peripheral is subservient to the peripheral. The
tion that is defined as an input only, it is nevertheless
peripheral’s output buffer data and control signals are
regarded as a dedicated port because there is no
provided to a pair of multiplexers. The multiplexers
other competing source of outputs.
select whether the peripheral or the associated port
has ownership of the output data and control signals of
FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module Output Multiplexers

Peripheral Input Data
Peripheral Module Enable
I/O
Peripheral Output Enable
1 Output Enable
Peripheral Output Data
0
PIO Module 1 Output Data

Read TRISx 0
Data Bus
D Q
I/O Pin
WR TRISx
CK
TRISx Latch
D Q
WR LATx +
CK
WR PORTx
Data Latch
Read LATx
Input Data
Read PORTx

10.1.1 OPEN-DRAIN CONFIGURATION 10.3 Input Change Notification (ICN)
In addition to the PORTx, LATx and TRISx registers The Input Change Notification function of the I/O ports
for data control, port pins can also be individually allows devices to generate interrupt requests to the
configured for either digital or open-drain output. This processor in response to a Change-of-State (COS) on
is controlled by the Open-Drain Control x register, selected input pins. This feature can detect input
ODCx, associated with each port. Setting any of the Change-of-States, even in Sleep mode, when the
bits configures the corresponding pin to act as an clocks are disabled. Every I/O port pin can be selected
open-drain output. (enabled) for generating an interrupt request on a
The open-drain feature allows the generation of out- Change-of-State.
puts other than VDD by using external pull-up resistors. Three control registers are associated with the ICN
The maximum open-drain voltage allowed on any pin functionality of each I/O port. The CNENx registers
is the same as the maximum VIH specification for that contain the ICN interrupt enable control bits for each of
particular pin. the input pins. Setting any of these bits enables an ICN
See the “Pin Diagrams” section for the available interrupt for the corresponding pins.
5V tolerant pins and Table 26-11 for the maximum Each I/O pin also has a weak pull-up and a weak
VIH specification for each pin. pull-down connected to it. The pull-ups and pull-
downs act as a current source, or sink source,
10.2 Configuring Analog and Digital connected to the pin, and eliminate the need for
Port Pins external resistors when push button or keypad
devices are connected. The pull-ups and pull-downs
The ANSELx register controls the operation of the are enabled separately, using the CNPUx and the
analog port pins. The port pins that are to function as CNPDx registers, which contain the control bits for
analog inputs or outputs must have their corresponding each of the pins. Setting any of the control bits
ANSELx and TRISx bits set. In order to use port pins for enables the weak pull-ups and/or pull-downs for the
I/O functionality with digital modules, such as timers, corresponding pins.
UARTs, etc., the corresponding ANSELx bit must be
cleared. Note: Pull-ups and pull-downs on Input Change
Notification pins should always be
The ANSELx register has a default value of 0xFFFF;
disabled when the port pin is configured
therefore, all pins that share analog functions are
as a digital output.
analog (not digital) by default.
Pins with analog functions affected by the ANSELx
EXAMPLE 10-1: PORT WRITE/READ
registers are listed with a buffer type of analog in the
EXAMPLE
Pinout I/O Descriptions (see Table 1-1).
MOV 0xFF00, W0 ; Configure PORTB<15:8>
If the TRISx bit is cleared (output) while the ANSELx bit
; as inputs
is set, the digital output level (VOH or VOL) is converted MOV W0, TRISB ; and PORTB<7:0>
by an analog peripheral, such as the ADC module or ; as outputs
comparator module. NOP ; Delay 1 cycle
When the PORTx register is read, all pins configured as BTSS PORTB, #13 ; Next Instruction
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin, defined as a
digital input (including the ANx pins), can cause the
input buffer to consume current that exceeds the
device specifications.
10.2.1 I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP, as shown in Example 10-1.

10.4 Peripheral Pin Select (PPS) In comparison, some digital only peripheral modules
are never included in the Peripheral Pin Select feature.
A major challenge in general purpose devices is This is because the peripheral’s function requires
providing the largest possible set of peripheral features, special I/O circuitry on a specific port and cannot be
while minimizing the conflict of features on I/O pins. easily connected to multiple pins. One example
The challenge is even greater on low pin count devices. includes I2C modules. A similar requirement excludes
In an application where more than one peripheral all modules with analog inputs, such as the ADC
needs to be assigned to a single pin, inconvenient Converter.
work arounds in application code, or a complete
redesign, may be the only option. A key difference between remappable and non-
remappable peripherals is that remappable peripherals
Peripheral Pin Select configuration provides an alter- are not associated with a default I/O pin. The peripheral
native to these choices by enabling peripheral set must always be assigned to a specific I/O pin before it
selection and placement on a wide range of I/O pins. can be used. In contrast, non-remappable peripherals
By increasing the pinout options available on a particu- are always available on a default pin, assuming that the
lar device, users can better tailor the device to their peripheral is active and not conflicting with another
entire application, rather than trimming the application peripheral.
to fit the device.
When a remappable peripheral is active on a given I/O
The Peripheral Pin Select configuration feature pin, it takes priority over all other digital I/O and digital
operates over a fixed subset of digital I/O pins. Users communication peripherals associated with the pin.
may independently map the input and/or output of most Priority is given regardless of the type of peripheral that
digital peripherals to any one of these I/O pins. Hard- is mapped. Remappable peripherals never take priority
ware safeguards are included that prevent accidental over any analog functions associated with the pin.
or spurious changes to the peripheral mapping once it
has been established. 10.4.3 CONTROLLING PERIPHERAL PIN
SELECT
10.4.1 AVAILABLE PINS
Peripheral Pin Select features are controlled through
The number of available pins is dependent on the par- two sets of SFRs: one to map peripheral inputs and one
ticular device and its pin count. Pins that support the to map outputs. Because they are separately con-
Peripheral Pin Select feature include the label, “RPn”, trolled, a particular peripheral’s input and output (if the
in their full pin designation, where “n” is the remappable peripheral has both) can be placed on any selectable
pin number. “RP” is used to designate pins that support function pin without constraint.
both remappable input and output functions.
The association of a peripheral to a peripheral-
10.4.2 AVAILABLE PERIPHERALS selectable pin is handled in two different ways,
depending on whether an input or output is being
The peripherals managed by the Peripheral Pin Select
mapped.
are all digital only peripherals. These include general
serial communications (UART and SPI), general pur-
pose timer clock inputs, timer-related peripherals (input
capture and output compare) and interrupt-on-change
inputs.

10.4.4 INPUT MAPPING 10.4.4.1 Virtual Connections
The inputs of the Peripheral Pin Select options are The dsPIC33EPXXGS50X devices support six virtual
mapped on the basis of the peripheral. That is, a control RPn pins (RP176-RP181), which are identical in
register associated with a peripheral dictates the pin it functionality to all other RPn pins, with the exception of
will be mapped to. The RPINRx registers are used to pinouts. These six pins are internal to the devices and
configure peripheral input mapping (see Register 10-1 are not connected to a physical device pin.
through Register 10-19). Each register contains sets of These pins provide a simple way for inter-peripheral
8-bit fields, with each set associated with one of the connection without utilizing a physical pin. For
remappable peripherals. Programming a given periph- example, the output of the analog comparator can be
eral’s bit field with an appropriate 8-bit value maps the connected to RP176 and the PWM Fault input can be
RPn pin with the corresponding value to that peripheral. configured for RP176 as well. This configuration allows
For any given device, the valid range of values for any the analog comparator to trigger PWM Faults without
bit field corresponds to the maximum number of the use of an actual physical pin on the device.
Peripheral Pin Selections supported by the device.
For example, Figure 10-2 illustrates remappable pin
selection for the U1RX input.
FIGURE 10-2: REMAPPABLE INPUT FOR

U1RX
U1RXR<7:0>
0
RP0
1
RP1
U1RX Input
2 to Peripheral
RP2
n
RPn
Note: For input only, Peripheral Pin Select func-

tionality does not have priority over TRISx
settings. Therefore, when configuring an
RPn pin for input, the corresponding bit in
the TRISx register must also be configured
for input (set to ‘1’).

TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)
Input Name(1) Function Name Register Configuration Bits
External Interrupt 1 INT1 RPINR0 INT1R<7:0>
External Interrupt 2 INT2 RPINR1 INT2R<7:0>
Timer1 External Clock T1CK RPINR2 T1CKR<7:0>
Input Capture 1 IC1 RPINR7 IC1R<7:0>
Output Compare Fault A OCFA RPINR11 OCFAR<7:0>
PWM Fault 1 FLT1 RPINR12 FLT1R<7:0>
UART1 Receive U1RX RPINR18 U1RXR<7:0>
UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<7:0>
UART2 Receive U2RX RPINR19 U2RXR<7:0>
UART2 Clear-to-Send U2CTS RPINR19 U2CTSR<7:0>
SPI1 Data Input SDI1 RPINR20 SDI1R<7:0>
SPI1 Clock Input SCK1 RPINR20 SCK1R<7:0>
SPI1 Slave Select SS1 RPINR21 SS1R<7:0>
SPI2 Data Input SDI2 RPINR22 SDI2R<7:0>
SPI2 Clock Input SCK2 RPINR22 SCK2R<7:0>
SPI2 Slave Select SS2 RPINR23 SS2R<7:0>
PWM Synch Input 1 SYNCI1 RPINR37 SYNCI1R<7:0>
PWM Synch Input 2 SYNCI2 RPINR38 SYNCI2R<7:0>
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

10.4.5 OUTPUT MAPPING 10.4.5.1 Mapping Limitations
In contrast to inputs, the outputs of the Peripheral Pin The control schema of the peripheral select pins is not
Select options are mapped on the basis of the pin. In limited to a small range of fixed peripheral configura-
this case, a control register associated with a particular tions. There are no mutual or hardware-enforced
pin dictates the peripheral output to be mapped. The lockouts between any of the peripheral mapping SFRs.
RPORx registers are used to control output mapping. Literally any combination of peripheral mappings,
Each register contains sets of 6-bit fields, with each set across any or all of the RPn pins, is possible. This
associated with one RPn pin (see Register 10-20 includes both many-to-one and one-to-many mappings
through Register 10-38). The value of the bit field cor- of peripheral inputs, and outputs to pins. While such
responds to one of the peripherals and that peripheral’s mappings may be technically possible from a configu-
output is mapped to the pin (see Table 10-2 and ration point of view, they may not be supportable from
Figure 10-3). an electrical point of view.
A null output is associated with the output register
Reset value of ‘0’. This is done to ensure that remap-
pable outputs remain disconnected from all output pins
by default.
FIGURE 10-3: MULTIPLEXING REMAPPABLE

OUTPUTS FOR RPn
RPnR<5:0>
Default
0
U1TX Output
1
SDO2 Output
2
RPn
Output Data
PWM5H Output
53
PWM5L Output
54

TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)
Function RPnR<5:0> Output Name
Default PORT 000000 RPn tied to Default Pin
U1TX 000001 RPn tied to UART1 Transmit
U1RTS 000010 RPn tied to UART1 Request-to-Send
U2TX 000011 RPn tied to UART2 Transmit
U2RTS 000100 RPn tied to UART2 Request-to-Send
SDO1 000101 RPn tied to SPI1 Data Output
SCK1 000110 RPn tied to SPI1 Clock Output
SS1 000111 RPn tied to SPI1 Slave Select
SDO2 001000 RPn tied to SPI2 Data Output
SCK2 001001 RPn tied to SPI2 Clock Output
SS2 001010 RPn tied to SPI2 Slave Select
OC1 010000 RPn tied to Output Compare 1 Output
ACMP1 011000 RPn tied to Analog Comparator 1 Output
SYNCO1 101101 RPn tied to PWM Primary Master Time Base Sync Output
SYNCO2 101110 RPn tied to PWM Secondary Master Time Base Sync Output
REFCLKO 110001 RPn tied to Reference Clock Output
PWM4H 110011 RPn tied to PWM Output Pins Associated with PWM Generator 4
PWM4L 110100 RPn tied to PWM Output Pins Associated with PWM Generator 4
PWM5H 110101 RPn tied to PWM Output Pins Associated with PWM Generator 5
PWM5L 110110 RPn tied to PWM Output Pins Associated with PWM Generator 5

10.5 I/O Helpful Tips 3. Most I/O pins have multiple functions. Referring to
the device pin diagrams in this data sheet, the prior-
1. In some cases, certain pins, as defined in
ities of the functions allocated to any pins are
Table 26-11 under “Injection Current”, have inter-
indicated by reading the pin name from left-to-right.
nal protection diodes to VDD and VSS. The term,
The left most function name takes precedence over
“Injection Current”, is also referred to as “Clamp
any function to its right in the naming convention.
Current”. On designated pins, with sufficient exter-
For example: AN16/T2CK/T7CK/RC1; this indi-
nal current-limiting precautions by the user, I/O pin
cates that AN16 is the highest priority in this
input voltages are allowed to be greater or less
example and will supersede all other functions to its
than the data sheet absolute maximum ratings,
right in the list. Those other functions to its right,
with respect to the VSS and VDD supplies. Note
even if enabled, would not work as long as any
that when the user application forward biases
other function to its left was enabled. This rule
either of the high or low side internal input clamp
applies to all of the functions listed for a given pin.
diodes, that the resulting current being injected
into the device, that is clamped internally by the 4. Each pin has an internal weak pull-up resistor and
VDD and VSS power rails, may affect the ADC pull-down resistor that can be configured using the
accuracy by four to six counts. CNPUx and CNPDx registers, respectively. These
resistors eliminate the need for external resistors
2. I/O pins that are shared with any analog input pin
in certain applications. The internal pull-up is up to
(i.e., ANx) are always analog pins by default after
~(VDD – 0.8), not VDD. This value is still above the
any Reset. Consequently, configuring a pin as an
minimum VIH of CMOS and TTL devices.
analog input pin automatically disables the digital
input pin buffer and any attempt to read the digital 5. When driving LEDs directly, the I/O pin can source
input level by reading PORTx or LATx will always or sink more current than what is specified in the
return a ‘0’, regardless of the digital logic level on VOH/IOH and VOL/IOL DC characteristics specifica-
the pin. To use a pin as a digital I/O pin on a shared tion. The respective IOH and IOL current rating only
ANx pin, the user application needs to configure the applies to maintaining the corresponding output at
Analog Pin Configuration registers in the I/O ports or above the VOH, and at or below the VOL levels.
module (i.e., ANSELx) by setting the appropriate bit However, for LEDs, unlike digital inputs of an exter-
that corresponds to that I/O port pin to a ‘0’. nally connected device, they are not governed by
the same minimum VIH/VIL levels. An I/O pin output
Note: Although it is not possible to use a digital can safely sink or source any current less than that
input pin when its analog function is listed in the Absolute Maximum Ratings in
enabled, it is possible to use the digital I/O Section 26.0 “Electrical Characteristics”of this
output function, TRISx = 0x0, while the data sheet. For example:
analog function is also enabled. However, VOH = 2.4v @ IOH = -8 mA and VDD = 3.3V
this is not recommended, particularly if the
The maximum output current sourced by any 8 mA
analog input is connected to an external
I/O pin = 12 mA.
analog voltage source, which would
create signal contention between the LED source current < 12 mA is technically permitted.
analog signal and the output pin driver. Refer to the VOH/IOH graphs in Section 27.0 “DC
and AC Device Characteristics Graphs” for
additional information.

6. The Peripheral Pin Select (PPS) pin mapping rules 10.6 I/O Ports Resources
are as follows:
Many useful resources are provided on the main prod-
a) Only one “output” function can be active on a
uct page of the Microchip web site for the devices listed
given pin at any time, regardless if it is a
in this data sheet. This product page contains the latest
dedicated or remappable function (one pin,
one output).
b) It is possible to assign a “remappable output” 10.6.1 KEY RESOURCES
function to multiple pins and externally short or
tie them together for increased current drive. • “I/O Ports” (DS70000598) in the “dsPIC33/PIC24
Family Reference Manual”
c) If any “dedicated output” function is enabled
on a pin, it will take precedence over any • Code Samples
remappable “output” function. • Application Notes
d) If any “dedicated digital” (input or output) func- • Software Libraries
tion is enabled on a pin, any number of “input” • Webinars
remappable functions can be mapped to the • All Related “dsPIC33/PIC24 Family Reference
same pin. Manual” Sections
e) If any “dedicated analog” function(s) are • Development Tools
enabled on a given pin, “digital input(s)” of any
kind will all be disabled, although a single “dig-
ital output”, at the user’s cautionary discretion,
can be enabled and active as long as there is
no signal contention with an external analog
input signal. For example, it is possible for the
ADC to convert the digital output logic level, or
to toggle a digital output on a comparator or
ADC input, provided there is no external
analog input, such as for a built-in self-test.
f) Any number of “input” remappable functions
can be mapped to the same pin(s) at the same
time, including to any pin with a single output
from either a dedicated or remappable “output”.
g) The TRISx registers control only the digital I/O
output buffer. Any other dedicated or remap-
pable active “output” will automatically override
the TRISx setting. The TRISx register does not
control the digital logic “input” buffer. Remap-
pable digital “inputs” do not automatically
override TRISx settings, which means that the
TRISx bit must be set to input for pins with only
remappable input function(s) assigned.
h) All analog pins are enabled by default after any
Reset and the corresponding digital input buffer
on the pin has been disabled. Only the Analog
Pin Select x (ANSELx) registers control the dig-
ital input buffer, not the TRISx register. The user
must disable the analog function on a pin using
the Analog Pin Select x registers in order to use
any “digital input(s)” on a corresponding pin, no
exceptions.

10.7 Peripheral Pin Select Registers
REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
INT1R7 INT1R6 INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 INT1R<7:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
10110101 = Input tied to RP181
•
•
•
00000000 = Input tied to VSS

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

INT2R7 INT2R6 INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0
bit 7 bit 0
Legend:

bit 7-0 INT2R<7:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits
•
•
•

T1CKR7 T1CKR6 T1CKR5 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 T1CKR<7:0>: Assign Timer1 External Clock (T1CK) to the Corresponding RPn Pin bits
•
•
•

bit 15 bit 8

bit 7 bit 0
Legend:
•
•
•
•
•
•

IC2R7 IC2R6 IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-8 IC2R<7:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits
•
•
•
•
•
•

bit 15 bit 8

bit 7 bit 0
Legend:
•
•
•
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

OCFAR7 OCFAR6 OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0
bit 7 bit 0
Legend:

bit 7-0 OCFAR<7:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits
•
•
•

FLT2R7 FLT2R6 FLT2R5 FLT2R4 FLT2R3 FLT2R2 FLT2R1 FLT2R0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-8 FLT2R<7:0>: Assign PWM Fault 2 (FLT2) to the Corresponding RPn Pin bits
•
•
•
•
•
•

bit 15 bit 8

bit 7 bit 0
Legend:
•
•
•
•
•
•

U1CTSR7 U1CTSR6 U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0
bit 15 bit 8

U1RXR7 U1RXR6 U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0
bit 7 bit 0
Legend:
bit 15-8 U1CTSR<7:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits
•
•
•
bit 7-0 U1RXR<7:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits
•
•
•

U2CTSR7 U2CTSR6 U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0
bit 15 bit 8

U2RXR7 U2RXR6 U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0
bit 7 bit 0
Legend:
bit 15-8 U2CTSR<7:0>: Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn Pin bits
•
•
•
bit 7-0 U2RXR<7:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits
•
•
•

SCK1INR7 SCK1INR6 SCK1INR5 SCK1INR4 SCK1INR3 SCK1INR2 SCK1INR1 SCK1INR0
bit 15 bit 8

SDI1R7 SDI1R6 SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0
bit 7 bit 0
Legend:
bit 15-8 SCK1INR<7:0>: Assign SPI1 Clock Input (SCK1) to the Corresponding RPn Pin bits
•
•
•
bit 7-0 SDI1R<7:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

SS1R7 SS1R6 SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0
bit 7 bit 0
Legend:

bit 7-0 SS1R<7:0>: Assign SPI1 Slave Select (SS1) to the Corresponding RPn Pin bits
•
•
•

SCK2INR7 SCK2INR6 SCK2INR5 SCK2INR4 SCK2INR3 SCK2INR2 SCK2INR1 SCK2INR0
bit 15 bit 8

SDI2R7 SDI2R6 SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0
bit 7 bit 0
Legend:
bit 15-8 SCK2INR<7:0>: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits
•
•
•
bit 7-0 SDI2R<7:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

SS2R7 SS2R6 SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0
bit 7 bit 0
Legend:

bit 7-0 SS2R<7:0>: Assign SPI2 Slave Select (SS2) to the Corresponding RPn Pin bits
•
•
•

SYNCI1R7 SYNCI1R6 SYNCI1R5 SYNCI1R4 SYNCI1R3 SYNCI1R2 SYNCI1R1 SYNCI1R0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 SYNCI1R<7:0>: Assign PWM Synchronization Input 1 to the Corresponding RPn Pin bits
•
•
•

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

SYNCI2R7 SYNCI2R6 SYNCI2R5 SYNCI2R4 SYNCI2R3 SYNCI2R2 SYNCI2R1 SYNCI2R0
bit 7 bit 0
Legend:

bit 7-0 SYNCI2R<7:0>: Assign PWM Synchronization Input 2 to the Corresponding RPn Pin bits
•
•
•

bit 15 bit 8

bit 7 bit 0
Legend:
•
•
•
•
•
•

bit 15 bit 8

bit 7 bit 0
Legend:
•
•
•
•
•
•

REGISTER 10-20: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — RP33R5 RP33R4 RP33R3 RP33R2 RP33R1 RP33R0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:

bit 13-8 RP33R<5:0>: Peripheral Output Function is Assigned to RP33 Output Pin bits
(see Table 10-2 for peripheral function numbers)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0
Legend:


NOTES:

11.0 TIMER1 The Timer1 module can operate in one of the following
modes:
Note 1: This data sheet summarizes the • Timer mode
• Gated Timer mode
family of devices. It is not intended to be
• Synchronous Counter mode
a comprehensive reference source. To
complement the information in this data • Asynchronous Counter mode
sheet, refer to “Timers” (DS70362) in In Timer and Gated Timer modes, the input clock is
the “dsPIC33/PIC24 Family Reference derived from the internal instruction cycle clock (FCY).
Manual”, which is available from the In Synchronous and Asynchronous Counter modes,
Microchip web site (www.microchip.com). the input clock is derived from the external clock input
2: Some registers and associated bits at the T1CK pin.
described in this section may not be The Timer modes are determined by the following bits:
available on all devices. Refer to • Timer Clock Source Control bit (TCS): T1CON<1>
• Timer Synchronization Control bit (TSYNC):
T1CON<2>
• Timer Gate Control bit (TGATE): T1CON<6>
The Timer1 module is a 16-bit timer that can operate as Timer control bit settings for different operating modes
a free-running interval timer/counter. are provided in Table 11-1.
The Timer1 module has the following unique features
over other timers: TABLE 11-1: TIMER MODE SETTINGS
• Can be Operated in Asynchronous Counter mode Mode TCS TGATE TSYNC
from an External Clock Source
Timer 0 0 x
• The External Clock Input (T1CK) can Optionally be
Synchronized to the Internal Device Clock and the Gated Timer 0 1 x
Clock Synchronization is Performed after the Synchronous 1 x 1
Prescaler Counter
A block diagram of Timer1 is shown in Figure 11-1. Asynchronous 1 x 0
Counter
FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Gate Falling Edge

1
Sync Detect
Set T1IF Flag
FP(1) Prescaler 10 T1CLK

(/n) TGATE
Reset Data
00 TMR1 Latch
TCKPS<1:0>
0 CLK ADC Trigger
T1CK x1
Prescaler Equal
Sync 1 Comparator
(/n)
TGATE
TSYNC
TCKPS<1:0> TCS
PR1
Note 1: FP is the peripheral clock.

11.1 Timer1 Resources 11.1.1 KEY RESOURCES
Many useful resources are provided on the main prod- • “Timers” (DS70362) in the “dsPIC33/PIC24
uct page of the Microchip web site for the devices listed Family Reference Manual”
in this data sheet. This product page contains the latest • Code Samples
updates and additional information. • Application Notes
• Webinars
Manual” Sections

11.2 Timer1 Control Register
REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(1) — TSIDL — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

— TGATE TCKPS1 TCKPS0 — TSYNC(1) TCS(1) —
bit 7 bit 0
Legend:
bit 15 TON: Timer1 On bit(1)

1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 13 TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit(1)
When TCS = 1:
1 = Synchronizes external clock input
0 = Does not synchronize external clock input
When TCS = 0:
bit 1 TCS: Timer1 Clock Source Select bit(1)
1 = External clock is from pin, T1CK (on the rising edge)
0 = Internal clock (FP)
Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any
attempts by user software to write to the TMR1 register are ignored.

NOTES:

12.0 TIMER2/3 AND TIMER4/5 Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
Note 1: This data sheet summarizes the features listed previously, except for the event trigger;
features of the dsPIC33EPXXGS50X this is implemented only with Timer2/3. The operating
family of devices. It is not intended to be modes and enabled features are determined by setting
a comprehensive reference source. To the appropriate bit(s) in the T2CON, T3CON, T4CON
complement the information in this data and T5CON registers. T2CON and T4CON are shown
sheet, refer to “Timers” (DS70362) in in generic form in Register 12-1. T3CON and T5CON
the “dsPIC33/PIC24 Family Reference are shown in Register 12-2.
Manual”, which is available from the For 32-bit timer/counter operation, Timer2 and Timer4
Microchip web site (www.microchip.com). are the least significant word (lsw); Timer3 and Timer5
2: Some registers and associated bits are the most significant word (msw) of the 32-bit timers.
Note: For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
The Timer2/3 and Timer4/5 modules are 32-bit timers, modules, but an interrupt is generated
which can also be configured as four independent with the Timer3 and Timer5 interrupt flags.
16-bit timers with selectable operating modes. A block diagram for an example 32-bit timer pair
As 32-bit timers, Timer2/3 and Timer4/5 operate in (Timer2/3 and Timer4/5) is shown in Figure 12-2.
three modes:
• Two Independent 16-Bit Timers (e.g., Timer2 and 12.1 Timer Resources
Timer3) with All 16-Bit Operating modes (except
Many useful resources are provided on the main prod-
Asynchronous Counter mode)
• Single 32-Bit Timer in this data sheet. This product page contains the latest
• Single 32-Bit Synchronous Counter updates and additional information.
They also support these features:
12.1.1 KEY RESOURCES
• Timer Gate Operation
• “Timers” (DS70362) in the “dsPIC33/PIC24
• Selectable Prescaler Settings
Family Reference Manual”
• Timer Operation during Idle and Sleep modes
• Code Samples
• Interrupt on a 32-Bit Period Register Match
• Time Base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
• Webinars
Manual” Sections

FIGURE 12-1: TIMERx BLOCK DIAGRAM (x = 2 THROUGH 5)
Gate Falling Edge

1
Sync Detect
Set TxIF Flag
FP(1) Prescaler 10
TxCLK
(/n) TGATE
Reset Data
00 TMRx Latch
TCKPS<1:0>
CLK
TxCK
Prescaler ADC
Sync x1 Trigger(2)
(/n) Equal
Comparator
TCKPS<1:0> TGATE
TCS
PRx
Note 1: FP is the peripheral clock.

2: The ADC trigger is only available on TMR2.
FIGURE 12-2: TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)
Gate Falling Edge

1
Sync Detect
Set TyIF Flag
PRx PRy
0
TGATE
Equal
Comparator
Data
FP(1) Prescaler 10
(/n) CLK
lsw msw Latch
Reset
00 TMRx TMRy
TCKPS<1:0>
TxCK
Prescaler
Sync x1
(/n)
TMRyHLD
TCKPS<1:0> TGATE
TCS
Data Bus<15:0>
Note 1: Timerx is a Type B timer (x = 2 and 4).

2: Timery is a Type C timer (y = 3 and 5).

12.2 Timer Control Registers
REGISTER 12-1: TxCON: (TIMER2 AND TIMER4) CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON — TSIDL — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

— TGATE TCKPS1 TCKPS0 T32 — TCS(1) —
bit 7 bit 0
Legend:
bit 15 TON: Timerx On bit

When T32 = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When T32 = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 13 TSIDL: Timerx Stop in Idle Mode bit
bit 6 TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
When TCS = 0:
bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 T32: 32-Bit Timer Mode Select bit
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
bit 1 TCS: Timerx Clock Source Select bit(1)
1 = External clock is from pin, TxCK (on the rising edge)
Note 1: The TxCK pin is not available on all devices. Refer to the “Pin Diagrams” section for the available pins.

REGISTER 12-2: TyCON: (TIMER3 AND TIMER5) CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(1) — TSIDL(2) — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0

— TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,3) —
bit 7 bit 0
Legend:
bit 15 TON: Timery On bit(1)

1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 13 TSIDL: Timery Stop in Idle Mode bit(2)
bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
When TCS = 0:
bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 1 TCS: Timery Clock Source Select bit(1,3)
1 = External clock is from pin, TyCK (on the rising edge)
Note 1: When 32-bit operation is enabled (TxCON<3> = 1), these bits have no effect on Timery operation; all timer
functions are set through TxCON.
2: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
3: The TyCK pin is not available on all devices. See the “Pin Diagrams” section for the available pins.

13.0 INPUT CAPTURE • Synchronous and Trigger modes of Output
Compare Operation, with up to 21 User-Selectable
Note 1: This data sheet summarizes the Trigger/Sync Sources Available
features of the dsPIC33EPXXGS50X • A 4-Level FIFO Buffer for Capturing and Holding
family of devices. It is not intended to Timer Values for Several Events
be a comprehensive reference source. • Configurable Interrupt Generation
To complement the information in this
• Up to Six Clock Sources Available for Each Module,
data sheet, refer to “Input Capture”
Driving a Separate Internal 16-Bit Counter
(DS70000352) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip web site 13.1 Input Capture Resources
(www.microchip.com). Many useful resources are provided on the main prod-
2: Some registers and associated bits uct page of the Microchip web site for the devices listed
described in this section may not be in this data sheet. This product page contains the latest
available on all devices. Refer to updates and additional information.
this data sheet for device-specific register 13.1.1 KEY RESOURCES
and bit information. • “Input Capture” (DS70000352) in the “dsPIC33/
PIC24 Family Reference Manual”
The input capture module is useful in applications
requiring frequency (period) and pulse measurements. • Code Samples
The dsPIC33EPXXGS50X family devices support four • Application Notes
input capture channels. • Software Libraries
• Webinars
Key features of the input capture module include:
• Hardware-Configurable for 32-Bit Operation in All Manual” Sections
modes by Cascading Two Adjacent Modules • Development Tools
FIGURE 13-1: INPUT CAPTURE x MODULE BLOCK DIAGRAM
ICM<2:0>
ICI<1:0>
Prescaler Edge Detect Logic Event and Set ICxIF

Counter and Interrupt
1:1/4/16 Clock Synchronizer Logic
ICx Pin
ICTSEL<2:0>
Increment
16
ICx Clock Clock 4-Level FIFO Buffer
ICxTMR
Sources Select 16
Trigger and Trigger and Reset 16

Sync Sources Sync Logic ICxBUF
ICOV, ICBNE System Bus

SYNCSEL<4:0>(1)
Note 1: The trigger/sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for
proper ICx module operation or the trigger/sync source must be changed to another source option.

13.2 Input Capture Registers
REGISTER 13-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
— — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R-0, HC, HS R-0, HC, HS R/W-0 R/W-0 R/W-0
— ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit


bit 13 ICSIDL: Input Capture x Stop in Idle Control bit
1 = Input capture will halt in CPU Idle mode
0 = Input capture will continue to operate in CPU Idle mode
bit 12-10 ICTSEL<2:0>: Input Capture x Timer Select bits
111 = Peripheral clock (FP) is the clock source of the ICx
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of the ICx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the ICx
bit 6-5 ICI<1:0>: Number of Captures per Interrupt Select bits (this field is not used if ICM<2:0> = 001 or 111)
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input capture buffer overflow has occurred
0 = No input capture buffer overflow has occurred
bit 3 ICBNE: Input Capture x Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0 ICM<2:0>: Input Capture x Mode Select bits
111 = Input Capture x functions as an interrupt pin only in CPU Sleep and Idle modes (rising edge
detect only, all other control bits are not applicable)
110 = Unused (module is disabled)
101 = Capture mode, every 16th rising edge (Prescaler Capture mode)
100 = Capture mode, every 4th rising edge (Prescaler Capture mode)
011 = Capture mode, every rising edge (Simple Capture mode)
010 = Capture mode, every falling edge (Simple Capture mode)
001 = Capture mode, every rising and falling edge (Edge Detect mode, ICI<1:0>, is not used in this mode)
000 = Input Capture x is turned off

REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — IC32
bit 15 bit 8
R/W-0 R/W-0, HS U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1

ICTRIG(2) TRIGSTAT(3) — SYNCSEL4(4) SYNCSEL3(4) SYNCSEL2(4) SYNCSEL1(4) SYNCSEL0(4)
bit 7 bit 0
Legend: HS = Hardware Settable bit


bit 8 IC32: Input Capture x 32-Bit Timer Mode Select bit (Cascade mode)
1 = Odd ICx and even ICx form a single 32-bit input capture module(1)
0 = Cascade module operation is disabled
bit 7 ICTRIG: Input Capture x Trigger Operation Select bit(2)
1 = Input source is used to trigger the input capture timer (Trigger mode)
0 = Input source is used to synchronize the input capture timer to a timer of another module
(Synchronization mode)
bit 6 TRIGSTAT: Timer Trigger Status bit(3)
1 = ICxTMR has been triggered and is running
0 = ICxTMR has not been triggered and is being held clear
Note 1: The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits); it can be read, set and
cleared in software.
4: Do not use the ICx module as its own sync or trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.

REGISTER 13-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0 SYNCSEL<4:0>: Input Source Select for Synchronization and Trigger Operation bits(4)
11111 = No sync or trigger source for ICx
11110 = Reserved
11101 = Reserved
11100 = Reserved
11011 = CMP4 module synchronizes or triggers ICx(5)
10111 = Reserved
10110 = Reserved
10101 = Reserved
10100 = Reserved
10011 = IC4 module interrupt synchronizes or triggers ICx
01111 = Timer5 synchronizes or triggers ICx
01101 = Timer3 synchronizes or triggers ICx (default)
01010 = Reserved
01001 = Reserved
01000 = IC4 module synchronizes or triggers ICx
00100 = OC4 module synchronizes or triggers ICx
00000 = No sync or trigger source for ICx
Note 1: The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits); it can be read, set and
cleared in software.
4: Do not use the ICx module as its own sync or trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.

14.0 OUTPUT COMPARE single output pulse, or a sequence of output pulses, by
changing the state of the output pin on the compare
Note 1: This data sheet summarizes the features match events. The output compare module can also
of the dsPIC33EPXXGS50X family of generate interrupts on compare match events.
devices. It is not intended to be a
comprehensive reference source. To 14.1 Output Compare Resources
sheet, refer to “Output Compare with Many useful resources are provided on the main prod-
Dedicated Timer” (DS70005159) in uct page of the Microchip web site for the devices listed
the “dsPIC33/PIC24 Family Reference in this data sheet. This product page contains the latest
Manual”, which is available from the updates and additional information.
Microchip web site (www.microchip.com).
14.1.1 KEY RESOURCES
described in this section may not be • “Output Compare with Dedicated Timer”
available on all devices. Refer to (DS70005159) in the “dsPIC33/PIC24 Family
Section 4.0 “Memory Organization” in Reference Manual”
this data sheet for device-specific register • Code Samples
and bit information. • Application Notes
The output compare module can select one of six
• Webinars
available clock sources for its time base. The module
compares the value of the timer with the value of one or • All Related “dsPIC33/PIC24 Family Reference
two Compare registers, depending on the operating Manual” Sections
mode selected. The state of the output pin changes • Development Tools
when the timer value matches the Compare register
value. The output compare module generates either a
FIGURE 14-1: OUTPUT COMPARE x MODULE BLOCK DIAGRAM
OCxCON1
OCxCON2
OCxR
Rollover/Reset
OCxR Buffer
OCx Pin
Comparator
Increment Match
OCx Clock Clock Event
Sources Select
OCx Output and
OCxTMR
Rollover Fault Logic
Reset
OCFA
Comparator
Match Event Match
Trigger and Event
Trigger and
Sync Sources Sync Logic
OCxRS Buffer
SYNCSEL<4:0> Rollover/Reset
Trigger(1)
OCx Synchronization/Trigger Event
OCxRS
OCx Interrupt
Reset
Note 1: The trigger/sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for
proper OCx module operation or the trigger/sync source must be changed to another source option.

14.2 Output Compare Control Registers
REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
— — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — —
bit 15 bit 8
R/W-0 U-0 U-0 R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0

ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit


bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
bit 12-10 OCTSEL<2:0>: Output Compare x Clock Select bits
111 = Peripheral clock (FP)
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of the OCx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the OCx
bit 7 ENFLTA: Fault A Input Enable bit
1 = Output Compare Fault A input (OCFA) is enabled
0 = Output Compare Fault A input (OCFA) is disabled
bit 4 OCFLTA: PWM Fault A Condition Status bit
1 = PWM Fault A condition on the OCFA pin has occurred
0 = No PWM Fault A condition on the OCFA pin has occurred
bit 3 TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is cleared only by software
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.

REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
bit 2-0 OCM<2:0>: Output Compare x Mode Select bits
111 = Center-Aligned PWM mode: Output is set high when OCxTMR = OCxR and set low when
OCxTMR = OCxRS(1)
110 = Edge-Aligned PWM mode: Output is set high when OCxTMR = 0 and set low when OCxTMR = OCxR(1)
101 = Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously
on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of
OCxR and OCxRS for one cycle
011 = Single Compare mode: Compare event with OCxR, continuously toggles OCx pin
010 = Single Compare Single-Shot mode: Initializes OCx pin high, compare event with OCxR, forces OCx
pin low
001 = Single Compare Single-Shot mode: Initializes OCx pin low, compare event with OCxR, forces OCx
pin high
000 = Output compare channel is disabled
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.

REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
FLTMD FLTOUT FLTTRIEN OCINV — — — OC32
bit 15 bit 8
R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0

OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 7 bit 0
Legend: HS = Hardware Settable bit

bit 15 FLTMD: Fault Mode Select bit

1 = Fault mode is maintained until the Fault source is removed; the corresponding OCFLTA bit is
cleared in software and a new PWMx period starts
0 = Fault mode is maintained until the Fault source is removed and a new PWMx period starts
bit 14 FLTOUT: Fault Out bit
1 = PWMx output is driven high on a Fault
0 = PWMx output is driven low on a Fault
bit 13 FLTTRIEN: Fault Output State Select bit
1 = OCx pin is tri-stated on a Fault condition
0 = OCx pin I/O state is defined by the FLTOUT bit on a Fault condition
bit 12 OCINV: Output Compare x Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
bit 8 OC32: Cascade Two OCx Modules Enable bit (32-bit operation)
1 = Cascade module operation is enabled
0 = Cascade module operation is disabled
bit 7 OCTRIG: Output Compare x Trigger/Sync Select bit
1 = Triggers OCx from the source designated by the SYNCSELx bits
0 = Synchronizes OCx with the source designated by the SYNCSELx bits
bit 6 TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
bit 5 OCTRIS: Output Compare x Output Pin Direction Select bit
1 = OCx is tri-stated
0 = OCx module drives the OCx pin
Note 1: Do not use the OCx module as its own synchronization or trigger source.
2: When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.

REGISTER 14-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits
11111 = OCxRS compare event is used for synchronization
11110 = INT2 pin synchronizes or triggers OCx
11101 = INT1 pin synchronizes or triggers OCx
11100 = Reserved
11011 = CMP4 module synchronizes or triggers OCx
10111 = Reserved
10110 = Reserved
10101 = Reserved
10100 = Reserved
10011 = IC4 input capture interrupt event synchronizes or triggers OCx
01111 = Timer5 synchronizes or triggers OCx
01100 = Timer2 synchronizes or triggers OCx (default)
01010 = Reserved
01001 = Reserved
01000 = IC4 input capture event synchronizes or triggers OCx
00100 = OC4 module synchronizes or triggers OCx(1,2)
00000 = No sync or trigger source for OCx
Note 1: Do not use the OCx module as its own synchronization or trigger source.
2: When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.

NOTES:

15.0 HIGH-SPEED PWM Figure 15-1 conceptualizes the PWM module in a
simplified block diagram. Figure 15-2 illustrates how
Note: This data sheet summarizes the features the module hardware is partitioned for each PWMx
of the dsPIC33EPXXGS50X family of output pair for the Complementary PWM mode.
devices. It is not intended to be a The PWM module contains five PWM generators. The
comprehensive reference source. To module has up to 10 PWMx output pins: PWM1H/
complement the information in this data PWM1L through PWM5H/PWM5L. For complementary
sheet, refer to “High-Speed PWM outputs, these 10 I/O pins are grouped into high/low
Module” (DS70000323) in the “dsPIC33/ pairs.
PIC24 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com).
15.2 Feature Description
The PWM module is designed for applications that
The high-speed PWM module on dsPIC33EPXXGS50X
require:
devices supports a wide variety of PWM modes and
output formats. This PWM module is ideal for power • High resolution at high PWM frequencies
conversion applications, such as: • The ability to drive Standard, Edge-Aligned,
• AC/DC Converters Center-Aligned Complementary mode and
Push-Pull mode outputs
• DC/DC Converters
• The ability to create multiphase PWM outputs
• Power Factor Correction
• Uninterruptible Power Supply (UPS) Two common, medium power converter topologies are
push-pull and half-bridge. These designs require the
• Inverters
PWM output signal to be switched between alternate
• Battery Chargers pins, as provided by the Push-Pull PWM mode.
• Digital Lighting
Phase-shifted PWM describes the situation where
each PWM generator provides outputs, but the phase
15.1 Features Overview relationship between the generator outputs is
The high-speed PWM module incorporates the specifiable and changeable.
following features: Multiphase PWM is often used to improve DC/DC
• Five PWMx Generators with Two Outputs converter load transient response, and reduce the size
per Generator of output filter capacitors and inductors. Multiple DC/DC
converters are often operated in parallel, but phase
• Two Master Time Base Modules
shifted in time. A single PWM output, operating at
• Individual Time Base and Duty Cycle for 250 kHz, has a period of 4 s but an array of four PWM
Each PWM Output channels, staggered by 1 s each, yields an effective
• Duty Cycle, Dead Time, Phase Shift and a switching frequency of 1 MHz. Multiphase PWM
Frequency Resolution of 1.04 ns applications typically use a fixed-phase relationship.
• Independent Fault and Current-Limit Inputs Variable phase PWM is useful in Zero Voltage
• Redundant Output Transition (ZVT) power converters. Here, the PWM
• True Independent Output duty cycle is always 50% and the power flow is
• Center-Aligned PWM mode controlled by varying the relative phase shift between
the two PWM generators.
• Output Override Control
• Chop mode (also known as Gated mode)
• Special Event Trigger
• Dual Trigger from PWMx to Analog-to-Digital
Converter (ADC)
• PWMxL and PWMxH Output Pin Swapping
• Independent PWMx Frequency, Duty Cycle and
Phase-Shift Changes
• Enhanced Leading-Edge Blanking (LEB) Functionality
• PWM Capture Functionality
Note: Duty cycle, dead time, phase shift and
frequency resolution is 8.32 ns in
Center-Aligned PWM mode.

15.2.1 WRITE-PROTECTED REGISTERS To gain write access to these locked registers, the user
application must write two consecutive values (0xABCD
On dsPIC33EPXXGS50X family devices, write protection
and 0x4321) to the PWMKEY register to perform the
is implemented for the IOCONx and FCLCONx registers.
unlock operation. The write access to the IOCONx or
The write protection feature prevents any inadvertent
FCLCONx registers must be the next SFR access
writes to these registers. This protection feature can be
following the unlock process. There can be no other SFR
controlled by the PWMLOCK Configuration bit
accesses during the unlock process and subsequent
(FDEVOPT<0>). The default state of the write protection
write access. To write to both the IOCONx and
feature is enabled (PWMLOCK = 1). The write protection
FCLCONx registers requires two unlock operations.
feature can be disabled by configuring PWMLOCK = 0.
The correct unlocking sequence is described in
Example 15-1.
EXAMPLE 15-1: PWM WRITE-PROTECTED REGISTER UNLOCK SEQUENCE

; Writing to FCLCON1 register requires unlock sequence
mov #0xabcd, w10 ; Load first unlock key to w10 register

mov #0x4321, w11 ; Load second unlock key to w11 register
mov #0x0000, w0 ; Load desired value of FCLCON1 register in w0
mov w10, PWMKEY ; Write first unlock key to PWMKEY register
mov w11, PWMKEY ; Write second unlock key to PWMKEY register
mov w0, FCLCON1 ; Write desired value to FCLCON1 register
; Set PWM ownership and polarity using the IOCON1 register

; Writing to IOCON1 register requires unlock sequence
mov #0xabcd, w10 ; Load first unlock key to w10 register

mov #0x4321, w11 ; Load second unlock key to w11 register
mov #0xF000, w0 ; Load desired value of IOCON1 register in w0
mov w10, PWMKEY ; Write first unlock key to PWMKEY register
mov w11, PWMKEY ; Write second unlock key to PWMKEY register
mov w0, IOCON1 ; Write desired value to IOCON1 register
15.3 PWM Resources 15.3.1 KEY RESOURCES

uct page of the Microchip web site for the devices listed • Application Notes
Manual” Sections

FIGURE 15-1: HIGH-SPEED PWM MODULE ARCHITECTURAL DIAGRAM
SYNCI1/SYNCI2
Data Bus
Primary and Secondary

Master Time Base
SYNCO1/SYNCO2
Synchronization Signal
PWM1 Interrupt
PWM1H
PWM
Generator 1
PWM1L
Fault, Current Limit
PWM2 Interrupt
PWM2H
PWM
Generator 2
CPU PWM2L
Fault, Current Limit
PWM3 through PWM4
PWM5 Interrupt PWM5H

PWM
Generator 5
PWM5L
Primary Trigger
Secondary Trigger
ADC Module Fault and
Current Limit
Special Event Trigger

FIGURE 15-2: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF THE HIGH-SPEED PWM
PTCON, PTCON2 Module Control and Timing

STCON, STCON2 SYNCI1 SYNCI2
PWMKEY
PTPER SEVTCMP Special Event Compare Trigger SYNCO1
Comparator Special Event

Comparator Postscaler Special Event Trigger
Master Time Base Counter
Clock
PMTMR Prescaler Primary Master Time Base
SYNCO2
STPER SEVTCMP Special Event Compare Trigger
Special Event
Comparator Comparator
Postscaler Special Event Trigger
Master Time Base Counter

Clock
SMTMR Prescaler Secondary Master Time Base
MDC Master Duty Cycle Register

Synchronization
Master Duty Cycle
16-Bit Data Bus
PDCx PWMx Generator 1
MUX
Master Period
Comparator PWMx Output Mode

PWMCAPx Control Logic
ADC Trigger User Override Logic

Dead-Time Pin
PTMRx Control PWM1H
Current-Limit Logic
Comparator Logic
Override Logic PWM1L
PHASEx
TRIGx Fault Override Logic
SDCx
Secondary PWMx
MUX
Interrupt Fault and

Comparator Current-Limit
Logic FLTx
Logic
ADC Trigger
STMRx
Comparator
Synchronization
SPHASEx
STRIGx FCLCONx IOCONx ALTDTRx
Master Duty Cycle
PWMCONx
Master Period
AUXCONx TRGCONx LEBCONx DTRx
PWMxH
PWMx Generator 2 – PWMx Generator 5 PWMxL
FLTx

REGISTER 15-1: PTCON: PWMx TIME BASE CONTROL REGISTER
R/W-0 U-0 R/W-0 R-0, HSC R/W-0 R/W-0 R/W-0 R/W-0
(1) (1)
PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN(1)
bit 15 bit 8

(1) (1) (1) (1) (1) (1) (1)
SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0(1)
bit 7 bit 0

bit 15 PTEN: PWMx Module Enable bit

1 = PWMx module is enabled
0 = PWMx module is disabled
bit 13 PTSIDL: PWMx Time Base Stop in Idle Mode bit
1 = PWMx time base halts in CPU Idle mode
0 = PWMx time base runs in CPU Idle mode
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWMx cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit(1)
1 = SYNCIx/SYNCO1 polarity is inverted (active-low)
0 = SYNCIx/SYNCO1 is active-high
bit 8 SYNCOEN: Primary Time Base Synchronization Enable bit(1)
1 = SYNCO1 output is enabled
0 = SYNCO1 output is disabled
bit 7 SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1)
111 = Reserved
101 = Reserved
100 = Reserved
011 = Reserved
010 = Reserved
001 = SYNCI2
000 = SYNCI1
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.

REGISTER 15-1: PTCON: PWMx TIME BASE CONTROL REGISTER (CONTINUED)
bit 3-0 SEVTPS<3:0>: PWMx Special Event Trigger Output Postscaler Select bits(1)
1111 = 1:16 Postscaler generates a Special Event Trigger on every sixteenth compare match event
•
•
•
0001 = 1:2 Postscaler generates a Special Event Trigger on every second compare match event
0000 = 1:1 Postscaler generates a Special Event Trigger on every compare match event
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
REGISTER 15-2: PTCON2: PWMx CLOCK DIVIDER SELECT REGISTER 2

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>(1)
bit 7 bit 0
Legend:

bit 2-0 PCLKDIV<2:0>: PWMx Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64, maximum PWM timing resolution
000 = Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.

REGISTER 15-3: PTPER: PWMx PRIMARY MASTER TIME BASE PERIOD REGISTER(1,2)
PTPER<15:8>
bit 15 bit 8

PTPER<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits
Note 1: The PWMx time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.
2: Any period value that is less than 0x0028 must have the Least Significant 3 bits set to ‘0’, thus yielding a
period resolution at 8.32 ns (at fastest auxiliary clock rate).
REGISTER 15-4: SEVTCMP: PWMx SPECIAL EVENT COMPARE REGISTER(1)

SEVTCMP<12:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

SEVTCMP<4:0> — — —
bit 7 bit 0
Legend:
bit 15-3 SEVTCMP<12:0>: Special Event Compare Count Value bits

Note 1: One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SEVTCMP resolution is 8.32 ns.

REGISTER 15-5: STCON: PWMx SECONDARY MASTER TIME BASE CONTROL REGISTER
U-0 U-0 U-0 R-0, HSC R/W-0 R/W-0 R/W-0 R/W-0
— — — SESTAT SEIEN EIPU(1) SYNCPOL SYNCOEN
bit 15 bit 8

SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0
bit 7 bit 0


bit 12 SESTAT: Special Event Interrupt Status bit
1 = Secondary special event interrupt is pending
0 = Secondary special event interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Secondary special event interrupt is enabled
0 = Secondary special event interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(1)
1 = Active Secondary Period register is updated immediately
0 = Active Secondary Period register updates occur on PWMx cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCIx/SYNCO2 polarity is inverted (active-low)
0 = SYNCIx/SYNCO2 polarity is active-high
bit 8 SYNCOEN: Secondary Master Time Base Synchronization Enable bit
1 = SYNCO2 output is enabled
0 = SYNCO2 output is disabled
bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit
1 = External synchronization of secondary time base is enabled
0 = External synchronization of secondary time base is disabled
bit 6-4 SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits
111 = Reserved
101 = Reserved
100 = Reserved
011 = Reserved
010 = Reserved
001 = SYNCI2
000 = SYNCI1
bit 3-0 SEVTPS<3:0>: PWMx Secondary Special Event Trigger Output Postscaler Select bits
1111 = 1:16 Postcale
0001 = 1:2 Postcale
•
•
•
0000 = 1:1 Postscale
Note 1: This bit only applies to the secondary master time base period.

REGISTER 15-6: STCON2: PWMx SECONDARY CLOCK DIVIDER SELECT REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>(1)
bit 7 bit 0
Legend:

bit 2-0 PCLKDIV<2:0>: PWMx Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
000 = Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
REGISTER 15-7: STPER: PWMx SECONDARY MASTER TIME BASE PERIOD REGISTER(1,2)
STPER<15:8>
bit 15 bit 8

STPER<7:0>
bit 7 bit 0
Legend:
bit 15-0 STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits
Note 1: The PWMx time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.
2: Any period value that is less than 0x0028 must have the Least Significant 3 bits set to ‘0’, thus yielding a
period resolution at 8.32 ns (at fastest auxiliary clock rate).

REGISTER 15-8: SSEVTCMP: PWMx SECONDARY SPECIAL EVENT COMPARE REGISTER(1)
SSEVTCMP<12:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

SSEVTCMP<4:0> — — —
bit 7 bit 0
Legend:
bit 15-3 SSEVTCMP<12:0>: Special Event Compare Count Value bits

Note 1: One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SEVTCMP resolution is 8.32 ns.
REGISTER 15-9: CHOP: PWMx CHOP CLOCK GENERATOR REGISTER(1)

R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
CHPCLKEN — — — — — CHOPCLK6 CHOPCLK5
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0 — — —
bit 7 bit 0
Legend:
bit 15 CHPCLKEN: Enable Chop Clock Generator bit

1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 9-3 CHOPCLK<6:0>: Chop Clock Divider bits
Value is in 8.32 ns increments. The frequency of the chop clock signal is given by:
Chop Frequency = 1/(16.64 * (CHOP<7:3> + 1) * Primary Master PWM Input Clock Period)
Note 1: The chop clock generator operates with the primary PWMx clock prescaler (PCLKDIV<2:0>) in the
PTCON2 register (Register 15-2).

REGISTER 15-10: MDC: PWMx MASTER DUTY CYCLE REGISTER(1,2)
MDC<15:8>
bit 15 bit 8

MDC<7:0>
bit 7 bit 0
Legend:
bit 15-0 MDC<15:0>: PWMx Master Duty Cycle Value bits
Note 1: The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
2: As the duty cycle gets closer to 0% or 100% of the PWMx period (0 to 40 ns, depending on the mode of
operation), PWMx duty cycle resolution will increase from 1 to 3 LSBs.
REGISTER 15-11: PWMKEY: PWMx PROTECTION LOCK/UNLOCK KEY REGISTER

PWMKEY<15:8>
bit 15 bit 8

PWMKEY<7:0>
bit 7 bit 0
Legend:
bit 15-0 PWMKEY<15:0>: PWMx Protection Lock/Unlock Key Value bits

REGISTER 15-12: PWMCONx: PWMx CONTROL REGISTER (x = 1 to 5)
R-0, HSC R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSTAT(1) CLSTAT(1) TRGSTAT FLTIEN CLIEN TRGIEN ITB(3) MDCS(3)
bit 15 bit 8
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

DTC1 DTC0 — — MTBS CAM(2,3,4) XPRES(5) IUE
bit 7 bit 0

bit 15 FLTSTAT: Fault Interrupt Status bit(1)

1 = Fault interrupt is pending
0 = No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
bit 14 CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
bit 13 TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
bit 12 FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11 CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared
bit 10 TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9 ITB: Independent Time Base Mode bit(3)
1 = PHASEx/SPHASEx registers provide the time base period for this PWMx generator
0 = PTPER register provides timing for this PWMx generator
bit 8 MDCS: Master Duty Cycle Register Select bit(3)
1 = MDC register provides duty cycle information for this PWMx generator
0 = PDCx and SDCx registers provide duty cycle information for this PWMx generator
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should not be changed after the PWMx is enabled by setting PTEN = 1 (PTCON<15>).
4: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
5: Configure CLMOD = 0 (FCLCONx<8>) and ITB = 1 (PWMCONx<9>) to operate in External Period
Reset mode.

REGISTER 15-12: PWMCONx: PWMx CONTROL REGISTER (x = 1 to 5) (CONTINUED)
bit 7-6 DTC<1:0>: Dead-Time Control bits
11 = Reserved
10 = Dead-time function is disabled
01 = Negative dead time is actively applied for Complementary Output mode
00 = Positive dead time is actively applied for all Output modes
bit 3 MTBS: Master Time Base Select bit
1 = PWMx generator uses the secondary master time base for synchronization and the clock source
for the PWMx generation logic (if secondary time base is available)
0 = PWMx generator uses the primary master time base for synchronization and the clock source for
the PWMx generation logic
bit 2 CAM: Center-Aligned Mode Enable bit(2,3,4)
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
bit 1 XPRES: External PWMx Reset Control bit(5)
1 = Current-limit source resets the time base for this PWMx generator if it is in Independent Time Base
mode
0 = External pins do not affect the PWMx time base
bit 0 IUE: Immediate Update Enable bit
1 = Updates to the active Duty Cycle, Phase Offset, Dead-Time and local Time Base Period registers
are immediate
0 = Updates to the active Duty Cycle, Phase Offset, Dead-Time and local Time Base Period registers
are synchronized to the local PWMx time base
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should not be changed after the PWMx is enabled by setting PTEN = 1 (PTCON<15>).
4: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
5: Configure CLMOD = 0 (FCLCONx<8>) and ITB = 1 (PWMCONx<9>) to operate in External Period
Reset mode.

REGISTER 15-13: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER (x = 1 to 5)(1,2,3)
PDCx<15:8>
bit 15 bit 8

PDCx<7:0>
bit 7 bit 0
Legend:
bit 15-0 PDCx<15:0>: PWMx Generator Duty Cycle Value bits
Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In the
Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both
the PWMxH and PWMxL.
2: The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,
REGISTER 15-14: SDCx: PWMx SECONDARY DUTY CYCLE REGISTER (x = 1 to 5)(1,2,3)

SDCx<15:8>
bit 15 bit 8

SDCx<7:0>
bit 7 bit 0
Legend:
bit 15-0 SDCx<15:0>: PWMx Secondary Duty Cycle for PWMxL Output Pin bits
Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the
SDCx register controls the PWMxL duty cycle.
2: The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,

REGISTER 15-15: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER (x = 1 to 5)(1,2)
PHASEx<15:8>
bit 15 bit 8

PHASEx<7:0>
bit 7 bit 0
Legend:
bit 15-0 PHASEx<15:0>: PWMx Phase-Shift Value or Independent Time Base Period for the PWMx Generator bits
Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation:

• Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01 or 10);
PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs
• True Independent Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Phase-shift value for
PWMxH only
• When the PHASEx/SPHASEx registers provide the phase shift with respect to the master time base;
therefore, the valid range is 0x0000 through period
2: If PWMCONx<9> = 1, the following applies based on the mode of operation:
• Complementary, Redundant, and Push-Pull Output mode (IOCONx<11:10> = 00, 01 or 10);
PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL
• True Independent Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Independent time base
period value for PWMxH only
• When the PHASEx/SPHASEx registers provide the local period, the valid range is 0x0000 through
0xFFF8

REGISTER 15-16: SPHASEx: PWMx SECONDARY PHASE-SHIFT REGISTER (x = 1 to 5)(1,2)
SPHASEx<15:8>
bit 15 bit 8

SPHASEx<7:0>
bit 7 bit 0
Legend:
bit 15-0 SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits
(used in Independent PWM mode only)
Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation:

SPHASEx<15:0> = Not used
• True Independent Output mode (IOCONx<11:10> = 11), PHASEx<15:0> = Phase-shift value for
PWMxL only
2: If PWMCONx<9> = 1, the following applies based on the mode of operation:
SPHASEx<15:0> = Not used
• True Independent Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Independent time base
period value for PWMxL only
• When the PHASEx/SPHASEx registers provide the local period, the valid range of values is
0x0010-0xFFF8

REGISTER 15-17: DTRx: PWMx DEAD-TIME REGISTER (x = 1 to 5)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DTRx<13:8>
bit 15 bit 8

DTRx<7:0>
bit 7 bit 0
Legend:

bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
REGISTER 15-18: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER (x = 1 to 5)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — ALTDTRx<13:8>
bit 15 bit 8

ALTDTRx<7:0>
bit 7 bit 0
Legend:

bit 13-0 ALTDTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits

REGISTER 15-19: TRGCONx: PWMx TRIGGER CONTROL REGISTER (x = 1 to 5)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — —
bit 15 bit 8

DTM(1) — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
bit 7 bit 0
Legend:
bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits

1111 = Trigger output for every 16th trigger event
0010 = Trigger output for every 3rd trigger event
0001 = Trigger output for every 2nd trigger event
0000 = Trigger output for every trigger event
bit 7 DTM: Dual Trigger Mode bit(1)
1 = Secondary trigger event is combined with the primary trigger event to create a PWM trigger
0 = Secondary trigger event is not combined with the primary trigger event to create a PWM trigger;
two separate PWM triggers are generated
bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits
111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000001 = Wait 1 PWM cycle before generating the first trigger event after the module is enabled
Note 1: The secondary PWMx generator cannot generate PWM trigger interrupts.

REGISTER 15-20: IOCONx: PWMx I/O CONTROL REGISTER (x = 1 to 5)
(1) (1)
PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL
bit 15 bit 8

(2) FLTDAT0(2) CLDAT1(2) CLDAT0(2)
OVRDAT1 OVRDAT0 FLTDAT1 SWAP OSYNC
bit 7 bit 0
Legend:
bit 15 PENH: PWMxH Output Pin Ownership bit

1 = PWMx module controls the PWMxH pin
0 = GPIO module controls the PWMxH pin
bit 14 PENL: PWMxL Output Pin Ownership bit
1 = PWMx module controls the PWMxL pin
0 = GPIO module controls the PWMxL pin
bit 13 POLH: PWMxH Output Pin Polarity bit
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
bit 12 POLL: PWMxL Output Pin Polarity bit
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
bit 11-10 PMOD<1:0>: PWMx I/O Pin Mode bits(1)
11 = PWMx I/O pin pair is in the True Independent Output mode
10 = PWMx I/O pin pair is in the Push-Pull Output mode
01 = PWMx I/O pin pair is in the Redundant Output mode
00 = PWMx I/O pin pair is in the Complementary Output mode
bit 9 OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT1 provides data for output on the PWMxH pin
0 = PWMx generator provides data for the PWMxH pin
bit 8 OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT0 provides data for output on the PWMxL pin
0 = PWMx generator provides data for the PWMxL pin
bit 7-6 OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits
If OVERENH = 1, OVRDAT1 provides data for the PWMxH pin
If OVERENL = 1, OVRDAT0 provides data for the PWMxL pin
bit 5-4 FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD<1:0> are Enabled bits(2)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault Mode:
If Fault is active, then FLTDAT1 provides the state for the PWMxH pin.
If Fault is active, then FLTDAT0 provides the state for the PWMxL pin.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault Mode:
If current limit is active, then FLTDAT1 provides the state for the PWMxH pin.
If Fault is active, then FLTDAT0 provides the state for the PWMxL pin.
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.

REGISTER 15-20: IOCONx: PWMx I/O CONTROL REGISTER (x = 1 to 5) (CONTINUED)
bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits(2)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault Mode:
If current limit is active, then CLDAT1 provides the state for the PWMxH pin.
If current limit is active, then CLDAT0 provides the state for the PWMxL pin.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault Mode:
CLDAT<1:0> bits are ignored.
bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to the PWMxL pins; PWMxL output signal is connected to the
PWMxH pins
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0 OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWMx time base
0 = Output overrides via the OVRDAT<1:0> bits occur on the next CPU clock boundary
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.
REGISTER 15-21: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER (x = 1 to 5)

TRGCMP<12:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

TRGCMP<4:0> — — —
bit 7 bit 0
Legend:
bit 15-3 TRGCMP<12:0>: Trigger Compare Value bits

When the primary PWMx functions in the local time base, this register contains the compare values
that can trigger the ADC module.

REGISTER 15-22: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
(x = 1 to 5)
IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL(1) CLMOD
bit 15 bit 8

FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL(1) FLTMOD1 FLTMOD0
bit 7 bit 0
Legend:
bit 15 IFLTMOD: Independent Fault Mode Enable bit

1 = Independent Fault mode: Current-limit input maps FLTDAT1 to the PWMxH output and the Fault
input maps FLTDAT0 to the PWMxL output; the CLDAT<1:0> bits are not used for override functions
0 = Normal Fault mode: Current-Limit mode maps CLDAT<1:0> bits to the PWMxH and PWMxL
outputs; the PWM Fault mode maps FLTDAT<1:0> to the PWMxH and PWMxL outputs
bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWMx Generator bits
11111 = Reserved
10001 = Reserved
10000 = Analog Comparator 4
01100 = Fault 12
01011 = Fault 11
01010 = Fault 10
01001 = Fault 9
01000 = Fault 8
00111 = Fault 7
00110 = Fault 6
00101 = Fault 5
00100 = Fault 4
00011 = Fault 3
00010 = Fault 2
00001 = Fault 1
00000 = Reserved
bit 9 CLPOL: Current-Limit Polarity for PWMx Generator bit(1)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
bit 8 CLMOD: Current-Limit Mode Enable for PWMx Generator bit
1 = Current-Limit mode is enabled
0 = Current-Limit mode is disabled
Note 1: These bits should be changed only when PTEN = 0 (PTCON<15>).

REGISTER 15-22: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
(x = 1 to 5) (CONTINUED)
bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWMx Generator bits
11111 = Fault 31 (Default)
10001 = Reserved
01100 = Fault 12
01011 = Fault 11
01010 = Fault 10
01001 = Fault 9
01000 = Fault 8
00111 = Fault 7
00110 = Fault 6
00101 = Fault 5
00100 = Fault 4
00011 = Fault 3
00010 = Fault 2
00001 = Fault 1
00000 = Reserved
bit 2 FLTPOL: Fault Polarity for PWMx Generator bit(1)
1 = The selected Fault source is active-low
0 = The selected Fault source is active-high
bit 1-0 FLTMOD<1:0>: Fault Mode for PWMx Generator bits
11 = Fault input is disabled
10 = Reserved
01 = The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (cycle)
00 = The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (latched condition)
Note 1: These bits should be changed only when PTEN = 0 (PTCON<15>).
REGISTER 15-23: STRIGx: PWMx SECONDARY TRIGGER COMPARE VALUE REGISTER (x = 1 to 5)(1)
STRGCMP<12:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

STRGCMP<4:0> — — —
bit 7 bit 0
Legend:
bit 15-3 STRGCMP<12:0>: Secondary Trigger Compare Value bits

When the secondary PWMx functions in the local time base, this register contains the compare values
that can trigger the ADC module.
Note 1: STRIGx cannot generate the PWM trigger interrupts.

REGISTER 15-24: LEBCONx: PWMx LEADING-EDGE BLANKING (LEB) CONTROL REGISTER
(x = 1 to 5)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
PHR PHF PLR PLF FLTLEBEN CLLEBEN — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1) (1)
— — BCH BCL BPHH BPHL BPLH BPLL
bit 7 bit 0
Legend:
bit 15 PHR: PWMxH Rising Edge Trigger Enable bit

1 = Rising edge of PWMxH will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the rising edge of PWMxH
bit 14 PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the falling edge of PWMxH
bit 13 PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the rising edge of PWMxL
bit 12 PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the falling edge of PWMxL
bit 11 FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to the selected Fault input
0 = Leading-Edge Blanking is not applied to the selected Fault input
bit 10 CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to the selected current-limit input
0 = Leading-Edge Blanking is not applied to the selected current-limit input
bit 5 BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when the selected blanking signal is high
0 = No blanking when the selected blanking signal is high
bit 4 BCL: Blanking in Selected Blanking Signal Low Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when the selected blanking signal is low
0 = No blanking when the selected blanking signal is low
bit 3 BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxH output is high
0 = No blanking when the PWMxH output is high
bit 2 BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxH output is low
0 = No blanking when the PWMxH output is low
Note 1: The blanking signal is selected via the BLANKSEL<3:0> bits in the AUXCONx register.

REGISTER 15-24: LEBCONx: PWMx LEADING-EDGE BLANKING (LEB) CONTROL REGISTER
bit 1 BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxL output is high
0 = No blanking when the PWMxL output is high
bit 0 BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxL output is low
0 = No blanking when the PWMxL output is low
Note 1: The blanking signal is selected via the BLANKSEL<3:0> bits in the AUXCONx register.
REGISTER 15-25: LEBDLYx: PWMx LEADING-EDGE BLANKING DELAY REGISTER (x = 1 to 5)

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — LEB<8:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

LEB<4:0> — — —
bit 7 bit 0
Legend:

bit 11-3 LEB<8:0>: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits
The value is in 8.32 ns increments.

REGISTER 15-26: AUXCONx: PWMx AUXILIARY CONTROL REGISTER (x = 1 to 5)
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
bit 7 bit 0
Legend:
bit 15 HRPDIS: High-Resolution PWMx Period Disable bit

1 = High-resolution PWMx period is disabled to reduce power consumption
0 = High-resolution PWMx period is enabled
bit 14 HRDDIS: High-Resolution PWMx Duty Cycle Disable bit
1 = High-resolution PWMx duty cycle is disabled to reduce power consumption
0 = High-resolution PWMx duty cycle is enabled
bit 11-8 BLANKSEL<3:0>: PWMx State Blank Source Select bits
The selected state blank signal will block the current-limit and/or Fault input signals (if enabled via the
BCH and BCL bits in the LEBCONx register).
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM5H is selected as the state blank source
0000 = No state blanking
bit 5-2 CHOPSEL<3:0>: PWMx Chop Clock Source Select bits
The selected signal will enable and disable (chop) the selected PWMx outputs.
1001 = Reserved
1000 = Reserved
0111 = Reserved
0110 = Reserved
0101 = PWM5H is selected as the chop clock source
0000 = Chop clock generator is selected as the chop clock source
bit 1 CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled
0 = PWMxH chopping function is disabled
bit 0 CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled
0 = PWMxL chopping function is disabled

REGISTER 15-27: PWMCAPx: PWMx PRIMARY TIME BASE CAPTURE REGISTER (x = 1 to 5)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
PWMCAP<12:5>(1,2,3,4)
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 U-0 U-0 U-0

PWMCAP<4:0>(1,2,3,4) — — —
bit 7 bit 0
Legend:
bit 15-3 PWMCAP<12:0>: PWMx Primary Time Base Capture Value bits(1,2,3,4)
The value in this register represents the captured PWMx time base value when a leading edge is
detected on the current-limit input.
Note 1: The capture feature is only available on a primary output (PWMxH).

2: This feature is active only after LEB processing on the current-limit input signal is complete.
3: The minimum capture resolution is 8.32 ns.
4: This feature can be used when the XPRES bit (PWMCONx<1>) is set to ‘0’.

16.0 SERIAL PERIPHERAL The dsPIC33EPXXGS50X device family offers two SPI
modules on a single device. These modules, which are
INTERFACE (SPI)
designated as SPI1 and SPI2, are functionally identical.
Note 1: This data sheet summarizes the Note: In this section, the SPI modules are
features of the dsPIC33EPXXGS50X referred to together as SPIx, or separately
family of devices. It is not intended to be as SPI1 and SPI2. Special Function
a comprehensive reference source. To Registers follow a similar notation. For
complement the information in this data example, SPIxCON refers to the control
sheet, refer to “Serial Peripheral register for the SPI1 and SPI2 modules.
Interface (SPI)” (DS70005185) in the
“dsPIC33/PIC24 Family Reference Man- The SPIx module takes advantage of the Peripheral
ual”, which is available from the Microchip Pin Select (PPS) feature to allow for greater flexibility in
web site (www.microchip.com). pin configuration.
2: Some registers and associated bits The SPIx serial interface consists of four pins, as follows:
described in this section may not be • SDIx: Serial Data Input
available on all devices. Refer to • SDOx: Serial Data Output
• SCKx: Shift Clock Input or Output
and bit information. • SSx/FSYNCx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPI module is a synchronous serial interface, The SPIx module can be configured to operate with
useful for communicating with other peripherals or two, three or four pins. In 3-Pin mode, SSx is not used.
microcontroller devices. These peripheral devices can In 2-Pin mode, neither SDOx nor SSx is used.
be serial EEPROMs, shift registers, display drivers,
ADC Converters, etc. The SPI module is compatible Figure 16-1 illustrates the block diagram of the SPIx
with Motorola® SPI and SIOP interfaces. module in Standard and Enhanced modes.
FIGURE 16-1: SPIx MODULE BLOCK DIAGRAM
SCKx 1:1 to 1:8 1:1/4/16/64

Secondary Primary FP
Prescaler Prescaler
SSx/FSYNCx
Sync Control Select
Control Clock Edge
SPIxCON1<1:0>
SDOx Shift Control SPIxCON1<4:2>
Enable
Master Clock
SDIx bit 0
SPIxSR
Transfer Transfer
8-Level FIFO 8-Level FIFO

Receive Buffer(1) Transmit Buffer(1)
SPIxBUF
Read SPIxBUF Write SPIxBUF
16
Internal Data Bus
Note 1: In Standard mode, the FIFO is only one-level deep.

16.1 SPI Helpful Tips To avoid invalid slave read data to the master, the
user’s master software must ensure enough time for
1. In Frame mode, if there is a possibility that the slave software to fill its write buffer before the user
master may not be initialized before the slave: application initiates a master write/read cycle. It is
a) If FRMPOL (SPIxCON2<13>) = 1, use a always advisable to preload the SPIxBUF Transmit
pull-down resistor on SSx. register in advance of the next master transaction
b) If FRMPOL = 0, use a pull-up resistor on cycle. SPIxBUF is transferred to the SPIx Shift register
SSx. and is empty once the data transmission begins.
Note: This ensures that the first frame
transmission after initialization is not 16.2 SPI Resources
shifted or corrupted. Many useful resources are provided on the main prod-
2. In Non-Framed 3-Wire mode (i.e., not using SSx uct page of the Microchip web site for the devices listed
from a master): in this data sheet. This product page contains the latest
a) If CKP (SPIxCON1<6>) = 1, always place a
pull-up resistor on SSx. 16.2.1 KEY RESOURCES
b) If CKP = 0, always place a pull-down
• “Serial Peripheral Interface (SPI)”
resistor on SSx.
(DS70005185) in the “dsPIC33/PIC24 Family
Note: This will ensure that during power-up and Reference Manual”
initialization, the master/slave will not lose • Code Samples
synchronization due to an errant SCKx
transition that would cause the slave to
accumulate data shift errors for both • Software Libraries
transmit and receive, appearing as • Webinars
corrupted data. • All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
3. FRMEN (SPIxCON2<15>) = 1 and SSEN
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
frame sync pulse is active on the SSx pin, which
indicates the start of a data frame.
Note: Not all third-party devices support Frame
mode timing. Refer to the SPIx
specifications in Section 26.0 “Electrical
Characteristics” for details.
4. In Master mode only, set the SMP bit

(SPIxCON1<9>) to a ‘1’ for the fastest SPIx data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit (SPIxCON1<5>)
is set.

16.3 SPI Control Registers
REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0
bit 15 bit 8
R/W-0 R/C-0, HS R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R-0, HS, HC
SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF
bit 7 bit 0
Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit HS = Hardware Settable bit HC = Hardware Clearable bit
bit 15 SPIEN: SPIx Enable bit

1 = Enables the module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables the module
bit 13 SPISIDL: SPIx Stop in Idle Mode bit
1 = Discontinues the module operation when device enters Idle mode
0 = Continues the module operation in Idle mode
bit 10-8 SPIBEC<2:0>: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode)
Master Mode:
Number of SPIx transfers that are pending.
Slave Mode:
Number of SPIx transfers that are unread.
bit 7 SRMPT: SPIx Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode)
1 = SPIx Shift register is empty and ready to send or receive the data
0 = SPIx Shift register is not empty
bit 6 SPIROV: SPIx Receive Overflow Flag bit
1 = A new byte/word is completely received and discarded; the user application has not read the previous
data in the SPIxBUF register
0 = No overflow has occurred
bit 5 SRXMPT: SPIx Receive FIFO Empty bit (valid in Enhanced Buffer mode)
1 = RX FIFO is empty
0 = RX FIFO is not empty
bit 4-2 SISEL<2:0>: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)
111 = Interrupt when the SPIx transmit buffer is full (SPITBF bit is set)
110 = Interrupt when the last bit is shifted into SPIxSR, and as a result, the TX FIFO is empty
101 = Interrupt when the last bit is shifted out of SPIxSR and the transmit is complete
100 = Interrupt when one data is shifted into the SPIxSR, and as a result, the TX FIFO has one open
memory location
011 = Interrupt when the SPIx receive buffer is full (SPIRBF bit is set)
010 = Interrupt when the SPIx receive buffer is 3/4 or more full
001 = Interrupt when data is available in the receive buffer (SRMPT bit is set)
000 = Interrupt when the last data in the receive buffer is read, and as a result, the buffer is empty
(SRXMPT bit is set)

REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)
bit 1 SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit has not yet started, SPIxTXB is full
0 = Transmit has started, SPIxTXB is empty
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer Mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write
operation.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive is complete, SPIxRXB is full
0 = Receive is incomplete, SPIxRXB is empty
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
Enhanced Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last unread
buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from
SPIxSR.

REGISTER 16-2: SPIxCON1: SPIx CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — DISSCK DISSDO MODE16 SMP CKE(1)
bit 15 bit 8

SSEN(2) CKP MSTEN SPRE2(3) SPRE1(3) SPRE0(3) PPRE1(3) PPRE0(3)
bit 7 bit 0
Legend:

bit 12 DISSCK: Disable SCKx Pin bit (SPIx Master modes only)
1 = Internal SPIx clock is disabled, pin functions as I/O
0 = Internal SPIx clock is enabled
bit 11 DISSDO: Disable SDOx Pin bit
1 = SDOx pin is not used by the module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10 MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9 SMP: SPIx Data Input Sample Phase bit
Master Mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave Mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8 CKE: SPIx Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (refer to bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)
bit 7 SSEN: Slave Select Enable bit (Slave mode)(2)
1 = SSx pin is used for Slave mode
0 = SSx pin is not used by the module; pin is controlled by port function
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to the value of 1:1.

REGISTER 16-2: SPIxCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3)
111 = Secondary prescale 1:1
•
•
•
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3)
11 = Primary prescale 1:1
Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).
2: This bit must be cleared when FRMEN = 1.
3: Do not set both primary and secondary prescalers to the value of 1:1.

REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
FRMEN SPIFSD FRMPOL — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — FRMDLY SPIBEN
bit 7 bit 0
Legend:
bit 15 FRMEN: Framed SPIx Support bit

1 = Framed SPIx support is enabled (SSx pin is used as the frame sync pulse input/output)
0 = Framed SPIx support is disabled
bit 14 SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 13 FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
bit 1 FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with the first bit clock
0 = Frame sync pulse precedes the first bit clock
bit 0 SPIBEN: Enhanced Buffer Enable bit
1 = Enhanced buffer is enabled
0 = Enhanced buffer is disabled (Standard mode)

NOTES:

17.0 INTER-INTEGRATED CIRCUIT The I2C module offers the following key features:
(I2C) • I2C Interface Supporting Both Master and Slave
modes of Operation
Note 1: This data sheet summarizes the • I2C Slave mode Supports 7 and 10-Bit Addressing
• I2C Master mode Supports 7 and 10-Bit Addressing
family of devices. It is not intended to be
a comprehensive reference source. To • I2C Port allows Bidirectional Transfers between
complement the information in this data Master and Slaves
sheet, refer to “Inter-Integrated Circuit • Serial Clock Synchronization for I2C Port can be
(I2C)” (DS70000195) in the “dsPIC33/ used as a Handshake Mechanism to Suspend
PIC24 Family Reference Manual”, which and Resume Serial Transfer (SCLREL control)
is available from the Microchip web site • I2C Supports Multi-Master Operation, Detects Bus
(www.microchip.com). Collision and Arbitrates accordingly
2: Some registers and associated bits • System Management Bus (SMBus) Support
described in this section may not be • Alternate I2C Pin Mapping (ASCLx/ASDAx)
Section 4.0 “Memory Organization” in 17.1 I2C Resources
and bit information. Many useful resources are provided on the main prod-
The dsPIC33EPXXGS50X family of devices contains in this data sheet. This product page contains the latest
two Inter-Integrated Circuit (I2C) modules: I2C1 and updates and additional information.
I2C2.
The I2C module provides complete hardware support 17.1.1 KEY RESOURCES
for both Slave and Multi-Master modes of the I2C serial • Code Samples
communication standard, with a 16-bit interface. • Application Notes
The I2C module has a 2-pin interface: • Software Libraries
• The SCLx/ASCLx pin is clock • Webinars
• The SDAx/ASDAx pin is data • All Related “dsPIC33/PIC24 Family Reference
Manual” Sections

FIGURE 17-1: I2Cx BLOCK DIAGRAM (x = 1 OR 2)
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx/ASCLx Clock
I2CxRSR
LSb
SDAx/ASDAx Address Match

Match Detect Write
I2CxMSK
Write Read
I2CxADD
Read
Start and Stop

Bit Detect
Write
Start and Stop

Bit Generation I2CxSTAT
Control Logic
Read
Collision Write
Detect
I2CxCONH
Acknowledge
Generation Read
Write
Clock
Stretching I2CxCONL
Read
Write
I2CxTRN
LSb
Shift Clock Read
Reload
Control
Write
BRG Down Counter I2CxBRG
Read
FP/2

17.2 I2C Control Registers
REGISTER 17-1: I2CxCONL: I2Cx CONTROL REGISTER LOW

R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
I2CEN — I2CSIDL SCLREL STRICT A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bit

bit 15 I2CEN: I2Cx Enable bit

1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C pins are controlled by port functions
bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at the beginning of every slave data byte transmission. Hardware is clear at the end of every slave
address byte reception. Hardware is clear at the end of every slave data byte reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at the beginning of every
slave data byte transmission. Hardware is clear at the end of every slave address byte reception.
bit 11 STRICT: Strict I2Cx Reserved Address Enable bit
1 = Strict Reserved Addressing is Enabled:
In Slave mode, the device will NACK any reserved address. In Master mode, the device is allowed
to generate addresses within the reserved address space.
0 = Reserved Addressing is Acknowledged:
In Slave mode, the device will ACK any reserved address. In Master mode, the device should not
address a slave device with a reserved address.
bit 10 A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specification
0 = Disables SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in I2CxRSR (module is enabled for reception)
0 = General call address is disabled

REGISTER 17-1: I2CxCONL: I2Cx CONTROL REGISTER LOW (CONTINUED)
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software or receives clock stretching
0 = Disables software or receives clock stretching
bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; hardware
is clear at the end of the master Acknowledge sequence
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C; hardware is clear at the end of the eighth bit of the master receive
data byte
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDAx and SCLx pins; hardware is clear at the end of the master Stop
sequence
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins; hardware is clear at the end of the
master Repeated Start sequence
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins; hardware is clear at the end of the master Start
sequence
0 = Start condition is not in progress

REGISTER 17-2: I2CxCONH: I2Cx CONTROL REGISTER HIGH
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

— PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:

bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enables interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enables interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 4 BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)
1 = I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of
the I2COV only if the RBF bit = 0
0 = I2CxRCV is only updated when I2COV is clear
bit 3 SDAHT: SDAx Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
1 = Enables slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
If the rising edge of SCLx and SDAx is sampled low when the module is in a high state, the BCL bit is
set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences.
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte, the SCLREL
(I2CxCONL<12>) bit will be cleared and SCLx will be held low
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte, the slave hardware clears the
SCLREL (I2CxCONL<12>) bit and SCLx is held low
0 = Data holding is disabled

REGISTER 17-3: I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC R-0, HSC R-0, HSC U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC
ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10
bit 15 bit 8
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
IWCOL I2COV D_A P S R_W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit ‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’
bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation)
1 = NACK was received from slave
0 = ACK was received from slave
Hardware is set or clear at the end of a slave Acknowledge.
bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at the beginning of master transmission. Hardware is clear at the end of slave Acknowledge.
bit 13 ACKTIM: Acknowledge Time Status bit (I2C Slave mode only)
1 = I2C bus is an Acknowledge sequence, set on the 8th falling edge of SCLx
0 = Not an Acknowledge sequence, cleared on the 9th rising edge of SCLx
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No bus collision detected
Hardware is set at detection of a bus collision.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when address matches the general call address. Hardware is clear at Stop detection.
bit 8 ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at the match of the 2nd byte of the matched 10-bit address. Hardware is clear at Stop
detection.
bit 7 IWCOL: I2Cx Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware is set at the occurrence of a write to I2CxTRN while busy (cleared by software).
bit 6 I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register was still holding the previous byte
0 = No overflow
Hardware is set at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5 D_A: Data/Address bit (I2C Slave mode only)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
Hardware is clear at a device address match. Hardware is set by reception of a slave byte.

REGISTER 17-3: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is set or clear when a Start, Repeated Start or Stop is detected.
bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware is set or clear when a Start, Repeated Start or Stop is detected.
bit 2 R_W: Read/Write Information bit (I2C Slave mode only)
1 = Read – Indicates data transfer is output from the slave
0 = Write – Indicates data transfer is input to the slave
Hardware is set or clear after reception of an I 2C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
Hardware is set when I2CxRCV is written with a received byte. Hardware is clear when software reads
I2CxRCV.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress, I2CxTRN is full
0 = Transmit is complete, I2CxTRN is empty
Hardware is set when software writes to I2CxTRN. Hardware is clear at completion of a data transmission.

REGISTER 17-4: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — AMSK<9:8>
bit 15 bit 8

AMSK<7:0>
bit 7 bit 0
Legend:

bit 9-0 AMSK<9:0>: Address Mask Select bits
For 10-Bit Address:
1 = Enables masking for bit Ax of incoming message address; bit match is not required in this position
0 = Disables masking for bit Ax; bit match is required in this position
For 7-Bit Address (I2CxMSK<6:0> only):
1 = Enables masking for bit Ax + 1 of incoming message address; bit match is not required in this position
0 = Disables masking for bit Ax + 1; bit match is required in this position

18.0 UNIVERSAL ASYNCHRONOUS The primary features of the UARTx module are:
RECEIVER TRANSMITTER • Full-Duplex, 8 or 9-Bit Data Transmission through
(UART) the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
Note 1: This data sheet summarizes the • One or Two Stop bits
features of the dsPIC33EPXXGS50X • Hardware Flow Control Option with UxCTS and
family of devices. It is not intended to be UxRTS Pins
a comprehensive reference source. To
• Fully Integrated Baud Rate Generator with 16-Bit
Prescaler
sheet, refer to “Universal Asynchro-
nous Receiver Transmitter (UART)” • Baud Rates Ranging from 4.375 Mbps to 67 bps in
(DS70000582) in the “dsPIC33/PIC24 16x mode at 70 MIPS
Family Reference Manual”, which is • Baud Rates Ranging from 17.5 Mbps to 267 bps in
available from the Microchip web site 4x mode at 70 MIPS
(www.microchip.com). • 4-Deep First-In First-Out (FIFO) Transmit Data
2: Some registers and associated bits Buffer
described in this section may not be • 4-Deep FIFO Receive Data Buffer
available on all devices. Refer to • Parity, Framing and Buffer Overrun Error Detection
Section 4.0 “Memory Organization” in • Support for 9-Bit Mode with Address Detect
this data sheet for device-specific register (9th bit = 1)
• Transmit and Receive Interrupts
The dsPIC33EPXXGS50X family of devices contains • A Separate Interrupt for all UARTx Error Conditions
two UART modules. • Loopback mode for Diagnostic Support
The Universal Asynchronous Receiver Transmitter • Support for Sync and Break Characters
(UART) module is one of the serial I/O modules • Support for Automatic Baud Rate Detection
available in the dsPIC33EPXXGS50X device family. • IrDA® Encoder and Decoder Logic
The UART is a full-duplex, asynchronous system that
• 16x Baud Clock Output for IrDA Support
can communicate with peripheral devices, such as
personal computers, LIN/J2602, RS-232 and RS-485 A simplified block diagram of the UARTx module is
interfaces. The module also supports a hardware flow shown in Figure 18-1. The UARTx module consists of
control option with the UxCTS and UxRTS pins, and these key hardware elements:
also includes an IrDA® encoder and decoder. • Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 18-1: UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control UxRTS/BCLKx

UxCTS
UARTx Receiver UxRX
UARTx Transmitter UxTX

18.1 UART Helpful Tips 18.2 UART Resources
1. In multi-node, direct connect UART networks, Many useful resources are provided on the main prod-
UART receive inputs react to the complemen- uct page of the Microchip web site for the devices listed
tary logic level defined by the URXINV bit in this data sheet. This product page contains the latest
(UxMODE<4>), which defines the Idle state, the updates and additional information.
default of which is logic high (i.e., URXINV = 0).
Because remote devices do not initialize at the 18.2.1 KEY RESOURCES
same time, it is likely that one of the devices, • Code Samples
because the RX line is floating, will trigger a Start
bit detection and will cause the first byte received,
after the device has been initialized, to be invalid. • Software Libraries
To avoid this situation, the user should use a pull- • Webinars
up or pull-down resistor on the RX pin depending • All Related “dsPIC33/PIC24 Family Reference
on the value of the URXINV bit. Manual” Sections
a) If URXINV = 0, use a pull-up resistor on the • Development Tools
UxRX pin.
b) If URXINV = 1, use a pull-down resistor on
the UxRX pin.
2. The first character received on a wake-up from
Sleep mode, caused by activity on the UxRX pin
of the UARTx module, will be invalid. In Sleep
mode, peripheral clocks are disabled. By the
time the oscillator system has restarted and
stabilized from Sleep mode, the baud rate bit
sampling clock, relative to the incoming UxRX
bit timing, is no longer synchronized, resulting in
the first character being invalid; this is to be
expected.

18.3 UART Control Registers
REGISTER 18-1: UxMODE: UARTx MODE REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0
bit 15 bit 8
R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL
bit 7 bit 0
Legend: HC = Hardware Clearable bit

bit 15 UARTEN: UARTx Enable bit(1)

1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is
minimal
bit 13 USIDL: UARTx Stop in Idle Mode bit
bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 9-8 UEN<1:0>: UARTx Pin Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by PORT latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by PORT latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
PORT latches
bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin, interrupt is generated on the falling edge; bit is cleared
in hardware on the following rising edge
0 = No wake-up is enabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the

“dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for receive or
transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).

REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
bit 4 URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the

“dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for receive or
transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).

REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1
(1)
UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0

URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bit

bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits

11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14 UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA® encoded, UxTX Idle state is ‘1’
0 = IrDA encoded, UxTX Idle state is ‘0’
bit 11 UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10 UTXEN: UARTx Transmit Enable bit(1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; UxTX pin is controlled
by the PORT
bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.

REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1  0 transition) resets the
receiver buffer and the UxRSR to the empty state
bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.

19.0 HIGH-SPEED, 12-BIT • Simultaneous Sampling of up to 5 Analog Inputs
ANALOG-TO-DIGITAL • Channel Scan Capability
CONVERTER (ADC) • Multiple Conversion Trigger Options for each
Core, including:
Note 1: This data sheet summarizes the - PWM1 through PWM5 (primary and
features of the dsPIC33EPXXGS50X secondary triggers, and current-limit event
family of devices. It is not intended to be trigger)
a comprehensive reference source. To - PWM Special Event Trigger
complement the information in this data - Timer1/Timer2 period match
sheet, refer to “12-Bit High-Speed,
- Output Compare 1 and event trigger
Multiple SARs A/D Converter (ADC)”
(DS70005213) in the “dsPIC33/PIC24 - External pin trigger event (ADTRG31)
Family Reference Manual”, which is - Software trigger
available from the Microchip web site • Two Integrated Digital Comparators with
(www.microchip.com). Dedicated Interrupts:
2: Some registers and associated bits - Multiple comparison options
described in this section may not be - Assignable to specific analog inputs
available on all devices. Refer to • Two Oversampling Filters with Dedicated
Section 4.0 “Memory Organization” in Interrupts:
- Provide increased resolution
- Assignable to a specific analog input
dsPIC33EPXXGS50X devices have a high-speed, The module consists of five independent SAR ADC
12-bit Analog-to-Digital Converter (ADC) that features cores. Simplified block diagrams of the Multiple SARs
a low conversion latency, high resolution and over- 12-Bit ADC are shown in Figure 19-1, Figure 19-2 and
sampling capabilities to improve performance in Figure 19-3.
AC/DC, DC/DC power converters.
The analog inputs (channels) are connected through
multiplexers and switches to the Sample-and-Hold
19.1 Features Overview (S&H) circuit of each ADC core. The core uses the
The High Speed, 12-Bit Multiple SARs Analog-to-Digital channel information (the output format, the measure-
Converter (ADC) includes the following features: ment mode and the input number) to process the analog
sample. When conversion is complete, the result is
• Five ADC Cores: Four Dedicated Cores and
stored in the result buffer for the specific analog input,
One Shared (Common) Core
and passed to the digital filter and digital comparator if
• User-Configurable Resolution of up to 12 Bits for they were configured to use data from this particular
each Core channel.
• Up to 3.25 Msps Conversion Rate per Channel at
The ADC module can sample up to five inputs at a time
12-Bit Resolution
(four inputs from the dedicated SAR cores and one
• Low-Latency Conversion from the shared SAR core). If multiple ADC inputs
• Up to 22 Analog Input Channels, with a Separate request conversion on the shared core, the module will
16-Bit Conversion Result Register for each Input convert them in a sequential manner, starting with the
• Conversion Result can be Formatted as Unsigned lowest order input.
or Signed Data, on a per Channel Basis, for All The ADC provides each analog input the ability to
Channels specify its own trigger source. This capability allows the
• Single-Ended and Pseudodifferential ADC to sample and convert analog inputs that are
Conversions are available on All ADC Cores associated with PWM generators operating on
independent time bases.

FIGURE 19-1: ADC MODULE BLOCK DIAGRAM
AVDD AVSS
Voltage Reference
(REFSEL<2:0>)
AN0 Reference
AN7 Dedicated Output Data
PGA1 (1) ADC Core 0(2) Digital Comparator 0
Clock ADCMP0 Interrupt
(3)
AN0ALT
Digital Comparator 1 ADCMP1 Interrupt
AN1 Reference
AN18 Dedicated Output Data
PGA2(1) ADC Core 1(2)
Clock
AN1ALT(3)
Digital Filter 0 ADFL0DAT
ADFLTR0 Interrupt
Reference
AN2 Digital Filter 1 ADFL1DAT
ADFLTR1 Interrupt
Dedicated Output Data
VBG Reference(1) ADC Core 2(2)
Clock
AN11
Reference
ADCBUF0
AN3 ADCAN0 Interrupt
Dedicated Output Data ADCBUF1
ADC Core 3(2) ADCAN1 Interrupt
AN15 Clock
ADCBUF21
ADCAN21 Interrupt
Reference
AN4
Shared Output Data
ADC Core
Clock
AN21
Divider
(CLKDIV<5:0>)
Clock Selection
(CLKSEL<1:0>)
Instruction FRC AUX

Clock Clock
Note 1: PGA1, PGA2 and Band Gap Reference (VBG) are internal analog inputs and are not available on device pins.
2: If the dedicated core uses an alternate channel, then shared core function cannot be used.
3: AN0ALT and AN1ALT are not available on dsPIC33EPXXGS502 devices.

FIGURE 19-2: DEDICATED CORES 0 TO 3 BLOCK DIAGRAM
Positive Input Positive Input

Selection +
PGAx
Alternate (CxCHS<1:0>) Reference
Positive Input Sample- 12-Bit SAR
and-Hold ADC
Output Data
Negative Input Negative Input
–
Selection
(1)
(DIFFx)
ADC Core Clock

Clock Divider
Trigger Stops
Sampling (ADCS<6:0> bits)
AVSS
Note 1: The DIFFx bit for the corresponding positive input channel must be set in order to use the negative
differential input.
FIGURE 19-3: SHARED CORE BLOCK DIAGRAM
AN4
+
Reference
12-Bit
AN21 SAR
Shared ADC Output Data
Sample-
Analog Channel Number and-Hold
from Current Trigger
ADC Core Clock
AN9(1) Negative Input – Clock Divider
Selection
(SHRADC<6:0> bits)
(DIFFx)(1)
SHRSAMC<9:0>
Sampling Time
AVSS
Note 1: Differential-mode conversion is not available for the shared ADC core in dsPIC33EPXXGS502 devices.
For all other devices, the DIFFx bit for the corresponding positive input channel must be set to use AN9
as the negative differential input.

19.2 Analog-to-Digital Converter 19.2.1 KEY RESOURCES
Resources • Code Samples
Many useful resources are provided on the main • Application Notes
product page of the Microchip web site for the devices • Software Libraries
listed in this data sheet. This product page contains the • Webinars
latest updates and additional information. • All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
REGISTER 19-1: ADCON1L: ADC CONTROL REGISTER 1 LOW

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
ADON(1) — ADSIDL — — — — —
bit 15 bit 8
U-0 r-0 r-0 r-0 r-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend: r = Reserved bit

bit 15 ADON: ADC Enable bit(1)

1 = ADC module is enabled
0 = ADC module is off
bit 13 ADSIDL: ADC Stop in Idle Mode bit
bit 6-3 Reserved: Maintain as ‘0’
Note 1: Set the ADON bit only after the ADC module has been configured. Changing ADC Configuration bits when
ADON = 1 will result in unpredictable behavior.

REGISTER 19-2: ADCON1H: ADC CONTROL REGISTER 1 HIGH
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-1 R/W-1 r-0 r-0 r-0 r-0 r-0

FORM SHRRES1 SHRRES0 — — — — —
bit 7 bit 0


bit 7 FORM: Fractional Data Output Format bit
1 = Fractional
0 = Integer
bit 6-5 SHRRES<1:0>: Shared ADC Core Resolution Selection bits
11 = 12-bit resolution

R/W-0 R/W-0 r-0 R/W-0 r-0 R/W-0 R/W-0 R/W-0
REFCIE REFERCIE — EIEN — SHREISEL2(1) SHREISEL1(1) SHREISEL0(1)
bit 15 bit 8

— SHRADCS6 SHRADCS5 SHRADCS4 SHRADCS3 SHRADCS2 SHRADCS1 SHRADCS0
bit 7 bit 0

bit 15 REFCIE: Band Gap and Reference Voltage Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when the band gap will become ready
0 = Common interrupt is disabled for the band gap ready event
bit 14 REFERCIE: Band Gap or Reference Voltage Error Common Interrupt Enable bit
1 = Common interrupt will be generated when a band gap or reference voltage error is detected
0 = Common interrupt is disabled for the band gap and reference voltage error event
bit 13 Reserved: Maintain as ‘0’
bit 12 EIEN: Early Interrupts Enable bit
1 = The early interrupt feature is enabled for the input channel interrupts (when the EISTATx flag is set)
0 = The individual interrupts are generated when conversion is done (when the ANxRDY flag is set)
bit 11 Reserved: Maintain as ‘0’
bit 10-8 SHREISEL<2:0>: Shared Core Early Interrupt Time Selection bits(1)
111 = Early interrupt is set and interrupt is generated 8 TADCORE clocks prior to when the data is ready
000 = Early interrupt is set and interrupt is generated 1 TADCORE clock prior to when the data is ready
bit 6-0 SHRADCS<6:0>: Shared ADC Core Input Clock Divider bits
These bits determine the number of TCORESRC (Source Clock Periods) for one shared TADCORE (Core
Clock Period).
1111111 = 254 Source Clock Periods
•
•
•
Note 1: For the 6-bit shared ADC core resolution (SHRRES<1:0> = 00), the SHREISEL<2:0> settings,
from ‘100’ to ‘111’, are not valid and should not be used. For the 8-bit shared ADC core resolution
(SHRRES<1:0> = 01), the SHREISEL<2:0> settings, ‘110’ and ‘111’, are not valid and should not be used.

R-0, HSC R-0, HSC r-0 r-0 r-0 r-0 R/W-0 R/W-0
REFRDY REFERR — — — — SHRSAMC9 SHRSAMC8
bit 15 bit 8

SHRSAMC7 SHRSAMC6 SHRSAMC5 SHRSAMC4 SHRSAMC3 SHRSAMC2 SHRSAMC1 SHRSAMC0
bit 7 bit 0
Legend: r = Reserved bit U = Unimplemented bit, read as ‘0’

R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit
bit 15 REFRDY: Band Gap and Reference Voltage Ready Flag bit
1 = Band gap is ready
0 = Band gap is not ready
bit 14 REFERR: Band Gap or Reference Voltage Error Flag bit
1 = Band gap was removed after the ADC module was enabled (ADON = 1)
0 = No band gap error was detected
bit 9-0 SHRSAMC<9:0>: Shared ADC Core Sample Time Selection bits
These bits specify the number of shared ADC Core Clock Periods (TADCORE) for the shared ADC core
sample time.
1111111111 = 1025 TADCORE
•
•
•
0000000001 = 3 TADCORE
0000000000 = 2 TADCORE

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0, HSC R/W-0 R-0, HSC
REFSEL2 REFSEL1 REFSEL0 SUSPEND SUSPCIE SUSPRDY SHRSAMP CNVRTCH
bit 15 bit 8
R/W-0 R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SWLCTRG SWCTRG CNVCHSEL5 CNVCHSEL4 CNVCHSEL3 CNVCHSEL2 CNVCHSEL1 CNVCHSEL0
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’

bit 15-13 REFSEL<2:0>: ADC Reference Voltage Selection bits
Value VREFH VREFL

000 AVDD AVSS
001-111 = Unimplemented: Do not use
bit 12 SUSPEND: All ADC Cores Triggers Disable bit
1 = All new trigger events for all ADC cores are disabled
0 = All ADC cores can be triggered
bit 11 SUSPCIE: Suspend All ADC Cores Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC core triggers are suspended (SUSPEND bit = 1)
and all previous conversions are finished (SUSPRDY bit becomes set)
0 = Common interrupt is not generated for suspend ADC cores event
bit 10 SUSPRDY: All ADC Cores Suspended Flag bit
1 = All ADC cores are suspended (SUSPEND bit = 1) and have no conversions in progress
0 = ADC cores have previous conversions in progress
bit 9 SHRSAMP: Shared ADC Core Sampling Direct Control bit
This bit should be used with the individual channel conversion trigger controlled by the CNVRTCH bit.
It connects an analog input, specified by the CNVCHSEL<5:0> bits, to the shared ADC core and allows
extending the sampling time. This bit is not controlled by hardware and must be cleared before the
conversion starts (setting CNVRTCH to ‘1’).
1 = Shared ADC core samples an analog input specified by the CNVCHSEL<5:0> bits
0 = Sampling is controlled by the shared ADC core hardware
bit 8 CNVRTCH: Software Individual Channel Conversion Trigger bit
1 = Single trigger is generated for an analog input specified by the CNVCHSEL<5:0> bits; when the bit
is set, it is automatically cleared by hardware on the next instruction cycle
0 = Next individual channel conversion trigger can be generated
bit 7 SWLCTRG: Software Level-Sensitive Common Trigger bit
1 = Triggers are continuously generated for all channels with the software, level-sensitive common
trigger selected as a source in the ADTRIGxL and ADTRIGxH registers
0 = No software, level-sensitive common triggers are generated
bit 6 SWCTRG: Software Common Trigger bit
1 = Single trigger is generated for all channels with the software, common trigger selected as a source
in the ADTRIGxL and ADTRIGxH registers; when the bit is set, it is automatically cleared by
hardware on the next instruction cycle
0 = Ready to generate the next software, common trigger
bit 5-0 CNVCHSEL <5:0>: Channel Number Selection for Software Individual Channel Conversion Trigger bits
These bits define a channel to be converted when the CNVRTCH bit is set.

CLKSEL1 CLKSEL0 CLKDIV5 CLKDIV4 CLKDIV3 CLKDIV2 CLKDIV1 CLKDIV0
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

SHREN — — — C3EN C2EN C1EN C0EN
bit 7 bit 0
Legend:
bit 15-14 CLKSEL<1:0>: ADC Module Clock Source Selection bits

11 = APLL
10 = FRC
01 = FOSC (System Clock x 2)
00 = FSYS (System Clock)
bit 13-8 CLKDIV<5:0>: ADC Module Clock Source Divider bits
The divider forms a TCORESRC clock used by all ADC cores (shared and dedicated) from the TSRC ADC
module clock source selected by the CLKSEL<2:0> bits. Then, each ADC core individually divides the
TCORESRC clock to get a core-specific TADCORE clock using the ADCS<6:0> bits in the ADCORExH
register or the SHRADCS<6:0> bits in the ADCON2L register.
•
•
•
000000 = 1 Source Clock Period
bit 7 SHREN: Shared ADC Core Enable bit
1 = Shared ADC core is enabled
0 = Shared ADC core is disabled
bit 3 C3EN: Dedicated ADC Core 3 Enable bits
1 = Dedicated ADC Core 3 is enabled
0 = Dedicated ADC Core 3 is disabled

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — SYNCTRG3 SYNCTRG2 SYNCTRG1 SYNCTRG0
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — SAMC3EN SAMC2EN SAMC1EN SAMC0EN
bit 7 bit 0
Legend:

bit 11 SYNCTRG3: Dedicated ADC Core 3 Trigger Synchronization bit
1 = All triggers are synchronized with the core source clock (TCORESRC)
0 = The ADC core triggers are not synchronized
bit 3 SAMC3EN: Dedicated ADC Core 3 Conversion Delay Enable bit
1 = After trigger, the conversion will be delayed and the ADC core will continue sampling during the
time specified by the SAMC<9:0> bits in the ADCORE3L register
0 = After trigger, the sampling will be stopped immediately and the conversion will be started on the
next core clock cycle

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

C3CHS1 C3CHS0 C2CHS1 C2CHS0 C1CHS1 C1CHS0 C0CHS1 C0CHS0
bit 7 bit 0
Legend:

bit 7-6 C3CHS<1:0>: Dedicated ADC Core 3 Input Channel Selection bits
1x = Reserved
01 = AN15 (differential negative input when DIFF3 (ADMOD0L<7>) = 1)
00 = AN3
11 = Reserved
10 = VREF Band Gap
00 = AN2
11 = AN1ALT
10 = PGA2
00 = AN1
11 = AN0ALT
10 = PGA1
00 = AN0

R-0, HSC U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC
SHRRDY — — — C3RDY C2RDY C1RDY C0RDY
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

SHRPWR — — — C3PWR C2PWR C1PWR C0PWR
bit 7 bit 0

bit 15 SHRRDY: Shared ADC Core Ready Flag bit

1 = ADC core is powered and ready for operation
0 = ADC core is not ready for operation
bit 11 C3RDY: Dedicated ADC Core 3 Ready Flag bit
bit 7 SHRPWR: Shared ADC Core x Power Enable bit
1 = ADC Core x is powered
0 = ADC Core x is off
bit 3 C3PWR: Dedicated ADC Core 3 Power Enable bit
1 = ADC core is powered
0 = ADC core is off
0 = ADC core is off
0 = ADC core is off
0 = ADC core is off

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — WARMTIME3 WARMTIME2 WARMTIME1 WARMTIME0
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

SHRCIE — — — C3CIE C2CIE C1CIE C0CIE
bit 7 bit 0
Legend:

bit 11-8 WARMTIME<3:0>: ADC Dedicated Core x Power-up Delay bits
These bits determine the power-up delay in the number of the Core Source Clock Periods (TCORESRC)
for all ADC cores.
00xx = 16 Source Clock Periods
bit 7 SHRCIE: Shared ADC Core Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC core is powered and ready for operation
0 = Common interrupt is disabled for an ADC core ready event
bit 3 C3CIE: Dedicated ADC Core 3 Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC Core 3 is powered and ready for operation
0 = Common interrupt is disabled for an ADC Core 3 ready event

REGISTER 19-11: ADCORExL: DEDICATED ADC CORE x CONTROL REGISTER LOW (x = 0 to 3)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SAMC<9:8>
bit 15 bit 8

SAMC<7:0>
bit 7 bit 0
Legend:

bit 9-0 SAMC<9:0>: Dedicated ADC Core x Conversion Delay Selection bits
These bits determine the time between the trigger event and the start of conversion in the number of
the Core Clock Periods (TADCORE). During this time, the ADC Core x still continues sampling. This
feature is enabled by the SAMCxEN bits in the ADCON4L register.
1111111111 = 1025 TADCORE
•
•
•
0000000001 = 3 TADCORE
0000000000 = 2 TADCORE

REGISTER 19-12: ADCORExH: DEDICATED ADC CORE x CONTROL REGISTER HIGH (x = 0 to 3)(1)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
— — — EISEL2 EISEL1 EISEL0 RES1 RES0
bit 15 bit 8

— ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0
bit 7 bit 0
Legend:

bit 12-10 EISEL<2:0>: ADC Core x Early Interrupt Time Selection bits
111 = Early interrupt is set and an interrupt is generated 8 TADCORE clocks prior to when the data is ready
000 = Early interrupt is set and an interrupt is generated 1 TADCORE clock prior to when the data is ready
bit 9-8 RES<1:0>: ADC Core x Resolution Selection bits
bit 6-0 ADCS<6:0>: ADC Core x Input Clock Divider bits
These bits determine the number of Source Clock Periods (TCORESRC) for one Core Clock Period
(TADCORE).
•
•
•
Note 1: For the 6-bit ADC core resolution (RES<1:0> = 00), the EISEL<2:0> bits settings, from ‘100’ to ‘111’, are
not valid and should not be used. For the 8-bit ADC core resolution (RES<1:0> = 01), the EISEL<2:0> bits
settings, ‘110’ and ‘111’, are not valid and should not be used.

REGISTER 19-13: ADLVLTRGL: ADC LEVEL-SENSITIVE TRIGGER CONTROL REGISTER LOW
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
LVLEN<15:8>
bit 15 bit 8

LVLEN<7:0>
bit 7 bit 0
Legend:
bit 15-0 LVLEN<15:0>: Level Trigger for Corresponding Analog Input Enable bits
1 = Input trigger is level-sensitive
0 = Input trigger is edge-sensitive
REGISTER 19-14: ADLVLTRGH: ADC LEVEL-SENSITIVE TRIGGER CONTROL REGISTER HIGH

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — LVLEN<21:16>
bit 7 bit 0
Legend:

bit 5-0 LVLEN<21:16>: Level Trigger for Corresponding Analog Input Enable bits
1 = Input trigger is level-sensitive
0 = Input trigger is edge-sensitive

REGISTER 19-15: ADEIEL: ADC EARLY INTERRUPT ENABLE REGISTER LOW
EIEN<15:8>
bit 15 bit 8

EIEN<7:0>
bit 7 bit 0
Legend:
bit 15-0 EIEN<15:0>: Early Interrupt Enable for Corresponding Analog Inputs bits
1 = Early interrupt is enabled for the channel
0 = Early interrupt is disabled for the channel
REGISTER 19-16: ADEIEH: ADC EARLY INTERRUPT ENABLE REGISTER HIGH

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — EIEN<21:16>
bit 7 bit 0
Legend:

bit 5-0 EIEN<21:16>: Early Interrupt Enable for Corresponding Analog Inputs bits
1 = Early interrupt is enabled for the channel
0 = Early interrupt is disabled for the channel

REGISTER 19-17: ADEISTATL: ADC EARLY INTERRUPT STATUS REGISTER LOW
EISTAT<15:8>
bit 15 bit 8

EISTAT<7:0>
bit 7 bit 0
Legend:
bit 15-0 EISTAT<15:0>: Early Interrupt Status for Corresponding Analog Inputs bits
1 = Early interrupt was generated
0 = Early interrupt was not generated since the last ADCBUFx read
REGISTER 19-18: ADEISTATH: ADC EARLY INTERRUPT STATUS REGISTER HIGH

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — EISTAT<21:16>
bit 7 bit 0
Legend:

bit 5-0 EISTAT<21:16>: Early Interrupt Status for Corresponding Analog Inputs bits
1 = Early interrupt was generated
0 = Early interrupt was not generated since the last ADCBUFx read

REGISTER 19-19: ADMOD0L: ADC INPUT MODE CONTROL REGISTER 0 LOW
DIFF7 SIGN7 DIFF6 SIGN6 DIFF5 SIGN5 DIFF4 SIGN4
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-1(odd) DIFF<7:0>: Differential-Mode for Corresponding Analog Inputs bits

1 = Channel is differential
0 = Channel is single-ended
bit 14-0 (even) SIGN<7:0>: Output Data Sign for Corresponding Analog Inputs bits
1 = Channel output data is signed
0 = Channel output data is unsigned
REGISTER 19-20: ADMOD0H: ADC INPUT MODE CONTROL REGISTER 0 HIGH

bit 15 bit 8

bit 7 bit 0
Legend:


REGISTER 19-21: ADMOD1L: ADC INPUT MODE CONTROL REGISTER 1 LOW
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — DIFF21 SIGN21 DIFF20 SIGN20
bit 15 bit 8

bit 7 bit 0
Legend:


REGISTER 19-22: ADIEL: ADC INTERRUPT ENABLE REGISTER LOW
IE<15:8>
bit 15 bit 8

IE<7:0>
bit 7 bit 0
Legend:
bit 15-0 IE<15:0>: Common Interrupt Enable bits

1 = Common and individual interrupts are enabled for the corresponding channel
0 = Common and individual interrupts are disabled for the corresponding channel
REGISTER 19-23: ADIEH: ADC INTERRUPT ENABLE REGISTER HIGH

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — IE<21:16>
bit 7 bit 0
Legend:

bit 5-0 IE<21:16>: Common Interrupt Enable bits
1 = Common and individual interrupts are enabled for the corresponding channel
0 = Common and individual interrupts are disabled for the corresponding channel

REGISTER 19-24: ADSTATL: ADC DATA READY STATUS REGISTER LOW
R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC
AN<15:8>RDY
bit 15 bit 8
R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC
AN<7:0>RDY
bit 7 bit 0

bit 15-0 AN<15:0>RDY: Common Interrupt Enable for Corresponding Analog Inputs bits
1 = Channel conversion result is ready in the corresponding ADCBUFx register
0 = Channel conversion result is not ready
REGISTER 19-25: ADSTATH: ADC DATA READY STATUS REGISTER HIGH

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC
— — AN<21:16>RDY
bit 7 bit 0


bit 5-0 AN<21:16>RDY: Common Interrupt Enable for Corresponding Analog Inputs bits
1 = Channel conversion result is ready in the corresponding ADCBUFx register
0 = Channel conversion result is not ready

REGISTER 19-26: ADTRIGxL: ADC CHANNEL TRIGGER x SELECTION REGISTER LOW
(x = 0 to 5)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC(4x+1)<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TRGSRC(4x)<4:0>
bit 7 bit 0
Legend:

bit 12-8 TRGSRC(4x+1)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits
11111 = ADTRG31
11110 = Reserved
11101 = Reserved
11100 = PWM Generator 5 current-limit trigger
10111 = Output Compare 2 trigger
10101 = Reserved
10100 = Reserved
10011 = PWM Generator 5 secondary trigger
01110 = PWM secondary Special Event Trigger
01101 = Timer2 period match
01011 = Reserved
01010 = Reserved
01001 = PWM Generator 5 primary trigger
00100 = PWM Special Event Trigger
00011 = Reserved
00010 = Level software trigger
00001 = Common software trigger
00000 = No trigger is enabled

REGISTER 19-26: ADTRIGxL: ADC CHANNEL TRIGGER x SELECTION REGISTER LOW
bit 4-0 TRGSRC(4x)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits
11111 = ADTRG31
11110 = Reserved
11101 = Reserved
10101 = Reserved
10100 = Reserved
01011 = Reserved
01010 = Reserved
00011 = Reserved

REGISTER 19-27: ADTRIGxH: ADC CHANNEL TRIGGER x SELECTION REGISTER HIGH
(x = 0 to 5)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC(4x+3)<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TRGSRC(4x+2)<4:0>
bit 7 bit 0
Legend:

11111 = ADTRG31
11110 = Reserved
11101 = Reserved
10101 = Reserved
10100 = Reserved
01011 = Reserved
01010 = Reserved
00011 = Reserved

REGISTER 19-27: ADTRIGxH: ADC CHANNEL TRIGGER x SELECTION REGISTER HIGH
11111 = ADTRG31
11110 = Reserved
11101 = Reserved
10101 = Reserved
10100 = Reserved
01011 = Reserved
01010 = Reserved
00011 = Reserved

REGISTER 19-28: ADCAL0L: ADC CALIBRATION REGISTER 0 LOW
R-0, HSC U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0
CAL1RDY — — — — CAL1DIFF CAL1EN CAL1RUN
bit 15 bit 8
R-0, HSC U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0

bit 15 CAL1RDY: Dedicated ADC Core 1 Calibration Status Flag bit

1 = Dedicated ADC Core 1 calibration is finished
0 = Dedicated ADC Core 1 calibration is in progress
bit 11 Reserved: Must be written as ‘0’
bit 10 CAL1DIFF: Dedicated ADC Core 1 Differential-Mode Calibration bit
1 = Dedicated ADC Core 1 will be calibrated in Differential Input mode
0 = Dedicated ADC Core 1 will be calibrated in Single-Ended Input mode
bit 9 CAL1EN: Dedicated ADC Core 1 Calibration Enable bit
1 = Dedicated ADC Core 1 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by
software
0 = Dedicated ADC Core 1 calibration bits are disabled
bit 8 CAL1RUN: Dedicated ADC Core 1 Calibration Start bit
1 = If this bit is set by software, the dedicated ADC Core 1 calibration cycle is started; this bit is
automatically cleared by hardware
0 = Software can start the next calibration cycle
software

REGISTER 19-29: ADCAL0H: ADC CALIBRATION REGISTER 0 HIGH
R-0, HSC U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
R-0, HSC U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0


software
software

REGISTER 19-30: ADCAL1H: ADC CALIBRATION REGISTER 1 HIGH
R/W-0, HS U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0
CSHRRDY — — — — CSHRDIFF CSHREN CSHRRUN
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0

R = Readable bit W = Writable bit HS = Hardware Settable bit
bit 15 CSHRRDY: Shared ADC Core Calibration Status Flag bit

1 = Shared ADC core calibration is finished
0 = Shared ADC core calibration is in progress
bit 10 CSHRDIFF: Shared ADC Core Differential-Mode Calibration bit
1 = Shared ADC core will be calibrated in Differential Input mode
0 = Shared ADC core will be calibrated in Single-Ended Input mode
bit 9 CSHREN: Shared ADC Core Calibration Enable bit
1 = Shared ADC core calibration bits (CSHRRDY, CSHRDIFF and CSHRRUN) can be accessed by
software
0 = Shared ADC core calibration bits are disabled
bit 8 CSHRRUN: Shared ADC Core Calibration Start bit
1 = If this bit is set by software, the shared ADC core calibration cycle is started; this bit is cleared
automatically by hardware

REGISTER 19-31: ADCMPxCON: ADC DIGITAL COMPARATOR x CONTROL REGISTER (x = 0 or 1)
U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC
— — — CHNL4 CHNL3 CHNL2 CHNL1 CHNL0
bit 15 bit 8
R/W-0 R/W-0 R-0, HC, HS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CMPEN IE STAT BTWN HIHI HILO LOHI LOLO
bit 7 bit 0
Legend: HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware Settable bit

bit 12-8 CHNL<4:0>: Input Channel Number bits
If the comparator has detected an event for a channel, this channel number is written to these bits.
11111 = Reserved
•
•
10110 = Reserved
10101 = AN21
10100 = AN20
•
•
00001 = AN1
00000 = AN0
bit 7 CMPEN: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled and the STAT status bit is cleared
bit 6 IE: Comparator Common ADC Interrupt Enable bit
1 = Common ADC interrupt will be generated if the comparator detects a comparison event
0 = Common ADC interrupt will not be generated for the comparator
bit 5 STAT: Comparator Event Status bit
This bit is cleared by hardware when the channel number is read from the CHNL<4:0> bits.
1 = A comparison event has been detected since the last read of the CHNL<4:0> bits
0 = A comparison event has not been detected since the last read of the CHNL<4:0> bits
bit 4 BTWN: Between Low/High Comparator Event bit
1 = Generates a comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI
0 = Does not generate a digital comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI
bit 3 HIHI: High/High Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx ≥ ADCMPxHI
0 = Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxHI
bit 2 HILO: High/Low Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx < ADCMPxHI
0 = Does not generate a digital comparator event when ADCBUFx < ADCMPxHI
bit 1 LOHI: Low/High Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx ≥ ADCMPxLO
0 = Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxLO
bit 0 LOLO: Low/Low Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx < ADCMPxLO
0 = Does not generate a digital comparator event when ADCBUFx < ADCMPxLO

REGISTER 19-32: ADCMPxENL: ADC DIGITAL COMPARATOR x CHANNEL ENABLE REGISTER
LOW (x = 0 or 1)
CMPEN<15:8>
bit 15 bit 8
R/W/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CMPEN<7:0>
bit 7 bit 0
Legend:
bit 15-0 CMPEN<15:0>: Comparator Enable for Corresponding Input Channels bits
1 = Conversion result for corresponding channel is used by the comparator
0 = Conversion result for corresponding channel is not used by the comparator
REGISTER 19-33: ADCMPxENH: ADC DIGITAL COMPARATOR x CHANNEL ENABLE REGISTER

HIGH (x = 0 or 1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CMPEN<21:16>
bit 7 bit 0
Legend:

bit 5-0 CMPEN<21:16>: Comparator Enable for Corresponding Input Channels bits
1 = Conversion result for corresponding channel is used by the comparator
0 = Conversion result for corresponding channel is not used by the comparator

REGISTER 19-34: ADFLxCON: ADC DIGITAL FILTER x CONTROL REGISTER
(x = 0 or 1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0, HSC
FLEN MODE1 MODE0 OVRSAM2 OVRSAM1 OVRSAM0 IE RDY
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — FLCHSEL4 FLCHSEL3 FLCHSEL2 FLCHSEL1 FLCHSEL0
bit 7 bit 0

bit 15 FLEN: Filter Enable bit

1 = Filter is enabled
0 = Filter is disabled and the RDY bit is cleared
bit 14-13 MODE<1:0>: Filter Mode bits
11 = Averaging mode
10 = Reserved
01 = Reserved
00 = Oversampling mode
bit 12-10 OVRSAM<2:0>: Filter Averaging/Oversampling Ratio bits
If MODE<1:0> = 00:
111 = 128x (16-bit result in the ADFLxDAT register is in 12.4 format)
If MODE<1:0> = 11 (12-bit result in the ADFLxDAT register in all instances):
111 = 256x
110 = 128x
101 = 64x
100 = 32x
011 = 16x
010 = 8x
001 = 4x
000 = 2x
bit 9 IE: Filter Common ADC Interrupt Enable bit
1 = Common ADC interrupt will be generated when the filter result will be ready
0 = Common ADC interrupt will not be generated for the filter
bit 8 RDY: Oversampling Filter Data Ready Flag bit
This bit is cleared by hardware when the result is read from the ADFLxDAT register.
1 = Data in the ADFLxDAT register is ready
0 = The ADFLxDAT register has been read and new data in the ADFLxDAT register is not ready

REGISTER 19-34: ADFLxCON: ADC DIGITAL FILTER x CONTROL REGISTER
(x = 0 or 1) (CONTINUED)
bit 4-0 FLCHSEL<4:0>: Oversampling Filter Input Channel Selection bits
11111 = Reserved
•
•
•
10110 = Reserved
10101 = AN21
10100 = AN20
•
•
•
00001 = AN1
00000 = AN0

NOTES:

20.0 HIGH-SPEED ANALOG 20.1 Features Overview
COMPARATOR The SMPS comparator module offers the following
Note 1: This data sheet summarizes the major features:
features of the dsPIC33EPXXGS50X • Four Rail-to-Rail Analog Comparators
family of devices. It is not intended to be • Dedicated 12-Bit DAC for each Analog
a comprehensive reference source. To Comparator
complement the information in this data • Up to Six Selectable Input Sources per
sheet, refer to “High-Speed Analog Comparator:
Comparator Module” (DS70005128) in
- Four external inputs
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the - Two internal inputs from the PGAx module
Microchip web site (www.microchip.com). • Programmable Comparator Hysteresis
2: Some registers and associated bits • Programmable Output Polarity
described in this section may not be • Up to Two DAC Outputs to Device Pins
available on all devices. Refer to • Multiple Voltage References for the DAC:
Section 4.0 “Memory Organization” in - External References (EXTREF1 or
this data sheet for device-specific register EXTREF2)
- AVDD
The high-speed analog comparator module monitors • Interrupt Generation Capability
current and/or voltage transients that may be too fast • Functional Support for PWMx:
for the CPU and ADC to capture. - PWMx duty cycle control
- PWMx period control
- PWMx Fault detected

20.2 Module Description The analog comparator input pins are typically shared
with pins used by the Analog-to-Digital Converter (ADC)
Figure 20-1 shows a functional block diagram of one module. Both the comparator and the ADC can use the
analog comparator from the high-speed analog same pins at the same time. This capability enables a
comparator module. The analog comparator provides user to measure an input voltage with the ADC and
high-speed operation with a typical delay of 15 ns. The detect voltage transients with the comparator.
negative input of the comparator is always connected
to the DACx circuit. The positive input of the compara-
tor is connected to an analog multiplexer that selects
the desired source pin.
FIGURE 20-1: HIGH-SPEED ANALOG COMPARATOR x MODULE BLOCK DIAGRAM
INSELx
PWM Trigger
ALTINP
PGA1OUT (remappable I/O)
PGA2OUT
MUX
CMPxA(1)
Status
CMPxB(1) CMPx(1) 0 Pulse Stretcher
CMPxC(1) and
CMPxD(1) 1 Digital Filter Interrupt
Request
EXTREF
RANGE CMPPOL
AVDD
MUX
EXTREF1(2) DACx(1) DACOE
EXTREF2(2,3)
12 DAC1/
DAC3 Output
CMREFx Buffer
DACOUT1
PGA1OUT
DBCC Bit
FDEVOPT<6>
PGAOEN
DACOE
DAC2/
DAC4 Output
Buffer
DACOUT2(3)
PGA2OUT
PGAOEN
Note 1: x = 1-4
2: EXTREF1 is connected to DAC1/DAC3. EXTREF2 is connected to DAC2/DAC4.
3: Not available on all devices.

20.3 Module Applications Each DACx has an output enable bit, DACOE, in the
CMPxCON register that enables the DACx reference
This module provides a means for the SMPS dsPIC® voltage to be routed to an external output pin
DSC devices to monitor voltage and currents in a (DACOUTx). Refer to Figure 20-1 for connecting the
power conversion application. The ability to detect DACx output voltage to the DACOUTx pins.
transient conditions and stimulate the dsPIC DSC
processor and/or peripherals, without requiring the Note 1: Ensure that multiple DACOE bits are not
processor and ADC to constantly monitor voltages or set in software. The output on the
currents, frees the dsPIC DSC to perform other tasks. DACOUTx pin will be indeterminate if
multiple comparators enable the DACx
The comparator module has a high-speed comparator output.
and an associated 12-bit DAC that provides a
programmable reference voltage to the inverting input 2: DACOUT2 is not available on all devices.
of the comparator. The polarity of the comparator out-
put is user-programmable. The output of the module 20.5 Pulse Stretcher and Digital Logic
can be used in the following modes:
The analog comparator can respond to very fast tran-
• Generate an Interrupt sient signals. After the comparator output is given the
• Trigger an ADC Sample and Convert Process desired polarity, the signal is passed to a pulse
• Truncate the PWMx Signal (current limit) stretching circuit. The pulse stretching circuit has an
• Truncate the PWMx Period (current minimum) asynchronous set function and a delay circuit that
ensures the minimum pulse width is three system clock
• Disable the PWMx Outputs (Fault latch)
cycles wide to allow the attached circuitry to properly
The output of the comparator module may be used in respond to a narrow pulse event.
multiple modes at the same time, such as: 1) generate
The pulse stretcher circuit is followed by a digital filter.
an interrupt, 2) have the ADC take a sample and con-
The digital filter is enabled via the FLTREN bit in the
vert it, and 3) truncate the PWMx output in response to
CMPxCON register. The digital filter operates with the
a voltage being detected beyond its expected value.
clock specified via the FCLKSEL bit in the CMPxCON
The comparator module can also be used to wake-up the register. The comparator signal must be stable in a high
system from Sleep or Idle mode when the analog input or low state, for at least three of the selected clock
voltage exceeds the programmed threshold voltage. cycles, for it to pass through the digital filter.
20.4 Digital-to-Analog Comparator (DAC)

Each analog comparator has a dedicated 12-bit DAC
that is used to program the comparator threshold voltage
via the CMPxDAC register. The DAC voltage reference
source is selected using the EXTREF and RANGE bits
in the CMPxCON register.
The EXTREF bit selects either the external voltage ref-
erence, EXTREFx, or an internal source as the voltage
reference source. The EXTREFx input enables users to
connect to a voltage reference that better suits their
application. The RANGE bit enables AVDD as the
voltage reference source for the DAC when an internal
voltage reference is selected.
Note: EXTREF2 is not available on all devices.

20.6 Hysteresis 20.7 Analog Comparator Resources
An additional feature of the module is hysteresis con- Many useful resources are provided on the main prod-
trol. Hysteresis can be enabled or disabled and its uct page of the Microchip web site for the devices listed
amplitude can be controlled by the HYSSEL<1:0> bits in this data sheet. This product page contains the latest
in the CMPxCON register. Three different values are updates and additional information.
available: 5 mV, 10 mV and 20 mV. It is also possible to
select the edge (rising or falling) to which hysteresis is 20.7.1 KEY RESOURCES
to be applied.
• Code Samples
Hysteresis control prevents the comparator output from • Application Notes
continuously changing state because of small
perturbations (noise) at the input (see Figure 20-2).
• Webinars
FIGURE 20-2: HYSTERESIS CONTROL • All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
Output • Development Tools
Hysteresis Range
(5 mV/10 mV/20 mV)
Input

REGISTER 20-1: CMPxCON: COMPARATOR x CONTROL REGISTER
CMPON — CMPSIDL HYSSEL1 HYSSEL0 FLTREN FCLKSEL DACOE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 HC-0, HS R/W-0 R/W-0 R/W-0

INSEL1 INSEL0 EXTREF HYSPOL CMPSTAT ALTINP CMPPOL RANGE
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit

bit 15 CMPON: Comparator Operating Mode bit

1 = Comparator module is enabled
0 = Comparator module is disabled (reduces power consumption)
bit 13 CMPSIDL: Comparator Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode.
If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables all comparators while in Idle mode.
bit 12-11 HYSSEL<1:0>: Comparator Hysteresis Select bits
11 = 20 mV hysteresis
00 = No hysteresis is selected
bit 10 FLTREN: Digital Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 9 FCLKSEL: Digital Filter and Pulse Stretcher Clock Select bit
1 = Digital filter and pulse stretcher operate with the PWM clock
0 = Digital filter and pulse stretcher operate with the system clock
bit 8 DACOE: DACx Output Enable bit
1 = DACx analog voltage is connected to the DACOUTx pin(1)
0 = DACx analog voltage is not connected to the DACOUTx pin
bit 7-6 INSEL<1:0>: Input Source Select for Comparator bits
If ALTINP = 0, Select from Comparator Inputs:
11 = Selects CMPxD input pin
10 = Selects CMPxC input pin
01 = Selects CMPxB input pin
00 = Selects CMPxA input pin
If ALTINP = 1, Select from Alternate Inputs:
11 = Reserved
10 = Reserved
01 = Selects PGA2 output
00 = Selects PGA1 output
Note 1: DACOUTx can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DACx output by setting their respective DACOE bit.

REGISTER 20-1: CMPxCON: COMPARATOR x CONTROL REGISTER (CONTINUED)
bit 5 EXTREF: Enable External Reference bit
1 = External source provides reference to DACx (maximum DAC voltage is determined by the external
voltage source)
0 = AVDD provides reference to DACx (maximum DAC voltage is AVDD)
bit 4 HYSPOL: Comparator Hysteresis Polarity Select bit
1 = Hysteresis is applied to the falling edge of the comparator output
0 = Hysteresis is applied to the rising edge of the comparator output
bit 3 CMPSTAT: Comparator Current State bit
Reflects the current output state of Comparator x, including the setting of the CMPPOL bit.
bit 2 ALTINP: Alternate Input Select bit
1 = INSEL<1:0> bits select alternate inputs
0 = INSEL<1:0> bits select comparator inputs
bit 1 CMPPOL: Comparator Output Polarity Control bit
1 = Output is inverted
0 = Output is non-inverted
bit 0 RANGE: DACx Output Voltage Range Select bit
1 = AVDD is the maximum DACx output voltage
0 = Unimplemented, do not use
Note 1: DACOUTx can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DACx output by setting their respective DACOE bit.

REGISTER 20-2: CMPxDAC: COMPARATOR x DAC CONTROL REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — CMREF<11:8>
bit 15 bit 8

CMREF<7:0>
bit 7 bit 0
Legend:

bit 11-0 CMREF<11:0>: Comparator Reference Voltage Select bits
111111111111
•
•
• = ([CMREF<11:0>] * (AVDD)/4096) volts (EXTREF = 0)
• or ([CMREF<11:0>] * (EXTREF)/4096) volts (EXTREF = 1)
•
•
000000000000

NOTES:

21.0 PROGRAMMABLE GAIN The dsPIC33EPXXGS50X family devices have two
Programmable Gain Amplifiers (PGA1, PGA2). The
AMPLIFIER (PGA)
PGA is an op amp-based, non-inverting amplifier with
Note 1: This data sheet summarizes the user-programmable gains. The output of the PGA can
features of the dsPIC33EPXXGS50X be connected to a number of dedicated Sample-and-
family of devices. It is not intended to be Hold inputs of the Analog-to-Digital Converter and/or to
a comprehensive reference source. To the high-speed analog comparator module. The PGA
complement the information in this data has five selectable gains and may be used as a ground
sheet, refer to “Programmable Gain referenced amplifier (single-ended) or used with an
Amplifier (PGA)” (DS70005146) in the independent ground reference point.
“dsPIC33/PIC24 Family Reference Man- Key features of the PGA module include:
ual”, which is available from the Microchip
• Single-Ended or Independent Ground Reference
web site (www.microchip.com).
• Selectable Gains: 4x, 8x, 16x, 32x and 64x
• High Gain Bandwidth
available on all devices. Refer to • Rail-to-Rail Output Voltage
Section 4.0 “Memory Organization” in • Wide Input Voltage Range
FIGURE 21-1: PGAx MODULE BLOCK DIAGRAM
GAIN<2:0> = 6
Gain of 64x
GAIN<2:0> = 5
Gain of 32x
GAIN<2:0> = 4
Gain of 16x
GAIN<2:0> = 3
Gain of 8x
GAIN<2:0> = 2
Gain of 4x
PGAx Negative Input – PGAxOUT

AMPx
PGAx Positive Input +
PGAx Calibrations<5:0>
Note 1: x = 1 and 2.

21.1 Module Description input source. To provide an independent ground
reference, PGAxN2 and PGAxN3 pins are available as
The Programmable Gain Amplifiers are used to amplify the negative input source to the PGAx module.
small voltages (i.e., voltages across burden/shunt
resistors) to improve the signal-to-noise ratio of the Note 1: Not all PGA positive/negative inputs are
measured signal. The PGAx output voltage can be available on all devices. Refer to the
read by any of the four dedicated Sample-and-Hold specific device pinout for available input
circuits on the ADC module. The output voltage can source pins.
also be fed to the comparator module for overcurrent/ The output voltage of the PGAx module can be
voltage protection. Figure 21-2 shows a functional connected to the DACOUTx pin by setting the
block diagram of the PGAx module. Refer to PGAOEN bit in the PGAxCON register. When the
Section 19.0 “High-Speed, 12-Bit Analog-to-Digital PGAOEN bit is enabled, the output voltage of PGA1 is
Converter (ADC)” and Section 20.0 “High-Speed connected to DACOUT1 and PGA2 is connected to
Analog Comparator” for more interconnection details. DACOUT2. For devices with a single DACOUTx pin,
The gain of the PGAx module is selectable via the the output voltage of PGA2 can be connected to
GAIN<2:0> bits in the PGAxCON register. There are DACOUT1 by configuring the DBCC Configuration bit
five selectable gains, ranging from 4x to 64x. The in the FDEVOPT register (FDEVOPT<6>).
SELPI<2:0> and SELNI<2:0> bits in the PGAxCON If both the DACx output voltage and PGAx output volt-
register select one of four positive/negative inputs to age are connected to the DACOUTx pin, the resulting
the PGAx module. For single-ended applications, the output voltage would be a combination of signals.
SELNI<2:0> bits will select the ground as the negative There is no assigned priority between the PGAx
module and the DACx module.
FIGURE 21-2: PGAx FUNCTIONAL BLOCK DIAGRAM
INSEL<1:0>
(CMPxCON)
SELPI<2:0>
PGAxCON(1) PGAxCAL(1)
+
PGAEN GAIN<2:0> –
PGAxP1(1)
DACx
PGAxP2(1) PGACAL<5:0>
PGAxP3(1)
CxCHS<1:0>
PGAxP4(1) (ADCON4H)
ADC
+
PGAx(1) S&H
GND
–
PGAxN2(1)
PGAxN3(1,3)
GND
PGAOEN
SELNI<2:0> To DACOUTx Pin(2)
Note 1: x = 1 and 2.
2: The DACOUT2 device pin is only available on 64-pin devices.
3: The PGAxN3 input is not available on 28-pin devices.

21.2 PGA Resources 21.2.1 KEY RESOURCES
uct page of the Microchip website for the devices listed • Application Notes
Manual” Sections
REGISTER 21-1: PGAxCON: PGAx CONTROL REGISTER

PGAEN PGAOEN SELPI2 SELPI1 SELPI0 SELNI2 SELNI1 SELNI0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — GAIN2 GAIN1 GAIN0
bit 7 bit 0
Legend:
bit 15 PGAEN: PGAx Enable bit

1 = PGAx module is enabled
0 = PGAx module is disabled (reduces power consumption)
bit 14 PGAOEN: PGAx Output Enable bit
1 = PGAx output is connected to the DACOUTx pin
0 = PGAx output is not connected to the DACOUTx pin
bit 13-11 SELPI<2:0>: PGAx Positive Input Selection bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = PGAxP4
010 = PGAxP3
001 = PGAxP2
000 = PGAxP1
bit 10-8 SELNI<2:0>: PGAx Negative Input Selection bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = Ground (Single-Ended mode)
010 = PGAxN3
001 = PGAxN2
000 = Ground (Single-Ended mode)

REGISTER 21-1: PGAxCON: PGAx CONTROL REGISTER (CONTINUED)
bit 2-0 GAIN<2:0>: PGAx Gain Selection bits
111 = Reserved
110 = Gain of 64x
101 = Gain of 32x
100 = Gain of 16x
011 = Gain of 8x
010 = Gain of 4x
001 = Reserved
000 = Reserved
REGISTER 21-2: PGAxCAL: PGAx CALIBRATION REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — PGACAL<5:0>
bit 7 bit 0
Legend:

bit 5-0 PGACAL<5:0>: PGAx Offset Calibration bits
The calibration values for PGA1 and PGA2 must be copied from Flash addresses, 0x800E48 and
0x800E4C, respectively, into these bits before the module is enabled. Refer to the calibration data
address table (Table 23-3) in Section 23.0 “Special Features” for more information.

22.0 CONSTANT-CURRENT 22.1 Features Overview
SOURCE The constant-current source module offers the following
major features:
features of the dsPIC33EPXXGS50X • Constant-Current Generator (10 µA nominal)
family of devices. It is not intended to be • Internal Selectable Connection to One of Four Pins
a comprehensive reference source. To • Enable/Disable Bit
sheet, refer to the related section of the 22.2 Module Description
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip Figure 22-1 shows a functional block diagram of the
web site (www.microchip.com). constant-current source module. It consists of a preci-
2: Some registers and associated bits sion current generator with a nominal value of 10 µA.
described in this section may not be The module can be enabled and disabled using the
available on all devices. Refer to ISRCEN bit in the ISRCCON register. The output of
Section 4.0 “Memory Organization” in the current generator is internally connected to a
this data sheet for device-specific register device pin. The dsPIC33EPXXGS50X family can have
and bit information. up to 4 selectable current source pins. The
OUTSEL<2:0> bits in the ISRCCON register allow
The constant-current source module is a precision selection of the target pin.
current generator and is used in conjunction with the The current source is calibrated during testing.
ADC module to measure the resistance of external
resistors connected to device pins.
FIGURE 22-1: CONSTANT-CURRENT SOURCE MODULE BLOCK DIAGRAM
Constant-Current Source
ISRC1
M ISRC2
U
X ISRC3
ISRC4
ISRCEN
OUTSEL<2:0>

22.3 Current Source Control Register
REGISTER 22-1: ISRCCON: CONSTANT-CURRENT SOURCE CONTROL REGISTER
R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
ISRCEN — — — — OUTSEL2 OUTSEL1 OUTSEL0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — ISRCCAL5 ISRCCAL4 ISRCCAL3 ISRCCAL2 ISRCCAL1 ISRCCAL0
bit 7 bit 0
Legend:
bit 15 ISRCEN: Constant-Current Source Enable bit

1 = Current source is enabled
0 = Current source is disabled
bit 10-8 OUTSEL<2:0>: Output Constant-Current Select bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Input pin, ISRC4 (AN4)
000 = No output is selected
bit 5-0 ISRCCAL<5:0>: Constant-Current Source Calibration bits
The calibration value must be copied from Flash address, 0x800E78, into these bits before the
module is enabled. Refer to the calibration data address table (Table 23-3) in Section 23.0 “Special
Features” for more information.

23.0 SPECIAL FEATURES 23.1 Configuration Bits
Note: This data sheet summarizes the features In dsPIC33EPXXGS50X family devices, the Configu-
of the dsPIC33EPXXGS50X family of ration Words are implemented as volatile memory. This
devices. It is not intended to be a compre- means that configuration data must be programmed
hensive reference source. To complement each time the device is powered up. Configuration data
the information in this data sheet, refer to is stored at the end of the on-chip program memory
the related section of the “dsPIC33/PIC24 space, known as the Flash Configuration Words. Their
Family Reference Manual”, which is specific locations are shown in Table 23-1 with detailed
available from the Microchip web site descriptions in Table 23-2. The configuration data is
(www.microchip.com). automatically loaded from the Flash Configuration
Words to the proper Configuration Shadow registers
The dsPIC33EPXXGS50X family devices include during device Resets.
several features intended to maximize application For devices operating in Dual Partition modes, the
flexibility and reliability, and minimize cost through BSEQx bits (FBTSEQ<11:0>) determine which panel is
elimination of external components. These are: the Active Partition at start-up and the Configuration
• Flexible Configuration Words from that panel are loaded into the Configuration
• Watchdog Timer (WDT) Shadow registers.
• Code Protection and CodeGuard™ Security Note: Configuration data is reloaded on all types
• JTAG Boundary Scan Interface of device Resets.
• In-Circuit Serial Programming™ (ICSP™)
When creating applications for these devices, users
• In-Circuit Emulation should always specifically allocate the location of the
• Brown-out Reset (BOR) Flash Configuration Words for configuration data in
their code for the compiler. This is to make certain that
program code is not stored in this address when the
code is compiled. Program code executing out of
configuration space will cause a device Reset.
Note: Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words.

CONFIGURATION REGISTER MAP(3)
DS70005127D-page 278
TABLE 23-1:
Device
Memory
Name Address Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Size
(Kbytes)
002B80 16
FSEC 005780 32 — AIVTDIS — — — CSS<2:0> CWRP GSS<1:0> GWRP — BSEN BSS<1:0> BWRP
00AF80 64
002B90 16
FBSLIM 005790 32 — — — — BSLIM<12:0>

00AF90 64
002B94 16
FSIGN 005794 32 — Reserved(2) — — — — — — — — — — — — — — —

00AF94 64
002B98 16
FOSCSEL 005798 32 — — — — — — — — — IESO — — — — FNOSC<2:0>

00AF98 64
002B9C 16
FOSC 00579C 32 — — — — — — — — PLLKEN FCKSM<1:0> IOL1WAY — — OSCIOFNC POSCMD<1:0>

00AF9C 64
002BA0 16
FWDT 0057A0 32 — — — — — — — WDTWIN<1:0> WINDIS WDTEN<1:0> WDTPRE WDTPOST<3:0>

00AFA0 64
002BA4 16
FPOR 0057A4 32 — — — — — — — — — — — — — — — — Reserved(1)

00AFA4 64
002BA8 16
FICD 0057A8 32 — BTSWP — — — — — — — Reserved(1) — JTAGEN — — — ICS<1:0>

00AFA8 64
Note 1: These bits are reserved and must be programmed as ‘1’.

2: This bit is reserved and must be programmed as ‘0’.
3: When operating in Dual Partition mode, each partition will have dedicated Configuration registers. On a device Reset, the configuration values of the Active Partition are read at start-up, but during a soft
swap condition, the configuration settings of the newly Active Partition are ignored.
4: FBOOT resides in configuration memory space.
CONFIGURATION REGISTER MAP(3) (CONTINUED)
TABLE 23-1:
Device
Memory
Name Address Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Size
(Kbytes)
FDEVOPT 002BAC 16
0057AC 32 — — — — — — — — — — DBCC — ALTI2C2 ALTI2C1 Reserved(1) — PWMLOCK

00AFAC 64
FALTREG 002BB0 16
0057B0 32 — — — — — — — — — — CTXT2<2:0> — CTXT1<2:0>

00AFB0 64
FBTSEQ 002BFC 16
0057FC 32 IBSEQ<11:0> BSEQ<11:0>
00AFFC 64
FBOOT(4) 801000 — — — — — — — — — — — — — — — — BTMODE<1:0>

Note 1: These bits are reserved and must be programmed as ‘1’.
2: This bit is reserved and must be programmed as ‘0’.
3: When operating in Dual Partition mode, each partition will have dedicated Configuration registers. On a device Reset, the configuration values of the Active Partition are read at start-up, but during a soft
swap condition, the configuration settings of the newly Active Partition are ignored.
4: FBOOT resides in configuration memory space.
DS70005127D-page 279
TABLE 23-2: CONFIGURATION BITS DESCRIPTION
Bit Field Description
BSS<1:0> Boot Segment Code-Protect Level bits
11 = Boot Segment is not code-protected other than BWRP
10 = Standard security
0x = High security
BSEN Boot Segment Control bit
1 = No Boot Segment is enabled
0 = Boot Segment size is determined by the BSLIM<12:0> bits
BWRP Boot Segment Write-Protect bit
1 = Boot Segment can be written
0 = Boot Segment is write-protected
BSLIM<12:0> Boot Segment Flash Page Address Limit bits
Contains the last active Boot Segment page. The value to be programmed is the inverted
page address, such that programming additional ‘0’s can only increase the Boot Segment
size (i.e., 0x1FFD = 2 Pages or 1024 IW).
GSS<1:0> General Segment Code-Protect Level bits
11 = User program memory is not code-protected
0x = High security
GWRP General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
CWRP Configuration Segment Write-Protect bit
1 = Configuration data is not write-protected
0 = Configuration data is write-protected
CSS<2:0> Configuration Segment Code-Protect Level bits
111 = Configuration data is not code-protected
10x = Enhanced security
0xx = High security
BTSWP BOOTSWP Instruction Enable/Disable bit
1 = BOOTSWP instruction is disabled
0 = BOOTSWP instruction is enabled
BSEQ<11:0> Boot Sequence Number bits (Dual Partition modes only)
Relative value defining which partition will be active after device Reset; the partition
containing a lower boot number will be active.
IBSEQ<11:0> Inverse Boot Sequence Number bits (Dual Partition modes only)
The one’s complement of BSEQ<11:0>; must be calculated by the user and written for
device programming. If BSEQx and IBSEQx are not complements of each other, the Boot
Sequence Number is considered to be invalid.
AIVTDIS(1) Alternate Interrupt Vector Table bit
1 = Alternate Interrupt Vector Table is disabled
0 = Alternate Interrupt Vector Table is enabled if INTCON2<8> = 1
IESO Two-Speed Oscillator Start-up Enable bit
1 = Starts up device with FRC, then automatically switches to the user-selected oscillator
source when ready
0 = Starts up device with the user-selected oscillator source
PWMLOCK PWMx Lock Enable bit
1 = Certain PWMx registers may only be written after a key sequence
0 = PWMx registers may be written without a key sequence
Note 1: The Boot Segment must be present to use the Alternate Interrupt Vector Table.

TABLE 23-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)
FNOSC<2:0> Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Fast RC Oscillator with Divide-by-16
100 = Reserved; do not use
011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)
001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL)
FCKSM<1:0> Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY Peripheral Pin Select Configuration bit
1 = Allows only one reconfiguration
0 = Allows multiple reconfigurations
OSCIOFNC OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is a general purpose digital I/O pin
POSCMD<1:0> Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
WDTEN<1:0> Watchdog Timer Enable bits
11 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the
SWDTEN bit in the RCON register will have no effect)
10 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by
clearing the SWDTEN bit in the RCON register)
01 = Watchdog Timer is enabled only while device is active and is disabled while in Sleep
mode; software control is disabled in this mode
00 = Watchdog Timer and SWDTEN bit are disabled
WINDIS Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
PLLKEN PLL Lock Enable bit
1 = PLL lock is enabled
0 = PLL lock is disabled
WDTPRE Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST<3:0> Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1

TABLE 23-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)
WDTWIN<1:0> Watchdog Timer Window Select bits
11 = WDT window is 25% of the WDT period
10 = WDT window is 37.5% of the WDT period
ALTI2C1 Alternate I2C1 Pin bit
1 = I2C1 is mapped to the SDA1/SCL1 pins
0 = I2C1 is mapped to the ASDA1/ASCL1 pins
ALTI2C2 Alternate I2C2 Pin bit
1 = I2C2 is mapped to the SDA2/SCL2 pins
0 = I2C2 is mapped to the ASDA2/ASCL2 pins
JTAGEN JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
ICS<1:0> ICD Communication Channel Select bits
11 = Communicates on PGEC1 and PGED1
00 = Reserved, do not use
DBCC DACx Output Cross Connection Select bit
1 = No cross connection between DAC outputs
0 = Interconnects DACOUT1 and DACOUT2
CTXT1<2:0> Alternate Working Register Set 1 Interrupt Priority Level (IPL) Select bits
111 = Reserved
110 = Assigned to IPL of 7
CTXT2<2:0> Alternate Working Register Set 2 Interrupt Priority Level (IPL) Select bits
111 = Reserved
BTMODE<1:0> Boot Mode Configuration bits
11 = Single Partition mode
10 = Dual Partition mode
01 = Protected Dual Partition mode
00 = Privileged Dual Partition mode

23.2 Device Calibration and The dsPIC33EPXXGS50X devices have two identifica-
Identification tion registers near the end of configuration memory
space that store the Device ID (DEVID) and Device
The PGAx and current source modules on the Revision (DEVREV). These registers are used to deter-
dsPIC33EPXXGS50X family devices require Calibra- mine the mask, variant and manufacturing information
tion Data registers to improve performance of the about the device. These registers are read-only and
module over a wide operating range. These Calibration are shown in Register 23-1 and Register 23-2.
registers are read-only and are stored in configuration
memory space. Prior to enabling the module, the
calibration data must be read (TBLPAG and Table
Read instruction) and loaded into its respective SFR
registers. The device calibration addresses are shown
in Table 23-3.
TABLE 23-3: DEVICE CALIBRATION ADDRESSES(1)

Calibration
Address Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
PGA1CAL 800E48 — — — — — — — — — — — PGA1 Calibration Data

PGA2CAL 800E4C — — — — — — — — — — — PGA2 Calibration Data
ISRCCAL 800E78 — — — — — — — — — — — Current Source Calibration Data
Note 1: The calibration data must be copied into its respective registers prior to enabling the module.

REGISTER 23-1: DEVID: DEVICE ID REGISTER
R R R R R R R R
DEVID<23:16>
bit 23 bit 16
R R R R R R R R
DEVID<15:8>
bit 15 bit 8
R R R R R R R R
DEVID<7:0>
bit 7 bit 0
Legend: R = Read-Only bit U = Unimplemented bit
bit 23-0 DEVID<23:0>: Device Identifier bits
REGISTER 23-2: DEVREV: DEVICE REVISION REGISTER

R R R R R R R R
DEVREV<23:16>
bit 23 bit 16
R R R R R R R R
DEVREV<15:8>
bit 15 bit 8
R R R R R R R R
DEVREV<7:0>
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit
bit 23-0 DEVREV<23:0>: Device Revision bits

23.3 User OTP Memory 23.5 Brown-out Reset (BOR)
dsPIC33EPXXGS50X family devices contain 64 words The Brown-out Reset (BOR) module is based on an
of User One-Time-Programmable (OTP) memory, internal voltage reference circuit that monitors the reg-
located at addresses, 0x800F80 through 0x800FFE. ulated supply voltage, VCAP. The main purpose of the
The User OTP Words can be used for storing checksum, BOR module is to generate a device Reset when a
code revisions, product information, such as serial num- brown-out condition occurs. Brown-out conditions are
bers, system manufacturing dates, manufacturing lot generally caused by glitches on the AC mains (for
numbers and other application-specific information. example, missing portions of the AC cycle waveform
These words can only be written once at program time due to bad power transmission lines or voltage sags
and not at run time; they can be read at run time. due to excessive current draw when a large inductive
load is turned on).
23.4 On-Chip Voltage Regulator A BOR generates a Reset pulse which resets the
device. The BOR selects the clock source based on the
All the dsPIC33EPXXGS50X family devices power their
device Configuration bit values (FNOSC<2:0> and
core digital logic at a nominal 1.8V. This can create a
POSCMD<1:0>).
conflict for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system If an Oscillator mode is selected, the BOR activates the
design, all devices in the dsPIC33EPXXGS50X family Oscillator Start-up Timer (OST). The system clock is
incorporate an on-chip regulator that allows the device held until OST expires. If the PLL is used, the clock is
to run its core logic from VDD. held until the LOCK bit (OSCCON<5>) is ‘1’.
The regulator provides power to the core from the other Concurrently, the PWRT Time-out (TPWRT) is applied
VDD pins. A low-ESR (less than 1 Ohm) capacitor (such before the internal Reset is released. If TPWRT = 0 and a
as tantalum or ceramic) must be connected to the VCAP crystal oscillator is being used, then a nominal delay of
pin (Figure 23-1). This helps to maintain the stability of TFSCM is applied. The total delay in this case is TFSCM.
the regulator. The recommended value for the filter Refer to Parameter SY35 in Table 26-23 of Section 26.0
capacitor is provided in Table 26-5, located in “Electrical Characteristics” for specific TFSCM values.
Section 26.0 “Electrical Characteristics”. The BOR status bit (RCON<1>) is set to indicate that a
Note: It is important for the low-ESR capacitor to BOR has occurred. The BOR circuit continues to oper-
be placed as close as possible to the VCAP ate while in Sleep or Idle modes and resets the device
pin. should VDD fall below the BOR threshold voltage.
FIGURE 23-1: CONNECTIONS FOR THE

ON-CHIP VOLTAGE
REGULATOR(1,2,3)
3.3V
dsPIC33EP
VDD
VCAP
CEFC
VSS
Note 1: These are typical operating voltages.

Refer to Table 26-5 located in
Section 26.0 “Electrical Characteris-
tics” for the full operating ranges of VDD
and VCAP.
2: It is important for the low-ESR capacitor
to be placed as close as possible to the
VCAP pin.
3: Typical VCAP pin voltage = 1.8V when
VDD ≥ VDDMIN.

23.6 Watchdog Timer (WDT) 23.6.2 SLEEP AND IDLE MODES
For dsPIC33EPXXGS50X family devices, the WDT is If the WDT is enabled, it continues to run during Sleep or
driven by the LPRC oscillator. When the WDT is Idle modes. When the WDT time-out occurs, the device
enabled, the clock source is also enabled. wakes and code execution continues from where the
PWRSAV instruction was executed. The corresponding
23.6.1 PRESCALER/POSTSCALER SLEEP or IDLE bit (RCON<3:2>) needs to be cleared in
software after the device wakes up.
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either 23.6.3 ENABLING WDT
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration The WDT is enabled or disabled by the WDTEN<1:0>
bit. With a 32 kHz input, the prescaler yields a WDT Configuration bits in the FWDT Configuration register.
Time-out Period (TWDT), as shown in Parameter SY12 When the WDTEN<1:0> Configuration bits have been
in Table 26-23. programmed to ‘0b11’, the WDT is always enabled.
A variable postscaler divides down the WDT prescaler The WDT can be optionally controlled in software
output and allows for a wide range of time-out periods. when the WDTEN<1:0> Configuration bits have been
The postscaler is controlled by the WDTPOST<3:0> programmed to ‘0b10’. The WDT is enabled in soft-
Configuration bits (FWDT<3:0>), which allow the ware by setting the SWDTEN control bit (RCON<5>).
selection of 16 settings, from 1:1 to 1:32,768. Using the The SWDTEN control bit is cleared on any device
prescaler and postscaler, time-out periods, ranges from Reset. The software WDT option allows the user appli-
1 ms to 131 seconds can be achieved. cation to enable the WDT for critical code segments
and disables the WDT during non-critical segments for
The WDT, prescaler and postscaler are reset: maximum power savings.
• On any device Reset The WDT Time-out flag bit, WDTO (RCON<4>), is not
• On the completion of a clock switch, whether automatically cleared following a WDT time-out. To
invoked by software (i.e., setting the OSWEN bit detect subsequent WDT events, the flag must be
after changing the NOSCx bits) or by hardware cleared in software.
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed 23.6.4 WDT WINDOW
(i.e., Sleep or Idle mode is entered) The Watchdog Timer has an optional Windowed mode,
• When the device exits Sleep or Idle mode to enabled by programming the WINDIS bit in the WDT
resume normal operation Configuration register (FWDT<7>). In the Windowed
• By a CLRWDT instruction during normal execution mode (WINDIS = 0), the WDT should be cleared based
on the settings in the programmable Watchdog Timer
Note: The CLRWDT and PWRSAV instructions
Window select bits (WDTWIN<1:0>).
clear the prescaler and postscaler counts
when executed.
FIGURE 23-2: WDT BLOCK DIAGRAM
All Device Resets

Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
Watchdog Timer
Sleep/Idle
WDTPRE WDTPOST<3:0>
SWDTEN WDT
WDTEN<1:0> Wake-up
1
RS RS
Prescaler Postscaler
LPRC Clock (Divide-by-N1) (Divide-by-N2) WDT
0 Reset
WINDIS
WDT Window Select
WDTWIN<1:0>
CLRWDT Instruction

23.7 JTAG Interface 23.10 Code Protection and
The dsPIC33EPXXGS50X family devices implement a
CodeGuard™ Security
JTAG interface, which supports boundary scan device dsPIC33EPXXGS50X devices offer multiple levels of
testing. Detailed information on this interface is security for protecting individual intellectual property. The
provided in future revisions of the document. program Flash protection can be broken up into three
Note: Refer to “Programming and Diagnostics” segments: Boot Segment (BS), General Segment (GS)
(DS70608) in the “dsPIC33/PIC24 Family and Configuration Segment (CS). Boot Segment has the
Reference Manual” for further information on highest security privilege and can be thought to have
usage, configuration and operation of the limited restrictions when accessing other segments.
JTAG interface. General Segment has the least security and is intended
for the end user system code. Configuration Segment
contains only the device user configuration data which is
23.8 In-Circuit Serial Programming™ located at the end of the program memory space.
The dsPIC33EPXXGS50X family devices can be seri- The code protection features are controlled by the
ally programmed while in the end application circuit. This Configuration registers, FSEC and FBSLIM. The FSEC
is done with two lines for clock and data, and three other register controls the code-protect level for each
lines for power, ground and the programming sequence. segment and if that segment is write-protected. The
Serial programming allows customers to manufacture size of BS and GS will depend on the BSLIM<12:0>
boards with unprogrammed devices and then program setting and if the Alternate Interrupt Vector Table (AIVT)
the device just before shipping the product. Serial is enabled. The BSLIM<12:0> bits define the number of
programming also allows the most recent firmware or a pages for BS with each page containing 512 IW. The
custom firmware to be programmed. Refer to the smallest BS size is one page, which will consist of the
“dsPIC33E/PIC24E Flash Programming Specification Interrupt Vector Table (IVT) and 256 IW of code
for Devices with Volatile Configuration Bits” (DS70663) protection.
for details about In-Circuit Serial Programming™ If the AIVT is enabled, the last page of BS will contain
(ICSP™). the AIVT and will not contain any BS code. With AIVT
Any of the three pairs of programming clock/data pins enabled, the smallest BS size is now two pages
can be used: (1024 IW), with one page for the IVT and BS code, and
• PGEC1 and PGED1 the other page for the AIVT. Write protection of the BS
does not cover the AIVT. The last page of BS can
• PGEC2 and PGED2
always be programmed or erased by BS code. The
• PGEC3 and PGED3 General Segment will start at the next page and will
consume the rest of program Flash except for the Flash
23.9 In-Circuit Debugger Configuration Words. The IVT will assume GS security
only if BS is not enabled. The IVT is protected from
When MPLAB® ICD 3 or REAL ICE™ emulator is
being programmed or page erased when either
selected as a debugger, the in-circuit debugging function-
security segment has enabled write protection.
ality is enabled. This function allows simple debugging
functions when used with MPLAB IDE. Debugging func- Note: Refer to “CodeGuard™ Intermediate
tionality is controlled through the PGECx (Emulation/ Security” (DS70005182) in the “dsPIC33/
Debug Clock) and PGEDx (Emulation/Debug Data) pin PIC24 Family Reference Manual” for further
functions. information on usage, configuration and
Any of the three pairs of debugging clock/data pins can operation of CodeGuard Security.
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins (PGECx and PGEDx).

The different device security segments are shown in Privileged Dual Partition mode performs the same
Figure 23-3. Here, all three segments are shown but function as Protected Dual Partition mode, except
are not required. If only basic code protection is additional constraints are applied in an effort to prevent
required, then GS can be enabled independently or code in the Boot Segment and General Segment from
combined with CS, if desired. being used against each other.
FIGURE 23-3: SECURITY SEGMENTS FIGURE 23-4: SECURITY SEGMENTS

EXAMPLE FOR EXAMPLE FOR
dsPIC33EP64GS50X dsPIC33EP64GS50X
DEVICES DEVICES (DUAL
PARTITION MODES)
0x000000
IVT 0x000000
0x000200 IVT
IVT and AIVT 0x000200
Assume BS IVT and AIVT
BS Protection Assume BS
BS Protection
AIVT + 256 IW(2)
BSLIM<12:0> AIVT + 256IW(2)
BSLIM<12:0>
GS
GS
CS(1) 0x00B000
CS(1)
0x005800
Unimplemented
Note 1: If CS is write-protected, the last page (GS (Read ‘0’s)
+ CS) of program memory will be protected 0x400000
from an erase condition. IVT
2: The last half (256 IW) of the last page of 0x400200
BS is unusable program memory.
IVT and AIVT
Assume BS
BS Protection
dsPIC33EP64GS50X family devices can be operated
in Dual Partition mode, where security is required for
AIVT + 256 IW(2)
each partition. When operating in Dual Partition mode,
BSLIM<12:0>
the Active and Inactive Partitions both contain unique
copies of the Reset vector, Interrupt Vector Tables (IVT
and AIVT, if enabled) and the Flash Configuration
GS
Words. Both partitions have the three security
segments described previously. Code may not be
executed from the Inactive Partition, but it may be
programmed by, and read from, the Active Partition, CS(1)
0x405800
subject to defined code protection. Figure 23-4 shows
the different security segments for a device operating in
Dual Partition mode. Note 1: If CS is write-protected, the last page
(GS + CS) of program memory will be
The device may also operate in a Protected Dual protected from an erase condition.
Partition mode or in Privileged Dual Partition mode. In 2: The last half (256 IW) of the last page of
Protected Dual Partition mode, Partition 1 is perma- BS is unusable program memory.
nently erase/write-protected. This implementation
allows for a “Factory Default” mode, which provides a
fail-safe backup image to be stored in Partition 1. For
example, a fail-safe bootloader can be placed in
Partition 1, along with a fail-safe backup code image,
which can be used or rewritten into Partition 2 in the
event of a failed Flash update to Partition 2.

24.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
Note: This data sheet summarizes the • The W register (with or without an address
features of the dsPIC33EPXXGS50X modifier) or file register (specified by the value of
family of devices. It is not intended to be a ‘Ws’ or ‘f’)
comprehensive reference source. To
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
sheet, refer to the related section of the
register ‘Wb’)
“dsPIC33/PIC24 Family Reference
Manual”, which is available from the The literal instructions that involve data movement can
Microchip web site (www.microchip.com). use some of the following operands:
• A literal value to be loaded into a W register or file
The dsPIC33EP instruction set is almost identical to
register (specified by ‘k’)
that of the dsPIC30F and dsPIC33F.
• The W register or file register where the literal
Most instructions are a single program memory word value is to be loaded (specified by ‘Wb’ or ‘f’)
(24 bits). Only three instructions require two program
memory locations. However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction • The first source operand, which is a register ‘Wb’
type and one or more operands, which further specify without any address modifier
the operation of the instruction. • The second source operand, which is a literal
value
The instruction set is highly orthogonal and is grouped
into five basic categories: • The destination of the result (only if not the same
as the first source operand), which is typically a
• Word or byte-oriented operations register ‘Wd’ with or without an address modifier
• Bit-oriented operations
The MAC class of DSP instructions can use some of the
• Literal operations following operands:
• DSP operations
• The accumulator (A or B) to be used (required
• Control operations operand)
Table 24-1 lists the general symbols used in describing • The W registers to be used as the two operands
the instructions. • The X and Y address space prefetch operations
The dsPIC33E instruction set summary in Table 24-2 • The X and Y address space prefetch destinations
lists all the instructions, along with the status flags • The accumulator write back destination
affected by each instruction.
The other DSP instructions do not involve any
Most word or byte-oriented W register instructions multiplication and can include:
(including barrel shift instructions) have three
operands: • The accumulator to be used (required)
• The source or destination operand (designated as
• The first source operand, which is typically a
Wso or Wdo, respectively) with or without an
register ‘Wb’ without any address modifier
address modifier
• The second source operand, which is typically a
• The amount of shift specified by a W register ‘Wn’
register ‘Ws’ with or without an address modifier
or a literal value
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier The control instructions can use some of the following
operands:
However, word or byte-oriented file register instructions
have two operands: • A program memory address
• The mode of the table read and table write
• The file register specified by the value ‘f’
instructions
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’

Most instructions are a single word. Certain double-word with the additional instruction cycle(s) executed as a
instructions are designed to provide all the required NOP. Certain instructions that involve skipping over the
information in these 48 bits. In the second word, the subsequent instruction require either two or three cycles
8 MSbs are ‘0’s. If this second word is executed as an if the skip is performed, depending on whether the
instruction (by itself), it executes as a NOP. instruction being skipped is a single-word or two-word
The double-word instructions execute in two instruction instruction. Moreover, double-word moves require two
cycles. cycles.
Most single-word instructions are executed in a single Note: For more details on the instruction set,
instruction cycle, unless a conditional test is true or the refer to the “16-bit MCU and DSC
Program Counter is changed as a result of the Programmer’s Reference Manual”
instruction, or a PSV or table read is performed. In these (DS70157).
cases, the execution takes multiple instruction cycles,
TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description
#text Means literal defined by “text”

(text) Means “content of text”
[text] Means “the location addressed by text”
{} Optional field or operation
a  {b, c, d} a is selected from the set of values b, c, d
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
Acc One of two accumulators {A, B}
AWB Accumulator write-back destination address register {W13, [W13]+ = 2}
bit4 4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address {0x0000...0x1FFF}
lit1 1-bit unsigned literal {0,1}
lit4 4-bit unsigned literal {0...15}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None Field does not require an entry, can be blank
OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Wb Base W register {W0...W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register 
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor Working register pair (direct addressing)

TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field Description
Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions 
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions 
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn One of 16 Working registers {W0...W15}
Wnd One of 16 Destination Working registers {W0...W15}
Wns One of 16 Source Working registers {W0...W15}
WREG W0 (Working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register 
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X Data Space Prefetch Address register for DSP instructions
 {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Wy Y Data Space Prefetch Address register for DSP instructions
 {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd Y Data Space Prefetch Destination register for DSP instructions {W4...W7}

TABLE 24-2: INSTRUCTION SET OVERVIEW
Base
Assembly # of # of Status Flags
Instr Assembly Syntax Description
Mnemonic Words Cycles(1) Affected
#
1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB

ADD f f = f + WREG 1 1 C,DC,N,OV,Z
ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB
2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z
3 AND AND f f = f .AND. WREG 1 1 N,Z
AND f,WREG WREG = f .AND. WREG 1 1 N,Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z
4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z
5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
6 BOOTSWP BOOTSWP Swap the active and inactive program 1 2 None
Flash Space
7 BRA BRA C,Expr Branch if Carry 1 1 (4) None
BRA GE,Expr Branch if greater than or equal 1 1 (4) None
BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (4) None
BRA GT,Expr Branch if greater than 1 1 (4) None
BRA GTU,Expr Branch if unsigned greater than 1 1 (4) None
BRA LE,Expr Branch if less than or equal 1 1 (4) None
BRA LEU,Expr Branch if unsigned less than or equal 1 1 (4) None
BRA LT,Expr Branch if less than 1 1 (4) None
BRA LTU,Expr Branch if unsigned less than 1 1 (4) None
BRA N,Expr Branch if Negative 1 1 (4) None
BRA NC,Expr Branch if Not Carry 1 1 (4) None
BRA NN,Expr Branch if Not Negative 1 1 (4) None
BRA NOV,Expr Branch if Not Overflow 1 1 (4) None
BRA NZ,Expr Branch if Not Zero 1 1 (4) None
BRA OA,Expr Branch if Accumulator A overflow 1 1 (4) None
BRA OB,Expr Branch if Accumulator B overflow 1 1 (4) None
BRA OV,Expr Branch if Overflow 1 1 (4) None
BRA SA,Expr Branch if Accumulator A saturated 1 1 (4) None
BRA SB,Expr Branch if Accumulator B saturated 1 1 (4) None
BRA Expr Branch Unconditionally 1 4 None
BRA Z,Expr Branch if Zero 1 1 (4) None
BRA Wn Computed Branch 1 4 None
8 BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
Note 1: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.

TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
#
9 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None

BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
10 BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
11 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None
(2 or 3)
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None
(2 or 3)
12 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None
(2 or 3)
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None
(2 or 3)
13 BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
14 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
15 CALL CALL lit23 Call subroutine 2 4 SFA
CALL Wn Call indirect subroutine 1 4 SFA
CALL.L Wn Call indirect subroutine (long address) 1 4 SFA
16 CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB
17 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep
18 COM COM f f=f 1 1 N,Z
COM f,WREG WREG = f 1 1 N,Z
COM Ws,Wd Wd = Ws 1 1 N,Z
19 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z
CP Wb,#lit8 Compare Wb with lit8 1 1 C,DC,N,OV,Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z
20 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z
CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z
21 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,#lit8 Compare Wb with lit8, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z
(Wb – Ws – C)
22 CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, skip if = 1 1 None
(2 or 3)
CPBEQ CPBEQ Wb,Wn,Expr Compare Wb with Wn, branch if = 1 1 (5) None
23 CPSGT CPSGT Wb,Wn Compare Wb with Wn, skip if > 1 1 None
(2 or 3)
CPBGT CPBGT Wb,Wn,Expr Compare Wb with Wn, branch if > 1 1 (5) None
24 CPSLT CPSLT Wb,Wn Compare Wb with Wn, skip if < 1 1 None
(2 or 3)
CPBLT CPBLT Wb,Wn,Expr Compare Wb with Wn, branch if < 1 1 (5) None
25 CPSNE CPSNE Wb,Wn Compare Wb with Wn, skip if  1 1 None
(2 or 3)
CPBNE CPBNE Wb,Wn,Expr Compare Wb with Wn, branch if  1 1 (5) None

Base
#
26 CTXTSWP CTXTSWP #1it3 Switch CPU register context to context 1 2 None

defined by lit3
CTXTSWP Wn Switch CPU register context to context 1 2 None
defined by Wn
27 DAW DAW Wn Wn = decimal adjust Wn 1 1 C
28 DEC DEC f f=f–1 1 1 C,DC,N,OV,Z
DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z
DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z
29 DEC2 DEC2 f f=f–2 1 1 C,DC,N,OV,Z
DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z
30 DISI DISI #lit14 Disable Interrupts for k instruction cycles 1 1 None
31 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV
32 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV
33 DO DO #lit15,Expr Do code to PC + Expr, lit15 + 1 time 2 2 None
DO Wn,Expr Do code to PC + Expr, (Wn) + 1 time 2 2 None
34 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,
SA,SB,SAB
35 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,
SA,SB,SAB
36 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
37 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C
38 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
39 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
40 GOTO GOTO Expr Go to address 2 4 None
GOTO Wn Go to indirect 1 4 None
GOTO.L Wn Go to indirect (long address) 1 4 None
41 INC INC f f=f+1 1 1 C,DC,N,OV,Z
INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
42 INC2 INC2 f f=f+2 1 1 C,DC,N,OV,Z
INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z
43 IOR IOR f f = f .IOR. WREG 1 1 N,Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z
44 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
45 LNK LNK #lit14 Link Frame Pointer 1 1 SFA
46 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z
47 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB Multiply and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB

Base
#
48 MOV MOV f,Wn Move f to Wn 1 1 None

MOV f Move f to f 1 1 None
MOV f,WREG Move f to WREG 1 1 None
MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 None
MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None
49 MOVPAG MOVPAG #lit10,DSRPAG Move 10-bit literal to DSRPAG 1 1 None
MOVPAG #lit8,TBLPAG Move 8-bit literal to TBLPAG 1 1 None
MOVPAGW Ws, DSRPAG Move Ws<9:0> to DSRPAG 1 1 None
MOVPAGW Ws, TBLPAG Move Ws<7:0> to TBLPAG 1 1 None
50 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and store accumulator 1 1 None
51 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
52 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None
53 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
54 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None
signed(Ws)
MUL.SS Wb,Ws,Acc Accumulator = signed(Wb) * signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None
unsigned(Ws)
MUL.SU Wb,Ws,Acc Accumulator = signed(Wb) * 1 1 None
unsigned(Ws)
MUL.SU Wb,#lit5,Acc Accumulator = signed(Wb) * unsigned(lit5) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None
signed(Ws)
MUL.US Wb,Ws,Acc Accumulator = unsigned(Wb) * signed(Ws) 1 1 None
MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None
unsigned(Ws)
MUL.UU Wb,#lit5,Acc Accumulator = unsigned(Wb) * 1 1 None
unsigned(lit5)
MUL.UU Wb,Ws,Acc Accumulator = unsigned(Wb) * 1 1 None
unsigned(Ws)
MULW.SS Wb,Ws,Wnd Wnd = signed(Wb) * signed(Ws) 1 1 None
MULW.SU Wb,Ws,Wnd Wnd = signed(Wb) * unsigned(Ws) 1 1 None
MULW.US Wb,Ws,Wnd Wnd = unsigned(Wb) * signed(Ws) 1 1 None
MULW.UU Wb,Ws,Wnd Wnd = unsigned(Wb) * unsigned(Ws) 1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * 1 1 None
unsigned(lit5)
MUL.SU Wb,#lit5,Wnd Wnd = signed(Wb) * unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * 1 1 None
unsigned(lit5)
MUL.UU Wb,#lit5,Wnd Wnd = unsigned(Wb) * unsigned(lit5) 1 1 None
MUL f W3:W2 = f * WREG 1 1 None

Base
#
55 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB
NEG f f=f+1 1 1 C,DC,N,OV,Z
NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
56 NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
57 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None
W(nd):W(nd + 1)
POP.S Pop Shadow Registers 1 1 All
58 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack 1 2 None
(TOS)
PUSH.S Push Shadow Registers 1 1 None
59 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep
60 RCALL RCALL Expr Relative Call 1 4 SFA
RCALL Wn Computed Call 1 4 SFA
61 REPEAT REPEAT #lit15 Repeat Next Instruction lit15 + 1 time 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 time 1 1 None
62 RESET RESET Software device Reset 1 1 None
63 RETFIE RETFIE Return from interrupt 1 6 (5) SFA
64 RETLW RETLW #lit10,Wn Return with literal in Wn 1 6 (5) SFA
65 RETURN RETURN Return from Subroutine 1 6 (5) SFA
66 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z
67 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z
68 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z
69 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z
70 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None
SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None
71 SE SE Ws,Wnd Wnd = sign-extended Ws 1 1 C,N,Z
72 SETM SETM f f = 0xFFFF 1 1 None
SETM WREG WREG = 0xFFFF 1 1 None
SETM Ws Ws = 0xFFFF 1 1 None
73 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,
SA,SB,SAB
SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,
SA,SB,SAB

Base
#
74 SL SL f f = Left Shift f 1 1 C,N,OV,Z

SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z
75 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,
SA,SB,SAB
SUB f f = f – WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z
76 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z
77 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z
78 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z
79 SWAP SWAP.b Wn Wn = nibble swap Wn 1 1 None
SWAP Wn Wn = byte swap Wn 1 1 None
80 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 5 None
81 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 5 None
82 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
83 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
84 ULNK ULNK Unlink Frame Pointer 1 1 SFA
85 XOR XOR f f = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
86 ZE ZE Ws,Wnd Wnd = Zero-extend Ws 1 1 C,Z,N

NOTES:

25.0 DEVELOPMENT SUPPORT 25.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

25.2 MPLAB XC Compilers 25.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16 and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
• Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
25.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
25.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

25.6 MPLAB X SIM Software Simulator 25.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the
buffer and logic analyzer display extend the power of MPLAB IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 25.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
25.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the
programs all 8, 16 and 32-bit MCU, and DSC devices target via a Microchip debug (RJ-11) connector (com-
with the easy-to-use, powerful graphical user interface of patible with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 25.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display
downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod-
significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

25.11 Demonstration/Development 25.12 Third-Party Development Tools
Boards, Evaluation Kits and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and • Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

26.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the dsPIC33EPXXGS50X family electrical characteristics. Additional information
will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33EPXXGS50X family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(1)

Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(3)..................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(3) ................................................... -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(3) ................................................... -0.3V to +3.6V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2) ...........................................................................................................................300 mA
Maximum current sunk/sourced by any 4x I/O pin..................................................................................................15 mA
Maximum current sunk/sourced by any 8x I/O pin ..................................................................................................25 mA
Maximum current sunk by all ports(2) ....................................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those, or any other conditions
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 26-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.

26.1 DC Characteristics
TABLE 26-1: OPERATING MIPS vs. VOLTAGE

VDD Range Temperature Range Maximum MIPS
Characteristic
(in Volts) (in °C) dsPIC33EPXXGS50X Family
— 3.0V to 3.6V(1) -40°C to +85°C 70
— 3.0V to 3.6V(1) -40°C to +125°C 60
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators)
may have degraded performance. Device functionality is tested but not characterized. Refer to
Parameter BO10 in Table 26-13 for the minimum and maximum BOR values.
TABLE 26-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min. Typ. Max. Unit
Industrial Temperature Devices
Operating Junction Temperature Range TJ -40 — +125 °C
Operating Ambient Temperature Range TA -40 — +85 °C
Extended Temperature Devices
Operating Junction Temperature Range TJ -40 — +140 °C
Operating Ambient Temperature Range TA -40 — +125 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD –  IOH) PD PINT + PI/O W
I/O Pin Power Dissipation:
I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
TABLE 26-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ. Max. Unit Notes
Package Thermal Resistance, 64-Pin TQFP 10x10x1 mm JA 49.0 — °C/W 1
Package Thermal Resistance, 48-Pin TQFP 7x7x1.0 mm JA 63.0 — °C/W 1
Package Thermal Resistance, 44-Pin QFN 8x8 mm JA 29.0 — °C/W 1
Package Thermal Resistance, 44-Pin TQFP 10x10x1 mm JA 50.0 — °C/W 1
Package Thermal Resistance, 28-Pin QFN-S 6x6x0.9 mm JA 30.0 — °C/W 1
Package Thermal Resistance, 28-Pin UQFN 6x6x0.5 mm JA 26.0 — °C/W 1
Package Thermal Resistance, 28-Pin SOIC 7.50 mm JA 70.0 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.

TABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
Operating Voltage
DC10 VDD Supply Voltage 3.0 — 3.6 V
DC12 VDR (2)
RAM Retention Voltage 1.8 — — V -40ºC
2 — — +25ºC, +85ºC, +125ºC
DC16 VPOR VDD Start Voltage — — VSS V
to Ensure Internal
Power-on Reset Signal
DC17 SVDD VDD Rise Rate 1.0 — — V/ms 0V-3V in 3 ms
to Ensure Internal
Power-on Reset Signal
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators) may
have degraded performance. Device functionality is tested but not characterized. Refer to
Parameter BO10 in Table 26-13 for the minimum and maximum BOR values.
2: This is the limit to which VDD may be lowered and the RAM contents will always be retained.
TABLE 26-5: FILTER CAPACITOR (CEFC) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated):
Param
Symbol Characteristics Min. Typ. Max. Units Comments
No.
CEFC External Filter Capacitor 4.7 10 — F Capacitor must have a low
Value(1) series resistance (<1 ohm)
Note 1: Typical VCAP Voltage = 1.8 volts when VDD  VDDMIN.

TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
(unless otherwise stated)
DC CHARACTERISTICS
Parameter
Typ. Max. Units Conditions
No.
Operating Current (IDD)(1)
DC20d 7 12 mA -40°C
DC20a 7 12 mA +25°C
3.3V 10 MIPS
DC20b 7 12 mA +85°C
DC20c 7 12 mA +125°C
DC22d 11 19 mA -40°C
DC22a 11 19 mA +25°C
3.3V 20 MIPS
DC22b 11 19 mA +85°C
DC22c 11 19 mA +125°C
DC24d 19 30 mA -40°C
DC24a 19 30 mA +25°C
3.3V 40 MIPS
DC24b 19 30 mA +85°C
DC24c 19 30 mA +125°C
DC25d 26 41 mA -40°C
DC25a 26 41 mA +25°C
3.3V 60 MIPS
DC25b 26 41 mA +85°C
DC25c 26 41 mA +125°C
DC26d 30 46 mA -40°C
DC26a 30 46 mA +25°C 3.3V 70 MIPS
DC26b 30 46 mA +85°C
DC27d 51 81 mA -40°C
70 MIPS
DC27a 51 81 mA +25°C 3.3V
(Note 2)
DC27b 52 82 mA +85°C
Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from
rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating or being clocked (all defined PMDx bits are set)
• CPU is executing while(1) statement
• JTAG is disabled
2: For this specification, the following test conditions apply:
• APLL clock is enabled
• All 5 PWMs enabled and operating at maximum speed (PTCON2<2:0> = 000), PTPER = 1000h,
50% duty cycle
• All other peripherals are disabled (corresponding PMDx bits are set)

TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS
Parameter
No.
Idle Current (IIDLE)(1)
DC40d 2 4 mA -40°C
DC40a 2 4 mA +25°C
3.3V 10 MIPS
DC40b 2 4 mA +85°C
DC40c 2 4 mA +125°C
DC42d 3 6 mA -40°C
DC42a 3 6 mA +25°C
3.3V 20 MIPS
DC42b 3 6 mA +85°C
DC42c 3 6 mA +125°C
DC44d 6 12 mA -40°C
DC44a 6 12 mA +25°C
3.3V 40 MIPS
DC44b 6 12 mA +85°C
DC44c 6 12 mA +125°C
DC45d 8 15 mA -40°C
DC45a 8 15 mA +25°C
3.3V 60 MIPS
DC45b 8 15 mA +85°C
DC45c 8 15 mA +125°C
DC46d 10 20 mA -40°C
DC46a 10 20 mA +25°C 3.3V 70 MIPS
DC46b 10 20 mA +85°C
Note 1: Base Idle current (IIDLE) is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• The NVMSIDL bit (NVMCON<12>) = 1 (i.e., Flash regulator is set to standby while the device is in
Idle mode)
• The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to standby while the device is in
Sleep mode)

TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Parameter
No.
Power-Down Current (IPD)(1)
DC60d 12 100 A -40°C
DC60a 18 100 A +25°C
3.3V
DC60b 130 400 A +85°C
DC60c 500 1100 A +125°C
Note 1: IPD (Sleep) current is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• All peripheral modules are disabled (PMDx bits are all set)
• The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to standby while the device is in
Sleep mode)
• The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to standby while the device is in
Sleep mode)
TABLE 26-9: DC CHARACTERISTICS: WATCHDOG TIMER DELTA CURRENT (IWDT)(1)

DC CHARACTERISTICS
Parameter No. Typ. Max. Units Conditions
DC61d 13 50 A -40°C
DC61a 19 80 A +25°C
3.3V
DC61b 12 — A +85°C
DC61c 13 — A +125°C
Note 1: The IWDT current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current. All parameters are characterized but not tested during manufacturing.

TABLE 26-10: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
DC CHARACTERISTICS
Doze
Parameter No. Typ. Max. Units Conditions
Ratio
Doze Current (IDOZE)(1)
DC73a(2) 20 40 1:2 mA
-40°C 3.3V FOSC = 140 MHz
DC73g 9 20 1:128 mA
DC70a(2) 20 40 1:2 mA
+25°C 3.3V FOSC = 140 MHz
DC70g 9 20 1:128 mA
DC71a(2) 20 40 1:2 mA
+85°C 3.3V FOSC = 140 MHz
DC71g 9 20 1:128 mA
DC72a(2) 20 40 1:2 mA
+125°C 3.3V FOSC = 120 MHz
DC72g 9 20 1:128 mA
Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CPU, SRAM, program memory and data memory are operational
• CPU is executing while(1) statement
2: These parameter are characterized but not tested in manufacturing.

TABLE 26-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param
Symbol Characteristic Min. Typ.(1) Max. Units Conditions
No.
VIL Input Low Voltage
DI10 Any I/O Pin and MCLR VSS — 0.2 VDD V
DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMBus disabled
DI19 I/O Pins with SDAx, SCLx VSS — 0.8 V SMBus enabled
VIH Input High Voltage
DI20 I/O Pins Not 5V Tolerant(4) 0.8 VDD — VDD V
I/O Pins 5V Tolerant and 0.8 VDD — 5.5 V
MCLR(4)
5V Tolerant I/O Pins with 0.8 VDD — 5.5 V SMBus disabled
SDAx, SCLx(4)
5V Tolerant I/O Pins with 2.1 — 5.5 V SMBus enabled
SDAx, SCLx(4)
I/O Pins with SDAx, SCLx Not 0.8 VDD — VDD V SMBus disabled
5V Tolerant(4)
I/O Pins with SDAx, SCLx Not 2.1 — VDD V SMBus enabled
5V Tolerant(4)
DI30 ICNPU Input Change Notification 150 340 550 A VDD = 3.3V, VPIN = VSS
Pull-up Current
DI31 ICNPD Input Change Notification 20 60 100 A VDD = 3.3V, VPIN = VDD
Pull-Down Current(5)
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See the “Pin Diagrams” section for the 5V tolerant I/O pins.
5: VIL Source < (VSS – 0.3). Characterized but not tested.
6: VIH Source > (VDD + 0.3) for pins that are not 5V tolerant only.
7: Digital 5V tolerant pins do not have internal high-side diodes to VDD and cannot tolerate any “positive”
input injection current.
8: Injection Currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.

TABLE 26-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Param
No.
IIL Input Leakage Current(2,3)
DI50 I/O Pins 5V Tolerant(4) -1 — +1 A VSS  VPIN  VDD,
pin at high-impedance
DI51 I/O Pins Not 5V Tolerant(4) -1 — +1 A VSS  VPIN  VDD,
pin at high-impedance,
-40°C  TA  +85°C
DI51a I/O Pins Not 5V Tolerant(4) -1 — +1 A Analog pins shared with
external reference pins,
-40°C  TA  +85°C
DI51b I/O Pins Not 5V Tolerant(4) -1 — +1 A VSS  VPIN  VDD,
pin at high-impedance,
-40°C  TA  +125°C
DI51c I/O Pins Not 5V Tolerant(4) -1 — +1 A Analog pins shared with
external reference pins,
-40°C  TA  +125°C
DI55 MCLR -5 — +5 A VSS VPIN VDD
DI56 OSC1 -5 — +5 A VSS VPIN VDD,
XT and HS modes
voltages.

TABLE 26-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Param
No.
IICL Input Low Injection Current
DI60a 0 — -5(5,8) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP
and RB7
IICH Input High Injection Current
DI60b 0 — +5(6,7,8) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB7 and all 5V tolerant
pins(7)
IICT Total Input Injection Current
DI60c (sum of all I/O and control -20(9) — +20(9) mA Absolute instantaneous
pins) sum of all ± input injection
currents from all I/O pins
( | IICL | + | IICH | )  IICT
voltages.

TABLE 26-12: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
DO10 VOL Output Low Voltage — — 0.4 V VDD = 3.3V,
4x Sink Driver Pins(2) IOL  6 mA, -40°C  TA  +85°C,
IOL  5 mA, +85°C  TA  +125°C
Output Low Voltage — — 0.4 V VDD = 3.3V,
8x Sink Driver Pins(3) IOL  12 mA, -40°C  TA  +85°C,
IOL  8 mA, +85°C  TA  +125°C
DO20 VOH Output High Voltage 2.4 — — V IOH  -10 mA, VDD = 3.3V
4x Source Driver Pins(2)
Output High Voltage 2.4 — — V IOH  -15 mA, VDD = 3.3V
DO20A VOH1 Output High Voltage 1.5(1) — — IOH  -14 mA, VDD = 3.3V
2.0(1) — — V IOH  -12 mA, VDD = 3.3V
3.0(1) — — IOH  -7 mA, VDD = 3.3V
Output High Voltage 1.5(1) — — IOH  -22 mA, VDD = 3.3V

2.0(1) — — V IOH  -18 mA, VDD = 3.3V
3.0(1) — — IOH  -10 mA, VDD = 3.3V
Note 1: Parameters are characterized but not tested.

2: Includes RA0-RA2, RB0-RB1, RB9-RB10, RC1-RC2, RC9-RC10, RC12 and RD7 pins.
3: Includes all I/O pins that are not 4x driver pins (see Note 2).
TABLE 26-13: ELECTRICAL CHARACTERISTICS: BOR

DC CHARACTERISTICS
Param
Symbol Characteristic Min.(2) Typ. Max. Units Conditions
No.
BO10 VBOR BOR Event on VDD Transition 2.65 — 2.95 V VDD
High-to-Low (Notes 2 and 3)
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, PGAs and comparators) may have degraded
performance.
2: Parameters are for design guidance only and are not tested in manufacturing.
3: The VBOR specification is relative to VDD.

TABLE 26-14: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Param
No.
Program Flash Memory
D130 EP Cell Endurance 10,000 — — E/W -40C to +125C
D131 VPR VDD for Read 3.0 — 3.6 V
D132b VPEW VDD for Self-Timed Write 3.0 — 3.6 V
D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications
are violated, -40C to +125C
D135 IDDP Supply Current during — 10 — mA
Programming(2)
D136 IPEAK Instantaneous Peak Current — — 150 mA
During Start-up
D137a TPE Page Erase Time 19.7 — 20.1 ms TPE = 146893 FRC cycles,
TA = +85°C (Note 3)
D137b TPE Page Erase Time 19.5 — 20.3 ms TPE = 146893 FRC cycles,
TA = +125°C (Note 3)
D138a TWW Word Write Cycle Time 46.5 — 47.3 µs TWW = 346 FRC cycles,
TA = +85°C (Note 3)
D138b TWW Word Write Cycle Time 46.0 — 47.9 µs TWW = 346 FRC cycles,
TA = +125°C (Note 3)
D139a TRW Row Write Time 667 — 679 µs TRW = 4965 FRC cycles,
TA = +85°C (Note 3)
D139b TRW Row Write Time 660 — 687 µs TRW = 4965 FRC cycles,
TA = +125°C (Note 3)
2: Parameter characterized but not tested in manufacturing.
3: Other conditions: FRC = 7.37 MHz, TUN<5:0> = 011111 (for Minimum), TUN<5:0> = 100000 (for
Maximum). This parameter depends on the FRC accuracy (see Table 26-20) and the value of the FRC
Oscillator Tuning register (see Register 8-4). For complete details on calculating the Minimum and
Maximum time, see Section 5.3 “Programming Operations”.

26.2 AC Characteristics and Timing
Parameters
This section defines the dsPIC33EPXXGS50X family
AC characteristics and timing parameters.
TABLE 26-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial
Operating voltage VDD range as described in Section 26.1 “DC Characteristics”.
FIGURE 26-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSC2
VSS 15 pF for OSC2 output
TABLE 26-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param
No.
DO50 COSCO OSC2 Pin — — 15 pF In XT and HS modes, when
external clock is used to drive
OSC1
DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode
DO58 CB SCLx, SDAx — — 400 pF In I2C mode

FIGURE 26-2: EXTERNAL CLOCK TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKO
OS41 OS40
TABLE 26-17: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
Symb Characteristic Min. Typ.(1) Max. Units Conditions
No.
OS10 FIN External CLKI Frequency DC — 60 MHz EC
(External clocks allowed only
in EC and ECPLL modes)
Oscillator Crystal Frequency 3.5 — 10 MHz XT
10 — 40 MHz HS
OS20 TOSC TOSC = 1/FOSC 8.33 — DC ns +125°C
TOSC = 1/FOSC 7.14 — DC ns +85°C
OS25 TCY Instruction Cycle Time(2) 16.67 — DC ns +125°C
Instruction Cycle Time(2) 14.28 — DC ns +85°C
OS30 TosL, External Clock in (OSC1) 0.45 x TOSC — 0.55 x TOSC ns EC
TosH High or Low Time
OS31 TosR, External Clock in (OSC1) — — 20 ns EC
TosF Rise or Fall Time
OS40 TckR CLKO Rise Time(3,4) — 5.2 — ns
(3,4)
OS41 TckF CLKO Fall Time — 5.2 — ns
OS42 GM External Oscillator — 12 — mA/V HS, VDD = 3.3V,
Transconductance(4) TA = +25°C
— 6 — mA/V XT, VDD = 3.3V,
TA = +25°C
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at
“Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used,
the “Maximum” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: This parameter is characterized but not tested in manufacturing.

TABLE 26-18: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Param
No.
OS50 FPLLI PLL Voltage Controlled Oscillator 0.8 — 8.0 MHz ECPLL, XTPLL modes
(VCO) Input Frequency Range
OS51 FVCO On-Chip VCO System Frequency 120 — 340 MHz
OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 ms
(2)
OS53 DCLK CLKO Stability (Jitter) -3 0.5 3 %
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases, or communication clocks used by the application, use the following formula:
D CLK
Effective Jitter = -------------------------------------------------------------------------------------------
F OSC
---------------------------------------------------------------------------------------
Time Base or Communication Clock
For example, if FOSC = 120 MHz and the SPIx bit rate = 10 MHz, the effective jitter is as follows:
D CLK D CLK D CLK
Effective Jitter = -------------- = -------------- = --------------
120 12 3.464
---------
10
TABLE 26-19: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS

AC CHARACTERISTICS
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
OS56 FHPOUT On-Chip 16x PLL CCO 112 118 120 MHz
Frequency
OS57 FHPIN On-Chip 16x PLL Phase 7.0 7.37 7.5 MHz
Detector Input Frequency
OS58 TSU Frequency Generator Lock — — 10 µs
Time
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.

TABLE 26-20: INTERNAL FRC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Param
Characteristic Min. Typ. Max. Units Conditions
No.
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a FRC -2 0.5 +2 % -40°C  TA -10°C VDD = 3.0-3.6V
-0.9 0.5 +0.9 % -10°C  TA +85°C VDD = 3.0-3.6V
F20b FRC -2 1 +2 % +85°C  TA  +125°C VDD = 3.0-3.6V
Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
TABLE 26-21: INTERNAL LPRC ACCURACY

Param
Characteristic Min. Typ. Max. Units Conditions
No.
LPRC @ 32.768 kHz(1)
F21a LPRC -30 — +30 % -40°C  TA  -10°C VDD = 3.0-3.6V
-20 — +20 % -10°C  TA  +85°C VDD = 3.0-3.6V
F21b LPRC -30 — +30 % +85°C  TA  +125°C VDD = 3.0-3.6V
Note 1: This is the change of the LPRC frequency as VDD changes.

FIGURE 26-3: I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin New Value

Old Value
(Output)
DO31
DO32
Note: Refer to Figure 26-1 for load conditions.
TABLE 26-22: I/O TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
DO31 TIOR Port Output Rise Time — 5 10 ns
DO32 TIOF Port Output Fall Time — 5 10 ns
DI35 TINP INTx Pin High or Low Time (input) 20 — — ns
DI40 TRBP CNx High or Low Time (input) 2 — — TCY
FIGURE 26-4: BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS
MCLR
TMCLR
(SY20)
BOR
TBOR Various Delays (depending on configuration)

(SY30)
Reset Sequence
CPU Starts Fetching Code

TABLE 26-23: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions
No.
SY00 TPU Power-up Period — 400 600 s
SY10 TOST Oscillator Start-up Time — 1024 TOSC — — TOSC = OSC1 period
SY12 TWDT Watchdog Timer 0.81 — 1.22 ms WDTPRE = 0,
Time-out Period WDTPOST<3:0> = 0000,
using LPRC tolerances indicated in
F21 (see Table 26-21) at +85°C
3.25 — 4.88 ms WDTPRE = 1,
WDTPOST<3:0> = 0000,
using LPRC tolerances indicated in
F21 (see Table 26-21) at +85°C
SY13 TIOZ I/O High-Impedance from 0.68 0.72 1.2 s
MCLR Low or Watchdog
Timer Reset
SY20 TMCLR MCLR Pulse Width (low) 2 — — s
SY30 TBOR BOR Pulse Width (low) 1 — — s
SY35 TFSCM Fail-Safe Clock Monitor — 500 900 s -40°C to +85°C
Delay
SY36 TVREG Voltage Regulator — — 30 s
Standby-to-Active mode
Transition Time
SY37 TOSCDFRC FRC Oscillator Start-up — 48 — s
Delay
SY38 TOSCDLPRC LPRC Oscillator Start-up — — 70 s
Delay
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

FIGURE 26-5: TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRx
TABLE 26-24: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

AC CHARACTERISTICS
Param
Symbol Characteristic(2) Min. Typ. Max. Units Conditions
No.
TA10 TTXH T1CK High Synchronous Greater of: — — ns Must also meet
Time mode 20 or Parameter TA15,
(TCY + 20)/N N = Prescale Value
(1, 8, 64, 256)
Asynchronous 35 — — ns
TA11 TTXL T1CK Low Synchronous Greater of: — — ns Must also meet
Time mode 20 or Parameter TA15,
(1, 8, 64, 256)
Asynchronous 10 — — ns
TA15 TTXP T1CK Input Synchronous Greater of: — — ns N = Prescale Value
Period mode 40 or (1, 8, 64, 256)
(2 TCY + 40)/N
OS60 Ft1 T1CK Oscillator Input DC — 50 kHz
Frequency Range (oscillator
enabled by setting bit, TCS
(T1CON<1>))
TA20 TCKEXTMRL Delay from External T1CK 0.75 TCY + 40 — 1.75 TCY + 40 ns
Clock Edge to Timer
Increment
Note 1: Timer1 is a Type A timer.
2: These parameters are characterized but not tested in manufacturing.

TABLE 26-25: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
TB10 TtxH TxCK High Synchronous Greater of: — — ns Must also meet
Time mode 20 or Parameter TB15,
(1, 8, 64, 256)
TB11 TtxL TxCK Low Synchronous Greater of: — — ns Must also meet
Time mode 20 or Parameter TB15,
(1, 8, 64, 256)
TB15 TtxP TxCK Synchronous Greater of: — — ns N = Prescale Value
Input mode 40 or (1, 8, 64, 256)
Period (2 TCY + 40)/N
TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns
Clock Edge to Timer
Increment
TABLE 26-26: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
TC10 TtxH TxCK High Synchronous TCY + 20 — — ns Must also meet
Time Parameter TC15
TC11 TtxL TxCK Low Synchronous TCY + 20 — — ns Must also meet
Time Parameter TC15
TC15 TtxP TxCK Input Synchronous 2 TCY + 40 — — ns N = Prescale Value
Period with Prescaler (1, 8, 64, 256)
TC20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns
Clock Edge to Timer
Increment

FIGURE 26-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10 IC11
IC15
TABLE 26-27: INPUT CAPTURE x MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param.
Symbol Characteristics(1) Min. Max. Units Conditions
No.
IC10 TCCL ICx Input Low Time Greater of: — ns Must also meet
12.5 + 25 or Parameter IC15
(0.5 TCY/N) + 25
IC11 TCCH ICx Input High Time Greater of: — ns Must also meet
N = Prescale Value
12.5 + 25 or Parameter IC15
(1, 4, 16)
(0.5 TCY/N) + 25
IC15 TCCP ICx Input Period Greater of: — ns
25 + 50 or
(1 TCY/N) + 50

FIGURE 26-7: OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11 OC10
TABLE 26-28: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32
OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31
FIGURE 26-8: OCx/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
TABLE 26-29: OCx/PWMx MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
OC15 TFD Fault Input to PWMx I/O — — TCY + 20 ns
Change
OC20 TFLT Fault Input Pulse Width TCY + 20 — — ns

FIGURE 26-9: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
Fault Input
(active-low)
MP20
PWMx
FIGURE 26-10: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
TABLE 26-30: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
MP10 TFPWM PWMx Output Fall Time — — — ns See Parameter DO32
MP11 TRPWM PWMx Output Rise Time — — — ns See Parameter DO31
MP20 TFD Fault Input  to PWMx — — 15 ns
I/O Change
MP30 TFH Fault Input Pulse Width 15 — — ns

TABLE 26-31: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
AC CHARACTERISTICS
Master Master Slave
Maximum
Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP
Data Rate
(Half-Duplex) (Full-Duplex) (Full-Duplex)
15 MHz Table 26-31 — — 0,1 0,1 0,1
9 MHz — Table 26-32 — 1 0,1 1
9 MHz — Table 26-33 — 0 0,1 1
15 MHz — — Table 26-34 1 0 0
11 MHz — — Table 26-35 1 1 0
15 MHz — — Table 26-36 0 1 0
11 MHz — — Table 26-37 0 0 0
FIGURE 26-11: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)

TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP20 SP21
SDOx MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP30, SP31

FIGURE 26-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
SP36
SCKx
(CKP = 0)
SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP20 SP21
SP30, SP31
TABLE 26-32: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
SP10 FscP Maximum SCKx Frequency — — 15 MHz (Note 3)
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDOx Data Output Valid After — 6 20 ns
TscL2doV SCKx Edge
SP36 TdiV2scH, SDOx Data Output Setup to 30 — — ns
TdiV2scL First SCKx Edge
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.

FIGURE 26-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
SP36
SCKx
(CKP = 0)
SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP20 SP21
SP40 SP30, SP31
SDIx MSb In Bit 14 - - - -1 LSb In
SP41
TABLE 26-33: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)

TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
SP10 FscP Maximum SCKx Frequency — — 9 MHz (Note 3)
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 (Note 4)
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 (Note 4)
SP30 TdoF SDOx Data Output Fall — — — ns See Parameter DO32 (Note 4)
Time
SP31 TdoR SDOx Data Output Rise — — — ns See Parameter DO31 (Note 4)
Time
SP35 TscH2doV, SDOx Data Output Valid — 6 20 ns
TscL2doV After SCKx Edge
SP36 TdoV2sc, SDOx Data Output Setup 30 — — ns
TdoV2scL to First SCKx Edge
SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns
TdiV2scL Input to SCKx Edge
SP41 TscH2diL, Hold Time of SDIx Data 30 — — ns
TscL2diL Input to SCKx Edge
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.

FIGURE 26-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
SCKx
(CKP = 0)
SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP36 SP20 SP21
SP30, SP31 SP30, SP31
SP40 SP41
RefertotoFigure
Note:Refer
Note: Figure26-1
26-1for
forload
loadconditions.
conditions.
TABLE 26-34: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)

TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
SP10 FscP Maximum SCKx Frequency — — 9 MHz -40°C to +125°C
(Note 3)
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCKx Edge
SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns
TdoV2scL First SCKx Edge
SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns
TdiV2scL Input to SCKx Edge
SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns
TscL2diL to SCKx Edge
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.

FIGURE 26-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
SP60
SSx
SP50 SP52
SCKx
(CKP = 0)
SP70 SP73 SP72
SCKx
(CKP = 1) SP36
SP35
SP72 SP73
SP30, SP31 SP51

SP41
SP40

TABLE 26-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
SP70 FscP Maximum SCKx Input — — Lesser of: MHz (Note 3)
Frequency FP or 15
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCKx Edge
SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns
TdiV2scL to SCKx Edge
SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns
TssL2scL Input
SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns (Note 4)
High-Impedance
SP52 TscH2ssH, SSx after SCKx Edge 1.5 TCY + 40 — — ns (Note 4)
TscL2ssH
SP60 TssL2doV SDOx Data Output Valid After — — 50 ns
SSx Edge
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.

SP60
SSx
SP50 SP52
SCKx
(CKP = 0)
SP70 SP73 SP72
SCKx
(CKP = 1) SP36
SP35
SP72 SP73
SP30, SP31 SP51

SP41
SP40

TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
SP70 FscP Maximum SCKx Input — — Lesser of: MHz (Note 3)
Frequency FP or 11
(Note 4)
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCKx Edge
TssL2scL Input
High-Impedance
SP52 TscH2ssH, SSx after SCKx Edge 1.5 TCY + 40 — — ns (Note 4)
TscL2ssH
SP60 TssL2doV SDOx Data Output Valid after — — 50 ns
SSx Edge
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not

SSx
SP50 SP52
SCKx
(CKP = 0)
SP70 SP73 SP72
SCKx
(CKP = 1)
SP72 SP73
SP35 SP36
SP30, SP31 SP51

SP41
SP40

TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
SP70 FscP Maximum SCKx Input Frequency — — 15 MHz (Note 3)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCKx Edge
TssL2scL Input
High-Impedance
SP52 TscH2ssH, SSx After SCKx Edge 1.5 TCY + 40 — — ns (Note 4)
TscL2ssH
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.

SSx
SP50 SP52
SCKx
(CKP = 0)
SP70 SP73 SP72
SCKx
(CKP = 1)
SP72 SP73
SP35 SP36
SP30, SP31 SP51

SP41
SP40

TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
SP70 FscP Maximum SCKx Input Frequency — — 11 MHz (Note 3)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCKx Edge
TssL2scL Input
High-Impedance
SP52 TscH2ssH, SSx After SCKx Edge 1.5 TCY + 40 — — ns (Note 4)
TscL2ssH
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not

FIGURE 26-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31 IM34
IM30 IM33
SDAx
Start Stop
Condition Condition
FIGURE 26-20: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20 IM11 IM21

IM10
SCLx
IM11
IM26 IM25
IM10 IM33
SDAx
In
IM40 IM40 IM45
SDAx
Out

TABLE 26-39: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Param
Symbol Characteristic(4) Min.(1) Max. Units Conditions
No.
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2) — s
400 kHz mode TCY/2 (BRG + 2) — s
1 MHz mode (2)
TCY/2 (BRG + 2) — s
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2) — s
400 kHz mode TCY/2 (BRG + 2) — s
1 MHz mode(2) TCY/2 (BRG + 2) — s
IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode(2) — 100 ns
IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
IM25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
(2)
1 MHz mode 40 — ns
IM26 THD:DAT Data Input 100 kHz mode 0 — s
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode(2) 0.2 — s
IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) — s Only relevant for
Setup Time 400 kHz mode TCY/2 (BRG + 2) — s Repeated Start
1 MHz mode(2) TCY/2 (BRG + 2) — s condition
IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) — s After this period, the
Hold Time 400 kHz mode TCY/2 (BRG +2) — s first clock pulse is
1 MHz mode(2) TCY/2 (BRG + 2) — s generated
IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — s
Setup Time 400 kHz mode TCY/2 (BRG + 2) — s
1 MHz mode (2)
TCY/2 (BRG + 2) — s
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — s
Hold Time 400 kHz mode TCY/2 (BRG + 2) — s
1 MHz mode(2) TCY/2 (BRG + 2) — s
IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns
from Clock 400 kHz mode — 1000 ns
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be
400 kHz mode 1.3 — s free before a new
1 MHz mode(2) 0.5 — s transmission can start
IM50 CB Bus Capacitive Loading — 400 pF
IM51 TPGD Pulse Gobbler Delay 65 390 ns (Note 3)
Note 1: 2
BRG is the value of the I C Baud Rate Generator.
2: Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.

FIGURE 26-21: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31 IS34
IS30 IS33
SDAx
Start Stop
Condition Condition
FIGURE 26-22: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20 IS11 IS21

IS10
SCLx
IS30 IS26 IS25
IS31 IS33
SDAx
In
IS40 IS40 IS45
SDAx
Out

TABLE 26-40: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Param
Symbol Characteristic(3) Min. Max. Units Conditions
No.
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s
400 kHz mode 1.3 — s
1 MHz mode(1) 0.5 — s
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
1 MHz mode(1) 0.5 — s
IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
IS25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
1 MHz mode (1) 100 — ns
IS26 THD:DAT Data Input 100 kHz mode 0 — s
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode(1) 0 0.3 s
IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated
Setup Time 400 kHz mode 0.6 — s Start condition
1 MHz mode(1) 0.25 — s
IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first
Hold Time 400 kHz mode 0.6 — s clock pulse is generated
1 MHz mode(1) 0.25 — s
IS33 TSU:STO Stop Condition 100 kHz mode 4 — s
Setup Time 400 kHz mode 0.6 — s
1 MHz mode (1) 0.25 — s
IS34 THD:STO Stop Condition 100 kHz mode 4 — s
Hold Time 400 kHz mode 0.6 — s
1 MHz mode(1) 0.25 s
IS40 TAA:SCL Output Valid from 100 kHz mode 0 3500 ns
Clock 400 kHz mode 0 1000 ns
1 MHz mode(1) 0 350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new transmission
1 MHz mode(1) 0.5 — s can start
IS50 CB Bus Capacitive Loading — 400 pF
IS51 TPGD Pulse Gobbler Delay 65 390 ns (Note 2)
Note 1: Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: Typical value for this parameter is 130 ns.

FIGURE 26-23: UARTx MODULE I/O TIMING CHARACTERISTICS
UA20
UxRX MSb In Bit 6-1 LSb In

UXTX
UA10
TABLE 26-41: UARTx MODULE I/O TIMING REQUIREMENTS

AC CHARACTERISTICS (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
No.
UA10 TUABAUD UARTx Baud Time 66.67 — — ns
UA11 FBAUD UARTx Baud Frequency — — 15 Mbps
UA20 TCWF Start Bit Pulse Width to Trigger 500 — — ns
UARTx Wake-up
2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 26-42: ANALOG CURRENT SPECIFICATIONS

AC CHARACTERISTICS (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
No.
AVD01 IDD Analog Modules Current — 9 — mA Characterized data with the
Consumption following modules enabled:
APLL, 5 ADC Cores, 2 PGAs
and 4 Analog Comparators
2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.

TABLE 26-43: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
Symbol Characteristics Min. Typical Max. Units Conditions
No.
Device Supply
AD01 AVDD Module VDD Supply Greater of: — Lesser of: V The difference between
VDD – 0.3 VDD + 0.3 AVDD supply and VDD
or 3.0 or 3.6 supply must not exceed
±300 mV at all times,
including during device
power-up
AD02 AVSS Module VSS Supply VSS — VSS + 0.3 V
Reference Inputs
AD06 VREFL Reference Voltage Low — AVSS — V (Note 1)
AD07 VREF Absolute Reference 2.7 — AVDD V (Note 3)
Voltage (VREFH – VREFL)
AD08 IREF Reference Input Current — 5 10 A ADC operating or in standby
Analog Input
AD12 VINH-VINL Full-Scale Input Span AVSS — AVDD V
AD14 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V
AD17 RIN Recommended — 100 —  For minimum sampling
Impedance of Analog time (Note 1)
Voltage Source
AD66 VBG Internal Voltage — 1.2 — V
Reference Source
ADC Accuracy: Pseudo-Differential Input
AD20a Nr Resolution 12 bits
AD21a INL Integral Nonlinearity > -3 — <3 LSb AVSS = 0V, AVDD = 3.3V
AD22a DNL Differential Nonlinearity > -1 — <1 LSb AVSS = 0V, AVDD = 3.3V
(Note 2)
AD23a GERR Gain Error >5 13 < 20 LSb AVSS = 0V, AVDD = 3.3V
(Dedicated Core)
Gain Error > -1 5 < 10 LSb
(Shared Core)
AD24a EOFF Offset Error >2 7 < 12 LSb AVSS = 0V, AVDD = 3.3V
(Dedicated Core)
Offset Error > -2 3 <8 LSb
(Shared Core)
AD25a — Monotonicity — — — — Guaranteed
Note 1: These parameters are not characterized or tested in manufacturing.
2: No missing codes, limits based on characterization results.
4: Characterized with a 1 kHz sine wave.
5: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is ensured, but not characterized.

TABLE 26-43: ADC MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS
Param
Symbol Characteristics Min. Typical Max. Units Conditions
No.
ADC Accuracy: Single-Ended Input
AD20b Nr Resolution 12 bits
AD21b INL Integral Nonlinearity > -3 — <3 LSb AVSS = 0V, AVDD = 3.3V
AD22b DNL Differential Nonlinearity > -1 — < 1.5 LSb AVSS = 0V, AVDD = 3.3V
(Note 2)
AD23b GERR Gain Error >5 13 < 20 LSb AVSS = 0V, AVDD = 3.3V
(Dedicated Core)
Gain Error > -1 5 < 10 LSb
(Shared Core)
AD24b EOFF Offset Error >2 10 < 18 LSb AVSS = 0V, AVDD = 3.3V
(Dedicated Core)
Offset Error >2 8 < 15 LSb
(Shared Core)
AD25b — Monotonicity — — — — Guaranteed
Dynamic Performance
AD31b SINAD Signal-to-Noise and 63 — > 65 dB (Notes 3, 4)
Distortion
AD34b ENOB Effective Number of Bits 10.3 — — bits (Notes 3, 4)
Note 1: These parameters are not characterized or tested in manufacturing.
2: No missing codes, limits based on characterization results.
4: Characterized with a 1 kHz sine wave.

TABLE 26-44: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS(2) Operating temperature -40°C  TA  +85°C for Industrial
Param
Symbol Characteristics Min. Typ.(1) Max. Units Conditions
No.
Clock Parameters
AD50 TAD ADC Clock Period 14.28 — — ns
Throughput Rate
AD51 FTP SH0-SH3 — — 3.25 Msps 70 MHz ADC clock, 12 bits, no pending
SH4 — — 3.25 Msps conversion at time of trigger
TABLE 26-45: HIGH-SPEED ANALOG COMPARATOR MODULE SPECIFICATIONS

AC/DC CHARACTERISTICS(2)
Param
Symbol Characteristic Min. Typ. Max. Units Comments
No.
CM10 VIOFF Input Offset Voltage -35 ±5 +35 mV
CM11 VICM Input Common-Mode 0 — AVDD V
Voltage Range(1)
CM13 CMRR Common-Mode 60 — — dB
Rejection Ratio
CM14 TRESP Large Signal Response — 15 — ns V+ input step of 100 mV while
V- input is held at AVDD/2. Delay
measured from analog input pin to
PWMx output pin.
CM15 VHYST Input Hysteresis 5 10 20 mV Depends on HYSSEL<1:0>
CM16 TON Comparator Enabled to — — 1 µs
Valid Output
Note 1: These parameters are for design guidance only and are not tested in manufacturing.
2: The comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.

TABLE 26-46: DACx MODULE SPECIFICATIONS
(2) (unless otherwise stated)
AC/DC CHARACTERISTICS
Param
No.
DA01 EXTREF External Voltage Reference(1) 0 — AVDD V
DA02 CVRES Resolution 12 bits
DA03 INL Integral Nonlinearity Error -16 -12 0 LSB
DA04 DNL Differential Nonlinearity Error -1.8 ±1 1.8 LSB
DA05 EOFF Offset Error -8 3 15 LSB
DA06 EG Gain Error -1.2 -0.5 0 %
DA07 TSET Settling Time(1) — 700 — ns Output with 2% of desired
output voltage with a
10-90% or 90-10% step
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
TABLE 26-47: DACx OUTPUT (DACOUTx PIN) SPECIFICATIONS

DC CHARACTERISTICS(1)
Param
No.
DA11 RLOAD Resistive Output Load 10K — — Ohm
Impedance
DA11a CLOAD Output Load — — 35 pF Including output pin
Capacitance capacitance
DA12 IOUT Output Current Drive — 300 — µA Sink and source
Strength
DA13 VRANGE Output Drive Voltage AVSS + 250 mV — AVDD – 900 mV V
Range at Current
Drive of 300 µA
DA14 VLRANGE Output Drive Voltage AVSS + 50 mV — AVDD – 500 mV V
Range at Reduced
Current Drive of 50 µA
DA15 IDD Current Consumed — — 1.3 x IOUT µA Module will always
when Module is consume this current,
Enabled even if no load is
connected to the output
DA30 VOFFSET Input Offset Voltage — 5 — mV
Note 1: The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless

TABLE 26-48: PGAx MODULE SPECIFICATIONS
(1) (unless otherwise stated)
AC/DC CHARACTERISTICS
Param
No.
PA01 VIN Input Voltage Range AVSS – 0.3 — AVDD + 0.3 V
PA02 VCM Common-Mode Input AVSS — AVDD – 1.6 V
Voltage Range
PA03 VOS Input Offset Voltage -10 — 10 mV
PA04 VOS Input Offset Voltage Drift — 15 — µV/C
with Temperature
PA05 RIN+ Input Impedance of — >1M || 7 pF — || pF
Positive Input
PA06 RIN- Input Impedance of — 10K || 7 pF — || pF
Negative Input
PA07 GERR Gain Error -2 — 2 % Gain = 4x, 8x
-3 — 3 % Gain = 16x
-4 — 4 % Gain = 32x, 64x
PA08 LERR Gain Nonlinearity Error — — 0.5 % % of full scale,
Gain = 16x
PA09 IDD Current Consumption — 2.0 — mA Module is enabled with
a 2-volt P-P output
voltage swing
PA10a BW Small Signal G = 4x — 10 — MHz
PA10b Bandwidth (-3 dB) G = 8x — 5 — MHz
PA10c G = 16x — 2.5 — MHz
PA10d G = 32x — 1.25 — MHz
PA10e G = 64x — 0.625 — MHz
PA11 OST Output Settling Time to 1% — 0.4 — µs Gain = 16x, 100 mV
of Final Value input step change
PA12 SR Output Slew Rate — 40 — V/µs Gain = 16x
PA13 TGSEL Gain Selection Time — 1 — µs
PA14 TON Module Turn On/Setting Time — — 10 µs
Note 1: The PGAx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
TABLE 26-49: CONSTANT-CURRENT SOURCE SPECIFICATIONS

DC CHARACTERISTICS(1)
Param
No.
CC01 IDD Current Consumption — 30 — µA
CC02 IREG Regulation of Current with — ±3 — %
Voltage On
CC03 IOUT Current Output at Terminal — 10 — µA
Note 1: The constant-current source module is functional at VBORMIN < VDD < VDDMIN, but with degraded
performance. Unless otherwise stated, module functionality is tested, but not characterized.

NOTES:

27.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS
Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 27-1: VOH – 4x DRIVER PINS FIGURE 27-3: VOL – 4x DRIVER PINS
VOH (V)
-0.050 VOL(V)
0.050
-0.045 3.6V
0.045 3.6V
-0.040 3.3V 0.040 3.3V
-0.035
0.035 3V
-0.030 3V
0.030
IOH(A)
IOL(A)
IOH(A)
-0.025 0.025
-0.020 0.020
-0.015 Absolute Maximum 0.015 Absolute Maximum
-0.010 0.010
-0.005 0.005
0.000 0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FIGURE 27-2: VOH – 8x DRIVER PINS FIGURE 27-4: VOL – 8x DRIVER PINS
8X
VOH(V) VOL(V)
-0.080 0.080 3.6V
3.6V
-0.070 0.070 3.3V
3.3V
-0.060 0.060 3V
-0.050 3V 0.050
IOH(A)
IOH(A)
IOL(A)
-0.040 0.040
DS70005127D-page 349
0 030
-0.030 0.030
Absolute Maximum Absolute Maximum
-0.020 0 020
0.020
-0.010 0.010
0.000 0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FIGURE 27-5: TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 27-7: TYPICAL IDOZE CURRENT @ VDD = 3.3V, +25°C
DS70005127D-page 350
300 30.0
250 25.0
200 20.0
IDOZE (mA)
IPD (µA)
150 15.0
100 10.0
50 5.0
0 0.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 1:1 1:2 1:64 1:128
Temperature (°C) Doze Ratio
FIGURE 27-6: TYPICAL IDD CURRENT @ VDD = 3.3V, +25°C FIGURE 27-8: TYPICAL IIDLE CURRENT @ VDD = 3.3V, +25°C
30 12.0
10.0
25
8.0
IIDLE (mA)
20
IDD (mA)
6.0
15
4.0
10
2.0
5 0.0
10 20 30 40 50 60 70 10 20 30 40 50 60 70
MIPS MIPS
FIGURE 27-9: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 27-10: TYPICAL LPRC FREQUENCY @ VDD = 3.3V
7400 34.4
34.2
7350
34
Frequency (kHz)
Frequency (kHz)
7300
33.8
33.6
7250
33.4
7200
33.2
7150 33
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature (°C) Temperature (°C)
DS70005127D-page 351
NOTES:

28.0 PACKAGING INFORMATION
28.1 Package Marking Information
28-Lead SOIC (.300”) Example
XXXXXXXXXXXXXXXXXXXX dsPIC33EP64GS502
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN 1710017
28-Lead UQFN (6x6x0.55 mm) Example
XXXXXXXX 33EP64GS
XXXXXXXX 502
YYWWNNN 1710017
28-Lead QFN-S (6x6x0.9 mm) Example
XXXXXXXX 33EP64GS
XXXXXXXX 502
YYWWNNN 1710017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

28.1 Package Marking Information (Continued)
44-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX dsPIC33EP
XXXXXXXXXX 64GS504
XXXXXXXXXX
YYWWNNN 1710017
44-Lead QFN (8x8 mm) Example
XXXXXXXXXXX dsPIC33EP
XXXXXXXXXXX 64GS504
XXXXXXXXXXX
YYWWNNN 1710017
48-Lead TQFP (7x7x1.0 mm) Example
1
XXXXXXX
1
EP64GS
XXXYYWW 5051710
NNN 017
64-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX dsPIC33EP
XXXXXXXXXX 64GS506
XXXXXXXXXX
YYWWNNN 1710017

28.2 Package Details
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging



28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (2N) - 6x6x0.55 mm Body [UQFN]
With 4.65x4.65 mm Exposed Pad and Corner Anchors
D A B
NOTE 1 N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.10 C
TOP VIEW
A
C A1
0.10 C
SEATING
PLANE
(A3) 28X
SIDE VIEW 0.08 C
8X b1
0.10 C A B
D2
0.10 C A B
8X b2
E2
2 28X K
1
2X P
N
NOTE 1 e
L 28X b
0.10 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-385B Sheet 1 of 2

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 28
Pitch e 0.65 BSC
Overall Height A 0.45 0.50 0.55
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.127 REF
Overall Width E 6.00 BSC
Exposed Pad Width E2 4.55 4.65 4.75
Overall Length D 6.00 BSC
Exposed Pad Length D2 4.55 4.65 4.75
Exposed Pad Corner Chamfer P - 0.35 -
Terminal Width b 0.25 0.30 0.35
Corner Anchor Pad b1 0.35 0.40 0.43
Corner Pad, Metal Free Zone b2 0.15 0.20 0.25
Terminal Length L 0.30 0.40 0.50
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-385B Sheet 2 of 2

C2
Y2
EV
28
Y3
1
X1
2 ØV
Y4
C1 G1
EV G2
X4 Y1
X3 E SILK SCREEN
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Contact Pitch E 0.65 BSC
Optional Center Pad Width X2 4.75
Optional Center Pad Length Y2 4.75
Contact Pad Spacing C1 6.00
Contact Pad Width (X28) X1 0.35
Contact Pad Length (X28) Y1 0.80
Corner Anchor (X4) X3 1.00
Corner Anchor (X4) Y3 1.00
Corner Anchor Chamfer (X4) X4 0.35
Corner Anchor Chamfer (X4) Y4 0.35
Contact Pad to Pad (X28) G1 0.20
Contact Pad to Center Pad (X28) G2 0.20
Thermal Via Diameter V 0.33
Thermal Via Pitch EV 1.20
Notes:
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2385B
Note: Corner anchor pads are not connected internally and are designed as mechanical features when the
package is soldered to the PCB.



/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH00±[[PP%RG\>4)16@
ZLWKPP&RQWDFW/HQJWK
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ

44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
D A
D1 B
NOTE 2
(DATUM A)
(DATUM B)
E1 E
NOTE 1 A A
2X
N
0.20 H A B
2X 1 2 3
0.20 H A B 4X 11 TIPS
TOP VIEW
0.20 C A B
A A2
C
SEATING PLANE
0.10 C A1
SIDE VIEW
1 2 3
NOTE 1
44 X b
e 0.20 C A B
BOTTOM VIEW
Microchip Technology Drawing C04-076C Sheet 1 of 2

44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
L θ
(L1)
SECTION A-A
Units MILLIMETERS
Number of Leads N 44
Lead Pitch e 0.80 BSC
Overall Height A - - 1.20
Standoff A1 0.05 - 0.15
Molded Package Thickness A2 0.95 1.00 1.05
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Width b 0.30 0.37 0.45
Lead Thickness c 0.09 - 0.20
Lead Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle θ 0° 3.5° 7°
Notes:
2. Exact shape of each corner is optional.


44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
D A B
N
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
0.20 C TOP VIEW
0.10 C A1
C
SEATING A
PLANE 44X
A3 0.08 C
SIDE VIEW
L
0.10 C A B
D2
0.10 C A B
E2
K
2
1
NOTE 1 N
44X b
e 0.07 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-103D Sheet 1 of 2

Units MILLIMETERS
Number of Pins N 44
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.20 REF
Exposed Pad Width E2 6.25 6.45 6.60
Exposed Pad Length D2 6.25 6.45 6.60
Terminal Width b 0.20 0.30 0.35
Terminal Length L 0.30 0.40 0.50
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
2. Package is saw singulated
Microchip Technology Drawing C04-103D Sheet 2 of 2

C1
X2
EV
44
G2
1
2
ØV
EV
C2 Y2
G1
Y1
E SILK SCREEN
X1

Units MILLIMETERS
Optional Center Pad Width X2 6.60
Optional Center Pad Length Y2 6.60
Contact Pad to Contact Pad (X40) G1 0.30
Contact Pad to Center Pad (X44) G2 0.28
Thermal Via Diameter V 0.33
Thermal Via Pitch EV 1.20
Notes:
reflow process
Microchip Technology Drawing No. C04-2103C

48-Lead Thin Quad Flatpack (Y8) - 7x7x1.0 mm Body [TQFP]
48X TIPS
0.20 C A-B D
D
D1
D1
2
A B
E1 E
E1
A A 2
E1
4 N
NOTE 1 1 2 4X
D1 0.20 H A-B D
4
48x b
e 0.08 C A-B D
TOP VIEW
0.10 C H
C A2
A
SEATING
PLANE 0.08 C
A1 SIDE VIEW
Microchip Technology Drawing C04-300-Y8 Rev A Sheet 1 of 2

E T
L
(L1)
SECTION A-A
Units MILLIMETERS
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Foot Angle I 0° 3.5° 7°
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top D 11° 12° 13°
Mold Draft Angle Bottom E 11° 12° 13°
Notes:
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
5. Datums A-B and D to be determined at center line between leads where leads exit
plastic body at datum plane H
Microchip Technology Drawing C04-300-Y8 Rev A Sheet 2 of 2

C1
C2 G
SILK SCREEN
48
Y1
1 2
X1
E
Units MILLIMETERS
Distance Between Pads G 0.20
Notes:
reflow process
Microchip Technology Drawing C04-2300-Y8 Rev A

64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
D
D1
D1/2
D
NOTE 2
E1/2
A B
E1 E
A A
SEE DETAIL 1
N
4X N/4 TIPS
0.20 C A-B D 1 3
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
C 0.05
SEATING
PLANE
A1
64 X b
0.08 C 0.08 C A-B D
e
SIDE VIEW

64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
E
L T
(L1) X=A—B OR D
SECTION A-A X
e/2
DETAIL 1
Units MILLIMETERS
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Foot Angle I 0° 3.5° 7°
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top D 11° 12° 13°
Notes: Mold Draft Angle Bottom E 11° 12° 13°
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.


NOTES:

APPENDIX A: REVISION HISTORY Removes the internal voltage reference in all occur-
rences. For analog modules, the internal band gap
reference is substituted as a replacement source.
Revision A (June 2013)
Changes the following register names in all
This is the initial released version of the document. occurrences throughout the text:
• “CMPCONx” to “CMPxCON”
Revision B (May 2015) • “CMPDACx” to “CMPxDAC”
Adds dsPIC33EPXXGS505 (48-pin) devices to the • “I2CxCON1” to “I2CxCONL”
document: • “I2CxCON2” to “I2CxCONH”
• Amends the table on page 2 to add the three new Updates the text of Section 5.4.2 “Dual Partition
devices of this group Modes” to change “Untrusted Dual Panel mode” to
• Adds the 48-pin TQFP pin diagram on page 7 “Privileged Dual Partition mode” and clarifies the
• Amends Table 26-3 to include thermal packaging mode’s code security features.
characteristics for 48-pin packages Changes the BSS2 Configuration bit to “BSEN”
• Updates Section 28.1 “Package Marking Infor- throughout the text.
mation” to include package marking details for Replaces Section 23.3 “User OTP Memory” with new
48-pin TQFP devices text to describe the 64-word User OTP Memory space;
• Updates Section 28.2 “Package Details” to also removes Table 23-4.
include Microchip Drawings C04-183A and
Amends Table 24-2 with a footnote indicating an
C04-2183A (7x7x1.0 mm 48-lead TQFP)
increase of instruction execution cycles for most
Changes all references to Dual Boot Flash Program instructions under certain conditions.
Memory throughout the text to “Dual Partition Flash
Updates the following tables in Section 26.0 “Electrical
Program Memory”. In addition, all accompanying refer-
Characteristics” (in addition to changes previously
ences to “panels” and “Boot modes” are changed to
noted):
“partitions” and “Partition modes”. This includes, but is
not limited, to: • Table 26-4, with new specification DC12 (and
accompanying footnote)
• Section 4.1 “Program Address Space”
• Table 26-6, with updated Typical and new Maxi-
• Section 5.4 “Dual Partition Flash Configuration”,
mum data throughout, and the addition of
and Register 5-1
Parameter DC27 (with accompanying footnote)
• Section 23.10 “Code Protection and CodeGuard™
• Table 26-7, Table 26-8 and Table 26-10 with
Security”, and Table 23-2
updated Typical and Maximum data throughout
Replaces the high-speed pipeline A/D Converter • Table 26-9 with updated Typical and Maximum
present in pre-production samples with a high-speed, data for Parameters DC61a and DC61b
multiple SAR A/D Converter in production devices:
• Footnotes 6 and 7 of Table 26-11 to clarify the
• Replaces Section 19.0 “High-Speed, 12-Bit behavior of 5V tolerant pins
Analog-to-Digital Converter (ADC)” with an • The “ADC Accuracy” specifications of Table 26-43
entirely new section of the same title, replacing all
• Table 26-45 (Table 26-45 in Revision A) with
previous figures and registers
updated specifications for Parameter CM15
• Updates the summary bullet points under
• Table 26-46 (Table 26-46 in Revision A) with
“High-Speed ADC Module” on Page 1 to reflect
updated specifications for Parameters DA03
the feature set of the new module
through DA06
• Updates Table 4-3 and Table 7-1 to reflect the
new module’s interrupt structure Clarifies the text of Footnotes 6 and 7 in Table 26-11
(I/O Pin Input Specifications).
• Replaces Table 4-16 with a new register map
• Removes Table 4-16 (“ADC Calibration Register Removes the “Reference Inputs” specifications from
Map”); subsequent tables are renumbered Table 26-43 in their entirety.
accordingly Replaces Figure 27-5 through Figure 27-10 with new
• Updates Section 23.2 “Device Calibration and characterization graphs to reflect the most current data
Identification” and Table 23-3 to remove the and removes “TBD” watermarks.
ADCAL registers from the Calibration register Updates Section 28.1 “Package Marking Informa-
table tion” to reflect the removal of redundant temperature
• Removes all references to the internal tempera- and package code information from all package
ture sensor, including Table 26-44 (Temperature markings; this is in addition to the new 48-pin package
Sensor Specifications) and Figure 27-11 (Typical markings previously described.
Temperature Sensor Voltage vs. Current)
Other minor typographic corrections throughout the
Changes the ESR specification of the VCAP filter document.
capacitor from < 4Ω to < 0.5Ω.

Revision C (October 2015) Revision D (May 2017)
Updates Note 2 in Table 1-1. Updates Pin 14 Function on page 3, updates Pin 11
Updates Figure 2-5. Function on page 4, updates Pin 41 Function on
page 5, updates Pin 41 Function on page 6, updates
Inserts new Section 4.2 “Unique Device Identifier Pin 45 Function on page 7 and updates Pin 43
(UDID)” and adds Table 4-1. Subsequent tables were
Function on page 8.
renumbered accordingly. Updates Table 4-3 (which
was Table 4-2), Table 4-5 (which was Table 4-4), Updates Table 1-1, Table 4-8, Table 4-9, Table 4-10,
Table 4-10 (which was Table 4-9), Table 4-11 (which Table 4-11, Table 4-12, Table 4-16, Table 26-4,
was Table 4-10), Table 4-21 (which was Table 4-20), Table 26-40, Table 26-43 and Table 26-45.
Table 4-32 (which was Table 4-31), Table 4-36 (which Updates Register 5-1, Register 8-4, Register 15-22,
was Table 4-35) and Table 4-37 (which was Table 4-36).
Register 19-5, Register 19-6, Register 19-26,
Updates Section 4.8.1 “Bit-Reversed Addressing
Register 19-27, Register 19-28, Register 19-29 and
Implementation” (which was Section 4.7.1).
Register 19-30.
Updates Register 9-1.
Updates Figure 20-2, Figure 26-20 and Figure 26-22.
Updates Figure 12-2 and Register 12-2.
Adds 48-Lead Thin Quad Flatpack (Y8) - 7x7x1.0 mm
Updates Register 13-1. Body TQFP drawings to Section 28.0 “Packaging
Updates Note 1 in Section 14.0 “Output Compare”. Information” section.
Updates Register 15-1, Register 15-6, Register 15-20 Updates Section 20.6 “Hysteresis”
and Register 15-22.
Updates Figure 17-1.
Updates Register 18-2.
Updates Figure 19-2 and Figure 19-3. Updates
Register 19-1, Register 19-2, Register 19-3,
Register 19-4, Register 19-26 and Register 19-33. Adds
Register 19-27.
Updates Figure 21-2.
Updates Section 23.6.2 “Sleep and Idle Modes”.
Updates Table 26-8, Table 26-11, Table 26-29. Adds
new Table 26-42. Subsequent tables were renumbered
accordingly. Updates Table 26-43 (which was
Table 26-42), Table 26-46 (which was Table 26-45) and
Table 26-48 (which was Table 26-47).
Updated diagrams in Section 28.0 “Packaging
Information”.
Updates the Product Identification System section.
Other minor typographic corrections throughout the
document.

INDEX
A Addressing for Table Registers .................................. 77
CALL Stack Frame ..................................................... 69
Absolute Maximum Ratings .............................................. 303
Connections for On-Chip Voltage Regulator ............ 285
AC Characteristics ............................................................ 315
Constant-Current Source.......................................... 275
ADC Specifications ................................................... 343
CPU Core ................................................................... 22
Analog Current Specifications................................... 342
Data Access from Program Space
Analog-to-Digital Conversion Requirements............. 345
Address Generation............................................ 75
Auxiliary PLL Clock ................................................... 317
Dedicated ADC Cores 0-3 ........................................ 231
Capacitive Loading Requirements on
dsPIC33EPXXGS50X Family ..................................... 11
Output Pins ....................................................... 315
High-Speed Analog Comparator x............................ 264
External Clock Requirements ................................... 316
High-Speed PWM Architecture................................. 183
High-Speed PWMx Requirements ............................ 325
Hysteresis Control .................................................... 266
I/O Requirements...................................................... 319
I2Cx Module ............................................................. 216
I2Cx Bus Data Requirements (Master Mode) ........... 339
Input Capture x ......................................................... 171
I2Cx Bus Data Requirements (Slave Mode) ............. 341
Interleaved PFC.......................................................... 18
Input Capture x Requirements .................................. 323
MCLR Pin Connections .............................................. 16
Internal FRC Accuracy.............................................. 318
Multiplexing Remappable Outputs for RPn .............. 130
Internal LPRC Accuracy............................................ 318
Off-Line UPS .............................................................. 20
Load Conditions ........................................................ 315
Oscillator System...................................................... 104
OCx/PWMx Module Requirements ........................... 324
Output Compare x Module ....................................... 175
Output Compare x Requirements ............................. 324
PGAx Functions........................................................ 272
PLL Clock.................................................................. 317
PGAx Module ........................................................... 271
Reset, WDT, OST, PWRT Requirements ................. 320
Phase-Shifted Full-Bridge Converter.......................... 19
SPIx Master Mode (Full-Duplex, CKE = 0,
PLL Module .............................................................. 105
CKP = x, SMP = 1) Requirements .................... 329
Programmer’s Model .................................................. 24
SPIx Master Mode (Full-Duplex, CKE = 1,
PSV Read Address Generation.................................. 66
CKP = x, SMP = 1) Requirements .................... 328
Recommended Minimum Connection ........................ 16
SPIx Master Mode (Half-Duplex,
Remappable Input for U1RX .................................... 128
Transmit Only) Requirements ........................... 327
Reset System ............................................................. 85
SPIx Maximum Data/Clock Rate Summary .............. 326
Security Segments for dsPIC33EP64GS50X ........... 288
SPIx Slave Mode (Full-Duplex, CKE = 0,
Security Segments for dsPIC33EP64GS50X
CKP = 0, SMP = 0) Requirements .................... 337
(Dual Partition Modes)...................................... 288
Shared Port Structure............................................... 125
Simplified Conceptual of High-Speed PWM ............. 184
SPIx Module ............................................................. 207
Suggested Oscillator Circuit Placement ..................... 17
Timerx (x = 2 through 5) ........................................... 168
Type B/Type C Timer Pair (32-Bit Timer) ................. 168
Temperature and Voltage Specifications .................. 315
UARTx Module ......................................................... 223
Timer1 External Clock Requirements ....................... 321
Watchdog Timer (WDT)............................................ 286
Timer2/Timer4 External Clock Requirements ........... 322
Brown-out Reset (BOR)............................................ 277, 285
Timer3/Timer5 External Clock Requirements ........... 322
UARTx I/O Requirements ......................................... 342 C
AC/DC Characteristics
C Compilers
DACx Specifications ................................................. 346
MPLAB XC ............................................................... 300
High-Speed Analog Comparator Specifications........ 345
Code Examples
PGAx Specifications ................................................. 347
Port Write/Read ........................................................ 126
Analog-to-Digital Converter. See ADC.
PWM Write-Protected Register
Arithmetic Logic Unit (ALU)................................................. 30
Unlock Sequence ............................................. 182
Assembler
PWRSAV Instruction Syntax .................................... 115
MPASM Assembler................................................... 300
Code Protection ........................................................ 277, 287
MPLAB Assembler, Linker, Librarian ........................ 300
CodeGuard Security ................................................. 277, 287
B Configuration Bits ............................................................. 277
Bit-Reversed Addressing .................................................... 73 Description................................................................ 280
Example ...................................................................... 74 Constant-Current Source.................................................. 275
Control Register........................................................ 276
Implementation ........................................................... 73
Sequence Table (16-Entry)......................................... 74 Description................................................................ 275
Block Diagrams Features Overview ................................................... 275
16-Bit Timer1 Module................................................ 163
ADC Module.............................................................. 230
ADC Shared Core ..................................................... 231

CPU F
Addressing Modes ...................................................... 21
Filter Capacitor (CEFC) Specifications .............................. 305
Clocking System Options .......................................... 105
Flash Program Memory ...................................................... 77
Fast RC (FRC) Oscillator .................................. 105
and Table Instructions ................................................ 77
FRC Oscillator with PLL (FRCPLL)................... 105
Control Registers ........................................................ 80
FRC Oscillator with Postscaler ......................... 105
Dual Partition Flash Configuration .............................. 79
Low-Power RC (LPRC) Oscillator..................... 105
Operations .................................................................. 78
Primary (XT, HS, EC) Oscillator........................ 105
Resources .................................................................. 79
Primary Oscillator with PLL............................... 105
RTSP Operation ......................................................... 78
Control Registers ........................................................ 26
Flexible Configuration ....................................................... 277
Data Space Addressing .............................................. 21
Instruction Set ............................................................. 21 G
Registers ..................................................................... 21 Getting Started Guidelines.................................................. 15
Resources ................................................................... 25 Connection Requirements .......................................... 15
Customer Change Notification Service ............................. 384 CPU Logic Filter Capacitor Connection (VCAP) .......... 16
Customer Notification Service........................................... 384 Decoupling Capacitors................................................ 15
Customer Support ............................................................. 384 External Oscillator Pins............................................... 17
D ICSP Pins ................................................................... 17
Master Clear (MCLR) Pin ........................................... 16
Data Address Space ........................................................... 37
Oscillator Value Conditions on Start-up...................... 18
Memory Map for dsPIC33EP16GS50X Devices ......... 38
Targeted Applications ................................................. 18
Unused I/Os................................................................ 18
Near Data Space ........................................................ 37 H
Organization, Alignment.............................................. 37 High-Speed Analog Comparator
SFR Space.................................................................. 37 Applications .............................................................. 265
Width ........................................................................... 37 Description................................................................ 264
Data Space Digital-to-Analog Comparator (DAC) ........................ 265
Extended X ................................................................. 69 Features Overview.................................................... 263
Paged Data Memory Space (figure) ........................... 67 Hysteresis ................................................................. 266
Paged Memory Scheme ............................................. 66 Pulse Stretcher and Digital Logic.............................. 265
DC Characteristics Resources ................................................................ 266
Brown-out Reset (BOR) ............................................ 313 High-Speed PWM
Constant-Current Source Specifications ................... 347 Description................................................................ 181
DACx Output (DACOUTx Pin) Specifications ........... 346 Features ................................................................... 181
Doze Current (IDOZE) ................................................ 309 Resources ................................................................ 182
I/O Pin Input Specifications ....................................... 310 Write-Protected Registers......................................... 182
I/O Pin Output Specifications .................................... 313 High-Speed, 12-Bit Analog-to-Digital
Idle Current (IIDLE) .................................................... 307 Converter (ADC) ....................................................... 229
Operating Current (IDD)............................................. 306 Control Registers ...................................................... 232
Operating MIPS vs. Voltage...................................... 304 Features Overview.................................................... 229
Power-Down Current (IPD) ........................................ 308 Resources ................................................................ 232
Program Memory ...................................................... 314
Temperature and Voltage Specifications .................. 305 I
Watchdog Timer Delta Current (IWDT) .................... 308 I/O Ports............................................................................ 125
DC/AC Characteristics Configuring Analog/Digital Port Pins......................... 126
Graphs and Tables ................................................... 349 Helpful Tips............................................................... 132
Demo/Development Boards, Evaluation and Open-Drain Configuration......................................... 126
Starter Kits ................................................................ 302 Parallel I/O (PIO) ...................................................... 125
Development Support ....................................................... 299 Resources ................................................................ 133
Device Calibration ............................................................. 283 Write/Read Timing .................................................... 126
Addresses ................................................................. 283 In-Circuit Debugger........................................................... 287
and Identification ....................................................... 283 MPLAB ICD 3 ........................................................... 301
Device Programmer PICkit 3 Programmer ................................................ 301
MPLAB PM3 ............................................................. 301 In-Circuit Emulation .......................................................... 277
Doze Mode........................................................................ 117 In-Circuit Serial Programming (ICSP)....................... 277, 287
DSP Engine......................................................................... 30 Input Capture .................................................................... 171
Control Registers ...................................................... 172
E
Resources ................................................................ 171
Electrical Characteristics................................................... 303 Input Change Notification (ICN)........................................ 126
AC ............................................................................. 315
Equations
Device Operating Frequency .................................... 105
FPLLO Calculation...................................................... 105
FVCO Calculation....................................................... 105
Errata .................................................................................. 10

Instruction Addressing Modes............................................. 70 P
File Register Instructions ............................................ 70
Packaging ......................................................................... 353
Fundamental Modes Supported.................................. 70
Details....................................................................... 355
MAC Instructions......................................................... 71
Marking..................................................................... 353
MCU Instructions ........................................................ 70
Peripheral Module Disable (PMD) .................................... 117
Move and Accumulator Instructions............................ 71
Peripheral Pin Select (PPS).............................................. 127
Other Instructions........................................................ 71
Available Peripherals................................................ 127
Instruction Set Summary................................................... 289
Available Pins ........................................................... 127
Overview ................................................................... 292
Control ...................................................................... 127
Symbols Used in Opcode Descriptions..................... 290
Control Registers...................................................... 134
Instruction-Based Power-Saving Modes ........................... 115
Input Mapping........................................................... 128
Idle ............................................................................ 116
Output Mapping ........................................................ 130
Sleep......................................................................... 116
Output Selection for Remappable Pins .................... 131
Inter-Integrated Circuit (I2C).............................................. 215
Selectable Input Sources.......................................... 129
PGA
Resources................................................................. 215
Pinout I/O Descriptions (table)............................................ 12
Inter-Integrated Circuit. See I2C.
Power-Saving Features .................................................... 115
Internet Address................................................................ 384
Clock Frequency and Switching ............................... 115
Interrupt Controller
Resources ................................................................ 117
Alternate Interrupt Vector Table (AIVT) ...................... 89
Program Address Space..................................................... 31
Control and Status Registers ...................................... 94
Construction ............................................................... 75
INTCON1 ............................................................ 94
Data Access from Program Memory Using
INTCON2 ............................................................ 94
Table Instructions ............................................... 76
INTCON3 ............................................................ 94
Memory Map (dsPIC33EP16GS50X Devices) ........... 32
INTCON4 ............................................................ 94
INTTREG ............................................................ 94
Memory Map (dsPIC33EP64GS50X Devices,
Interrupt Vector Details ............................................... 92
Dual Partition)..................................................... 35
Interrupt Vector Table (IVT) ........................................ 89
Reset Sequence ......................................................... 89
Table Read High Instructions (TBLRDH) ................... 76
Resources................................................................... 94
Table Read Low Instructions (TBLRDL) ..................... 76
Interrupts Coincident with Power Save Instructions.......... 116
Program Memory
J Interfacing with Data Memory Spaces........................ 75
Organization ............................................................... 36
JTAG Boundary Scan Interface ........................................ 277
Reset Vector............................................................... 36
JTAG Interface .................................................................. 287
Programmable Gain Amplifier (PGA)................................ 271
L Description................................................................ 272
Leading-Edge Blanking (LEB)........................................... 181 Resources ................................................................ 273
LPRC Oscillator Programmable Gain Amplifier. See PGA.
Programmer’s Model .......................................................... 23
Use with WDT ........................................................... 286
Register Descriptions ................................................. 23
M
R
Memory Organization.......................................................... 31
Register Maps
Resources................................................................... 41
ADC ............................................................................ 54
Microchip Internet Web Site .............................................. 384
Analog Comparator .................................................... 61
Modulo Addressing ............................................................. 72
Configuration Registers ............................................ 278
Applicability ................................................................. 73
Constant-Current Source............................................ 60
Operation Example ..................................................... 72
CPU Core ................................................................... 42
Start and End Address................................................ 72
I2C1 and I2C2 ............................................................ 52
W Address Register Selection .................................... 72
Input Capture 1 through Input Capture 4.................... 47
MPLAB REAL ICE In-Circuit Emulator System................. 301
Interrupt Controller...................................................... 44
MPLAB X Integrated Development
JTAG Interface ........................................................... 61
Environment Software............................................... 299
NVM............................................................................ 59
MPLINK Object Linker/MPLIB Object Librarian ................ 300
Output Compare 1 through Output Compare 4 .......... 48
O Peripheral Pin Select Input ......................................... 58
Oscillator Peripheral Pin Select Output
Control Registers ...................................................... 107 (dsPIC33EPXXGS502 Devices)......................... 56
Resources................................................................. 106 Peripheral Pin Select Output
Output Compare ............................................................... 175 (dsPIC33EPXXGS504/505 Devices).................. 56
Control Registers ...................................................... 176 Peripheral Pin Select Output
Resources................................................................. 175 (dsPIC33EPXXGS506 Devices)......................... 57

PMD ............................................................................ 60 ADTRIGxL (ADC Channel Trigger x
PORTA (dsPIC33EPXXGS502 Devices) .................... 62 Selection Low) .................................................. 251
PORTA (dsPIC33EPXXGS504/505 Devices) ............. 63 ALTDTRx (PWMx Alternate Dead-Time).................. 197
PORTA (dsPIC33EPXXGS506 Devices) .................... 64 AUXCONx (PWMx Auxiliary Control) ....................... 205
PORTB (dsPIC33EPXXGS502 Devices) .................... 62 CHOP (PWMx Chop Clock Generator)..................... 190
PORTB (dsPIC33EPXXGS504/505 Devices) ............. 63 CLKDIV (Clock Divisor) ............................................ 109
PORTB (dsPIC33EPXXGS506 Devices) .................... 64 CMPxCON (Comparator x Control) .......................... 267
PORTC (dsPIC33EPXXGS504/505 Devices)............. 63 CMPxDAC (Comparator x DAC Control) .................. 269
PORTC (dsPIC33EPXXGS506 Devices).................... 64 CORCON (Core Control) ...................................... 28, 96
PORTD (dsPIC33EPXXGS506 Devices).................... 65 CTXTSTAT (CPU W Register Context Status)........... 29
Programmable Gain Amplifier ..................................... 60 DEVID (Device ID).................................................... 284
PWM ........................................................................... 49 DEVREV (Device Revision)...................................... 284
PWM Generator 1 ....................................................... 49 DTRx (PWMx Dead-Time)........................................ 197
PWM Generator 2 ....................................................... 50 FCLCONx (PWMx Fault Current-Limit Control)........ 201
PWM Generator 3 ....................................................... 50 I2CxCONH (I2Cx Control High) ................................ 219
PWM Generator 4 ....................................................... 51 I2CxCONL (I2Cx Control Low) ................................. 217
PWM Generator 5 ....................................................... 51 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 222
SPI1 and SPI2 ............................................................ 53 I2CxSTAT (I2Cx Status) ........................................... 220
System Control ........................................................... 59 ICxCON1 (Input Capture x Control 1)....................... 172
Timer1 through Timer5 ............................................... 46 ICxCON2 (Input Capture x Control 2)....................... 173
UART1 and UART2 .................................................... 52 INTCON1 (Interrupt Control 1).................................... 97
Registers INTCON2 (Interrupt Control 2).................................... 99
ACLKCON (Auxiliary Clock Divisor Control) ............. 112 INTCON3 (Interrupt Control 3).................................. 100
ADCAL0H (ADC Calibration 0 High) ......................... 256 INTCON4 (Interrupt Control 4).................................. 100
ADCAL0L (ADC Calibration 0 Low) .......................... 255 INTTREG (Interrupt Control and Status) .................. 101
ADCAL1H (ADC Calibration 1 High) ......................... 257 IOCONx (PWMx I/O Control).................................... 199
ADCMPxCON (ADC Digital Comparator x ISRCCON (Constant-Current Source Control) ......... 276
Control) ............................................................. 258 LEBCONx (PWMx Leading-Edge
ADCMPxENH (ADC Digital Comparator x Blanking Control) .............................................. 203
Channel Enable High)....................................... 259 LEBDLYx (PWMx Leading-Edge
ADCMPxENL (ADC Digital Comparator x Blanking Delay) ................................................ 204
Channel Enable Low)........................................ 259 LFSR (Linear Feedback Shift) .................................. 114
ADCON1H (ADC Control 1 High) ............................. 233 MDC (PWMx Master Duty Cycle) ............................. 191
ADCON1L (ADC Control 1 Low) ............................... 232 NVMADR (Nonvolatile Memory
ADCON2H (ADC Control 2 High) ............................. 235 Lower Address) .................................................. 83
ADCON2L (ADC Control 2 Low) ............................... 234 NVMADRU (Nonvolatile Memory
ADCON3H (ADC Control 3 High) ............................. 237 Upper Address) .................................................. 83
ADCON3L (ADC Control 3 Low) ............................... 236 NVMCON (Nonvolatile Memory (NVM) Control)......... 81
ADCON4H (ADC Control 4 High) ............................. 239 NVMKEY (Nonvolatile Memory Key) .......................... 84
ADCON4L (ADC Control 4 Low) ............................... 238 NVMSRCADR (NVM Source Data Address) .............. 84
ADCON5H (ADC Control 5 High) ............................. 241 OCxCON1 (Output Compare x Control 1) ................ 176
ADCON5L (ADC Control 5 Low) ............................... 240 OCxCON2 (Output Compare x Control 2) ................ 178
ADCORExH (Dedicated ADC Core x OSCCON (Oscillator Control) ................................... 107
Control High)..................................................... 243 OSCTUN (FRC Oscillator Tuning)............................ 111
ADCORExL (Dedicated ADC Core x PDCx (PWMx Generator Duty Cycle)....................... 194
Control Low)...................................................... 242 PGAxCAL (PGAx Calibration) .................................. 274
ADEIEH (ADC Early Interrupt Enable High) ............. 245 PGAxCON (PGAx Control) ....................................... 273
ADEIEL (ADC Early Interrupt Enable Low) ............... 245 PHASEx (PWMx Primary Phase-Shift)..................... 195
ADEISTATH (ADC Early Interrupt Status High)........ 246 PLLFBD (PLL Feedback Divisor).............................. 110
ADEISTATL (ADC Early Interrupt Status Low) ......... 246 PMD1 (Peripheral Module Disable Control 1)........... 118
ADFLxCON (ADC Digital Filter x Control)................. 260 PMD2 (Peripheral Module Disable Control 2)........... 119
ADIEH (ADC Interrupt Enable High) ......................... 249 PMD3 (Peripheral Module Disable Control 3)........... 120
ADIEL (ADC Interrupt Enable Low) .......................... 249 PMD4 (Peripheral Module Disable Control 4)........... 120
ADLVLTRGH (ADC Level-Sensitive Trigger PMD6 (Peripheral Module Disable Control 6)........... 121
Control High)..................................................... 244 PMD7 (Peripheral Module Disable Control 7)........... 122
ADLVLTRGL (ADC Level-Sensitive Trigger PMD8 (Peripheral Module Disable Control 8)........... 123
Control Low)...................................................... 244 PTCON (PWMx Time Base Control) ........................ 185
ADMOD0H (ADC Input Mode Control 0 High) .......... 247 PTCON2 (PWMx Clock Divider Select 2) ................. 186
ADMOD0L (ADC Input Mode Control 0 Low) ........... 247 PTPER (PWMx Primary Master
ADMOD1L (ADC Input Mode Control 1 Low) ........... 248 Time Base Period)............................................ 187
ADSTATH (ADC Data Ready Status High)............... 250 PWMCAPx (PWMx Primary
ADSTATL (ADC Data Ready Status Low) ................ 250 Time Base Capture) ......................................... 206
ADTRIGxH (ADC Channel Trigger x PWMCONx (PWMx Control)..................................... 192
Selection High).................................................. 253 PWMKEY (PWMx Protection Lock/Unlock Key)....... 191
RCON (Reset Control)................................................ 87

REFOCON (Reference Oscillator Control) ............... 113 Resets ................................................................................ 85
RPINR0 (Peripheral Pin Select Input 0).................... 134 Brown-out Reset (BOR).............................................. 85
RPINR1 (Peripheral Pin Select Input 1).................... 134 Configuration Mismatch Reset (CM) .......................... 85
RPINR11 (Peripheral Pin Select Input 11)................ 139 Illegal Condition Reset (IOPUWR) ............................. 85
RPINR12 (Peripheral Pin Select Input 12)................ 140 Illegal Opcode .................................................... 85
RPINR13 (Peripheral Pin Select Input 13)................ 141 Security .............................................................. 85
RPINR18 (Peripheral Pin Select Input 18)................ 142 Uninitialized W Register ..................................... 85
RPINR19 (Peripheral Pin Select Input 19)................ 143 Master Clear (MCLR) Pin Reset................................. 85
RPINR2 (Peripheral Pin Select Input 2).................... 135 Power-on Reset (POR)............................................... 85
RPINR20 (Peripheral Pin Select Input 20)................ 144 RESET Instruction (SWR) .......................................... 85
RPINR21 (Peripheral Pin Select Input 21)................ 145 Resources .................................................................. 86
RPINR22 (Peripheral Pin Select Input 22)................ 146 Trap Conflict Reset (TRAPR) ..................................... 85
RPINR23 (Peripheral Pin Select Input 23)................ 147 Watchdog Timer Time-out Reset (WDTO) ................. 85
RPINR3 (Peripheral Pin Select Input 3).................... 136 Revision History................................................................ 377
RPINR37 (Peripheral Pin Select Input 37)................ 148
RPINR38 (Peripheral Pin Select Input 38)................ 149 S
RPINR42 (Peripheral Pin Select Input 42)................ 150 Serial Peripheral Interface (SPI) ....................................... 207
RPINR43 (Peripheral Pin Select Input 43)................ 151 Serial Peripheral Interface. See SPI.
RPINR7 (Peripheral Pin Select Input 7).................... 137 Software Simulator
RPINR8 (Peripheral Pin Select Input 8).................... 138 MPLAB X SIM........................................................... 301
RPOR0 (Peripheral Pin Select Output 0).................. 152 Special Features of the CPU ............................................ 277
RPOR1 (Peripheral Pin Select Output 1).................. 152 SPI
RPOR10 (Peripheral Pin Select Output 10).............. 157 Control Registers...................................................... 209
RPOR11 (Peripheral Pin Select Output 11).............. 157 Helpful Tips............................................................... 208
RPOR12 (Peripheral Pin Select Output 12).............. 158 Resources ................................................................ 208
RPOR13 (Peripheral Pin Select Output 13).............. 158
RPOR14 (Peripheral Pin Select Output 14).............. 159
T
RPOR15 (Peripheral Pin Select Output 15).............. 159 Thermal Operating Conditions.......................................... 304
RPOR16 (Peripheral Pin Select Output 16).............. 160 Thermal Packaging Characteristics .................................. 304
RPOR17 (Peripheral Pin Select Output 17).............. 160 Third-Party Development Tools ........................................ 302
RPOR18 (Peripheral Pin Select Output 18).............. 161 Timer1 .............................................................................. 163
RPOR2 (Peripheral Pin Select Output 2).................. 153 Control Register........................................................ 165
RPOR3 (Peripheral Pin Select Output 3).................. 153 Mode Settings........................................................... 163
RPOR4 (Peripheral Pin Select Output 4).................. 154 Resources ................................................................ 164
RPOR5 (Peripheral Pin Select Output 5).................. 154 Timer2/3 and Timer4/5 ..................................................... 167
RPOR6 (Peripheral Pin Select Output 6).................. 155 Control Registers...................................................... 169
RPOR7 (Peripheral Pin Select Output 7).................. 155 Resources ................................................................ 167
RPOR8 (Peripheral Pin Select Output 8).................. 156 Timing Diagrams
RPOR9 (Peripheral Pin Select Output 9).................. 156 BOR and Master Clear Reset Characteristics .......... 319
SDCx (PWMx Secondary Duty Cycle) ...................... 194 External Clock .......................................................... 316
SEVTCMP (PWMx Special Event Compare)............ 187 High-Speed PWMx Fault Characteristics ................. 325
SPHASEx (PWMx Secondary Phase-Shift).............. 196 High-Speed PWMx Module Characteristics ............. 325
SPIxCON1 (SPIx Control 1)...................................... 211 I/O Characteristics .................................................... 319
SPIxCON2 (SPIx Control 2)...................................... 213 I2Cx Bus Data (Master Mode) .................................. 338
SPIxSTAT (SPIx Status and Control) ....................... 209 I2Cx Bus Data (Slave Mode) .................................... 340
SR (CPU STATUS)............................................... 26, 95 I2Cx Bus Start/Stop Bits (Master Mode)................... 338
SSEVTCMP (PWMx Secondary I2Cx Bus Start/Stop Bits (Slave Mode)..................... 340
Special Event Compare) ................................... 190 Input Capture x (ICx) Characteristics ....................... 323
STCON (PWMx Secondary Master OCx/PWMx Characteristics ...................................... 324
Time Base Control) ........................................... 188 Output Compare x (OCx) Characteristics ................. 324
STCON2 (PWMx Secondary Clock Divider SPIx Master Mode (Full-Duplex, CKE = 0,
Select 2)............................................................ 189 CKP = x, SMP = 1) ........................................... 329
STPER (PWMx Secondary Master SPIx Master Mode (Full-Duplex, CKE = 1,
Time Base Period) ............................................ 189 CKP = x, SMP = 1) ........................................... 328
STRIGx (PWMx Secondary Trigger SPIx Master Mode (Half-Duplex,
Compare Value)................................................ 202 Transmit Only, CKE = 0) .................................. 326
T1CON (Timer1 Control)........................................... 165 SPIx Master Mode (Half-Duplex,
TRGCONx (PWMx Trigger Control).......................... 198 Transmit Only, CKE = 1) .................................. 327
TRIGx (PWMx Primary Trigger SPIx Slave Mode (Full-Duplex, CKE = 0,
Compare Value)................................................ 200 CKP = 0, SMP = 0) ........................................... 336
TxCON (Timer2/4 Control)........................................ 169 SPIx Slave Mode (Full-Duplex, CKE = 0,
TyCON (Timer3/5 Control)........................................ 170 CKP = 1, SMP = 0) ........................................... 334
UxMODE (UARTx Mode).......................................... 225 SPIx Slave Mode (Full-Duplex, CKE = 1,
UxSTA (UARTx Status and Control)......................... 227 CKP = 0, SMP = 0) ........................................... 330

SPIx Slave Mode (Full-Duplex, CKE = 1, V
CKP = 1, SMP = 0) ........................................... 332
Voltage Regulator (On-Chip) ............................................ 285
Timer1-Timer5 External Clock Characteristics.......... 321
UARTx I/O Characteristics ........................................ 342 W
U Watchdog Timer (WDT)............................................ 277, 286
Programming Considerations ................................... 286
Unique Device Identifier (UDID).......................................... 31
WWW Address ................................................................. 384
Universal Asynchronous Receiver
WWW, On-Line Support ..................................................... 10
Transmitter (UART)................................................... 223
Helpful Tips ............................................................... 224
Resources ................................................................. 224
Universal Asynchronous Receiver Transmitter. See UART.
User OTP Memory ............................................................ 285

THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design Customers should contact their distributor,
resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for
documents, latest software releases and archived support. Local sales offices are also available to help
software customers. A listing of sales offices and locations is
• General Technical Support – Frequently Asked included in the back of this document.
Questions (FAQ), technical support requests, Technical support is available through the web site
online discussion groups, Microchip consultant at: http://microchip.com/support
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

NOTES:

PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC 33 EP 64 GS5 04 T - I / PT XXX Examples:
dsPIC33EP64GS504-I/PT:
Microchip Trademark dsPIC33, Enhanced Performance,
64-Kbyte Program Memory, SMPS,
Architecture
44-Pin, Industrial Temperature,
Flash Memory Family TQFP Package.
Program Memory Size (Kbyte)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture: 33 = 16-Bit Digital Signal Controller
Flash Memory Family: EP = Enhanced Performance
Product Group: GS = SMPS Family
Pin Count: 02 = 28-pin

04 = 44-pin
05 = 48-pin
06 = 64-pin
Temperature Range: I = -40C to +85C (Industrial)

E = -40C to +125C (Extended)
Package: 2N = Ultra Thin Quad Flat, No Lead – (28-pin) 6x6 mm (UQFN)

ML = Plastic Quad Flat, No Lead – (44-pin) 8x8 mm body (QFN)
MM = Plastic Quad Flat, No Lead – (28-pin) 6x6 mm body (QFN-S)
PT = Plastic Thin Quad Flatpack – (44-pin) 10x10 mm body (TQFP)
PT = Plastic Thin Quad Flatpack – (64-pin) 10x10 mm body (TQFP)
SO = Plastic Small Outline, Wide – (28-pin) 7.50 mm body (SOIC)
Y8 = Thin Quad Flatpack – (48-pin) 7x7 mm (TQFP)

NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
ensure that your application meets with your specifications. CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
MICROCHIP MAKES NO REPRESENTATIONS OR KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries.
arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company,
devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A.
suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
intellectual property rights unless otherwise stated. CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
Microchip received ISO/TS-16949:2009 certification for its worldwide the U.S.A.
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California Silicon Storage Technology is a registered trademark of Microchip
and India. The Company’s quality system processes and procedures Technology Inc. in other countries.
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and GestIC is a registered trademark of Microchip Technology
analog products. In addition, Microchip’s quality system for the design Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
and manufacture of development systems is ISO 9001:2000 certified.
Inc., in other countries.
All other trademarks mentioned herein are property of their
QUALITY MANAGEMENT SYSTEM respective companies.

© 2013-2017, Microchip Technology Incorporated, All Rights
CERTIFIED BY DNV Reserved.
ISBN: 978-1-5224-1714-9
== ISO/TS 16949 ==

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11/07/16

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dsPIC33EPXXGS50X FAMILY

16-Bit Digital Signal Controllers for Digital Power Applications with

Operating Conditions Advanced Analog Features

High-Speed PWM Timers/Output Compare/Input Capture

 2013-2017 Microchip Technology Inc. DS70005127D-page 1

Input/Output Debugger Development Support

dsPIC33EP16GS502 28 16K 2K 21 5 4 4 2 2 5x2 3 1 2 12 5 2 4 1 1 SOIC,

dsPIC33EP16GS504 44 16K 2K 35 5 4 4 2 2 5x2 3 1 2 19 5 2 4 1 1

DS70005127D-page 2  2013-2017 Microchip Technology Inc.

Pin Pin Function Pin Pin Function

Legend: Shaded pins are up to 5 VDC tolerant.

 2013-2017 Microchip Technology Inc. DS70005127D-page 3

28-Pin QFN-S, UQFN

Pin Pin Function Pin Pin Function

Legend: Shaded pins are up to 5 VDC tolerant.

DS70005127D-page 4  2013-2017 Microchip Technology Inc.

Pin Pin Function Pin Pin Function

Legend: Shaded pins are up to 5 VDC tolerant.

 2013-2017 Microchip Technology Inc. DS70005127D-page 5

Pin Pin Function Pin Pin Function

Legend: Shaded pins are up to 5 VDC tolerant.

DS70005127D-page 6  2013-2017 Microchip Technology Inc.

Pin Pin Function Pin Pin Function

Legend: Shaded pins are up to 5 VDC tolerant.

 2013-2017 Microchip Technology Inc. DS70005127D-page 7

Legend: Shaded pins are up to 5 VDC tolerant.

DS70005127D-page 8  2013-2017 Microchip Technology Inc.

 2013-2017 Microchip Technology Inc. DS70005127D-page 9

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS70005127D-page 10  2013-2017 Microchip Technology Inc.

FIGURE 1-1: dsPIC33EPXXGS50X FAMILY BLOCK DIAGRAM

Peripheral Modules PORTD

Constant Analog Ports

 2013-2017 Microchip Technology Inc. DS70005127D-page 11

DS70005127D-page 12  2013-2017 Microchip Technology Inc.

 2013-2017 Microchip Technology Inc. DS70005127D-page 13

DS70005127D-page 14  2013-2017 Microchip Technology Inc.

 2013-2017 Microchip Technology Inc. DS70005127D-page 15

DS70005127D-page 16  2013-2017 Microchip Technology Inc.

 2013-2017 Microchip Technology Inc. DS70005127D-page 17

2.8 Unused I/Os

FIGURE 2-4: INTERLEAVED PFC

PGA/ADC Channel PWM PGA/ADC PWM PGA/ADC ADC

DS70005127D-page 18  2013-2017 Microchip Technology Inc.

FET PWM PGA/ADC PWM ADC

 2013-2017 Microchip Technology Inc. DS70005127D-page 19

FET FET FET FET FET FET

PWM PWM PGA/ADC ADC PWM PWM PWM PWM

DS70005127D-page 20  2013-2017 Microchip Technology Inc.

 2013-2017 Microchip Technology Inc. DS70005127D-page 21

Interrupt Data Latch Data Latch

Control Signals Instruction

Power, Reset Ports

DS70005127D-page 22  2013-2017 Microchip Technology Inc.

TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

 2013-2017 Microchip Technology Inc. DS70005127D-page 23

PUSH.s and POP.s Shadows

AD39 AD31 AD15 AD0