PIC32MZ

PIC32MZ Graphics (DA) Family
32-bit Graphics Applications MCUs (up to 2 MB Live Update Flash,

640 KB SRAM, and 32 MB DDR2 SDRAM) with XLP Technology
Operating Conditions Advanced Analog Features

2.2V to 3.6V, -40C to +85C, DC to 200 MHz 12-bit ADC modules:
2.2V to 3.6V, -40C to +105C (Planned) - 18 Msps with up to six ADC circuits (five dedicated and one
shared)
Core: 200 MHz / 330 DMIPS MIPS32 microAptiv - Up to 45 analog input
32 KB I-Cache, 32 KB D-Cache - Can operate during Sleep and Idle modes
MMU for optimum embedded OS execution - Multiple trigger sources
microMIPS mode for up to 35% smaller code size - Six Digital Comparators and six Digital Filters
DSP-enhanced core:
Two Comparators with 32 programmable voltage references
- Four 64-bit accumulators
- Single-cycle MAC, saturating and fractional math Temperature sensor with 2C accuracy
Code-efficient (C and Assembly) architecture Charge Time Measurement Unit (CTMU)
Clock Management Communication Interfaces
Programmable PLLs and oscillator clock sources Two CAN modules (with dedicated DMA channels):
Dedicated PLL for DDR2 - 2.0B Active with DeviceNet addressing support
Fail-Safe Clock Monitor Six UART modules (25 Mbps):
Independent Watchdog and Deadman Timers - Supports LIN 1.2 and IrDA protocols
Fast wake-up and start-up Six 4-wire SPI modules (up to 50 MHz)
Power Management SQI configurable as additional SPI module (up to 80 MHz)
Various power management options for extreme power Five I2C modules (up to 1 Mbaud) with SMBus support
reduction (VBAT, Deep Sleep, Sleep and Idle) Parallel Master Port (PMP)
Deep Sleep current: < 1 A (typical) Peripheral Pin Select (PPS) to enable function remap
Integrated POR and BOR
Programmable High/Low-Voltage Detect (HLVD) on VDDIO Timers/Output Compare/Input Capture
and High-Voltage Detect (HVD) on VDDR1V8 Nine 16-bit and up to four 32-bit timers/counters
Nine Output Compare (OC) modules
Memory Interfaces Nine Input Capture (IC) modules
DDR2 SDRAM interface (up to DDR2-400) Real-Time Clock and Calendar (RTCC) module
SD/SDIO/eMMC bus interface (up to 50 MHz)
Serial Quad Interface (up to 80 MHz) Input/Output
External Bus Interface (up to 50 MHz) 5V-tolerant pins with up to 32 mA source/sink
Graphics Features Selectable open drain, pull-ups, and pull-downs
3-layer Graphics Controller with up to 24-bit color support Selectable slew rate control
High-performance 2D Graphics Processing Unit (GPU) External interrupts on all I/O pins
PPS to enable function remap
Audio Interfaces
Audio data communication: I2S, LJ, and RJ Qualification and Class B Support
Audio control interfaces: SPI and I2C AEC-Q100 REVG (Grade 2 -40C to +105C) (Planned)
Audio master clock: Fractional clock frequencies with USB Class B Safety Library, IEC 60730
synchronization Back-up internal oscillator
High-Speed Communication Interfaces (with Debugger Development Support
Dedicated DMA) In-circuit and in-application programming
USB 2.0-compliant High-Speed On-The-Go (OTG) controller 4-wire MIPS Enhanced JTAG interface
10/100 Mbps Ethernet MAC with MII and RMII interface Unlimited software and 12 complex breakpoints
Security Features IEEE 1149.2-compatible (JTAG) boundary scan
Crypto Engine with a RNG for data encryption/decryption and Non-intrusive hardware-based instruction trace
authentication (AES, 3DES, SHA, MD5, and HMAC)
Advanced memory protection: Integrated Software Libraries and Tools
- Peripheral and memory region access control C/C++ compiler with native DSP/fractional support
MPLAB Harmony Integrated Software Framework
Direct Memory Access (DMA) TCP/IP, USB, Graphics, and mTouch middleware
Eight channels with automatic data size detection MFi, Android, and Bluetooth audio frameworks
Programmable Cyclic Redundancy Check (CRC)
RTOS Kernels: Express Logic ThreadX, FreeRTOS,
OPENRTOS, Micrim C/OS, and SEGGER embOS
Packages
Type LFBGA LQFP
Pin Count 169 288 176
I/O Pins (up to) 120 120 120
Contact/Lead Pitch 0.8 mm 0.8 mm 0.4 mm
Dimensions 11x11 mm 15x15 mm 20x20 mm
2015-2017 Microchip Technology Inc. DS60001361E-page 1

TABLE 1: PIC32MZ DA FEATURES COMMON TO ALL DEVICES
Remappable Peripherals
Boot Flash Memory (KB)
Analog Comparators
12-bit ADC Channels
USB 2.0 HS OTG

External Interrupts(2)
Timers(1)/Capture/
Remappable Pins
Ethernet
I/O Pins
CTMU
GLCD
SDHC
RTCC
Trace
JTAG
CAN 2.0B
Compare
GPU
PMP
SQI
EBI
I2C
SPI/I2S
UART
160 47 9/9/9 6 6 2 5 45 2 Y Y 5 Y Y Y Y Y Y Y Y 120 Y Y

Note 1: Eight out of nine timers are remappable.
2: Four out of five external interrupts are remappable.
TABLE 2: 169-PIN LFBGA PIC32MZ DA TABLE 3: 176-PIN LQFP PIC32MZ DA

FEATURES FEATURES
Interface (Internal/External)
Program Memory (KB)
Program Memory (KB
Data Memory (KB

DDR2 Controller
DDR2 Controller
(Programmable/
(Programmable/
DMA Channels
DMA Channels
DDR2 SDRAM
DDR2 SDRAM
Memory (KB)
Crypto/RNG
Crypto/RNG
Dedicated)
Dedicated)
Size (MB)
Size (MB)
Devices
Devices
Data
PIC32MZ1025DAA169 N 8/24 PIC32MZ1025DAA176 N 8/24

256 256
PIC32MZ1025DAB169 Y 8/26 PIC32MZ1025DAB176 Y 8/26
1024 1024
640 640
No No
256 256
2048 2048
640 640
PIC32MZ1025DAG169 N 8/24 PIC32MZ1025DAG176 N 8/24
256 256
PIC32MZ1025DAH169 Y 8/26 PIC32MZ1025DAH176 Y 8/26
1024 1024
640 640
PIC32MZ1064DAH169 Yes Y 8/26 PIC32MZ1064DAH176 Yes Y 8/26
32 32
PIC32MZ2025DAG169 (INT) N 8/24 PIC32MZ2025DAG176 (INT) N 8/24
256 256
2048 2048
640 640
TABLE 4: 288-PIN LFBGA PIC32MZ DA

FEATURES
(Programmable/Dedicated)
Program Memory (KB)
Data Memory (KB)
DDR2 Controller
DMA Channels
Crypto/RNG
Devices
PIC32MZ1025DAA288 N 8/24
256
PIC32MZ1025DAB288 Y 8/26
1024
PIC32MZ1064DAA288 N 8/24
640
PIC32MZ1064DAB288 Yes Y 8/26
PIC32MZ2025DAA288 (EXT) N 8/24
256
PIC32MZ2025DAB288 Y 8/26
2048
PIC32MZ2064DAA288 N 8/24
640
PIC32MZ2064DAB288 Y 8/26
DS60001361E-page 2 2015-2017 Microchip Technology Inc.

Device Pin Tables
TABLE 5: PIN NAMES FOR 169-PIN DEVICES
169-PIN LFBGA (BOTTOM VIEW)
PIC32MZ1025DAA169 N1
A1
PIC32MZ1025DAB169
PIC32MZ1064DAA169
PIC32MZ1064DAB169
PIC32MZ2025DAA169
PIC32MZ2025DAB169
PIC32MZ2064DAA169
N13
PIC32MZ2064DAB169
PIC32MZ1025DAG169
PIC32MZ1025DAH169
PIC32MZ1064DAG169
PIC32MZ1064DAH169 A13
PIC32MZ2025DAG169
PIC32MZ2025DAH169
PIC32MZ2064DAG169 Polarity Indicator
PIC32MZ2064DAH169
Ball/Pin Ball/Pin
Full Pin Name Full Pin Name
Number Number
A1 No Connect C5 EBIA2/AN23/C2INC/RPG9/PMA2/RG9
A2 VBUS C6 TDO/AN31/RPF12/RF12
A3 RPF2/SDA3/RF2 C7 EBID7/AN15/PMD7/RE7
A4 EBID1/AN39/PMD1/RE1 C8 AVSS
A5 AN21/RG15 C9 VDDCORE
A6 TDI/AN17/SCK5/RF13 C10 VREF+/CVREF+/AN28/RA10
A7 EBIWE/AN34/RPC3/PMWR/RC3 C11 CVREFOUT/AN5/RPB10/RB10
A8 EBID12/AN10/RPC2/PMD12/RC2 C12 PGED1/AN0/RPB0/CTED2/RB0
A9 EBID10/AN4/RPB8/PMD10/RB8 C13 SOSCI/RPC13(6)/RC13(6)
A10 AN8/RPB3/RB3 D1 TRD3/SDDATA3/SQID3/RA7
A11 EBIA5/AN7/PMA5/RA5 D2 TMS/SDCD/RA0
A12 AN2/C1INB/RB4 D3 USBID
A13 AN1/C2INB/RPB2/RB2 D4 AN20/RH4
B1 D- D5 AN13/C1INC/RPG7/SDA4/RG7
B2 VUSB3V3 D6 AN26/RPE9/RE9
B3 EBID4/AN18/PMD4/RE4 D7 PGEC2/RPB6/RB6
B4 VDDCORE D8 AVSS
B5 AN30/C2IND/RPG8/SCL4/RG8 D9 AVDD
B6 VDDIO D10 VBAT
B7 EBID5/AN12/RPC1/PMD5/RC1 D11 AN45/RPB5/RB5
B8 EBIOE/AN19/RPC4/PMRD/RC4 D12 PGED2/C1INA/AN46/RPB7/RB7
B9 PGEC1/AN9/RPB1/CTED1/RB1 D13 SOSCO/RPC14(6)/T1CK/RC14(6)
B10 AN3/C2INA/RPB15/OCFB/RB15 E1 TRD2/SDDATA2/SQID2/RG14
B11 VREF-/CVREF-/AN27/RA9 E2 TRD0/SDDATA0/SQID0/RG13
B12 EBIA7/AN47/HLVDIN/RPB9/PMA7/RB9 E3 TRD1/SDDATA1/SQID1/RG12
B13 AN6/RB12 E4 TRCLK/SDCK/SQICLK/RA6
C1 D+ E5 AN14/C1IND/SCK2/RG6
C2 VSS E6 AN25/RPE8/RE8
C3 INT0/RH14 E7 AN49/RB11
C4 EBID0/PMD0/RE0 E8 GD20/EBIA22/RJ3
Note 1: The RPn pins can be used by remappable peripherals. See Table 1 and Table 2 for the available peripherals and 12.4 Peripheral Pin
Select (PPS) for restrictions.
2: Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See 12.0 I/O Ports for more information.
3: Shaded pins are 5V tolerant.
4: This pin must be tied to Vss through a 20k resistor in devices without DDR.
5: This pin is a No Connect in devices without DDR.
6: These pins are restricted to input functions only.

TABLE 5: PIN NAMES FOR 169-PIN DEVICES (CONTINUED)
A1
PIC32MZ1025DAB169
PIC32MZ1064DAA169
PIC32MZ1064DAB169
PIC32MZ2025DAA169
PIC32MZ2025DAB169
PIC32MZ2064DAA169
N13
PIC32MZ2064DAB169
PIC32MZ1025DAG169
PIC32MZ1025DAH169
PIC32MZ1064DAG169
PIC32MZ2025DAG169
PIC32MZ2025DAH169
PIC32MZ2064DAH169
Ball/Pin Ball/Pin
Number Number
E9 AN22/RPD14/RD14 H2 SCK4/RD10
E10 AN29/SCK3/RB14 H3 RTCC/RPD0/RD0
E11 TCK/AN24/RA1 H4 VSS1V8
E12 OSC1/CLKI/RC12 H5 VDDR1V8(4)
E13 OSC2/CLKO/RC15 H6 VDDR1V8(4)
F1 SDCMD/SQICS0/RPD4/RD4 H7 VSS
F2 SQICS1/RPD5/RD5 H8 VSS
F3 EBIA6/RPE5/PMA6/RE5 H9 VDDIO
F4 DDRVREF(5) H10 GD13/EBIA18/RK4
F5 VSS H11 EBIA3/AN11/PMA3/RK2
F6 EBID6/AN16/PMD6/RE6 H12 SDWP/EBIRP/RH2
F7 AN48/CTPLS/RB13 H13 EBIA0/PMA0/RJ15
F8 GD18/EBIBS1/RJ10 J1 GD7/EBIA12/RPD12/PMA12/RD12
F9 GD9/EBIBS0/RJ12 J2 GD22/EBIA13/PMA13/RD13
F10 EBIRDY3/AN32/RJ2 J3 RPF8/SCL3/RF8
F11 AN33/SCK6/RD15 J4 VSS1V8
F12 HSYNC/EBICS1/RJ5 J5 VDDR1V8(4)
F13 VSYNC/EBICS0/RJ4 J6 VDDR1V8(4)
G1 SCK1/RD1 J7 VSS
G2 GD10/EBIA14/RPD2/PMA14/PMCS1/RD2 J8 VSS
G3 GD11/EBIA15/RPD3/PMA15/PMCS2/RD3 J9 VDDIO
G4 VSS1V8 J10 GD14/EBIA19/RK5
G5 VSS J11 EBIA1/AN38/PMA1/RK1
G6 VSS J12 EBIA4/AN36/PMA4/RH7
G7 VSS J13 AN35/RH3
G8 VSS K1 MCLR
G9 VDDIO K2 GD16/EBID8/RPF5/SCL5/PMD8/RF5
G10 GD8/EBID11/PMD11/RJ14 K3 GD5/EBIA10/RPF1/PMA10/RF1
G11 GCLK/EBICS2/RJ6 K4 VSS1V8
G12 GD0/EBID13/PMD13/RJ13 K5 VDDR1V8(4)
G13 GEN/EBICS3/RJ7 K6 VDDR1V8(4)
H1 GD2/EBID15/RPD9/PMD15/RD9 K7 Vss

A1
PIC32MZ1025DAB169
PIC32MZ1064DAA169
PIC32MZ1064DAB169
PIC32MZ2025DAA169
PIC32MZ2025DAB169
PIC32MZ2064DAA169
N13
PIC32MZ2064DAB169
PIC32MZ1025DAG169
PIC32MZ1025DAH169
PIC32MZ1064DAG169
PIC32MZ2025DAG169
PIC32MZ2025DAH169
PIC32MZ2064DAH169
Ball/Pin Ball/Pin
Number Number
K8 VSS M5 ERXDV/ECRSDV/RH13
K9 VDDIO M6 ECOL/RH10
K10 EMDIO/RJ1 M7 ETXD3/RH1
K11 ETXEN/RPD6/RD6 M8 ETXD2/RH0
K12 GD23/EBIA16/RK0 M9 ETXD1/RJ9
K13 EBIRDY2/AN37/RH11 M10 ETXCLK/RPD7/RD7
L1 GD6/EBIA11/RPF0/PMA11/RF0 M11 RPA14/SCL1/RA14
L2 GD21/EBIA23/RH15 M12 GD19/EBIA21/RK7
L3 GD17/EBID9/RPF4/SDA5/PMD9/RF4 M13 GD15/EBIA20/RK6
L4 VSS1V8 N1 VDDCORE
L5 VSS1V8 N2 GD3/EBIA8/RPG0/PMA8/RG0
L6 VDDIO N3 EBID2/PMD2/RE2
L7 VDDIO N4 ERXD2/RH6
L8 VDDCORE N5 ECRS/RH12
L9 VDDIO N6 ERXD3/RH9
L10 ETXERR/RJ0 N7 ERXD0/RH8
L11 GD1/EBID14/PMD14/RA4 N8 ERXCLK/EREFCLK/RJ11
L12 SCL2/RA2 N9 ETXD0/RJ8
L13 GD12/EBIA17/RK3 N10 EMDC/RPD11/RD11
M1 ERXERR/RPF3/RF3 N11 RPA15/SDA1/RA15
M2 GD4/EBIA9/RPG1/PMA9/RG1 N12 EBIRDY1/SDA2/RA3
M3 EBID3/RPE3/PMD3/RE3 N13 No Connect
M4 ERXD1/RH5

176-PIN LQFP (TOP VIEW)

PIC32MZ1025DAA176
PIC32MZ1025DAB176
PIC32MZ1064DAA176
PIC32MZ1064DAB176
PIC32MZ2025DAA176
PIC32MZ2025DAB176
PIC32MZ2064DAA176
PIC32MZ2064DAB176
PIC32MZ1025DAG176
PIC32MZ1025DAH176
PIC32MZ1064DAG176
PIC32MZ1064DAH176
PIC32MZ2025DAG176
PIC32MZ2025DAH176
PIC32MZ2064DAG176 176
PIC32MZ2064DAH176 1
Pin Full Pin Name Pin Full Pin Name

Number Number
1 VREF-/CVREF-/AN27/RA9 37 VSS
2 VREF+/CVREF+/AN28/RA10 38 VDDIO
3 AVDD 39 VDDCORE
4 AVDD 40 EBID0/PMD0/RE0
5 AVSS 41 RPF2/SDA3/RF2
6 AVSS 42 INT0/RH14
7 AN3/C2INA/RPB15/OCFB/RB15 43 EBID4/AN18/PMD4/RE4
8 AN8/RPB3/RB3 44 No Connect
9 AN48/CTPLS/RB13 45 VBUS
10 EBID10/AN4/RPB8/PMD10/RB8 46 VUSB3V3
11 PGEC1/AN9/RPB1/CTED1/RB1 47 VUSB3V3
12 AN49/RB11 48 VSS
13 PGEC2/RPB6/RB6 49 VSS
14 EBID12/AN10/RPC2/PMD12/RC2 50 D-
15 EBIWE/AN34/RPC3/PMWR/RC3 51 D+
16 EBIOE/AN19/RPC4/PMRD/RC4 52 USBID
17 EBID5/AN12/RPC1/PMD5/RC1 53 TMS/SDCD/RA0
18 VDDCORE 54 TRCLK/SDCK/SQICLK/RA6
19 VDDIO 55 TRD3/SDDATA3/SQID3/RA7
20 No Connect 56 TRD1/SDDATA1/SQID1/RG12
21 VSS 57 VDDR1V8(5)
22 VSS 58 VDDR1V8(5)
23 EBID6/AN16/PMD6/RE6 59 VDDR1V8(5)
25 AN25/RPE8/RE8 61 VDDR1V8(5)
26 AN26/RPE9/RE9 62 VDDR1V8(5)
27 TDO/AN31/RPF12/RF12 63 VDDR1V8(5)
28 TDI/AN17/SCK5/RF13 64 TRD0/SDDATA0/SQID0/RG13
29 VSS 65 TRD2/SDDATA2/SQID2/RG14
30 AN14/C1IND/SCK2/RG6 66 DDRVREF(6)
31 AN13/C1INC/RPG7/SDA4/RG7 67 VDDR1V8(5)
32 AN30/C2IND/RPG8/SCL4/RG8 68 VDDR1V8(5)
33 EBIA2/AN23/C2INC/RPG9/PMA2/RG9 69 EBIA6/RPE5/PMA6/RE5
34 AN21/RG15 70 SDCMD/SQICS0/RPD4/RD4
35 AN20/RH4 71 SQICS1/RPD5/RD5
4: The metal plane at the bottom of the device is internally tied to VSS1V8 and should be connected to 1.8V ground externally.


PIC32MZ1025DAA176
PIC32MZ1025DAB176
PIC32MZ1064DAA176
PIC32MZ1064DAB176
PIC32MZ2025DAA176
PIC32MZ2025DAB176
PIC32MZ2064DAA176
PIC32MZ2064DAB176
PIC32MZ1025DAG176
PIC32MZ1025DAH176
PIC32MZ1064DAG176
PIC32MZ1064DAH176
PIC32MZ2025DAG176
PIC32MZ2025DAH176
PIC32MZ2064DAG176 176
PIC32MZ2064DAH176 1

Number Number
73 SCK1/RD1 109 ETXD3/RH1
74 GD10/EBIA14/RPD2/PMA14/PMCS1/RD2 110 ETXD2/RH0
75 GD11/EBIA15/RPD3/PMA15/PMCS2/RD3 111 ERXCLK/EREFCLK/RJ11
76 GD2/EBID15/RPD9/PMD15/RD9 112 ETXD1/RJ9
77 SCK4/RD10 113 ETXD0/RJ8
78 VDDR1V8(5) 114 EMDIO/RJ1
79 RTCC/RPD0/RD0 115 VSS
80 GD7/EBIA12/RPD12/PMA12/RD12 116 VDDCORE
81 GD22/EBIA13/PMA13/RD13 117 VDDIO
82 RPF8/SCL3/RF8 118 ETXERR/RJ0
83 VSS 119 EMDC/RPD11/RD11
84 VDDCORE 120 ETXCLK/RPD7/RD7
85 MCLR 121 ETXEN/RPD6/RD6
86 VDDIO 122 VSS
87 VSS 123 VSS
88 No Connect 124 VDDIO
89 GD16/EBID8/RPF5/SCL5/PMD8/RF5 125 RPA15/SDA1/RA15
90 GD5/EBIA10/RPF1/PMA10/RF1 126 RPA14/SCL1/RA14
91 GD6/EBIA11/RPF0/PMA11/RF0 127 GD1/EBID14/PMD14/RA4
92 GD21/EBIA23/RH15 128 EBIRDY1/SDA2/RA3
93 ERXERR/RPF3/RF3 129 SCL2/RA2
94 VSS 130 GD19/EBIA21/RK7
95 GD4/EBIA9/RPG1/PMA9/RG1 131 GD15/EBIA20/RK6
96 GD3/EBIA8/RPG0/PMA8/RG0 132 GD14/EBIA19/RK5
97 GD17/EBID9/RPF4/SDA5/PMD9/RF4 133 GD13/EBIA18/RK4
98 EBID3/RPE3/PMD3/RE3 134 GD12/EBIA17/RK3
99 EBID2/PMD2/RE2 135 EBIA3/AN11/PMA3/RK2
100 ERXD1/RH5 136 EBIA1/AN38/PMA1/RK1
101 ERXD2/RH6 137 GD23/EBIA16/RK0
102 VDDIO 138 EBIRDY2/AN37/RH11
103 VSS 139 EBIA4/AN36/PMA4/RH7
104 ERXDV/ECRSDV/RH13 140 AN35/RH3
105 ECRS/RH12 141 SDWP/EBIRP/RH2
106 ECOL/RH10 142 EBIA0/PMA0/RJ15
107 ERXD3/RH9 143 GD8/EBID11/PMD11/RJ14
108 ERXD0/RH8 144 GD0/EBID13/PMD13/RJ13


PIC32MZ1025DAA176
PIC32MZ1025DAB176
PIC32MZ1064DAA176
PIC32MZ1064DAB176
PIC32MZ2025DAA176
PIC32MZ2025DAB176
PIC32MZ2064DAA176
PIC32MZ2064DAB176
PIC32MZ1025DAG176
PIC32MZ1025DAH176
PIC32MZ1064DAG176
PIC32MZ1064DAH176
PIC32MZ2025DAG176
PIC32MZ2025DAH176
PIC32MZ2064DAG176 176
PIC32MZ2064DAH176 1

Number Number
145 GD9/EBIBS0/RJ12 161 SOSCO/RPC14(7)/T1CK/RC14(7)
146 GD18/EBIBS1/RJ10 162 SOSCI/RPC13(7)/RC13(7)
147 GEN/EBICS3/RJ7 163 OSC2/CLKO/RC15
148 GCLK/EBICS2/RJ6 164 OSC1/CLKI/RC12
149 HSYNC/EBICS1/RJ5 165 VDDIO
150 VSYNC/EBICS0/RJ4 166 VBAT
151 GD20/EBIA22/RJ3 167 AN45/RPB5/RB5
152 EBIRDY3/AN32/RJ2 168 AN5/RPB10/RB10
153 VSS 169 PGED1/AN0/RPB0/CTED2/RB0
154 VSS 170 PGED2/C1INA/AN46/RPB7/RB7
155 VDDIO 171 AN6/RB12
156 VDDIO 172 AN1/C2INB/RPB2/RB2
157 AN33/SCK6/RD15 173 EBIA7/AN47/HLVDIN/RPB9/PMA7/RB9
158 AN22/RPD14/RD14 174 EBIA5/AN7/PMA5/RA5
159 AN29/SCK3/RB14 175 AN2/C1INB/RB4
160 TCK/AN24/RA1 176 No Connect

A1 V1
N6
PIC32MZ1025DAA288 F6
PIC32MZ1025DAB288
PIC32MZ1064DAA288
PIC32MZ1064DAB288 N13
PIC32MZ2025DAA288
PIC32MZ2025DAB288 F13
V18
PIC32MZ2064DAA288
PIC32MZ2064DAB288
A18
Polarity Indicator
Ball/Pin Ball/Pin
Number Number
A1 No Connect B17 AN2/C1INB/RB4
A2 DDRUDQS B18 EBIA5/AN7/PMA5/RA5
A3 DDRDM1 C1 DDRDQ8
A4 D- C2 DDRDQ15
A5 VSS C3 DDRDQ9
A6 INT0/RH14 C4 VUSB3V3
A7 RPF2/SDA3/RF2 C5 VBUS
A8 AN21/RG15 C6 USBID
A9 AN14/C1IND/SCK2/RG6 C7 VSS
A10 TDI/AN17/SCK5/RF13 C8 No Connect
A11 TDO/AN31/RPF12/RF12 C9 AN30/C2IND/RPG8/SCL4/RG8
A12 EBID5/AN12/RPC1/PMD5/RC1 C10 AN25/RPE8/RE8
A13 EBIOE/AN19/RPC4/PMRD/RC4 C11 EBID6/AN16/PMD6/RE6
A14 PGEC1/AN9/RPB1/CTED1/RB1 C12 No Connect
A15 EBID10/AN4/RPB8/PMD10/RB8 C13 EBID12/AN10/RPC2/PMD12/RC2
A16 AN8/RPB3/RB3 C14 AN49/RB11
A17 VREF-/CVREF-/AN27/RA9 C15 VREF+/CVREF+/AN28/RA10
A18 No Connect C16 VDDIO
B1 No Connect C17 AN1/C2INB/RPB2/RB2
B2 DDRUDQS C18 AN6/RB12
B3 DDRDQ14 D1 DDRDQ13
B4 D+ D2 DDRDQ10
B5 VSS D3 VSS1V8
B6 EBID4/AN18/PMD4/RE4 D4 TMS/SDCD/RA0
B7 EBID0/PMD0/RE0 D5 VUSB3V3
B8 AN20/RH4 D6 No Connect
B9 EBIA2/AN23/C2INC/RPG9/PMA2/RG9 D7 VDDCORE
B10 AN26/RPE9/RE9 D8 EBID1/AN39/PMD1/RE1
B11 EBID7/AN15/PMD7/RE7 D9 AN13/C1INC/RPG7/SDA4/RG7
B12 No Connect D10 VSS
B13 EBIWE/AN34/RPC3/PMWR/RC3 D11 VSS
B14 PGEC2/RPB6/RB6 D12 VSS
B15 AN48/CTPLS/RB13 D13 VSS
B16 AN3/C2INA/RPB15/OCFB/RB15 D14 VDDCORE
4: This pin must be tied to Vss through a 20k resistor when DDR is not connected in the system.
5: This pin is a No Connect when DDR is not connected in the system.

A1 V1
N6
PIC32MZ1025DAB288
PIC32MZ1064DAA288
PIC32MZ2025DAA288
V18
PIC32MZ2064DAA288
PIC32MZ2064DAB288
A18
Polarity Indicator
Ball/Pin Ball/Pin
Number Number
D15 VDDIO G8 VSS1V8
D16 VDDIO G9 VSS1V8
D17 PGED2/C1INA/AN46/RPB7/RB7 G10 VSS
D18 PGED1/AN0/RPB0/CTED2/RB0 G11 VDDIO
E1 DDRLDQS G12 AVSS
E2 DDRLDQS G13 AVDD
E3 DDRDQ12 G15 VDDIO
E4 TRCLK/SDCK/SQICLK/RA6 G16 No Connect
E15 VDDIO G17 OSC1/CLKI/RC12
E16 EBIA7/AN47/HLVDIN/RPB9/PMA7/RB9 G18 OSC2/CLKO/RC15
E17 AN45/RPB5/RB5 H1 DDRDQ2
E18 CVREFOUT/AN5/RPB10/RB10 H2 DDRDQ5
F1 DDRDQ0 H3 DDRDQ6
F2 DDRDQ7 H4 TRD0/SDDATA0/SQID0/RG13
F3 DDRDQ11 H6 VDDR1V8(4)
F4 TRD3/SDDATA3/SQID3/RA7 H7 VDDR1V8(4)
F6 VSS1V8 H8 VDDR1V8(4)
F7 VSS1V8 H9 VSS1V8
F8 VSS1V8 H10 VSS
F9 VSS H11 VDDIO
F10 VSS H12 VDDIO
F11 VDDIO H13 VDDIO
F12 AVSS H15 VDDIO
F13 AVDD H16 TCK/AN24/RA1
F15 VDDIO H17 SOSCI/RPC13(6)/RC13(6)
F16 VBAT H18 SOSCO/RPC14(6)/T1CK/RC14(6)
F17 No Connect J1 DDRVREF(5)
F18 No Connect J2 No Connect
G1 DDRDQ3 J3 DDRDQ1
G2 DDRDQ4 J4 TRD2/SDDATA2/SQID2/RG14
G3 DDRDM0 J6 VDDR1V8(4)
G4 TRD1/SDDATA1/SQID1/RG12 J7 VDDR1V8(4)
G6 VSS1V8 J8 VDDR1V8(4)
G7 VSS1V8 J9 VSS1V8

A1 V1
N6
PIC32MZ1025DAB288
PIC32MZ1064DAA288
PIC32MZ2025DAA288
V18
PIC32MZ2064DAA288
PIC32MZ2064DAB288
A18
Polarity Indicator
Ball/Pin Ball/Pin
Number Number
J10 VDDIO L12 VDDIO
J11 VSS L13 VSS
J12 VSS L15 VSS
J13 VSS L16 GEN/EBICS3/RJ7
J15 VDDIO L17 GCLK/EBICS2/RJ6
J16 AN33/SCK6/RD15 L18 HSYNC/EBICS1/RJ5
J17 AN29/SCK3/RB14 M1 DDRRAS
J18 AN22/RPD14/RD14 M2 DDRBA0
K1 DDRCK M3 DDRBA1
K2 DDRCK M4 SCK1/RD1
K3 EBIA6/RPE5/PMA6/RE5 M6 VSS1V8
K4 SDCMD/SQICS0/RPD4/RD4 M7 VSS1V8
K6 VDDR1V8(4) M8 VSS1V8
K7 VDDR1V8(4) M9 VSS1V8
K8 VDDR1V8(4) M10 VSS
K9 VSS1V8 M11 VSS
K10 VDDIO M12 VDDIO
K11 VSS M13 VDDIO
K12 VSS M15 VDDIO
K13 VSS M16 GD0/EBID13/PMD13/RJ13
K15 VSS M17 GD9/EBIBS0/RJ12
K16 EBIRDY3/AN32/RJ2 M18 GD18/EBIBS1/RJ10
K17 GD20/EBIA22/RJ3 N1 DDRODT
K18 VSYNC/EBICS0/RJ4 N2 DDRCS0
L1 DDRWE N3 DDRA2
L2 DDRCKE N4 GD22/EBIA13/PMA13/RD13
L3 DDRA1 N6 VSS1V8
L4 SQICS1/RPD5/RD5 N7 VSS1V8
L6 VDDR1V8(4) N8 VSS1V8
L7 VDDR1V8(4) N9 VSS1V8
L8 VDDR1V8(4) N10 VSS
L9 VSS1V8 N11 VSS
L10 VSS N12 VDDIO
L11 VDDIO N13 VDDIO

A1 V1
N6
PIC32MZ1025DAB288
PIC32MZ1064DAA288
PIC32MZ2025DAA288
V18
PIC32MZ2064DAA288
PIC32MZ2064DAB288
A18
Polarity Indicator
Ball/Pin Ball/Pin
Number Number
N15 EBIA4/AN36/PMA4/RH7 T5 No Connect
N16 SDWP/EBIRP/RH2 T6 GD11/EBIA15/RPD3/PMA15/PMCS2/RD3
N17 EBIA0/PMA0/RJ15 T7 GD16/EBID8/RPF5/SCL5/PMD8/RF5
N18 GD8/EBID11/PMD11/RJ14 T8 GD4/EBIA9/RPG1/PMA9/RG1
P1 DDRA10 T9 EBID3/RPE3/PMD3/RE3
P2 DDRCAS T10 ERXD2/RH6
P3 DDRA4 T11 ECOL/RH10
P4 RPF8/SCL3/RF8 T12 ETXD3/RH1
P15 GD13/EBIA18/RK4 T13 ETXD1/RJ9
P16 GD23/EBIA16/RK0 T14 No Connect
P17 EBIRDY2/AN37/RH11 T15 ETXCLK/RPD7/RD7
P18 AN35/RH3 T16 RPA14/SCL1/RA14
R1 DDRA0 T17 GD19/EBIA21/RK7
R2 DDRA3 T18 GD15/EBIA20/RK6
R3 DDRA9 U1 DDRA6
R4 VSS1V8 U2 DDRA8
R5 MCLR U3 DDRA13
R6 GD10/EBIA14/RPD2/PMA14/PMCS1/RD2 U4 DDRBA2
R7 VSS U5 GD7/EBIA12/RPD12/PMA12/RD12
R8 VSS U6 GD2/EBID15/RPD9/PMD15/RD9
R9 VDDIO U7 GD5/EBIA10/RPF1/PMA10/RF1
R10 VDDIO U8 ERXERR/RPF3/RF3
R11 VDDCORE U9 GD17/EBID9/RPF4/SDA5/PMD9/RF4
R12 VDDIO U10 ERXD1/RH5
R13 VDDIO U11 ECRS/RH12
R14 VDDIO U12 ERXD0/RH8
R15 GD14/EBIA19/RK5 U13 ERXCLK/EREFCLK/RJ11
R16 GD12/EBIA17/RK3 U14 EMDIO/RJ1
R17 EBIA3/AN11/PMA3/RK2 U15 EMDC/RPD11/RD11
R18 EBIA1/AN38/PMA1/RK1 U16 RPA15/SDA1/RA15
T1 DDRA5 U17 EBIRDY1/SDA2/RA3
T2 DDRA7 U18 SCL2/RA2
T3 DDRA12 V1 No Connect
T4 DDRA14 V2 DDRA11

A1 V1
N6
PIC32MZ1025DAB288
PIC32MZ1064DAA288
PIC32MZ2025DAA288
V18
PIC32MZ2064DAA288
PIC32MZ2064DAB288
A18
Polarity Indicator
Ball/Pin Ball/Pin
Number Number
V3 DDRA15 V11 ERXDV/ECRSDV/RH13
V4 VDDCORE V12 ERXD3/RH9
V5 RTCC/RPD0/RD0 V13 ETXD2/RH0
V6 SCK4/RD10 V14 ETXD0/RJ8
V7 GD6/EBIA11/RPF0/PMA11/RF0 V15 ETXERR/RJ0
V8 GD21/EBIA23/RH15 V16 ETXEN/RPD6/RD6
V9 GD3/EBIA8/RPG0/PMA8/RG0 V17 GD1/EBID14/PMD14/RA4
V10 EBID2/PMD2/RE2 V18 No Connect

Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 17
2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 39
3.0 CPU ............................................................................................................................................................................................ 45
4.0 Memory Organization ................................................................................................................................................................. 55
5.0 Flash Program Memory ............................................................................................................................................................ 105
6.0 Resets ...................................................................................................................................................................................... 115
7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................. 123
8.0 Oscillator Configuration ............................................................................................................................................................ 157
9.0 Prefetch Module ....................................................................................................................................................................... 173
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 177
11.0 Hi-Speed USB with On-The-Go (OTG) .................................................................................................................................... 201
12.0 I/O Ports ................................................................................................................................................................................... 251
13.0 Timer1 ...................................................................................................................................................................................... 279
14.0 Timer2/3, Timer4/5, Timer6/7, and Timer8/9............................................................................................................................ 283
15.0 Input Capture............................................................................................................................................................................ 289
16.0 Output Compare ....................................................................................................................................................................... 293
17.0 Deadman Timer (DMT) ............................................................................................................................................................ 299
18.0 Watchdog Timer (WDT) ........................................................................................................................................................... 307
19.0 Deep Sleep Watchdog Timer (DSWDT)................................................................................................................................... 311
20.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 313
21.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S) ....................................................................................................... 323
22.0 Serial Quad Interface (SQI) ...................................................................................................................................................... 333
23.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 361
24.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 369
25.0 Parallel Master Port (PMP)....................................................................................................................................................... 377
26.0 External Bus Interface (EBI) ..................................................................................................................................................... 391
27.0 Crypto Engine........................................................................................................................................................................... 399
28.0 Random Number Generator (RNG) ......................................................................................................................................... 421
29.0 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)......................................... 427
30.0 Controller Area Network (CAN) ................................................................................................................................................ 483
31.0 Ethernet Controller ................................................................................................................................................................... 521
32.0 Comparator .............................................................................................................................................................................. 565
33.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 569
34.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 573
35.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 577
36.0 Graphics LCD (GLCD) Controller ............................................................................................................................................. 583
37.0 2-D Graphics Processing Unit (GPU) ....................................................................................................................................... 603
38.0 DDR2 SDRAM Controller ......................................................................................................................................................... 605
39.0 Secure Digital Host Controller (SDHC) .................................................................................................................................... 641
40.0 Power-Saving Features ........................................................................................................................................................... 669
41.0 Special Features ...................................................................................................................................................................... 683
42.0 Instruction Set .......................................................................................................................................................................... 711
43.0 Development Support............................................................................................................................................................... 713
44.0 Electrical Characteristics .......................................................................................................................................................... 717
45.0 AC and DC Characteristics Graphs.......................................................................................................................................... 777
46.0 Packaging Information.............................................................................................................................................................. 785
Index ................................................................................................................................................................................................. 799

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Referenced Sources
This device data sheet is based on the following
individual sections of the PIC32 Family Reference
Manual. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note: To access the following documents, refer
to the Documentation > Reference
Manuals section of the Microchip PIC32
website: http://www.microchip.com/pic32.
Section 1. Introduction (DS60001127)

Section 7. Resets (DS60001118)
Section 8. Interrupt Controller (DS60001108)
Section 9. Watchdog, Deadman, and Power-up Timers (DS60001114)
Section 10. Power-Saving Features (DS60001130)
Section 12. I/O Ports (DS60001120)
Section 13. Parallel Master Port (PMP) (DS60001128)
Section 14. Timers (DS60001105)
Section 15. Input Capture (DS60001122)
Section 16. Output Compare (DS60001111)
Section 19. Comparator (DS60001110)
Section 20. Comparator Voltage Reference (CVREF) (DS60001109)
Section 21. Universal Asynchronous Receiver Transmitter (UART) (DS60001107)
Section 22. 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter
(ADC) (DS60001344)
Section 23. Serial Peripheral Interface (SPI) (DS60001106)
Section 24. Inter-Integrated Circuit (I2C) (DS60001116)
Section 29. Real-Time Clock and Calendar (RTCC) (DS60001125)
Section 31. Direct Memory Access (DMA) Controller (DS60001117)
Section 32. Configuration (DS60001124)
Section 33. Programming and Diagnostics (DS60001129)
Section 34. Controller Area Network (CAN) (DS60001154)
Section 35. Ethernet Controller (DS60001155)
Section 37. Charge Time Measurement Unit (CTMU) (DS60001167)
Section 38. High/Low Voltage Detect (HLVD) (DS60001408)
Section 41. Prefetch Module for Devices with L1 CPU Cache (DS60001183)
Section 42. Oscillators with Enhanced PLL (DS60001250)
Section 46. Serial Quad Interface (SQI) (DS60001244)
Section 47. External Bus Interface (EBI) (DS60001245)
Section 48. Memory Organization and Permissions (DS60001214)
Section 49. Crypto Engine (CE) and Random Number Generator (RNG) (DS60001246)
Section 50. CPU for Devices with MIPS32 microAptiv and M-Class Cores (DS60001192)
Section 51. High-Speed USB with On-The-Go (OTG) (DS60001326)
Section 52. Flash Program Memory with Support for Live Update (DS60001193)
Section 54. Graphics LCD (GLCD) Controller (DS60001379)
Section 55. DDR SDRAM Controller (DS60001321)
Section 57. Secure Digital Host Controller (SDHC) (DS60001334)

1.0 DEVICE OVERVIEW This data sheet contains device-specific information for
the PIC32MZ DA family of devices.
Note: This data sheet summarizes the features
of the PIC32MZ Graphics (DA) Family of Figure 1-1 illustrates a general block diagram of the
devices. It is not intended to be a core and peripheral modules in the PIC32MZ DA family
comprehensive reference source. To of devices.
complement the information in this data Table 1-1 through Table 1-24 list the pinout I/O
sheet, refer to the documents listed in the descriptions for the pins shown in the device pin tables
Documentation > Reference Manual (see Table 5 through Table 7).
section of the Microchip PIC32 web site
(www.microchip.com/pic32).
FIGURE 1-1: PIC32MZ DA FAMILY BLOCK DIAGRAM
OSC2/CLKO POSC/SOSC
OSC1/CLKI Oscillators Voltage , SS
VDDIOV
Regulator Power-up
FRC Timer MCLR
SOSC SOSC
Oscillator Oscillator Precision
Band Gap Oscillator
VBAT SPLL Reference Start-up Timer
Power
Switch UPLL
VDDIO MPLL USBCLK Power-on
LPRC Reset
INT0 SYSCLK
Oscillator DIVIDERS 6 PORTA
PBCLKx Brown-out
Timing Reset PORTB
DSWDT Generation
Deep Sleep PORTC
PORTD
RTCC
PORTE
DSCTRL PORTF
EVIC Deep Sleep PORTG
PORTH
EJTAG INT
PORTJ
MIPS32
Controller
CRYPTO
HS USB
Ethernet
DMAC
CAN1
CAN2
SQI
EBI
microAptiv Core PORTK

I-Cache D-Cache Peripheral Peripheral Peripheral
System Bus Bridge 6 Bridge 5 Bridge 4
SDHC
I1 I3 I2 T22 I11 T12 I9 T11 I4 T10 T23 I8 I7 I5 I6 T9 T8
T19 I14
System Bus
T15,
T1 T16,
T5 I10 T2 T3 T13 I12 T14 T20, T18 I13 T6 T7
T21
Peripheral Bridge 1 Peripheral Peripheral
Controller
Prefetch
Controller
Controller
Bridge 2 Bridge 3
Cache
SRAM2
SRAM1
Flash
DDR2
Flash
RNG
GPU
LCD
CFG
Timer1-9
PPS
128 I12 T17 I13 OC1-9
128
CVREF
PFM Flash IC1-9
Wrapper SPI1-6
WDT
Comparator
140-bit Wide I2C1-5 1-2
DMT
Dual Panel
Flash Memory 6 S&H
HLVD UART1-6 12-bit ADC
PMP CTMU
Note: Not all features are available on all devices. Refer to Table 1 through Table 4 for the list of features by device.

TABLE 1-1: ADC PINOUT I/O DESCRIPTIONS

Pin Number
Pin Pin Buffer
169-pin 176-pin 288-pin Description
Name Type Type
LFBGA LQFP LFBGA
Analog-to-Digital Converter
AN0 C12 169 D18 I Analog Analog Input Channels
AN1 A13 172 C17 I Analog
AN2 A12 175 B17 I Analog
AN3 B10 7 B16 I Analog
AN4 A9 10 A15 I Analog
AN5 C11 168 E18 I Analog
AN6 B13 171 C18 I Analog
AN9 B9 11 A14 I Analog
AN10 A8 14 C13 I Analog
AN11 H11 135 R17 I Analog
AN13 D5 31 D9 I Analog
AN14 E5 30 A9 I Analog
AN15 C7 24 B11 I Analog
AN16 F6 23 C11 I Analog
AN18 B3 43 B6 I Analog
AN20 D4 35 B8 I Analog
AN22 E9 158 J18 I Analog
AN23 C5 33 B9 I Analog
AN24 E11 160 H16 I Analog
AN25 E6 25 C10 I Analog
AN26 D6 26 B10 I Analog
AN28 C10 2 C15 I Analog
AN29 E10 159 J17 I Analog
AN30 B5 32 C9 I Analog
AN31 C6 27 A11 I Analog
AN32 F10 152 K16 I Analog
AN33 F11 157 J16 I Analog
AN35 J13 140 P18 I Analog
AN36 J12 139 N15 I Analog
AN37 K13 138 P17 I Analog
AN38 J11 136 R18 I Analog
AN39 A4 36 D8 I Analog
AN45 D11 167 E17 I Analog
AN46 D12 170 D17 I Analog
AN47 B12 173 E16 I Analog
AN48 F7 9 B15 I Analog
AN49 E7 12 C14 I Analog
Legend: CMOS = CMOS-compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = Transistor-transistor Logic input buffer PPS = Peripheral Pin Select

TABLE 1-2: OSCILLATOR PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Pin Name 169-pin 176-pin 288-pin Description
Type Type
LFBGA LQFP LFBGA
Oscillators
CLKI E12 164 G17 I ST/CMOS External clock source input. Always associated with OSC1 pin
function.
CLKO E13 163 G18 O Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC and
EC modes. Always associated with OSC2 pin function.
OSC1 E12 164 G17 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
OSC2 E13 163 G18 O Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. Optionally functions as CLKO in RC and
EC modes.
SOSCI C13 162 H17 I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
SOSCO D13 161 H18 O ST/CMOS 32.768 low-power oscillator crystal output.
REFCLKI1 PPS PPS PPS I Reference Clock Generator Inputs 1-4
REFCLKI3 PPS PPS PPS I
REFCLKI4 PPS PPS PPS I
REFCLKO1 PPS PPS PPS O Reference Clock Generator Outputs 1-4
REFCLKO3 PPS PPS PPS O
REFCLKO4 PPS PPS PPS O
TABLE 1-3: IC1 THROUGH IC9 PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
Input Capture
IC1 PPS PPS PPS I ST Input Capture Inputs 1-9
IC2 PPS PPS PPS I ST

TABLE 1-4: OC1 THROUGH OC9 PINOUT I/O DESCRIPTIONS

Pin Number
Pin Pin Buffer
Name Type Type
LFBGA LQFP LFBGA
Output Compare
OC1 PPS PPS PPS O Output Compare Outputs 1-9
OC2 PPS PPS PPS O
OC3 PPS PPS PPS O
OC4 PPS PPS PPS O
OC5 PPS PPS PPS O
OC6 PPS PPS PPS O
OC7 PPS PPS PPS O
OC8 PPS PPS PPS O
OC9 PPS PPS PPS O
OCFA PPS PPS PPS I ST Output Compare Fault A Input
OCFB PPS PPS PPS I ST Output Compare Fault B Input
TABLE 1-5: EXTERNAL INTERRUPTS PINOUT I/O DESCRIPTIONS

Pin Number
Pin Pin Buffer
Name Type Type
LFBGA LQFP LFBGA
External Interrupts
INT0 C3 42 A6 I ST External Interrupt 0
INT1 PPS PPS PPS I ST External Interrupt 1

TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS

Pin Number
Pin Pin Buffer
Name Type Type
LFBGA LQFP LFBGA
PORTA
RA0 D2 53 D4 I/O ST PORTA is a bidirectional I/O port
RA1 E11 160 H16 I/O ST
RA2 L12 129 U18 I/O ST
RA3 N12 128 U17 I/O ST
RA4 L11 127 V17 I/O ST
RA5 A11 174 B18 I/O ST
RA6 E4 54 E4 I/O ST
RA7 D1 55 F4 I/O ST
RA9 B11 1 A17 I/O ST
RA10 C10 2 C15 I/O ST
RA14 M11 126 T16 I/O ST
RA15 N11 125 U16 I/O ST
PORTB
RB0 C12 169 D18 I/O ST PORTB is a bidirectional I/O port
RB1 B9 11 A14 I/O ST
RB2 A13 172 C17 I/O ST
RB3 A10 8 A16 I/O ST
RB4 A12 175 B17 I/O ST
RB5 D11 167 E17 I/O ST
RB6 D7 13 B14 I/O ST
RB7 D12 170 D17 I/O ST
RB8 A9 10 A15 I/O ST
RB9 B12 173 E16 I/O ST
RB10 C11 168 E18 I/O ST
RB11 E7 12 C14 I/O ST
RB12 B13 171 C18 I/O ST
RB13 F7 9 B15 I/O ST
RB14 E10 175 J17 I/O ST
RB15 B10 7 B16 I/O ST
PORTC
RC1 B7 17 A12 I/O ST PORTC is a bidirectional I/O port
RC2 A8 14 C13 I/O ST
RC3 A7 15 B13 I/O ST
RC4 B8 16 A13 I/O ST
RC12 E12 164 G17 I/O ST
RC13 C13 162 H17 I ST
RC14 D13 161 H18 I ST
RC15 E13 163 G18 I/O ST

TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Pin Buffer
Name Type Type
LFBGA LQFP LFBGA
PORTD
RD0 H3 79 V5 I/O ST PORTD is a bidirectional I/O port
RD1 G1 73 M4 I/O ST
RD2 G2 74 R6 I/O ST
RD3 G3 75 T6 I/O ST
RD4 F1 70 K4 I/O ST
RD5 F2 71 L4 I/O ST
RD6 K11 121 V16 I/O ST
RD7 M10 120 T15 I/O ST
RD9 H1 76 U6 I/O ST
RD10 H2 77 V6 I/O ST
RD11 N10 119 U15 I/O ST
RD12 J1 80 U5 I/O ST
RD13 J2 81 N4 I/O ST
RD14 E9 158 J18 I/O ST
RD15 F11 157 J16 I/O ST
PORTE
RE0 C4 40 B7 I/O ST PORTE is a bidirectional I/O port
RE1 A4 36 D8 I/O ST
RE2 N3 99 V10 I/O ST
RE3 M3 98 T9 I/O ST
RE4 B3 43 B6 I/O ST
RE5 F3 17 K3 I/O ST
RE6 F6 23 C11 I/O ST
RE7 C7 24 B11 I/O ST
RE8 E6 25 C10 I/O ST
RE9 D6 26 B10 I/O ST
PORTF
RF0 L1 91 V7 I/O ST PORTF is a bidirectional I/O port
RF1 K3 90 U7 I/O ST
RF2 A3 41 A7 I/O ST
RF3 M1 93 U8 I/O ST
RF4 L3 44 U9 I/O ST
RF5 K2 89 T7 I/O ST
RF8 J3 82 P4 I/O ST
RF12 C6 27 A11 I/O ST
RF13 A6 28 A10 I/O ST

Pin Number
Pin Pin Buffer
Name Type Type
LFBGA LQFP LFBGA
PORTG
RG0 N2 96 V9 I/O ST PORTG is a bidirectional I/O port
RG1 M2 95 T8 I/O ST
RG6 E5 30 A9 I/O ST
RG7 D5 31 D9 I/O ST
RG8 B5 32 C9 I/O ST
RG9 C5 33 B9 I/O ST
RG12 E3 56 G4 I/O ST
RG13 E2 64 H4 I/O ST
RG14 E1 65 J4 I/O ST
RG15 A5 34 A8 I/O ST
PORTH
RH0 M8 110 V13 I/O ST PORTH is a bidirectional I/O port
RH1 M7 109 T12 I/O ST
RH2 H12 141 N16 I/O ST
RH3 J13 140 P18 I/O ST
RH4 D4 35 B8 I/O ST
RH5 M4 100 U10 I/O ST
RH6 N4 101 T10 I/O ST
RH7 J12 139 N15 I/O ST
RH8 N7 108 U12 I/O ST
RH9 N6 107 V12 I/O ST
RH10 M6 106 T11 I/O ST
RH11 K13 138 P17 I/O ST
RH12 N5 105 U11 I/O ST
RH13 M5 104 V11 I/O ST
RH14 C3 42 A6 I/O ST
RH15 L2 92 V8 I/O ST
PORTJ
RJ0 L10 118 V15 I/O ST PORTJ is a bidirectional I/O port
RJ1 K10 114 U14 I/O ST
RJ2 F10 152 K16 I/O ST
RJ3 E8 151 K17 I/O ST
RJ4 F13 150 K18 I/O ST
RJ5 F12 149 L18 I/O ST
RJ6 G11 148 L17 I/O ST
RJ7 G13 147 L16 I/O ST
RJ8 N9 113 V14 I/O ST
RJ9 M9 112 T13 I/O ST
RJ10 F8 146 M18 I/O ST
RJ11 N8 111 U13 I/O ST
RJ12 F9 145 M17 I/O ST
RJ13 G12 144 M16 I/O ST
RJ14 G10 143 N18 I/O ST
RJ15 H13 142 N17 I/O ST

Pin Number
Pin Pin Buffer
Name Type Type
LFBGA LQFP LFBGA
PORTK
RK0 K12 137 P16 I/O ST PORTK is a bidirectional I/O port
RK1 J11 136 R18 I/O ST
RK2 H11 135 R17 I/O ST
RK3 L13 134 R16 I/O ST
RK4 H10 133 P15 I/O ST
RK5 J10 132 R15 I/O ST
RK6 M13 131 T18 I/O ST
RK7 M12 130 T17 I/O ST
TABLE 1-7: TIMER1 THROUGH TIMER9 AND RTCC PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
Timer1 through Timer9
T1CK D13 161 H18 I ST Timer1 External Clock Input
T2CK PPS PPS PPS I ST Timer2 External Clock Input
Real-Time Clock and Calendar
RTCC(1) H3 79 V5 O Real-Time Clock Alarm/Seconds Output
Note 1: RTCC pin function in not available during VBAT operation.

TABLE 1-8: UART1 THROUGH UART6 PINOUT I/O DESCRIPTIONS

Pin Number
Pin Pin Buffer
Name Type Type
LFBGA LQFP LFBGA
Universal Asynchronous Receiver Transmitter 1
U1RX PPS PPS PPS I ST UART1 Receive
U1TX PPS PPS PPS O UART1 Transmit
U1CTS PPS PPS PPS I ST UART1 Clear to Send
U1RTS PPS PPS PPS O UART1 Ready to Send
U2CTS PPS PPS PPS I ST UART2 Clear To Send
U2RTS PPS PPS PPS O UART2 Ready To Send

TABLE 1-9: SPI1 THROUGH SPI 6 PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
Serial Peripheral Interface 1
SCK1 G1 73 M4 I/O ST SPI1 Synchronous Serial Clock Input/Output
SDI1 PPS PPS PPS I ST SPI1 Data In
SDO1 PPS PPS PPS O SPI1 Data Out
SS1 PPS PPS PPS I/O ST SPI1 Slave Synchronization Or Frame Pulse I/O
SCK2 E5 30 A9 I/O ST SPI2 Synchronous Serial Clock Input/output
SCK3 E10 159 J17 I/O ST SPI3 Synchronous Serial Clock Input/Output
SCK4 H2 77 V6 I/O ST SPI4 Synchronous Serial Clock Input/Output
SCK5 A6 28 A10 I/O ST SPI5 Synchronous Serial Clock Input/Output
SCK6 F11 157 J16 I/O ST SPI6 Synchronous Serial Clock Input/Output

TABLE 1-10: I2C1 THROUGH I2C5 PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
Inter-Integrated Circuit 1
SCL1 M11 126 T16 I/O ST I2C1 Synchronous Serial Clock Input/Output
SDA1 N11 125 U16 I/O ST I2C1 Synchronous Serial Data Input/Output
SCL2 L12 129 U18 I/O ST I2C2 Synchronous Serial Clock Input/Output
SDA2 N12 128 U17 I/O ST I2C2 Synchronous Serial Data Input/Output
SCL3 J3 82 P4 I/O ST I2C3 Synchronous Serial Clock Input/Output
SDA3 A3 42 A7 I/O ST I2C3 Synchronous Serial Data Input/Output
SCL4 B5 32 C9 I/O ST I2C4 Synchronous Serial Clock Input/Output
SDA4 D5 31 D9 I/O ST I2C4 Synchronous Serial Data Input/Output
SCL5 K2 89 T7 I/O ST I2C5 Synchronous Serial Clock Input/Output
SDA5 L3 97 U9 I/O ST I2C5 Synchronous Serial Data Input/Output
TABLE 1-11: COMPARATOR 1, COMPARATOR 2 AND CVREF PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
Comparator Voltage Reference
CVREF+ C10 2 C15 I Analog Comparator Voltage Reference (High) Input
CVREF- B11 1 A17 I Analog Comparator Voltage Reference (Low) Input
CVREFOUT C11 168 E18 O Analog Comparator Voltage Reference Output
Comparator 1
C1INA D12 170 D17 I Analog Comparator 1 Positive Input
C1INB A12 176 B17 I Analog Comparator 1 Selectable Negative Input
C1INC D5 31 D9 I Analog
C1IND E5 30 A9 I Analog
C1OUT PPS PPS PPS O Comparator 1 Output
Comparator 2
C2INA B10 7 B16 I Analog Comparator 2 Positive Input
C2INB A13 172 C17 I Analog Comparator 2 Selectable Negative Input
C2INC C5 33 B9 I Analog
C2IND B5 32 C9 I Analog
C2OUT PPS PPS PPS O Comparator 2 Output

TABLE 1-12: PMP PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
Parallel Master Port
Parallel Master Port Address bit 0 Input (Buffered Slave
PMA0 H13 142 N17 I/O TTL/ST
modes) and Output (Master modes)
Parallel Master Port Address bit 1 Input (Buffered Slave
PMA1 J11 136 R18 I/O TTL/ST
modes) and Output (Master modes)
PMA2 C5 33 B9 O Parallel Master Port Address (Demultiplexed Master modes)
PMA3 H11 135 R17 O
PMA4 J12 139 N15 O
PMA5 A11 174 B18 O
PMA6 F3 69 K3 O
PMA7 B12 173 E16 O
PMA8 N2 96 V9 O
PMA9 M2 95 T8 O
PMA10 K3 90 U7 O
PMA11 L1 91 V7 O
PMA12 J1 80 U5 O
PMA13 J2 81 N4 O
PMA14 G2 74 R6 O
PMA15 G3 75 T6 O
PMCS1 G2 74 R6 O Parallel Master Port Chip Select 1 Strobe
PMCS2 G3 75 T6 O Parallel Master Port Chip Select 2 Strobe
PMD0 C4 40 B7 I/O TTL/ST Parallel Master Port Data (Demultiplexed Master mode) or
PMD1 I/O TTL/ST Address/Data (Multiplexed Master modes)
A4 36 D8
PMD2 N3 99 V10 I/O TTL/ST
PMD3 M3 98 T9 I/O TTL/ST
PMD4 B3 43 B6 I/O TTL/ST
PMD5 B7 17 A12 I/O TTL/ST
PMD6 F6 23 C11 I/O TTL/ST
PMD7 C7 24 B11 I/O TTL/ST
PMD8 K2 89 T7 I/O TTL/ST
PMD9 L3 97 U9 I/O TTL/ST
PMD10 A9 10 A15 I/O TTL/ST
PMD11 G10 143 N18 I/O TTL/ST
PMD12 A8 14 C13 I/O TTL/ST
PMD13 G12 144 M16 I/O TTL/ST
PMD14 L11 127 V17 I/O TTL/ST
PMD15 H1 76 U6 I/O TTL/ST
Parallel Master Port Address Latch Enable Low Byte
PMALL H13 142 N17 O
(Multiplexed Master modes)
Parallel Master Port Address Latch Enable High Byte
PMALH J11 136 R18 O
(Multiplexed Master modes)
PMRD B8 16 A13 O Parallel Master Port Read Strobe
PMWR A7 15 B13 O Parallel Master Port Write Strobe

TABLE 1-13: EBI PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
External Bus Interface
EBIA0 H13 142 N17 O External Bus Interface Address Bus
EBIA1 J11 136 R18 O
EBIA2 C5 33 B9 O
EBIA3 H11 135 R17 O
EBIA4 J12 139 N15 O
EBIA5 A11 174 B18 O
EBIA6 F3 69 K3 O
EBIA7 B12 173 E16 O
EBIA8 N2 96 V9 O
EBIA9 M2 95 T8 O
EBIA10 K3 90 U7 O
EBIA11 L1 91 V7 O
EBIA12 J1 80 U5 O
EBIA13 J2 81 N4 O
EBIA14 G2 74 R6 O
EBIA15 G3 75 T6 O
EBIA16 K12 137 P16 O
EBIA17 L13 134 R16 O
EBIA18 H10 133 P15 O
EBIA19 J10 132 R15 O
EBIA20 M13 131 T18 O
EBIA21 M12 130 T17 O
EBIA22 E8 151 K17 O
EBIA23 L2 92 V8 O
EBID0 C4 40 B7 I/O ST External Bus Interface Data I/O Bus
EBID1 A4 40 D8 I/O ST
EBID2 N3 36 V10 I/O ST
EBID3 M3 99 T9 I/O ST
EBID4 B3 98 B6 I/O ST
EBID5 B7 43 A12 I/O ST
EBID6 F6 17 C11 I/O ST
EBID7 C7 23 B11 I/O ST
EBID8 K2 24 T7 I/O ST
EBID9 L3 89 U9 I/O ST
EBID10 A9 97 A15 I/O ST
EBID11 G10 10 N18 I/O ST
EBID12 A8 143 C13 I/O ST
EBID13 G12 14 M16 I/O ST
EBID14 L11 144 V17 I/O ST
EBID15 H1 127 U6 I/O ST

TABLE 1-13: EBI PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
EBIBS0 J11 145 M17 O

External Bus Interface Byte Select
EBIBS1 J12 146 M18 O
EBICS0 G10 150 K18 O
EBICS1 H12 149 L18 O
External Bus Interface Chip Select
EBIOE E12 16 A13 O External Bus Interface Output Enable
EBIRDY1 M10 128 U17 I ST
EBIRDY2 C5 138 P17 I ST External Bus Interface Ready Input
EBIRDY3 C4 152 K16 I ST
EBIRP F1 141 N16 O External Bus Interface Flash Reset Pin
EBIWE D11 15 B13 O External Bus Interface Write Enable
TABLE 1-14: USB PINOUT I/O DESCRIPTIONS

Pin Number
Pin Pin Buffer
Name Type Type
LFBGA LQFP LFBGA
Universal Serial Bus
VBUS A2 45 C5 I Analog USB bus power monitor
USB internal transceiver supply. If the USB module is not used,
VUSB3V3 B2 46, 47 C4, D5 P
this pin must be connected to VSS.
D+ C1 51 B4 I/O Analog USB D+
D- B1 50 A4 I/O Analog USB D-
USBID D3 52 C6 I ST USB OTG ID detect
TABLE 1-15: CAN1 AND CAN2 PINOUT I/O DESCRIPTIONS

Pin Number
Pin Pin Buffer
Name Type Type
LFBGA LQFP LFBGA
Controller Area Network
C1TX PPS PPS PPS O CAN1 Bus Transmit Pin
C1RX PPS PPS PPS I ST CAN1 Bus Receive Pin
C2TX PPS PPS PPS O CAN2 Bus Transmit Pin
C2RX PPS PPS PPS I ST CAN2 Bus Receive Pin

TABLE 1-16: ETHERNET MII I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
Ethernet
ERXD0 N7 108 U12 I ST Ethernet Receive Data 0
ERXD1 M4 100 U10 I ST Ethernet Receive Data 1
ERXD2 N4 101 T10 I ST Ethernet Receive Data 2
ERXD3 N6 107 V12 I ST Ethernet Receive Data 3
ERXERR M1 93 U8 I ST Ethernet Receive Error Input
ERXDV M5 104 V11 I ST Ethernet Receive Data Valid
ERXCLK N8 111 U13 I ST Ethernet Receive Clock
ETXD0 N9 113 V14 O Ethernet Transmit Data 0
ETXD1 M9 112 T13 O Ethernet Transmit Data 1
ETXD2 M8 110 V13 O Ethernet Transmit Data 2
ETXERR L10 118 V15 O Ethernet Transmit Error
ETXEN K11 121 V16 O Ethernet Transmit Enable
ETXCLK M10 120 T15 I ST Ethernet Transmit Clock
ECOL M6 106 T11 I ST Ethernet Collision Detect
ECRS N5 105 U11 I ST Ethernet Carrier Sense
EMDC N10 119 U15 O Ethernet Management Data Clock
EMDIO K10 114 U14 I/O Ethernet Management Data
TABLE 1-17: ETHERNET RMII PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
Ethernet MII Interface
ERXD0 N7 108 U12 I ST Ethernet Receive Data 0
ERXD1 M4 100 U10 I ST Ethernet Receive Data 1
ERXERR M1 93 U8 I ST Ethernet Receive Error Input
ETXD0 N9 113 V14 O Ethernet Transmit Data 0
ETXEN K11 121 V16 O Ethernet Transmit Enable
EMDC N10 119 U15 O Ethernet Management Data Clock
EMDIO K10 114 U14 I/O Ethernet Management Data
EREFCLK N8 111 U13 I ST Ethernet Reference Clock
ECRSDV M5 104 V11 I ST Ethernet Carrier Sense Data Valid

TABLE 1-18: SQI1 PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
Serial Quad Interface
SQICLK E4 54 E4 O Serial Quad Interface Clock
SQICS0 F1 70 K4 O Serial Quad Interface Chip Select 0
SQICS1 F2 71 L4 O Serial Quad Interface Chip Select 1
SQID0 E2 64 H4 I/O ST Serial Quad Interface Data 0
SQID1 E3 56 G4 I/O ST Serial Quad Interface Data 1
SQID2 E1 65 J4 I/O ST Serial Quad Interface Data 2
SQID3 D1 55 F4 I/O ST Serial Quad Interface Data 3
TABLE 1-19: SDHC PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
SDHC
SDCK E4 54 E4 O SD Serial Clock
SDCMD F1 70 K4 O SD Command/Response
SDDATA0 E2 64 H4 I/O ST SD Serial Data 0
SDDATA1 E3 56 G4 I/O ST SD Serial Data 1
SDDATA2 E1 65 J4 I/O ST SD Serial Data 2
SDDATA3 D1 55 F4 I/O ST SD Serial Data 3/Card Detect
SDCD D2 53 D4 I ST SD Mechanical Card Detect
SDWP H12 141 N16 I ST SD Write Protect
TABLE 1-20: CTMU PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
Charge Time Measurement Unit
CTED1 B9 11 A14 I ST CTMU External Edge Input 1
CTED2 C12 169 D18 I ST CTMU External Edge Input 2
CTPLS F7 9 B15 O CTMU Output Pulse

TABLE 1-21: GRAPHICS LCD (GLCD) CONTROLLER PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
GLCD Controller
GCLK G11 148 L17 O Graphics Display Pixel Clock
HSYNC F12 149 L18 O Graphics Display Horizontal Sync Pulse
VSYNC F13 150 K18 O Graphics Display Vertical Sync Pulse
GEN G13 147 L16 O Graphics Display Enable Output
GD0 G12 144 M16 O Graphics Controller Data Output
GD1 L11 127 V17 O
GD2 H1 76 U6 O
GD3 N2 96 V9 O
GD4 M2 95 T8 O
GD5 K3 90 U7 O
GD6 L1 91 V7 O
GD7 J1 80 U5 O
GD8 G10 143 N18 O
GD9 F9 145 M17 O
GD10 G2 74 R6 O
GD11 G3 75 T6 O
GD12 L13 134 R16 O
GD13 H10 133 P15 O
GD14 J10 132 R15 O
GD15 M13 131 T18 O
GD16 K2 89 T7 O
GD17 L3 97 U9 O
GD18 F8 146 M18 O
GD19 M12 130 T17 O
GD20 E8 151 K17 O
GD21 L2 92 V8 O
GD22 J2 81 N4 O
GD23 K12 137 P16 O

TABLE 1-22: DDR2 SDRAM CONTROLLER PINOUT I/O DESCRIPTIONS

Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
DDR2 SDRAM Controller
DDRCK DDR Internal DDR Internal K2 O SSTL Differential Clocks
DDRCK to the Package to the Package O SSTL
K1
DDRCKE L2 O SSTL Clock Enable
DDRCS0 N2 O SSTL Chip Select 0
DDRRAS M1 O SSTL Row Address Strobe
DDRCAS N2 O SSTL Column Address Strobe
DDRWE L1 O SSTL Write Enable Strobe
DDRLDM G3 O SSTL Lower Data Byte Mask
DDRUDM A3 O SSTL Upper Data Byte Mask
DDRODT N1 O SSTL On-Die Termination
DDRLDQS E1 I/O SSTL Lower Data Byte Qualifier Strobes (Differential)
DDRLDQS E2 I/O SSTL
DDRUDQS B2 I/O SSTL Upper Data Byte Qualifier Strobes (Differential)
DDRUDQS A2 I/O SSTL
DDRBA0 M2 O SSTL Bank Address Select 0
DDRBA1 M3 O SSTL Bank Address Select 1
DDRBA2 U4 O SSTL Bank Address Select 2
DDRA0 R1 O SSTL DDR2 Address Bus
DDRA1 L3 O SSTL
DDRA2 N3 O SSTL
DDRA3 R2 O SSTL
DDRA4 P3 O SSTL
DDRA5 T1 O SSTL
DDRA6 U1 O SSTL
DDRA7 T2 O SSTL
DDRA8 U2 O SSTL
DDRA9 R3 O SSTL
DDRA10 P1 O SSTL
DDRA11 V2 O SSTL
DDRA12 T3 O SSTL
DDRA13 U3 O SSTL
DDRA14 T4 O SSTL
DDRA15 V3 O SSTL
TTL = Transistor-transistor Logic input buffer PPS = Peripheral Pin Select SSTL = Stub Series Terminated Logic

TABLE 1-22: DDR2 SDRAM CONTROLLER PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
LFBGA LQFP LFBGA
DDRDQ0 DDR Internal DDR Internal F1 I/O SSTL DDR2 Data Bus
DDRDQ1 to the Package to the Package I/O SSTL
J3
DDRDQ2 H1 I/O SSTL
DDRDQ3 G1 I/O SSTL
DDRDQ4 G2 I/O SSTL
DDRDQ5 H2 I/O SSTL
DDRDQ6 H3 I/O SSTL
DDRDQ7 F2 I/O SSTL
DDRDQ8 C1 I/O SSTL DDR2 Data Bus
DDRDQ9 C3 I/O SSTL
DDRDQ10 D2 I/O SSTL
DDRDQ11 F3 I/O SSTL
DDRDQ12 E3 I/O SSTL
DDRDQ13 D1 I/O SSTL
DDRDQ14 B3 I/O SSTL
DDRDQ15 C2 I/O SSTL
TTL = Transistor-transistor Logic input buffer PPS = Peripheral Pin Select SSTL = Stub Series Terminated Logic

TABLE 1-23: POWER, GROUND, AND VOLTAGE REFERENCE PINOUT I/O

DESCRIPTIONS
Pin Name Pin Number Pin Buffer Description
Type Type
169-pin 176-pin 288-pin
LFBGA LQFP LFBGA
Power and Ground
AVDD D9 3, 4 F13, G13 P P Positive supply for analog modules. This pin must be
connected at all times.
AVSS C8, D8 5, 6 F12, G12 P P Ground reference for analog modules. This pin must be
connected at all times.
VDDIO B6, G9, 19, 38, 86, C16, D15, P Positive supply for peripheral logic and I/O pins. This pin
H9, J9, 102, 117, D16, E15, must be connected at all times.
K9, L6, 124, 155, F11, F15,
L7, L9 156, 165 G11, G15,
H11, H12,
H13, H15,
J10, J15,
K10, L11,
L12, M12,
M13, M15,
N12, N13,
R9, R10,
R12, R13,
R14
VDDCORE B4, C9, 18, 39, 84, D7, D14, P 1.8V positive supply for peripheral logic. This pin must be
L8, N1 116 R11, V4 connected at all times.
VSS C2, F5, 21, 22, 29, A5, B5, P Ground reference for logic, I/O pins, and USB. This pin
G5, G6, 37, 48, 49, C7, D10, must be connected at all times.
G7, G8, 83, 87, 94, D11, D12,
H7, H8, 103, 115, D13, F9,
J7, J8, K7, 122, 123, F10, G10,
K8 153, 154 H10, J11,
J12, J13,
K11, K12,
K13, K15,
L10, L13,
L15, M10,
M11, N10,
N11, R7,
R8
HLVDIN B12 173 E16 P Low-voltage detect pin.
VBAT D10 166 F16 P Positive supply for the battery backed section. It is
recommended to connect this pin to VDDIO if VBAT mode is
not used (i.e., not connected to the battery).
VDDR1V8 H5, H6, 57, 58, 59, H6, H7, P Positive supply for the DDR2 SDRAM memory.
J5, J6, K5, 60, 61, 62, H8, J6, J7,
K6 63, 67, 68, J8, K6,
(Note 2) 72, 78 K7, K8,
(Note 2) L6, L7, L8
(Note 2)
Note 1: The metal plane at the bottom of the device is internally tied to VSS1V8 and must be connected to 1.8V ground externally.

TABLE 1-23: POWER, GROUND, AND VOLTAGE REFERENCE PINOUT I/O
DESCRIPTIONS (CONTINUED)
Type Type
169-pin 176-pin 288-pin
LFBGA LQFP LFBGA
VSS1V8 G4, H4, See D3, F6, P Ground reference for DDR2 SDRAM memory.
J4, K4, L4, Note 1 F7, F8,
L5 G6, G7,
G8, G9,
H9, J9,
K9, L9,
M6, M7,
M8, M9,
N6, N7,
N8, N9,
R4
Voltage Reference
DDRVREF F4 66 J11 P 1.8V Voltage Reference to DDR2 SDRAM memory.
(Note 3) (Note 3)
VREF+ C10 2 C15 I Analog Analog Voltage Reference (High) Input
VREF- B11 1 A17 I Analog Analog Voltage Reference (Low) Input
Note 1: The metal plane at the bottom of the device is internally tied to VSS1V8 and must be connected to 1.8V ground externally.

TABLE 1-24: JTAG, TRACE, AND PROGRAMMING/DEBUGGING PINOUT I/O DESCRIPTIONS

Type Type
169-pin 176-pin 288-pin
LFBGA LQFP LFBGA
JTAG
TCK E11 160 H16 I ST JTAG Test Clock Input Pin
TDI A6 28 A10 I ST JTAG Test Data Input Pin
TDO C6 27 A11 O JTAG Test Data Output Pin
TMS D2 53 D4 I ST JTAG Test Mode Select Pin
Trace
TRCLK E4 54 E4 O Trace Clock
TRD0 E2 64 H4 O Trace Data bits 0-3
TRD1 E3 56 G4 O
TRD2 E1 65 J4 O
TRD3 D1 55 F4 O
Programming/Debugging
Data I/O pin for Programming/Debugging Communication
PGED1 C12 169 D18 I/O ST Channel 1
Clock input pin for Programming/Debugging Communication
PGEC1 B9 11 A14 I ST Channel 1
Data I/O pin for Programming/Debugging Communication
PGED2 D12 170 D17 I/O ST Channel 2
Clock input pin for Programming/Debugging Communication
PGEC2 D7 13 B14 I ST Channel 2
Master Clear (Reset) input. This pin is an active-low Reset to
MCLR K1 85 R5 I/P ST the device.

2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors
STARTED WITH 32-BIT The use of decoupling capacitors on power supply
MICROCONTROLLERS pins, such as VDDIO, VSS, AVDD and AVSS is
required. See Figure 2-1.
Consider the following criteria when using decoupling
of the PIC32MZ Graphics (DA) Family of
capacitors:
devices. It is not intended to be a
comprehensive reference source. To Value and type of capacitor: It is recommended
complement the information in this data that two parallel capacitors with a value of 0.1 F
sheet, refer to the documents listed in the (100 nF, 10-20V) and a value of 0.01 F be used.
Documentation > Reference Manual The 0.1 F capacitor should be a low Equivalent
section of the Microchip PIC32 web site Series Resistance (low-ESR) capacitor and have
(www.microchip.com/pic32). resonance frequency in the range of 20 MHz and
higher. Place both capacitors in close proximity and
2.1 Basic Connection Requirements consider implementing the pair of capacitances as
close to the power and ground pins as possible. It is
Getting started with the PIC32MZ DA family of 32-bit further recommended that ceramic capacitors be
Microcontrollers (MCUs) requires attention to a minimal used.
set of device pin connections before proceeding with Placement on the printed circuit board: The
development. The following is a list of pin names, which decoupling capacitors should be placed as close to
must always be connected: the pins as possible. It is recommended that the
All VDDIO, VDDCORE, and VSS pins (see capacitors be placed on the same side of the board
2.2 Decoupling Capacitors) as the device. If space is constricted, the capacitor
All AVDD and AVSS pins, even if the ADC module can be placed on another layer on the PCB using a
is not used (see 2.2 Decoupling Capacitors) via; however, ensure that the trace length from the
VBAT pin (see 2.2 Decoupling Capacitors) pin to the capacitor is within one-quarter inch
(6 mm) in length.
All VDDR1V8 and VSS1V8 pins (see
2.2 Decoupling Capacitors) Maximizing performance: On the board layout
from the power supply circuit, run the power and
MCLR pin (see 2.3 Master Clear (MCLR) Pin)
return traces to the decoupling capacitors first, and
PGECx/PGEDx pins, used for In-Circuit Serial then to the device pins. This ensures that the decou-
Programming (ICSP) and debugging purposes pling capacitors are first in the power chain. Equally
(see 2.4 ICSP Pins) important is to keep the trace length between the
OSC1 and OSC2 pins, when external oscillator capacitor and the power pins to a minimum thereby
source is used (see 2.7 External Oscillator reducing PCB track inductance.
Pins)
The following pin(s) may be required as well:
VREF+/VREF- pins, used when external voltage
reference for the ADC module is implemented.
Note: The AVDD and AVSS pins must be
connected, regardless of ADC use and
the ADC voltage reference source.

FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION
VDDIO(1,2) VDDCORE(1,2) VDDIO(1) AVDD(1) VUSB3V3(3)
L1(4)
0.01 F 0.01 F 0.01 F 0.01 F 0.01 F
0.1 F 0.1 F 0.1 F 0.1F 0.1 F
VSS(1) VSS(1) VSS(1) AVSS(1) VSS(1)
VBAT(1) VDDR1V8(1) VDDIO
R
0.01 F 0.01 F
R1
0.1 F 0.1 F MCLR
C
VSS(1) VSS1V8(1) VSS
Note 1: There are multiple power and ground pairs and minimum connection rules apply for each power source (i.e., VDDIO, VDDCORE,
AVDD, VUSB3V3, VBAT, VDDR1V8) and each ground source (VSS, AVSS, VSS1V8).
2: Voltage on VDDIO must always be greater than or equal to VDDCORE during power-up.
3: If the USB module is not used, this pin must be connected to VSS.
4: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDDIO and AVDD to improve ADC
noise rejection. The inductor impedance should be less than 1 and the inductor capacity greater than 10 mA.
Where: F C NV
f = -------------
- (i.e., ADC conversion rate/2)
2
1 -
f = -----------------------
2 LC
1 - 2
L = ---------------------
2f C
2.2.1 BULK CAPACITORS

The use of a bulk capacitor on VDDIO and VDDCORE
is recommended to improve power supply stability.
Typical values range from 4.7 F to 47 F. This
capacitor should be located as close to the device as
possible.

2.3 Master Clear (MCLR) Pin Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
The MCLR pin provides for two specific device will interfere with the programmer/debugger communi-
functions: cations to the device. If such discrete components are
Device Reset an application requirement, they should be removed
Device programming and debugging from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
Pulling The MCLR pin low generates a device Reset. timing requirements information in the respective
Figure 2-2 illustrates a typical MCLR circuit. During device Flash programming specification for information
device programming and debugging, the resistance on capacitive loading limits and pin input voltage high
and capacitance that can be added to the pin must (VIH) and input low (VIL) requirements.
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage Ensure that the Communication Channel Select (i.e.,
PGECx/PGEDx pins) programmed into the device
levels (VIH and VIL) and fast signal transitions must
matches the physical connections for the ICSP to
not be adversely affected. Therefore, specific values
MPLAB ICD 3 or MPLAB REAL ICE.
of R and C will need to be adjusted based on the
application and PCB requirements. For additional information on ICD 3 and REAL ICE
connection requirements, refer to the following
For example, as illustrated in Figure 2-2, it is documents that are available for download from the
recommended that the capacitor C be isolated from the Microchip web site, www.microchip.com:
MCLR pin during programming and debugging
Using MPLAB ICD 3 (poster) (DS50001765)
operations.
MPLAB ICD 3 Design Advisory (DS50001764)
Place the components illustrated in Figure 2-2 within MPLAB REAL ICE In-Circuit Debugger
one-quarter inch (6 mm) from the MCLR pin. Users Guide (DS50001616)
Using MPLAB REAL ICE Emulator (poster)
FIGURE 2-2: EXAMPLE OF MCLR PIN (DS50001749)
CONNECTIONS
VDDIO 2.5 JTAG
10k
The TMS, TDO, TDI and TCK pins are used for testing
R R1(1) and debugging according to the Joint Test Action
MCLR Group (JTAG) standard. It is recommended to keep the
0.1 F(2) 1 k
C trace length between the JTAG connector and the
PIC32 JTAG pins on the device as short as possible. If the
1 JTAG connector is expected to experience an ESD
5
4
PGECx(3) event, a series resistor is recommended, with the value
ICSP
2 PGEDx(3) in the range of a few tens of Ohms, not to exceed 100

VDDIO
3
VSS Ohms.
6
NC
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
Note 1: 470 R1 1 will limit any current flowing into
as they will interfere with the programmer or debugger
MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge communications to the device. If such discrete compo-
(ESD) or Electrical Overstress (EOS). Ensure that the nents are an application requirement, they should be
MCLR pin VIH and VIL specifications are met without removed from the circuit during programming and
interfering with the Debug/Programmer tools. debugging. Alternatively, refer to the AC/DC character-
2: The capacitor can be sized to prevent unintentional istics and timing requirements information in the
Resets from brief glitches or to extend the device
Reset period during POR.
respective device Flash programming specification for
3: No pull-ups or bypass capacitors are allowed on
information on capacitive loading limits and pin input
active debug/program PGECx/PGEDx pins. voltage high (VIH) and input low (VIL) requirements.
2.6 Trace
2.4 ICSP Pins
The trace pins can be connected to a hardware
The PGECx and PGEDx pins are used for In-Circuit
trace-enabled programmer to provide a compressed
Serial Programming (ICSP) and debugging pur-
real-time instruction trace. When used for trace, the
poses. It is recommended to keep the trace length
TRD3, TRD2, TRD1, TRD0 and TRCLK pins should
between the ICSP connector and the ICSP pins on
be dedicated for this use. The trace hardware
the device as short as possible. If the ICSP connec-
requires a 22 Ohm series resistor between the trace
tor is expected to experience an ESD event, a series
pins and the trace connector.
resistor is recommended, with the value in the range
of a few tens of Ohms, not to exceed 100 Ohms.

2.7 External Oscillator Pins TABLE 2-1: PERIPHERALS THAT
PRODUCE HS SIGNALS ON
Many MCUs have options for at least two oscillators: a
EXTERNAL PINS
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 Oscillator Maximum
High-Speed
Configuration for details). Peripheral Speed on
Signal Pins
The oscillator circuit should be placed on the same side Signal Pin
of the board as the device. Also, place the oscillator cir- DDR2 SDRAM DDRCLK, 200 MHz
cuit close to the respective oscillator pins, not exceed- Controller DDRCLK,
ing one-half inch (12 mm) distance between them. The DDRUDQS,
load capacitors should be placed next to the oscillator DDRUDQS,
itself, on the same side of the board. Use a grounded DDRLDQS,
copper pour around the oscillator circuit to isolate them DDRLDQS
from surrounding circuits. The grounded copper pour DDRAx, DDRDx 400 MHz
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground EBI EBIAx, 50 MHz
pour. Also, if using a two-sided board, avoid any traces EBIDx
on the other side of the board where the crystal is HS USB D+, D- 480 MHz
placed. A suggested layout is illustrated in Figure 2-3. SDHC SDCK, DATAx 50 MHz
SQI SQICLK, SQIDx 80 MHz
FIGURE 2-3: SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT Due to these high-speed signals, it is important to
consider several factors when designing a product that
uses these peripherals, as well as the PCB on which
Oscillator these components will be placed. Adhering to these
Secondary recommendations will help achieve the following goals:
Minimize the effects of electromagnetic interference
Guard Trace
to the proper operation of the product
Ensure signals arrive at their intended destination at
Guard Ring
the same time
Minimize crosstalk
Main Oscillator
Maintain signal integrity
Reduce system noise
Minimize ground bounce and power sag
2.8 Unused I/Os
Unused I/O pins should not be allowed to float as 2.9.1 SYSTEM DESIGN
inputs. They can be configured as outputs and driven
to a logic-low state. 2.9.1.1 Impedance Matching
Alternatively, inputs can be reserved by connecting the When selecting parts to place on high-speed buses,
pin to VSS through a 1k to 10k resistor and configuring particularly the SQI bus, if the impedance of the periph-
the pin as an input. eral device does not match the impedance of the pins
on the PIC32MZ DA device to which it is connected,
signal reflections could result, thereby degrading the
2.9 Designing for High-Speed quality of the signal.
Peripherals
If it is not possible to select a product that matches
The PIC32MZ DA family devices have peripherals that impedance, place a series resistor at the load to create
operate at frequencies much higher than typical for an the matching impedance, see Figure 2-4 for an
embedded environment. Table 2-1 lists the peripherals example.
that produce high-speed signals on their external pins:
FIGURE 2-4: SERIES RESISTOR
SQI
PIC32MZ Flash
50 Device

2.9.1.2 PCB Layout Recommendations 2.9.1.3 EMI/EMC/EFT (IEC 61000-4-4 and
The following list contains recommendations that will IEC 61000-4-2) Suppression
help ensure the PCB layout will promote the goals Considerations
previously listed. The use of LDO regulators is preferred to reduce
Component Placement overall system noise and provide a cleaner power
- Place bypass capacitors as close to their source. However, when utilizing switching Buck/Boost
component power and ground pins as possible, regulators as the local power source for PIC32MZ DA
and place them on the same side of the PCB devices, as well as in electrically noisy environments or
test conditions required for IEC 61000-4-4 and IEC
- Devices on the same bus that have larger setup
61000-4-2, users should evaluate the use of T-Filters
times should be placed closer to the PIC32MZ DA
(i.e., L-C-L) on the power pins, as shown in Figure 2-5.
device
In addition to a more stable power source, using
Power and Ground T-Filters can greatly reduce susceptibility to EMI
- Multi-layer PCBs will allow separate power and sources and events.
ground planes
Note: The EMI/EMC/EFT Suppression Circuit
- Each ground pin should be connected to the
represents only a few supply/ground
ground plane individually
pairs. However, the number of pairs on a
- Place bypass capacitor vias as close to the pad given package may vary. The number of
as possible (preferably inside the pad) T-Filters in the system depends on the fer-
- If power and ground planes are not used, rite chip current limitation and the number
maximize width for power and ground traces of supply/ground pairs. For example, with
- Use low-ESR, surface-mount bypass capacitors 600 mA current limitation per T-Filter for
Clocks and Oscillators the 288-LFBGA package, the system
should use three T-Filters.
- Place crystals as close as possible to the
PIC32MZ DA device OSC/SOSC pins
- Do not route high-speed signals near the clock or FIGURE 2-5: EMI/EMC/EFT
oscillator SUPPRESSION CIRCUIT
- Avoid via usage and branches in clock lines Ferrite Chip SMD
(SQICLK) DCR = 0.15(max)
600 ma ISAT
- Place termination resistors at the end of clock 300@ 100 MHz
lines PN#:
Traces VDD
0.01 F
Ferrite
- Higher-priority signals should have the shortest Chips
traces
0.1 F 0.1 F
- Follow vendor-recommended layout guidelines for
the DDR2 interface
VDD
VSS
VDD
VSS
- Match trace lengths for parallel buses (EBIAx, VSS

EBIDx, SQIDx) VSS VDD
VDD
- Avoid long run lengths on parallel traces to reduce
0.1 F
coupling 0.1 F VSS
PIC32MZ VDD
- Make the clock traces as straight as possible
VSS 0.1 F
- Use rounded turns rather than right-angle turns VSS
VDD VUSB3V3
- Have traces on different layers intersect on right 0.1 F
AVDD
AVSS
VDD
VSS
angles to minimize crosstalk 0.1 F
- Maximize the distance between traces, preferably

no less than three times the trace width
0.1 F 0.1 F Ferrite
- Power traces should be as short and as wide as Chips
possible VDD
- High-speed traces should be placed close to the 0.01 F

ground plane

2.10 Typical Application Connection
Example
An example of a typical application connection is
shown in Figure 2-6.
FIGURE 2-6: GRAPHICS APPLICATION
PIC32
GD<23:0>(1)
GCLK
GLCD I/F
GLCD HSYNC DISPLAY
VSYNC
System Bus GEN
RAM(2)
GPU
DDRCS0
DDRCK, DDRCK
DDR2 SDRAM Controller I/F
DDRUDQS, DDRUDQS
DDRLDQS, DDRLDQS
DDRA<13:0> DDR2 SDRAM(2.3)

DDR2 DDRDQ<15:0>
SDRAM
Controller
DDRCAS, DDRRAS, DDRWE
ODT
Note 1: R<7:0> = GD<7:0>; G<7:0> = GD<15:8>; B<7:0> = GD<23:16>.

2: Frame buffers are either in system RAM or in the DDR2 SDRAM (maximum resolution supported depends on
the memory size).
3: Stacked die version (169-pin LFBGA and 176-pin LQFP) supports 32 MB DDR2 SDRAM devices.

3.0 CPU MMU with Translation Lookaside Buffer (TLB)
mechanism:
Note 1: This data sheet summarizes the features - 32 dual-entry fully associative Joint TLB
of the PIC32MZ Graphics (DA) Family of - 4-entry fully associative Instruction TLB
devices. It is not intended to be a - 4-entry fully associative Data TLB
comprehensive reference source. To - 4 KB pages
complement the information in this data
Separate L1 data and instruction caches:
sheet, refer to Section 50. CPU for
Devices with MIPS32 microAptiv - 32 KB 4-way Instruction Cache (I-Cache)
and M-Class Cores (DS60001192), - 32 KB 4-way Data Cache (D-Cache)
which is available from the Autonomous Multiply/Divide Unit (MDU):
Documentation > Reference Manual - Maximum issue rate of one 32x32 multiply per
section of the Microchip PIC32 web site clock
(www.microchip.com/pic32). - Early-in iterative divide. Minimum 12 and
maximum 38 clock latency (dividend (rs) sign
2: MIPS32 microAptiv Microprocessor
extension-dependent)
Core resources are available at:
http://www.imgtec.com. Power Control:
- Minimum frequency: 0 MHz
The MIPS32 microAptiv Microprocessor Core is the - Low-Power mode (triggered by WAIT instruction)
heart of the PIC32MZ DA family device processor. The - Extensive use of local gated clocks
CPU fetches instructions, decodes each instruction,
EJTAG Debug and Instruction Trace:
fetches source operands, executes each instruction
and writes the results of instruction execution to the - Support for single stepping
proper destinations. - Virtual instruction and data address/value
breakpoints
3.1 Features - Hardware breakpoint supports both address
match and address range triggering.
PIC32MZ DA family processor core key features: - Eight instruction and four data complex
5-stage pipeline breakpoints
32-bit address and data paths iFlowtrace version 2.0 support:
MIPS32 Enhanced Architecture (Release 2): - Real-time instruction program counter
- Multiply-accumulate and multiply-subtract - Special events trace capability
instructions - Two performance counters with 34 user-
- Targeted multiply instruction selectable countable events
- Zero/One detect instructions - Disabled if the processor enters Debug mode
- WAIT instruction Four Watch registers:
- Conditional move instructions (MOVN, MOVZ) - Instruction, Data Read, Data Write options
- Vectored interrupts - Address match masking options
- Programmable exception vector base DSP ASE Extension:
- Atomic interrupt enable/disable - Native fractional format data type operations
- GPR shadow registers to minimize latency for
- Register Single Instruction Multiple Data
interrupt handlers
(SIMD) operations (add, subtract, multiply,
- Bit field manipulation instructions shift)
- Virtual memory support
- GPR-based shift
microMIPS compatible instruction set:
- Bit manipulation
- Improves code size density over MIPS32, while
maintaining MIPS32 performance. - Compare-Pick
- Supports all MIPS32 instructions (except branch- - DSP Control Access
likely instructions) - Indexed-Load
- Fifteen additional 32-bit instructions and 39 16-bit - Branch
instructions corresponding to commonly-used - Multiplication of complex operands
MIPS32 instructions
- Variable bit insertion and extraction
- Stack pointer implicit in instruction
- Virtual circular buffers
- MIPS32 assembly and ABI compatible
- Arithmetic saturation and overflow handling
- Zero-cycle overhead saturation and rounding
operations

A block diagram of the PIC32MZ DA family processor
core is shown in Figure 3-1.
FIGURE 3-1: PIC32MZ DA FAMILY MICROPROCESSOR CORE BLOCK DIAGRAM
microAptiv Microprocessor Core
I-Cache
Decode microMIPS I-Cache
PBCLK7
(MIPS32/microMIPS) Controller
GPR
(8 sets)
Execution Unit MMU
BIU System Bus
(TLB)
ALU/Shift Enhanced MDU
Atomic/LdSt (with DSP ASE)
DSP ASE
D-Cache
Controller
Debug/Profiling D-Cache
System System Break Points
Interface Coprocessor iFlowtrace
Fast Debug Channel
Interrupt Performance Counters Power
Interface Sampling
Secure Debug Management
2-wire Debug EJTAG

3.2 Architecture Overview Leading Zero/One detect unit for implementing the
CLZ and CLO instructions
The MIPS32 microAptiv Microprocessor core in
Arithmetic Logic Unit (ALU) for performing arithmetic
PIC32MZ DA family devices contains several logic
and bitwise logical operations
blocks working together in parallel, providing an
efficient high-performance computing engine. The Shifter and store aligner
following blocks are included with the core: DSP ALU and logic block for performing DSP
instructions, such as arithmetic/shift/compare opera-
Execution unit tions
General Purpose Register (GPR)
Multiply/Divide Unit (MDU) 3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
System control coprocessor (CP0) The processor core includes a Multiply/Divide Unit
Memory Management Unit (MMU) (MDU) that contains a separate pipeline for multiply
Instruction/Data cache controllers and divide operations, and DSP ASE multiply instruc-
Power Management tions. This pipeline operates in parallel with the Integer
Instructions and data caches Unit (IU) pipeline and does not stall when the IU pipe-
line stalls. This allows MDU operations to be partially
microMIPS support
masked by system stalls and/or other integer unit
Enhanced JTAG (EJTAG) controller instructions.
3.2.1 EXECUTION UNIT The high-performance MDU consists of a 32x32 booth
The processor core execution unit implements a load/ recoded multiplier, four pairs of result/accumulation
store architecture with single-cycle ALU operations registers (HI and LO), a divide state machine, and the
(logical, shift, add, subtract) and an autonomous necessary multiplexers and control logic. The first num-
multiply/divide unit. The core contains thirty-two 32-bit ber shown (32 of 32x32) represents the rs operand.
General Purpose Registers (GPRs) used for integer The second number (32 of 32x32) represents the rt
operations and address calculation. Seven additional operand.
register file shadow sets (containing thirty-two The MDU supports execution of one multiply or
registers) are added to minimize context switching multiply-accumulate operation every clock cycle.
overhead during interrupt/exception processing. The
register file consists of two read ports and one write Divide operations are implemented with a simple 1-bit-
port and is fully bypassed to minimize operation latency per-clock iterative algorithm. An early-in detection
in the pipeline. checks the sign extension of the dividend (rs) oper-
and. If rs is 8 bits wide, 23 iterations are skipped. For
The execution unit includes:
a 16-bit wide rs, 15 iterations are skipped and for a
32-bit adder used for calculating the data address 24-bit wide rs, 7 iterations are skipped. Any attempt to
Address unit for calculating the next instruction issue a subsequent MDU instruction while a divide is
address still active causes an IU pipeline stall until the divide
Logic for branch determination and branch target operation has completed.
address calculation
Table 3-1 lists the repeat rate (peak issue rate of cycles
Load aligner
until the operation can be reissued) and latency (num-
Trap condition comparator
ber of cycles until a result is available) for the processor
Bypass multiplexers used to avoid stalls when
core multiply and divide instructions. The approximate
executing instruction streams where data producing
latency and repeat rates are listed in terms of pipeline
instructions are followed closely by consumers of
clocks.
their results
TABLE 3-1: MIPS32 microAptiv MICROPROCESSOR CORE HIGH-PERFORMANCE INTEGER

MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate
MULT/MULTU, MADD/MADDU, 16 bits 5 1
MSUB/MSUBU (HI/LO destination) 32 bits 5 1
MUL (GPR destination) 16 bits 5 1
32 bits 5 1
DIV/DIVU 8 bits 12/14 12/14
16 bits 20/22 20/22
24 bits 28/30 28/30
32 bits 36/38 36/38

The MIPS architecture defines that the result of a Table 3-2 lists the latencies and repeat rates for the
multiply or divide operation be placed in one of four DSP multiply and dot-product operations. The approxi-
pairs of HI and LO registers. Using the Move-From-HI mate latencies and repeat rates are listed in terms of
(MFHI) and Move-From-LO (MFLO) instructions, these pipeline clocks.
values can be transferred to the General Purpose
Register file. TABLE 3-2: DSP-RELATED LATENCIES
In addition to the HI/LO targeted operations, the AND REPEAT RATES
MIPS32 architecture also defines a multiply instruc- Repeat
tion, MUL, which places the least significant results in Op code Latency
Rate
the primary register file instead of the HI/LO register
pair. By avoiding the explicit MFLO instruction Multiply and dot-product without 5 1
required when using the LO register, and by support- saturation after accumulation
ing multiple destination registers, the throughput of Multiply and dot-product with 5 1
multiply-intensive operations is increased. saturation after accumulation
Two other instructions, Multiply-Add (MADD) and Multiply without accumulation 5 1
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations. 3.2.3 SYSTEM CONTROL
The MADD instruction multiplies two numbers and then COPROCESSOR (CP0)
adds the product to the current contents of the HI and
In the MIPS architecture, CP0 is responsible for the
LO registers. Similarly, the MSUB instruction multiplies
virtual-to-physical address translation and cache proto-
two operands and then subtracts the product from the
cols, the exception control system, the processors
HI and LO registers. The MADD and MSUB operations
diagnostics capability, the operating modes (Kernel,
are commonly used in DSP algorithms.
User and Debug) and whether interrupts are enabled or
The MDU also implements various shift instructions disabled. Configuration information, such as cache
operating on the HI/LO register and multiply instruc- size and set associativity, and the presence of options
tions as defined in the DSP ASE. The MDU supports all like microMIPS, is also available by accessing the CP0
of the data types required for this purpose and includes registers, listed in Table 3-3.
three extra HI/LO registers as defined by the ASE.
TABLE 3-3: COPROCESSOR 0 REGISTERS

Register Register
Function
Number Name
0 Index Index into the TLB array (microAptiv MPU only).
1 Random Randomly generated index into the TLB array (microAptiv MPU only).
2 EntryLo0 Low-order portion of the TLB entry for even-numbered virtual pages (microAptiv MPU
only).
3 EntryLo1 Low-order portion of the TLB entry for odd-numbered virtual pages (microAptiv MPU
only).
4 Context/ Pointer to the page table entry in memory (microAptiv MPU only).
UserLocal User information that can be written by privileged software and read via the RDHWR
instruction.
5 PageMask/ PageMask controls the variable page sizes in TLB entries. PageGrain enables support
PageGrain of 1 KB pages in the TLB (microAptiv MPU only).
6 Wired Controls the number of fixed (i.e., wired) TLB entries (microAptiv MPU only).
7 HWREna Enables access via the RDHWR instruction to selected hardware registers in
Non-privileged mode.
8 BadVAddr Reports the address for the most recent address-related exception.
9 Count Processor cycle count.
10 EntryHi High-order portion of the TLB entry (microAptiv MPU only).
11 Compare Core timer interrupt control.

TABLE 3-3: COPROCESSOR 0 REGISTERS (CONTINUED)
Register Register
Function
Number Name
12 Status Processor status and control.
IntCtl Interrupt control of vector spacing.
SRSCtl Shadow register set control.
SRSMap Shadow register mapping control.
View_IPL Allows the Priority Level to be read/written without
extracting or inserting that bit from/to the Status register.
SRSMAP2 Contains two 4-bit fields that provide the mapping from a vector number to the shadow
set number to use when servicing such an interrupt.
13 Cause Describes the cause of the last exception.
NestedExc Contains the error and exception level status bit values that existed prior to the current
exception.
View_RIPL Enables read access to the RIPL bit that is available in the Cause register.
14 EPC Program counter at last exception.
NestedEPC Contains the exception program counter that existed prior to the current exception.
15 PRID Processor identification and revision
Ebase Exception base address of exception vectors.
CDMMBase Common device memory map base.
16 Config Configuration register.
Config1 Configuration register 1.
17 LLAddr Load link address (microAptiv MPU only).
18 WatchLo Low-order watchpoint address (microAptiv MPU only).
19 WatchHi High-order watchpoint address (microAptiv MPU only).
20-22 Reserved Reserved in the PIC32 core.
23 Debug EJTAG debug register.
TraceControl EJTAG trace control.
TraceControl2 EJTAG trace control 2.
UserTraceData1 EJTAG user trace data 1 register.
TraceBPC EJTAG trace breakpoint register.
Debug2 Debug control/exception status 1.
24 DEPC Program counter at last debug exception.
UserTraceData2 EJTAG user trace data 2 register.
25 PerfCtl0 Performance counter 0 control.
PerfCnt0 Performance counter 0.
PerfCtl1 Performance counter 1 control.
PerfCnt1 Performance counter 1.
26 ErrCtl Software test enable of way-select and data RAM arrays for I-Cache and D-Cache
(microAptiv MPU only).
27 Reserved Reserved in the PIC32 core.
28 TagLo/DataLo Low-order portion of cache tag interface (microAptiv MPU only).

3.3 Power Management In addition to I-Cache locking, the processor core also
supports a D-Cache locking mechanism identical to the
The processor core offers a number of power manage- I-Cache. Critical data segments are locked into the
ment features, including low-power design, active power cache on a per-line basis. The locked contents can be
management and power-down modes of operation. The updated on a store hit, but cannot be selected for
core is a static design that supports slowing or halting replacement on a cache miss.
the clocks, which reduces system power consumption
during Idle periods. The D-Cache locking function is always available on
all D-Cache entries. Entries can then be marked as
3.3.1 INSTRUCTION-CONTROLLED locked or unlocked on a per-entry basis using the
POWER MANAGEMENT CACHE instruction.
The mechanism for invoking Power-Down mode is 3.4.3 ATTRIBUTES

through execution of the WAIT instruction. For more The processor core I-Cache and D-Cache attributes
information on power management, see Section 40.0 are listed in the Configuration registers (see
Power-Saving Features. Register 3-1 through Register 3-4).
3.3.2 LOCAL CLOCK GATING
3.5 EJTAG Debug Support
The majority of the power consumed by the processor
core is in the clock tree and clocking registers. The The processor core provides for an Enhanced JTAG
PIC32MZ family makes extensive use of local gated- (EJTAG) interface for use in the software debug of
clocks to reduce this dynamic power consumption. application and kernel code. In addition to standard
User mode and Kernel modes of operation, the proces-
sor core provides a Debug mode that is entered after a
3.4 L1 Instruction and Data Caches
debug exception (derived from a hardware breakpoint,
3.4.1 INSTRUCTION CACHE (I-CACHE) single-step exception, etc.) is taken and continues until
a Debug Exception Return (DERET) instruction is
The I-Cache is an on-core memory block of 32 Kbytes.
executed. During this time, the processor executes the
Because the I-Cache is virtually indexed, the virtual-to-
debug exception handler routine.
physical address translation occurs in parallel with the
cache access rather than having to wait for the physical The EJTAG interface operates through the Test Access
address translation. The tag holds 23 bits of physical Port (TAP), a serial communication port used for trans-
address, a valid bit, and a lock bit. The LRU replace- ferring test data in and out of the core. In addition to the
ment bits are stored in a separate array. standard JTAG instructions, special instructions
defined in the EJTAG specification specify which
The I-Cache block also contains and manages the
registers are selected and how they are used.
instruction line fill buffer. Besides accumulating data to
be written to the cache, instruction fetches that refer- 3.6 MIPS DSP ASE Extension
ence data in the line fill buffer are serviced either by a
bypass of that data, or data coming from the external The MIPS DSP Application-Specific Extension
interface. The I-Cache control logic controls the bypass Revision 2 is an extension to the MIPS32 architecture.
function. This extension comprises new integer instructions and
states that include new HI/LO accumulator register
The processor core supports I-Cache locking. Cache
pairs and a DSP control register. This extension is
locking allows critical code or data segments to be
crucial in a wide range of DSP, multimedia, and DSP-
locked into the cache on a per-line basis, enabling the
like algorithms covering Audio and Video processing
system programmer to maximize the efficiency of the
applications. The extension supports native fractional
system cache.
format data type operations, register Single Instruction
The cache locking function is always available on all Multiple Data (SIMD) operations, such as add,
I-Cache entries. Entries can then be marked as subtract, multiply, and shift. In addition, the extension
locked or unlocked on a per entry basis using the includes the following features that are essential in
CACHE instruction. making DSP algorithms computationally efficient:
3.4.2 DATA CACHE (D-CACHE) Support for multiplication of complex operands

Variable bit insertion and extraction
The D-Cache is an on-core memory block of
32 Kbytes. This virtually indexed, physically tagged Implementation and use of virtual circular buffers
cache is protected. Because the D-Cache is virtually Arithmetic saturation and overflow handling
indexed, the virtual-to-physical address translation support
occurs in parallel with the cache access. The tag holds Zero cycle overhead saturation and rounding
23 bits of physical address, a valid bit, and a lock bit. operations
There is an additional array holding dirty bits and LRU
replacement algorithm bits for each set of the cache.

3.7 microAptiv Core Configuration
Register 3-1 through Register 3-4 show the default
configuration of the microAptiv core, which is included
on PIC32MZ DA family devices.
REGISTER 3-1: CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-1 U-0 U-0 U-0 U-0 U-0 U-0 R-0
31:24
ISP
R-0 R-0 R-1 R-0 U-0 R-1 R-0 R-0
23:16
DSP UDI SB MDU MM<1:0> BM
R-0 R-0 R-0 R-0 R-0 R-1 R-0 R-0
15:8
BE AT<1:0> AR<2:0> MT<2:1>
R-1 U-0 U-0 U-0 U-0 R/W-0 R/W-1 R/W-0
7:0
MT<0> K0<2:0>
Legend: r = Reserved bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
bit 31 Reserved: This bit is hardwired to 1 to indicate the presence of the Config1 register.
bit 30-25 Unimplemented: Read as 0
bit 24 ISP: Instruction Scratch Pad RAM bit
0 = Instruction Scratch Pad RAM is not implemented
bit 23 DSP: Data Scratch Pad RAM bit
0 = Data Scratch Pad RAM is not implemented
bit 22 UDI: User-defined bit
0 = CorExtend User-Defined Instructions are not implemented
bit 21 SB: SimpleBE bit
1 = Only simple byte enables are allowed on the internal bus interface
bit 20 MDU: Multiply/Divide Unit bit
0 = Fast, high-performance MDU
bit 19 Unimplemented: Read as 0
bit 18-17 MM<1:0>: Merge Mode bits
10 = Merging is allowed
bit 16 BM: Burst Mode bit
0 = Burst order is sequential
bit 15 BE: Endian Mode bit
0 = Little-endian
bit 14-13 AT<1:0>: Architecture Type bits
00 = MIPS32
bit 12-10 AR<2:0>: Architecture Revision Level bits
001 = MIPS32 Release 2
bit 9-7 MT<2:0>: MMU Type bits
001 = microAptiv MPU Microprocessor core uses a TLB-based MMU
bit 2-0 K0<2:0>: Kseg0 Coherency Algorithm bits
010 = Uncached

REGISTER 3-2: CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-1 R-0 R-1 R-1 R-1 R-1 R-1 R-0
31:24
MMU Size<5:0> IS<2>
R-1 R-1 R-0 R-1 R-1 R-0 R-1 R-1
23:16
IS<1:0> IL<2:0> IA<2:0>
R-0 R-1 R-1 R-0 R-1 R-1 R-0 R-1
15:8
DS<2:0> DL<2:0> DA<2:1>
R-1 U-0 U-0 R-1 R-0 R-0 R-1 R-0
7:0
DA<0> PC WR CA EP FP

bit 31 Reserved: This bit is hardwired to a 1 to indicate the presence of the Config2 register.
bit 30-25 MMU Size<5:0>: Contains the number of TLB entries minus 1
011111 = 32 TLB entries
bit 24-22 IS<2:0>: Instruction Cache Sets bits
011 = Contains 512 instruction cache sets per way
bit 21-19 IL<2:0>: Instruction-Cache Line bits
011 = Contains instruction cache line size of 16 bytes
bit 18-16 IA<2:0: Instruction-Cache Associativity bits
011 = Contains 4-way instruction cache associativity
bit 15-13 DS<2:0>: Data-Cache Sets bits
011 = Contains 512 data cache sets per way
bit 12-10 DL<2:0>: Data-Cache Line bits
011 = Contains data cache line size of 16 bytes
bit 9-7 DA<2:0>: Data-Cache Associativity bits
011 = Contains the 4-way set associativity for the data cache
bit 4 PC: Performance Counter bit
1 = The processor core contains Performance Counters
bit 3 WR: Watch Register Presence bit
1 = Four Watch registers are present
bit 2 CA: Code Compression Implemented bit
0 = No MIPS16e present
bit 1 EP: EJTAG Present bit
1 = Core implements EJTAG
bit 0 FP: Floating Point Unit bit
0 = Floating Point Unit is not implemented


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 R-0 R-1 R-0 R-0 R-0 R-1 R/W-y
23:16
IPLW<1:0> MMAR<2:0> MCU ISAONEXC(1)
R-y R-y R-1 R-1 R-1 R-1 U-0 R-1
15:8
ISA<1:0>(1) ULRI RXI DSP2P DSPP ITL
U-0 R-1 R-1 R-0 R-1 U-0 U-0 R-1
7:0
VEIC VINT SP CDMM TL
Legend: r = Reserved bit y = Value set from Configuration bits on POR

bit 31 Reserved: This bit is hardwired as 1 to indicate the presence of the Config4 register
bit 22-21 IPLW<1:0>: Width of the Status IPL and Cause RIPL bits
01 = IPL and RIPL bits are 8-bits in width
bit 20-18 MMAR<2:0>: microMIPS Architecture Revision Level bits
000 = Release 1
bit 17 MCU: MIPS MCU ASE Implemented bit
1 = MCU ASE is implemented
bit 16 ISAONEXC: ISA on Exception bit(1)
1 = microMIPS is used on entrance to an exception vector
0 = MIPS32 ISA is used on entrance to an exception vector
bit 15-14 ISA<1:0>: Instruction Set Availability bits(1)
11 = Both MIPS32 and microMIPS are implemented; microMIPS is used when coming out of reset
10 = Both MIPS32 and microMIPS are implemented; MIPS32 ISA used when coming out of reset
bit 13 ULRI: UserLocal Register Implemented bit
1 = UserLocal Coprocessor 0 register is implemented
bit 12 RXI: RIE and XIE Implemented in PageGrain bit
1 = RIE and XIE bits are implemented
bit 11 DSP2P: MIPS DSP ASE Revision 2 Presence bit
1 = DSP Revision 2 is present
bit 10 DSPP: MIPS DSP ASE Presence bit
1 = DSP is present
bit 8 ITL: Indicates that iFlowtrace hardware is present
1 = The iFlowtrace is implemented in the core
bit 6 VEIC: External Vector Interrupt Controller bit
1 = Support for an external interrupt controller is implemented.
bit 5 VINT: Vector Interrupt bit
1 = Vector interrupts are implemented
bit 4 SP: Small Page bit
0 = 4 KB page size
bit 3 CDMM: Common Device Memory Map bit
1 = CDMM is implemented
bit 0 TL: Trace Logic bit
0 = Trace logic is not implemented (this is old trace logic, which is replaced by iFlowtrace (ITL bit))
Note 1: These bits are set based on the value of the BOOTISA Configuration bit (DEVCFG0<6>).


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-1
7:0
NF
Legend: r = Reserved

bit 0 NF: Nested Fault bit
1 = Nested Fault feature is implemented

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
WII
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:
bit 31 WII: Wait IE Ignore bit

1 = Indicates that this processor will allow an interrupt to unblock a WAIT instruction

4.0 MEMORY ORGANIZATION 4.1 Memory Layout
Note: This data sheet summarizes the features PIC32MZ DA microcontrollers implement two address
of the PIC32MZ Graphics (DA) Family of schemes: virtual and physical. All hardware
devices. It is not intended to be a resources, such as program memory, data memory
comprehensive reference source.For and peripherals, are located at their respective
detailed information, refer to Section 48. physical addresses. Virtual addresses are exclusively
Memory Organization and used by the CPU to fetch and execute instructions as
Permissions (DS60001214), which is well as access peripherals. Physical addresses are
available from the Documentation > used by bus master peripherals, such as DMA and
Reference Manual section of the the Flash controller, that access memory
Microchip PIC32 web site independently of the CPU.
(www.microchip.com/pic32). The main memory maps for the PIC32MZ DA devices
are illustrated in Figure 4-1. Figure 4-2 provides
PIC32MZ DA microcontrollers provide 4 GB of unified memory map information for Boot Flash and boot
virtual memory address space. All memory regions, alias. Table 4-1 provides memory map information for
including program, data memory, SFRs and Program Flash, RAM, and DDR2 SDRAM. Table 4-2
Configuration registers, reside in this address space provides memory map information for Special
at their respective unique addresses. The program Function Registers (SFRs).
and data memories can be optionally partitioned into
user and kernel memories. In addition, PIC32MZ DA
devices allow execution from data memory.
Key features include:
32-bit native data width
Separate User (KUSEG) and Kernel (KSEG0/
KSEG1/KSEG2/KSEG3) mode address space
Separate Boot Flash memory for protected code
Robust bus exception handling to intercept
runaway code
Cacheable (KSEG0/KSEG2) and non-cacheable
(KSEG1/KSEG3) address regions
Read-Write permission access to predefined
memory regions

FIGURE 4-1: PIC32MZ DA FAMILY MEMORY MAP
Virtual Physical
Memory Map(1) Memory Map(1)
0xFFFFFFFF 0xFFFFFFFF
Reserved
(not cacheable)
0xF4000000
0xF3FFFFFF External Memory via
KSEG3(3)
0xF0000000 SQI
Reserved Reserved
0xE4000000
0xE3FFFFFF External Memory via
0xE0000000 EBI
Reserved
0xD4000000 0x34000000
0xD3FFFFFF External Memory via (cacheable) 0x33FFFFFF
KSEG2(3)
SQI External Memory via

0xD0000000
SQI
0x30000000
Reserved
0xC4000000
Reserved
0xC3FFFFFF External Memory via 0x24000000
0xC0000000 EBI 0x23FFFFFF
External Memory via
Reserved EBI
0xCFC74000 0x20000000
0xBFC73FFF Boot Flash
Reserved
0xCFC00000 (see Figure 4-2) 0x1FC74000
0x1FC73FFF
Reserved Boot Flash
0xBF900000
(see Figure 4-2)
0xBF8FFFFF SFRs 0x1FC00000
0xBF800000 (see Table 4-2)
(not cacheable)
Reserved
0x1F900000
Reserved
KSEG1
0x1F8FFFFF
SFRs
Program Flash (see Table 4-2)
0xBD000000 (see Table 4-1) 0x1F800000
Reserved
Reserved
DDR2 SDRAM(4)
0xA8000000 (see Table 4-1)
Reserved Program Flash

(see Table 4-1)
RAM(2)
0xA0000000 (see Table 4-1) 0x1D000000
Reserved Reserved
0x9FC74000
0x9FC73FFF Boot Flash
0x9FC00000 (see Figure 4-2)
DDR2 SDRAM(4)
Reserved (see Table 4-1)
Program Flash 0x08000000

(cacheable)
KSEG0
0x9D000000 (see Table 4-1)

Reserved
Reserved
DDR2 SDRAM(4)
(see Table 4-1) RAM(2)
0x88000000
(see Table 4-1)
Reserved
0x00000000
RAM(2)
0x80000000 (see Table 4-1)
Reserved
0x00000000
Note 1: Memory areas are not shown to scale.

2: RAM memory is divided into two banks. Refer to Table 4-1 for additional information.
3: The MMU must be enabled and the TLB must be set up to access this segment.
4: This region is Reserved in devices without the DDR2 option.

TABLE 4-1: ADDRESS MAPPING TABLE
Region End Region End Region End
Memory Size
Address (KSEG1) Address (KSEG0) Address (Physical)
2 MB 0xBD1FFFFF 0x9D1FFFFF 0x1D1FFFFF
Program Flash
1 MB 0xBD0FFFFF 0x9D0FFFFF 0x1D0FFFFF
EXT(1) 0xAFFFFFFF 0x8FFFFFFF 0x0FFFFFFF
(5)
DDR2 SDRAM 32 MB 0xA9FFFFFF 0x89FFFFFF 0x09FFFFFF
(2) Reserved Reserved Reserved
(3)
640 KB 0xA009FFFF 0x8009FFFF 0x0009FFFF
RAM
256 KB(4) 0xA003FFFF 0x8003FFFF 0x0003FFFF
Note 1: External DDR2 SDRAM can be up to 128 MB, EXTDDRSIZE<3:0> bits (DEVCFG3<19:16>) should be
set, and the region end address should be scaled accordingly.
2: Devices without the DDR2 option.
3: Devices with 640 KB RAM contain SRAM Bank 1 (256 KB) and SRAM Bank 2 (384 KB).
4: Devices with 256 KB RAM contain SRAM Bank 1 (128 KB) and SRAM Bank 2 (128 KB).
5: Refer to 4.2 DDR2 SDRAM for DDR2 SDRAM features, which are applicable to devices with internal
DDR2 SDRAM.

FIGURE 4-2: BOOT AND ALIAS TABLE 4-2: SFR MEMORY MAP
MEMORY MAP Virtual Address
Peripheral Offset
Physical Memory Map(1) 0x1FC74000 Base
Start
0x1FC70000 System Bus(1) 0xBF8F0000 0x0000

Sequence/Configuration Space(3)
0x1FC6FF00 SDHC 0xC000
GPU 0xB000
Boot Flash 2
GLCD 0xA000
0x1FC60000
DDRPHY 0x9100
Reserved 0x1FC54020
Serial Number(4) 0x1FC54000 DDRC 0x8000
RNG 0xBF8E0000 0x6000
Sequence/Configuration Space(3)
0x1FC50000 Crypto 0x5000
0x1FC4FF00
USB 0x3000
Boot Flash 1 SQI1 0x2000
0x1FC40000 EBI 0x1000
Prefetch 0x0000
Reserved
0x1FC34000 DSCTRL 0x0200
0xBF8C0000
RTCC 0x0000
(5) 0x1FC30000 USBCR
Unused Configuration Space 0x4000
0x1FC2FF00
Ethernet 0xBF880000 0x2000
Upper Boot Alias CAN1 and CAN2 0x0000
0x1FC20000
PORTA-PORTK 0xBF860000 0x0000
Reserved CTMU 0xC200
0x1FC14000 Comparator 1, 2 0xC000
ADC 0xB000
0x1FC10000 0xBF840000
Configuration Space(2,3) OC1-OC9 0x4000
0x1FC0FF00
IC1-IC9 0x2000
Lower Boot Alias Timer1-Timer9 0x0000
0x1FC00000
PMP 0xE000
Note 1: Memory areas are not shown to scale. UART1-UART6 0x2000
0xBF820000
2: Memory locations 0x1FC0FF40 SPI1-SPI6 0x1000
through 0x1FC0FFFC are used to
initialize Configuration registers (see I2C1-I2C5 0x0000
Section 41.0 Special Features). DMA 0x1000
3: Refer toSection 4.1.1 Boot Flash 0xBF810000
Sequence and Configuration
Interrupt Controller 0x0000
Spaces for more information. HLVD 0x1800
4: Memory locations 0x1FC54020 and
PPS 0x1400
0x1FC54024 contain a unique device
serial number (see Section 41.0 Oscillator 0x1200
Special Features).
CVREF 0x0E00
5: This configuration space cannot be 0xBF800000
used for executing code in the upper Deadman Timer 0x0A00
boot alias. Watchdog Timer 0x0800
Flash Controller 0x0600
Configuration 0x0000
Note 1: Refer to 4.4 System Bus Arbitration
for important legal information.

4.1.1 BOOT FLASH SEQUENCE AND 4.1.2 ALTERNATE SEQUENCE AND
CONFIGURATION SPACES CONFIGURATION WORDS
Sequence space is used to identify which Boot Flash is Every word in the configuration space and sequence
aliased by aliased regions. If the value programmed space has an associated alternate word (designated by
into the TSEQ<15:0> bits of the BF1SEQ3 word is the letter A as the first letter in the name of the word).
equal to or greater than the value programmed into the During device start-up, primary words are read and if
TSEQ<15:0> bits of the BF2SEQ3 word, Boot Flash 1 uncorrectable ECC errors are found, the BCFGERR
is aliased by the lower boot alias region, and Boot (RCON<27>) flag is set and alternate words are used.
Flash 2 is aliased by the upper boot alias region. If the If uncorrectable ECC errors are found in primary and
TSEQ<15:0> bits of the BF2SEQ3 word are greater alternate words, the BCFGFAIL (RCON<26>) flag is
than the TSEQ<15:0> bits of the BF1SEQ3 word, the set and the default configuration is used.
opposite is true (see Table 4-3 and Table 4-4 for
BFxSEQ3 word memory locations).
The CSEQ<15:0> bits must contain the complement
value of the TSEQ<15:0> bits; otherwise, the value of
the TSEQ<15:0> bits are considered invalid, and an
alternate sequence is used, see Section 4.1.2
Alternate Sequence and Configuration Words for
more information.
Once Boot Flash memories are aliased, configuration
space located in the lower boot alias region is used as
the basis for the Configuration words, DEVSIGN0,
DEVCP0, and DEVCFGx (and the associated alternate
configuration registers). This means that the Boot
Flash region to be aliased by lower boot alias region
memory must contain configuration values in the
appropriate memory locations.
Note: Do not use word program operation
(NVMOP<3:0> = 0001) when program-
ming data into the sequence and
configuration spaces.

TABLE 4-3: BOOT FLASH 1 SEQUENCE AND CONFIGURATION WORDS SUMMARY
DS60001361E-page 60

Bits
Virtual Address
Bit Range
(BFC4_#)
All Reset
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
FF3C ABF1DEVCFG4
31:0 xxxx
FF40 ABF1DEVCFG3
31:0 xxxx
FF44 ABF1DEVCFG2
31:0 xxxx
FF48 ABF1DEVCFG1
31:0 xxxx
FF4C ABF1DEVCFG0
31:0 xxxx
FF50 ABF1DEVCP3
31:0 xxxx
FF54 ABF1DEVCP2
31:0 Note: See Table 41-2 for the bit descriptions. xxxx
FF58 ABF1DEVCP1
31:0 xxxx
FF5C ABF1DEVCP0
31:0 xxxx
FF60 ABF1DEVSIGN3
31:0 xxxx
FF64 ABF1DEVSIGN2
31:0 xxxx
FF68 ABF1DEVSIGN1
31:0 xxxx
FF6C ABF1DEVSIGN0
31:0 xxxx
31:16 CSEQ<15:0> xxxx
FF70 ABF1SEQ3
15:0 TSEQ<15:0> xxxx
31:16 xxxx
FFF4 ABF1SEQ2
15:0 xxxx
31:16 xxxx
FF78 ABF1SEQ1
15:0 xxxx
31:16 xxxx
FF7C ABF1SEQ0
15:0 xxxx
FFBC BF1DEVCFG4 31:0 xxxx
FFC0 BF1DEVCFG3 31:0 xxxx
FFCC BF1DEVCFG0 31:0 xxxx
FFD0 BF1DEVCP3 31:0 xxxx
FFD4 BF1DEVCP2 31:0 Note: See Table 41-1 for the bit descriptions. xxxx
2015-2017 Microchip Technology Inc.
FFDC BF1DEVCP0 31:0 xxxx

FFE0 BF1DEVSIGN3 31:0 xxxx
FFEC BF1DEVSIGN0 31:0 xxxx
31:16 CSEQ<15:0> xxxx
FFF0 BF1SEQ3
31:16 xxxx
FFF4 BF1SEQ2
15:0 xxxx
31:16 xxxx
FFF8 BF1SEQ1
15:0 xxxx
31:16 xxxx
FFFC BF1SEQ0
15:0 xxxx
Legend: x = unknown value on Reset; = unimplemented, read as 0. Reset values are shown in hexadecimal.
TABLE 4-4: BOOT FLASH 2 SEQUENCE AND CONFIGURATION WORDS SUMMARY
Bits
Virtual Address
All Resets
Bit Range
(BFC6_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
FF3C ABF2DEVCFG4
31:0 xxxx
FF40 ABF2DEVCFG3
31:0 xxxx
FF44 ABF2DEVCFG2
31:0 xxxx
FF48 ABF2DEVCFG1
31:0 xxxx
FF4C ABF2DEVCFG0
31:0 xxxx
FF50 ABF2DEVCP3
31:0 xxxx
FF54 ABF2DEVCP2
31:0 Note: See Table 41-2 for the bit descriptions. xxxx
FF58 ABF2DEVCP1
31:0 xxxx
FF5C ABF2DEVCP0
31:0 xxxx
FF60 ABF2DEVSIGN3
31:0 xxxx
FF64 ABF2DEVSIGN2
31:0 xxxx
FF68 ABF2DEVSIGN1
31:0 xxxx

FF6C ABF2DEVSIGN0
31:0 xxxx
31:16 CSEQ<15:0> xxxx
FF70 ABF2SEQ3
31:16 xxxx
FFF4 ABF2SEQ2
15:0 xxxx
31:16 xxxx
FF78 ABF2SEQ1
15:0 xxxx
31:16 xxxx
FF7C ABF2SEQ0
15:0 xxxx
FFBC BF2DEVCFG4 31:0 xxxx
FFCC BF2DEVCFG0 31:0 xxxx
FFD4 BF2DEVCP2 31:0 Note: See Table 41-1 for the bit descriptions. xxxx
FFDC BF2DEVCP0 31:0 xxxx
FFEC BF2DEVSIGN0 31:0 xxxx
31:16 CSEQ<15:0> xxxx
DS60001361E-page 61
FFF0 BF2SEQ3
31:16 xxxx
FFF4 BF2SEQ2
15:0 xxxx
31:16 xxxx
FFF8 BF2SEQ1
15:0 xxxx
31:16 xxxx
FFFC BF2SEQ0
15:0 xxxx
REGISTER 4-1: BFxSEQ3/ABFxSEQ3: BOOT FLASH x SEQUENCE WORD 0 REGISTER

(x = 1 AND 2)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/P R/P R/P R/P R/P R/P R/P R/P
31:24
CSEQ<15:8>
23:16
CSEQ<7:0>
15:8
TSEQ<15:8>
7:0
TSEQ<7:0>
Legend: P = Programmable bit

bit 31-16 CSEQ<15:0>: Boot Flash Complement Sequence Number bits

bit 15-0 TSEQ<15:0>: Boot Flash True Sequence Number bits
Note: The BFxSEQ0 through BFxSEQ2 and ABFxSEQ0 through ABFxSEQ2 registers are used for Quad Word
programming operation when programming the BFxSEQ3/ABFxSEQ3 registers, and do not contain any
valid information.

4.2 DDR2 SDRAM Data masks (DDRUDM, DDRLDM) for write data
Commands entered on each positive DDRCK
Stacked DDR2 SDRAM memory devices support
edge, data and data mask are referenced to both
32 MB of DDR2 SDRAM. Memory in these devices is
edges of DDRxDQS
organized as 4,194,304 x 4 banks x 16 bits. Refer to
Figure 4-1 and Table 4-1 for the DDR2 SDRAM Posted CAS programmable additive latency sup-
address ranges. ported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS
4.2.1 FEATURES Latency (RL = AL + CL)
The DDR2 SDRAM includes the following features: Off-Chip-Driver impedance adjustment (OCD)
and On-Die-Termination (ODT) for better signal
Double Data Rate architecture: two data transfers quality
per clock cycle
Auto-precharge operation for read and write
CAS Latency: 3 and 4 bursts
Burst Length: 8 Auto Refresh and Self Refresh modes
Bi-directional, differential data strobes Precharged Power Down and Active Power Down
(DDRUDQS, DDRLDQS and DDRUDQS,
Write Latency = Read Latency - 1 (WL = RL - 1)
DDRLDQS) are transmitted / received with data
Edge-aligned with Read data and center-aligned Figure 4-3 provides a block diagram of the DDR2
with Write data SDRAM.
DLL aligns Data (DDRDQx) and Data Qualifier
Strobe (DDRxDQS, DDRxDQS) transitions with
clock
Differential clock inputs (DDRCK and /DDRCK)
FIGURE 4-3: DDR2 SDRAM BLOCK DIAGRAM
DDRCK
DLL Clock
DDRCK
Buffer
Bank 3
DDRCKE Bank 2
Bank 1
Bank 0
Control
DDRCS0 Signal
DDRRAS Command Generator
DDRCAS Decoder
DDRWE
DDRODT
DDRDQ<15:0>
DDRA<0> DDRLDQS
Mode Memory
Register Array ODT DDRLDQS
DDRA<9:0> Control
DDRA<11> Address DDRUDQS
DDRA<12> Buffer DDRUDQS
DDRBA0
DDRBA1 DDRLDM
DDRUDM
Refresh Column
Counter Counter

4.3 Timing Parameters 4.4 System Bus Arbitration
Table 4-5 only applies to device variants with internal Note: The System Bus interconnect
32 MB DDR2 SDRAM. For device variants supporting implements one or more instantiations of
external DDR2 SDRAM memory, refer to the vendor the SonicsSX interconnect from Sonics,
data sheet for timing parameters. Inc. This document contains materials
that are (c) 2003-2015 Sonics, Inc., and
TABLE 4-5: TIMING PARAMETERS that constitute proprietary information of
Sonics, Inc. SonicsSX is a registered
Parameter Description Value Units
trademark of Sonics, Inc. All such
tRFC Auto-refresh Cycle Time 130 ns materials and trademarks are used under
tWR Write Recovery Time 25 ns license from Sonics, Inc.
tRP Precharge-to-Active 20 ns As shown in the PIC32MZ DA Family Block Diagram
Command Delay Time (see Figure 1-1), there are multiple initiator modules (I1
tRCD Active to Read/Write 20 ns through I14) in the system that can access various tar-
Command Delay Time get modules (T1 through T23). Table 4-6 illustrates
tRRD Row-to-Row (RAS to 7.5 ns which initiator can access which target. The System
RAS) Command Delay Bus supports simultaneous access to targets by
Time initiators, so long as the initiators are accessing differ-
ent targets. The System Bus will perform arbitration if
tWTR Write-to-Read Command 15 ns
multiple initiators attempt to access the same target.
Delay Time
tRTP Read-to-Precharge 20 ns
Command Delay Time
tDLLK DLL Lock Delay Time 200 Clock
cycles
tRAS Active to Precharge 40 ns
Minimum Command
Delay Time
tRC Row Cycle Time 110 ns
tFAW Four Bank Activation 35 ns
Window
tMRD Mode Register Set 4 Clock
Command Cycle Delay cycles
tXP Power Down Exit Delay 6 Clock
cycles
tCKE Power Down Minimum 6 Clock
Delay cycles
RL CAS Latency 4 Clock
cycles
tRFI Average Periodic 7.8 s
Refresh Interval
WL Write Latency 3 Clock
cycles
BL Burst Length (in cycles) 8 Clock
cycles

TABLE 4-6: INITIATORS TO TARGETS ACCESS ASSOCIATION
Initiator ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Target
Number DMA DMA Ethernet Ethernet Flash
Name CPU USB CAN1 CAN2 SQI1 Crypto GLCD GPU SDHC
Read Write Read Write Controller
Flash Memory:
Program Flash
1 X X X X X X X
Boot Flash
Prefetch Module
2 RAM Bank 1 Memory X X X X X X X X X X X X X X
3 RAM Bank 2 Memory X X X X X X X X X X X X X X
Peripheral Set 1:
System Control
Flash Control
DMT
CVREF
5 X
PPS Input
PPS Output
Interrupts
DMA

WDT
Peripheral Set 2:
SPI1-SPI6
6 I2C1-I2C5 X X X
UART1-UART6
PMP
Peripheral Set 3:
Timer1-Timer9
IC1-IC9
OC1-OC9
7 X X X
ADC
Comparator 1
Comparator 2
CTMU
Peripheral Set 4:
8 X X X
PORTA-PORTK
Peripheral Set 5:
CAN1
9 X X X
CAN2
Ethernet Controller
10 USB X X X
11 External Memory via SQI1 and SQI1 Module X
12 Crypto Engine X
DS60001361E-page 65
13 RNG Module X
14 Graphics LCD Controller X
15 External Memory via DDR2 and DDR2 Target 0 X
16 External Memory via DDR2 and DDR2 Targets 1 and 2 X X X X X X X X X X X
17 External Memory via DDR2 and DDR2 Targets 3 and 4 X(1) X(1)
Note 1: The GLCD and GPU are directly connected to the DDR2 SDRAM Controller to use DDR2 SDRAM for frame buffers. Arbitration control is done through the DDR2 SDRAM Controller arbitration engine.
Refer to Section 55. DDR2 SDRAM Controller (DS60001321) in the PIC32 Family Reference Manual for additional information.
DS60001361E-page 66
TABLE 4-6: INITIATORS TO TARGETS ACCESS ASSOCIATION (CONTINUED)

Initiator ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Target
Number DMA DMA Ethernet Ethernet Flash
Name CPU USB CAN1 CAN2 SQI1 Crypto GLCD GPU SDHC
Read Write Read Write Controller
18 2D Graphics Processing Unit X
19 Secure Digital Host Controller X
20 DDR2 PHY Control Register Interface X
21 DDR2 Control Register Interface X
Peripheral Set 6:
22 RTCC X
DSCTRL
23 External Memory via EBI and EBI Module X X X X X X X X X X X
Note 1: The GLCD and GPU are directly connected to the DDR2 SDRAM Controller to use DDR2 SDRAM for frame buffers. Arbitration control is done through the DDR2 SDRAM Controller arbitration engine.
Refer to Section 55. DDR2 SDRAM Controller (DS60001321) in the PIC32 Family Reference Manual for additional information.
The System Bus arbitration scheme implements a non- 4.5 Permission Access and System
programmable, Least Recently Serviced (LRS). Bus Registers
The arbitration scheme for the available initiators is
The System Bus on PIC32MZ DA family of
shown in Table 4-7.
microcontrollers provides access control capabilities
for the transaction initiators on the System Bus.
TABLE 4-7: INITIATOR ID AND
ARBITRATION The System Bus divides the entire memory space into
17 regions and permits access to each target by initia-
ID Name Arbitration tors via permission groups. Four Permission Groups
1 CPU LRS (0 through 3) can be assigned to each initiator. Each
permission group is independent of the others and
2 DMA Read LRS
can have exclusive or shared access to a region.
3 DMA Write LRS
Using the CFGPG register (see Register 41-12 in
4 USB LRS Section 41.0 Special Features), Boot firmware can
5 Ethernet Read LRS assign a permission group to each initiator, which can
6 Ethernet Write LRS make requests on the System Bus.
7 CAN1 LRS The available targets and their regions, as well as the
associated control registers to assign protection, are
8 CAN2 LRS
described and listed in Table 4-8.
9 SQI1 LRS
Register 4-2 through Register 4-13 are used for setting
10 Flash Controller LRS and controlling access permission groups and regions.
11 Crypto LRS
To change these registers, they must be unlocked in
12 GLCD(1) LRS hardware. The register lock is controlled by the
13 GPU(1) LRS PGLOCK Configuration bit (CFGCON<11>). Setting
14 SDHC LRS the PGLOCK bit prevents writes to the control
registers and clearing the PGLOCK bit allows writes.
Note 1: The GLCD and GPU are directly
connected to DDR2 SDRAM Controller to To set or clear the PGLOCK bit, an unlock sequence
use DDR2 SDRAM for frame buffers. must be executed. Refer to Section 42. Oscillators
Arbitration control is done through the with Enhanced PLL (DS60001250) in the PIC32
DDR2 SDRAM Controller arbitration Family Reference Manual for details.
engine.

TABLE 4-8: SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS
DS60001361E-page 68

SBTxREGy Register (see Note 7) SBTxRDy Register SBTxWRy Register
Read Write
Target
Target Description Permission Permission
Protection Region Base Physical Region Size
(see Note 5) Region Priority Priority (GROUP3, (GROUP3,
Number Name (BASE<21:0>) Start (SIZE<4:0>) Name Name
Size (PRI) Level GROUP2, GROUP2,
(see Note 2) Address (see Note 3)
GROUP1, GROUP1,
GROUP0) GROUP0)
0 System Bus SBT0REG0 R 0x1F8F0000 R 64 KB 0 SBT0RD0 0,1,1,1 SBT0WR0 0,1,1,1
SBT0REG1 R 0x1F8F8000 R 32 KB 3 SBT0RD1 0,0,0,1 SBT0WR1 0,0,0,1
1 Flash Memory(6): SBT1REG0 R 0x1D000000 R(4) R(4) 0 SBT1RD0 0,0,0,0 SBT1WR0 0,0,0,0
Program Flash SBT1REG2 R 0x1F8E0000 R 4 KB 1 2 SBT1RD2 R/W(1) SBT1WR2 R/W(1)
Boot Flash Prefetch
SBT1REG3 R/W R/W R/W R/W 1 2 SBT1RD3 0,0,0,0 SBT1WR3 0,0,0,0
2 RAM Bank 1 Memory SBT2REG0 R 0 R(4) R(4) 0 SBT2RD0 R/W(1) SBT2WR0 R/W(1)
SBT2REG1 R/W R/W R/W R/W 3 SBT2RD1 R/W(1) SBT2WR1 R/W(1)
SBT2REG2 R/W R/W R/W R/W 0 1 SBT2RD2 R/W(1) SBT2WR2 R/W(1)
(4) (4) (4) (4) (1)
3 RAM Bank 2 Memory SBT3REG0 R R R R 0 SBT3RD0 R/W SBT3WR0 R/W(1)
(1)
4 External Memory via DDR2 and SBT4REG0 R 0x08000000 R R(4) 0 SBT4RD0 R/W SBT4WR0 R/W(1)
DDR2 Target 0 SBT4REG1 R/W R/W R/W R/W 3 SBT4RD1 R/W(1) SBT4WR1 R/W(1)
5 External Memory via DDR2 and SBT5REG0 R 0x08000000 R R(4) 0 SBT5RD0 R/W(1) SBT5WR0 R/W(1)
DDR2 Targets 1 and 2 R/W(1) R/W(1)
SBT5REG1 R/W R/W R/W R/W 3 SBT5RD1 SBT5WR1

(1)
SBT5REG4 R/W R/W R/W R/W 1 2 SBT5RD4 R/W SBT5WR4 R/W(1)
Legend: R = Read; R/W = Read/Write; x in a register name = 0-13; y in a register name = 0-8.
Note 1: Reset values for these bits are 0, 1, 1, 1, respectively.
2: The BASE<21:0> bits must be set to the corresponding Physical Address and right shifted by 10 bits. For Read-only bits, this value is set by hardware on Reset.
3: The SIZE<4:0> bits must be set to the corresponding Region Size, based on the following formula: Region Size = 2(SIZE-1) x 1024 bytes. For read-only bits, this value is set by hardware on Reset.
4: Refer to the Device Memory Map (Figure 4-1) for specific device memory sizes and start addresses.
5: See Table 4-2 for information on specific target memory size and start addresses.
6: The SBTxREG1 SFRs are reserved, and therefore, are not listed in this table for this target.
7: The x' in the SBTxREGy, SBTxRDy, and SBTxWRy registers represents the target protection number and not the actual target number (e.g., for SQI x = 13 and not 11, whereas 11 is the actual
target number).
TABLE 4-8: SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS (CONTINUED)
Read Write
Target
GROUP1, GROUP1,
GROUP0) GROUP0)
6 External Memory via EBI and EBI SBT6REG0 R 0x20000000 R 64 MB 0 SBT6RD0 R/W(1) SBT6WR0 R/W(1)
Module(6) SBT6REG2 R 0x1F8EC000 R 4 KB 0 1 SBT6RD2 R/W (1)
SBT6WR2 R/W(1)
7 System Controller SBT7REG0 R 0x1F800000 R 0 SBT7RD0 R/W(1) SBT7WR0 R/W(1)
Flash Controller SBT7REG1 R/W R/W R/W R/W 3 SBT7RD1 R/W(1) SBT7WR1 R/W(1)
(1)
DMT/WDT SBT7REG2 R/W R/W R/W R/W 0 1 SBT7RD2 R/W SBT7WR2 R/W(1)
CVREF
PPS Input
PPS Output
Interrupts
DMA

8 SPI1-SPI6 SBT8REG0 R 0x1F820000 R 64 KB 0 SBT8RD0 R/W(1) SBT8WR0 R/W(1)
I2C1-I2C5 SBT8REG1 R/W R/W R/W R/W 3 SBT8RD1 R/W(1) SBT8WR1 R/W(1)
UART1-UART6
PMP
9 Timer1-Timer9 SBT9REG0 R 0x1F840000 R 64 KB 0 SBT9RD0 R/W(1) SBT9WR0 R/W(1)
IC1-IC9 SBT9REG1 R/W R/W R/W R/W 3 SBT9RD1 R/W(1) SBT9WR1 R/W(1)
OC1-OC9
ADC
Comparator 1
Comparator 2
10 PORTA-PORTK SBT10REG0 R 0x1F860000 R 64 KB 0 SBT10RD0 R/W(1) SBT10WR0 R/W(1)
11 CAN1 SBT11REG0 R 0x1F880000 R 64 KB 0 SBT11RD0 R/W(1) SBT11WR0 R/W(1)
(1)
CAN2 SBT11REG1 R/W R/W R/W R/W 3 SBT11RD1 R/W SBT11WR1 R/W(1)
Ethernet
12 GLCD SBT12REG0 R 0x1F8EA000 R 4 KB 0 SBT12RD0 R/W(1) SBT12WR0 R/W(1)
GPU R 0x1F8EB000 R 4 KB 0 R/W(1) R/W(1)
DDR2PHY R 0x1F8E9000 R 4 KB 0 R/W(1) R/W(1)
DDR2SFR R 0x1F8E8000 R 4 KB 0 R/W(1) R/W(1)
(1)
13 External Memory via SQI1 and SBT13REG0 R 0x30000000 R 64 MB 0 SBT13RD0 R/W SBT13WR0 R/W(1)
SQI1 SBT13REG1 R 0x1F8E2000 R 4 KB 3 SBT13RD1 R/W(1) SBT13WR1 R/W(1)
DS60001361E-page 69
target number).
DS60001361E-page 70
TABLE 4-8: SYSTEM BUS TARGETS AND ASSOCIATED PROTECTION REGISTERS (CONTINUED)

Read Write
Target
GROUP1, GROUP1,
GROUP0) GROUP0)
14 DSCTRL SBT14REG0 R 0x1F8C0000 R 4 KB 0 SBT14RD0 R/W(1) SBT14WR0 R/W(1)
RTCC SBT14REG1 R/W R/W R/W R/W 3 SBT14RD1 R/W(1) SBT14WR1 R/W(1)
(1)
15 USB SBT15REG0 R 0x1F8E0000 R 4 KB 0 SBT15RD0 R/W SBT15WR0 R/W(1)
Crypto R 0x1F8E5000 R 4 KB 0 R/W(1) R/W(1)
RNG R 0x1F8E6000 R 4 KB 0 R/W(1) R/W(1)
SDHC R 0x1F8EC000 R 4 KB 0 R/W(1) R/W(1)
16 External Memory via DDR2 and SBT16REG0 R 0x08000000 R R(4) 0 SBT16RD0 R/W(1) SBT16WR0 R/W(1)
DDR2 Targets 3 and 4 SBT16REG1 R/W R/W R/W R/W 3 SBT16RD1 R/W (1)
SBT16WR1 R/W(1)
(1)
SBT16REG4 R/W R/W R/W R/W 1 2 SBT16RD4 R/W SBT16WR4 R/W(1)
target number).
TABLE 4-9: SYSTEM BUS VIOLATION FLAG REGISTER MAP
Virtual Address
Bits
Bit Range
(BFxx_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
8F_ 31:16 0000

0510 SBFLAG0
15:0 T0PGV0 T3PGV T6PGV T2PGV T5PGV T4PGV T1PGV 0000
90_ 31:16 0000
0510 SBFLAG1
15:0 T0PGV1 T12PGV T11PGV T10PGV T9PGV T8PGV T7PGV 0000
91_ 31:16 0000
0510 SBFLAG2
15:0 T0PGV2 T15PGV T14PGV T13PGV 0000
92_ 31:16 0000
0510 SBFLAG3
15:0 T0PGV3 T16PGV 0000

DS60001361E-page 71
TABLE 4-10: SYSTEM BUS TARGET PROTECTION GROUP 0 (T0PGV0 - T0PGV3) REGISTER MAP
DS60001361E-page 72

Virtual Address
Bits
Bit Range
(BF8F_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

8020 SBT0ELOG1
15:0 INITID<7:0> REGION<3:0> CMD<2:0> 0000
31:16 0000
8024 SBT0ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
8028 SBT0ECON
15:0 0000
31:16 0000
8030 SBT0ECLRS
15:0 CLEAR 0000
31:16 0000
8038 SBT0ECLRM
15:0 CLEAR 0000
31:16 BASE<21:6> xxxx
8040 SBT0REG0
15:0 BASE<5:0> PRI SIZE<4:0> xxxx
31:16 xxxx
8050 SBT0RD0
15:0 GROUP3 GROUP2 GROUP1 GROUP0 xxxx
31:16 xxxx
8058 SBT0WR0
31:16 BASE<21:6> xxxx
8060 SBT0REG1
31:16 xxxx
8070 SBT0RD1
31:16 xxxx
8078 SBT0WR1
Note: For reset values listed as xxxx, please refer to Table 4-8 for the actual reset values.
TABLE 4-11: SYSTEM BUS TARGET PROTECTION GROUP 1 REGISTER MAP
Virtual Address
Bits
Bit Range
(BF8F_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

8420 SBT1ELOG1
31:16 0000
8424 SBT1ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
8428 SBT1ECON
15:0 0000
31:16 0000
8430 SBT1ECLRS
15:0 CLEAR 0000
31:16 0000
8438 SBT1ECLRM
15:0 CLEAR 0000

31:16 BASE<21:6> xxxx
8440 SBT1REG0
31:16 xxxx
8450 SBT1RD0
31:16 xxxx
8458 SBT1WR0
31:16 BASE<21:6> xxxx
8480 SBT1REG2
31:16 xxxx
8490 SBT1RD2
31:16 xxxx
8498 SBT1WR2
31:16 BASE<21:6> xxxx
84A0 SBT1REG3
31:16 xxxx
84B0 SBT1RD3
31:16 xxxx
84B8 SBT1WR3
31:16 BASE<21:6> xxxx
84C0 SBT1REG4
DS60001361E-page 73

31:16 xxxx
84D0 SBT1RD4
31:16 xxxx
84D8 SBT1WR4
DS60001361E-page 74
TABLE 4-11: SYSTEM BUS TARGET PROTECTION GROUP 1 REGISTER MAP (CONTINUED)

Virtual Address
Bits
Bit Range
(BF8F_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 BASE<21:6> xxxx

84E0 SBT1REG5
31:16 xxxx
84F0 SBT1RD5
31:16 xxxx
84F8 SBT1WR5
31:16 BASE<21:6> xxxx
8500 SBT1REG6
31:16 xxxx
8510 SBT1RD6
31:16 xxxx
8518 SBT1WR6
31:16 BASE<21:6> xxxx
8520 SBT1REG7
31:16 xxxx
8530 SBT1RD7
31:16 xxxx
8538 SBT1WR7
31:16 BASE<21:6> xxxx
8540 SBT1REG8
31:16 xxxx
8550 SBT1RD8
31:16 xxxx
8558 SBT1WR8
Virtual Address Bits
Bit Range
(BF8F_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

8820 SBT2ELOG1
31:16 0000
8824 SBT2ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
8828 SBT2ECON
15:0 0000
31:16 0000
8830 SBT2ECLRS
15:0 CLEAR 0000
31:16 0000
8838 SBT2ECLRM
15:0 CLEAR

0000
31:16 BASE<21:6> xxxx
8840 SBT2REG0
31:16 xxxx
8850 SBT2RD0
31:16 xxxx
8858 SBT2WR0
31:16 BASE<21:6> xxxx
8860 SBT2REG1
31:16 xxxx
8870 SBT2RD1
31:16 xxxx
8878 SBT2WR1
31:16 BASE<21:6> xxxx
8880 SBT2REG2
31:16 xxxx
8890 SBT2RD2
31:16 xxxx
DS60001361E-page 75
8898 SBT2WR2
DS60001361E-page 76

Virtual Address
Bits
Bit Range
(BF8F_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

8C20 SBT3ELOG1
31:16 0000
8C24 SBT3ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
8C28 SBT3ECON
15:0 0000
31:16 0000
8C30 SBT3ECLRS
15:0 CLEAR 0000
31:16 0000
8C38 SBT3ECLRM
15:0 CLEAR 0000
31:16 BASE<21:6> xxxx
8C40 SBT3REG0
31:16 xxxx
8C50 SBT3RD0
31:16 xxxx
8C58 SBT3WR0
31:16 BASE<21:6> xxxx
8C60 SBT3REG1
31:16 xxxx
8C70 SBT3RD1
31:16 xxxx
8C78 SBT3WR1
31:16 BASE<21:6> xxxx

8C80 SBT3REG2
31:16 xxxx
8C90 SBT3RD2
31:16 xxxx
8C98 SBT3WR2
Bit Range
(BF8F_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

9020 SBT4ELOG1
31:16 0000
9024 SBT4ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
9028 SBT4ECON
15:0 0000
31:16 0000
9030 SBT4ECLRS
15:0 CLEAR 0000
31:16 0000
9038 SBT4ECLRM
15:0 CLEAR

0000
31:16 BASE<21:6> xxxx
9040 SBT4REG0
31:16 xxxx
9050 SBT4RD0
31:16 xxxx
9058 SBT4WR0
31:16 BASE<21:6> xxxx
9060 SBT4REG1
31:16 xxxx
9070 SBT4RD1
31:16 xxxx
9078 SBT4WR1
31:16 BASE<21:6> xxxx
9080 SBT4REG2
31:16 xxxx
9090 SBT4RD2
31:16 xxxx
DS60001361E-page 77
9098 SBT4WR2
31:16 BASE<21:6> xxxx

90A0 SBT4REG3
DS60001361E-page 78

Virtual Address
Bits
Bit Range
(BF8F_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 xxxx
90B0 SBT4RD3
31:16 xxxx
90B8 SBT4WR3
31:16 BASE<21:6> xxxx
90C0 SBT4REG4
31:16 xxxx
90D0 SBT4RD4
31:16 xxxx
90D8 SBT4WR4
Bit Range
(BF8F_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

9420 SBT5ELOG1
31:16 0000
9424 SBT5ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
9428 SBT5ECON
15:0 0000
31:16 0000
9430 SBT5ECLRS
15:0 CLEAR 0000
31:16 0000
9438 SBT5ECLRM
15:0 CLEAR

0000
31:16 BASE<21:6> xxxx
9440 SBT5REG0
31:16 xxxx
9450 SBT5RD0
31:16 xxxx
9458 SBT5WR0
31:16 BASE<21:6> xxxx
9460 SBT5REG1
31:16 xxxx
9470 SBT5RD1
31:16 xxxx
9478 SBT5WR1
31:16 BASE<21:6> xxxx
9480 SBT5REG2
31:16 xxxx
9490 SBT5RD2
31:16 xxxx
DS60001361E-page 79
9498 SBT5WR2
DS60001361E-page 80

Virtual Address
Bits
Bit Range
(BF8F_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 BASE<21:6> xxxx

94A0 SBT5REG3
31:16 xxxx
94B0 SBT5RD3
31:16 xxxx
94B8 SBT5WR3
31:16 BASE<21:6> xxxx
94C0 SBT5REG4
31:16 xxxx
94D0 SBT5RD4
31:16 xxxx
94D8 SBT5WR4
Bit Range
(BF8F_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

9820 SBT6ELOG1
31:16 0000
9824 SBT6ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
9828 SBT6ECON
15:0 0000
31:16 0000
9830 SBT6ECLRS
15:0 CLEAR 0000
31:16 0000
9838 SBT6ECLRM
15:0 CLEAR

0000
31:16 BASE<21:6> xxxx
9840 SBT6REG0
31:16 xxxx
9850 SBT6RD0
31:16 xxxx
9858 SBT6WR0
31:16 BASE<21:6> xxxx
9860 SBT6REG1
31:16 xxxx
9870 SBT6RD1
31:16 xxxx
9878 SBT6WR1
DS60001361E-page 81
DS60001361E-page 82

Virtual Address
Bits
Bit Range
(BF90_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

8420 SBT7ELOG1
31:16 0000
8424 SBT7ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
8428 SBT7ECON
15:0 0000
31:16 0000
8430 SBT7ECLRS
15:0 CLEAR 0000
31:16 0000
8438 SBT7ECLRM
15:0 CLEAR 0000
31:16 BASE<21:6> xxxx
8440 SBT7REG0
31:16 xxxx
8450 SBT7RD0
31:16 xxxx
8458 SBT7WR0
31:16 BASE<21:6> xxxx
8460 SBT7REG1
31:16 xxxx
8470 SBT7RD1
31:16 xxxx
8478 SBT7WR1
31:16 BASE<21:6> xxxx

8480 SBT7REG2
31:16 xxxx
8490 SBT7RD2
31:16 xxxx
8498 SBT7WR2
Bit Range
(BF90_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

8820 SBT8ELOG1
31:16 0000
8824 SBT8ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
8828 SBT8ECON
15:0 0000
31:16 0000
8830 SBT8ECLRS
15:0 CLEAR 0000
31:16 0000
8838 SBT8ECLRM
15:0 CLEAR

0000
31:16 BASE<21:6> xxxx
8840 SBT8REG0
31:16 xxxx
8850 SBT8RD0
31:16 xxxx
8858 SBT8WR0
31:16 BASE<21:6> xxxx
8860 SBT8REG1
31:16 xxxx
8870 SBT8RD1
31:16 xxxx
8878 SBT8WR1
DS60001361E-page 83
DS60001361E-page 84

Virtual Address
Bits
Bit Range
(BF90_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

8C20 SBT9ELOG1
31:16 0000
8C24 SBT9ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
8C28 SBT9ECON
15:0 0000
31:16 0000
8C30 SBT9ECLRS
15:0 CLEAR 0000
31:16 0000
8C38 SBT9ECLRM
15:0 CLEAR 0000
31:16 BASE<21:6> xxxx
8C40 SBT9REG0
31:16 xxxx
8C50 SBT9RD0
31:16 xxxx
8C58 SBT9WR0
31:16 BASE<21:6> xxxx
8C60 SBT9REG1
31:16 xxxx
8C70 SBT9RD1
31:16 xxxx
8C78 SBT9WR1
Bit Range
(BF90_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

9020 SBT10ELOG1
31:16 0000
9024 SBT10ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
9028 SBT10ECON
15:0 0000
31:16 0000
9030 SBT10ECLRS
15:0 CLEAR 0000
31:16 0000
9038 SBT10ECLRM
15:0 CLEAR

0000
31:16 BASE<21:6> xxxx
9040 SBT10REG0
31:16 xxxx
9050 SBT10RD0
31:16 xxxx
9058 SBT10WR0
31:16 BASE<21:6> xxxx
9060 SBT10REG1
31:16 xxxx
9070 SBT10RD1
31:16 xxxx
9078 SBT10WR1
DS60001361E-page 85
DS60001361E-page 86

Virtual Address
Bits
Bit Range
(BF90_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

9420 SBT11ELOG1
31:16 0000
9424 SBT11ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
9428 SBT11ECON
15:0 0000
31:16 0000
9430 SBT11ECLRS
15:0 CLEAR 0000
31:16 0000
9438 SBT11ECLRM
15:0 CLEAR 0000
31:16 BASE<21:6> xxxx
9440 SBT11REG0
31:16 xxxx
9450 SBT11RD0
31:16 xxxx
9458 SBT11WR0
31:16 BASE<21:6> xxxx
9460 SBT11REG1
31:16 xxxx
9470 SBT11RD1
31:16 xxxx
9478 SBT11WR1
Bit Range
(BF90_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

9820 SBT12ELOG1
31:16 0000
9824 SBT12ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
9828 SBT12ECON
15:0 0000
31:16 0000
9830 SBT12ECLRS
15:0 CLEAR 0000
31:16 0000
9838 SBT12ECLRM
15:0 CLEAR

0000
31:16 BASE<21:6> xxxx
9840 SBT12REG0
31:16 xxxx
9850 SBT12RD0
31:16 xxxx
9858 SBT12WR0
DS60001361E-page 87
DS60001361E-page 88

Virtual Address
Bits
Bit Range
(BF91_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

8420 SBT13ELOG1
31:16 0000
8424 SBT13ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
8428 SBT13ECON
15:0 0000
31:16 0000
8430 SBT13ECLRS
15:0 CLEAR 0000
31:16 0000
8438 SBT13ECLRM
15:0 CLEAR 0000
31:16 BASE<21:6> xxxx
8440 SBT13REG0
31:16 xxxx
8450 SBT13RD0
31:16 xxxx
8458 SBT13WR0
31:16 BASE<21:6> xxxx
8460 SBT13REG1
31:16 xxxx
8470 SBT13RD1
31:16 xxxx
8478 SBT13WR1
Virtual Address
Bits
Bit Range
(BF91_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

8820 SBT14ELOG1
31:16 0000
8824 SBT14ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
8828 SBT14ECON
15:0 0000
31:16 0000
8830 SBT14ECLRS
15:0 CLEAR 0000
31:16 0000
8838 SBT14ECLRM
15:0 CLEAR 0000

31:16 BASE<21:6> xxxx
8840 SBT14REG0
31:16 xxxx
8850 SBT14RD0
31:16 xxxx
8858 SBT14WR0
31:16 BASE<21:6> xxxx
8860 SBT14REG1
31:16 xxxx
8870 SBT14RD1
31:16 xxxx
8878 SBT14WR1
DS60001361E-page 89
DS60001361E-page 90

Virtual Address
Bits
Bit Range
(BF91_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

8C20 SBT15ELOG1
31:16 0000
8C24 SBT15ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
8C28 SBT15ECON
15:0 0000
31:16 0000
8C30 SBT15ECLRS
15:0 CLEAR 0000
31:16 0000
8C38 SBT15ECLRM
15:0 CLEAR 0000
31:16 BASE<21:6> xxxx
8C40 SBT15REG0
31:16 xxxx
8C50 SBT15RD0
31:16 xxxx
8C58 SBT15WR0
Virtual Address
Bits
Bit Range
(BF92_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 MULTI CODE<3:0> 0000

C420 SBT16ELOG1
31:16 0000
C424 SBT16ELOG2
15:0 GROUP<1:0> 0000
31:16 ERRP 0000
C428 SBT16ECON
15:0 0000
31:16 0000
C430 SBT16ECLRS
15:0 CLEAR 0000
31:16 0000
C438 SBT16ECLRM
15:0 CLEAR 0000

31:16 BASE<21:6> xxxx
C440 SBT16REG0
31:16 xxxx
C450 SBT16RD0
31:16 xxxx
C458 SBT16WR0
31:16 BASE<21:6> xxxx
C460 SBT16REG1
31:16 xxxx
C470 SBT16RD1
31:16 xxxx
C478 SBT16WR1
31:16 BASE<21:6> xxxx
C480 SBT16REG2
31:16 xxxx
C490 SBT16RD2
31:16 xxxx
C498 SBT16WR2
31:16 BASE<21:6> xxxx
C4A0 SBT16REG3
DS60001361E-page 91

31:16 xxxx
C4B0 SBT16RD3
31:16 xxxx
C4B8 SBT16WR3
DS60001361E-page 92

Virtual Address
Bits
Bit Range
(BF92_#)
Register
Resets
Name
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 BASE<21:6> xxxx

C4C0 SBT16REG4
31:16 xxxx
C4D0 SBT16RD4
31:16 xxxx
C4D8 SBT16WR4
REGISTER 4-2: SBFLAG0: SYSTEM BUS STATUS FLAG REGISTER 0

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
T0PGV0(1) T3PGV T6PGV T2PGV T5PGV T4PGV T1PGV
Legend:
-n = Value at POR 1 = Bit is set 0 = Bit is cleared

bit 6 T0PGV0: Target 0 (System Bus 0) Permission Group Violation Status bit(1)
1 = Target 0 (System Bus 0) is reporting a Permission Group (PG) violation
0 = Target 0 (System Bus 0) is not reporting a PG violation
bit 5 T3PGV: Target 3 (RAM Bank 2) Permission Group Violation Status bit
1 = Target 3 is reporting a Permission Group (PG) violation
0 = Target 3 is not reporting a PG violation
bit 4 T6PGV: Target 6 (EBI) Permission Group Violation Status bit
bit 3 T2PGV: Target 2 (RAM Bank 1) Permission Group Violation Status bit
bit 2 T5GV: Target 5 (DDR2 Target 1 and Target 2) Permission Group Violation Status bit
bit 1 T4PGV: Target 4 (DDR2 Target 0) Permission Group Violation Status bit
bit 0 T1PGV: Target 1 (Flash Memory) Permission Group Violation Status bit
Note 1: System Bus 0 represents an internal sub-system element and should be treated as a general System Bus
violation.
Note: All errors are cleared at the source (i.e., SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM
registers).


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
T0PGV1(1) T12PGV(2) T11PGV T10PGV T9PGV T8PGV T7PGV
Legend:

bit 5 T12PGV: Target Group 12 (GLCD, GPU, DDR2PHY, DDR2SFR) Permission Group Violation Status bit(2)
1 = Target group 12 is reporting a Permission Group (PG) violation
0 = Target group 12 is not reporting a PG violation
bit 4 T11PGV: Target 11 (PB5) Permission Group Violation Status bit
violation.
2: This bit reports violations on Targets 14 (GLCD), 18 (GPU), 20 (DDR2PHY) and 21 (DDR2SFR).
registers).


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
T0PGV2(1) T15PGV(2) T14PGV T13PGV
Legend:

bit 2 T15PGV: Target Group 15 (USB, Crypto, RNG, SDHC) Permission Group Violation Status bit(2)
1 = Target group 15 is reporting a Permission Group (PG) violation
0 = Target group 15 is not reporting a PG violation
bit 0 T13PGV: Target 13 (SQI) Permission Group Violation Status bit
Note 1: System Bus 2 represents an internal sub-system element and should be treated as a general System Bus vio-
lation.
2: This bit reports violations on Targets 10 (USB), 12 (Crypto), 13 (RNG) and 19 (SDHC).
Note: All errors are cleared at the source (i.e., SBTxELOG1, SBTxELOG2, SBTxECLRS, or SBTxECLRM registers).


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
7:0
T0PGV3(1) T16PGV
Legend:

bit 0 T16PGV: Target 16 (DDR2 Target 3 and Target 4) Permission Group Violation Status bit
violation.
registers).

REGISTER 4-6: SBTxELOG1: SYSTEM BUS TARGET x ERROR LOG REGISTER 1

(x = 0-13)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0, C U-0 U-0 U-0 R/W-0, C R/W-0, C R/W-0, C R/W-0, C
31:24
MULTI CODE<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
INITID<7:0>
R-0 R-0 R-0 R-0 U-0 R-0 R-0 R-0
7:0
REGION<3:0> CMD<2:0>
Legend: C = Clearable bit

bit 31 MULTI: Multiple Permission Violations Status bit

This bit is cleared by writing a 1.
1 = Multiple errors have been detected
0 = No multiple errors have been detected
bit 27-24 CODE<3:0>: Error Code bits
Indicates the type of error that was detected. These bits are cleared by writing a 1.
1111 = Reserved
1101 = Reserved

0011 = Permission violation
0010 = Reserved
0001 = Reserved
0000 = No error
Note: Refer to Table 4-8 for the list of available targets and their descriptions.

REGISTER 4-6: SBTxELOG1: SYSTEM BUS TARGET x ERROR LOG REGISTER 1
(x = 0-13) (CONTINUED)
bit 15-8 INITID<7:0>: Initiator ID of Requester bits
11111111 = Reserved

00001111 = Reserved
00001110 = SDHC
00001101 = GPU
00001100 = GLCD
00001011 = Crypto Engine
00001010 = Flash Controller
00001001 = SQI1
00001000 = CAN2
00000111 = CAN1
00000110 = Ethernet Write
00000101 = Ethernet Read
00000100 = USB
00000011 = DMA Write
00000010 = DMA Read
00000001 = CPU
00000000 = Reserved
bit 7-4 REGION<3:0>: Requested Region Number bits
1111 - 0000 = Targets region that reported a permission group violation
bit 2-0 CMD<2:0>: Transaction Command of the Requester bits
111 = Reserved
110 = Reserved
101 = Write (a non-posted write)
100 = Reserved
011 = Read (a locked read caused by a Read-Modify-Write transaction)
010 = Read
001 = Write
000 = Idle

REGISTER 4-7: SBTxELOG2: SYSTEM BUS TARGET x ERROR LOG REGISTER 2 (x = 0-13)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0
7:0
GROUP<1:0>
Legend:

bit 1-0 GROUP<1:0>: Requested Permissions Group bits
11 = Group 3
10 = Group 2
01 = Group 1
00 = Group 0
REGISTER 4-8: SBTxECON: SYSTEM BUS TARGET x ERROR CONTROL REGISTER

(x = 0-13)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
31:24
ERRP
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:

bit 24 ERRP: Error Control bit
1 = Report protection group violation errors
0 = Do not report protection group violation errors

REGISTER 4-9: SBTxECLRS: SYSTEM BUS TARGET x SINGLE ERROR CLEAR REGISTER
(x = 0-13)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0
7:0
CLEAR
Legend:

bit 0 CLEAR: Clear Single Error on Read bit
A single error as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.
REGISTER 4-10: SBTxECLRM: SYSTEM BUS TARGET x MULTIPLE ERROR CLEAR REGISTER
(x = 0-13)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0
7:0
CLEAR
Legend:

bit 0 CLEAR: Clear Multiple Errors on Read bit
Multiple errors as reported via SBTxELOG1 and SBTxELOG2 is cleared by a read of this register.

REGISTER 4-11: SBTxREGy: SYSTEM BUS TARGET x REGION y REGISTER

(x = 0-13; y = 0-8)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W0 R/W-0 R/W0 R/W-0 R/W0 R/W-0 R/W0 R/W-0
31:24
BASE<21:14>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
BASE<13:6>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 U-0
15:8
BASE<5:0> PRI
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
7:0
SIZE<4:0>
Legend:
bit 31-10 BASE<21:0>: Region Base Address bits

bit 9 PRI: Region Priority Level bit
1 = Level 2
0 = Level 1
bit 7-3 SIZE<4:0>: Region Size bits
Permissions for a region are only active is the SIZE is non-zero.
11111 = Region size = 2(SIZE 1) x 1024 (bytes)

00001 = Region size = 2(SIZE 1) x 1024 (bytes)
00000 = Region is not present
Note 1: Refer to Table 4-8 for the list of available targets and their descriptions.
2: For some target regions, certain bits in this register are read-only with preset values. See Table 4-8 for
more information.

REGISTER 4-12: SBTxRDy: SYSTEM BUS TARGET x REGION y READ PERMISSIONS

REGISTER (x = 0-13; y = 0-8)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-1
7:0
GROUP3 GROUP2 GROUP1 GROUP0
Legend:

bit 3 Group3: Group3 Read Permissions bits
1 = Privilege Group 3 has read permission
0 = Privilege Group 3 does not have read permission
more information.

REGISTER 4-13: SBTxWRy: SYSTEM BUS TARGET x REGION y WRITE PERMISSIONS

REGISTER (x = 0-13; y = 0-8)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-1
7:0
GROUP3 GROUP2 GROUP1 GROUP0
Legend:

bit 3 Group3: Group 3 Write Permissions bits
1 = Privilege Group 3 has write permission
0 = Privilege Group 3 does not have write permission
more information.

NOTES:

5.0 FLASH PROGRAM MEMORY RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP
Note: This data sheet summarizes the features techniques is available in Section 52. Flash
of the PIC32MZ Graphics (DA) Family of Program Memory with Support for Live Update
devices. It is not intended to be a (DS60001193) in the PIC32 Family Reference
comprehensive reference source. To Manual.
complement the information in this data EJTAG is performed using the EJTAG port of the
sheet, refer to Section 52. Flash device and an EJTAG capable programmer.
Program Memory with Support for Live
Update (DS60001193), which is ICSP is performed using a serial data connection to the
available from the Documentation > device and allows much faster programming times than
Reference Manual section of the RTSP.
Microchip PIC32 web site The EJTAG and ICSP methods are described in the
(www.microchip.com/pic32). PIC32 Flash Programming Specification
(DS60001145), which is available for download from
PIC32MZ DA devices contain an internal Flash the Microchip website.
program memory for executing user code, which
includes the following features: Note: In PIC32MZ DA devices, the Flash page
size is 16 KB (4K IW) and the row size is
Two Flash banks for live update support
2 KB (512 IW).
Dual boot support
Write protection for program and Boot Flash
ECC support
There are three methods by which the user can
program this memory:
Run-Time Self-Programming (RTSP)
EJTAG Programming
In-Circuit Serial Programming (ICSP)

DS60001361E-page 106
5.1 Flash Control Registers

TABLE 5-1: FLASH CONTROLLER REGISTER MAP
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0600 NVMCON(1)
15:0 WR WREN WRERR LVDERR PFSWAP BFSWAP NVMOP<3:0> 0000
31:16 0000
0610 NVMKEY NVMKEY<31:0>
15:0 0000
31:16 0000
0620 NVMADDR(1) NVMADDR<31:0>
15:0 0000
31:16 0000
0630 NVMDATA0 NVMDATA0<31:0>
15:0 0000
31:16 0000
15:0 0000
31:16 0000
15:0 0000
31:16 0000
15:0 0000
NVMSRC 31:16 0000
0670 NVMSRCADDR<31:0>
ADDR 15:0 0000
31:16 PWPULOCK PWP<23:16> 8000
0680 NVMPWP(1)
15:0 PWP<15:0> 0000
31:16 0000
0690 NVMBWP(1)
15:0 LBWPULOCK LBWP4 LBWP3 LBWP2 LBWP1 LBWP0 UBWPULOCK UBWP4 UBWP3 UBWP2 UBWP1 UBWP0 9FDF
31:16 00xx
06A0 NVMCON2(1)
15:0 SWAPLOCK<1:0> 0000
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for more
information.
REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0, HC R/W-0 R-0, HS, HC R-0, HS, HC U-0 U-0 U-0 U-0
15:8 (1) (1) (1) (1)
WR WREN WRERR LVDERR
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
PFSWAP(3) BFSWAP(3,4) NVMOP<3:0>
Legend: HS = Hardware Set HC = Cleared by Hardware


bit 15 WR: Write Control bit(1)
This bit cannot be cleared and can be set only when WREN = 1 and the unlock sequence has been
performed.
1 = Initiate a Flash operation
0 = Flash operation is complete or inactive
bit 14 WREN: Write Enable bit(1)
1 = Enable writes to the WR bit and the SWAP bit and disables writes to the NVMOP<3:0> bits
0 = Disable writes to WR bit and the SWAP bit and enables writes to the NVMOP<3:0> bits
bit 13 WRERR: Write Error bit(1)
This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12 LVDERR: Low-Voltage Detect Error bit(1)
This bit can be cleared only by setting the NVMOP<3:0> bits = 0000 and initiating a Flash operation.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
bit 7 PFSWAP: Program Flash Bank Swap Control bit(3)
1 = Program Flash Bank 2 is mapped to the lower mapped region and program Flash Bank 1 is mapped to
the upper mapped region
0 = Program Flash Bank 1 is mapped to the lower mapped region and program Flash Bank 2 is mapped to
the upper mapped region
Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
2: This operation results in a no operation (NOP) when the Dynamic Flash ECC Configuration bits = 00
(FECCCON<1:0> (DVCFG0<9:8>)), which enables ECC at all times. For all other FECCCON<1:0> bit
settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors
if dynamic Flash ECC is enabled (FECCCON<1:0> = 01). Refer to Section 52. Flash Program Memory
with Support for Live Update (DS60001193) for information regarding ECC and Flash programming.
3: This bit can only be modified when the WREN bit = 0, the NVMKEY unlock sequence is satisfied, and the
SWAPLOCK<1:0> bits (NVMCON2<7:6>) are cleared to 0.
4: The BFSWAP value is determined by the values the user programmed Sequence Numbers in each boot
panel.

REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER (CONTINUED)
bit 6 BFSWAP: Boot Flash Bank Swap Control bit(3,4)
1 = Boot Flash Bank 2 is mapped to the lower boot region and Boot Flash Bank 1 is mapped to the upper
mapped region
0 = Boot Flash Bank 1 is mapped to the lower boot region and Boot Flash Bank 2 is mapped to the upper
mapped region
bit 3-0 NVMOP<3:0>: NVM Operation bits
These bits are only writable when WREN = 0.
1111 = Reserved

1000 = Reserved
0111 = Program erase operation: erase all of program Flash memory (all pages must be unprotected,
PWP<23:0> = 0x000000)
0110 = Upper program Flash memory erase operation: erases only the upper mapped region of program
Flash (all pages in that region must be unprotected)
0101 = Lower program Flash memory erase operation: erases only the lower mapped region of program
Flash (all pages in that region must be unprotected)
0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010 = Quad Word (128-bit) program operation: programs the 128-bit Flash word selected by NVMADDR,
if it is not write-protected
0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected(2)
0000 = No operation
Note 1: These bits are only reset by a Power-on Reset (POR) and are not affected by other reset sources.
2: This operation results in a no operation (NOP) when the Dynamic Flash ECC Configuration bits = 00
(FECCCON<1:0> (DVCFG0<9:8>)), which enables ECC at all times. For all other FECCCON<1:0> bit
settings, this command will execute, but will not write the ECC bits for the word and can cause DED errors
if dynamic Flash ECC is enabled (FECCCON<1:0> = 01). Refer to Section 52. Flash Program Memory
with Support for Live Update (DS60001193) for information regarding ECC and Flash programming.
3: This bit can only be modified when the WREN bit = 0, the NVMKEY unlock sequence is satisfied, and the
SWAPLOCK<1:0> bits (NVMCON2<7:6>) are cleared to 0.
4: The BFSWAP value is determined by the values the user programmed Sequence Numbers in each boot
panel.

REGISTER 5-2: NVMKEY: PROGRAMMING UNLOCK REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
31:24
NVMKEY<31:24>
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
23:16
NVMKEY<23:16>
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15:8
NVMKEY<15:8>
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
7:0
NVMKEY<7:0>
Legend:
bit 31-0 NVMKEY<31:0>: Unlock Register bits

These bits are write-only, and read as 0 on any read
Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.
REGISTER 5-3: NVMADDR: FLASH ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
NVMADDR<31:24>(1)
23:16
NVMADDR<23:16>(1)
15:8
NVMADDR<15:8>(1)
7:0
NVMADDR<7:0>(1)
Legend:
bit 31-0 NVMADDR<31:0>: Flash Address bits(1)
NVMOP<3:0>
Flash Address Bits (NVMADDR<31:0>)
Selection
Page Erase Address identifies the page to erase (NVMADDR<13:0> are ignored).
Row Program Address identifies the row to program (NVMADDR<11:0> are ignored).
Word Program Address identifies the word to program (NVMADDR<1:0> are ignored).
Quad Word Program Address identifies the quad word (128-bit) to program (NVMADDR<3:0> bits are
ignored).
Note 1: For all other NVMOP<3:0> bit settings, the Flash address is ignored.
Note: The bits in this register are only reset by a Power-on Reset (POR) and are not affected by other reset
sources.

REGISTER 5-4: NVMDATAx: FLASH DATA REGISTER (x = 0-3)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
NVMDATA<31:24>
23:16
NVMDATA<23:16>
15:8
NVMDATA<15:8>
7:0
NVMDATA<7:0>
Legend:
bit 31-0 NVMDATA<31:0>: Flash Data bits

Word Program: Writes NVMDATA0 to the target Flash address defined in NVMADDR
Quad Word Program: Writes NVMDATA3:NVMDATA2:NVMDATA1:NVMDATA0 to the target Flash address
defined in NVMADDR. NVMDATA0 contains the Least Significant Instruction Word.
sources.
REGISTER 5-5: NVMSRCADDR: SOURCE DATA ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
NVMSRCADDR<31:24>
23:16
NVMSRCADDR<23:16>
15:8
NVMSRCADDR<15:8>
7:0
NVMSRCADDR<7:0>
Legend:
bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits

The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits
(NVMCON<3:0>) are set to perform row programming.
sources.

REGISTER 5-6: NVMPWP: PROGRAM FLASH WRITE-PROTECT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
PWPULOCK
23:16
PWP<23:16>
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
PWP<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
PWP<7:0>
Legend:
bit 31 PWPULOCK: Program Flash Memory Page Write-protect Unlock bit

1 = Register is not locked and can be modified
0 = Register is locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 23-0 PWP<23:0>: Flash Program Write-protect (Page) Address bits
Physical memory below address 0x1Dxxxxxx is write protected, where xxxxxx is specified by PWP<23:0>.
When PWP<23:0> has a value of 0, write protection is disabled for the entire program Flash. If the specified
address falls within the page, the entire page and all pages below the current page will be protected.
Note: The bits in this register are only writable when the NVMKEY unlock sequence is followed.

REGISTER 5-7: NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
15:8
LBWPULOCK LBWP4(1) LBWP3(1) LBWP2(1) LBWP1(1) LBWP0(1)
R/W-1 r-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
7:0 (1) (1) (1) (1)
UBWPULOCK UBWP4 UBWP3 UBWP2 UBWP1 UBWP0(1)

bit 15 LBWPULOCK: Lower Boot Alias Write-protect Unlock bit
1 = LBWPx bits are not locked and can be modified
0 = LBWPx bits are locked and cannot be modified
This bit is only clearable and cannot be set except by any reset.
bit 12 LBWP4: Lower Boot Alias Page 4 Write-protect bit(1)
1 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF enabled
0 = Write protection for physical address 0x01FC10000 through 0x1FC13FFF disabled
1 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF enabled
0 = Write protection for physical address 0x01FC0C000 through 0x1FC0FFFF disabled
1 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF enabled
0 = Write protection for physical address 0x01FC08000 through 0x1FC0BFFF disabled
bit 7 UBWPULOCK: Upper Boot Alias Write-protect Unlock bit
1 = UBWPx bits are not locked and can be modified
0 = UBWPx bits are locked and cannot be modified
This bit is only user-clearable and cannot be set except by any reset.
bit 6 Reserved: This bit is reserved for use by development tools
Note 1: These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock
bit (LBWPULOCK or UBWPULOCK) is set.

REGISTER 5-7: NVMBWP: FLASH BOOT (PAGE) WRITE-PROTECT REGISTER
bit 4 UBWP4: Upper Boot Alias Page 4 Write-protect bit(1)
1 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF enabled
0 = Write protection for physical address 0x01FC2C000 through 0x1FC2FFFF disabled
1 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF enabled
0 = Write protection for physical address 0x01FC28000 through 0x1FC2BFFF disabled
Note 1: These bits are only available when the NVMKEY unlock sequence is performed and the associated Lock
bit (LBWPULOCK or UBWPULOCK) is set.

REGISTER 5-8: NVMCON2: PROGRAMMING CONTROL REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0 (1)
SWAPLOCK<1:0>
Legend:

bit 7-6 SWAPLOCK<1:0>: Program Flash Memory Page Write-protect Unlock bits(1)
11 = PFSWAP and BFSWP in the NVMCON register are Not Writable and SWAPLOCK<1:0> is Not Writable
10 = PFSWAP and BFSWP in the NVMCON register are Not Writable and SWAPLOCK<1:0> is Writable
01 = PFSWAP and BFSWP in the NVMCON register are Not Writable and SWAPLOCK<1:0> is Writable
00 = PFSWAP and BFSWP in the NVMCON register are Writable and SWAPLOCK<1:0> is Writable
Note 1: These bits can only be modified when the NVMKEY unlock sequence is satisfied and the
SWAPLOCK<1:0> bits 11. If the SWAPLOCK<1:0> bits == 11, only a Reset can clear these bits.

6.0 RESETS The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
Note: This data sheet summarizes the features device Reset sources are as follows:
of the PIC32MZ Graphics (DA) Family of Power-on Reset (POR)
Brown-out Reset (BOR)
comprehensive reference source. To
complement the information in this data VBAT Power-on Reset (VBPOR)
sheet, refer to Section 7. Resets High Voltage Detect Reset (HVD1V8R) on
(DS60001118), which is available from the VDDR1V8
Documentation > Reference Manual Master Clear Reset pin (MCLR)
section of the Microchip PIC32 web site Software Reset (SWR)
Watchdog Timer Reset (WDTR)
Configuration Mismatch Reset (CMR)
Deadman Timer Reset (DMTR)
All types of device Reset will set a corresponding
Status bit in the RCON register (see Register 6-1) to
indicate the type of reset.
A simplified block diagram of the Reset module is
illustrated in Figure 6-1.
FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM
MCLR
MCLR
Glitch Filter
Sleep or Idle DMTR/WDTR

WDT NMI
Time-out Time-out
DMT
Time-out
Voltage Regulator Enabled
Power-up POR(1)
VDDIO Timer
VDDIO Rise
SYSRST
Detect
VDDCORE
POR
Brown-out BOR(1)
Reset
Configuration
CMR
Mismatch
Reset
SWR
Software Reset
High-Voltage HVD1V8R(1)
Detect
VDDR1V8
VBAT VBPOR(1)
Monitor
VBAT
Note 1: Refer to Table 44-4 for various RESET specifications.

DS60001361E-page 116
6.1 Reset Control Registers

TABLE 6-1: RESETS REGISTER MAP
Bits
Virtual Address
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 HVD1V8R BCFGERR BCFGFAIL VBPOR VBAT C802

1240 RCON
15:0 DPSLP CMR EXTR SWR DMTO WDTO SLEEP IDLE BOR POR 0003
31:16 0000
1250 RSWRST
15:0 SWRST 0000
31:16 DMTO WDTO SWNMI GNMI HLVD CF WDTS 0000
1260 RNMICON
15:0 NMICNT<15:0> 0000
31:16 0000
1270 PWRCON
15:0 VREGS 0000
Note 1: All registers have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for more
information.
REGISTER 6-1: RCON: RESET CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 R/W-0, HS U-0 RW-0, HC R/W-0, HC U-0 U-0
31:24
HVD1V8R BCFGERR BCFGFAIL
U-0 U-0 U-0 U-0 U-0 U-0 R/W-1, HS R/W-1, HS
23:16
VBPOR VBAT
U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS U-0
15:8
DPSLP(1) CMR
R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS
7:0 (1) (1)
EXTR SWR DMTO WDTO SLEEP IDLE BOR POR
Legend: HS = Hardware Set HC = Hardware Cleared


bit 29 HVD1V8R: VDDR1V8 (DDR2) High Voltage Detect Flag bit
1 = A high voltage condition on the VDDR1V8 voltage has occurred
0 = A high voltage condition on the VDDR1V8 voltage has not occurred
bit Unimplemented: Read as 0
bit 27 BCFGERR: Primary Configuration Registers Error Flag bit
1 = An error occurred during a read of the primary configuration registers
0 = No error occurred during a read of the primary configuration registers
bit 26 BCFGFAIL: Primary/Secondary Configuration Registers Error Flag bit
1 = An error occurred during a read of the primary and alternate configuration registers
0 = No error occurred during a read of the primary and alternate configuration registers
bit 17 VBPOR: VBPOR Mode Flag bit
1 = A VBAT domain POR has occurred
0 = A VBAT domain POR has not occurred
bit 16 VBAT: VBAT Mode Flag bit
1 = A POR exit from VBAT has occurred (a true POR must be established with the valid VBAT voltage on the
VBAT pin)
0 = A POR exit from VBAT has not occurred
bit 10 DPSLP: Deep Sleep Mode Flag bit(1)
1 = Deep Sleep mode has occurred
0 = Deep Sleep mode has not occurred
bit 9 CMR: Configuration Mismatch Reset Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
bit 7 EXTR: External Reset (MCLR) Pin Flag bit
1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset Flag bit
1 = Software Reset was executed
0 = Software Reset was not executed
bit 5 DMTO: Deadman Timer Time-out Flag bit
1 = A DMT time-out has occurred
0 = A DMT time-out has not occurred
Note 1: User software must clear this bit to view the next detection.

REGISTER 6-1: RCON: RESET CONTROL REGISTER
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred
bit 3 SLEEP: Wake From Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
bit 2 IDLE: Wake From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1 BOR: Brown-out Reset Flag bit(1)
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit(1)
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred
Note 1: User software must clear this bit to view the next detection.

REGISTER 6-2: RSWRST: SOFTWARE RESET REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC
7:0
SWRST(1,2)
Legend: HC = Hardware Cleared


bit 0 SWRST: Software Reset Trigger bit(1,2)
1 = Enable software Reset event
0 = No effect
Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to the
Section 42. Oscillators with Enhanced PLL (DS60001250) in the PIC32 Family Reference Manual
for details.
2: Once this bit is set, any read of the RSWRST register will cause a reset to occur.

REGISTER 6-3: RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
31:24
DMTO WDTO
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
SWNMI GNMI HLVD CF WDTS
15:8
NMICNT<15:8>
7:0
NMICNT<7:0>
Legend:

bit 25 DMTO: Deadman Timer Time-out Flag bit
1 = DMT time-out has occurred and caused a NMI
0 = DMT time-out has not occurred
Setting this bit will cause a DMT NMI event, and NMICNT will begin counting.
bit 24 WDTO: Watchdog Timer Time-Out Flag bit
1 = WDT time-out has occurred and caused a NMI
0 = WDT time-out has not occurred
Setting this bit will cause a WDT NMI event, and MNICNT will begin counting.
bit 23 SWNMI: Software NMI Trigger.
1 = An NMI will be generated
0 = An NMI will not be generated
bit 19 GNMI: General NMI bit
1 = A general NMI event has been detected or a user-initiated NMI event has occurred
0 = A general NMI event has not been detected
Setting GNMI to a 1 causes a user-initiated NMI event. This bit is also set by writing 0x4E to the
NMIKEY<7:0> (INTCON<31:24>) bits.
bit 18 HLVD: High/Low-Voltage Detect bit
1 = HLVD has detected a low-voltage condition and caused an NMI
0 = HLVD has not detected a low-voltage condition
bit 17 CF: Clock Fail Detect bit
1 = FSCM has detected clock failure and caused an NMI
0 = FSCM has not detected clock failure
Setting this bit will cause a a CF NMI event, but will not cause a clock switch to the BFRC.
bit 16 WDTS: Watchdog Timer Time-out in Sleep Mode Flag bit
1 = WDT time-out has occurred during Sleep mode and caused a wake-up from sleep
0 = WDT time-out has not occurred during Sleep mode
Setting this bit will cause a WDT NMI.
Note 1: If a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is cleared
before this counter reaches 0, no device Reset is asserted. This NMI reset counter is only applicable to
these two specific NMI events.
Note: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
42. Oscillators with Enhanced PLL (DS60001250) in the PIC32 Family Reference Manual for details.

REGISTER 6-3: RNMICON: NON-MASKABLE INTERRUPT (NMI) CONTROL REGISTER
bit 15-0 NMICNT<15:0>: NMI Reset Counter Value bits
These bits specify the reload value used by the NMI reset counter.
1111111111111111-0000000000000001 = Number of SYSCLK cycles before a device Reset occurs(1)
0000000000000000 = No delay between NMI assertion and device Reset event
Note 1: If a Watchdog Timer NMI event (when not in Sleep mode) or a Deadman Timer NMI event is cleared
before this counter reaches 0, no device Reset is asserted. This NMI reset counter is only applicable to
these two specific NMI events.
Note: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
42. Oscillators with Enhanced PLL (DS60001250) in the PIC32 Family Reference Manual for details.

REGISTER 6-4: PWRCON: POWER CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
7:0
VREGS
Legend:

bit 0 VREGS: Voltage Regulator Stand-by Enable bit
1 = Voltage regulator will remain active during Sleep
0 = Voltage regulator will go to Stand-by mode during Sleep

7.0 CPU EXCEPTIONS AND The CPU handles interrupt events as part of the excep-
tion handling mechanism, which is described in
INTERRUPT CONTROLLER Section 7.1 CPU Exceptions.
Note: This data sheet summarizes the features The Interrupt Controller module includes the following
of the PIC32MZ Graphics (DA) Family of features:
Up to 210 interrupt sources and vectors with
dedicated programmable offsets, eliminating the
need for redirection
sheet, refer to Section 8. Interrupt Con-
troller (DS60001108) and Section 50. Single and multi-vector mode operations
CPU for Devices with MIPS32 Five external interrupts with edge polarity control
microAptiv and M-Class Cores Interrupt proximity timer
(DS60001192), which are available from Seven user-selectable priority levels for each
the Documentation > Reference Manual vector
section of the Microchip PIC32 web site Four user-selectable sub-priority levels within
(www.microchip.com/pic32). each priority
PIC32MZ DA devices generate interrupt requests in Seven shadow register sets that can be used for any
response to interrupt events from peripheral modules. priority level, eliminating software context switch and
The Interrupt Controller module exists outside of the reducing interrupt latency
CPU and prioritizes the interrupt events before Software can generate any interrupt
presenting them to the CPU. Figure 7-1 shows the block diagram for the Interrupt
Controller and CPU exceptions.
FIGURE 7-1: CPU EXCEPTIONS AND INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM
Vector Number and Offset

Interrupt Requests
Priority Level
Interrupt Controller CPU Core
(Exception Handling)
Shadow Set Number
SYSCLK

DS60001361E-page 124
7.1 CPU Exceptions

CPU coprocessor 0 contains the logic for identifying and managing exceptions.
Exceptions can be caused by a variety of sources, including boundary cases in
data, external events or program errors. Table 7-1 lists the exception types in
order of priority.
TABLE 7-1: MIPS32 microAptiv MICROPROCESSOR CORE EXCEPTION TYPES

Exception Type
Status Debug Bits
(In Order of Description Branches to EXCCODE XC32 Function Name
Bits Set Set
Priority)
Highest Priority
Reset Assertion MCLR or a Power-on Reset (POR). 0xBFC0_0000 BEV, ERL _on_reset
Soft Reset Assertion of a software Reset. 0xBFC0_0000 BEV, SR, _on_reset
ERL
DSS EJTAG debug single step. 0xBFC0_0480 DSS
DINT EJTAG debug interrupt. Caused by the assertion of 0xBFC0_0480 DINT
the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
NMI Assertion of NMI signal. 0xBFC0_0000 BEV, NMI, _nmi_handler
ERL
Machine Check TLB write that conflicts with an existing entry. EBASE+0x180 MCHECK, 0x18 _general_exception_handler
EXL
Interrupt Assertion of unmasked hardware or software inter- See Table 7-2. IPL<2:0> 0x00 See Table 7-2.
rupt signal.
Deferred Watch Deferred watch (unmasked by K|DM=>!(K|DM) EBASE+0x180 WP, EXL 0x17 _general_exception_handler
transition).
DIB EJTAG debug hardware instruction break matched. 0xBFC0_0480 DIB
WATCH A reference to an address that is in one of the EBASE+0x180 EXL 0x17 _general_exception_handler
Watch registers (fetch).
AdEL Fetch address alignment error. Fetch reference to EBASE+0x180 EXL 0x04 _general_exception_handler
protected address.
TLBL Fetch TLB miss or fetch TLB hit to page with V = 0. EBASE if Status.EXL = 0 0x02
EBASE+0x180 if 0x02 _general_exception_handler
Status.EXL == 1
TLBL Execute- An instruction fetch matched a valid TLB entry that EBASE+0x180 EXL 0x14 _general_exception_handler
Inhibit had the XI bit set.
IBE Instruction fetch bus error. EBASE+0x180 EXL 0x06 _general_exception_handler
TABLE 7-1: MIPS32 microAptiv MICROPROCESSOR CORE EXCEPTION TYPES (CONTINUED)
Exception Type
Status Debug Bits
(In Order of Description Branches to EXCCODE XC32 Function Name
Bits Set Set
Priority)
Instruction An instruction could not be completed because it EBASE+0x180 EXL 0x0A or _general_exception_handler
Validity was not allowed to access the required resources 0x0B
Exceptions (Coprocessor Unusable) or was illegal (Reserved
Instruction). If both exceptions occur on the same
instruction, the Coprocessor Unusable Exception
takes priority over the Reserved Instruction
Exception.
Execute An instruction-based exception occurred: Integer EBASE+0x180 EXL 0x08-0x0C _general_exception_handler
Exception overflow, trap, system call, breakpoint, floating
point, or DSP ASE state disabled exception.
Tr Execution of a trap (when trap condition is true). EBASE+0x180 EXL 0x0D _general_exception_handler
DDBL/DDBS EJTAG Data Address Break (address only) or 0xBFC0_0480 DDBL or

EJTAG data value break on store (address + DDBS
value).
WATCH A reference to an address that is in one of the EBASE+0x180 EXL 0x17 _general_exception_handler
Watch registers (data).
AdEL Load address alignment error. User mode load EBASE+0x180 EXL 0x04 _general_exception_handler
reference to kernel address.
AdES Store address alignment error. User mode store to EBASE+0x180 EXL 0x05 _general_exception_handler
kernel address.
TLBL Load TLB miss or load TLB hit to page with V = 0. EBASE+0x180 EXL 0x02 _general_exception_handler
TLBS Store TLB miss or store TLB hit to page with V = 0. EBASE+0x180 EXL 0x03 _general_exception_handler
DBE Load or store bus error. EBASE+0x180 EXL 0x07 _general_exception_handler
DDBL EJTAG data hardware breakpoint matched in load 0xBFC0_0480 DDBL
data compare.
CBrk EJTAG complex breakpoint. 0xBFC0_0480 DIBIMPR,
DDBLIMPR,
and/or
DDBSIMPR
Lowest Priority
DS60001361E-page 125
DS60001361E-page 126
7.2 Interrupts For details on the Variable Offset feature, refer to 8.5.2 Variable Offset in

Section 8. Interrupt Controller (DS60001108) of the PIC32 Family
The PIC32MZ DA family uses variable offsets for vector spacing. This allows Reference Manual.
the interrupt vector spacing to be configured according to application needs. A
unique interrupt vector offset can be set for each vector using its associated Table 7-2 provides the Interrupt IRQ, vector and bit location information.
OFFx register.
TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION
IRQ Interrupt Bit Location Persistent
Interrupt Source(1) XC32 Vector Name Vector #
# Flag Enable Priority Sub-priority Interrupt
Highest Natural Order Priority

Core Timer Interrupt _CORE_TIMER_VECTOR 0 OFF000<17:1> IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0> No
Core Software Interrupt 0 _CORE_SOFTWARE_0_VECTOR 1 OFF001<17:1> IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8> No
Core Software Interrupt 1 _CORE_SOFTWARE_1_VECTOR 2 OFF002<17:1> IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16> No
External Interrupt 0 _EXTERNAL_0_VECTOR 3 OFF003<17:1> IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24> No
Timer1 _TIMER_1_VECTOR 4 OFF004<17:1> IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0> No
Input Capture 1 Error _INPUT_CAPTURE_1_ERROR_VECTOR 5 OFF005<17:1> IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8> Yes
Input Capture 1 _INPUT_CAPTURE_1_VECTOR 6 OFF006<17:1> IFS0<6> IEC0<6> IPC1<20:18> IPC1<17:16> Yes
Output Compare 1 _OUTPUT_COMPARE_1_VECTOR 7 OFF007<17:1> IFS0<7> IEC0<7> IPC1<28:26> IPC1<25:24> No

Note 1: Not all interrupt sources are available on all devices. See the Family Features tables (Table 1 through Table 2) for the list of available peripherals.
2: Upon Reset, the GLCD interrupt (both HSYNC and VSYNC) are persistent. However, through the IRQCON bit (GLCDINT<31>), the type of interrupt can be
changed to non-persistent.
TABLE 7-2: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)



ADC Global Interrupt _ADC_VECTOR 44 OFF044<17:1> IFS1<12> IEC1<12> IPC11<4:2> IPC11<1:0> Yes
ADC FIFO Interrupt _ADC_FIFO_VECTOR 45 OFF045<17:1> IFS1<13> IEC1<13> IPC11<12:10> IPC11<9:8> Yes
ADC Digital Comparator 1 _ADC_DC1_VECTOR 46 OFF046<17:1> IFS1<14> IEC1<14> IPC11<20:18> IPC11<17:16> Yes
DS60001361E-page 127
DS60001361E-page 128

ADC Digital Filter 1 _ADC_DF1_VECTOR 52 OFF052<17:1> IFS1<20> IEC1<20> IPC13<4:2> IPC13<1:0> Yes
ADC Fault _ADC_FAULT_VECTOR 58 OFF058<17:1> IFS1<26> IEC1<26> IPC14<20:18> IPC14<17:16> Yes
ADC Data 0 _ADC_DATA0_VECTOR 59 OFF059<17:1> IFS1<27> IEC1<27> IPC14<28:26> IPC14<25:24> Yes




USB Suspend/Resume Event _USB1_SR_VECTOR 103 OFF103<17:1> IFS3<7> IEC3<7> IPC25<28:26> IPC25<25:24> No
Core Performance Counter Interrupt _CORE_PERF_COUNT_VECTOR 104 OFF104<17:1> IFS3<8> IEC3<8> IPC26<4:2> IPC26<1:0> No
Core Fast Debug Channel Interrupt _CORE_FAST_DEBUG_CHAN_VECTOR 105 OFF105<17:1> IFS3<9> IEC3<9> IPC26<12:10> IPC26<9:8> Yes
System Bus Protection Violation _SYSTEM_BUS_PROTECTION_VECTOR 106 OFF106<17:1> IFS3<10> IEC3<10> IPC26<20:18> IPC26<17:16> Yes
DS60001361E-page 129
Crypto Engine Event _CRYPTO_VECTOR 107 OFF107<17:1> IFS3<11> IEC3<11> IPC26<28:26> IPC26<25:24> Yes
Reserved 108
SPI1 Fault _SPI1_FAULT_VECTOR 109 OFF109<17:1> IFS3<13> IEC3<13> IPC27<12:10> IPC27<9:8> Yes
DS60001361E-page 130

SPI1 Receive Done _SPI1_RX_VECTOR 110 OFF110<17:1> IFS3<14> IEC3<14> IPC27<20:18> IPC27<17:16> Yes
SPI1 Transfer Done _SPI1_TX_VECTOR 111 OFF111<17:1> IFS3<15> IEC3<15> IPC27<28:26> IPC27<25:24> Yes
UART1 Fault _UART1_FAULT_VECTOR 112 OFF112<17:1> IFS3<16> IEC3<16> IPC28<4:2> IPC28<1:0> Yes
UART1 Receive Done _UART1_RX_VECTOR 113 OFF113<17:1> IFS3<17> IEC3<17> IPC28<12:10> IPC28<9:8> Yes
UART1 Transfer Done _UART1_TX_VECTOR 114 OFF114<17:1> IFS3<18> IEC3<18> IPC28<20:18> IPC28<17:16> Yes
I2C1 Bus Collision Event _I2C1_BUS_VECTOR 115 OFF115<17:1> IFS3<19> IEC3<19> IPC28<28:26> IPC28<25:24> Yes
I2C1 Slave Event _I2C1_SLAVE_VECTOR 116 OFF116<17:1> IFS3<20> IEC3<20> IPC29<4:2> IPC29<1:0> Yes
I2C1 Master Event _I2C1_MASTER_VECTOR 117 OFF117<17:1> IFS3<21> IEC3<21> IPC29<12:10> IPC29<9:8> Yes
PORTA Input Change Interrupt _CHANGE_NOTICE_A_VECTOR 118 OFF118<17:1> IFS3<22> IEC3<22> IPC29<20:18> IPC29<17:16> Yes
PORTB Input Change Interrupt _CHANGE_NOTICE_B_VECTOR 119 OFF119<17:1> IFS3<23> IEC3<23> IPC29<28:26> IPC29<25:24> Yes
PORTC Input Change Interrupt _CHANGE_NOTICE_C_VECTOR 120 OFF120<17:1> IFS3<24> IEC3<24> IPC30<4:2> IPC30<1:0> Yes
PORTD Input Change Interrupt _CHANGE_NOTICE_D_VECTOR 121 OFF121<17:1> IFS3<25> IEC3<25> IPC30<12:10> IPC30<9:8> Yes
PORTE Input Change Interrupt _CHANGE_NOTICE_E_VECTOR 122 OFF122<17:1> IFS3<26> IEC3<26> IPC30<20:18> IPC30<17:16> Yes
PORTF Input Change Interrupt _CHANGE_NOTICE_F_VECTOR 123 OFF123<17:1> IFS3<27> IEC3<27> IPC30<28:26> IPC30<25:24> Yes
PORTG Input Change Interrupt _CHANGE_NOTICE_G_VECTOR 124 OFF124<17:1> IFS3<28> IEC3<28> IPC31<4:2> IPC31<1:0> Yes
PORTH Input Change Interrupt _CHANGE_NOTICE_H_VECTOR 125 OFF125<17:1> IFS3<29> IEC3<29> IPC31<12:10> IPC31<9:8> Yes
PORTJ Input Change Interrupt _CHANGE_NOTICE_J_VECTOR 126 OFF126<17:1> IFS3<30> IEC3<30> IPC31<20:18> IPC31<17:16> Yes
PORTK Input Change Interrupt _CHANGE_NOTICE_K_VECTOR 127 OFF127<17:1> IFS3<31> IEC3<31> IPC31<28:26> IPC31<25:24> Yes
Parallel Master Port _PMP_VECTOR 128 OFF128<17:1> IFS4<0> IEC4<0> IPC32<4:2> IPC32<1:0> Yes
Parallel Master Port Error _PMP_ERROR_VECTOR 129 OFF129<17:1> IFS4<1> IEC4<1> IPC32<12:10> IPC32<9:8> Yes
Comparator 1 Interrupt _COMPARATOR_1_VECTOR 130 OFF130<17:1> IFS4<2> IEC4<2> IPC32<20:18> IPC32<17:16> No
Comparator 2 Interrupt _COMPARATOR_2_VECTOR 131 OFF131<17:1> IFS4<3> IEC4<3> IPC32<28:26> IPC32<25:24> No
USB General Event _USB1_VECTOR 132 OFF132<17:1> IFS4<4> IEC4<4> IPC33<4:2> IPC33<1:0> Yes
USB DMA Event _USB1_DMA_VECTOR 133 OFF133<17:1> IFS4<5> IEC4<5> IPC33<12:10> IPC33<9:8> Yes
DMA Channel 0 _DMA0_VECTOR 134 OFF134<17:1> IFS4<6> IEC4<6> IPC33<20:18> IPC33<17:16> No



Control Area Network 1 _CAN1_VECTOR 151 OFF151<17:1> IFS4<23> IEC4<23> IPC37<28:26> IPC37<25:24> Yes
Control Area Network 2 _CAN2_VECTOR 152 OFF152<17:1> IFS4<24> IEC4<24> IPC38<4:2> IPC38<1:0> Yes
Ethernet Interrupt _ETHERNET_VECTOR 153 OFF153<17:1> IFS4<25> IEC4<25> IPC38<12:10> IPC38<9:8> Yes
DS60001361E-page 131
Real Time Clock _RTCC_VECTOR 166 OFF166<17:1> IFS5<6> IEC5<6> IPC41<20:18> IPC41<17:16> No
Flash Control Event _FLASH_CONTROL_VECTOR 167 OFF167<17:1> IFS5<7> IEC5<7> IPC41<28:26> IPC41<25:24> No
DS60001361E-page 132

Prefetch Module SEC Event _PREFETCH_VECTOR 168 OFF168<17:1> IFS5<8> IEC5<8> IPC42<4:2> IPC42<1:0> Yes
SQI1 Event _SQI1_VECTOR 169 OFF169<17:1> IFS5<9> IEC5<9> IPC42<12:10> IPC42<9:8> Yes
SDHC Interrupt _SDHC_VECTOR 191 OFF191<17:1> IFS5<31> IEC5<31> IPC47<28:26> IPC47<25:24> Yes
GLCD Interrupt _GLCD_VECTOR 192 OFF192<17:1> IFS6<0> IEC6<0> IPC48<4:2> IPC48<1:0> Yes/No(2)
GPU Interrupt _GPU_VECTOR 193 OFF193<17:1> IFS6<1> IEC6<1> IPC48<12:10> IPC48<9:8> Yes
Reserved
CTMU Interrupt _CTMU_VECTOR 195 OFF195<17:1> IFS6<3> IEC6<3> IPC48<28:26> IPC48<25:24> Yes
ADC End of Scan _ADC_EOS_VECTOR 196 OFF196<17:1> IFS6<4> IEC6<4> IPC49<4:2> IPC49<1:0> Yes

ADC Analog Circuit Ready _ADC_ARDY_VECTOR 197 OFF197<17:1> IFS6<5> IEC6<5> IPC49<12:10> IPC49<9:8> Yes
ADC Update Ready _ADC_URDY_VECTOR 198 OFF198<17:1> IFS6<6> IE6<6> IPC49<20:18> IPC49<17:16> Yes
ADC0 Early Interrupt _ADC0_EARLY_VECTOR 199 OFF199<17:1> IFS6<7> IEC6<7> IPC49<28:26> IPC49<25:24> Yes
Reserved
ADC Group Early Interrupt Request _ADC_EARLY_VECTOR 205 OFF205<17:1> IFS6<13> IEC6<13> IPC51<12:10> IPC51<9:8> Yes

ADC0 Warm Interrupt _ADC0_WARM_VECTOR 207 OFF207<17:1> IFS6<15> IEC6<15> IPC51<28:26> IPC51<25:24> Yes
Reserved
Reserved
MPLL Fault Interrupt _MPLL_FAULT_VECTOR 215 OFF215<17:1> IFS6<23> IEC6<23> IPC53<28:26> IPC53<25:24> Yes
Lowest Natural Order Priority
DS60001361E-page 133
DS60001361E-page 134
7.3 Interrupt Control Registers

TABLE 7-3: INTERRUPT REGISTER MAP
Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 NMIKEY<7:0> 0000

0000 INTCON
15:0 MVEC TPC<2:0> INT4EP INT3EP INT2EP INT1EP INT0EP 0000
31:16 PRI7SS<3:0> PRI6SS<3:0> PRI5SS<3:0> PRI4SS<3:0> 0000
0010 PRISS
15:0 PRI3SS<3:0> PRI2SS<3:0> PRI1SS<3:0> SS0 0000
INT- 31:16 0000
0020
STAT 15:0 SRIPL<2:0> SIRQ<7:0> 0000
31:16 0000
0030 IPTMR IPTMR<31:0>
15:0 0000
31:16 OC6IF IC6IF IC6EIF T6IF OC5IF IC5IF IC5EIF T5IF INT4IF OC4IF IC4IF IC4EIF T4IF INT3IF OC3IF IC3IF 0000
0040 IFS0
15:0 IC3EIF T3IF INT2IF OC2IF IC2IF IC2EIF T2IF INT1IF OC1IF IC1IF IC1EIF T1IF INT0IF CS1IF CS0IF CTIF 0000
31:16 ADCD4IF ADCD3IF ADCD2IF ADCD1IF ADCD0IF ADCFLTIF ADCDF6IF ADCDF5IF ADCDF4IF ADCDF3IF ADCDF21IF ADCDF1IF ADCDC6IF ADCDC5IF ADCDC4IF ADCDC3IF 0000
0050 IFS1
15:0 ADCDC2IF ADCDC1IF ADCFIFOIF ADCIF OC9IF IC9IF IC9EIF T9IF OC8IF IC8IF IC8EIF T8IF OC7IF IC7IF IC7EIF T7IF 0000
31:16 ADCD36IF ADCD35IF ADCD34IF ADCD33IF ADCD32IF ADCD31IF ADCD30IF ADCD29IF ADCD28IF ADCD27IF ADCD26IF ADCD25IF ADCD24IF ADCD23IF ADCD22IF ADCD21IF 0000
0060 IFS2
15:0 ADCD20IF ADCD19IF ADCD18IF ADCD17IF ADCD16IF ADCD15IF ADCD14IF ADCD13IF ADCD12IF ADCD11IF ADCD10IF ADCD9IF ADCD8IF ADCD7IF ADCD6IF ADCD5IF 0000
31:16 CNKIF CNJIF CNHIF CNGIF CNFIF CNEIF CNDIF CNCIF CNBIF CNAIF I2C1MIF I2C1SIF I2C1BIF U1TXIF U1RXIF U1EIF 0000
0070 IFS3
15:0 SPI1TXIF SPI1RXIF SPI1EIF CRPTIF(2) SBIF CFDCIF CPCIF USBSRIF ADCD43IF ADCD42IF ADCD41IF ADCD40IF ADCD39IF ADCD38IF ADCD37IF 0000
31:16 U3TXIF U3RXIF U3EIF SPI3TXIF SPI3RXIF SPI3EIF ETHIF CAN2IF CAN1IF I2C2MIF I2C2SIF I2C2BIF U2TXIF U2RXIF U2EIF SPI2TXIF 0000
0080 IFS4
15:0 SPI2RXIF SPI2EIF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF DMA0IF USBDMAIF USBIF CMP2IF CMP1IF PMPEIF PMPIF 0000
31:16 SDHCIF U6TXIF U6RXIF U6EIF SPI6TX SPI6RXIF SPI6IF I2C5MIF I2C5SIF I2C5BIF U5TXIF U5RXIF U5EIF SPI5TXIF SPI5RXIF SPI5EIF 0000
0090 IFS5
15:0 I2C4MIF I2C4SIF I2C4BIF U4TXIF U4RXIF U4EIF SQI1IF PREIF FCEIF RTCCIF SPI4TXIF SPI4RXIF SPI4EIF I2C3MIF I2C3SIF I2C3BIF 0000
31:16 MPLLFLTIF ADC7WIF ADC4WIF ADC3WIF ADC2WIF ADC1WIF 0000
00A0 IFS6
15:0 ADC0WIF ADC7EIF ADCGRPIF ADC4EIF ADC3EIF ADC2EIF ADC1EIF ADC0EIF ADCURDYIF ADCARDYIF ADCEOSIF CTMUIF GPUIF GLCDIF 0000
31:16 OC6IE IC6IE IC6EIE T6IE OC5IE IC5IE IC5EIE T5IE INT4IE OC4IE IC4IE IC4EIE T4IE INT3IE OC3IE IC3IE 0000
00C0 IEC0
15:0 IC3EIE T3IE INT2IE OC2IE IC2IE IC2EIE T2IE INT1IE OC1IE IC1IE IC1EIE T1IE INT0IE CS1IE CS0IE CTIE 0000
31:16 ADCD4IE ADCD3IE ADCD2IE ADCD1IE ADCD0IE ADCFLTIE ADCDF6IE ADCDF5IE ADCDF4IE ADCDF3IE ADCDF2IE ADCDF1IE ADCDC6IE ADCDC5IE ADCDC4IE ADCDC3IE 0000
00D0 IEC1
15:0 ADCDC2IE ADCDC1IE ADCFIFOIE ADCIE OC9IE IC9IE IC9EIE T9IE OC8IE IC8IE IC8EIE T8IE OC7IE IC7IE IC7EIE T7IE 0000
31:16 ADCD36IE ADCD35IE ADCD34IE ADCD33IE ADCD32IE ADCD31IE ADCD30IE ADCD29IE ADCD28IE ADCD27IE ADCD26IE ADCD25IE ADCD24IE ADCD23IE ADCD22IE ADCD21IE 0000
00E0 IEC2
15:0 ADCD20IE ADCD19IE ADCD18IE ADCD17IE ADCD16IE ADCD15IE ADCD14IE ADCD13IE ADCD12IE ADCD11IE ADCD10IE ADCD9IE ADCD8IE ADCD7IE ADCD6IE ADCD5IE 0000
31:16 CNKIE CNJIE CNHIE CNGIE CNFIE CNEIE CNDIE CNCIE CNBIE CNAIE I2C1MIE I2C1SIE I2C1BIE U1TXIE U1RXIE U1EIE 0000
00F0 IEC3
15:0 SPI1TXIE SPI1RXIE SPI1EIE CRPTIE(2) SBIE CFDCIE CPCIE USBSRIE ADCD43IE ADCD42IE ADCD41IE ADCD40IE ADCD39IE ADCD38IE ADCD37IE 0000
31:16 U3TXIE U3RXIE U3EIE SPI3TXIE SPI3RXIE SPI3EIE ETHIE CAN2IE CAN1IE I2C2MIE I2C2SIE I2C2BIE U2TXIE U2RXIE U2EIE SPI2TXIE 0000
0100 IEC4
15:0 SPI2RXIE SPI2EIE DMA7IE DMA6IE DMA5IE DMA4IE DMA3IE DMA2IE DMA1IE DMA0IE USBDMAIE USBIE CMP2IE CMP1IE PMPEIE PMPIE 0000
31:16 SDHCIE U6TXIE U6RXIE U6EIE SPI6TXIE SPI6RXIE SPI6IE I2C5MIE I2C5SIE I2C5BIE U5TXIE U5RXIE U5EIE SPI5TXIE SPI5RXIE SPI5EIE 0000
0110 IEC5
15:0 I2C4MIE I2C4SIE I2C4BIE U4TXIE U4RXIE U4EIE SQI1IE PREIE FCEIE RTCCIE SPI4TXIE SPI4RXIE SPI4EIE I2C3MIE I2C3SIE I2C3BIE 0000
31:16 MPLLFLTIE ADC7WIE ADC4WIE ADC3WIE ADC2WIE ADC1WIE 0000
0120 IEC6
15:0 ADC0WIE ADC7EIE ADCGRPIE ADC4EIE ADC3EIE ADC2EIE ADC1EIE ADC0EIE ADCURDYIE ADCARDYIE ADCEOSIE CTMUIE GPUIE GLCDIE 0000
Note 1: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET,
and INV Registers for more information.
2: This bit is only available on devices with a Crypto module.
TABLE 7-3: INTERRUPT REGISTER MAP (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 INT0IP<2:0> INT0IS<1:0> CS1IP<2:0> CS1IS<1:0> 0000

0140 IPC0
15:0 CS0IP<2:0> CS0IS<1:0> CTIP<2:0> CTIS<1:0> 0000
31:16 OC1IP<2:0> OC1IS<1:0> IC1IP<2:0> IC1IS<1:0> 0000
0150 IPC1
15:0 IC1EIP<2:0> IC1EIS<1:0> T1IP<2:0> T1IS<1:0> 0000
31:16 IC2IP<2:0> IC2IS<1:0> IC2EIP<2:0> IC2EIS<1:0> 0000
0160 IPC2
15:0 T2IP<2:0> T2IS<1:0> INT1IP<2:0> INT1IS<1:0> 0000
0170 IPC3
15:0 INT2IP<2:0> INT2IS<1:0> OC2IP<2:0> OC2IS<1:0> 0000
31:16 T4IP<2:0> T4IS<1:0> INT3IP<2:0> INT3IS<1:0> 0000
0180 IPC4
31:16 INT4IP<2:0> INT4IS<1:0> OC4IP<2:0> OC4IS<1:0> 0000
0190 IPC5
15:0 IC4IP<2:0> IC4IS<1:0> IC4EIP<2:0> IC4EIS<1:0> 0000

01A0 IPC6
01B0 IPC7
01C0 IPC8
01D0 IPC9
01E0 IPC10
31:16 ADCDC2IP<2:0> ADCDC2IS<1:0> ADCDC1IP<2:0> ADCDC1IS<1:0> 0000
01F0 IPC11
15:0 ADCFIFOIP<2:0> ADCFIFOIS<1:0> ADCIP<2:0> ADCIS<1:0> 0000
31:16 ADCDC6IP<2:0> ADCDC6S<1:0> ADCDC5IP<2:0> ADCDC5IS<1:0> 0000
0200 IPC12
15:0 ADCDC4IP<2:0> ADCDC4IS<1:0> ADCDC3IP<2:0> ADCDC3IS<1:0> 0000
31:16 ADCDF4IP<2:0> ADCDF4IS<1:0> ADCDF3IP<2:0> ADCDF3IS<1:0> 0000
0210 IPC13
31:16 ADCD0IP<2:0> ADCD0IS<1:0> ADCFLTIP<2:0> ADCFLTIS<1:0> 0000
0220 IPC14
31:16 ADCD4IP<2:0> ADCD4IS<1:0> ADCD3IP<2:0> ADCD3IS<1:0> 0000
0230 IPC15
0240 IPC16
DS60001361E-page 135

0250 IPC17
0260 IPC18
DS60001361E-page 136

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

0270 IPC19
0280 IPC20
0290 IPC21
02A0 IPC22
02B0 IPC23
02C0 IPC24
31:16 USBSRIP<2:0> USBSRIS<1:0> ADCD43IP<2:0> ADCD43IS<1:0> 0000
02D0 IPC25
31:16 CRPTIP<2:0>(2) CRPTIS<1:0>(2) SBIP<2:0> SBIS<1:0> 0000
02E0 IPC26
15:0 CFDCIP<2:0> CFDCIS<1:0> CPCIP<2:0> CPCIS<1:0> 0000
31:16 SPI1TXIP<2:0> SPI1TXIS<1:0> SPI1RXIP<2:0> SPI1RXIS<1:0> 0000
02F0 IPC27
15:0 SPI1EIP<2:0> SPI1EIS<1:0> 0000
31:16 I2C1BIP<2:0> I2C1BIS<1:0> U1TXIP<2:0> U1TXIS<1:0> 0000
0300 IPC28
15:0 U1RXIP<2:0> U1RXIS<1:0> U1EIP<2:0> U1EIS<1:0> 0000
31:16 CNBIP<2:0> CNBIS<1:0> CNAIP<2:0> CNAIS<1:0> 0000
0310 IPC29
15:0 I2C1MIP<2:0> I2C1MIS<1:0> I2C1SIP<2:0> I2C1SIS<1:0> 0000
31:16 CNFIP<2:0> CNFIS<1:0> CNEIP<2:0> CNEIS<1:0> 0000
0320 IPC30
15:0 CNDIP<2:0> CNDIS<1:0> CNCIP<2:0> CNCIS<1:0> 0000
31:16 CNKIP<2:0> CNKIS<1:0> CNJIP<2:0> CNJIS<1:0> 0000
0330 IPC31
15:0 CNHIP<2:0> CNHIS<1:0> CNGIP<2:0> CNGIS<1:0> 0000
31:16 CMP2IP<2:0> CMP2IS<1:0> CMP1IP<2:0> CMP1IS<1:0> 0000
0340 IPC32
15:0 PMPEIP<2:0> PMPEIS<1:0> PMPIP<2:0> PMPIS<1:0> 0000
31:16 DMA1IP<2:0> DMA1IS<1:0> DMA0IP<2:0> DMA0IS<1:0> 0000

0350 IPC33
15:0 USBDMAIP<2:0> USBDMAIS<1:0> USBIP<2:0> USBIS<1:0> 0000
0360 IPC34
31:16 SPI2RXIP<2:0> SPI2RXIS<1:0> SPI2EIP<2:0> SPI2EIS<1:0> 0000
0370 IPC35
31:16 U2TXIP<2:0> U2TXIS<1:0> U2RXIP<2:0> U2RXIS<1:0> 0000
0380 IPC36
15:0 U2EIP<2:0> U2EIS<1:0> SPI2TXIP<2:0> SPI2TXIS<1:0> 0000
31:16 CAN1IP<2:0> CAN1IS<1:0> I2C2MIP<2:0> I2C2MIS<1:0> 0000
0390 IPC37
15:0 I2C2SIP<2:0> I2C2SIS<1:0> I2C2BIP<2:0> I2C2BIS<1:0> 0000
Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

03A0 IPC38
15:0 ETHIP<2:0> ETHIS<1:0> CAN2IP<2:0> CAN2IS<1:0> 0000
03B0 IPC39
31:16 SPI4EIP<2:0> SPI4EIS<1:0> I2C3MIP<2:0> I2C3MIS<1:0> 0000
03C0 IPC40
31:16 FCEIP<2:0> FCEIS<1:0> RTCCIP<2:0> RTCCIS<1:0> 0000
03D0 IPC41
03E0 IPC42
15:0 SQI1IP<2:0> SQI1IS<1:0> PREIP<2:0> PREIS<1:0> 0000
31:16 I2C4MIP<2:0> I2C4MIS<1:0> I2C4SIP<2:0> I2C4SIS<1:0> 0000
03F0 IPC43
15:0 I2C4BIP<2:0> I2C4BIS<1:0> U4TXIP<2:0> U4TXIS<1:0> 0000

0400 IPC44
0410 IPC45
0420 IPC46
15:0 SPI6EIP<2:0> SPI6EIS<1:0> I2C5MIP<2:0> I2C5MIS<1:0> 0000
31:16 SDHCIP<2:0> SDHC1IS<1:0> U6TXIP<2:0> U6TXIS<1:0> 0000
0430 IPC47
31:16 CTMU1IP<2:0> CTMU1IS<1:0> 0000
0440 IPC48
15:0 GPUIP<2:0> GPU1IS<1:0> GLCDIP<2:0> GLCDIS<1:0> 0000
31:16 ADC0EIP<2:0> ADC0EIS<1:0> ADCURDYIP<2:0> ADCURDYIS<1:0> 0000
0450 IPC49
15:0 ADCARDYIP<2:0> ADCARDYIS<1:0> ADCEOSIP<2:0> ADCEOSIS<1:0> 0000
31:16 ADC4EIP<2:0> ADC4EIS<1:0> ADC3EIP<2:0> ADC3EIS<1:0> 0000
0460 IPC50
15:0 ADC2EIP<2:0> ADC2EIS<1:0> ADC1EIP<2:0> ADC1EIS<1:0> 0000
31:16 ADC0WIP<2:0> ADC0WIS<1:0> ADC7EIP<2:0> ADC7EIS<1:0> 0000
0470 IPC51
15:0 ADCGRPIP<2:0> ADCGRPIS<1:0> 0000
31:16 ADC4WIP<2:0> ADC4WIS<1:0> ADC3WIP<2:0> ADC3WIS<1:0> 0000
0480 IPC52
15:0 ADC2WIP<2:0> ADC2WIS<1:0> ADC1WIP<2:0> ADC1WIS<1:0> 0000
31:16 MPLLFLTIP<2:0> MPLLFLTIS<1:0> ADC7WIP<2:0> ADC7WIS<1:0> 0000
0490 IPC53
15:0 0000
31:16 VOFF<17:16> 0000
0540 OFF000
DS60001361E-page 137
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
0544 OFF001
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0548 OFF002
15:0 VOFF<15:1> 0000
DS60001361E-page 138

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

054C OFF003
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0550 OFF004
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0554 OFF005
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0558 OFF006
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
055C OFF007
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0560 OFF008
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0564 OFF009
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0568 OFF010
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
056C OFF011
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0570 OFF012
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0574 OFF013
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0578 OFF014
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
057C OFF015
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0580 OFF016
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000

0584 OFF017
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0588 OFF018
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
058C OFF019
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0590 OFF020
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0594 OFF021
15:0 VOFF<15:1> 0000
Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

0598 OFF022
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
059C OFF023
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05A0 OFF024
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05A4 OFF025
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05A8 OFF026
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05AC OFF027
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
05B0 OFF028
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05B4 OFF029
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05B8 OFF030
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05BC OFF031
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05C0 OFF032
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05C4 OFF033
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05C8 OFF034
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05CC OFF035
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05D0 OFF036
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05D4 OFF037
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05D8 OFF038
DS60001361E-page 139
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
05DC OFF039
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05E0 OFF040
15:0 VOFF<15:1> 0000
DS60001361E-page 140

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

05E4 OFF041
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05E8 OFF042
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05EC OFF043
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05F0 OFF044
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05F4 OFF045
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05F8 OFF046
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
05FC OFF047
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0600 OFF048
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0604 OFF049
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0608 OFF059
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
060C OFF051
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0610 OFF052
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0614 OFF053
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0618 OFF054
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000

061C OFF055
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0620 OFF056
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0624 OFF057
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0628 OFF058
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
062C OFF059
15:0 VOFF<15:1> 0000
Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

0630 OFF060
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0634 OFF061
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0638 OFF062
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
063C OFF063
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0640 OFF064
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0644 OFF065
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
0648 OFF066
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
064C OFF067
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0650 OFF068
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0654 OFF069
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0658 OFF070
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
065C OFF071
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0660 OFF072
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0664 OFF073
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0668 OFF074
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
066C OFF075
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0670 OFF076
DS60001361E-page 141
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
0674 OFF077
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0678 OFF078
15:0 VOFF<15:1> 0000
DS60001361E-page 142

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

067C OFF079
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0680 OFF080
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0684 OFF081
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0688 OFF082
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
068C OFF083
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0690 OFF084
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0694 OFF085
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0698 OFF086
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
069C OFF087
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06A0 OFF088
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06A4 OFF089
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06A8 OFF090
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06AC OFF091
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06B0 OFF092
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000

06B4 OFF093
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06B8 OFF094
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06BC OFF095
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06C0 OFF096
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06C4 OFF097
15:0 VOFF<15:1> 0000
Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

06C8 OFF098
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06CC OFF099
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06D0 OFF100
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06D4 OFF101
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06D8 OFF102
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06DC OFF103
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
06E0 OFF104
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06E4 OFF105
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06E8 OFF106
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06EC OFF107
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06F4 OFF109
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06F8 OFF110
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
06FC OFF111
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0700 OFF112
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0704 OFF113
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0708 OFF114
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
070C OFF115
DS60001361E-page 143
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
0710 OFF116
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0714 OFF117
15:0 VOFF<15:1> 0000
DS60001361E-page 144

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

0718 OFF118
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
071C OFF119
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0720 OFF120
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0724 OFF121
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0728 OFF122
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
072C OFF123
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0730 OFF124
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0734 OFF125
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0738 OFF126
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
073C OFF127
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0740 OFF128
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0744 OFF129
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0748 OFF130
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
074C OFF131
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000

0750 OFF132
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0754 OFF133
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0758 OFF134
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
075C OFF135
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0760 OFF136
15:0 VOFF<15:1> 0000
Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

0764 OFF137
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0768 OFF138
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
076C OFF139
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0770 OFF140
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0774 OFF141
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0778 OFF142
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
077C OFF143
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0780 OFF144
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0784 OFF145
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0788 OFF146
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
078C OFF147
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0790 OFF148
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0794 OFF149
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0798 OFF150
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
079C OFF151
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07A0 OFF152
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07A4 OFF153
DS60001361E-page 145
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
07A8 OFF154
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07AC OFF155
15:0 VOFF<15:1> 0000
DS60001361E-page 146

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

07B0 OFF156
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07B4 OFF157
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07B8 OFF158
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07BC OFF159
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07C0 OFF160
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07C4 OFF161
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07C8 OFF162
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07CC OFF163
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07D0 OFF164
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07D4 OFF165
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07D8 OFF166
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07DC OFF167
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07E0 OFF168
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07E4 OFF169
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000

07E8 OFF170
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07EC OFF171
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07F0 OFF172
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07F4 OFF173
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
07F8 OFF174
15:0 VOFF<15:1> 0000
Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

07FC OFF175
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0800 OFF176
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0804 OFF177
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0808 OFF178
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
080C OFF179
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0810 OFF180
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
0814 OFF181
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0818 OFF182
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
081C OFF183
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0820 OFF184
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0824 OFF185
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0828 OFF186
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
082C OFF187
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0830 OFF188
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0834 OFF189
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0838 OFF190
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
083C OFF191
DS60001361E-page 147
15:0 VOFF<15:1> 0000

31:16 VOFF<17:16> 0000
0840 OFF192
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0844 OFF193
15:0 VOFF<15:1> 0000
DS60001361E-page 148

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 VOFF<17:16> 0000

084C OFF195
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0850 OFF196
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0854 OFF197
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0858 OFF198
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
085C OFF199
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0860 OFF200
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0864 OFF201
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0868 OFF202
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
086C OFF203
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0874 OFF205
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0878 OFF206
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
087C OFF207
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0880 OFF208
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0884 OFF209
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000

0888 OFF210
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
08A4 OFF211
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
0898 OFF214
15:0 VOFF<15:1> 0000
31:16 VOFF<17:16> 0000
089C OFF215
15:0 VOFF<15:1> 0000
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
NMIKEY<7:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
15:8
MVEC TPC<2:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
INT4EP INT3EP INT2EP INT1EP INT0EP
Legend:
bit 31-24 NMIKEY<7:0>: Non-Maskable Interrupt Key bits

When the correct key (0x4E) is written, a software NMI will be generated. The status is indicated by the
GNMI bit (RNMICON<19>).
bit 12 MVEC: Multi Vector Configuration bit
1 = Interrupt controller configured for multi-vectored mode
0 = Interrupt controller configured for single vectored mode
bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits
111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer
bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
1 = Rising edge
0 = Falling edge
1 = Rising edge
0 = Falling edge
1 = Rising edge
0 = Falling edge
1 = Rising edge
0 = Falling edge

REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
PRI7SS<3:0>(1) PRI6SS<3:0>(1)
23:16
PRI5SS<3:0>(1) PRI4SS<3:0>(1)
15:8
PRI3SS<3:0> PRI2SS<3:0>(1)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
7:0
PRI1SS<3:0>(1) SS0
Legend:
bit 31-28 PRI7SS<3:0>: Interrupt with Priority Level 7 Shadow Set bits(1)
1xxx = Reserved (by default, an interrupt with a priority level of 7 uses Shadow Set 0)
0111 = Interrupt with a priority level of 7 uses Shadow Set 7




Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.

REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED)



bit 0 SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow set
0 = Single vector is not presented with a shadow set
Note 1: These bits are ignored if the MVEC bit (INTCON<12>) = 0.

REGISTER 7-3: INTSTAT: INTERRUPT STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
15:8
SRIPL<2:0>(1)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
SIRQ<7:0>
Legend:

bit 10-8 SRIPL<2:0>: Requested Priority Level bits for Single Vector Mode bits(1)
111-000 = The priority level of the latest interrupt presented to the CPU
bit 7-0 SIRQ<7:0>: Last Interrupt Request Serviced Status bits
11111111-00000000 = The last interrupt request number serviced by the CPU
Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode.
REGISTER 7-4: IPTMR: INTERRUPT PROXIMITY TIMER REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
IPTMR<31:24>
23:16
IPTMR<23:16>
15:8
IPTMR<15:8>
7:0
IPTMR<7:0>
Legend:
bit 31-0 IPTMR<31:0>: Interrupt Proximity Timer Reload bits

Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by
an interrupt event.

REGISTER 7-5: IFSx: INTERRUPT FLAG STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
IFS31 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24
23:16
15:8
7:0
Legend:
bit 31-0 IFS31-IFS0: Interrupt Flag Status bits

1 = Interrupt request has occurred
0 = No interrupt request has occurred
Note: This register represents a generic definition of the IFSx register. Refer to Table 7-2 for the exact bit
definitions.
REGISTER 7-6: IECx: INTERRUPT ENABLE CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
IEC31 IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC24
23:16
15:8
7:0
Legend:
bit 31-0 IEC31-IEC0: Interrupt Enable bits

1 = Interrupt is enabled
0 = Interrupt is disabled
Note: This register represents a generic definition of the IECx register. Refer to Table 7-2 for the exact bit
definitions.

REGISTER 7-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
IP3<2:0> IS3<1:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
IP2<2:0> IS2<1:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
IP1<2:0> IS1<1:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
IP0<2:0> IS0<1:0>
Legend:

bit 28-26 IP3<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7

bit 25-24 IS3<1:0>: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
00 = Interrupt subdirectory is 0

Note: This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit
definitions.

REGISTER 7-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)


Note: This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit
definitions.

REGISTER 7-8: OFFx: INTERRUPT VECTOR ADDRESS OFFSET REGISTER (x = 0-190)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
23:16
VOFF<17:16>
15:8
VOFF<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
7:0
VOFF<7:1>
Legend:

bit 17-1 VOFF<17:1>: Interrupt Vector x Address Offset bits

8.0 OSCILLATOR The PIC32MZ DA oscillator system has the following
modules and features:
CONFIGURATION
Five external and internal oscillator options as clock
Note: This data sheet summarizes the sources
features of the PIC32MZ DA family of On-Chip PLL with user-selectable input divider,
devices. It is not intended to be a multiplier and output divider to boost operating fre-
comprehensive reference source. To quency on select internal and external oscillator
complement the information in this data sources
sheet, refer to Section 42. Oscillators On-Chip user-selectable divisor postscaler on select
with Enhanced PLL (DS60001250) in oscillator sources
the PIC32 Family Reference Manual, Software-controllable switching between
which is available from the Microchip various clock sources
web site (www.microchip.com/PIC32). A Fail-Safe Clock Monitor (FSCM) that detects clock
failure and permits safe application recovery or shut-
down with dedicated Back-up FRC (BFRC)
Dedicated On-Chip PLL for DDR2 and USB modules
Flexible reference clock output
Multiple clock branches for peripherals for better
performance flexibility
A block diagram of the oscillator system is provided
in Figure 8-1. The clock distribution is shown in
Table 8-1.

FIGURE 8-1: PIC32MZ DA FAMILY OSCILLATOR DIAGRAM
(12 or 24 MHz only)
From POSC USB Clock (USBCLK)
USB PLL
Reference Clock(5)
REFOxCON REFOxTRIM
UPLLFSEL REFCLKIx
POSC ROTRIM<8:0> (M) OE
System PLL FRC
LPRC
N
FIN(6)
PLL x M
FVco(6) SOSC
PBCLK1
2 N + ---------
M
512
-
PLLODIV<2:0> REFCLKOx
SYSCLK
(N) FREF(6)
BFRC RODIV<14:0> (N)
PLLIDIV<2:0>
PLLRANGE<2:0>
(N) (6) To SPI, ADC,
PLLICLK PLLMULT<6:0>
(M) N FPLL SPLL SQI, GLCD,
and SDHC
ROSEL<3:0> x = 1-5
SPLL
Primary Oscillator (POSC)
OSC1 Peripheral Bus Clock(5)
C1(3) POSC (HS, EC)
Peripherals,
CPU
XTAL RP(1) RF(2) Postscaler
PBCLKx
Enable
RS(1) PBxDIV<6:0>
(N) x = 1-7
C2(3) OSC2(4) POSCBOOST
POSCGAIN<1:0>
To ADC and Flash
FRC FRCDIV Clock SYSCLK

Oscillator Postscaler N Switch/
Slew Fsys(6)
8 MHz typical
TUN<5:0> FRCDIV<2:0>
(N)
Backup FRC BFRC
Oscillator
8 MHz typical
LPRC LPRC
Oscillator 32.768 kHz
Secondary Oscillator (SOSC)

SOSCO 32.768 kHz
SOSC
SOSCEN
Clock Control Logic FSCM INT
SOSCI SOSCBOOST Fail-Safe
Clock FSCM Event
SOSCGAIN<1:0> Monitor
MPLL(7)
MFIN NOSC<2:0>
MFVCO MFMPLL(7)
N xM N N COSC<2:0>
To DDR2 FCKSM<1:0> OSWEN
MPLLIDIV<5:0> MPLLMULT<7:0> MPLLODIV1<2:0> MPLLODIV2<2:0> Controller WDT, RTCC
(N) (M) (N) (N)
Timer1, RTCC
Notes: 1. A series resistor, RS, may be required for AT strip cut crystals, or to eliminate clipping. Alternately, to increase oscillator circuit gain,
add a parallel resistor, RP, with a value of 1 M.
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 M
3. Refer to Section 42. Oscillators with Enhanced PLL (DS60001250) in the PIC32 Family Reference Manual for help in deter-
mining the best oscillator components.
4. PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.
5. Shaded regions indicate multiple instantiations of a peripheral or feature.
6. Refer to Table 44-25 in Section 44.0 Electrical Characteristics for frequency limitations.
7. Memory Phase-Locked Loop (MPLL) is controlled through the CFGMPLL register (see 41.0 Special Features for details).
MFMPLL drives the DDR2 PHY and is the source clock (DDRCK, DDRCK) for DDR2 SDRAM.

TABLE 8-1: SYSTEM AND PERIPHERAL CLOCK DISTRIBUTION
Peripheral Clock Source
REFCLKO1
REFCLKO2
REFCLKO3
REFCLKO4
REFOCLK5
PBCLK1(1)
USBCLK
SYSCLK
PBCLK2
PBCLK3
PBCLK4
PBCLK5
PBCLK6
PBCLK7
SOSC
LPRC
MPLL
FRC
CPU X
WDT X X X(3)
DMT X X(3) X
GLCD X(3) X(6)
GPU X
DDR2C X(3) X
SDHC X(3) X
Flash X(2) X(2) X(2)
ADC X X X(3) X
Comparator X(3)
CTMU X(3)
Crypto X(3)
RNG X(3)
USB X X(3)
USBCR(7) X(3)
CAN X(3)
Ethernet X(3)
PMP X(3)
I2C X(3)
UART X(3)
RTCC X X X(3)
EBI X
SQI X(3) X
SPI X X
Timers X X(4) X
Output Compare X
Input Capture X
Ports X(3)
DMA X
Interrupts X
Prefetch X
OSC2 Pin X(5)
DSCTRL(8) X X
HLVD X(3)
Note 1: PBCLK1 is used by system modules and cannot be turned off.
2: SYSCLK/PBCLK5 is used to fetch data from/to the Flash Controller, while the FRC clock is used for programming.
3: Special Function Register (SFR) access only.
4: Timer1 only.
5: PBCLK1 divided by 2 is available on the OSC2 pin in certain clock modes.
6: REFCLKO5 (divided version of SPLL clock) is used for the Pixel Clock.
7: USBCR is the Clock/Reset Control block for the USB.
8: DSCTRL is the Deep Sleep Control Block.

8.1 Fail-Safe Clock Monitor (FSCM)
The PIC32MZ DA oscillator system includes a Fail-safe
Clock Monitor (FSCM). The FSCM monitors the
SYSCLK for continuous operation. If it detects that the
SYSCLK has failed, it switches the SYSCLK over to the
BFRC oscillator and triggers a NMI. The BFRC is an
untuned 8 MHz oscillator that will drive the SYSCLK
during FSCM event. When the NMI is executed, soft-
ware can attempt to restart the main oscillator or shut
down the system.
In Sleep mode both the SYSCLK and the FSCM halt,
which prevents FSCM detection.

8.2 Oscillator Control Registers
TABLE 8-2:
Virtual Address OSCILLATOR CONFIGURATION REGISTER MAP
Bits
All Resets(1)
Bit Range
(BF80_#)
Register
Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 FRCDIV<2:0> DRMEN SLP2SPD 0020

1200 OSCCON
15:0 COSC<2:0> NOSC<2:0> CLKLOCK SLPEN CF SOSCEN OSWEN xx0x
31:16 0000
1210 OSCTUN
15:0 TUN<5:0> 00xx
31:16 PLLODIV<2:0> PLLMULT<6:0> 01xx
1220 SPLLCON
15:0 PLLIDIV<2:0> PLLICLK PLLRANGE<2:0> 0x0x
31:16 RODIV<14:0> 0000
1280 REFO1CON
15:0 ON SIDL OE RSLP DIVSWEN ACTIVE ROSEL<3:0> 0000
31:16 ROTRIM<8:0> 0000
1290 REFO1TRIM

15:0 0000
31:16 RODIV<14:0> 0000
12A0 REFO2CON
15:0 ON SIDL RSLP DIVSWEN ACTIVE ROSEL<3:0> 0000
31:16 ROTRIM<8:0> 0000
12B0 REFO2TRIM
15:0 0000
31:16 RODIV<14:0> 0000
12C0 REFO3CON
31:16 ROTRIM<8:0> 0000
12D0 REFO3TRIM
15:0 0000
31:16 RODIV<14:0> 0000
12E0 REFO4CON
31:16 ROTRIM<8:0> 0000
12F0 REFO4TRIM
15:0 0000
31:16 RODIV<14:0> 0000
1300 REFO5CON
15:0 ON SIDL RSLP DIVSWEN ACTIVE ROSEL<3:0> 0000
31:16 ROTRIM<8:0> 0000
1310 REFO5TRIM
15:0 0000
31:16 0000
1340 PB1DIV
15:0 PBDIVRDY PBDIV<6:0> 8801
31:16 0000
DS60001361E-page 161
1350 PB2DIV
15:0 ON PBDIVRDY PBDIV<6:0> 8801
31:16 0000
1360 PB3DIV
31:16 0000
1370 PB4DIV
Note 1: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
DS60001361E-page 162
TABLE 8-2: OSCILLATOR CONFIGURATION REGISTER MAP (CONTINUED)

Virtual Address
Bits
All Resets(1)
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
1380 PB5DIV
31:16 0000
1390 PB6DIV
31:16 0000
13A0 PB7DIV
31:16 SYSDIV<3:0> 0000
13C0 SLEWCON
15:0 SLWDIV<2:0> UPEN DNEN BUSY 0000
31:16 0000
13D0 CLKSTAT
15:0 SPLLRDY LPRCRDY SOSCRDY POSCRDY FRCRDY 0000
Note 1: Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
FRCDIV<2:0>
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
23:16
DRMEN SLP2SPD
U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y
15:8
COSC<2:0> NOSC<2:0>
R/W-0 U-0 U-0 R/W-0 R/W-0, HS U-0 R/W-y R/W-y
7:0
CLKLOCK SLPEN CF SOSCEN OSWEN(1)
Legend: y = Value set from Configuration bits on POR HS = Hardware Set


bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
000 = FRC divided by 1 (default setting)
bit 23 DRMEN: Dream Mode Enable bit
1 = Dream mode is enabled
0 = Dream mode is disabled
bit 21 SLP2SPD: Sleep Two-speed Start-up Control bit
1 = Use FRC as SYSCLK until the selected clock is ready
0 = Use the selected clock directly
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
111 = System PLL (SPLL)
110 = Back-up Fast RC (BFRC) Oscillator
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (HS or EC)
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)
Note 1: The reset value for this bit depends on the setting of the IESO bit (DEVCFG1<7>). When IESO = 1, the
reset value is 1. When IESO = 0, the reset value is 0.
Note: Writes to this register require an unlock sequence. Refer to Section 42. Oscillators with Enhanced PLL
(DS60001250) in the PIC32 Family Reference Manual for details.

REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
bit 10-8 NOSC<2:0>: New Oscillator Selection bits
110 = Reserved
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Reserved
010 = Primary Oscillator (POSC) (HS or EC)
000 = Internal Fast RC (FRC) Oscillator divided by FRCDIV<2:0> bits (FRCDIV)
On Reset, these bits are set to the value of the FNOSC<2:0> Configuration bits (DEVCFG1<2:0>).
bit 7 CLKLOCK: Clock Selection Lock Enable bit
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified
bit 4 SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected
bit 1 SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 0 OSWEN: Oscillator Switch Enable bit(1)
1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is complete
Note 1: The reset value for this bit depends on the setting of the IESO bit (DEVCFG1<7>). When IESO = 1, the
reset value is 1. When IESO = 0, the reset value is 0.

REGISTER 8-2: OSCTUN: FRC TUNING REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0 (1)
TUN<5:0>
Legend:

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1)
100000 = Center frequency -4%
100001 =

111111 =
000000 = Center frequency; Oscillator runs at nominal frequency (8 MHz)
000001 =

011110 =
011111 = Center frequency +4%
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized, nor tested.
Note: Writes to this register require an unlock sequence. Refer to Section 42. Oscillators with Enhanced
PLL (DS60001250) in the PIC32 Family Reference Manual for details.

REGISTER 8-3: SPLLCON: SYSTEM PLL CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-y R/W-y R/W-y
31:24
PLLODIV<2:0>
U-0 R/W-y R/W-y R/W-y R/W-y R/W-y R/W-y R/W-y
23:16
PLLMULT<6:0>
U-0 U-0 U-0 U-0 U-0 R/W-y R/W-y R/W-y
15:8
PLLIDIV<2:0>
R/W-y U-0 U-0 U-0 U-0 R/W-y R/W-y R/W-y
7:0
PLLICLK PLLRANGE<2:0>
Legend: y = Value set from Configuration bits on POR


bit 26-24 PLLODIV<2:0>: System PLL Output Clock Divider bits
111 = Reserved
110 = Reserved
101 = PLL Divide by 32
000 = Reserved
The default setting is specified by the FPLLODIV<2:0> Configuration bits in the DEVCFG2 register. Refer
to Register 34-5 in Section 34.0 Special Features for information.
bit 22-16 PLLMULT<6:0>: System PLL Multiplier bits
1111111 = Multiply by 128

The default setting is specified by the FPLLMULT<6:0> Configuration bits in the DEVCFG2 register. Refer
to Register 34-5 in Section 34.0 Special Features for information.
Note 1: Writes to this register require an unlock sequence. Refer to Section 42. Oscillators with Enhanced
2: Writes to this register are not allowed if the SPLL is selected as a clock source (COSC<2:0> = 001).

REGISTER 8-3: SPLLCON: SYSTEM PLL CONTROL REGISTER
bit 10-8 PLLIDIV<2:0>: System PLL Input Clock Divider bits
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1
The default setting is specified by the FPLLIDIV<2:0> Configuration bits in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 Special Features for information. If the PLLICLK is set for FRC, this setting
is ignored by the PLL and the divider is set to Divide-by-1.
bit 7 PLLICLK: System PLL Input Clock Source bit
1 = FRC is selected as the input to the System PLL
0 = POSC is selected as the input to the System PLL
The POR default is specified by the FPLLICLK Configuration bit in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 Special Features for information.
bit 2-0 PLLRANGE<2:0>: System PLL Frequency Range Selection bits
111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
The default setting is specified by the FPLLRNG<2:0> Configuration bits in the DEVCFG2 register. Refer to
Register 34-5 in Section 34.0 Special Features for information.
Note 1: Writes to this register require an unlock sequence. Refer to Section 42. Oscillators with Enhanced
2: Writes to this register are not allowed if the SPLL is selected as a clock source (COSC<2:0> = 001).

REGISTER 8-4: REFOxCON: REFERENCE OSCILLATOR CONTROL REGISTER (x = 1-4)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
RODIV<14:8>
23:16
RODIV<7:0>
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R-0, HS, HC
15:8
ON(1) SIDL OE RSLP(2) DIVSWEN ACTIVE(1)
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0 ROSEL<3:0>(3)
Legend: HC = Hardware Cleared HS = Hardware Set


bit 30-16 RODIV<14:0> Reference Clock Divider bits
The value selects the reference clock divider bits (see Figure 8-1 for details). A value of 0 selects no divider.
bit 15 ON: Output Enable bit(1)
1 = Reference Oscillator Module enabled
0 = Reference Oscillator Module disabled
bit 13 SIDL: Peripheral Stop in Idle Mode bit
1 = Discontinue module operation when the device enters Idle mode
0 = Continue module operation in Idle mode
bit 12 OE: Reference Clock Output Enable bit
1 = Reference clock is driven out on REFCLKOx pin
0 = Reference clock is not driven out on REFCLKOx pin
bit 11 RSLP: Reference Oscillator Module Run in Sleep bit(2)
1 = Reference Oscillator Module output continues to run in Sleep
0 = Reference Oscillator Module output is disabled in Sleep
bit 9 DIVSWEN: Divider Switch Enable bit
1 = Divider switch is in progress
0 = Divider switch is complete
bit 8 ACTIVE: Reference Clock Request Status bit(1)
1 = Reference clock request is active
0 = Reference clock request is not active
bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits(3)
1111 = Reserved

1001 = BFRC
1000 = REFCLKIx
0111 = System PLL output
0110 = Reserved
0101 = SOSC
0100 = LPRC
0011 = FRC
0010 = POSC
0001 = PBCLK1
0000 = SYSCLK
Note 1: Do not write to this register when the ON bit is not equal to the ACTIVE bit.
2: This bit is ignored when the ROSEL<3:0> bits = 0000 or 0001.
3: The ROSEL<3:0> bits should not be written while the ACTIVE bit is 1, as undefined behavior may result.

REGISTER 8-5: REFOxTRIM: REFERENCE OSCILLATOR TRIM REGISTER (x = 1-4)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
ROTRIM<8:1>
R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
ROTRIM<0>
U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:
bit 31-23 ROTRIM<8:0>: Reference Oscillator Trim bits

111111111 = 511/512 divisor added to RODIV value


000000000 = 0 divisor added to RODIV value
Note 1: While the ON bit (REFOxCON<15>) is 1, writes to this register do not take effect until the DIVSWEN bit is
also set to 1.
2: Do not write to this register when the ON bit (REFOxCON<15>) is not equal to the ACTIVE bit
(REFOxCON<8>).
3: Specified values in this register do not take effect if RODIV<14:0> (REFOxCON<30:16>) = 0.

REGISTER 8-6: PBxDIV: PERIPHERAL BUS x CLOCK DIVISOR CONTROL REGISTER (x = 1-7)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-1 U-0 U-0 U-0 R-1 U-0 U-0 U-0
15:8 (1)
ON PBDIVRDY
U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
7:0
PBDIV<6:0>
Legend:

bit 15 ON: Peripheral Bus x Output Clock Enable bit(1)
1 = Output clock is enabled
0 = Output clock is disabled
bit 11 PBDIVRDY: Peripheral Bus x Clock Divisor Ready bit
1 = Clock divisor logic is not switching divisors and the PBxDIV<6:0> bits may be written
0 = Clock divisor logic is currently switching values and the PBxDIV<6:0> bits cannot be written
bit 6-0 PBDIV<6:0>: Peripheral Bus x Clock Divisor Control bits
1111111 = PBCLKx is SYSCLK divided by 128

0000001 = PBCLKx is SYSCLK divided by 2 (default value for x < 7)
0000000 = PBCLKx is SYSCLK divided by 1 (default value for x 7)
Note 1: The clock for peripheral bus 1 cannot be turned off. Therefore, the ON bit in the PB1DIV register cannot
be written as a 0.

REGISTER 8-7: SLEWCON: OSCILLATOR SLEW CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16 (1)
SYSDIV<3:0>
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
SLWDIV<2:0>
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R-0, HS, HC
7:0
UPEN DNEN BUSY


bit 19-16 SYSDIV<3:0>: System Clock Divide Control bits(1)
1111 = SYSCLK is divided by 16

0000 = SYSCLK is not divided
bit 10-8 SLWDIV<2:0>: Slew Divisor Steps Control bits
These bits control the maximum division steps used when slewing during a frequency change.
111 = Steps are divide by 128, 64, 32, 16, 8, 4, 2, and then no divisor
110 = Steps are divide by 64, 32, 16, 8, 4, 2, and then no divisor
101 = Steps are divide by 32, 16, 8, 4, 2, and then no divisor
100 = Steps are divide by 16, 8, 4, 2, and then no divisor
011 = Steps are divide by 8, 4, 2, and then no divisor
010 = Steps are divide by 4, 2, and then no divisor
001 = Steps are divide by 2, and then no divisor
000 = No divisor is used during slewing
The steps apply in reverse order (i.e., 2, 4, 8, etc.) during a downward frequency change.
bit 2 UPEN: Upward Slew Enable bit
1 = Slewing enabled for switching to a higher frequency
0 = Slewing disabled for switching to a higher frequency
bit 1 DNEN: Downward Slew Enable bit
1 = Slewing enabled for switching to a lower frequency
0 = Slewing disabled for switching to a lower frequency
bit 0 BUSY: Clock Switching Slewing Active Status bit
1 = Clock frequency is being actively slewed to the new frequency
0 = Clock switch has reached its final value
Note 1: The SYSDIV<3:0> bit settings are ignored if both UPEN and DNEN = 0, and SYSCLK will be divided by 1.

REGISTER 8-8: CLKSTAT: OSCILLATOR CLOCK STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R-0 U-0 R-0 R-0 U-0 R-0 U-0 R-0
7:0
SPLLRDY LPRCRDY SOSCRDY POSCRDY FRCRDY
Legend:

bit 7 SPLLRDY: System PLL (SPLL) Ready Status bit
1 = SPLL is ready
0 = SPLL is not ready
bit 5 LPRCRDY: Low-Power RC (LPRC) Oscillator Ready Status bit
1 = LPRC is stable and ready
0 = LPRC is disabled or not operating
bit 4 SOSCRDY: Secondary Oscillator (SOSC) Ready Status bit
1 = SOSC is stable and ready
0 = SOSC is disabled or not operating
bit 2 POSCRDY: Primary Oscillator (POSC) Ready Status bit
1 = POSC is stable and ready
0 = POSC is disabled or not operating
bit 0 FRCRDY: Fast RC (FRC) Oscillator Ready Status bit
1 = FRC is stable and ready
0 = FRC is disabled for not operating

9.0 PREFETCH MODULE The Prefetch module holds a subset of PFM in
temporary holding spaces known as lines. Each line
Note: This data sheet summarizes the features contains a tag and data field. Normally, the lines hold a
of the PIC32MZ Graphics (DA) Family of copy of what is currently in memory to make
devices. It is not intended to be a instructions or data available to the CPU without Flash
comprehensive reference source. To Wait states.
sheet, refer to Section 41. Prefetch 9.1 Features
Module for Devices with L1 CPU
Cache (DS60001183), which is available The Prefetch module includes the following key
from the Documentation > Reference features:
Manual section of the Microchip PIC32 4x16 byte fully-associative lines
web site (www.microchip.com/pic32). One line for CPU instructions
The Prefetch module is a performance enhancing One line for CPU data
module that is included in PIC32MZ DA family devices. Two lines for peripheral data
When running at high-clock rates, Wait states must be 16-byte parallel memory fetch
inserted into Program Flash Memory (PFM) read Configurable predictive prefetch
transactions to meet the access time of the PFM. Wait
Error detection and correction
states can be hidden to the core by prefetching and
storing instructions in a temporary holding area that the A simplified block diagram of the Prefetch module is
CPU can access quickly. Although the data path to the shown in Figure 9-1.
CPU is 32 bits wide, the data path to the PFM is 128
bits wide. This wide data path provides the same
bandwidth to the CPU as a 32-bit path running at four
times the frequency.
FIGURE 9-1: PREFETCH MODULE BLOCK DIAGRAM
SYSCLK
Tag Data
Bus Control
CPU
CPU
Prefetch Buffer
Line Control
Program Flash Memory (PFM)

DS60001361E-page 174
9.2 Prefetch Control Registers

TABLE 9-1: PREFETCH REGISTER MAP
Virtual Address
Bits
All Resets
Bit Range
(BF8E_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 PFMSECEN 0000

0000 PRECON
15:0 PREFEN<1:0> PFMWS<2:0> 0007
31:16 PFMDED PFMSEC 0000
0010 PRESTAT
15:0 PFMSECCNT<7:0> 0000
Legend: x = unknown value on Reset, = unimplemented, read as 0. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for
more information.
REGISTER 9-1: PRECON: PREFETCH MODULE CONTROL REGISTER

Bit Range Bit Bit Bit Bit Bit Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0
31:24
PFMSECEN
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
7:0
PREFEN<1:0> PFMWS<2:0>(1)
Legend:
bit 31-27 Unimplemented: Write 0; ignore read

bit 26 PFMSECEN: Flash SEC Interrupt Enable bit
1 = Generate an interrupt when the PFMSEC bit (PRESTAT<26>) is set
0 = Do not generate an interrupt when the PFMSEC bit is set
bit 5-4 PREFEN<1:0>: Predictive Prefetch Enable bits
11 = Enable predictive prefetch for any address
10 = Enable predictive prefetch for CPU instructions and CPU data
01 = Enable predictive prefetch for CPU instructions only
00 = Disable predictive prefetch
bit 3 Unimplemented: Write 0; ignore read
bit 2-0 PFMWS<2:0>: PFM Access Time Defined in Terms of SYSCLK Wait States bits(1)
111 = Seven Wait states

010 = Two Wait states
001 = One Wait state
000 = Zero Wait states
Note 1: For the Wait states to SYSCLK relationship, refer to Table 44-16 in Section44.0 Electrical
Characteristics.

Register 9-1: PRESTAT: Prefetch Module Status Register

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS U-0 U-0
31:24
PFMDED PFMSEC
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
PFMSECCNT<7:0>
Legend: HS = Hardware Set


bit 27 PFMDED: Flash Double-bit Error Detected (DED) Status bit
This bit is set in hardware and can only be cleared (i.e., set to 0) in software.
1 = A DED error has occurred
0 = A DED error has not occurred
bit 26 PFMSEC: Flash Single-bit Error Corrected (SEC) Status bit
1 = A SEC error occurred when PFMSECCNT<7:0> was equal to zero
0 = A SEC error has not occurred
bit 7-0 PFMSECCNT<7:0>: Flash SEC Count bits
11111111 - 00000000 = SEC count

10.0 DIRECT MEMORY ACCESS Fixed priority channel arbitration
(DMA) CONTROLLER Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt) DMA
Note: This data sheet summarizes the features requests
of the PIC32MZ Graphics (DA) Family of - One-Shot or Auto-Repeat Block Transfer modes
devices. It is not intended to be a - Channel-to-channel chaining
Flexible DMA requests:
sheet, refer to Section 31. Direct Mem- - A DMA request can be selected from any of the
ory Access (DMA) Controller peripheral interrupt sources
(DS60001117), which is available from the - Each channel can select any (appropriate)
Documentation > Reference Manual observable interrupt as its DMA request source
section of the Microchip PIC32 web site - A DMA transfer abort can be selected from any
(www.microchip.com/pic32). of the peripheral interrupt sources
- Up to 2-byte Pattern (data) match transfer
The Direct Memory Access (DMA) Controller is a bus termination
master module useful for data transfers between differ-
Multiple DMA channel status interrupts:
ent devices without CPU intervention. The source and
destination of a DMA transfer can be any of the mem- - DMA channel block transfer complete
ory mapped modules existent in the device such as - Source empty or half empty
SPI, UART, PMP, etc., or memory itself. - Destination full or half full
Following are some of the key features of the DMA - DMA transfer aborted due to an external event
Controller module: - Invalid DMA address generated
Eight identical channels, each featuring: DMA debug support features:
- Auto-increment source and destination - Most recent error address accessed by a DMA
address registers channel
- Source and destination pointers - Most recent DMA channel to transfer data
- Memory to memory and memory to CRC Generation module:
peripheral transfers - CRC module can be assigned to any of the
Automatic word-size detection: available channels
- Transfer granularity, down to byte level - CRC module is highly configurable
- Bytes need not be word-aligned at source and
destination
FIGURE 10-1: DMA BLOCK DIAGRAM
Interrupt Controller System IRQ
DMA SYSCLK
SE
L
Peripheral Bus Address Decoder Channel 0 Control I0
Channel 1 Control I1 Y Bus System Bus + Bus Arbitration

Interface
I2
Global Control Channel n Control In

(DMACON) L
SE
Channel Priority
Arbitration

DS60001361E-page 178
10.1 DMA Control Registers

TABLE 10-1: DMA GLOBAL REGISTER MAP
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
1000 DMACON
15:0 ON SUSPEND DMABUSY 0000
31:16 RDWR 0000
1010 DMASTAT
15:0 DMACH<2:0> 0000
31:16 0000
1020 DMAADDR DMAADDR<31:0>
15:0 0000
more information.
TABLE 10-2: DMA CRC REGISTER MAP

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 BYTO<1:0> WBO BITO 0000

1030 DCRCCON
15:0 PLEN<4:0> CRCEN CRCAPP CRCTYP CRCCH<2:0> 0000
31:16 0000
1040 DCRCDATA DCRCDATA<31:0>
15:0 0000
31:16 0000
1050 DCRCXOR DCRCXOR<31:0>
15:0 0000
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for
more information.
TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 CHPIGN<7:0> 7700

1060 DCH0CON
15:0 CHBUSY CHPIGNEN CHPATLEN CHCHNS CHEN CHAED CHCHN CHAEN CHEDET CHPRI<1:0> 0000
31:16 CHAIRQ<7:0> 00FF
1070 DCH0ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN FF00
31:16 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
1080 DCH0INT
15:0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 xxxx
1090 DCH0SSA CHSSA<31:0>
15:0 xxxx
31:16 xxxx
10A0 DCH0DSA CHDSA<31:0>
15:0 xxxx

31:16 0000
10B0 DCH0SSIZ
15:0 CHSSIZ<15:0> xxxx
31:16 0000
10C0 DCH0DSIZ
15:0 CHDSIZ<15:0> xxxx
31:16 0000
10D0 DCH0SPTR
15:0 CHSPTR<15:0> 0000
31:16 0000
10E0 DCH0DPTR
15:0 CHDPTR<15:0> 0000
31:16 0000
10F0 DCH0CSIZ
15:0 CHCSIZ<15:0> xxxx
31:16 0000
1100 DCH0CPTR
15:0 CHCPTR<15:0> 0000
31:16 0000
1110 DCH0DAT
15:0 CHPDAT<15:0> xxxx
31:16 CHPIGN<7:0> 7700
1120 DCH1CON
31:16 CHAIRQ<7:0> 00FF
1130 DCH1ECON
1140 DCH1INT
DS60001361E-page 179
31:16 xxxx
15:0 xxxx
31:16 xxxx
1160 DCH1DSA CHDSA<31:0>
15:0 xxxx
more information.
DS60001361E-page 180
TABLE 10-3: DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED)

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
1170 DCH1SSIZ
31:16 0000
1180 DCH1DSIZ
31:16 0000
1190 DCH1SPTR
15:0 CHSPTR<15:0> 0000
31:16 0000
11A0 DCH1DPTR
15:0 CHDPTR<15:0> 0000
31:16 0000
11B0 DCH1CSIZ
31:16 0000
11C0 DCH1CPTR
15:0 CHCPTR<15:0> 0000
31:16 0000
11D0 DCH1DAT
31:16 CHPIGN<7:0> 7700
11E0 DCH2CON
31:16 CHAIRQ<7:0> 00FF
11F0 DCH2ECON
1200 DCH2INT
31:16 xxxx
15:0 xxxx
31:16 xxxx
15:0 xxxx
31:16 0000
1230 DCH2SSIZ
31:16 0000
1240 DCH2DSIZ
31:16 0000
1250 DCH2SPTR
15:0 CHSPTR<15:0> 0000
31:16 0000
1260 DCH2DPTR
15:0 CHDPTR<15:0> 0000
31:16 0000
1270 DCH2CSIZ
more information.
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
1280 DCH2CPTR
15:0 CHCPTR<15:0> 0000
31:16 0000
1290 DCH2DAT
31:16 CHPIGN<7:0> 7700
12A0 DCH3CON
31:16 CHAIRQ<7:0> 00FF
12B0 DCH3ECON
12C0 DCH3INT

31:16 xxxx
12D0 DCH3SSA CHSSA<31:0>
15:0 xxxx
31:16 xxxx
12E0 DCH3DSA CHDSA<31:0>
15:0 xxxx
31:16 0000
12F0 DCH3SSIZ
31:16 0000
1300 DCH3DSIZ
31:16 0000
1310 DCH3SPTR
15:0 CHSPTR<15:0> 0000
31:16 0000
1320 DCH3DPTR
15:0 CHDPTR<15:0> 0000
31:16 0000
1330 DCH3CSIZ
31:16 0000
1340 DCH3CPTR
15:0 CHCPTR<15:0> 0000
31:16 0000
1350 DCH3DAT
31:16 CHPIGN<7:0> 7700
1360 DCH4CON
15:0 CHBUSY CHPIGNEN CHPATLEN CHCHNS CHEN CHAED CHCHN CHAEN CHEDET CHPRI<1:0>
DS60001361E-page 181
0000
31:16 CHAIRQ<7:0> 00FF
1370 DCH4ECON
1380 DCH4INT
more information.
DS60001361E-page 182

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 xxxx
15:0 xxxx
31:16 xxxx
13A0 DCH4DSA CHDSA<31:0>
15:0 xxxx
31:16 0000
13B0 DCH4SSIZ
31:16 0000
13C0 DCH4DSIZ
31:16 0000
13D0 DCH4SPTR
15:0 CHSPTR<15:0> 0000
31:16 0000
13E0 DCH4DPTR
15:0 CHDPTR<15:0> 0000
31:16 0000
13F0 DCH4CSIZ
31:16 0000
1400 DCH4CPTR
15:0 CHCPTR<15:0> 0000
31:16 0000
1410 DCH4DAT
31:16 CHPIGN<7:0> 7700
1420 DCH5CON
31:16 CHAIRQ<7:0> 00FF
1430 DCH5ECON
1440 DCH5INT
31:16 xxxx

15:0 xxxx
31:16 xxxx
15:0 xxxx
31:16 0000
1470 DCH5SSIZ
31:16 0000
1480 DCH5DSIZ
31:16 0000
1490 DCH5SPTR
15:0 CHSPTR<15:0> 0000
more information.
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
14A0 DCH5DPTR
15:0 CHDPTR<15:0> 0000
31:16 0000
14B0 DCH5CSIZ
31:16 0000
14C0 DCH5CPTR
15:0 CHCPTR<15:0> 0000
31:16 0000
14D0 DCH5DAT
31:16 CHPIGN<7:0> 7700
14E0 DCH6CON
31:16 CHAIRQ<7:0>

00FF
14F0 DCH6ECON
1500 DCH6INT
31:16 xxxx
15:0 xxxx
31:16 xxxx
15:0 xxxx
31:16 0000
1530 DCH6SSIZ
31:16 0000
1540 DCH6DSIZ
31:16 0000
1550 DCH6SPTR
15:0 CHSPTR<15:0> 0000
31:16 0000
1560 DCH6DPTR
15:0 CHDPTR<15:0> 0000
31:16 0000
1570 DCH6CSIZ
31:16 0000
1580 DCH6CPTR
15:0 CHCPTR<15:0> 0000
DS60001361E-page 183
31:16 0000
1590 DCH6DAT
31:16 CHPIGN<7:0> 7700
15A0 DCH7CON
more information.
DS60001361E-page 184

Virtual Address
Bits
All Resets
Bit Range
(BF81_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 CHAIRQ<7:0> 00FF

15B0 DCH7ECON
15C0 DCH7INT
31:16 xxxx
15D0 DCH7SSA CHSSA<31:0>
15:0 xxxx
31:16 xxxx
15E0 DCH7DSA CHDSA<31:0>
15:0 xxxx
31:16 0000
15F0 DCH7SSIZ
31:16 0000
1600 DCH7DSIZ
31:16 0000
1610 DCH7SPTR
15:0 CHSPTR<15:0> 0000
31:16 0000
1620 DCH7DPTR
15:0 CHDPTR<15:0> 0000
31:16 0000
1630 DCH7CSIZ
31:16 0000
1640 DCH7CPTR
15:0 CHCPTR<15:0> 0000
31:16 0000
1650 DCH7DAT
more information.
REGISTER 10-1: DMACON: DMA CONTROLLER CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0
15:8
ON SUSPEND DMABUSY
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:

bit 15 ON: DMA On bit
1 = DMA module is enabled
0 = DMA module is disabled
bit 12 SUSPEND: DMA Suspend bit
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
bit 11 DMABUSY: DMA Module Busy bit
1 = DMA module is active and is transferring data
0 = DMA module is disabled and not actively transferring data

REGISTER 10-2: DMASTAT: DMA STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
RDWR
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
7:0
DMACH<2:0>
Legend:
bit 31 RDWR: Read/Write Status bit

1 = Last DMA bus access when an error was detected was a read
0 = Last DMA bus access when an error was detected was a write
bit 2-0 DMACH<2:0>: DMA Channel bits
These bits contain the value of the most recent active DMA channel when an error was detected.
REGISTER 10-3: DMAADDR: DMA ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
DMAADDR<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
DMAADDR<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
DMAADDR<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
DMAADDR<7:0>
Legend:
bit 31-0 DMAADDR<31:0>: DMA Module Address bits

These bits contain the address of the most recent DMA access when an error was detected.

REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0
31:24 (1)
BYTO<1:0> WBO BITO
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
PLEN<4:0>(1)
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
7:0
CRCEN CRCAPP(1) CRCTYP CRCCH<2:0>
Legend:

bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits
11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order
per half-word)
10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per
half-word)
01 = Endian byte swap on word boundaries (i.e., reverse source byte order)
00 = No swapping (i.e., source byte order)
bit 27 WBO: CRC Write Byte Order Selection bit(1)
1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>
0 = Source data is written to the destination unaltered
bit 24 BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected)
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected)
0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected)
bit 12-8 PLEN<4:0>: Polynomial Length bits(1)
These bits are unused.

Denotes the length of the polynomial 1.
bit 7 CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
bit 6 CRCAPP: CRC Append Mode bit(1)
1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5 CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC
bit 2-0 CRCCH<2:0>: CRC Channel Select bits
111 = CRC is assigned to Channel 7
Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

REGISTER 10-5: DCRCDATA: DMA CRC DATA REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
DCRCDATA<31:24>
23:16
DCRCDATA<23:16>
15:8
DCRCDATA<15:8>
7:0
DCRCDATA<7:0>
Legend:
bit 31-0 DCRCDATA<31:0>: CRC Data Register bits

Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return 0 on any read.

Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always 0. Data written
to this register is converted and read back in 1s complement form (i.e., current IP header checksum value).

Bits greater than PLEN will return 0 on any read.
REGISTER 10-6: DCRCXOR: DMA CRCXOR ENABLE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
DCRCXOR<31:24>
23:16
DCRCXOR<23:16>
15:8
DCRCXOR<15:8>
7:0
DCRCXOR<7:0>
Legend:
bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits

This register is unused.

1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register

REGISTER 10-7: DCHxCON: DMA CHANNEL x CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
CHPIGN<7:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0
15:8
CHBUSY CHIPGNEN CHPATLEN CHCHNS(1)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R/W-0
7:0
CHEN(2) CHAED CHCHN CHAEN CHEDET CHPRI<1:0>
Legend:
bit 31-24 CHPIGN<7:0>: Channel Register Data bits

Pattern Terminate mode:
Any byte matching these bits during a pattern match may be ignored during the pattern match determina-
tion when the CHPIGNEN bit is set. If a byte is read that is identical to this data byte, the pattern match
logic will treat it as a dont care when the pattern matching logic is enabled and the CHPIGEN bit is set.
bit 15 CHBUSY: Channel Busy bit
1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled
bit 13 CHPIGNEN: Enable Pattern Ignore Byte bit
1 = Treat any byte that matches the CHPIGN<7:0> bits as a dont care when pattern matching is enabled
0 = Disable this feature
bit 11 CHPATLEN: Pattern Length bit
1 = 2 byte length
0 = 1 byte length
bit 8 CHCHNS: Chain Channel Selection bit(1)
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
bit 7 CHEN: Channel Enable bit(2)
1 = Channel is enabled
0 = Channel is disabled
bit 6 CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
bit 5 CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained
0 = Do not allow channel to be chained
Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.

REGISTER 10-7: DCHxCON: DMA CHANNEL x CONTROL REGISTER (CONTINUED)
bit 4 CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
bit 2 CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
bit 1-0 CHPRI<1:0>: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
Note 1: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1).
2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.

REGISTER 10-8: DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16 (1)
CHAIRQ<7:0>
15:8
CHSIRQ<7:0>(1)
S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
7:0
CFORCE CABORT PATEN SIRQEN AIRQEN
Legend: S = Settable bit


bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag

bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1)
11111111 = Interrupt 255 will initiate a DMA transfer

bit 7 CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a 1
0 = This bit always reads 0
bit 6 CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a 1
0 = This bit always reads 0
bit 5 PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
bit 4 SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
bit 3 AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
Note 1: See Table 7-2: Interrupt IRQ, Vector and Bit Location for the list of available interrupt IRQ sources.

REGISTER 10-9: DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF
Legend:

bit 23 CHSDIE: Channel Source Done Interrupt Enable bit
bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit
bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit
bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit
bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit
bit 16 CHERIE: Channel Address Error Interrupt Enable bit
bit 7 CHSDIF: Channel Source Done Interrupt Flag bit
1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0 = No interrupt is pending
bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit
1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)

REGISTER 10-9: DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED)
bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit
1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit
1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit
1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
bit 0 CHERIF: Channel Address Error Interrupt Flag bit
1 = A channel address error has been detected
Either the source or the destination address is invalid.

REGISTER 10-10: DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
CHSSA<31:24>
23:16
CHSSA<23:16>
15:8
CHSSA<15:8>
7:0
CHSSA<7:0>
Legend:
bit 31-0 CHSSA<31:0> Channel Source Start Address bits

Channel source start address.
Note: This must be the physical address of the source.
REGISTER 10-11: DCHxDSA: DMA CHANNEL x DESTINATION START ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
CHDSA<31:24>
23:16
CHDSA<23:16>
15:8
CHDSA<15:8>
7:0
CHDSA<7:0>
Legend:
bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits

Channel destination start address.
Note: This must be the physical address of the destination.

REGISTER 10-12: DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
CHSSIZ<15:8>
7:0
CHSSIZ<7:0>
Legend:

bit 15-0 CHSSIZ<15:0>: Channel Source Size bits
1111111111111111 = 65,535 byte source size

0000000000000010 = 2 byte source size
0000000000000001 = 1 byte source size
0000000000000000 = 65,536 byte source size
REGISTER 10-13: DCHxDSIZ: DMA CHANNEL x DESTINATION SIZE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
CHDSIZ<15:8>
7:0
CHDSIZ<7:0>
Legend:

bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits
1111111111111111 = 65,535 byte destination size

0000000000000010 = 2 byte destination size
0000000000000001 = 1 byte destination size
0000000000000000 = 65,536 byte destination size

REGISTER 10-14: DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
CHSPTR<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
CHSPTR<7:0>
Legend:

bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits
1111111111111111 = Points to byte 65,535 of the source

0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte 0 of the source
Note: When in Pattern Detect mode, this register is reset on a pattern detect.
REGISTER 10-15: DCHxDPTR: DMA CHANNEL x DESTINATION POINTER REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
CHDPTR<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
CHDPTR<7:0>
Legend:

bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits
1111111111111111 = Points to byte 65,535 of the destination

0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination

REGISTER 10-16: DCHxCSIZ: DMA CHANNEL x CELL-SIZE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
CHCSIZ<15:8>
7:0
CHCSIZ<7:0>
Legend:

bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits
1111111111111111 = 65,535 bytes transferred on an event

0000000000000010 = 2 bytes transferred on an event
0000000000000001= 1 byte transferred on an event
0000000000000000 = 65,536 bytes transferred on an event
REGISTER 10-17: DCHxCPTR: DMA CHANNEL x CELL POINTER REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
CHCPTR<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
CHCPTR<7:0>
Legend:

bit 15-0 CHCPTR<15:0>: Channel Cell Progress Pointer bits
1111111111111111 = 65,535 bytes have been transferred since the last event

0000000000000001 = 1 byte has been transferred since the last event
0000000000000000 = 0 bytes have been transferred since the last event
Note: When in Pattern Detect mode, this register is reset on a pattern detect.

REGISTER 10-18: DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
CHPDAT<15:8>
7:0
CHPDAT<7:0>
Legend:

bit 15-0 CHPDAT<15:0>: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match.
All other modes:

Unused.

NOTES:

11.0 HI-SPEED USB WITH ON- The USB module includes the following features:
THE-GO (OTG) USB Hi-Speed, Full-Speed, and Low-Speed
support for host and device
Note: This data sheet summarizes the USB OTG support with one or more Hi-Speed,
features of the PIC32MZ DA family of Full-Speed, or Low-Speed device
Integrated signaling resistors
complement the information in this data Integrated analog comparators for VBUS
sheet, refer to Section 51. Hi-Speed monitoring
USB with On-The-Go (OTG) Integrated USB transceiver
(DS60001326) in the PIC32 Family Transaction handshaking performed by hardware
Reference Manual, which is available Integrated 8-channel DMA to access system RAM
from the Microchip web site and Flash
(www.microchip.com/PIC32). Seven transmit endpoints and seven receive
The Universal Serial Bus (USB) module contains endpoints, in addition to Endpoint 0
analog and digital components to provide a USB 2.0 Session Request Protocol (SRP) and Host
embedded host, device, or OTG implementation with a Negotiation Protocol (HNP) support
minimum of external components. Suspend and resume signaling support
The module supports Hi-Speed, Full-Speed, or Low- Dynamic FIFO sizing
Speed in any of the operating modes. This module in Integrated RAM for the FIFOs, eliminating the
Host mode is intended for use as an embedded host need for system RAM for the FIFOs
and therefore does not implement a UHCI or OHCI Link power management support
controller.
Note 1: The implementation and use of the USB
The USB module consists of the RAM controller, specifications, as well as other third party
packet encode/decode, UTM synchronization, specifications or technologies, may
endpoint control, a dedicated USB DMA controller, pull- require licensing; including, but not
up and pull-down resistors, and the register interface. limited to, USB Implementers Forum, Inc.
A block diagram of the PIC32 USB OTG module is (also referred to as USB-IF). The user is
illustrated in Figure 11-1. fully responsible for investigating and
satisfying any applicable licensing
obligations.
2: If the USB module is used, the Primary
Oscillator (POSC) is limited to either
12 MHz or 24 MHz.

DS60001361E-page 202
FIGURE 11-1: PIC32MZ DA FAMILY USB INTERFACE DIAGRAM

USBCLK
POSC USB PLL
(12 MHz or 24 MHz only)
UPLLFSEL
Endpoint Control
DMA
EP0 EPO Transmit Requests
Control Control EP1 - EP7
Host Function Control Receive
Host Interrupt
Control Interrupts
Combine Endpoints Transaction
Scheduler EP Reg
Decoder
Common
Regs
UTM Packet RAM Controller Cycle System Bus

D+ Synchronization Encode/Decode Control Slave mode
RX RX
D- Data Sync Packet Encode Buff Buff
USB 2.0 FIFO
USBID HS PHY HS Negotiation Packet Decode Decoder
TX TX
VUSB3V3 HNP/SRP Buff Buff
CRC Gen/Check
VBUS
Timers Cycle Control
Link Power
Management
RAM
11.1 USB OTG Control Registers
TABLE 11-1: USB REGISTER MAP 1

Bits
All Resets
Bit Range
Register
Address
Virtual
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 EP7TXIF EP6TXIF EP5TXIF EP4TXIF EP3TXIF EP2TXIF EP1TXIF EP0IF 0000
SOFT
3000 USBCSR0 ISOUPD(1) SUSP FUNC<6:0>(1)
15:0 CONN(1) HSEN HSMODE RESET RESUME SUSPEN 2000
MODE
(2) (2) (2) (2) (2) (2) (2) (2) (2)
31:16 EP7TXIE EP6TXIE EP5TXIE EP4TXIE EP3TXIE EP2TXIE EP1TXIE EP0IE 00FF
3004 USBCSR1
15:0 EP7RXIF EP6RXIF EP5RXIF EP4RXIF EP3RXIF EP2RXIF EP1RXIF 0000
31:16 VBUSIE SESSRQIE DISCONIE CONNIE SOFIE RESETIE RESUMEIE SUSPIE VBUSIF SESSREQIF DISCONIF CONNIF SOFIF RESETIF RESUMEIF SUSPIF 0600
3008 USBCSR2
15:0 EP7RXIE EP6RXIE EP5RXIE EP4RXIE EP3RXIE EP2RXIE EP1RXIE 00FE
31:16 FORCEHST FIFOACC FORCEFS FORCEHS PACKET TESTK TESTJ NAK ENDPOINT<3:0> 0000
300C USBCSR3
15:0 RFRMNUM<10:0> 0000

SVC SEND SETUP SENT
(1) (1) (1) SVCRPR(1) DATAEND(1) 0000
SETEND(1) STALL(1) END(1) STALL(1) TXPKT RXPKT
USB 31:16 FLSHFIFO
3010 DATA NAK SETUP RDY RDY
IE0CSR0(3) DISPING(2) DTWREN(2) STATPKT(2) REQPKT(2) ERROR(2) RXSTALL(2) 0000
TGGL(2) TMOUT(2) PKT(2)
15:0 0000
USB 31:16 NAKLIM<4:0>(2) SPEED<1:0>(2) 0000
3018
IE0CSR2(3) 15:0 RXCNT<6:0> 0000
USB 31:16 MPRXEN MPTXEN BIGEND HBRXEN HBTXEN DYNFIFOS SOFTCONE UTMIDWID xx00
301C
IE0CSR3(3) 15:0 0000
INCOMP SENT SEND UNDER
ISO(1) (1) (1) 0000
DMA FRC DMA TX(1) STALL(1) STALL(1) RUN(1) TXPKT
USB 31:16 AUTOSET MODE CLRDT FLUSH FIFONE
3010 REQEN DATTG REQMD DATA NAK RDY
IENCSR0(4) DTWREN(2) RXSTALL(2) SETUPPKT(2) ERROR(2) 0000
TGGL(2) TMOUT(2)
15:0 MULT<4:0> TXMAXP<10:0> 0000
ISO(1) DISNYET(1) (1) (1) SENTSTALL(1) SENDSTALL(1) DATAERR(1) OVERRUN(1) 0000
DMA DMA INCOM RXPKT
USB 31:16 AUTOCLR DATA DATA CLRDT FLUSH DERR- FIFOFULL
3014 AUTORQ(2) REQEN PIDERR(2) REQMD PRX RXSTALL(2) REQPKT(2) ERROR(2) RDY 0000
IENCSR1(4) TWEN(2) TGGL(2) NAKT(1)
15:0 MULT<4:0> RXMAXP<10:0> 0000
USB 31:16 TXINTERV<7:0>(2) SPEED<1:0>(2) PROTOCOL<1:0> TEP<3:0> 0000
3018
IENCSR2(4) 15:0 RXCNT<13:0> 0000
USB 31:16 RXFIFOSZ<3:0> TXFIFOSZ<3:0> 0000
301C
IENCSR3(1,3) 15:0 RXINTERV<7:0> SPEED<1:0> PROTOCOL<1:0> TEP<3:0> 0000
DS60001361E-page 203
USB 31:16 DATA<31:16> 0000

3020
FIFO0 15:0 DATA<15:0> 0000
USB 31:16 DATA<31:16> 0000
3024
FIFO1 15:0 DATA<15:0> 0000
Note 1: Device mode.
2: Host mode.
3: Definition for Endpoint 0 (ENDPOINT<3:0> (USBCSR<19:16>) = 0).
4: Definition for Endpoints 1-7 (ENDPOINT<3:0> (USBCSR<19:16>) = 1 through 7).
DS60001361E-page 204
TABLE 11-1: USB REGISTER MAP 1 (CONTINUED)

Bits
All Resets
Bit Range
Address
Register
Virtual
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
USB 31:16 DATA<31:16> 0000

3028
FIFO2 15:0 DATA<15:0> 0000
USB 31:16 DATA<31:16> 0000
302C
FIFO3 15:0 DATA<15:0> 0000
USB 31:16 DATA<31:16> 0000
3030
FIFO4 15:0 DATA<15:0> 0000
USB 31:16 DATA<31:16> 0000
3034
FIFO5 15:0 DATA<15:0> 0000
USB 31:16 DATA<31:16> 0000
3038
FIFO6 15:0 DATA<15:0> 0000
USB 31:16 DATA<31:16> 0000
303C
FIFO7 15:0 DATA<15:0> 0000
31:16 RXDPB RXFIFOSZ<3:0> TXDPB TXFIFOSZ<3:0> 0000
3060 USBOTG
15:0 TXEDMA RXEDMA BDEV FSDEV LSDEV VBUS<1:0> HOSTMODE HOSTREQ SESSION 0088
USB 31:16 RXFIFOAD<12:0> 0000
3064
FIFOA 15:0 TXFIFOAD<12:0> 0000
USB 31:16 0000
306C
HWVER 15:0 RC VERMAJOR<4:0> VERMINOR<9:0> 0800
USB 31:16 VPLEN<7:0> WTCON<3:0> WTID<3:0> 3C5C
3078
INFO 15:0 DMACHANS<3:0> RAMBITS<3:0> RXENDPTS<3:0> TXENDPTS<3:0> 8C77
USB 31:16 NRSTX NRST LSEOF<7:0> 0072
307C
EOFRST 15:0 FSEOF<7:0> HSEOF<7:0> 7780
USB 31:16 TXHUBPRT<6:0> MULTTRAN TXHUBADD<6:0> 0000
3080
E0TXA 15:0 TXFADDR<6:0> 0000
USB 31:16 RXHUBPRT<6:0> MULTTRAN RXHUBADD<6:0> 0000
3084
E0RXA 15:0 0000
3088
E1TXA 15:0 TXFADDR<6:0> 0000
308C
E1RXA 15:0 RXFADDR<6:0> 0000
3090
E2TXA 15:0 TXFADDR<6:0> 0000
3094
E2RXA 15:0 RXFADDR<6:0> 0000
3098
E3TXA 15:0 TXFADDR<6:0> 0000
2: Host mode.
Bits
All Resets
Bit Range
Address
Register
Virtual
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

309C
E3RXA 15:0 RXFADDR<6:0> 0000
US 31:16 TXHUBPRT<6:0> MULTTRAN TXHUBADD<6:0> 0000
30A0
BE4TXA 15:0 TXFADDR<6:0> 0000
30A4
E4RXA 15:0 RXFADDR<6:0> 0000
30A8
E5TXA 15:0 TXFADDR<6:0> 0000
30AC
E5RXA 15:0 RXFADDR<6:0> 0000
30B0
E6TXA 15:0 TXFADDR<6:0>

0000
30B4
E6RXA 15:0 RXFADDR<6:0> 0000
30B8
E7TXA 15:0 TXFADDR<6:0> 0000
30BC
E7RXA 15:0 RXFADDR<6:0> 0000
USB 31:16 0000
3100 Indexed by the same bits in USBIE0CSR0
E0CSR0 15:0 0000
USB 31:16 0000
E0CSR2 15:0 0000
USB 31:16 0000
310C Indexed by the same bits in USBIE0CSR3
E0CSR3 15:0 0000
USB 31:16 0000
E1CSR0 15:0 0000
USB 31:16 0000
E1CSR1 15:0 0000
USB 31:16 0000
E1CSR2 15:0 0000
USB 31:16 0000
E1CSR3 15:0 0000
DS60001361E-page 205
USB 31:16 0000

E2CSR0 15:0 0000
USB 31:16 0000
E2CSR1 15:0 0000
2: Host mode.
DS60001361E-page 206

Bits
All Resets
Bit Range
Address
Register
Virtual
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
USB 31:16 0000

E2CSR2 15:0 0000
USB 31:16 0000
E2CSR3 15:0 0000
USB 31:16 0000
E3CSR0 15:0 0000
USB 31:16 0000
E3CSR1 15:0 0000
USB 31:16 0000
E3CSR2 15:0 0000
USB 31:16 0000
E3CSR3 15:0 0000
USB 31:16 0000
E4CSR0 15:0 0000
USB 31:16 0000
E4CSR1 15:0 0000
USB 31:16 0000
E4CSR2 15:0 0000
USB 31:16 0000
E4CSR3 15:0 0000
USB 31:16 0000
E5CSR0 15:0 0000
USB 31:16 0000
E5CSR1 15:0 0000
USB 31:16 0000
E5CSR2 15:0 0000
USB 31:16 0000

E5CSR3 15:0 0000
USB 31:16 0000
E6CSR0 15:0 0000
USB 31:16 0000
E6CSR1 15:0 0000
USB 31:16 0000
E6CSR2 15:0 0000
USB 31:16 0000
E6CSR3 15:0 0000
2: Host mode.
Bits
All Resets
Bit Range
Address
Register
Virtual
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
USB 31:16 0000

E7CSR0 15:0 0000
USB 31:16 0000
E7CSR1 15:0 0000
USB 31:16 0000
E7CSR2 15:0 0000
USB 31:16 0000
E7CSR3 15:0 0000
USB 31:16 0000
3200
DMAINT 15:0 DMA8IF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF 0000
USB 31:16 0000
3204
DMA1C 15:0 DMABRSTM<1:0> DMAERR DMAEP<3:0> DMAIE DMAMODE DMADIR DMAEN 0000

USB 31:16 DMAADDR<31:16> 0000
3208
DMA1A 15:0 DMAADDR<15:0> 0000
USB 31:16 DMACOUNT<31:16> 0000
320C
DMA1N 15:0 DMACOUNT<15:0> 0000
USB 31:16 0000
3214
USB 31:16 DMAADDR<31:16> 0000
3218
DMA2A 15:0 DMAADDR<15:0> 0000
USB 31:16 DMACOUNT<31:16> 0000
321C
USB 31:16 0000
3224
USB 31:16 DMAADDR<31:16> 0000
3228
DMA3A 15:0 DMAADDR<15:0> 0000
USB 31:16 DMACOUNT<31:16> 0000
322C
USB 31:16 0000
3234
USB 31:16 DMAADDR<31:16> 0000
3238
DMA4A 15:0 DMAADDR<15:0> 0000
DS60001361E-page 207
USB 31:16 DMACOUNT<31:16> 0000

323C
USB 31:16 0000
3244
2: Host mode.
DS60001361E-page 208

Bits
All Resets
Bit Range
Address
Register
Virtual
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
USB 31:16 DMAADDR<31:16> 0000

3248
DMA5A 15:0 DMAADDR<15:0> 0000
USB 31:16 DMACOUNT<31:16> 0000
324C
USB 31:16 0000
3254
USB 31:16 DMAADDR<31:16> 0000
3258
DMA6A 15:0 DMAADDR<15:0> 0000
USB 31:16 DMACOUNT<31:16> 0000
325C
USB 31:16 0000
3264
USB 31:16 DMAADDR<31:16> 0000
3268
DMA7A 15:0 DMAADDR<15:0> 0000
USB 31:16 DMACOUNT<31:16> 0000
326C
USB 31:16 0000
3274
USB 31:16 DMAADDR<31:16> 0000
3278
DMA8A 15:0 DMAADDR<15:0> 0000
USB 31:16 DMACOUNT<31:16> 0000
327C
USB 31:16 0000
3304
E1RPC 15:0 RQPKTCNT<15:0> 0000
USB 31:16 0000
3308
USB 31:16 0000
330C
USB 31:16 0000
3310
USB 31:16 0000
3314
USB 31:16 0000
3318
USB 31:16 0000
331C
2: Host mode.
Bits
All Resets
Bit Range
Address
Register
Virtual
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
USB 31:16 EP7TXD EP6TXD EP5TXD EP4TXD EP3TXD EP2TXD EP1TXD 0000
3340
DPBFD 15:0 EP7RXD EP6RXD EP5RXD EP4RXD EP3RXD EP2RXD EP1RXD 0000
USB 31:16 THHSRTN<15:0> 05E6
3344
TMCON1 15:0 TUCH<15:0> 4074
USB 31:16 0000
3348
TMCON2 15:0 THSBT<3:0> 0000
LPM LPM LPMNAK(1) LPMEN<1:0> 0000
USB 31:16 LPMACKIE LPMNYIE LPMSTIE LPMTOIE LPMRES LPMXMT
3360 ERRIE RESIE (2) (2) (2) 0000
LPMR1
15:0 ENDPOINT<3:0> RMTWAK HIRD<3:0> LNKSTATE<3:0> 0000
31:16 0000
USB
3364 15:0 LPMERR(1) 0000
LMPR2 LPMFADDR<6:0> LPMRES LPMNC LPMACK LPMNY LPMST
(2)

0000
2: Host mode.
TABLE 11-2: USB REGISTER MAP 2

Bits
All Resets
Bit Range
Address
Register
Virtual
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 USBIF USBRF USBWKUP 0000

USB
4000 USB USB VBUS ASVAL BSVAL SEND USB
CRCON 15:0 PHYIDEN USBIE USBRIE 0000
IDOVEN IDVAL MONEN MONEN MONEN MONEN WKUPEN
DS60001361E-page 209
REGISTER 11-1: USBCSR0: USB CONTROL STATUS REGISTER 0

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS
23:16
EP7TXIF EP6TXIF EP5TXIF EP4TXIF EP3TXIF EP2TXIF EP1TXIF EP0IF
R/W-0 R/W-0 R/W-1 R-0, HS R-0 R/W-0 R-0, HC R/W-0
15:8 ISOUPD SOFTCONN

HSEN HSMODE RESET RESUME SUSPMODE SUSPEN

7:0 FUNC<6:0>



bit 23-17 EP7TXIF:EP1TXIF: Endpoint n TX Interrupt Flag bit
1 = Endpoint has a transmit interrupt to be serviced
0 = No interrupt event
bit 16 EP0IF: Endpoint 0 Interrupt bit
1 = Endpoint 0 has an interrupt to be serviced
All EPxTX and EP0 bits are cleared when the byte is read. Therefore, these bits must be read independently
from the remaining bits in this register to avoid accidental clearing.
bit 15 ISOUPD: ISO Update bit (Device mode only; unimplemented in Host mode)
1 = USB module will wait for a SOF token from the time TXPKTRDY is set before sending the packet
0 = No change in behavior
This bit only affects endpoints performing isochronous transfers when in Device mode. This bit is
unimplemented in Host mode.
bit 14 SOFTCONN: Soft Connect/Disconnect Feature Selection bit
1 = The USB D+/D- lines are enabled and active
0 = The USB D+/D- lines are disabled and are tri-stated
This bit is only available in Device mode.
bit 13 HSEN: Hi-Speed Enable bit
1 = The USB module will negotiate for Hi-Speed mode when the device is reset by the hub
0 = Module only operates in Full-Speed mode
bit 12 HSMODE: Hi-Speed Mode Status bit
1 = Hi-Speed mode successfully negotiated during USB reset
0 = Module is not in Hi-Speed mode
In Device mode, this bit becomes valid when a USB reset completes. In Host mode, it becomes valid when
the RESET bit is cleared.
bit 11 RESET: Module Reset Status bit
1 = Reset signaling is present on the bus
0 = Normal module operation
In Device mode, this bit is read-only. In Host mode, this bit is read/write.

REGISTER 11-1: USBCSR0: USB CONTROL STATUS REGISTER 0 (CONTINUED)
bit 10 RESUME: Resume from Suspend control bit
1 = Generate Resume signaling when the device is in Suspend mode
0 = Stop Resume signaling
In Device mode, the software should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signal-
ing. In Host mode, the software should clear this bit after 20 ms.
bit 9 SUSPMODE: Suspend Mode status bit
1 = The USB module is in Suspend mode
0 = The USB module is in Normal operations
This bit is read-only in Device mode. In Host mode, it can be set by software, and is cleared by hardware.
bit 8 SUSPEN: Suspend Mode Enable bit
1 = Suspend mode is enabled
0 = Suspend mode is not enabled
bit 6-0 FUNC<6:0>: Device Function Address bits
These bits are only available in Device mode. This field is written with the address received through a
SET_ADDRESS command, which will then be used for decoding the function address in subsequent token
packets.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
EP7TXIE EP6TXIE EP5TXIE EP4TXIE EP3TXIE EP2TXIE EP1TXIE EP0IE
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS U-0
7:0
EP7RXIF EP6RXIF EP5RXIF EP4RXIF EP3RXIF EP2RXIF EP1RXIF
Legend:

bit 23-17 EP7TXIE:EP1TXIE: Endpoint n Transmit Interrupt Enable bits
1 = Endpoint Transmit interrupt events are enabled
0 = Endpoint Transmit interrupt events are not enabled
bit 16 EP0IE: Endpoint 0 Interrupt Enable bit
1 = Endpoint 0 interrupt events are enabled
0 = Endpoint 0 interrupt events are not enabled
bit 7-1 EP7RXIF:EP1RXIF: Endpoint n RX Interrupt bit
1 = Endpoint has a receive event to be serviced


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
VBUSIE SESSRQIE DISCONIE CONNIE SOFIE RESETIE RESUMEIE SUSPIE
R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS
23:16
VBUSIF SESSRQIF DISCONIF CONNIF SOFIF RESETIF RESUMEIF SUSPIF
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
EP7RXIE EP6RXIE EP5RXIE EP4RXIE EP3RXIE EP2RXIE EP1RXIE

bit 31 VBUSIE: VBUS Error Interrupt Enable bit

1 = VBUS error interrupt is enabled
0 = VBUS error interrupt is disabled
bit 30 SESSRQIE: Session Request Interrupt Enable bit
1 = Session request interrupt is enabled
0 = Session request interrupt is disabled
bit 29 DISCONIE: Device Disconnect Interrupt Enable bit
1 = Device disconnect interrupt is enabled
0 = Device disconnect interrupt is disabled
bit 28 CONNIE: Device Connection Interrupt Enable bit
1 = Device connection interrupt is enabled
0 = Device connection interrupt is disabled
bit 27 SOFIE: Start of Frame Interrupt Enable bit
1 = Start of Frame event interrupt is enabled
0 = Start of Frame event interrupt is disabled
bit 26 RESETIE: Reset/Babble Interrupt Enable bit
1 = Interrupt when reset (Device mode) or Babble (Host mode) is enabled
0 = Reset/Babble interrupt is disabled
bit 25 RESUMEIE: Resume Interrupt Enable bit
1 = Resume signaling interrupt is enabled
0 = Resume signaling interrupt is disabled
bit 24 SUSPIE: Suspend Interrupt Enable bit
1 = Suspend signaling interrupt is enabled
0 = Suspend signaling interrupt is disabled
bit 23 VBUSIF: VBUS Error Interrupt bit
1 = VBUS has dropped below the VBUS valid threshold during a session
0 = No interrupt
bit 22 SESSRQIF: Session Request Interrupt bit
1 = Session request signaling has been detected
0 = No session request detected
bit 21 DISCONIF: Device Disconnect Interrupt bit
1 = In Host mode, indicates when a device disconnect is detected. In Device mode, indicates when a
session ends.
0 = No device disconnect detected
bit 20 CONNIF: Device Connection Interrupt bit
1 = In Host mode, indicates when a device connection is detected
0 = No device connection detected

bit 19 SOFIF: Start of Frame Interrupt bit
1 = A new frame has started
0 = No start of frame detected
bit 18 RESETIF: Reset/Babble Interrupt bit
1 = In Host mode, indicates babble is detected. In Device mode, indicates reset signaling is detected on
the bus.
0 = No reset/babble detected
bit 17 RESUMEIF: Resume Interrupt bit
1 = Resume signaling is detected on the bus while USB module is in Suspend mode
0 = No Resume signaling detected
bit 16 SUSPIF: Suspend Interrupt bit
1 = Suspend signaling is detected on the bus (Device mode)
0 = No suspend signaling detected
bit 7-1 EP7RXIE:EP1RXIE: Endpoint n Receive Interrupt Enable bit
1 = Receive interrupt is enabled for this endpoint
0 = Receive interrupt is not enabled


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FORCEHST FIFOACC FORCEFS FORCEHS PACKET TESTK TESTJ NAK
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
ENDPOINT<3:0>
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
15:8
RFRMUM<10:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
RFRMNUM<7:0>

bit 31 FORCEHST: Test Mode Force Host Select bit

1 = Forces USB module into Host mode, regardless of whether it is connected to any peripheral
0 = Normal operation
bit 30 FIFOACC: Test Mode Endpoint 0 FIFO Transfer Force bit
1 = Transfers the packet in the Endpoint 0 TX FIFO to the Endpoint 0 RX FIFO
0 = No transfer
bit 29 FORCEFS: Test mode Force Full-Speed Mode Select bit
This bit is only active if FORCEHST = 1.
1 = Forces USB module into Full-Speed mode. Undefined behavior if FORCEHS = 1.
0 = If FORCEHS = 0, places USB module into Low-Speed mode.
bit 28 FORCEHS: Test mode Force Hi-Speed Mode Select bit
This bit is only active if FORCEHST = 1.
1 = Forces USB module into Hi-Speed mode. Undefined behavior if FORCEFS = 1.
0 = If FORCEFS = 0, places USB module into Low-Speed mode.
bit 27 PACKET: Test_Packet Test Mode Select bit
This bit is only active if module is in Hi-Speed mode.
1 = The USB module repetitively transmits on the bus a 53-byte test packet. Test packet must be loaded
into the Endpoint 0 FIFO before the test mode is entered.
bit 26 TESTK: Test_K Test Mode Select bit
1 = Enters Test_K test mode. The USB module transmits a continuous K on the bus.
This bit is only active if the USB module is in Hi-Speed mode.
bit 25 TESTJ: Test_J Test Mode Select bit
1 = Enters Test_J test mode. The USB module transmits a continuous J on the bus.
This bit is only active if the USB module is in Hi-Speed mode.
bit 24 NAK: Test_SE0_NAK Test Mode Select bit
1 = Enter Test_SE0_NAK test mode. The USB module remains in Hi-Speed mode but responds to any valid
IN token with a NAK
This mode is only active if module is in Hi-Speed mode.

bit 19-16 ENDPOINT<3:0>: Endpoint Registers Select bits
1111 = Reserved

1000 = Reserved
0111 = Endpoint 7

0000 = Endpoint 0
These bits select which endpoint registers are accessed through addresses 3010-301F.
bit 10-0 RFRMNUM<10:0>: Last Received Frame Number bits

REGISTER 11-5: USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0

(ENDPOINT 0)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 R/W-0 R/W-0, HC R/W-0 R/W-0, HC
31:24
FLSHFIFO
DISPING DTWREN DATATGGL
R/W-0, HC R/W-0, HC R/W-0, HC R/C-0, HS R/W-0, HS R-0, HS R-0 R-0
23:16 SVCSETEND SVCRPR SENDSTALL SETUPEND DATAEND SENTSTALL

TXPKTRDY RXPKTRDY
NAKTMOUT STATPKT REQPKT ERROR SETUPPKT RXSTALL
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0



bit 27 DISPING: Disable Ping tokens control bit (Host mode)
1 = USB Module will not issue PING tokens in data and status phases of a Hi-Speed Control transfer
0 = Ping tokens are issued
bit 26 DTWREN: Data Toggle Write Enable bit (Host mode)
1 = Enable the current state of the Endpoint 0 data toggle to be written. Automatically cleared.
0 = Disable data toggle write
bit 25 DATATGGL: Data Toggle bit (Host mode)
When read, this bit indicates the current state of the Endpoint 0 data toggle.
If DTWREN = 1, this bit is writable with the desired setting.
If DTWREN = 0, this bit is read-only.
bit 24 FLSHFIFO: Flush FIFO Control bit
1 = Flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO pointer is reset and
the TXPKTRDY/RXPKTRDY bit is cleared. Automatically cleared when the operation completes. Should
only be used when TXPKTRDY/RXPKTRDY = 1.
0 = No Flush operation
bit 23 SVCSETEND: Clear SETUPEND Control bit (Device mode)
1 = Clear the SETUPEND bit in this register. This bit is automatically cleared.
0 = Do not clear
NAKTMOUT: NAK Time-out Control bit (Host mode)

1 = Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the
NAKLIM<4:0> bits (USBICSR<28:24>)
0 = Allow the endpoint to continue
bit 22 SVCRPR: Serviced RXPKTRDY Clear Control bit (Device mode)
1 = Clear the RXPKTRDY bit in this register. This bit is automatically cleared.
0 = Do not clear
STATPKT: Status Stage Transaction Control bit (Host mode)

1 = When set at the same time as the TXPKTRDY or REQPKT bit is set, performs a status stage transaction
0 = Do not perform a status stage transaction

(ENDPOINT 0) (CONTINUED)
bit 21 SENDSTALL: Send Stall Control bit (Device mode)
1 = Terminate the current transaction and transmit a STALL handshake. This bit is automatically cleared.
0 = Do not send STALL handshake.
REQPKT: IN transaction Request Control bit (Host mode)

1 = Request an IN transaction. This bit is cleared when the RXPKTRDY bit is set.
0 = Do not request an IN transaction
bit 20 SETUPEND: Early Control Transaction End Status bit (Device mode)
1 = A control transaction ended before the DATAEND bit has been set. An interrupt will be generated and
the FIFO flushed at this time.
This bit is cleared by writing a 1 to the SVCSETEND bit in this register.
ERROR: No Response Error Status bit (Host mode)

1 = Three attempts have been made to perform a transaction with no response from the peripheral. An inter-
rupt is generated.
0 = Clear this flag. Software must write a 0 to this bit to clear it.
bit 19 DATAEND: End of Data Control bit (Device mode)
The software sets this bit when:
Setting TXPKTRDY for the last data packet
Clearing RXPKTRDY after unloading the last data packet
Setting TXPKTRDY for a zero length data packet
Hardware clears this bit.
SETUPPKT: Send a SETUP token Control bit (Host mode)

1 = When set at the same time as the TXPKTRDY bit is set, the module sends a SETUP token instead of an
OUT token for the transaction
0 = Normal OUT token operation
Setting this bit also clears the Data Toggle.
bit 18 SENTSTALL: STALL sent status bit (Device mode)
1 = STALL handshake has been transmitted
0 = Software clear of bit
RXSTALL: STALL handshake received Status bit (Host mode)

1 = STALL handshake was received
0 = Software clear of bit
bit 17 TXPKTRDY: TX Packet Ready Control bit
1 = Data packet has been loaded into the FIFO. It is cleared automatically.
0 = No data packet is ready for transmit
bit 16 RXPKTRDY: RX Packet Ready Status bit
1 = Data packet has been received. Interrupt is generated (when enabled) when this bit is set.
0 = No data packet has been received
This bit is cleared by setting the SVCRPR bit.


(ENDPOINT 0)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
NAKLIM<4:0>
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
SPEED<1:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
RXCNT<6:0>
Legend:

bit 28-24 NAKLIM<4:0>: Endpoint 0 NAK Limit bits
The number of frames/microframes (Hi-Speed transfers) after which Endpoint 0 should time-out on receiving
a stream of NAK responses.
bit 23-22 SPEED<1:0>: Operating Speed Control bits
11 = Low-Speed
10 = Full-Speed
01 = Hi-Speed
00 = Reserved
bit 6-0 RXCNT<6:0>: Receive Count bits
The number of received data bytes in the Endpoint 0 FIFO. The value returned changes as the contents of
the FIFO change and is only valid while the RXPKTRDY bit is set.


(ENDPOINT 0)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-x R-x R-0 R-x R-x R-x R-1 R-0
31:24
MPRXEN MPTXEN BIGEND HBRXEN HBTXEN DYNFIFOS SOFTCONE UTMIDWID
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:
bit 31 MPRXEN: Automatic Amalgamation Option bit

1 = Automatic amalgamation of bulk packets is done
0 = No automatic amalgamation
bit 30 MPTXEN: Automatic Splitting Option bit
1 = Automatic splitting of bulk packets is done
0 = No automatic splitting
bit 29 BIGEND: Byte Ordering Option bit
1 = Big Endian ordering
0 = Little Endian ordering
bit 28 HBRXEN: High-bandwidth RX ISO Option bit
1 = High-bandwidth RX ISO endpoint support is selected
0 = No High-bandwidth RX ISO support
bit 27 HBTXEN: High-bandwidth TX ISO Option bit
1 = High-bandwidth TX ISO endpoint support is selected
0 = No High-bandwidth TX ISO support
bit 26 DYNFIFOS: Dynamic FIFO Sizing Option bit
1 = Dynamic FIFO sizing is supported
0 = No Dynamic FIFO sizing
bit 25 SOFTCONE: Soft Connect/Disconnect Option bit
1 = Soft Connect/Disconnect is supported
0 = Soft Connect/Disconnect is not supported
bit 24 UTMIDWID: UTMI+ Data Width Option bit
Always 0, indicating 8-bit UTMI+ data width

REGISTER 11-8: USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0

(ENDPOINT 1-7)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 ISO
AUTOSET MODE DMAREQEN FRCDATTG DMAREQMD
DATAWEN DATATGGL
R/W-0, HS R/W-0, HC R/W-0, HS R/W-0 R/W-0 R/W-0, HS R/W-0 R/W-0, HC
23:16 INCOMPTX SENTSTALL SENDSTALL UNDERRUN
CLRDT FLUSH FIFONE TXPKTRDY
NAKTMOUT RXSTALL SETUPPKT ERROR
15:8
MULT<4:0> TXMAXP<10:8>
7:0
TXMAXP<7:0>
Legend:
bit 31 AUTOSET: Auto Set Control bit

1 = TXPKTRDY will be automatically set when data of the maximum packet size (value in TXMAXP) is loaded
into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TXPKTRDY will have
to be set manually.
0 = TXPKTRDY must be set manually for all packet sizes
bit 30 ISO: Isochronous TX Endpoint Enable bit (Device mode)
1 = Enables the endpoint for Isochronous transfers
0 = Disables the endpoint for Isochronous transfers and enables it for Bulk or Interrupt transfers.
This bit only has an effect in Device mode. In Host mode, it always returns zero.
bit 29 MODE: Endpoint Direction Control bit
1 = Endpoint is TX
0 = Endpoint is RX
This bit only has any effect where the same endpoint FIFO is used for both TX and RX transactions.
bit 28 DMAREQEN: Endpoint DMA Request Enable bit
1 = DMA requests are enabled for this endpoint
0 = DMA requests are disabled for this endpoint
bit 27 FRCDATTG: Force Endpoint Data Toggle Control bit
1 = Forces the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of
whether an ACK was received.
0 = No forced behavior
bit 26 DMAREQMD: Endpoint DMA Request Mode Control bit
1 = DMA Request Mode 1
This bit must not be cleared either before or in the same cycle as the DMAREQEN bit is cleared.
bit 25 DATAWEN: Data Toggle Write Enable bit (Host mode)
1 = Enable the current state of the TX Endpoint data toggle (DATATGGL) to be written
0 = Disables writing the DATATGGL bit
bit 24 DATATGGL: Data Toggle Control bit (Host mode)
When read, this bit indicates the current state of the TX Endpoint data toggle. If DATAWEN = 1, this bit may
be written with the required setting of the data toggle. If DATAWEN = 0, any value written to this bit is ignored.

(ENDPOINT 1-7) (CONTINUED)
bit 23 INCOMPTX: Incomplete TX Status bit (Device mode)
1 = For high-bandwidth Isochronous endpoint, a large packet has been split into 2 or 3 packets for
transmission but insufficient IN tokens have been received to send all the parts
In anything other than isochronous transfers, this bit will always return 0.
NAKTMOUT: NAK Time-out status bit (Host mode)

1 = TX endpoint is halted following the receipt of NAK responses for longer than the NAKLIM setting
0 = Written by software to clear this bit
bit 22 CLRDT: Clear Data Toggle Control bit
1 = Resets the endpoint data toggle to 0
0 = Do not clear the data toggle
bit 21 SENTSTALL: STALL handshake transmission status bit (Device mode)
1 = STALL handshake is transmitted. The FIFO is flushed and the TXPKTRDY bit is cleared.
RXSTALL: STALL receipt bit (Host mode)

1 = STALL handshake is received. Any DMA request in progress is stopped, the FIFO is completely flushed
and the TXPKTRDY bit is cleared.
bit 20 SENDSTALL: STALL handshake transmission control bit (Device mode)
1 = Issue a STALL handshake to an IN token
0 = Terminate stall condition
This bit has no effect when the endpoint is being used for Isochronous transfers.
SETUPPKT: Definition bit (Host mode)

1 = When set at the same time as the TXPKTRDY bit is set, send a SETUP token instead of an OUT token
for the transaction. This also clears the Data Toggle.
0 = Normal OUT token for the transaction
bit 19 FLUSH: FIFO Flush control bit
1 = Flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset, the TXPKTRDY bit is
cleared and an interrupt is generated.
0 = Do not flush the FIFO
bit 18 UNDERRUN: Underrun status bit (Device mode)
1 = An IN token has been received when the TXPKTRDY bit is not set.
0 = Written by software to clear this bit.
ERROR: Handshake failure status bit (Host mode)

1 = Three attempts have been made to send a packet and no handshake packet has been received
0 = Written by software to clear this bit.
bit 17 FIFONE: FIFO Not Empty status bit
1 = There is at least 1 packet in the TX FIFO
0 = TX FIFO is empty
bit 16 TXPKTRDY: TX Packet Ready Control bit
The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data
packet has been transmitted. This bit is also automatically cleared prior to loading a second packet into a dou-
ble-buffered FIFO.

bit 15-11 MULT<4:0>: Multiplier Control bits
For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1
for the payload size.
For Bulk endpoints, MULT can be up to 32 and defines the number of USB packets of the specified payload
into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required
to be an exact multiple of the payload specified by TXMAXP.
For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies
the maximum number of such transactions that can take place in a single microframe.
bit 10-0 TXMAXP<10:0>: Maximum TX Payload per transaction Control bits
This field sets the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the
constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in
Full-Speed and Hi-Speed operations.
TXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1.


(ENDPOINT 1-7)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HC R-0 R/W-0
31:24 ISO DISNYET
AUTOCLR DMAREQEN DMAREQMD INCOMPRX
AUTORQ PIDERR DATATWEN DATATGGL
R/W-0, HC R/W-0, HS R/W-0 R/W-0, HC R-0, HS R/W-0, HS R-0, HS, HC R/W-0, HS
23:16 SENTSTALL SENDSTALL DATAERR OVERRUN

CLRDT FLUSH FIFOFULL RXPKTRDY
RXSTALL REQPKT DERRNAKT ERROR
15:8
MULT<4:0> RXMAXP<10:8>
7:0
RXMAXP<7:0>

bit 31 AUTOCLR: RXPKTRDY Automatic Clear Control bit

1 = RXPKTRDY will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the
RX FIFO. When packets of less than the maximum packet size are unloaded, RXPKTRDY will have to be
cleared manually. When using a DMA to unload the RX FIFO, data is read from the RX FIFO in 4-byte
chunks regardless of the RXMAXP.
0 = No automatic clearing of RXPKTRDY
This bit should not be set for high-bandwidth Isochronous endpoints.
bit 30 ISO: Isochronous Endpoint Control bit (Device mode)
1 = Enable the RX endpoint for Isochronous transfers
0 = Enable the RX endpoint for Bulk/Interrupt transfers
AUTORQ: Automatic Packet Request Control bit (Host mode)

1 = REQPKT will be automatically set when RXPKTRDY bit is cleared.
0 = No automatic packet request
This bit is automatically cleared when a short packet is received.
bit 29 DMAREQEN: DMA Request Enable Control bit
1 = Enable DMA requests for the RX endpoint.
0 = Disable DMA requests for the RX endpoint.
bit 28 DISNYET: Disable NYET Handshakes Control/PID Error Status bit (Device mode)
1 = In Bulk/Interrupt transactions, disables the sending of NYET handshakes. All successfully received RX
packets are ACKed including at the point at which the FIFO becomes full.
0 = Normal operation.
In Bulk/Interrupt transactions, this bit only has any effect in Hi-Speed mode, in which mode it should be set for
all Interrupt endpoints.
PIDERR: PID Error Status bit (Host mode)

1 = In ISO transactions, this indicates a PID error in the received packet.
0 = No error
bit 27 DMAREQMD: DMA Request Mode Selection bit

bit 26 DATATWEN: Data Toggle Write Enable Control bit (Host mode)
1 = DATATGGL can be written
0 = DATATGGL is not writable
bit 25 DATATGGL: Data Toggle bit (Host mode)
When read, this bit indicates the current state of the endpoint data toggle.
If DATATWEN = 1, this bit may be written with the required setting of the data toggle.
If DATATWEN = 0, any value written to this bit is ignored.
bit 24 INCOMPRX: Incomplete Packet Status bit
1 = The packet in the RX FIFO during a high-bandwidth Isochronous/Interrupt transfer is incomplete because
parts of the data were not received
0 = Written by then software to clear this bit
In anything other than Isochronous transfer, this bit will always return 0.
bit 23 CLRDT: Clear Data Toggle Control bit
1 = Reset the endpoint data toggle to 0
0 = Leave endpoint data toggle alone
bit 22 SENTSTALL: STALL Handshake Status bit (Device mode)
1 = STALL handshake is transmitted
0 = Written by the software to clear this bit
RXSTALL: STALL Handshake Receive Status bit (Host mode)

1 = A STALL handshake has been received. An interrupt is generated.
0 = Written by the software to clear this bit
bit 21 SENDSTALL: STALL Handshake Control bit (Device mode)
1 = Issue a STALL handshake
0 = Terminate stall condition
REQPKT: IN Transaction Request Control bit (Host mode)

1 = Request an IN transaction.
0 = No request
This bit is cleared when RXPKTRDY is set.
bit 20 FLUSH: Flush FIFO Control bit
1 = Flush the next packet to be read from the endpoint RX FIFO. The FIFO pointer is reset and the
RXPKTRDY bit is cleared. This should only be used when RXPKTRDY is set. If the FIFO is double-
buffered, FLUSH may need to be set twice to completely clear the FIFO.
0 = Normal FIFO operation
This bit is automatically cleared.
bit 19 DATAERR: Data Packet Error Status bit (Device mode)
1 = The data packet has a CRC or bit-stuff error.
0 = No data error
This bit is cleared when RXPKTRDY is cleared. This bit is only valid when the endpoint is operating in ISO
mode. In Bulk mode, it always returns zero.
DERRNAKT: Data Error/NAK Time-out Status bit (Host mode)

1 = The data packet has a CRC or bit-stuff error. In Bulk mode, the RX endpoint is halted following the receipt
of NAK responses for longer than the time set as the NAK limit.
0 = No data or NAK time-out error

bit 18 OVERRUN: Data Overrun Status bit (Device mode)
1 = An OUT packet cannot be loaded into the RX FIFO.
This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero.
ERROR: No Data Packet Received Status bit (Host mode)

1 = Three attempts have been made to receive a packet and no data packet has been received. An interrupt
is generated.
0 = Written by the software to clear this bit.
This bit is only valid when the RX endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always
returns zero.
bit 17 FIFOFULL: FIFO Full Status bit
1 = No more packets can be loaded into the RX FIFO
0 = The RX FIFO has at least one free space
bit 16 RXPKTRDY: Data Packet Reception Status bit
1 = A data packet has been received. An interrupt is generated.
0 = Written by software to clear this bit when the packet has been unloaded from the RX FIFO.
bit 15-11 MULT<4:0>: Multiplier Control bits
For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1
for the payload size.
For Bulk endpoints, MULT can be up to 32 and defines the number of USB packets of the specified payload
into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required
to be an exact multiple of the payload specified by TXMAXP.
For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies
the maximum number of such transactions that can take place in a single microframe.
bit 10-0 RXMAXP<10:0>: Maximum RX Payload Per Transaction Control bits
This field sets the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the
constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in
Full-Speed and Hi-Speed operations.
RXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1.


(ENDPOINT 1-7)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
TXINTERV<7:0>
23:16
SPEED<1:0> PROTOCOL<1:0> TEP<3:0>
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
RXCNT<13:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
RXCNT<7:0>

bit 31-24 TXINTERV<7:0>: Endpoint TX Polling Interval/NAK Limit bits (Host mode)
For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk end-
points, this field sets the number of frames/microframes after which the endpoint should time out on receiving
The following table describes the valid values and interpretation for these bits:
Transfer Type Speed Valid Values (m) Interpretation

Interrupt Low/Full 0x01 to 0xFF Polling interval is m frames.
High 0x01 to 0x10 Polling interval is 2(m-1) frames.
Isochronous Full or High 0x01 to 0x10 Polling interval is 2(m-1) frames/microframes.
Bulk Full or High 0x02 to 0x10 NAK limit is 2(m-1) frames/microframes. A
value of 0 or 1 disables the NAK time-out
function.
bit 23-22 SPEED<1:0>: TX Endpoint Operating Speed Control bits (Host mode)
11 = Low-Speed
10 = Full-Speed
01 = Hi-Speed
00 = Reserved
bit 21-20 PROTOCOL<1:0>: TX Endpoint Protocol Control bits
11 = Interrupt
10 = Bulk
01 = Isochronous
00 = Control
bit 19-16 TEP<3:0>: TX Target Endpoint Number bits
This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during
device enumeration.
bit 13-0 RXCNT<13:0>: Receive Count bits
The number of received data bytes in the endpoint RX FIFO. The value returned changes as the contents of
the FIFO change and is only valid while RXPKTRDY is set.


(ENDPOINT 1-7)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-x R-x R-x R-x R-x R-x R-x R-x
31:24
RXFIFOSZ<3:0> TXFIFOSZ<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
RXINTERV<7:0>
7:0
SPEED<1:0> PROTOCOL<1:0> TEP<3:0>
Legend:
bit 31-28 RXFIFOSZ<3:0>: Receive FIFO Size bits

1111 = Reserved
1110 = Reserved
1101 = 8192 bytes
1100 = 4096 bytes

0011 = 8 bytes
0010 = Reserved
0001 = Reserved
0000 = Reserved or endpoint has not been configured
This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic
FIFO sizing is used.
bit 27-24 TXFIFOSZ<3:0>: Transmit FIFO Size bits
1111 = Reserved
1110 = Reserved
1101 = 8192 bytes
1100 = 4096 bytes

0011 = 8 bytes
0010 = Reserved
0001 = Reserved
0000 = Reserved or endpoint has not been configured
This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic
FIFO sizing is used.

bit 15-8 RXINTERV<7:0>: Endpoint RX Polling Interval/NAK Limit bits
For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk end-
points, this field sets the number of frames/microframes after which the endpoint should time out on receiving
The following table describes the valid values and meaning for this field:
Transfer Type Speed Valid Values (m) Interpretation

Interrupt Low/Full 0x01 to 0xFF Polling interval is m frames.
High 0x01 to 0x10 Polling interval is 2(m-1) frames.
Isochronous Full or High 0x01 to 0x10 Polling interval is 2(m-1) frames/microframes.
Bulk Full or High 0x02 to 0x10 NAK limit is 2(m-1) frames/microframes. A
value of 0 or 1 disables the NAK time-out
function.
bit 7-6 SPEED<1:0>: RX Endpoint Operating Speed Control bits

11 = Low-Speed
10 = Full-Speed
01 = Hi-Speed
00 = Reserved
bit 5-4 PROTOCOL<1:0>: RX Endpoint Protocol Control bits
11 = Interrupt
10 = Bulk
01 = Isochronous
00 = Control
bit 3-0 TEP<3:0>: RX Target Endpoint Number bits
This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during
device enumeration.

REGISTER 11-12: USBFIFOx: USB FIFO DATA REGISTER x (x = 0-7)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
DATA<31:24>
23:16
DATA<23:16>
15:8
DATA<15:8>
7:0
DATA<7:0>
Legend:
bit 31-0 DATA<31:0>: USB Transmit/Receive FIFO Data bits

Writes to this register loads data into the TxFIFO for the corresponding endpoint. Reading from this register
unloads data from the RxFIFO for the corresponding endpoint.
Transfers may be 8-bit, 16-bit or 32-bit as required, and any combination of access is allowed provided the
data accessed is contiguous. However, all transfers associated with one packet must be of the same width
so that data is consistently byte-, word- or double-word aligned. The last transfer may contain fewer bytes
than the previous transfers in order to complete an odd-byte or odd-word transfer.

REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
RXDPB RXFIFOSZ<3:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
TXDPB TXFIFOSZ<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
TXEDMA RXEDMA
R-1 R-0 R-0 R-0 R-0 R-0 R/W-0, HC R/W-0
7:0
BDEV FSDEV LSDEV VBUS<1:0> HOSTMODE HOSTREQ SESSION
Legend:

bit 28 RXDPB: RX Endpoint Double-packet Buffering Control bit
1 = Double-packet buffer is supported. This doubles the size set in RXFIFOSZ.
0 = Double-packet buffer is not supported
bit 27-24 RXFIFOSZ<3:0>: RX Endpoint FIFO Packet Size bits
The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth
packets prior to transmission)
1111 = Reserved

1010 = Reserved
1001 = 4096 bytes
1000 = 2048 bytes
0111 = 1024 bytes
0110 = 512 bytes
0101 = 256 bytes
0100 = 128 bytes
0011 = 64 bytes
0010 = 32 bytes
0001 = 16 bytes
0000 = 8 bytes
bit 20 TXDPB: TX Endpoint Double-packet Buffering Control bit
1 = Double-packet buffer is supported. This doubles the size set in TXFIFOSZ.
0 = Double-packet buffer is not supported

REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED)
bit 19-16 TXFIFOSZ<3:0>: TX Endpoint FIFO packet size bits
The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth
packets prior to transmission)
1111 = Reserved

1010 = Reserved
1001 = 4096 bytes
1000 = 2048 bytes
0111 = 1024 bytes
0110 = 512 bytes
0101 = 256 bytes
0100 = 128 bytes
0011 = 64 bytes
0010 = 32 bytes
0001 = 16 bytes
0000 = 8 bytes
bit 9 TXEDMA: TX Endpoint DMA Assertion Control bit
1 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP-8 bytes have been written to an
endpoint. This is Early mode.
0 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP bytes have been written to an
endpoint. This is Late mode.
bit 8 RXEDMA: RX Endpoint DMA Assertion Control bit
1 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP-8 bytes have been written to
an endpoint. This is Early mode.
0 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP bytes have been written to an
endpoint. This is Late mode.
bit 7 BDEV: USB Device Type bit
1 = USB is operating as a B device
0 = USB is operating as an A device
bit 6 FSDEV: Full-Speed/Hi-Speed device detection bit (Host mode)
1 = A Full-Speed or Hi-Speed device has been detected being connected to the port
0 = No Full-Speed or Hi-Speed device detected
bit 5 LSDEV: Low-Speed Device Detection bit (Host mode)
1 = A Low-Speed device has been detected being connected to the port
0 = No Low-Speed device detected
bit 4-3 VBUS<1:0>: VBUS Level Detection bits
11 = Above VBUS Valid
10 = Above AValid, below VBUS Valid
11 = Above Session End, below AValid
00 = Below Session End
bit 2 HOSTMODE: Host Mode bit
1 = USB module is acting as a Host
0 = USB module is not acting as a Host
bit 1 HOSTREQ: Host Request Control bit
B device only:
1 = USB module initiates the Host Negotiation when Suspend mode is entered. This bit is cleared when
Host Negotiation is completed.
0 = Host Negotiation is not taking place

REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED)
bit 0 SESSION: Active Session Control/Status bit
A device:
1 = Start a session
0 = End a session
B device:
1 = (Read) Session has started or is in progress, (Write) Initiate the Session Request Protocol
0 = When USB module is in Suspend mode, clearing this bit will cause a software disconnect
Clearing this bit when the USB module is not suspended will result in undefined behavior.

REGISTER 11-14: USBFIFOA: USB FIFO ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
RXFIFOAD<12:8>
23:16
RXFIFOAD<7:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
TXFIFOAD<12:8>
7:0
TXFIFOAD<7:0>
Legend:

bit 28-16 RXFIFOAD<12:0>: Receive Endpoint FIFO Address bits
Start address of the endpoint FIFO in units of 8 bytes as follows:
1111111111111 = 0xFFF8

0000000000010 = 0x0010
0000000000001 = 0x0008
0000000000000 = 0x0000
bit 12-0 TXFIFOAD<12:0>: Transmit Endpoint FIFO Address bits
Start address of the endpoint FIFO in units of 8 bytes as follows:
1111111111111 = 0xFFF8

0000000000010 = 0x0010
0000000000001 = 0x0008
0000000000000 = 0x0000

REGISTER 11-15: USBHWVER: USB HARDWARE VERSION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R-0 R-0 R-0 R-0 R-1 R-0 R-0 R-0
15:8
RC VERMAJOR<4:0> VERMINOR<9:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
VERMINOR<7:0>
Legend:

bit 15 RC: Release Candidate bit
1 = USB module was created using a release candidate
0 = USB module was created using a full release
bit 14-10 VERMAJOR<4:0>: USB Module Major Version number bits
This read-only number is the Major version number for the USB module.
bit 9-0 VERMINOR<9:0>: USB Module Minor Version number bits
This read-only number is the Minor version number for the USB module.

REGISTER 11-16: USBINFO: USB INFORMATION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
VPLEN<7:0>
23:16
WTCON<3:0> WTID<3:0>
R-1 R-0 R-0 R-0 R-1 R-1 R-0 R-0
15:8
DMACHANS<3:0> RAMBITS<3:0>
R-0 R-1 R-1 R-1 R-0 R-1 R-1 R-1
7:0
RXENDPTS<3:0> TXENDPTS<3:0>
Legend:
bit 31-24 VPLEN<7:0>: VBUS pulsing charge length bits

Sets the duration of the VBUS pulsing charge in units of 546.1 s. (The default setting corresponds to 32.77
ms.)
bit 23-20 WTCON<3:0>: Connect/Disconnect filter control bits
Sets the wait to be applied to allow for the connect/disconnect filter in units of 533.3 ns. The default setting
corresponds to 2.667 s.
bit 19-6 WTID<3:0>: ID delay valid control bits
Sets the delay to be applied from IDPULLUP being asserted to IDDIG being considered valid in units of
4.369ms. The default setting corresponds to 52.43ms.
bit 15-12 DMACHANS<3:0>: DMA Channels bits
These read-only bits provide the number of DMA channels in the USB module. For the PIC32MZ DA family,
this number is 8.
bit 11-8 RAMBITS<3:0>: RAM address bus width bits
These read-only bits provide the width of the RAM address bus. For the PIC32MZ DA family, this number is
12.
bit 7-4 RXENDPTS<3:0>: Included RX Endpoints bits
This read-only register gives the number of RX endpoints in the design. For the PIC32MZ DA family, this
number is 7.
bit 3-0 TXENDPTS<3:0>: Included TX Endpoints bits
These read-only bits provide the number of TX endpoints in the design. For the PIC32MZ DA family, this
number is 7.

REGISTER 11-17: USBEOFRST: USB END-OF-FRAME/SOFT RESET CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
31:24
NRSTX NRST
R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R.W-0 R/W-1 R/W-0
23:16
LSEOF<7:0>
15:8
FSEOF<7:0>
7:0
HSEOF<7:0>
Legend:

bit 25 NRSTX: Reset of XCLK Domain bit
1 = Reset the XCLK domain, which is clock recovered from the received data by the PHY
bit 24 NRST: Reset of CLK Domain bit
1 = Reset the CLK domain, which is clock recovered from the peripheral bus
bit 23-16 LSEOF<7:0>: Low-Speed EOF bits
These bits set the Low-Speed transaction in units of 1.067 s (default setting is 121.6 s) prior to the EOF
to stop new transactions from beginning.
bit 15-8 FSEOF<7:0>: Full-Speed EOF bits
These bits set the Full-Speed transaction in units of 533.3 s (default setting is 63.46 s) prior to the EOF
to stop new transactions from beginning.
bit 7-0 HSEOF<7:0>: Hi-Speed EOF bits
These bits set the Hi-Speed transaction in units of 133.3 s (default setting is 17.07s) prior to the EOF to
stop new transactions from beginning.

REGISTER 11-18: USBExTXA: USB ENDPOINT x TRANSMIT ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
TXHUBPRT<6:0>
23:16
MULTTRAN TXHUBADD<6:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
TXFADDR<6:0>
Legend:

bit 30-24 TXHUBPRT<6:0>: TX Hub Port bits (Host mode)
When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, this
field records the port number of that USB 2.0 hub.
bit 23 MULTTRAN: TX Hub Multiple Translators bit (Host mode)
1 = The USB 2.0 hub has multiple transaction translators
0 = The USB 2.0 hub has a single transaction translator
bit 22-16 TXHUBADD<6:0>: TX Hub Address bits (Host mode)
When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, these
bits record the address of the USB 2.0 hub.
bit 6-0 TXFADDR<6:0>: TX Functional Address bits (Host mode)
Specifies the address for the target function that is be accessed through the associated endpoint. It needs
to be defined for each TX endpoint that is used.

REGISTER 11-19: USBExRXA: USB ENDPOINT x RECEIVE ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
RXHUBPRT<6:0>
23:16
MULTTRAN RXHUBADD<6:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
RXFADDR<6:0>


bit 30-24 RXHUBPRT<6:0>: RX Hub Port bits (Host mode)
When a Low- Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, this field
records the port number of that USB 2.0 hub.
bit 23 MULTTRAN: RX Hub Multiple Translators bit (Host mode)
1 = The USB 2.0 hub has multiple transaction translators
0 = The USB 2.0 hub has a single transaction translator
bit 22-16 TXHUBADD<6:0>: RX Hub Address bits (Host mode)
When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, these
bits record the address of the USB 2.0 hub.
bit 6-0 RXFADDR<6:0>: RX Functional Address bits (Host mode)
Specifies the address for the target function that is be accessed through the associated endpoint. It needs to
be defined for each RX endpoint that is used.

REGISTER 11-20: USBDMAINT: USB DMA INTERRUPT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
DMA8IF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF
Legend:

bit 7-0 DMAxIF: DMA Channel x Interrupt bit
1 = The DMA channel has an interrupt event
All bits are cleared on a read of the register.

REGISTER 11-21: USBDMAxC: USB DMA CHANNEL x CONTROL REGISTER (x = 1-8)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
DMABRSTM<1:0> DMAERR
7:0
DMAEP<3:0> DMAIE DMAMODE DMADIR DMAEN
Legend:

bit 10-9 DMABRSTM<1:0>: DMA Burst Mode Selection bit
11 = Burst Mode 3: INCR16, INCR8, INCR4 or unspecified length
10 = Burst Mode 2: INCR8, INCR4 or unspecified length
01 = Burst Mode 1: INCR4 or unspecified length
00 = Burst Mode 0: Bursts of unspecified length
bit 8 DMAERR: Bus Error bit
1 = A bus error has been observed on the input
0 = The software writes this to clear the error
bit 7-4 DMAEP<3:0>: DMA Endpoint Assignment bits
These bits hold the endpoint that the DMA channel is assigned to. Valid values are 0-7.
bit 3 DMAIE: DMA Interrupt Enable bit
1 = Interrupt is enabled for this channel
0 = Interrupt is disabled for this channel
bit 2 DMAMODE: DMA Transfer Mode bit
1 = DMA Mode1 Transfers
0 = DMA Mode0 Transfers
bit 1 DMADIR: DMA Transfer Direction bit
1 = DMA Read (TX endpoint)
0 = DMA Write (RX endpoint)
bit 0 DMAEN: DMA Enable bit
1 = Enable the DMA transfer and start the transfer
0 = Disable the DMA transfer

REGISTER 11-22: USBDMAxA: USB DMA CHANNEL x MEMORY ADDRESS REGISTER (x = 1-8)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
DMAADDR<31:24>
23:16
DMAADDR<23:16>
15:8
DMAADDR<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0
7:0
DMAADDR<7:0>
Legend:
bit 31-0 DMAADDR<31:0>: DMA Memory Address bits

This register identifies the current memory address of the corresponding DMA channel. The initial memory
address written to this register during initialization must have a value such that its modulo 4 value is equal
to 0. The lower two bits of this register are read only and cannot be set by software. As the DMA transfer
progresses, the memory address will increment as bytes are transferred.
REGISTER 11-23: USBDMAxN: USB DMA CHANNEL x COUNT REGISTER (X = 1-8)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
DMACOUNT<31:24>
23:16
DMACOUNT<23:16>
15:8
DMACOUNT<15:8>
7:0
DMACOUNT<7:0>
Legend:
bit 31-0 DMACOUNT<31:0>: DMA Transfer Count bits

This register identifies the current DMA count of the transfer. Software will set the initial count of the transfer
which identifies the entire transfer length. As the count progresses this count is decremented as bytes are
transferred.

REGISTER 11-24: USBExRPC: USB ENDPOINT x REQUEST PACKET COUNT REGISTER (HOST
MODE ONLY) (x = 1-7)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
RQPKTCNT<15:8>
7:0
RQPKTCNT<7:0>
Legend:

bit 15-0 RQPKTCNT<15:0>: Request Packet Count bits
Sets the number of packets of size MAXP that are to be transferred in a block transfer. This register is only
available in Host mode when AUTOREQ is set.
REGISTER 11-25: USBDPBFD: USB DOUBLE PACKET BUFFER DISABLE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
EP7TXD EP6TXD EP5TXD EP4TXD EP3TXD EP2TXD EP1TXD
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
EP7RXD EP6RXD EP5RXD EP4RXD EP3RXD EP2RXD EP1RXD
Legend:
bit 31-17 EP7TXD:EP1TXD: TX Endpoint x Double Packet Buffer Disable bits

1 = TX double packet buffering is disabled for endpoint x
0 = TX double packet buffering is enabled for endpoint x
bit 15-1 EP7RXD:EP1RXD: RX Endpoint x Double Packet Buffer Disable bits
1 = RX double packet buffering is disabled for endpoint x
0 = RX double packet buffering is enabled for endpoint x

REGISTER 11-26: USBTMCON1: USB TIMING CONTROL REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
THHSRTN<15:8>
23:16
THHSRTN<7:0>
15:8
TUCH<15:8>
7:0
TUCH<7:0>
Legend:
bit 31-16 THHSRTN:<15:0>: Hi-Speed Resume Signaling Delay bits

These bits set the delay from the end of Hi-Speed resume signaling (acting as a Host) to enable the UTM
normal operating mode.
bit 15-0 TUCH<15:0>: Chirp Time-out bits
These bits set the chirp time-out. This number, when multiplied by 4, represents the number of USB module
clock cycles before the time-out occurs.
Note: Use of this register will allow the Hi-Speed time-out to be set to values that are greater than the maximum
specified in the USB 2.0 specification, making the USB module non-compliant.
REGISTER 11-27: USBTMCON2: USB TIMING CONTROL REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
THBST<3:0>
Legend:

bit 3-0 THBST<3:0>: High Speed Time-out Adder bits
These bits represent the value to be added to the minimum high speed time-out period of 736 bit times. The
time-out period can be increased in increments of 64 Hi-Speed bit times (133 ns).
Note: Use of this register will allow the Hi-Speed time-out to be set to values that are greater than the maximum
specified in the USB 2.0 specification, making the USB module non-compliant.

REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL

REGISTER 1
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
LPMERRIE LPMRESIE LPMACKIE LPMNYIE LPMSTIE LPMTOIE
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC
23:16
LPMNAK LPMEN<1:0> LPMRES LPMXMT
R-0 R-0 R-0 R-0 U-0 U-0 U-0 R-0
15:8
ENDPOINT<3:0> RMTWAK
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
HIRD<3:0> LNKSTATE<3:0>


bit 29 LPMERRIE: LPM Error Interrupt Enable bit
1 = LPMERR interrupt is enabled
0 = LPMERR interrupt is disabled
bit 28 LPMRESIE: LPM Resume Interrupt Enable bit
1 = LPMRES interrupt is enabled
0 = LPMRES interrupt is disabled
bit 27 LPMACKIE: LPM Acknowledge Interrupt Enable bit
1 = Enable the LPMACK Interrupt
0 = Disable the LPMACK Interrupt
bit 26 LPMNYIE: LPM NYET Interrupt Enable bit
1 = Enable the LPMNYET Interrupt
0 = Disable the LPMNYET Interrupt
bit 25 LPMSTIE: LPM STALL Interrupt Enable bit
1 = Enable the LPMST Interrupt
0 = Disable the LPMST Interrupt
bit 24 LPMTOIE: LPM Time-out Interrupt Enable bit
1 = Enable the LPMTO Interrupt
0 = Disable the LPMTO Interrupt
bit 20 LPMNAK: LPM-only Transaction Setting bit
1 = All endpoints will respond to all transactions other than a LPM transaction with a NAK
0 = Normal transaction operation
Setting this bit to 1 will only take effect after the USB module as been LPM suspended.
bit 19-18 LPMEN<1:0>: LPM Enable bits (Device mode)
11 = LPM Extended transactions are supported
10 = LPM and Extended transactions are not supported
01 = LPM mode is not supported but Extended transactions are supported
00 = LPM Extended transactions are supported
bit 17 LPMRES: LPM Resume bit
1 = Initiate resume (remote wake-up). Resume signaling is asserted for 50 s.
0 = No resume operation
This bit is self-clearing.

REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL
REGISTER 1 (CONTINUED)
bit 16 LPMXMT: LPM Transition to the L1 State bit
When in Device mode:
1 = USB module will transition to the L1 state upon the receipt of the next LPM transaction. LPMEN must
be set to 0b11. Both LPMXMT and LPMEN must be set in the same cycle.
0 = Maintain current state
When LPMXMT and LPMEN are set, the USB module can respond in the following ways:
If no data is pending (all TX FIFOs are empty), the USB module will respond with an ACK. The bit will
self clear and a software interrupt will be generated.
If data is pending (data resides in at least one TX FIFO), the USB module will respond with a NYET. In
this case, the bit will not self clear however a software interrupt will be generated.
When in Host mode:

1 = USB module will transmit an LPM transaction. This bit is self clearing, and will be immediately cleared
upon receipt of any Token or three time-outs have occurred.
0 = Maintain current state
bit 15-12 ENDPOINT<3:0>: LPM Token Packet Endpoint bits
This is the endpoint in the token packet of the LPM transaction.
bit 8 RMTWAK: Remote Wake-up Enable bit
This bit is applied on a temporary basis only and is only applied to the current suspend state.
1 = Remote wake-up is enabled
0 = Remote wake-up is disabled
bit 7-4 HIRD<3:0>: Host Initiated Resume Duration bits
The minimum time the host will drive resume on the bus. The value in this register corresponds to an actual
resume time of:
Resume Time = 50 s + HIRD * 75 s. The resulting range is 50 s to 1200 s.
bit 3-0 LNKSTATE<3:0>: Link State bits
This value is provided by the host to the peripheral to indicate what state the peripheral must transition to
after the receipt and acceptance of a LPM transaction. The only valid value for this register is 1 for Sleep
State (L1). All other values are reserved.

REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
LPMFADDR<6:0>
U-0 U-0 R-0 R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS
7:0
LPMERRIF LPMRESIF LPMNCIF LPMACKIF LPMNYIF LPMSTIF


bit 14-8 LPMFADDR<6:0>: LPM Payload Function Address bits
These bits contain the address of the LPM payload function.
bit 5 LPMERRIF: LPM Error Interrupt Flag bit (Device mode)
1 = An LPM transaction was received that had a LINKSTATE field that is not supported. The response will
be a STALL.
0 = No error condition
bit 4 LPMRESIF: LPM Resume Interrupt Flag bit
1 = The USB module has resumed (for any reason)
0 = No Resume condition
bit 3 LPMNCIF: LPM NC Interrupt Flag bit
1 = The USB module received a LPM transaction and responded with a NYET due to data pending in the
RX FIFOs.
0 = No NC interrupt condition
When in Host mode:

1 = A LPM transaction is transmitted and the device responded with an ACK
0 = No NC interrupt condition
bit 2 LPMACKIF: LPM ACK Interrupt Flag bit
1 = A LPM transaction was received and the USB Module responded with an ACK
0 = No ACK interrupt condition
When in Host mode:

1 = The LPM transaction is transmitted and the device responds with an ACK
0 = No ACK interrupt condition
bit 1 LPMNYIF: LPM NYET Interrupt Flag bit
1 = A LPM transaction is received and the USB Module responded with a NYET
0 = No NYET interrupt flag
When in Host mode:

1 = A LPM transaction is transmitted and the device responded with an NYET
0 = No NYET interrupt flag

REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2
bit 0 LPMSTIF: LPM STALL Interrupt Flag bit
1 = A LPM transaction was received and the USB Module responded with a STALL
0 = No Stall condition
When in Host mode:

1 = A LPM transaction was transmitted and the device responded with a STALL
0 = No Stall condition

REGISTER 11-30: USBCRCON: USB CLOCK/RESET CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R/W-1, HS
31:24
USBIF USBRF USBWKUP
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

r-1 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8 USB USB

IDOVEN IDVAL
7:0 VBUS ASVAL BSVAL SEND USB
PHYIDEN USBIE USBRIE
MONEN MONEN MONEN MONEN WKUPEN
Legend:

bit 26 USBIF: USB General Interrupt Flag bit
1 = An event on the USB Bus has occurred
0 = No interrupt from USB module or interrupts have not been enabled
bit 25 USBRF: USB Resume Flag bit
1 = Resume from Suspend state. Device wake-up activity can be started.
0 = No Resume activity detected during Suspend, or not in Suspend state
bit 24 USBWKUP: USB Activity Status bit
1 = Connect, disconnect, or other activity on USB detected since last cleared
0 = No activity detected on USB
Note: This bit should be cleared just prior to entering sleep, but it should be checked that no activity
has already occurred on USB before actually entering sleep.
bit 15 Reserved: Read as 1
bit 9 USBIDOVEN: USB ID Override Enable bit
1 = Enable use of USBIDVAL bit
0 = Disable use of USBIDVAL and instead use the PHY value
bit 8 USBIDVAL: USB ID Value bit
1 = ID override value is 1
0 = ID override value is 0
bit 7 PHYIDEN: PHY ID Monitoring Enable bit
1 = Enable monitoring of the ID bit from the USB PHY
0 = Disable monitoring of the ID bit from the USB PHY
bit 6 VBUSMONEN: VBUS Monitoring for OTG Enable bit
1 = Enable monitoring for VBUS in VBUS Valid range (between 4.4V and 4.75V)
0 = Disable monitoring for VBUS in VBUS Valid range
bit 5 ASVALMONEN: A-Device VBUS Monitoring for OTG Enable bit
1 = Enable monitoring for VBUS in Session Valid range for A-device (between 0.8V and 2.0V)
0 = Disable monitoring for VBUS in Session Valid range for A-device
bit 4 BSVALMONEN: B-Device VBUS Monitoring for OTG Enable bit
1 = Enable monitoring for VBUS in Session Valid range for B-device (between 0.8V and 4.0V)
0 = Disable monitoring for VBUS in Session Valid range for B-device

REGISTER 11-30: USBCRCON: USB CLOCK/RESET CONTROL REGISTER (CONTINUED)
bit 3 SENDMONEN: Session End VBUS Monitoring for OTG Enable bit
1 = Enable monitoring for VBUS in Session End range (between 0.2V and 0.8V)
0 = Disable monitoring for VBUS in Session End range
bit 2 USBIE: USB General Interrupt Enable bit
1 = Enables general interrupt from USB module
0 = Disables general interrupt from USB module
bit 1 USBRIE: USB Resume Interrupt Enable bit
1 = Enable remote resume from suspend Interrupt
0 = Disable interrupt to a Remote Devices USB resume signaling
bit 0 USBWKUPEN: USB Activity Detection Interrupt Enable bit
1 = Enable interrupt for detection of activity on USB bus in Sleep mode
0 = Disable interrupt for detection of activity on USB bus in Sleep mode

12.0 I/O PORTS Some of the key features of the I/O ports are as follows:
Individual output pin open-drain enable/disable
Individual input pin weak pull-up and pull-down
devices. It is not intended to be a Monitor selective inputs and generate interrupt
comprehensive reference source. To when change in pin state is detected
complement the information in this data Operation during Sleep and Idle modes
sheet, refer to Section 12. I/O Ports Fast bit manipulation using CLR, SET, and INV
(DS60001120), which is available from the registers
Documentation > Reference Manual Figure 12-1 illustrates a block diagram of a typical
section of the Microchip PIC32 web site multiplexed I/O port.
General purpose I/O pins are the simplest of

peripherals. They allow the PIC32MZ DA family device
to monitor and control other devices. To add flexibility
and functionality, some pins are multiplexed with
alternate function(s). These functions depend on which
peripheral features are on the device. In general, when
a peripheral is functioning, that pin may not be used as
a general purpose I/O pin.
FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE

Peripheral Module
Peripheral Module Enable
Port Control
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
PBCLK4
Data Bus D Q
PBCLK4 CK ODC
EN Q
WR ODC
1 I/O Cell
RD TRIS 0
0
1
D Q
TRIS 1
CK
EN Q 0
WR TRIS
Output Multiplexers
D Q
CK LAT I/O Pin
EN Q
WR LAT
WR PORT
RD LAT SRCON0x
1 SRCON1x
RD PORT
0 Q D Q D
Sleep Q CK Q CK
PBCLK4
Synchronization
Peripheral Input R
Peripheral Input Buffer
Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
Note: This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.

12.1 Parallel I/O (PIO) Ports 12.1.4 INPUT CHANGE NOTIFICATION
All port pins have ten registers directly associated with The input change notification function of the I/O ports
their operation as digital I/O. The data direction register allows the PIC32MZ DA devices to generate interrupt
(TRISx) determines whether the pin is an input or an requests to the processor in response to a change-of-
output. If the data direction bit is a 1, then the pin is an state on selected input pins. This feature can detect
input change-of-states even in Sleep mode, when the
input. All port pins are defined as inputs after a Reset.
clocks are disabled. Every I/O port pin can be selected
Reads from the latch (LATx) read the latch. Writes to
(enabled) for generating an interrupt request on a
the latch write the latch. Reads from the port (PORTx)
change-of-state.
read the port pins, while writes to the port pins write the
latch. Five control registers are associated with the CN
functionality of each I/O port. The CNENx/CNNEx
12.1.1 OPEN-DRAIN CONFIGURATION registers contain the CN interrupt enable control bits
for each of the input pins. Setting any of these bits
In addition to the PORTx, LATx, and TRISx registers for enables a CN interrupt for the corresponding pins.
data control, some port pins can also be individually CNENx enables a mismatch CN interrupt condition
configured for either digital or open-drain output. This is when the EDGEDETECT bit (CNCONx<11>) is not
controlled by the Open-Drain Control register, ODCx, set. When the EDGEDETECT bit is set, CNNEx
associated with each port. Setting any of the bits con- controls the negative edge while CNENx controls the
figures the corresponding pin to act as an open-drain positive.
output. The CNSTATx/CNFx registers indicate the status of
The open-drain feature allows the generation of out- change notice based on the setting of the
puts higher than VDDIO (e.g., 5V) on any desired 5V-tol- EDGEDETECT bit. If the EDGEDETECT bit is set to
erant pins by using external pull-up resistors. The 0, the CNSTATx register indicates whether a change
maximum open-drain voltage allowed is the same as occurred on the corresponding pin since the last read
the maximum VIH specification. of the PORTx bit. If the EDGEDETECT bit is set to 1,
the CNFx register indicates whether a change has
Refer to the pin name tables (Table 5 and Table 7) for occurred and through the CNNEx/CNENx registers
the available pins and their functionality. the edge type of the change that occurred is also
indicated.
12.1.2 CONFIGURING ANALOG AND
Each I/O pin also has a weak pull-up and a weak
DIGITAL PORT PINS
pull-down connected to it. The pull-ups act as a
The ANSELx register controls the operation of the current source or sink source connected to the pin,
analog port pins. The port pins that are to function as and eliminate the need for external resistors when
analog inputs must have their corresponding ANSEL push-button or keypad devices are connected. The
and TRIS bits set. In order to use port pins for I/O pull-ups and pull-downs are enabled separately using
functionality with digital modules, such as Timers, the CNPUx and the CNPDx registers, which contain
UARTs, etc., the corresponding ANSELx bit must be the control bits for each of the pins. Setting any of
cleared. the control bits enables the weak pull-ups and/or
pull-downs for the corresponding pins.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are Note: Pull-ups and pull-downs on change
analog (not digital) by default. notification pins should always be
If the TRIS bit is cleared (output) while the ANSELx bit disabled when the port pin is configured as
is set, the digital output level (VOH or VOL) is converted a digital output.
by an analog peripheral, such as the ADC module or An additional control register (CNCONx) is shown in
Comparator module. Register 12-3.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
12.2 CLR, SET, and INV Registers
Pins configured as digital inputs do not convert an Every I/O module register has a corresponding CLR
analog input. Analog levels on any pin defined as a (clear), SET (set) and INV (invert) register designed to
digital input (including the ANx pins) can cause the provide fast atomic bit manipulations. As the name of
input buffer to consume current that exceeds the the register implies, a value written to a SET, CLR or
device specifications. INV register effectively performs the implied operation,
but only on the corresponding base register and only
12.1.3 I/O PORT WRITE/READ TIMING bits specified as 1 are modified. Bits specified as 0
are not modified.
One instruction cycle is required between a port
direction change or port write operation and a read Reading SET, CLR and INV registers returns undefined
operation of the same port. Typically this instruction values. To see the affects of a write operation to a SET,
would be an NOP. CLR or INV register, the base register must be read.

12.3 Slew Rate Registers 12.4.2 AVAILABLE PERIPHERALS
Each I/O pin can be configured for various types of The peripherals managed by the PPS are all digital-
slew rate control on its associated port. This is con- only peripherals. These include general serial
trolled by the Slew Rate Control bits in the SRCON1x communications (UART, SPI, and CAN), general pur-
and SRCON0x registers that are associated with each pose timer clock inputs, timer-related peripherals (input
I/O port. capture and output compare), interrupt-on-change
inputs, and reference clocks (input and output).
12.4 Peripheral Pin Select (PPS) In comparison, some digital-only peripheral modules
are never included in the PPS feature. This is because
A major challenge in general purpose devices is provid- the peripherals function requires special I/O circuitry
ing the largest possible set of peripheral features while on a specific port and cannot be easily connected to
minimizing the conflict of features on I/O pins. The chal- multiple pins. These modules include I2C among oth-
lenge is even greater on low pin-count devices. In an ers. A similar requirement excludes all modules with
application where more than one peripheral needs to analog inputs, such as the Analog-to-Digital Converter
be assigned to a single pin, inconvenient workarounds (ADC).
in application code or a complete redesign may be the
only option. A key difference between remappable and non-remap-
pable peripherals is that remappable peripherals are
PPS configuration provides an alternative to these not associated with a default I/O pin. The peripheral
choices by enabling peripheral set selection and their must always be assigned to a specific I/O pin before it
placement on a wide range of I/O pins. By increasing can be used. In contrast, non-remappable peripherals
the pinout options available on a particular device, are always available on a default pin, assuming that the
users can better tailor the device to their entire peripheral is active and not conflicting with another
application, rather than trimming the application to fit peripheral.
the device.
When a remappable peripheral is active on a given I/O
The PPS configuration feature operates over a fixed pin, it takes priority over all other digital I/O and digital
subset of digital I/O pins. Users may independently communication peripherals associated with the pin.
map the input and/or output of most digital peripherals Priority is given regardless of the type of peripheral that
to these I/O pins. PPS is performed in software and is mapped. Remappable peripherals never take priority
generally does not require the device to be repro- over any analog functions associated with the pin.
grammed. Hardware safeguards are included that pre-
vent accidental or spurious changes to the peripheral 12.4.3 CONTROLLING PPS
mapping once it has been established.
PPS features are controlled through two sets of SFRs:
12.4.1 AVAILABLE PINS one to map peripheral inputs, and one to map outputs.
Because they are separately controlled, a particular
The number of available pins is dependent on the peripherals input and output (if the peripheral has both)
particular device and its pin count. Pins that support the can be placed on any selectable function pin without
PPS feature include the designation RPn in their full constraint.
pin designation, where RP designates a remappable
peripheral and n is the remappable port number. The association of a peripheral to a peripheral-select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.

12.4.4 INPUT MAPPING
The inputs of the PPS options are mapped on the basis
of the peripheral. That is, a control register associated
with a peripheral dictates the pin it will be mapped to.
The [pin name]R registers, where [pin name] refers to the
peripheral pins listed in Table 12-1, are used to config-
ure peripheral input mapping (see Register 12-1). Each
register contains sets of 4 bit fields. Programming these
bit fields with an appropriate value maps the RPn pin
with the corresponding value to that peripheral. For any
given device, the valid range of values for any bit field is
shown in Table 12-1.
For example, Figure 12-2 illustrates the remappable
pin selection for the U1RX input.
FIGURE 12-2: REMAPPABLE INPUT

EXAMPLE FOR U1RX
U1RXR<3:0>
0
RPD2
1
RPG8
2 U1RX input
RPF4 to peripheral
n
RPn
Note: For input only, PPS functionality does not

have priority over TRISx settings. Therefore,
when configuring RPn pin for input, the
corresponding bit in the TRISx register must
also be configured for input (set to 1).

TABLE 12-1: INPUT PIN SELECTION

[pin name]R Value to
Peripheral Pin [pin name]R SFR [pin name]R bits
RPn Pin Selection
INT3 INT3R INT3R<3:0> 0000 = RPD2

T2CK T2CKR T2CKR<3:0> 0001 = RPG8
T6CK T6CKR T6CKR<3:0> 0010 = RPF4

0011 = Reserved
IC3 IC3R IC3R<3:0>
0100 = RPF1
IC7 IC7R IC7R<3:0>
0101 = RPB9
U1RX U1RXR U1RXR<3:0> 0110 = RPB10
U2CTS U2CTSR U2CTSR<3:0> 0111 = RPC14
U5RX U5RXR U5RXR<3:0> 1000 = RPB5
U6CTS U6CTSR U6CTSR<3:0> 1001 = Reserved

1010 = RPC1
SDI1 SDI1R SDI1R<3:0>
1011 = RPD14
1100 = RPG1
SDI5 SDI5R SDI5R<3:0> 1101 = RPA14
SS6 SS6R SS6R<3:0> 1110 = RPD6
REFCLKI1 REFCLKI1R REFCLKI1R<3:0> 1111 = Reserved

0001 = RPG7
T5CK T5CKR T5CKR<3:0>
0010 = RPF5
T7CK T7CKR T7CKR<3:0> 0011 = RPD11
0100 = RPF0
IC4 IC4R IC4R<3:0>
0101 = RPB1
IC8 IC8R IC8R<3:0> 0110 = RPE5
0111 = RPC13
U3RX U3RXR U3RXR<3:0>
1000 = RPB3
U4CTS U4CTSR U4CTSR<3:0> 1001 = Reserved
1010 = RPC4
1011 = Reserved
SDI4 SDI4R SDI4R<3:0> 1100 = RPG0
1101 = RPA15
C1RX C1RXR C1RXR<3:0>
1110 = RPD7

TABLE 12-1: INPUT PIN SELECTION (CONTINUED)
[pin name]R Value to
Peripheral Pin [pin name]R SFR [pin name]R bits
RPn Pin Selection

T3CK T3CKR T3CKR<3:0> 0001 = Reserved
T8CK T8CKR T8CKR<3:0> 0010 = RPB8

0011 = RPB15
IC2 IC2R IC2R<3:0>
0100 = RPD4
IC5 IC5R IC5R<3:0>
0101 = RPB0
IC9 IC9R IC9R<3:0> 0110 = RPE3
U1CTS U1CTSR U1CTSR<3:0> 0111 = RPB7
U2RX U2RXR U2RXR<3:0> 1000 = Reserved
U5CTS U5CTSR U5CTSR<3:0> 1001 = RPF12

1010 = RPD12
SS1 SS1R SS1R<3:0>
1011 = RPF8
SS3 SS3R SS3R<3:0>
1100 = RPC3
SS4 SS4R SS4R<3:0> 1101 = RPE9
SS5 SS5R SS5R<3:0> 1110 = Reserved
C2RX C2RXR C2RXR<3:0> 1111 = Reserved
INT1 INT1R INT1R<3:0> 0000 = Reserved

T4CK T4CKR T4CKR<3:0> 0001 = RPG9
0010 = Reserved
T9CK T9CKR T9CKR<3:0> 0011 = RPD0
IC1 IC1R IC1R<3:0> 0100 = Reserved
0101 = RPB6
IC6 IC6R IC6R<3:0>
0110 = RPD5
U3CTS U3CTSR U3CTSR<3:0> 0111 = RPB2
U4RX U4RXR U4RXR<3:0> 1000 = RPF3
1001 = Reserved
U6RX U6RXR U6RXR<3:0>
1010 = Reserved
SS2 SS2R SS2R<3:0> 1011 = RPF2
1100 = RPC2
1101 = RPE8
OCFA OCFAR OCFAR<3:0> 1110 = Reserved

12.4.5 OUTPUT MAPPING 12.4.6.1 Control Register Lock
In contrast to inputs, the outputs of the PPS options Under normal operation, writes to the RPnR and [pin
are mapped on the basis of the pin. In this case, a name]R registers are not allowed. Attempted writes
control register associated with a particular pin appear to execute normally, but the contents of the
dictates the peripheral output to be mapped. The registers remain unchanged. To change these regis-
RPnR registers (Register 12-2) are used to control ters, they must be unlocked in hardware. The regis-
output mapping. Like the [pin name]R registers, each ter lock is controlled by the IOLOCK Configuration bit
register contains sets of 4 bit fields. The value of the (CFGCON<13>). Setting the IOLOCK bit prevents
bit field corresponds to one of the peripherals, and writes to the control registers and clearing the
that peripherals output is mapped to the pin (see IOLOCK bit allows writes.
Table 12-2 and Figure 12-3). To set or clear the IOLOCK bit, an unlock sequence
A null output is associated with the output register reset must be executed. Refer to Section 42. Oscillators
value of 0. This is done to ensure that remappable with Enhanced PLL (DS60001250) in the PIC32
outputs remain disconnected from all output pins by Family Reference Manual for details.
default.
12.4.6.2 Configuration Bit Select Lock
FIGURE 12-3: EXAMPLE OF As an additional level of safety, the device can be
MULTIPLEXING OF configured to prevent more than one write session to
REMAPPABLE OUTPUT the RPnR and [pin name]R registers. The IOL1WAY
FOR RPF0 Configuration bit (DEVCFG3<29>) blocks the IOLOCK
bit from being cleared after it has been set once. If
RPF0R<3:0> IOLOCK remains set, the register unlock procedure
does not execute, and the PPS control registers cannot
Default be written to. The only way to clear the bit and re-
0
enable peripheral remapping is to perform a device
U1TX Output
1 Reset.
U2RTS Output 2 In the default (unprogrammed) state, IOL1WAY is set,
RPF0
Output Data
restricting users to one write session.
14
REFCLKO1
15
12.4.6 CONTROLLING CONFIGURATION

CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC32MZ DA devices include two features to
prevent alterations to the peripheral map:
Control register lock sequence
Configuration bit select lock

TABLE 12-2: OUTPUT PIN SELECTION

RPnR Value to Peripheral
RPn Port Pin RPnR SFR RPnR bits
Selection
RPD2 RPD2R RPD2R<3:0> 0000 = No Connect

0001 = U3TX
RPG8 RPG8R RPG8R<3:0>
0010 = U4RTS
RPF4 RPF4R RPF4R<3:0> 0011 = Reserved
0101 = SDO1
RPB9 RPB9R RPB9R<3:0>
0110 = SDO2
RPB10 RPB10R RPB10R<3:0> 0111 = SDO3
RPB5 RPB5R RPB5R<3:0> 1000 = Reserved
1001 = SDO5
RPC1 RPC1R RPC1R<3:0>
1010 = SS6
RPD14 RPD14R RPD14R<3:0> 1011 = OC3
RPG1 RPG1R RPG1R<3:0> 1100 = OC6
1101 = REFCLKO4
RPA14 RPA14R RPA14R<3:0>
1110 = C2OUT
RPD6 RPD6R RPD6R<3:0> 1111 = C1TX
0001 = U1TX
0010 = U2RTS
RPF5 RPF5R RPF5R<3:0> 0011 = U5TX
RPD11 RPD11R RPD11R<3:0> 0100 = U6RTS
0101 = SDO1
RPF0 RPF0R RPF0R<3:0> 0110 = SDO2
RPB1 RPB1R RPB1R<3:0> 0111 = SDO3
1000 = SDO4
RPE5 RPE5R RPE5R<3:0>
1001 = SDO5
RPC4 RPC4R RPC4R<3:0> 1011 = OC4
1100 = OC7
1101 = Reserved
RPA15 RPA15R RPA15R<3:0> 1110 = Reserved
1111 = REFCLKO1
RPD7 RPD7R RPD7R<3:0>

TABLE 12-2: OUTPUT PIN SELECTION (CONTINUED)
RPnR Value to Peripheral
RPn Port Pin RPnR SFR RPnR bits
Selection

0001 = U3RTS
0010 = U4TX
RPD4 RPD4R RPD4R<3:0> 0100 = U6TX
0101 = SS1
0110 = Reserved
RPE3 RPE3R RPE3R<3:0> 0111 = SS3
RPB7 RPB7R RPB7R<3:0> 1000 = SS4
1001 = SS5
RPF12 RPF12R RPF12R<3:0>
1010 = SDO6
RPD12 RPD12R RPD12R<3:0> 1011 = OC5
RPF8 RPF8R RPF8R<3:0> 1100 = OC8
1101 = Reserved
RPC3 RPC3R RPC3R<3:0>
1110 = C1OUT
RPE9 RPE9R RPE9R<3:0> 1111 = REFCLKO3
RPG9 RPG9R RPG9R<3:0> 0000 = No Connect
0001 = U1RTS
RPD0 RPD0R RPD0R<3:0> 0010 = U2TX
0011 = U5RTS
RPB6 RPB6R RPB6R<3:0> 0100 = U6TX
0101 = Reserved
RPD5 RPD5R RPD5R<3:0> 0110 = SS2
0111 = Reserved
1000 = SDO4
1010 = SDO6
RPC2 RPC2R RPC2R<3:0> 1011 = OC2
1100 = OC1
RPE8 RPE8R RPE8R<3:0> 1101 = OC9
1110 = Reserved
RPF2 RPF2R RPF2R<3:0> 1111 = C2TX

DS60001361E-page 260
12.5 I/O Ports Control Registers

TABLE 12-3: PORTA REGISTER MAP
Virtual Address
Bits
Bit Range
(BF86_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0000 ANSELA
15:0 ANSA10 ANSA9 ANSA5 ANSA1 0622
31:16 0000
0010 TRISA
15:0 TRISA15 TRISA14 TRISA10 TRISA9 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF
31:16 0000
0020 PORTA
15:0 RA15 RA14 RA10 RA9 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx
31:16 0000
0030 LATA
15:0 LATA15 LATA14 LATA10 LATA9 LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx
31:16 0000
0040 ODCA
15:0 ODCA15 ODCA14 ODCA10 ODCA9 ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000
31:16 0000
0050 CNPUA
15:0 CNPUA15 CNPUA14 CNPUA10 CNPUA9 CNPUA7 CNPUA6 CNPUA5 CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000
31:16 0000
0060 CNPDA
15:0 CNPDA15 CNPDA14 CNPDA10 CNPDA9 CNPDA7 CNPDA6 CNPDA5 CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000
31:16 0000
0070 CNCONA EDGE 0000
15:0 ON
DETECT
31:16 0000
0080 CNENA
15:0 CNIEA15 CNIEA14 CNIEA10 CNIEA9 CNIEA7 CNIEA6 CNIEA5 CNIEA4 CNIEA3 CNIEA2 CNIEA1 CNIEA0 0000
31:16 0000
0090 CNSTATA CN CN CN CN CN CN CN CN CN CN CN CN 0000
15:0
STATA15 STATA14 STATA10 STATA9 STATA7 STATA6 STATA5 STATA4 STATA3 STATA2 STATA1 STATA0
31:16 0000
00A0 CNNEA
15:0 CNNEA15 CNNEA14 CNNEA10 CNNEA9 CNNEA7 CNNEA6 CNNEA5 CNNEA4 CNNEA3 CNNEA2 CNNEA1 CNNEA0 0000
31:16 0000
00B0 CNFA
15:0 CNFA15 CNFA14 CNFA10 CNFA9 CNFA7 CNFA76 CNFA5 CNFA4 CNFA3 CNFA2 CNFA1 CNFA0 0000
31:16 0000
00C0 SRCON0A
15:0 SR1A15 SR1A14 SR1A10 SR1A9 SR1A7 SR1A6 SR1A5 SR1A4 SR1A3 SR1A2 SR1A1 SR1A0 0000
31:16 0000
00D0 SRCON1A
15:0 SR0A15 SR0A14 SR0A10 SR0A9 SR0A7 SR0A6 SR0A5 SR0A4 SR0A3 SR0A2 SR0A1 SR0A0 0000
Legend: x = Unknown value on Reset; = Unimplemented, read as 0; Reset values are shown in hexadecimal.
more information.
TABLE 12-4: PORTB REGISTER MAP
Bit Range
(BF86_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0100 ANSELB
15:0 ANSB15 ANSB14 ANSB13 ANSB12 ANSB11 ANSB10 ANSB9 ANSB8 ANSB7 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 FFBF
31:16 0000
0110 TRISB
15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
31:16 0000
0120 PORTB
15:0 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
31:16 0000
0130 LATB
15:0 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
31:16 0000
0140 ODCB
15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
31:16 0000

0150 CNPUB
15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000
31:16 0000
0160 CNPDB
15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000
31:16 0000
0170 CNCONB EDGE
15:0 ON 0000
DETECT
31:16 0000
0180 CNENB
15:0 CNIEB15 CNIEB14 CNIEB13 CNIEB12 CNIEB11 CNIEB10 CNIEB9 CNIEB8 CNIEB7 CNIEB6 CNIEB5 CNIEB4 CNIEB3 CNIEB2 CNIEB1 CNIEB0 0000
31:16 0000
0190 CNSTATB CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN
15:0 0000
STATB15 STATB14 STATB13 STATB12 STATB11 STATB10 STATB9 STATB8 STATB7 STATB6 STATB5 STATB4 STATB3 STATB2 STATB1 STATB0
31:16 0000
01A0 CNNEB
15:0 CNNEB15 CNNEB14 CNNEB13 CNNEB12 CNNEB11 CNNEB10 CNNEB9 CNNEB8 CNNEB7 CNNEB6 CNNEB5 CNNEB4 CNNEB3 CNNEB2 CNNEB1 CNNEB0 0000
31:16 0000
01B0 CNFB
15:0 CNFB15 CNFB14 CNFB13 CNFB12 CNFB11 CNFB10 CNFB9 CNFB8 CNFB7 CNFB76 CNFB5 CNFB4 CNFB3 CNFB2 CNFB1 CNFB0 0000
31:16 0000
01C0 SRCON0B
15:0 SR1B15 SR1B14 SR1B13 SR1B12 SR1B11 SR1B10 SR1B9 SR1B8 SR1B7 SR1B6 SR1B5 SR1B4 SR1B3 SR1B2 SR1B1 SR1B0 0000
31:16 0000
01D0 SRCON1B
15:0 SR0B15 SR0B14 SR0B13 SR0B12 SR0B11 SR0B10 SR0B9 SR0B8 SR0B7 SR0B6 SR0B5 SR0B4 SR0B3 SR0B2 SR0B1 SR0B0 0000
DS60001361E-page 261
more information.
DS60001361E-page 262
TABLE 12-5: PORTC REGISTER MAP

Virtual Address
Bits
Bit Range
(BF86_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0200 ANSELC
15:0 ANSC4 ANSC3 ANSC2 ANSC1 001E
31:16 0000
0210 TRISC
15:0 TRISC15 TRISC12 TRISC4 TRISC3 TRISC2 TRISC1 901E
31:16 0000
0220 PORTC
15:0 RC15 RC14 RC13 RC12 RC4 RC3 RC2 RC1 xxxx
31:16 0000
0230 LATC
15:0 LATC15 LATC14 LATC13 LATC12 LATC4 LATC3 LATC2 LATC1 xxxx
31:16 0000
0240 ODCC
15:0 ODCC15 ODCC14 ODCC13 ODCC12 ODCC4 ODCC3 ODCC2 ODCC1 0000
31:16 0000
0250 CNPUC
15:0 CNPUC15 CNPUC14 CNPUC13 CNPUC12 CNPUC4 CNPUC3 CNPUC2 CNPUC1 0000
31:16 0000
0260 CNPDC
15:0 CNPDC15 CNPDC14 CNPDC13 CNPDC12 CNPDC4 CNPDC3 CNPDC2 CNPDC1 0000
31:16 0000
0270 CNCONC EDGE
15:0 ON 0000
DETECT
31:16 0000
0280 CNENC
15:0 CNIEC15 CNIEC14 CNIEC13 CNIEC12 CNIEC4 CNIEC3 CNIEC2 CNIEC1 0000
31:16 0000
0290 CNSTATC
15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12 CNSTATC4 CNSTATC3 CNSTATC2 CNSTATC1 0000
31:16 0000
02A0 CNNEC
15:0 CNNEC15 CNNEC14 CNNEC13 CNNEC12 CNNEC4 CNNEC3 CNNEC2 CNNEC1 0000
31:16 0000
02B0 CNFC
15:0 CNFC15 CNFC14 CNFC13 CNFC12 CNFC4 CNFC3 CNFC2 CNFC1 0000
31:16 0000
02C0 SRCON0C
15:0 SR1C15 SR1C14 SR1C13 SR1C12 SR1C4 SR1C3 SR1C2 SR1C1 0000
31:16 0000
02D0 SRCON1C
15:0 SR0C15 SR0C14 SR0C13 SR0C12 SR0C4 SR0C3 SR0C2 SR0C1 0000
more information.
TABLE 12-6: PORTD REGISTER MAP
Bit Range
(BF86_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0300 ANSELD
15:0 ANSD15 ANSD14 C000
31:16 0000
0310 TRISD
15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FEFF
31:16 0000
0320 PORTD
15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx
31:16 0000
0330 LATD
15:0 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx
31:16 0000
0340 ODCD
15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000
31:16 0000

0350 CNPUD
15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000
31:16 0000
0360 CNPDD
15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9 CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000
31:16 0000
0370 CNCOND EDGE
15:0 ON 0000
DETECT
31:16 0000
0380 CNEND
15:0 CNIED15 CNIED14 CNIED13 CNIED12 CNIED11 CNIED10 CNIED9 CNIED7 CNIED6 CNIED5 CNIED4 CNIED3 CNIED2 CNIED1 CNIED0 0000
31:16 0000
0390 CNSTATD CNS CN CN CN CN CN CN CN CN CN CN CN CN CN CN
15:0 0000
TATD15 STATD14 STATD13 STATD12 STATD11 STATD10 STATD9 STATD7 STATD6 STATD5 STATD4 STATD3 STATD2 STATD1 STATD0
31:16 0000
03A0 CNNED
15:0 CNNED15 CNNED14 CNNED13 CNNED12 CNNED11 CNNED10 CNNED9 CNNED7 CNNED6 CNNED5 CNNED4 CNNED3 CNNED2 CNNED1 CNNED0 0000
31:16 0000
03B0 CNFD
15:0 CNFD15 CNFD14 CNFD13 CNFD12 CNFD11 CNFD10 CNFD9 CNFD7 CNFD6 CNFD5 CNFD4 CNFD3 CNFD2 CNFD1 CNFD0 0000
31:16 0000
03C0 SRCON0D
15:0 SR1D15 SR1D14 SR1D13 SR1D12 SR1D11 SR1D10 SR1D9 SR1D7 SR1D6 SR1D5 SR1D4 SR1D3 SR1D2 SR1D1 SR1D0 0000
31:16 0000
03D0 SRCON1D
15:0 SR0D15 SR0D14 SR0D13 SR0D12 SR0D11 SR0D10 SR0D9 SR0D7 SR0D6 SR0D5 SR0D4 SR0D3 SR0D2 SR0D1 SR0D0 0000
DS60001361E-page 263
more information.
DS60001361E-page 264
TABLE 12-7: PORTE REGISTER MAP

Virtual Address
Bits
Bit Range
(BF86_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0400 ANSELE
15:0 ANSE9 ANSE8 ANSE7 ANSE6 ANSE4 ANSE1 03D2
31:16 0000
0410 TRISE
15:0 TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF
31:16 0000
0420 PORTE
15:0 RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx
31:16 0000
0430 LATE
15:0 LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx
31:16 0000
0440 ODCE
15:0 ODCE9 ODCE8 ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000
31:16 0000
0450 CNPUE
15:0 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
31:16 0000
0460 CNPDE
15:0 CNPDE9 CNPDE8 CNPDE7 CNPDE6 CNPDE5 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000
31:16 0000
0470 CNCONE EDGE
15:0 ON 0000
DETECT
31:16 0000
0480 CNENE
15:0 CNIEE9 CNIEE8 CNIEE7 CNIEE6 CNIEE5 CNIEE4 CNIEE3 CNIEE2 CNIEE1 CNIEE0 0000
31:16 0000
0490 CNSTATE CN CN CN CN CN CN CN CN CN CN
15:0 0000
STATE9 STATE8 STATE7 STATE6 STATE5 STATE4 STATE3 STATE2 STATE1 STATE0
31:16 0000
04A0 CNNEE
15:0 CNNEE9 CNNEE8 CNNEE7 CNNEE6 CNNEE5 CNNEE4 CNNEE3 CNNEE2 CNNEE1 CNNEE0 0000
31:16 0000
04B0 CNFE
15:0 CNFE9 CNFE8 CNFE7 CNFE6 CNFE5 CNFE4 CNFE3 CNFE2 CNFE1 CNFE0
0000
31:16 0000
04C0 SRCON0E
15:0 SR1E9 SR1E8 SR1E7 SR1E6 SR1E5 SR1E4 SR1E3 SR1E2 SR1E1 SR1E0 0000
31:16 0000
04D0 SRCON1E
15:0 SR0E9 SR0E8 SR0E7 SR0E6 SR0E5 SR0E4 SR0E3 SR0E2 SR0E1 SR0E0 0000
more information.
TABLE 12-8: PORTF REGISTER MAP
Bit Range
(BF86_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0500 ANSELF
15:0 ANSF13 ANSF12 3000
31:16 0000
0510 TRISF
15:0 TRISF13 TRISF12 TRISF8 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F
31:16 0000
0520 PORTF
15:0 RF13 RF12 RF8 RF5 RF4 RF3 RF2 RF1 RF0 xxxx
31:16 0000
0530 LATF
15:0 LATF13 LATF12 LATF8 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx
31:16 0000
0540 ODCF
15:0 ODCF13 ODCF12 ODCF8 ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000
31:16 0000

0550 CNPUF
15:0 CNPUF13 CNPUF12 CNPUF8 CNPUF5 CNPUF4 CNPUF3 CNPUF2 CNPUF1 CNPUF0 0000
31:16 0000
0560 CNPDF
15:0 CNPDF13 CNPDF12 CNPDF8 CNPDF5 CNPDF4 CNPDF3 CNPDF2 CNPDF1 CNPDF0 0000
31:16 0000
0570 CNCONF EDGE
15:0 ON 0000
DETECT
31:16 0000
0580 CNENF
15:0 CNIEF13 CNIEF12 CNIEF8 CNIEF5 CNIEF4 CNIEF3 CNIEF2 CNIEF1 CNIEF0 0000
31:16 0000
0590 CNSTATF CN CN CN CN CN CN CN CN CN
15:0 0000
STATF13 STATF12 STATF8 STATF5 STATF4 STATF3 STATF2 STATF1 STATF0
31:16 0000
05A0 CNNEF
15:0 CNNEF13 CNNEF12 CNNEF8 CNNEF5 CNNEF4 CNNEF3 CNNEF2 CNNEF1 CNNEF0 0000
31:16 0000
05B0 CNFF
15:0 CNFF13 CNFF12 CNFF8 CNFF5 CNFF4 CNFF3 CNFF2 CNFF1 CNFF0 0000
31:16 0000
05C0 SRCON0F
15:0 SR1F13 SR1F12 SR1F8 SR1F5 SR1F4 SR1F3 SR1F2 SR1F1 SR1F0 0000
31:16 0000
05D0 SRCON1F
15:0 SR0F13 SR0F12 SR0F8 SR0F5 SR0F4 SR0F3 SR0F2 SR0F1 SR0F0 0000
DS60001361E-page 265
more information.
DS60001361E-page 266
TABLE 12-9: PORTG REGISTER MAP

Virtual Address
Bits
Bit Range
(BF86_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0600 ANSELG
15:0 ANSG15 ANSG9 ANSG8 ANSG7 ANSG6 83C0
31:16 0000
0610 TRISG
15:0 TRISG15 TRISG14 TRISG13 TRISG12 TRISG9 TRISG8 TRISG7 TRISG6 TRISG1 TRISG0 F3C3
31:16 0000
0620 PORTG
15:0 RG15 RG14 RG13 RG12 RG9 RG8 RG7 RG6 RG1 RG0 xxxx
31:16 0000
0630 LATG
15:0 LATG15 LATG14 LATG13 LATG12 LATG9 LATG8 LATG7 LATG6 LATG1 LATG0 xxxx
31:16 0000
0640 ODCG
15:0 ODCG15 ODCG14 ODCG13 ODCG12 ODCG9 ODCG8 ODCG7 ODCG6 ODCG1 ODCG0 0000
31:16 0000
0650 CNPUG
15:0 CNPUG15 CNPUG14 CNPUG13 CNPUG12 CNPUG9 CNPUG8 CNPUG7 CNPUG6 CNPUG1 CNPUG0 0000
31:16 0000
0660 CNPDG
15:0 CNPDG15 CNPDG14 CNPDG13 CNPDG12 CNPDG9 CNPDG8 CNPDG7 CNPDG6 CNPDG1 CNPDG0 0000
31:16 0000
0670 CNCONG EDGE
15:0 ON 0000
DETECT
31:16 0000
0680 CNENG
15:0 CNIEG15 CNIEG14 CNIEG13 CNIEG12 CNIEG9 CNIEG8 CNIEG7 CNIEG6 CNIEG1 CNIEG0 0000
31:16 0000
0690 CNSTATG CN CN CN CN CN CN CN CN CN CN
15:0 0000
STATG15 STATG14 STATG13 STATG12 STATG9 STATG8 STATG7 STATG6 STATG1 STATG0
31:16 0000
06A0 CNNEG
15:0 CNNEG15 CNNEG14 CNNEG13 CNNEG12 CNNEG9 CNNEG8 CNNEG7 CNNEG6 CNNEG1 CNNEG0 0000
31:16 0000
06B0 CNFG
15:0 CNFG15 CNFG14 CNFG13 CNFG12 CNFG9 CNFG8 CNFG7 CNFG6 CNFG1 CNFG0
0000
31:16 0000
06C0 SRCON0G
15:0 SR1G15 SR1G14 SR1G13 SR1G12 SR1G9 SR1G9 SR1G7 SR1G6 SR1G1 SR1G0 0000
31:16 0000
06D0 SRCON1G
15:0 SR0G15 SR0G14 SR0G13 SR0G12 SR0G9 SR0G8 SR0G7 SR0G6 SR0G1 SR0G0 0000
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for
more information.
TABLE 12-10: PORTH REGISTER MAP
Bit Range
(BF86_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0700 ANSELH
15:0 ANSH11 ANSH7 ANSH4 ANSH3 0898
31:16 0000
0710 TRISH
15:0 TRISH15 TRISH14 TRISH13 TRISH12 TRISH11 TRISH10 TRISH9 TRISH8 TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 TRISH0 FFFF
31:16 0000
0720 PORTH
15:0 RH15 RH14 RH13 RH12 RH11 RH10 RH9 RH8 RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx
31:16 0000
0730 LATH
15:0 LATH15 LATH14 LATH13 LATH12 LATH11 LATH10 LATH9 LATH8 LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx
31:16 0000
0740 ODCH
15:0 ODCH15 ODCH14 ODCH13 ODCH12 ODCH11 ODCH10 ODCH9 ODCH8 ODCH7 ODCH6 ODCH5 ODCH4 ODCH3 ODCH2 ODCH1 ODCH0 0000
31:16 0000

0750 CNPUH
15:0 CNPUH15 CNPUH14 CNPUH13 CNPUH12 CNPUH11 CNPUH10 CNPUH9 CNPUH8 CNPUH7 CNPUH6 CNPUH5 CNPUH4 CNPUH3 CNPUH2 CNPUH1 CNPUH0 0000
31:16 0000
0760 CNPDH
15:0 CNPDH15 CNPDH14 CNPDH13 CNPDH12 CNPDH11 CNPDH10 CNPDH9 CNPDH8 CNPDH7 CNPDH6 CNPDH5 CNPDH4 CNPDH3 CNPDH2 CNPDH1 CNPDH0 0000
31:16 0000
0770 CNCONH EDGE
15:0 ON 0000
DETECT
31:16 0000
0780 CNENH
15:0 CNIEH15 CNIEH14 CNIEH13 CNIEH12 CNIEH11 CNIEH10 CNIEH9 CNIEH8 CNIEH7 CNIEH6 CNIEH5 CNIEH4 CNIEH3 CNIEH2 CNIEH1 CNIEH0 0000
31:16 0000
0790 CNSTATH CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN
15:0 0000
STATH15 STATH14 STATH13 STATH12 STATH11 STATH10 STATH9 STATH8 STATH7 STATH6 STATH5 STATH4 STATH3 STATH2 STATH1 STATH0
31:16 0000
07A0 CNNEH
15:0 CNNEH15 CNNEH14 CNNEH13 CNNEH12 CNNEH11 CNNEH10 CNNEH9 CNNEH8 CNNEH7 CNNEH6 CNNEH5 CNNEH4 CNNEH3 CNNEH2 CNNEH1 CNNEH0 0000
31:16 0000
07B0 CNFH
15:0 CNFH15 CNFH14 CNFH13 CNFH12 CNFH11 CNFH10 CNFH9 CNFH8 CNFH7 CNFH6 CNFH5 CNFH4 CNFH3 CNFH2 CNFH1 CNFH0 0000
31:16 0000
07C0 SRCON0H
15:0 SR1H15 SR1H14 SR1H13 SR1H12 SR1H11 SR1H10 SR1H9 SR1H8 SR1H7 SR1H6 SR1H5 SR1H4 SR1H3 SR1H2 SR1H1 SR1H0 0000
31:16 0000
07D0 SRCON1H
15:0 SR0H15 SR0H14 SR0H13 SR0H12 SR0H11 SR0H10 SR0H9 SR0H8 SR0H7 SR0H6 SR0H5 SR0H4 SR0H3 SR0H2 SR0H1 SR0H0 0000
DS60001361E-page 267
more information.
DS60001361E-page 268
TABLE 12-11: PORTJ REGISTER MAP

Virtual Address
Bits
Bit Range
(BF86_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0800 ANSELJ
15:0 ANSJ2 0004
31:16 0000
0810 TRISJ
15:0 TRISJ15 TRISJ14 TRISJ13 TRISJ12 TRISJ11 TRISJ10 TRISJ9 TRISJ8 TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 TRISJ0 FFFF
31:16 0000
0820 PORTJ
15:0 RJ15 RJ14 RJ13 RJ12 RJ11 RJ10 RJ9 RJ8 RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx
31:16 0000
0830 LATJ
15:0 LATJ15 LATJ14 LATJ13 LATJ12 LATJ11 LATJ10 LATJ9 LATJ8 LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx
31:16 0000
0840 ODCJ
15:0 ODCJ15 ODCJ14 ODCJ13 ODCJ12 ODCJ11 ODCJ10 ODCJ9 ODCJ18 ODCJ7 ODCJ6 ODCJ5 ODCJ4 ODCJ3 ODCJ2 ODCJ1 ODCJ0 0000
31:16 0000
0850 CNPUJ
15:0 CNPUJ15 CNPUJ14 CNPUJ13 CNPUJ12 CNPUJ11 CNPUJ10 CNPUJ9 CNPUJ8 CNPUJ7 CNPUJ6 CNPUJ5 CNPUJ4 CNPUJ3 CNPUJ2 CNPUJ1 CNPUJ0 0000
31:16 0000
0860 CNPDJ
15:0 CNPDJ15 CNPDJ14 CNPDJ13 CNPDJ12 CNPDJ11 CNPDJ10 CNPDJ9 CNPDJ8 CNPDJ7 CNPDJ6 CNPDJ5 CNPDJ4 CNPDJ3 CNPDJ2 CNPDJ1 CNPDJ0 0000
31:16 0000
0870 CNCONJ EDGE
15:0 ON 0000
DETECT
31:16 0000
0880 CNENJ
15:0 CNIEJ15 CNIEJ14 CNIEJ13 CNIEJ12 CNIEJ11 CNIEJ10 CNIEJ9 CNIEJ8 CNIEJ7 CNIEJ6 CNIEJ5 CNIEJ4 CNIEJ3 CNIEJ2 CNIEJ1 CNIEJ0 0000
31:16 0000
0890 CNSTATJ CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN CN
15:0 0000
STATJ15 STATJ14 STATJ13 STATJ12 STATJ11 STATJ10 STATJ9 STATJ8 STATJ7 STATJ6 STATJ5 STATJ4 STATJ3 STATJ2 STATJ1 STATJ0
31:16 0000
08A0 CNNEJ
15:0 CNNEJ15 CNNEJ14 CNNEJ13 CNNEJ12 CNNEJ11 CNNEJ10 CNNEJ9 CNNEJ8 CNNEJ7 CNNEJ6 CNNEJ5 CNNEJ4 CNNEJ3 CNNEJ2 CNNEJ1 CNNEJ0 0000
31:16 0000
08B0 CNFJ
15:0 CNFJ15 CNFJ14 CNFJ13 CNFJ12 CNFJ11 CNFJ10 CNFJ9 CNFJ8 CNFJ7 CNFJ6 CNFJ5 CNFJ4 CNFJ3 CNFJ2 CNFJ1 CNFJ0 0000
31:16 0000
08C0 SRCON0J
15:0 SR1J15 SR1J14 SR1J13 SR1J12 SR1J11 SR1J10 SR1J9 SR1J8 SR1J7 SR1J6 SR1J5 SR1J4 SR1J3 SR1J2 SR1J1 SR1J0 0000
31:16 0000
08D0 SRCON1J
15:0 SR0J15 SR0J14 SR0J13 SR0J12 SR0J11 SR0J10 SR0J9 SR0J8 SR0J7 SR0J6 SR0J5 SR0J4 SR0J3 SR0J2 SR0J1 SR0J0 0000
more information.
TABLE 12-12: PORTK REGISTER MAP
Bit Range
(BF86_#)
Register
Name(1)
Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0900 ANSELK
15:0 ANSK2 ANSK1 0006
31:16 0000
0910 TRISK
15:0 TRISK7 TRISK6 TRISK5 TRISK4 TRISK3 TRISK2 TRISK1 TRISK0 00E9
31:16 0000
0920 PORTK
15:0 RK7 RK6 RK5 RK4 RK3 RK2 RK1 RK0 xxxx
31:16 0000
0930 LATK
15:0 LATK7 LATK6 LATK5 LATK4 LATK3 LATK2 LATK1 LATK0 xxxx
31:16 0000
0940 ODCK
15:0 ODCK7 ODCK6 ODCK5 ODCK4 ODCK3 ODCK2 ODCK1 ODCK0 0000
31:16 0000

0950 CNPUK
15:0 CNPUK7 CNPUK6 CNPUK5 CNPUK4 CNPUK3 CNPUK2 CNPUK1 CNPUK0 0000
31:16 0000
0960 CNPDK
15:0 CNPDK7 CNPDK6 CNPDK5 CNPDK4 CNPDK3 CNPDK2 CNPDK1 CNPDK0 0000
31:16 0000
0970 CNCONK EDGE
15:0 ON 0000
DETECT
31:16 0000
0980 CNENK
15:0 CNIEK7 CNIEK6 CNIEK5 CNIEK4 CNIEK3 CNIEK2 CNIEK1 CNIEK0 0000
31:16 0000
0990 CNSTATK CN CN CN CN CN CN CN CN
15:0 0000
STATK7 STATK6 STATK5 STATK4 STATK3 STATK2 STATK1 STATK0
31:16 0000
09A0 CNNEK
15:0 CNNEK7 CNNEK6 CNNEK5 CNNEK4 CNNEK3 CNNEK2 CNNEK1 CNNEK0 0000
31:16 0000
09B0 CNFK
15:0 CNFK7 CNFK6 CNFK5 CNFK4 CNFK3 CNFK2 CNFK1 CNFK0 0000
31:16 0000
09C0 SRCON0K
15:0 SR1K7 SR1K6 SR1K5 SR1K4 SR1K3 SR1K2 SR1K1 SR1K0 0000
31:16 0000
09D0 SRCON1K
15:0 SR0K7 SR0K6 SR0K5 SR0K4 SR0K3 SR0K2 SR0K1 SR0K0 0000
DS60001361E-page 269
more information.
TABLE 12-13: PERIPHERAL PIN SELECT INPUT REGISTER MAP
DS60001361E-page 270

Bits
Virtual Address
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
1404 INT1R
15:0 INT1R<3:0> 0000
31:16 0000
1408 INT2R
15:0 INT2R<3:0> 0000
31:16 0000
140C INT3R
15:0 INT3R<3:0> 0000
31:16 0000
1410 INT4R
15:0 INT4R<3:0> 0000
31:16 0000
1418 T2CKR
15:0 T2CKR<3:0> 0000
31:16 0000
141C T3CKR
15:0 T3CKR<3:0> 0000
31:16 0000
1420 T4CKR
15:0 T4CKR<3:0> 0000
31:16 0000
1424 T5CKR
15:0 T5CKR<3:0> 0000
31:16 0000
1428 T6CKR
15:0 T6CKR<3:0> 0000
31:16 0000
142C T7CKR
15:0 T7CKR<3:0> 0000
31:16 0000
1430 T8CKR
15:0 T8CKR<3:0> 0000

31:16 0000
1434 T9CKR
15:0 T9CKR<3:0> 0000
31:16 0000
1438 IC1R
15:0 IC1R<3:0> 0000
31:16 0000
143C IC2R
15:0 IC2R<3:0> 0000
31:16 0000
1440 IC3R
15:0 IC3R<3:0> 0000
TABLE 12-13: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED)
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
1444 IC4R
15:0 IC4R<3:0> 0000
31:16 0000
1448 IC5R
15:0 IC5R<3:0> 0000
31:16 0000
144C IC6R
15:0 IC6R<3:0> 0000
31:16 0000
1450 IC7R
15:0 IC7R<3:0> 0000
31:16 0000

1454 IC8R
15:0 IC8R<3:0> 0000
31:16 0000
1458 IC9R
15:0 IC9R<3:0> 0000
31:16 0000
1460 OCFAR
15:0 OCFAR<3:0> 0000
31:16 0000
1468 U1RXR
15:0 U1RXR<3:0> 0000
31:16 0000
146C U1CTSR
15:0 U1CTSR<3:0> 0000
31:16 0000
1470 U2RXR
15:0 U2RXR<3:0> 0000
31:16 0000
1474 U2CTSR
15:0 U2CTSR<3:0> 0000
31:16 0000
1478 U3RXR
15:0 U3RXR<3:0> 0000
31:16 0000
147C U3CTSR
15:0 U3CTSR<3:0> 0000
DS60001361E-page 271
31:16 0000
1480 U4RXR
15:0 U4RXR<3:0> 0000
31:16 0000
1484 U4CTSR
15:0 U4CTSR<3:0> 0000
DS60001361E-page 272

Bits
Virtual Address
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
1488 U5RXR
15:0 U5RXR<3:0> 0000
31:16 0000
148C U5CTSR
15:0 U5CTSR<3:0> 0000
31:16 0000
1490 U6RXR
15:0 U6RXR<3:0> 0000
31:16 0000
1494 U6CTSR
15:0 U6CTSR<3:0> 0000
31:16 0000
149C SDI1R
15:0 SDI1R<3:0> 0000
31:16 0000
14A0 SS1R
15:0 SS1R<3:0> 0000
31:16 0000
14A8 SDI2R
15:0 SDI2R<3:0> 0000
31:16 0000
14AC SS2R
15:0 SS2R<3:0> 0000
31:16 0000
14B4 SDI3R
15:0 SDI3R<3:0> 0000
31:16 0000
14B8 SS3R
15:0 SS3R<3:0> 0000
31:16 0000
14C0 SDI4R
15:0 SDI4R<3:0> 0000

31:16 0000
14C4 SS4R
15:0 SS4R<3:0> 0000
31:16 0000
14CC SDI5R
15:0 SDI5R<3:0> 0000
31:16 0000
14D0 SS5R
15:0 SS5R<3:0> 0000
31:16 0000
14D8 SDI6R
15:0 SDI6R<3:0> 0000
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
14DC SS6R
15:0 SS6R<3:0> 0000
31:16 0000
14E0 C1RXR(1)
15:0 C1RXR<3:0> 0000
31:16 0000
14E4 C2RXR(1)
15:0 C2RXR<3:0> 0000
31:16 0000
14E8 REFCLKI1R
15:0 REFCLKI1R<3:0> 0000
31:16 0000

14F0 REFCLKI3R
15:0 REFCLKI3R<3:0> 0000
31:16 0000
14F4 REFCLKI4R
15:0 REFCLKI4R<3:0> 0000
DS60001361E-page 273
TABLE 12-14: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP
DS60001361E-page 274

Bits
Virtual Address
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
1538 RPA14R
15:0 RPA14R<3:0> 0000
31:16 0000
153C RPA15R
15:0 RPA15R<3:0> 0000
31:16 0000
1540 RPB0R
15:0 RPB0R<3:0> 0000
31:16 0000
1544 RPB1R
15:0 RPB1R<3:0> 0000
31:16 0000
1548 RPB2R
15:0 RPB2R<3:0> 0000
31:16 0000
154C RPB3R
15:0 RPB3R<3:0> 0000
31:16 0000
1554 RPB5R
15:0 RPB5R<3:0> 0000
31:16 0000
1558 RPB6R
15:0 RPB6R<3:0> 0000
31:16 0000
155C RPB7R
15:0 RPB7R<3:0> 0000
31:16 0000
1560 RPB8R
15:0 RPB8R<3:0> 0000
31:16 0000
1564 RPB9R
15:0 RPB9R<3:0> 0000
31:16 0000
1568 RPB10R
15:0 RPB10R<3:0> 0000
31:16 0000
157C RPB15R
15:0 RPB15R<3:0>
0000
31:16 0000
1584 RPC1R
15:0 RPC1R<3:0> 0000
31:16 0000
1588 RPC2R
15:0 RPC2R<3:0> 0000
31:16 0000
158C RPC3R
15:0 RPC3R<3:0> 0000
31:16 0000
15B4 RPC13R
15:0 RPC13R<3:0> 0000
31:16 0000
15B8 RPC14R
15:0 RPC14R<3:0> 0000
31:16 0000
15C0 RPD0R
15:0 RPD0R<3:0> 0000
TABLE 12-14: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)
Bits
Virtual Address
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
15C8 RPD2R
15:0 RPD2R<3:0> 0000
31:16 0000
15CC RPD3R
15:0 RPD3R<3:0> 0000
31:16 0000
15D0 RPD4R
15:0 RPD4R<3:0> 0000
31:16 0000
15D4 RPD5R
15:0 RPD5R<3:0> 0000
31:16 0000
15D8 RPD6R
15:0 RPD6R<3:0> 0000
31:16 0000

15DC RPD7R
15:0 RPD7R<3:0> 0000
31:16 0000
15E4 RPD9R
15:0 RPD9R<3:0> 0000
31:16 0000
15EC RPD11R
15:0 RPD11R<3:0> 0000
31:16 0000
15F0 RPD12R
15:0 RPD12R<3:0> 0000
31:16 0000
15F8 RPD14R
15:0 RPD14R<3:0> 0000
31:16 0000
160C RPE3R
15:0 RPE3R<3:0> 0000
31:16 0000
1614 RPE5R
15:0 RPE5R<3:0> 0000
31:16 0000
1620 RPE8R
15:0 RPE8R<3:0> 0000
31:16 0000
1624 RPE9R
15:0 RPE9R<3:0> 0000
31:16 0000
1640 RPF0R
15:0 RPF0R<3:0> 0000
31:16 0000
1644 RPF1R
DS60001361E-page 275
15:0 RPF1R<3:0> 0000

31:16 0000
1648 RPF2R
15:0 RPF2R<3:0> 0000
31:16 0000
164C RPF3R
15:0 RPF3R<3:0> 0000
31:16 0000
1650 RPF4R
15:0 RPF4R<3:0> 0000
DS60001361E-page 276
TABLE 12-14: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED)

Bits
Virtual Address
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
1654 RPF5R
15:0 RPF5R<3:0> 0000
31:16 0000
1660 RPF8R
15:0 RPF8R<3:0> 0000
31:16 0000
1670 RPF12R
15:0 RPG12R<3:0> 0000
31:16 0000
1680 RPG0R
15:0 RPG1R<3:0> 0000
31:16 0000
1684 RPG1R
15:0 RPG1R<3:0> 0000
31:16 0000
169C RPG7R
15:0 RPG7R<3:0> 0000
31:16 0000
16A0 RPG8R
15:0 RPG8R<3:0> 0000
31:16 0000
16A4 RPG9R
15:0 RPG9R<3:0> 0000
REGISTER 12-1: [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
[pin name]R<3:0>
Legend:

bit 3-0 [pin name]R<3:0>: Peripheral Pin Select Input bits
Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table for input
pin selection values.
Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.
REGISTER 12-2: RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RPnR<3:0>
Legend:

bit 3-0 RPnR<3:0>: Peripheral Pin Select Output bits
See Table for output pin selection values.
Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON<13>) = 0.

REGISTER 12-3: CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A G)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
15:8 EDGE
ON
DETECT
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:

bit 15 ON: Change Notice (CN) Control ON bit
1 = CN is enabled
0 = CN is disabled
bit 11 EDGEDETECT: Edge Detection Type Control bit
1 = Detects any edge on the pin (CNFx is used for the CN event)
0 = Detects any edge on the pin (CNSTATx is used for the CN event)

13.0 TIMER1 The following modes are supported by Timer1:
Synchronous Internal Timer
Synchronous Internal Gated Timer
devices. It is not intended to be a Synchronous External Timer
comprehensive reference source. To Asynchronous External Timer
sheet, refer to Section 14. Timers 13.1 Additional Supported Features
(DS60001105), which is available from the
Documentation > Reference Manual Selectable clock prescaler
section of the Microchip PIC32 web site Timer operation during Sleep and Idle modes
(www.microchip.com/pic32). Fast bit manipulation using CLR, SET and INV
registers
PIC32MZ DA devices feature one synchronous/asyn-
Asynchronous mode can be used with the SOSC
chronous 16-bit timer that can operate as a free-running
to function as a real-time clock
interval timer for various timing applications and counting
external events. This timer can also be used with the low- ADC event trigger
power Secondary Oscillator (SOSC) for real-time clock
applications.
FIGURE 13-1: TIMER1 BLOCK DIAGRAM
PR1
Equal
Trigger to ADC 16-bit Comparator TSYNC
1 Sync
TMR1
Reset
0
0
T1IF
Event Flag 1 Q D TGATE
Q TCS
TGATE
ON
x1
SOSC 00
Gate Prescaler
T1CK 01
Sync 10 1, 8, 64, 256
LPRC 10
PBCLK3 00
TECS<1:0> 2
TCKPS<1:0>

DS60001361E-page 280
13.2 Timer1 Control Register

TABLE 13-1: TIMER1 REGISTER MAP
Virtual Address
Bits
All Resets
Bit Range
(BF84_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0000 T1CON
15:0 ON SIDL TWDIS TWIP TECS<1:0> TGATE TCKPS<1:0> TSYNC TCS 0000
31:16 0000
0010 TMR1
15:0 TMR1<15:0> 0000
31:16 0000
0020 PR1
15:0 PR1<15:0> FFFF
more information.
REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 R/W-0 R/W-0
15:8
ON SIDL TWDIS TWIP TECS<1:0>
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
7:0
TGATE TCKPS<1:0> TSYNC TCS
Legend:

bit 15 ON: Timer On bit
1 = Timer is enabled
0 = Timer is disabled
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
bit 12 TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11 TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as 0.
bit TECS<1:0>: Timer1 External Clock Selection bits
11 = Reserved
10 = External clock comes from the LPRC
01 = External clock comes from the T1CK pin
00 = External clock comes from the SOSC
bit 7 TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled

REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits
11 = 1:256 prescale value
bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1 TCS: Timer Clock Source Select bit
1 = External clock is defined by the TECS<1:0> bits
0 = Internal peripheral clock

14.0 TIMER2/3, TIMER4/5, TIMER6/7, Four 32-bit synchronous timers are available by
combining Timer2 with Timer3, Timer4 with Timer5,
AND TIMER8/9 Timer6 with Timer7, and Timer8 with Timer9.
Note: This data sheet summarizes the features The 32-bit timers can operate in one of three modes:
Synchronous internal 32-bit timer
comprehensive reference source. To Synchronous internal 32-bit gated timer
complement the information in this data Synchronous external 32-bit timer
sheet, refer to Section 14. Timers
(DS60001105), which is available from the 14.1 Additional Features
Documentation > Reference Manual
section of the Microchip PIC32 web site Selectable clock prescaler
(www.microchip.com/pic32). Timers operational during CPU idle
Time base for Input Capture and Output Compare
This family of devices features eight synchronous modules (Timer2 through Timer7 only)
16-bit timers (default) that can operate as a free-
ADC event trigger (Timer3 and Timer5 only)
running interval timer for various timing applications
and counting external events. Fast bit manipulation using CLR, SET and INV
registers
The following modes are supported:
Synchronous internal 16-bit timer
Synchronous internal 16-bit gated timer
Synchronous external 16-bit timer
FIGURE 14-1: TIMER2 THROUGH TIMER9 BLOCK DIAGRAM (16-BIT)
Reset TMRx Sync
Trigger to ADC (1) Comparator x 16

Equal
PRx
0
TxIF Event Flag
1 Q D TGATE
Q TCS
TGATE
ON
TxCK x1
Prescaler
Gate 1, 2, 4, 8, 16,
Sync 10
32, 64, 256
PBCLK3 00
3
TCKPS
Note 1: The ADC event trigger is available on Timer3 and Timer5 only.

FIGURE 14-2: TIMER2/3, TIMER4/5, TIMER6/7, AND TIMER8/9 BLOCK DIAGRAM (32-BIT)
Reset
TMRy(2) TMRx(2) Sync
MS Half Word LS Half Word
ADC Event Trigger(1) 32-bit Comparator

Equal
PRy(2) PRx(2)
0
TyIF Event Flag(2)
1 Q D TGATE
Q TCS
TGATE
ON
TxCK(2) x1
Prescaler
Gate 1, 2, 4, 8, 16,
Sync 10
32, 64, 256
PBCLK3 00
3
TCKPS
Note 1: ADC event trigger is available only on the Timer2/3 and TImer4/5 pairs.
2: In this diagram, x represents Timer2, 4, 6, or 8, and y represents Timer3, 5, 7, or 9.

14.2 Timer2-Timer9 Control Registers
TABLE 14-1:
Virtual Address TIMER2 THROUGH TIMER9 REGISTER MAP
Bits
All Resets
Bit Range
(BF84_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0200 T2CON
15:0 ON SIDL TGATE TCKPS<2:0> T32 TCS 0000
31:16 0000
0210 TMR2
15:0 TMR2<15:0> 0000
31:16 0000
0220 PR2
15:0 PR2<15:0> FFFF
31:16 0000
0400 T3CON
15:0 ON SIDL TGATE TCKPS<2:0> TCS 0000
31:16 0000
0410 TMR3

15:0 TMR3<15:0> 0000
31:16 0000
0420 PR3
15:0 PR3<15:0> FFFF
31:16 0000
0600 T4CON
31:16 0000
0610 TMR4
15:0 TMR4<15:0> 0000
31:16 0000
0620 PR4
15:0 PR4<15:0> FFFF
31:16 0000
0800 T5CON
31:16 0000
0810 TMR5
15:0 TMR5<15:0> 0000
31:16 0000
0820 PR5
15:0 PR5<15:0> FFFF
31:16 0000
0A00 T6CON
31:16 0000
0A10 TMR6
15:0 TMR2<15:0> 0000
31:16
DS60001361E-page 285
0000
0A20 PR6
15:0 PR2<15:0> FFFF
31:16 0000
0C00 T7CON
more information.
DS60001361E-page 286
TABLE 14-1: TIMER2 THROUGH TIMER9 REGISTER MAP (CONTINUED)

Virtual Address
Bits
All Resets
Bit Range
(BF84_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0C10 TMR7
15:0 TMR3<15:0> 0000
31:16 0000
0C20 PR7
15:0 PR3<15:0> FFFF
31:16 0000
0E00 T8CON
31:16 0000
0E10 TMR8
15:0 TMR4<15:0> 0000
31:16 0000
0E20 PR8
15:0 PR4<15:0> FFFF
31:16 0000
1000 T9CON
31:16 0000
1010 TMR9
15:0 TMR5<15:0> 0000
31:16 0000
1020 PR9
15:0 PR5<15:0> FFFF
more information.
REGISTER 14-1: TxCON: TYPE B TIMER CONTROL REGISTER (x = 2-9)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
15:8
ON(1) SIDL(2)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
7:0
TGATE(1) TCKPS<2:0>(1) T32(3) TCS(1)
Legend:

bit 15 ON: Timer On bit(1)
1 = Module is enabled
0 = Module is disabled
bit 13 SIDL: Stop in Idle Mode bit(2)
0 = Continue operation even in Idle mode
bit 7 TGATE: Timer Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored and is read as 0.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits(1)
bit 3 T32: 32-Bit Timer Mode Select bit(3)
1 = Odd numbered and even numbered timers form a 32-bit timer
0 = Odd numbered and even numbered timers form a separate 16-bit timer
Note 1: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5,
Timer7, and Timer9). All timer functions are set through the even numbered timers.
2: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
3: This bit is available only on even numbered timers (Timer2, Timer4, Timer6, and Timer8).

REGISTER 14-1: TxCON: TYPE B TIMER CONTROL REGISTER (x = 2-9) (CONTINUED)
bit 1 TCS: Timer Clock Source Select bit(1)
1 = External clock from TxCK pin
0 = Internal peripheral clock
Note 1: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5,
Timer7, and Timer9). All timer functions are set through the even numbered timers.
2: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
3: This bit is available only on even numbered timers (Timer2, Timer4, Timer6, and Timer8).

15.0 INPUT CAPTURE Capture events are caused by the following:
Capture timer value on every edge (rising and falling),
Note: This data sheet summarizes the features specified edge first
Prescaler capture event modes:
comprehensive reference source. To - Capture timer value on every 4th rising edge of
complement the information in this data input at ICx pin
sheet, refer to Section 15. Input - Capture timer value on every 16th rising edge of
Capture (DS60001122), which is input at ICx pin
available from the Documentation > Each input capture channel can select between one of
Reference Manual section of the six 16-bit timers for the time base, or two of six 16-bit
Microchip PIC32 web site timers together to form a 32-bit timer. The selected
(www.microchip.com/pic32). timer can use either an internal or external clock.
The Input Capture module is useful in applications Other operational features include:
requiring frequency (period) and pulse measurement. Device wake-up from capture pin during Sleep and
Idle modes
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an Interrupt on input capture event
event occurs at the ICx pin. 4-word FIFO buffer for capture values; Interrupt
optionally generated after 1, 2, 3, or 4 buffer
locations are filled
Input capture can also be used to provide additional
sources of external interrupts
FIGURE 15-1: INPUT CAPTURE BLOCK DIAGRAM
FEDGE ICM<2:0>
Specified/Every
Edge Mode 110
PBCLK3
Prescaler Mode 101 Timerx(2) Timery(2)
(16th Rising Edge)
C32/ICTMR
Prescaler Mode 100
(4th Rising Edge)
CaptureEvent To CPU
FIFO Control
Rising Edge Mode 011
ICx(1)
ICxBUF(1)
Falling Edge Mode 010 FIFO
ICI<1:0>
ICM<2:0>
Edge Detection 001
Mode
/N Set Flag ICxIF(1)

(In IFSx Register)
Sleep/Idle
Wake-up Mode 001
111
Note 1: An x in a signal, register or bit name denotes the number of the capture channel.
2: See Table 15-1 for Timerx and Timery selections.

The timer source for each Input Capture module
depends on the setting of the ICACLK bit in the
CFGCON register. The available configurations are
TABLE 15-1: TIMER SOURCE

CONFIGURATIONS
Input Capture
Timerx Timery
Module
ICACLK (CFGCON<17>) = 0
IC1 Timer2 Timer3

IC9 Timer 2 Timer 3
ICACLK (CFGCON<17>) = 1
IC1 Timer4 Timer5
IC2 Timer4 Timer5
IC3 Timer4 Timer5
IC4 Timer2 Timer3
IC5 Timer2 Timer3
IC6 Timer2 Timer3
IC7 Timer6 Timer7
IC8 Timer6 Timer7
IC9 Timer6 Timer7

15.1 Input Capture Control Registers
TABLE 15-2: INPUT CAPTURE 1 THROUGH INPUT CAPTURE 9 REGISTER MAP

Bits
Virtual Address
All Resets
Bit Range
(BF84_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
2000 IC1CON(1)
15:0 ON SIDL FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2010 IC1BUF IC1BUF<31:0>
15:0 xxxx
31:16 0000
2200 IC2CON(1)
31:16 xxxx
15:0 xxxx
31:16 0000
2400 IC3CON(1)
15:0 ON SIDL FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

0000
31:16 xxxx
15:0 xxxx
31:16 0000
2600 IC4CON(1)
31:16 xxxx
15:0 xxxx
31:16 0000
2800 IC5CON(1)
31:16 xxxx
15:0 xxxx
31:16 0000
2A00 IC6CON(1)
31:16 xxxx
2A10 IC6BUF IC6BUF<31:0>
15:0 xxxx
31:16 0000
2C00 IC7CON(1)
31:16 xxxx
2C10 IC7BUF IC7BUF<31:0>
15:0 xxxx
31:16 0000
2E00 IC8CON(1)
31:16 xxxx
2E10 IC8BUF IC8BUF<31:0>
DS60001361E-page 291
15:0 xxxx
31:16 0000
3000 IC9CON(1)
31:16 xxxx
15:0 xxxx
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for more
information.
REGISTER 15-1: ICXCON: INPUT CAPTURE X CONTROL REGISTER

Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
ON SIDL FEDGE C32
R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0
7:0
ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit
-n = Bit Value at POR: (0, 1, x = unknown) P = Programmable bit r = Reserved bit

bit 15 ON: Input Capture Module Enable bit
1 = Module enabled
0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
bit 13 SIDL: Stop in Idle Control bit
1 = Halt in CPU Idle mode
0 = Continue to operate in CPU Idle mode
bit 9 FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110)
1 = Capture rising edge first
0 = Capture falling edge first
bit 8 C32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
bit 7 ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is 1)(1)
0 = Timery is the counter source for capture
1 = Timerx is the counter source for capture
bit 6-5 ICI<1:0>: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0 ICM<2:0>: Input Capture Mode Select bits
111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
110 = Simple Capture Event mode every edge, specified edge first and every edge thereafter
101 = Prescaled Capture Event mode every sixteenth rising edge
100 = Prescaled Capture Event mode every fourth rising edge
011 = Simple Capture Event mode every rising edge
010 = Simple Capture Event mode every falling edge
001 = Edge Detect mode every edge (rising and falling)
000 = Input Capture module is disabled
Note 1: Refer to Table 15-1 for Timerx and Timery selections.

16.0 OUTPUT COMPARE When a match occurs, the Output Compare module
generates an event based on the selected mode of
Note: This data sheet summarizes the operation.
features of the PIC32MZ Graphics (DA) The following are some of the key features of the
Family of devices. It is not intended to Output Compare module:
be a comprehensive reference source.
To complement the information in this Multiple Output Compare modules in a device
data sheet, refer to Section 16. Programmable interrupt generation on compare
Output Compare (DS60001111), event
which is available from the Single and Dual Compare modes
Documentation > Reference Manual Single and continuous output pulse generation
Pulse-Width Modulation (PWM) mode
Hardware-based PWM Fault detection and
The Output Compare module is used to generate a automatic output disable
single pulse or a train of pulses in response to selected Programmable selection of 16-bit or 32-bit time
time base events. bases
For all modes of operation, the Output Compare mod- Can operate from either of two available 16-bit
ule compares the values stored in the OCxR and/or the time bases or a single 32-bit time base
OCxRS registers to the value in the selected timer. ADC event trigger
FIGURE 16-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit OCxIF(1)
OCxRS(1)
Trigger to ADC(4)
Output S Q
OCxR(1) OCx(1)
Logic R
Output Output Enable

3 Logic
Enable
OCM<2:0>
Mode Select OCFA or
Comparator
OCFB(2)
0 1 OCTSEL 0 1
16 16
PBCLK3 Timerx(3) Timery(3) Timerx(3) Timery(3)

Rollover Rollover
Note 1: Where x is shown, reference is made to the registers associated with the respective output compare channels,
1 through 9.
2: The OCFA pin controls the OC1, OC3, and OC7-OC9 channels. The OCFB pin controls the OC4-OC6 channels.
3: Refer to Table 16-1 for Timerx and Timery selections.
4: The ADC event trigger is only available on OC1,OC3, and OC 5.

The timer source for each Output Compare module
depends on the setting of the OCACLK bit in the
CFGCON register. The available configurations are
TABLE 16-1: TIMER SOURCE

CONFIGURATIONS
Output
Compare Timerx Timery
Module
OCACLK (CFGCON<16>) = 0
OC1 Timer2 Timer3

OC9 Timer 2 Timer 3
OCACLK (CFGCON<16>) = 1
OC1 Timer4 Timer5
OC2 Timer4 Timer5
OC3 Timer4 Timer5
OC4 Timer2 Timer3
OC5 Timer2 Timer3
OC6 Timer2 Timer3
OC7 Timer6 Timer7
OC8 Timer6 Timer7
OC9 Timer6 Timer7

16.1 Output Compare Control Registers
TABLE 16-2:
Virtual Address OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP
Bits
All Resets
Bit Range
(BF84_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
4000 OC1CON
15:0 ON SIDL OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
4010 OC1R OC1R<31:0>
15:0 xxxx
31:16 xxxx
4020 OC1RS OC1RS<31:0>
15:0 xxxx
31:16 0000
4200 OC2CON
31:16 xxxx

4210 OC2R OC2R<31:0>
15:0 xxxx
31:16 xxxx
4220 OC2RS OC2RS<31:0>
15:0 xxxx
31:16 0000
4400 OC3CON
31:16 xxxx
4410 OC3R OC3R<31:0>
15:0 xxxx
31:16 xxxx
4420 OC3RS OC3RS<31:0>
15:0 xxxx
31:16 0000
4600 OC4CON
31:16 xxxx
4610 OC4R OC4R<31:0>
15:0 xxxx
31:16 xxxx
4620 OC4RS OC4RS<31:0>
15:0 xxxx
31:16 0000
4800 OC5CON
31:16 xxxx
4810 OC5R OC5R<31:0>
15:0 xxxx
DS60001361E-page 295
31:16 xxxx
4820 OC5RS OC5RS<31:0>
15:0 xxxx
more information.
DS60001361E-page 296
TABLE 16-2: OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP (CONTINUED)

Virtual Address
Bits
All Resets
Bit Range
(BF84_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
4A00 OC6CON
31:16 xxxx
4A10 OC6R OC6R<31:0>
15:0 xxxx
31:16 xxxx
4A20 OC6RS OC6RS<31:0>
15:0 xxxx
31:16 0000
4C00 OC7CON
31:16 xxxx
4C10 OC7R OC7R<31:0>
15:0 xxxx
31:16 xxxx
4C20 OC7RS OC7RS<31:0>
15:0 xxxx
31:16 0000
4E00 OC8CON
31:16 xxxx
4E10 OC8R OC8R<31:0>
15:0 xxxx
31:16 xxxx
4E20 OC8RS OC8RS<31:0>
15:0 xxxx
31:16 0000
5000 OC9CON
31:16 xxxx
5010 OC9R OC9R<31:0>
15:0 xxxx
31:16
5020 OC9RS OC9RS<31:0> xxxx
15:0
more information.
REGISTER 16-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
15:8
ON SIDL
U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
OC32 OCFLT(1) OCTSEL(2) OCM<2:0>
Legend:

bit 15 ON: Output Compare Peripheral On bit
1 = Output Compare peripheral is enabled
0 = Output Compare peripheral is disabled
1 = Discontinue operation when CPU enters Idle mode
0 = Continue operation in Idle mode
bit 5 OC32: 32-bit Compare Mode bit
1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisions to the 32-bit timer source
0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source
bit 4 OCFLT: PWM Fault Condition Status bit(1)
1 = PWM Fault condition has occurred (cleared in HW only)
0 = No PWM Fault condition has occurred
bit 3 OCTSEL: Output Compare Timer Select bit(2)
1 = Timery is the clock source for this Output Compare module
0 = Timerx is the clock source for this Output Compare module
bit 2-0 OCM<2:0>: Output Compare Mode Select bits
111 = PWM mode on OCx; Fault pin enabled
110 = PWM mode on OCx; Fault pin disabled
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current
Note 1: This bit is only used when OCM<2:0> = 111. It is read as 0 in all other modes.
2: Refer to Table 16-1 for Timerx and Timery selections.

NOTES:

17.0 DEADMAN TIMER (DMT) The primary function of the Deadman Timer (DMT) is
to reset the processor in the event of a software mal-
Note: This data sheet summarizes the features function. The DMT is a free-running instruction fetch
of the PIC32MZ Graphics (DA) Family timer, which is clocked whenever an instruction fetch
family of devices. It is not intended to be a occurs until a count match occurs. Instructions are not
comprehensive reference source. To fetched when the processor is in Sleep mode.
complement the information in this data The DMT consists of a 32-bit counter with a time-out
sheet, refer to Section 9. Watchdog, count match value as specified by the DMTCNT<3:0>
Deadman, and Power-up Timers bits in the DEVCFG1 Configuration register.
Documentation > Reference Manual A Deadman Timer is typically used in mission critical
section of the Microchip PIC32 web site and safety critical applications, where any single fail-
(www.microchip.com/pic32). ure of the software functionality and sequencing must
be detected.
Figure 17-1 shows a block diagram of the Deadman
Timer module.
FIGURE 17-1: DEADMAN TIMER BLOCK DIAGRAM
improper sequence flag

ON
Instruction Fetched Strobe
Force DMT Event
System Reset
Counter Initialization Value
PBCLK7 32-bit counter

Clock ON
Proper Clear Sequence Flag
32
DMT event
ON to NMI(3)
DMT Count Reset Load
System Reset
(COUNTER) = DMT Max Count(1)

(COUNTER) DMT Window Interval(2)
Window Interval Open
Note 1: DMT Max Count is controlled by the DMTCNT<3:0> bits in the DEVCFG1 Configuration register.
2: DMT Window Interval is controlled by the DMTINTV<2:0> bits in the DEVCFG1 Configuration register.
3: Refer to Section 6.0 Resets for more information.

DS60001361E-page 300
17.1 Deadman Timer Control Registers

TABLE 17-1: DEADMAN TIMER REGISTER MAP
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0A00 DMTCON
15:0 ON 0000
31:16 0000
0A10 DMTPRECLR
15:0 STEP1<7:0> 0000
31:16 0000
0A20 DMTCLR
15:0 STEP2<7:0> 0000
31:16 0000
0A30 DMTSTAT
15:0 BAD1 BAD2 DMTEVENT WINOPN 0000
31:16 0000
0A40 DMTCNT COUNTER<31:0>
15:0 0000
31:16 0000
0A60 DMTPSCNT PSCNT<31:0>
15:0 0000
31:16 0000
0A70 DMTPSINTV PSINTV<31:0>
15:0 0000
REGISTER 17-1: DMTCON: DEADMAN TIMER CONTROL REGISTER
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8 (1)
ON
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:

bit 15 ON: Deadman Timer Module Enable bit(1)
1 = Deadman Timer module is enabled
0 = Deadman Timer module is disabled
Note 1: This bit only has control when FDMTEN (DEVCFG1<3>) = 0.
REGISTER 17-2: DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER

Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
STEP1<7:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:

bit 15-8 STEP1<7:0>: Preclear Enable bits
01000000 = Enables the Deadman Timer Preclear (Step 1)
All other write patterns = Set BAD1 flag.
These bits are cleared when a DMT reset event occurs. STEP1<7:0> is also cleared if the
STEP2<7:0> bits are loaded with the correct value in the correct sequence.

REGISTER 17-3: DMTCLR: DEADMAN TIMER CLEAR REGISTER
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
STEP2<7:0>
Legend:

bit 7-0 STEP2<7:0>: Clear Timer bits
00001000 = Clears STEP1<7:0>, STEP2<7:0> and the Deadman Timer if, and only if, preceded by cor-
rect loading of STEP1<7:0> bits in the correct sequence. The write to these bits may be
verified by reading the DMTCNT bit and observing the counter being reset.
All other write patterns = Set BAD2 bit, the value of STEP1<7:0> will remain unchanged, and the new
value being written STEP2<7:0> will be captured. These bits are also cleared when a DMT reset event
occurs.

REGISTER 17-4: DMTSTAT: DEADMAN TIMER STATUS REGISTER
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R-0, HC R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R-0
7:0
BAD1 BAD2 DMTEVENT WINOPN
Legend: HC = Cleared by Hardware


bit 7 BAD1: Bad STEP1<7:0> Value Detect bit
1 = Incorrect STEP1<7:0> value was detected
0 = Incorrect STEP1<7:0> value was not detected
bit 6 BAD2: Bad STEP2<7:0> Value Detect bit
1 = Incorrect STEP2<7:0> value was detected
0 = Incorrect STEP2<7:0> value was not detected
bit 5 DMTEVENT: Deadman Timer Event bit
1 = Deadman timer event was detected (counter expired or bad STEP1<7:0> or STEP2<7:0> value was
entered prior to counter increment)
0 = Deadman timer event was not detected
bit 0 WINOPN: Deadman Timer Clear Window bit
1 = Deadman timer clear window is open
0 = Deadman timer clear window is not open

REGISTER 17-5: DMTCNT: DEADMAN TIMER COUNT REGISTER
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
COUNTER<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
COUNTER<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
COUNTER<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
COUNTER<7:0>
Legend:
bit 31-8 COUNTER<31:0>: Read current contents of DMT counter
REGISTER 17-6: DMTPSCNT: POST STATUS CONFIGURE DMT COUNT STATUS REGISTER
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
PSCNT<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
PSCNT<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
PSCNT<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
PSCNT<7:0>
Legend:
bit 31-8 PSCNT<31:0>: DMT Instruction Count Value Configuration Status bits
This is always the value of the DMTCNT<3:0> bits in the DEVCFG1 Configuration register.

REGISTER 17-7: DMTPSINTV: POST STATUS CONFIGURE DMT INTERVAL STATUS REGISTER
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
PSINTV<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
PSINTV<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
PSINTV<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
PSINTV<7:0>
Legend:
bit 31-8 PSINTV<31:0>: DMT Window Interval Configuration Status bits

This is always the value of the DMTINTV<2:0> bits in the DEVCFG1 Configuration register.

NOTES:

18.0 WATCHDOG TIMER (WDT) When enabled, the Watchdog Timer (WDT) operates
from the internal Low-Power Oscillator (LPRC) clock
Note: This data sheet summarizes the features source and can be used to detect system software mal-
of the PIC32MZ Graphics (DA) Family functions by resetting the device if the WDT is not
family of devices. It is not intended to be a cleared periodically in software. Various WDT time-out
comprehensive reference source. To periods can be selected using the WDT postscaler. The
complement the information in this data WDT can also be used to wake the device from Sleep
sheet, refer to Section 9. Watchdog, or Idle mode.
Deadman, and Power-up Timers The following are some of the key features of the WDT
(DS60001114), which is available from the module:
section of the Microchip PIC32 web site Configuration or software controlled
(www.microchip.com/pic32). User-configurable time-out period
Can wake the device from Sleep or Idle
FIGURE 18-1: WATCHDOG TIMER BLOCK DIAGRAM
Clock
ON
LPRC 25-bit Counter
WDTCLR = 1
ON 25
Wake 0
WDT Counter Reset WDT Event
ON 1 to NMI(1)
Reset Event
Power Save
Decoder
WDTPS<4:0> (DEVCFG1<20:16>)
Note 1: Refer to Section 6.0 Resets for more information.

DS60001361E-page 308
18.1 Watchdog Timer Control Registers

TABLE 18-1: WATCHDOG TIMER REGISTER MAP
All Resets
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 WDTCLRKEY<15:0> 0000

0800 WDTCON(1)
15:0 ON RUNDIV<4:0> SLPDIV<4:0> WDTWINEN xxxx
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for more information.
REGISTER 18-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
31:24
WDTCLRKEY<15:8>
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
23:16
WDTCLRKEY<7:0>
R/W-0 U-0 U-0 R-y R-y R-y R-y R-y
15:8
ON(1) RUNDIV<4:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
7:0
SLPDIV<4:0> WDTWINEN
Legend: y = Values set from Configuration bits on POR

bit 31-16 WDTCLRKEY<15:0>: Watchdog Timer Clear Key bits

To clear the Watchdog Timer to prevent a time-out, software must write the value 0x5743 to these bits using
a single 16-bit write.
bit 15 ON: Watchdog Timer Enable bit(1)
1 = The Watchdog Timer module is enabled
0 = The Watchdog Timer module is disabled
bit 12-8 RUNDIV<4:0>: Watchdog Timer Postscaler Value in Run Mode bits
In Run mode, these bits are set to the values of the WDTPS<4:0> Configuration bits in DEVCFG1.
bit 5-1 SLPDIV<4:0>: Watchdog Timer Postscaler Value in Sleep Mode bits
In Sleep mode, these bits are set to the values of the SWDTPS <4:0> Configuration bits in DEVCFG4.
bit 0 WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disable windowed Watchdog Timer
Note 1: This bit only has control when FWDTEN (DEVCFG1<23>) = 0.

NOTES:

19.0 DEEP SLEEP WATCHDOG The Deep Sleep Watchdog Timer (DSWDT) is a dedi-
cated Watchdog Timer for Deep Sleep mode opera-
TIMER (DSWDT) tions of the device. The DSWDT is very useful in
Note: This data sheet summarizes the features Battery-powered applications and in Low-Power
of the PIC32MZ Graphics (DA) Family modes of operations.
family of devices. It is not intended to be a The primary function of the DSWDT is to automatically
comprehensive reference source. To exit Deep Sleep mode after a prescribed amount of
complement the information in this data time has elapsed.
sheet, refer to Section 9. Watchdog,
The DSWDT is controlled through the DEVCFG2
Deadman, and Power-up Timers
Configuration register at boot time (one-time
programmable per POR). When enabled through the
DSWDTEN bit in DEVCFG2, the DSWDT operates
either from the internal Low-Power RC (LPRC) clock
or from the Secondary Oscillator (SOSC). The clock
selection for the DSWDT is done through the
DSWDTOSC bit in the DEVCFG2 register.
FIGURE 19-1: DEEP SLEEP WATCHDOG TIMER BLOCK DIAGRAM
DSWDTPS<4:0> (DEVCFG2<25:21>) Postscaler

DSWDT event
Compare
DSWDTEN (DEVCFG2<27>)
LPRC 0
5-bit Prescaler 31-bit Counter
SOSC 1
DSWDTOSC (DEVCFG2<26>)
Example: When DSWDTOSC = 1, DSWDTPS<4:0> bits = 00000, and the SOSC is 32 kHz, the Watchdog delay is set to 1 ms.

NOTES:

20.0 REAL-TIME CLOCK AND Key features of the RTCC module include:
CALENDAR (RTCC) Time: hours, minutes and seconds
24-hour format (military time)
Note: This data sheet summarizes the Visibility of one-half second period
features of the PIC32MZ Graphics (DA)
Provides calendar: Weekday, date, month and year
Family of devices. It is not intended to
be a comprehensive reference source. Alarm intervals are configurable for half of a second,
To complement the information in this one second, 10 seconds, one minute, 10 minutes,
data sheet, refer to Section 29. Real- one hour, one day, one week, one month, and one
Time Clock and Calendar (RTCC) year
(DS60001125), which is available from Alarm repeat with decrementing counter
the Documentation > Reference Manual Alarm with indefinite repeat: Chime
section of the Microchip PIC32 web site Year range: 2000 to 2099
Leap year correction
The RTCC module is intended for applications in which BCD format for smaller firmware overhead
accurate time must be maintained for extended periods Optimized for long-term battery operation
of time with minimal or no CPU intervention. Low- Fractional second synchronization
power optimization provides extended battery lifetime User calibration of the clock crystal frequency with
while keeping track of time.
auto-adjust
The RTCC module can operate in VBAT mode when Calibration range: 0.66 seconds error per month
there is a power loss on the VDDIO pin. The RTCC will Calibrates up to 260 ppm of crystal error
continue to operate if the VBAT pin is powered on (it is
usually connected to the battery). Uses external crystal or internal oscillator
Alarm pulse, seconds clock, or internal clock output
on RTCC pin
Note: RTCC pin function is not available during
VBAT operation.
FIGURE 20-1: RTCC BLOCK DIAGRAM

RTCCLKSEL<1:0>
Secondary Oscillator (SOSC)
Internal Oscillator (LPRC)

TRTC
RTCC Prescalers
0.5 seconds YEAR, MTH, DAY
RTCC Timer RTCVAL WKDAY
Alarm HR, MIN, SEC
Event
Comparator
MTH, DAY
Compare Registers ALRMVAL WKDAY
with Masks
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
Alarm Pulse
RTCC Interrupt Logic
Seconds Pulse
RTCC Pin
TRTC RTCOE
RTCOUTSEL<1:0>

DS60001361E-page 314
20.1 RTCC Control Registers

TABLE 20-1: RTCC REGISTER MAP
All Resets
Bit Range
(BF8C_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 CAL<9:0> 0000

0000 RTCCON
15:0 ON SIDL RTCCLKSEL<1:0> RTCOUTSEL<1:0> RTCCLKON RTCWREN RTCSYNC HALFSEC RTCOE 0000
31:16 0000
0010 RTCALRM
15:0 ALRMEN CHIME PIV ALRMSYNC AMASK<3:0> ARPT<7:0> 0000
31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx
0020 RTCTIME
15:0 SEC10<3:0> SEC01<3:0> xx00
31:16 YEAR10<3:0> YEAR01<3:0> MONTH10<3:0> MONTH01<3:0> xxxx
0030 RTCDATE
15:0 DAY10<3:0> DAY01<3:0> WDAY01<3:0> xx00
31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx
0040 ALRMTIME
15:0 SEC10<3:0> SEC01<3:0> xx00
31:16 MONTH10<3:0> MONTH01<3:0> 00xx
0050 ALRMDATE
15:0 DAY10<3:0> DAY01<3:0> WDAY01<3:0> xx0x
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for more
information.
REGISTER 20-1: RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
31:24
CAL<9:8>
23:16
CAL<7:0>
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8 RTC
ON(1) SIDL RTCCLKSEL<1:0>
OUTSEL<1>(2)
R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0
7:0 RTC RTC RTC RTC (4)
HALFSEC RTCOE
OUTSEL<0>(2) CLKON WREN(3) SYNC
Legend:

bit 25-16 CAL<9:0>: Real-Time Clock Drift Calibration bits, which contain a signed 10-bit integer value
0111111111 = Maximum positive adjustment, adds 511 real-time clock pulses every one minute

0000000001 = Minimum positive adjustment, adds 1 real-time clock pulse every one minute
0000000000 = No adjustment
1111111111 = Minimum negative adjustment, subtracts 1 real-time clock pulse every one minute

1000000000 = Minimum negative adjustment, subtracts 512 real-time clock pulses every one minute
bit 15 ON: RTCC On bit(1)
1 = RTCC module is enabled
0 = RTCC module is disabled
1 = Disables RTCC operation when CPU enters Idle mode
0 = Continue normal operation when CPU enters Idle mode
Note 1: The ON bit is only writable when RTCWREN = 1.

2: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
3: The RTCWREN bit can be set only when the write sequence is enabled.
4: This bit is read-only. It is cleared to 0 on a write to the seconds bit fields (RTCTIME<14:8>).
Note: This register is reset only on a Power-on Reset (POR).

REGISTER 20-1: RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER
bit 10-9 RTCCLKSEL<1:0>: RTCC Clock Select bits
When a new value is written to these bits, the Seconds Value register should also be written to properly
reset the clock prescalers in the RTCC.
11 = Reserved
10 = Reserved
01 = RTCC uses the external 32.768 kHz Secondary Oscillator (SOSC)
00 = RTCC uses the internal 32 kHz oscillator (LPRC)
bit 8-7 RTCOUTSEL<1:0>: RTCC Output Data Select bits(2)
11 = Reserved
10 = RTCC Clock is presented on the RTCC pin
01 = Seconds Clock is presented on the RTCC pin
00 = Alarm Pulse is presented on the RTCC pin when the alarm interrupt is triggered
bit 6 RTCCLKON: RTCC Clock Enable Status bit
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
bit 3 RTCWREN: Real-Time Clock Value Registers Write Enable bit(3)
1 = Real-Time Clock Value registers can be written to by the user
0 = Real-Time Clock Value registers are locked out from being written to by the user
bit 2 RTCSYNC: Real-Time Clock Value Registers Read Synchronization bit
1 = Real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid
data read). If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = Real-time clock value registers can be read without concern about a rollover ripple
bit 1 HALFSEC: Half-Second Status bit(4)
1 = Second half period of a second
0 = First half period of a second
bit 0 RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is not enabled
Note 1: The ON bit is only writable when RTCWREN = 1.

2: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
3: The RTCWREN bit can be set only when the write sequence is enabled.
4: This bit is read-only. It is cleared to 0 on a write to the seconds bit fields (RTCTIME<14:8>).

REGISTER 20-2: RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
ALRMEN(1,2) CHIME(2) PIV (2)
ALRMSYNC AMASK<3:0> (2)

7:0
ARPT<7:0>(2)
Legend:

bit 15 ALRMEN: Alarm Enable bit(1,2)
1 = Alarm is enabled
0 = Alarm is disabled
bit 14 CHIME: Chime Enable bit(2)
1 = Chime is enabled ARPT<7:0> is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled ARPT<7:0> stops once it reaches 0x00
bit 13 PIV: Alarm Pulse Initial Value bit(2)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
bit 12 ALRMSYNC: Alarm Sync bit
1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing.
0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is more than
32 real-time clocks away from a half-second rollover
bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(2)
0000 = Every half-second
0001 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29, once every four years)
1010 = Reserved
1011 = Reserved
11xx = Reserved
Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
2: This field should not be written when the RTCC ON bit = 1 (RTCCON<15>) and ALRMSYNC = 1.

REGISTER 20-2: RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER (CONTINUED)
bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits(2)
11111111 = Alarm will trigger 256 times

00000000 = Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.
Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
2: This field should not be written when the RTCC ON bit = 1 (RTCCON<15>) and ALRMSYNC = 1.

REGISTER 20-3: RTCTIME: REAL-TIME CLOCK TIME VALUE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
HR10<3:0> HR01<3:0>
23:16
MIN10<3:0> MIN01<3:0>
15:8
SEC10<3:0> SEC01<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:
bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10<3:0>: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9
Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).

REGISTER 20-4: RTCDATE: REAL-TIME CLOCK DATE VALUE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
YEAR10<3:0> YEAR01<3:0>
23:16
MONTH10<3:0> MONTH01<3:0>
15:8
DAY10<3:0> DAY01<3:0>
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
7:0
WDAY01<3:0>
Legend:
bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10 digits

bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1 digit
bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3
bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9
bit 3-0 WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6
Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).

REGISTER 20-5: ALRMTIME: ALARM TIME VALUE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
HR10<3:0> HR01<3:0>
23:16
MIN10<3:0> MIN01<3:0>
15:8
SEC10<3:0> SEC01<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:
bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9

REGISTER 20-6: ALRMDATE: ALARM DATE VALUE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
MONTH10<3:0> MONTH01<3:0>
15:8
DAY10<1:0> DAY01<3:0>
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
7:0
WDAY01<3:0>
Legend:

bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3
bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9
bit 3-0 WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6

21.0 SERIAL PERIPHERAL The SPI/I2S module is compatible with Motorola SPI
and SIOP interfaces.
INTERFACE (SPI) AND
INTER-IC SOUND (I2S) Some of the key features of the SPI module are:
Master and Slave modes support
Note: This data sheet summarizes the features Four different clock formats
of the PIC32MZ Graphics (DA) Family of Enhanced Framed SPI protocol support
devices. It is not intended to be a User-configurable 8-bit, 16-bit and 32-bit data width
comprehensive reference source. To Separate SPI FIFO buffers for receive and transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
sheet, refer to Section 23. Serial
based on 32/16/8-bit data width
Peripheral Interface (SPI)
(DS60001106), which is available from the Programmable interrupt event on every 8-bit,
16-bit and 32-bit data transfer
section of the Microchip PIC32 web site Operation during Sleep and Idle modes
(www.microchip.com/pic32). Audio Codec Support:
- I2S protocol
The SPI/I2S module is a synchronous serial interface - Left-justified
that is useful for communicating with external - Right-justified
peripherals and other microcontroller devices, as well - PCM
as digital audio devices. These peripheral devices may
be Serial EEPROMs, Shift registers, display drivers,
Analog-to-Digital Converters (ADC), etc.
FIGURE 21-1: SPI/I2S MODULE BLOCK DIAGRAM

Internal
Data Bus
SPIxBUF
Read Write
FIFOs Share Address SPIxBUF
SPIxRXB FIFO SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx bit 0
SDOx Shift MCLKSEL

Control
Slave Select Clock Edge
and Frame Control Select
SSx/FSYNC Sync Control REFCLKO1
Baud Rate
Generator
SCKx
PBCLK2
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register. MSTEN

DS60001361E-page 324
21.1 SPI Control Registers

TABLE 21-1: SPI1 THROUGH SPI6 REGISTER MAP
All Resets
Bit Range
(BF82_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> MCLKSEL SPIFE ENHBUF 0000
1000 SPI1CON
15:0 ON SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI STXISEL<1:0> SRXISEL<1:0> 0000
31:16 RXBUFELM<4:0> TXBUFELM<4:0> 0000
1010 SPI1STAT
15:0 FRMERR SPIBUSY SPITUR SRMT SPIROV SPIRBE SPITBE SPITBF SPIRBF 00A8
31:16 0000
1020 SPI1BUF DATA<31:0>
15:0 0000
31:16 0000
1030 SPI1BRG
15:0 BRG<12:0> 0000
31:16 0000
1040 SPI1CON2 SPI FRM SPI SPI AUD
15:0 IGNROV IGNTUR AUDEN AUDMOD<1:0> 0C00
SGNEXT ERREN ROVEN TUREN MONO
1200 SPI2CON
1210 SPI2STAT
15:0 FRMERR SPIBUSY SPITUR SRMT SPIROV SPIRBE SPITBE SPITBF SPIRBF 0008
31:16 0000
15:0 0000
31:16 0000
1230 SPI2BRG
15:0 BRG<8:0> 0000
31:16 0000
15:0 IGNROV IGNTUR AUDEN AUDMOD<1:0> 0000
1400 SPI3CON

1410 SPI3STAT
31:16 0000
15:0 0000
31:16 0000
1430 SPI3BRG
15:0 BRG<8:0> 0000
31:16 0000
Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and
INV Registers for more information.
TABLE 21-1: SPI1 THROUGH SPI6 REGISTER MAP (CONTINUED)
All Resets
Bit Range
(BF82_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
1600 SPI4CON
1610 SPI4STAT
31:16 0000
15:0 0000
31:16 0000
1630 SPI4BRG
15:0 BRG<8:0> 0000
31:16 0000

1800 SPI5CON
1810 SPI5STAT
31:16 0000
15:0 0000
31:16 0000
1830 SPI5BRG
15:0 BRG<8:0> 0000
31:16 0000
1A00 SPI6CON
1A10 SPI6STAT
31:16 0000
1A20 SPI6BUF DATA<31:0>
15:0 0000
31:16 0000
1A30 SPI6BRG
15:0 BRG<8:0> 0000
31:16 0000
DS60001361E-page 325
1A40 SPI6CON2 SPI FRM SPI SPI AUD

Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and
REGISTER 21-1: SPIxCON: SPI CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0>
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
23:16
MCLKSEL(1) SPIFE ENHBUF(1)
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
ON SIDL DISSDO(4) MODE32 MODE16 SMP CKE(2)
7:0
SSEN CKP(3) MSTEN DISSDI(4) STXISEL<1:0> SRXISEL<1:0>
Legend:
bit 31 FRMEN: Framed SPI Support bit

1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)
1 = Frame pulse is active-high
0 = Frame pulse is active-low
bit 28 MSSEN: Master Mode Slave Select Enable bit
1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in
Master mode. Polarity is determined by the FRMPOL bit.
0 = Slave select SPI support is disabled.
bit 27 FRMSYPW: Frame Sync Pulse Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per
pulse. This bit is only valid in Framed mode.
111 = Reserved
110 = Reserved
101 = Generate a frame sync pulse on every 32 data characters
000 = Generate a frame sync pulse on every data character
bit 23 MCLKSEL: Master Clock Enable bit(1)
1 = REFCLKO1 is used by the Baud Rate Generator
0 = PBCLK2 is used by the Baud Rate Generator
Note 1: This bit can only be written when the ON bit = 0. Refer to Section 44.0 Electrical Characteristics for
maximum clock frequency requirements.
2: This bit is not used in the Framed SPI mode. The user should program this bit to 0 for the Framed SPI
mode (FRMEN = 1).
3: When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to 1, regardless of the actual
value of the CKP bit.
4: This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see
Section 12.4 Peripheral Pin Select (PPS) for more information).

REGISTER 21-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)
bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
bit 16 ENHBUF: Enhanced Buffer Enable bit(1)
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
bit 15 ON: SPI/I2S Module On bit
1 = SPI/I2S module is enabled
0 = SPI/I2S module is disabled
1 = Discontinue operation when CPU enters in Idle mode
bit 12 DISSDO: Disable SDOx pin bit(4)
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module
bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits
When AUDEN = 1:
MODE32 MODE16 Communication
1 1 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame
When AUDEN = 0:
MODE32 MODE16 Communication
1 x 32-bit
0 1 16-bit
0 0 8-bit
bit 9 SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
bit 8 CKE: SPI Clock Edge Select bit(2)
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
bit 7 SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used for Slave mode, pin controlled by port function.
bit 6 CKP: Clock Polarity Select bit(3)
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
mode (FRMEN = 1).

REGISTER 21-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
bit 4 DISSDI: Disable SDI bit(4)
1 = SDI pin is not used by the SPI module (pin is controlled by PORT function)
0 = SDI pin is controlled by the SPI module
bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)
mode (FRMEN = 1).

REGISTER 21-2: SPIxCON2: SPI CONTROL REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
SPISGNEXT FRMERREN SPIROVEN SPITUREN IGNROV IGNTUR
R/W-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0
7:0
AUDEN(1) AUDMONO(1,2) AUDMOD<1:0>(1,2)
Legend:

bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit
1 = Data from RX FIFO is sign extended
0 = Data from RX FIFO is not sign extened
bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit
1 = Frame Error overflow generates error events
0 = Frame Error does not generate error events
bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit
1 = Receive overflow generates error events
0 = Receive overflow does not generate error events
bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit
1 = Transmit Underrun Generates Error Events
0 = Transmit Underrun Does Not Generates Error Events
bit 9 IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions)
1 = A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data
0 = A ROV is a critical error which stop SPI operation
bit 8 IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions)
1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty
0 = A TUR is a critical error which stop SPI operation
bit 7 AUDEN: Enable Audio CODEC Support bit(1)
1 = Audio protocol enabled
0 = Audio protocol disabled
bit 3 AUDMONO: Transmit Audio Data Format bit(1,2)
1 = Audio data is mono (Each data word is transmitted on both left and right channels)
0 = Audio data is stereo
bit 1-0 AUDMOD<1:0>: Audio Protocol Mode bit(1,2)
11 = PCM/DSP mode
10 = Right Justified mode
01 = Left Justified mode
00 = I2S mode
Note 1: This bit can only be written when the ON bit = 0.

2: This bit is only valid for AUDEN = 1.

REGISTER 21-3: SPIxSTAT: SPI STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
31:24
RXBUFELM<4:0>
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
23:16
TXBUFELM<4:0>
U-0 U-0 U-0 R/C-0, HS R-0 U-0 U-0 R-0
15:8
FRMERR SPIBUSY SPITUR
R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0
7:0
SRMT SPIROV SPIRBE SPITBE SPITBF SPIRBF
Legend: C = Clearable bit HS = Hardware Set


bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (valid only when ENHBUF = 1)
bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (valid only when ENHBUF = 1)
bit 12 FRMERR: SPI Frame Error status bit
1 = Frame error detected
0 = No Frame error detected
This bit is only valid when FRMEN = 1.
bit 11 SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
bit 8 SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling
the module.
bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
bit 6 SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 5 SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1)
1 = RX FIFO is empty (CRPTR = SWPTR)
0 = RX FIFO is not empty (CRPTR SWPTR)

REGISTER 21-3: SPIxSTAT: SPI STATUS REGISTER
bit 3 SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 1 SPITBF: SPI Transmit Buffer Full Status bit
1 = Transmit not yet started, SPITXB is full
0 = Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.
Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
bit 0 SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise

NOTES:

22.0 SERIAL QUAD INTERFACE Data transfer:
(SQI) - Programmed I/O mode (PIO)
- Buffer descriptor DMA
Note: This data sheet summarizes the features Supports SPI Mode 0 and Mode 3
Programmable Clock Polarity (CPOL) and Clock
Phase (CPHA) bits
complement the information in this data Supports up to two Chip Selects
sheet, refer to Section 46. Serial Quad Supports up to four bytes of Flash address
Interface (SQI) (DS60001244), which is Programmable interrupt thresholds
available from the Documentation > 32-byte transmit data buffer
Reference Manual section of the 32-byte receive data buffer
Microchip PIC32 web site
4-word controller buffer
Note: Once the SQI module is configured,
The SQI module is a synchronous serial interface that external devices are memory mapped
provides access to serial Flash memories and other into KSEG2 (see Figure 4-1 through
serial devices. The SQI module supports Single Lane Figure 4-2 in Section 4.0 Memory
(identical to SPI), Dual Lane, and Quad Lane modes. Organization for more information).
The following are some of the key features of the SQI The MMU must be enabled and the TLB
module: must be set up to access this memory
(see Section 50. CPU for Devices with
Supports Single, Dual, and Quad Lane modes
MIPS32 microAptiv and M-Class
Supports Single Data Rate (SDR) and Double Cores (DS60001192) in the PIC32
Data Rate (DDR) modes Family Reference Manual for more
Programmable command sequence information).
eXecute-In-Place (XIP)
FIGURE 22-1: SQI MODULE BLOCK DIAGRAM
PBCLK5(2)
REFCLKO2(1) SQID0
Control
(TBC)
Buffer
SQID1
SQID2
Control and
Status Transmit
Bus Slave Buffer
Registers SQID3
(PIO)
System Bus
SQI Master
Interface SQICLK
SQICS0
Receive
Bus Master DMA Buffer
SQICS1
Note 1: When configuring the REFCLKO2 clock source, a value of 0 for the ROTRIM<8:0> bits must be selected.
REFCLKO2 must be turned on before SQI Special Function Registers (SFR) access.
2: This clock source is only used for SQI Special Function Register (SFR) access.

DS60001361E-page 334
22.1 SQI Control Registers

TABLE 22-1: SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP
Virtual Address
Bits
All Resets
Bit Range
(BF8E_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
DDR DDR DDR

SQI1 31:16 SDRCMD DDRDATA DDRCMD DUMMYBYTES<2:0> ADDRBYTES<2:0> READOPCODE<7:6> 0000
2000 DUMMY MODE ADDR
XCON1
15:0 READOPCODE<5:0> TYPEDATA<1:0> TYPEDUMMY<1:0> TYPEMODE<1:0> TYPEADDR<1:0> TYPECMD<1:0> 0000
SQI1 31:16 0000
2004
XCON2 15:0 DEVSEL<1:0> MODEBYTES<1:0> MODECODE<7:0> 0000
CON
31:16 CSEN<1:0> SQIEN DATAEN<1:0> RXBUFST TXBUFST RESET 0000
2008 SQI1CFG BUFRST
15:0 BURSTEN HOLD WP LSBF CPOL CPHA MODE<2:0> 0000
31:16 SCHECK DDRMODE DASSERT DEVSEL<1:0> LANEMODE<1:0> CMDINIT<1:0> 0000
200C SQI1CON
15:0 TXRXCOUNT<15:0> 0000
SQI1 31:16 CLKDIV<10:8> 0000
2010
CLKCON 15:0 CLKDIV<7:0> STABLE EN 0000
SQI1 31:16 0000
2014
CMDTHR 15:0 TXCMDTHR<5:0> RXCMDTHR<5:0> 0000
SQI1 31:16 0000
2018
INTTHR 15:0 TXINTTHR<5:0> RXINTTHR<5:0> 0000
31:16 0000
SQI1
201C PKT BD CON CON CON RX RX RX TX TX TX
INTEN 15:0 DMAEIE 0000
COMPIE DONEIE THRIE EMPTYIE FULLIE THRIE FULLIE EMPTYIE THRIE FULLIE EMPTYIE
31:16 0000
SQI1
2020 PKT BD CON CON CON RX RX RX TX TX TX
INTSTAT 15:0 DMAEIF 0000
COMPIF DONEIF THRIF EMPTYIF FULLIF THRIF FULLIF EMPTYIF THRIF FULLIF EMPTYIF
SQI1 31:16 TXDATA<31:16> 0000
2024
TXDATA 15:0 TXDATA<15:0> 0000
SQI1 31:16 RXDATA<31:16> 0000
2028
RXDATA 15:0 RXDATA<15:0> 0000
SQI1 31:16 TXBUFFREE<5:0> 0000
202C
STAT1 15:0 RXBUFCNT<5:0> 0000
SQI1 31:16 CMDSTAT<1:0> 0000
2030
STAT2 15:0 CONAVAIL<3:0> SDID3 SDID2 SDID1 SDID0 RXUN TXOV 00x0
SQI1 31:16 0000
2034
BDCON 15:0 START POLLEN DMAEN 0000
SQI1BD 31:16 BDCURRADDR<31:16> 0000
2038
CURADD 15:0 BDCURRADDR<15:0> 0000
SQI1BD 31:16 BDADDR<31:16> 0000
2040
BASEADD 15:0 BDADDR<15:0> 0000
TABLE 22-1: SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF8E_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
DMA
SQI1BD 31:16 BDSTATE<3:0> DMAACTV 0000
2044 START
STAT
15:0 BDCON<15:0> 0000
SQI1BD 31:16 0000
2048
POLLCON 15:0 POLLCON<15:0> 0000
SQI1BD 31:16 TXSTATE<3:0> TXBUFCNT<5:0> 0000
204C
TXDSTAT 15:0 TXCURBUFLEN<8:0> 0000
SQI1BD 31:16 RXSTATE<3:0> RXBUFCNT<5:0> 0000
2050
RXDSTAT 15:0 RXCURBUFLEN<8:0> 0000
31:16 0000
2054 SQI1THR
15:0 THRES<3:0> 0000

31:16 0000
SQI1INT
2058 DMAEIS PKT BD CON CON CON RX RX RX TX TX TX
SIGEN 15:0 0000
E DONEISE DONEISE THRISE EMPTYISE FULLISE THRISE FULLISE EMPTYISE THRISE FULLISE EMPTYISE
SQI1 31:16 DDRCLKINDLY<5:0> SDRDATINDLY<3:0> DDRDATINDLY<3:0> 0000
205C
TAPCON 15:0 SDRCLKINDLY<5:0> DATAOUTDLY<3:0> CLKOUTDLY<3:0> 0000
SQI1 31:16 STATPOS TYPESTAT<1:0> STATBYTES<1:0> 0000
2060
MEMSTAT 15:0 STATCMD<15:0> 0000
INIT1
SQI1 31:16 INIT1COUNT<1:0> INIT1TYPE<1:0> INIT1CMD3<7:0> 0000
2064 SCHECK
XCON3
15:0 INIT1CMD2<7:0> INIT1CMD1<7:0> 0000
INIT2
SQI1 31:16 INIT2COUNT<1:0> INIT2TYPE<1:0> INIT2CMD3<7:0> 0000
2068 SCHECK
XCON4
15:0 INIT2CMD2<7:0> INIT2CMD1<7:0> 0000
DS60001361E-page 335
REGISTER 22-1: SQI1XCON1: SQI XIP CONTROL REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
SDRCMD DDRDATA DDRDUMMY DDRMODE DDRADDR DDRCMD(1)
23:16
DUMMYBYTES<2:0> ADDRBYTES<2:0> READOPCODE<7:6>
15:8
READOPCODE<5:0> TYPEDATA<1:0>
7:0
TYPEDUMMY<1:0> TYPEMODE<1:0> TYPEADDR<1:0> TYPECMD<1:0>
Legend:

bit 29 SDRCMD: SQI Command in SDR Mode bit
1 = SQI command is in SDR mode and SQI data is in DDR mode
0 = SQI command is in DDR mode and SQI data is in DDR mode
bit 28 DDRDATA: SQI Data DDR Mode bit
1 = SQI data bytes are transferred in DDR mode
0 = SQI data bytes are transferred in SDR mode
bit 27 DDRDUMMY: SQI Dummy DDR Mode bit
1 = SQI dummy bytes are transferred in DDR mode
0 = SQI dummy bytes are transferred in SDR mode
bit 26 DDRMODE: SQI DDR Mode bit
1 = SQI mode bytes are transferred in DDR mode
0 = SQI mode bytes are transferred in SDR mode
bit 25 DDRADDR: SQI Address Mode bit
1 = SQI address bytes are transferred in DDR mode
0 = SQI address bytes are transferred in SDR mode
bit 24 DDRCMD: SQI DDR Command Mode bit(1)
1 = SQI command bytes are transferred in DDR mode
0 = SQI command bytes are transferred in SDR mode
bit 23-21 DUMMYBYTES<2:0>: Transmit Dummy Bytes bits
111 = Transmit seven dummy bytes after the address bytes

011 = Transmit three dummy bytes after the address bytes
010 = Transmit two dummy bytes after the address bytes
001 = Transmit one dummy bytes after the address bytes
000 = Transmit zero dummy bytes after the address bytes
Note 1: When DDRCMD is set to 0, the SQI module will ignore the value in the SDRCMD bit.

REGISTER 22-1: SQI1XCON1: SQI XIP CONTROL REGISTER 1 (CONTINUED)
bit 20-18 ADDRBYTES<2:0>: Address Cycle bits
111 = Reserved

101 = Reserved
100 = Four address bytes
011 = Three address bytes
010 = Two address bytes
001 = One address bytes
000 = Zero address bytes
bit 17-10 READOPCODE<7:0>: Op code Value for Read Operation bits
These bits contain the 8-bit op code value for read operation.
bit 9-8 TYPEDATA<1:0>: SQI Type Data Enable bits
The boot controller will receive the data in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode data is enabled
01 = Dual Lane mode data is enabled
00 = Single Lane mode data is enabled
bit 7-6 TYPEDUMMY<1:0>: SQI Type Dummy Enable bits
The boot controller will send the dummy in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode dummy is enabled
01 = Dual Lane mode dummy is enabled
00 = Single Lane mode dummy is enabled
bit 5-4 TYPEMODE<1:0>: SQI Type Mode Enable bits
The boot controller will send the mode in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode is enabled
01 = Dual Lane mode is enabled
00 = Single Lane mode is enabled
bit 3-2 TYPEADDR<1:0>: SQI Type Address Enable bits
The boot controller will send the address in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode address is enabled
01 = Dual Lane mode address is enabled
00 = Single Lane mode address is enabled
bit 1-0 TYPECMD<1:0>: SQI Type Command Enable bits
The boot controller will send the command in Single Lane, Dual Lane, or Quad Lane.
11 = Reserved
10 = Quad Lane mode command is enabled
01 = Dual Lane mode command is enabled
00 = Single Lane mode command is enabled
Note 1: When DDRCMD is set to 0, the SQI module will ignore the value in the SDRCMD bit.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
DEVSEL<1:0> MODEBYTES<1:0>
7:0
MODECODE<7:0>
Legend:

bit 11-10 DEVSEL<1:0>: Device Select bits
11 = Reserved
10 = Reserved
01 = Device 1 is selected
00 = Device 0 is selected
bit 9-8 MODEBYTES<1:0>: Mode Byte Cycle Enable bits
11 = Three cycles
10 = Two cycles
01 = One cycle
00 = Zero cycles
bit 7-0 MODECODE<7:0>: Mode Code Value bits
These bits contain the 8-bit code value for the mode bits.

REGISTER 22-3: SQI1CFG: SQI CONFIGURATION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
31:24
CSEN<1:0>
R/W-0 U-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
23:16 CON RX TX
SQIEN DATAEN<1:0> RESET
BUFRST BUFRST BUFRST
U-0 r-0 r-0 R/W-0 r-0 R/W-0 R/W-0 U-0
15:8
BURSTEN(1) HOLD WP
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
LSBF CPOL CPHA MODE<2:0>
Legend: HC = Hardware Cleared r = Reserved


bit 25-24 CSEN<1:0>: Chip Select Output Enable bits
11 = Chip Select 0 and Chip Select 1 are used
10 = Chip Select 1 is used (Chip Select 0 is not used)
01 = Chip Select 0 is used (Chip Select 1 is not used)
00 = Chip Select 0 and Chip Select 1 are not used
bit 23 SQIEN: SQI Enable bit
1 = SQI module is enabled
0 = SQI module is disabled
bit 21-20 DATAEN<1:0>: Data Output Enable bits
11 = Reserved
10 = SQID3-SQID0 outputs are enabled
01 = SQID1 and SQID0 data outputs are enabled
00 = SQID0 data output is enabled
bit 19 CONBUFRST: Control Buffer Reset bit
1 = A reset pulse is generated clearing the control buffer
0 = A reset pulse is not generated
bit 18 RXBUFRST: Receive Buffer Reset bit
1 = A reset pulse is generated clearing the receive buffer
bit 17 TXBUFRST: Transmit Buffer Reset bit
1 = A reset pulse is generated clearing the transmit buffer
bit 16 RESET: Software Reset Select bit
This bit is automatically cleared by the SQI module. All of the internal state machines and buffer pointers
are reset by this reset pulse.
1 = A reset pulse is generated
bit 14-13 Reserved: Must be programmed as 0
Note 1: This bit must be programmed as 1.

REGISTER 22-3: SQI1CFG: SQI CONFIGURATION REGISTER (CONTINUED)
bit 12 BURSTEN: Burst Configuration bit(1)
1 = Burst is enabled
0 = Burst is not enabled
bit 11 Reserved: Must be programmed as 0
bit 10 HOLD: Hold bit
In Single Lane or Dual Lane mode, this bit is used to drive the SQID3 pin, which can be used for devices
with a HOLD input pin. The meaning of the values for this bit will depend on the device to which SQID3 is
connected.
bit 9 WP: Write Protect bit
In Single Lane or Dual Lane mode, this bit is used to drive the SQID2 pin, which can be used with devices
with a write-protect pin. The meaning of the values for this bit will depend on the device to which SQID2 is
connected.
bit 5 LSBF: Data Format Select bit
1 = LSB is sent or received first
0 = MSB is sent or received first
bit 4 CPOL: Clock Polarity Select bit
1 = Active-low SQICLK (SQICLK high is the Idle state)
0 = Active-high SQICLK (SQICLK low is the Idle state)
bit 3 CPHA: Clock Phase Select bit
1 = SQICLK starts toggling at the start of the first data bit
0 = SQICLK starts toggling at the middle of the first data bit
bit 2-0 MODE<2:0>: Mode Select bits
111 = Reserved

100 = Reserved
011 = XIP mode is selected (when this mode is entered, the module behaves as if executing in place (XIP),
but uses the register data to control timing)
010 = DMA mode is selected
001 = CPU mode is selected (the module is controlled by the CPU in PIO mode. This mode is entered when
leaving Boot or XIP mode)
000 = Reserved
Note 1: This bit must be programmed as 1.

REGISTER 22-4: SQI1CON: SQI CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 r-0 R/W-0
31:24
SCHECK(1)
23:16
DDRMODE DASSERT DEVSEL<1:0> LANEMODE<1:0> CMDINIT<1:0>
15:8
TXRXCOUNT<15:8>
7:0
TXRXCOUNT<7:0>

bit 25 Reserved: Must be programmed as 0
bit 24 SCHECK: Flash Status Check bit(1)
1 = Check the status of the Flash
0 = Do not check the status of the Flash
bit 23 DDRMODE: Double Data Rate Mode bit
1 = Set the SQI transfers to DDR mode
0 = Set the SQI transfers to SDR mode
bit 22 DASSERT: Chip Select Assert bit
1 = Chip Select is deasserted after transmission or reception of the specified number of bytes
0 = Chip Select is not deasserted after transmission or reception of the specified number of bytes
bit 21-20 DEVSEL<1:0>: SQI Device Select bits
11 = Reserved
10 = Reserved
01 = Select Device 1
00 = Select Device 0
bit 19-18 LANEMODE<1:0>: SQI Lane Mode Select bits
11 = Reserved
10 = Quad Lane mode
01 = Dual Lane mode
00 = Single Lane mode
bit 17-16 CMDINIT<1:0>: Command Initiation Mode Select bits
If it is Transmit, commands are initiated based on a write to the transmit register or the contents of TX
buffer. If CMDINIT is Receive, commands are initiated based on reads to the read register or RX buffer
availability.
11 = Reserved
10 = Receive
01 = Transmit
00 = Idle
bit 15-0 TXRXCOUNT<15:0>: Transmit/Receive Count bits
These bits specify the total number of bytes to transmit or received (based on CMDINIT).
Note 1: When this bit is set to 1, the SQI module uses the SQI1MEMSTAT register to control the status check
command process.

REGISTER 22-5: SQI1CLKCON: SQI CLOCK CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
23:16
CLKDIV<10:8>(1)
15:8 (1)
CLKDIV<7:0>
U-0 U-0 U-0 U-0 U-0 U-0 R-0 R/W-0
7:0
STABLE EN
Legend:

bit 18-8 CLKDIV<10:0>: SQI Clock TSQI Frequency Select bit(1)
10000000000 = Base clock TBC is divided by 2048
00000000000 = Base clock TBC
Setting these bits to 00000000 specifies the highest frequency of the SQI clock.
bit 1 STABLE: TSQI Clock Stable Select bit
This bit is set to 1 when the SQI clock, TSQI, is stable after writing a 1 to the EN bit.
1 = TSQI clock is stable
0 = TSQI clock is not stable
bit 0 EN: TSQI Clock Enable Select bit
When clock oscillation is stable, the SQI module will set the STABLE bit to 1.
1 = Enable the SQI clock (TSQI) (when clock oscillation is stable, the SQI module sets the STABLE bit to 1)
0 = Disable the SQI clock (TSQI) (the SQI module should stop its clock to enter a low power state); SFRs
can still be accessed, as they use PBCLK5
Note 1: Refer to Table 44-41 in 44.0 Electrical Characteristics for the maximum clock frequency
specifications.

REGISTER 22-6: SQI1CMDTHR: SQI COMMAND THRESHOLD REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
TXCMDTHR<5:0>
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RXCMDTHR<5:0>(1)
Legend:

bit 13-8 TXCMDTHR<5:0>: Transmit Command Threshold bits
In transmit initiation mode, the SQI module performs a transmit operation when transmit command
threshold bytes are present in the TX buffer. These bits should usually be set to 1 for normal Flash
commands, and set to a higher value for page programming. For 16-bit mode, the value should be a
multiple of 2.
bit 5-0 RXCMDTHR<5:0>: Receive Command Threshold bits(1)
In receive initiation mode, the SQI module attempts to perform receive operations to fetch the receive com-
mand threshold number of bytes in the receive buffer. If space for these bytes is not present in the buffer,
the SQI will not initiate a transfer. For 16-bit mode, the value should be a multiple of 2.
If software performs any reads, thereby reducing the buffer count, hardware would initiate a receive transfer
to make the buffer count equal to the value in these bits. If software would not like any more words latched
into the buffer, command initiation mode needs to be changed to Idle before any buffer reads by software.
In the case of Boot/XIP mode, the SQI module will use the System Bus burst size, instead of the receive
command threshold value.
Note 1: These bits should only be programmed when a receive is not active (i.e., during Idle mode or a transmit).

REGISTER 22-7: SQI1INTTHR: SQI INTERRUPT THRESHOLD REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
TXINTTHR<5:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RXINTTHR<5:0>
Legend:

bit 13-8 TXINTTHR<5:0>: Transmit Interrupt Threshold bits
A transmit interrupt is set when the transmit buffer has more space than the set number of bytes. For 16-bit
mode, the value should be a multiple of 2.
bit 5-0 RXINTTHR<5:0>: Receive Interrupt Threshold bits
A receive interrupt is set when the receive buffer count is larger than or equal to the set number of bytes.
For 16-bit mode, the value should be multiple of 2.

REGISTER 22-8: SQI1INTEN: SQI INTERRUPT ENABLE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
DMAEIE PKTCOMPIE BDDONEIE CONTHRIE
7:0
CONEMPTYIE CONFULLIE RXTHRIE RXFULLIE RXEMPTYIE TXTHRIE TXFULLIE TXEMPTYIE


bit 11 DMAEIE: DMA Bus Error Interrupt Enable bit
bit 10 PKTCOMPIE: DMA Buffer Descriptor Packet Complete Interrupt Enable bit
bit 9 BDDONEIE: DMA Buffer Descriptor Done Interrupt Enable bit
bit 8 CONTHRIE: Control Buffer Threshold Interrupt Enable bit
bit 7 CONEMPTYIE: Control Buffer Empty Interrupt Enable bit
bit 6 CONFULLIE: Control Buffer Full Interrupt Enable bit
This bit enables an interrupt when the receive buffer is full.
bit 5 RXTHRIE: Receive Buffer Threshold Interrupt Enable bit
bit 4 RXFULLIE: Receive Buffer Full Interrupt Enable bit
bit 3 RXEMPTYIE: Receive Buffer Empty Interrupt Enable bit
bit 2 TXTHRIE: Transmit Threshold Interrupt Enable bit
bit 1 TXFULLIE: Transmit Buffer Full Interrupt Enable bit
bit 0 TXEMPTYIE: Transmit Buffer Empty Interrupt Enable bit

REGISTER 22-9: SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS
15:8 DMA PKT BD CON

EIF COMPIF DONEIF THRIF
7:0 CON CON (1) RX TX
RXTHRIF RXFULLIF TXTHRIF TXFULLIF
EMPTYIF FULLIF EMPTYIF EMPTYIF


bit 11 DMAEIF: DMA Bus Error Interrupt Flag bit
1 = DMA bus error has occurred
0 = DMA bus error has not occurred
bit 10 PKTCOMPIF: DMA Buffer Descriptor Processor Packet Completion Interrupt Flag bit
1 = DMA BD packet is complete
0 = DMA BD packet is in progress
bit 9 BDDONEIF: DMA Buffer Descriptor Done Interrupt Flag bit
1 = DMA BD process is done
0 = DMA BD process is in progress
bit 8 CONTHRIF: Control Buffer Threshold Interrupt Flag bit
1 = The control buffer has more than THRES words of space available
0 = The control buffer has less than THRES words of space available
bit 7 CONEMPTYIF: Control Buffer Empty Interrupt Flag bit
1 = Control buffer is empty
0 = Control buffer is not empty
bit 6 CONFULLIF: Control Buffer Full Interrupt Flag bit
1 = Control buffer is full
0 = Control buffer is not full
bit 5 RXTHRIF: Receive Buffer Threshold Interrupt Flag bit(1)
1 = Receive buffer has more than RXINTTHR words of space available
0 = Receive buffer has less than RXINTTHR words of space available
bit 4 RXFULLIF: Receive Buffer Full Interrupt Flag bit
1 = Receive buffer is full
0 = Receive buffer is not full
bit 3 RXEMPTYIF: Receive Buffer Empty Interrupt Flag bit
1 = Receive buffer is empty
0 = Receive buffer is not empty
Note 1: In the case of Boot/XIP mode, the POR value of the receive buffer threshold is zero. Therefore, this bit will
be set to a 1, immediately after a POR until a read request on the System Bus bus is received.
Note: The bits in the register are cleared by writing a '1' to the corresponding bit position.

REGISTER 22-9: SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER (CONTINUED)
bit 2 TXTHRIF: Transmit Buffer Threshold Interrupt Flag bit
1 = Transmit buffer has more than TXINTTHR words of space available
0 = Transmit buffer has less than TXINTTHR words of space available
bit 1 TXFULLIF: Transmit Buffer Full Interrupt Flag bit
1 = The transmit buffer is full
0 = The transmit buffer is not full
bit 0 TXEMPTYIF: Transmit Buffer Empty Interrupt Flag bit
1 = The transmit buffer is empty
0 = The transmit buffer has content
Note 1: In the case of Boot/XIP mode, the POR value of the receive buffer threshold is zero. Therefore, this bit will
be set to a 1, immediately after a POR until a read request on the System Bus bus is received.
Note: The bits in the register are cleared by writing a '1' to the corresponding bit position.

REGISTER 22-10: SQI1TXDATA: SQI TRANSMIT DATA BUFFER REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
TXDATA<31:24>
23:16
TXDATA<23:16>
15:8
TXDATA<15:8>
7:0
TXDATA<7:0>
Legend:
bit 31-0 TXDATA<31:0>: Transmit Command Data bits

Data is loaded into this register before being transmitted. Just prior to the beginning of a data transfer, the
data in TXDATA is loaded into the shift register (SFDR).
Multiple writes to TXDATA can occur even while a transfer is already in progress. There can be a maximum
of eight commands that can be queued.
REGISTER 22-11: SQI1RXDATA: SQI RECEIVE DATA BUFFER REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
RXDATA<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
RXDATA<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
RXDATA<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
RXDATA<7:0>
Legend:
bit 31-0 RXDATA<31:0>: Receive Data Buffer bits

At the end of a data transfer, the data in the shift register is loaded into the RXDATA register. This register
works like a buffer. The depth of the receive buffer is eight words.

REGISTER 22-12: SQI1STAT1: SQI STATUS REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
TXBUFFREE<5:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
RXBUFCNT<5:0>
Legend:

bit 21-16 TXBUFFREE<5:0>: Transmit buffer Available Word Space bits
bit 5-0 RXBUFCNT<5:0>: Number of words of read data in the buffer

REGISTER 22-13: SQI1STAT2: SQI STATUS REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0
23:16
CMDSTAT<1:0>
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
15:8
CONAVAIL<3:1>
R-0 R-0 R-0 R-0 R-0 U-0 R-0 R-0
7:0
CONAVAIL<0> SQID3 SQID2 SQID1 SQID0 RXUN TXOV
Legend:

bit 17-16 CMDSTAT<1:0>: Current Command Status bits
These bits indicate the current command status.
11 = Reserved
10 = Receive
01 = Transmit
00 = Idle
bit 10-7 CONAVAIL<3:0>: Control buffer Space Available bits
These bits indicate the available control word space.
1000 = 8 words are available
0111 = 7 words are available

0001 = 1 word is available
0000 = No words are available
bit 6 SQID3: SQID3 Status bit
1 = Data is present on SQID3
0 = Data is not present on SQID3
bit 1 RXUN: Receive buffer Underflow Status bit
1 = Receive buffer Underflow has occurred
0 = Receive buffer underflow has not occurred
bit 0 TXOV: Transmit buffer Overflow Status bit
1 = Transmit buffer overflow has occurred
0 = Transmit buffer overflow has not occurred

REGISTER 22-14: SQI1BDCON: SQI BUFFER DESCRIPTOR CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
7:0
START POLLEN DMAEN
Legend:

bit 2 START: Buffer Descriptor Processor Start bit
1 = Start the buffer descriptor processor
0 = Disable the buffer descriptor processor
bit 1 POLLEN: Buffer Descriptor Poll Enable bit
1 = BDP poll is enabled
0 = BDP poll is not enabled
1 = DMA is enabled
0 = DMA is disabled
REGISTER 22-15: SQI1BDCURADD: SQI BUFFER DESCRIPTOR CURRENT ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
BDCURRADDR<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
BDCURRADDR<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
BDCURRADDR<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
BDCURRADDR<7:0>
Legend:
bit 31-0 BDCURRADDR<31:0>: Current Buffer Descriptor Address bits

These bits contain the address of the current descriptor being processed by the Buffer Descriptor
Processor.

REGISTER 22-16: SQI1BDBASEADD: SQI BUFFER DESCRIPTOR BASE ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
BDADDR<31:24>
23:16
BDADDR<23:16>
15:8
BDADDR<15:8>
7:0
BDADDR<7:0>
Legend:
bit 31-0 BDADDR<31:0>: DMA Base Address bits

These bits contain the physical address of the root buffer descriptor. This register should be updated only
when the DMA is idle.
REGISTER 22-17: SQI1BDSTAT: SQI BUFFER DESCRIPTOR STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 R-x R-x R-x R-x R-x R-x
23:16
BDSTATE<3:0> DMASTART DMAACTV
15:8
BDCON<15:8>
7:0
BDCON<7:0>
Legend:

bit 21-18 BDSTATE<3:0>: DMA Buffer Descriptor Processor State Status bits
These bits return the current state of the buffer descriptor processor:
5 = Fetched buffer descriptor is disabled
4 = Descriptor is done
3 = Data phase
2 = Buffer descriptor is loading
1 = Descriptor fetch request is pending
0 = Idle
bit 17 DMASTART: DMA Buffer Descriptor Processor Start Status bit
1 = DMA has started
0 = DMA has not started
bit 16 DMAACTV: DMA Buffer Descriptor Processor Active Status bit
1 = Buffer Descriptor Processor is active
0 = Buffer Descriptor Processor is idle
bit 15-0 BDCON<15:0>: DMA Buffer Descriptor Control Word bits
These bits contain the current buffer descriptor control word.

REGISTER 22-18: SQI1BDPOLLCON: SQI BUFFER DESCRIPTOR POLL CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
POLLCON<15:8>
7:0
POLLCON<7:0>
Legend:

bit 15-0 POLLCON<15:0>: Buffer Descriptor Processor Poll Status bits
These bits indicate the number of cycles the BDP would wait before refetching the descriptor control word
if the previous descriptor fetched was disabled.
REGISTER 22-19: SQI1BDTXDSTAT: SQI BUFFER DESCRIPTOR DMA TRANSMIT STATUS

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R-x R-x R-x R-x U-0
31:24
TXSTATE<3:0>
U-0 U-0 U-0 R-x R-x R-x R-x R-x
23:16
TXBUFCNT<4:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
TXCURBUFLEN<7:0>
Legend:

bit 28-25 TXSTATE<3:0>: Current DMA Transmit State Status bits
These bits provide information on the current DMA receive states.
bit 20-16 TXBUFCNT<4:0>: DMA Buffer Byte Count Status bits
These bits provide information on the internal buffer space.
bit 7-0 TXCURBUFLEN<7:0>: Current DMA Transmit Buffer Length Status bits
These bits provide the length of the current DMA transmit buffer.

REGISTER 22-20: SQI1BDRXDSTAT: SQI BUFFER DESCRIPTOR DMA RECEIVE STATUS

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R-x R-x R-x R-x U-0
31:24
RXSTATE<3:0>
U-0 U-0 U-0 R-x R-x R-x R-x R-x
23:16
RXBUFCNT<4:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
RXCURBUFLEN<7:0>
Legend:

bit 28-25 RXSTATE<3:0>: Current DMA Receive State Status bits
These bits provide information on the current DMA receive states.
bit 20-16 RXBUFCNT<4:0>: DMA Buffer Byte Count Status bits
These bits provide information on the internal buffer space.
bit 7-0 RXCURBUFLEN<7:0>: Current DMA Receive Buffer Length Status bits
These bits provide the length of the current DMA receive buffer.
REGISTER 22-21: SQI1THR: SQI THRESHOLD CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
THRES<3:0>
Legend:

bit 3-0 THRES<3:0>: SQI Control Threshold Value bits
The SQI control threshold interrupt is asserted when the amount of space indicated by THRES<6:0> is
available in the SQI control buffer.

REGISTER 22-22: SQI1INTSIGEN: SQI INTERRUPT SIGNAL ENABLE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8 PKT BD CON
DMAEISE
DONEISE DONEISE THRISE
7:0 CON CON RX RX RX TX TX TX
EMPTYISE FULLISE THRISE FULLISE EMPTYISE THRISE FULLISE EMPTYISE
Legend:

bit 11 DMAEISE: DMA Bus Error Interrupt Signal Enable bit
1 = Interrupt signal is enabled
0 = Interrupt signal is disabled
bit 10 PKTDONEISE: Receive Error Interrupt Signal Enable bit
bit 9 BDDONEISE: Transmit Error Interrupt Signal Enable bit
bit 8 CONTHRISE: Control Buffer Threshold Interrupt Signal Enable bit
bit 7 CONEMPTYISE: Control Buffer Empty Interrupt Signal Enable bit
bit 6 CONFULLISE: Control Buffer Full Interrupt Signal Enable bit
bit 5 RXTHRISE: Receive Buffer Threshold Interrupt Signal Enable bit
bit 4 RXFULLISE: Receive Buffer Full Interrupt Signal Enable bit
bit 3 RXEMPTYISE: Receive Buffer Empty Interrupt Signal Enable bit
bit 2 TXTHRISE: Transmit Buffer Threshold Interrupt Signal Enable bit
bit 1 TXFULLISE: Transmit Buffer Full Interrupt Signal Enable bit
bit 0 TXEMPTYISE: Transmit Buffer Empty Interrupt Signal Enable bit

REGISTER 22-23: SQI1TAPCON: SQI TAP CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
DDRCLKINDLY<5:0>
23:16
SDRDATINDLY<3:0> DDRDATINDLY<3:0>
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
SDRCLKINDLY<5:0>
7:0
DATAOUTDLY<3:0> CLKOUTDLY<3:0>
Legend:

bit 29-24 DDRCLKINDLY<5:0>: SQI Clock Input Delay in DDR Mode bits
These bits are used to add fractional delays to SQI Clock Input while sampling the incoming data in DDR
mode.
111111 = 64 taps added on clock input

000000 = 1 tap added on clock input
bit 23-20 SDRDATINDLY<3:0>: SQI Data Input Delay in SDR Mode bits
These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash in SDR
mode.
1111 = 16 taps added on data input

0000 = 1 tap added on data input
bit 19-16 DDRDATINDLY<3:0>: SQI Data Output Delay in DDR Mode bits
These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash in DDR
mode.

0000 = 1 tap added on data input

REGISTER 22-23: SQI1TAPCON: SQI TAP CONTROL REGISTER (CONTINUED)
bit 13-8 SDRCLKINDLY<5:0>: SQI Clock Input Delay in SDR Mode bits
These bits are used to add fractional delays to SQI Clock Input while sampling the incoming data in DDR
mode.

000000 = 1 tap added on clock input
bit 7-4 DATAOUTDLY<3:0>: SQI Data Output Delay bits
These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash in all
modes of operation.
1111 = 16 taps added on data output

0000 = 1 tap added on data output
bit 3-0 CLKOUTDLY<3:0>: SQI Clock Output Delay bits
These bits are used to add fractional delays to SQI Clock Output while writing the data to the Flash in all
modes of operation.
1111 = 16 taps added on clock output

0000 = 1 tap added on clock output

REGISTER 22-24: SQI1MEMSTAT: SQI MEMORY STATUS CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
STATPOS STATTYPE<1:0> STATBYTES<1:0>
15:8
STATCMD<15:8>
7:0
STATCMD<7:0>
Legend:

bit 20 STATPOS: Status Bit Position in Flash bit
Indicates the BUSY bit position in the Flash Status register. This bit is added to support all Flash types
(with BUSY bit at 0 and at 7).
1 = BUSY bit position is bit 7 in status register
0 = BUSY bit position is bit 0 in status register
bit 19-18 STATTYPE<1:0>: Status Command Lane Mode bits
11 = Reserved
10 = Status command and read are executed in Quad Lane mode
01 = Status command and read are executed in Dual Lane mode
00 = Status command and read are executed in Single Lane mode
bit 17-16 STATBYTES<1:0>: Number of Status Bytes bits
11 = Reserved
10 = Status command is 2 bytes long
01 = Status command is 1 byte long
00 = Reserved
bit 15-0 STATCMD<15:0>: Status Command bits
The status check command is written into these bits


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
INIT1SCHECK INIT1COUNT<1:0> INIT1TYPE<1:0>
23:16
INIT1CMD3<7:0>
15:8
INIT1CMD2<7:0>
7:0
INIT1CMD1<7:0>
Legend:

bit 28 INIT1SCHECK: Flash Initialization 1 Command Status Check bit
1 = Check the status after executing the INIT1 commands
0 = Do not check the status
bit 27-26 INIT1COUNT<1:0>: Flash Initialization 1 Command Count bits
11 = INIT1CMD1, INIT1CMD2, and INIT1CMD3 are sent
10 = INIT1CMD1 and INIT1CMD2 are sent, but INIT1CMD3 is still pending
01 = INIT1CMD1 is sent, but INIT1CMD2 and INIT1CMD3 are still pending
00 = No commands are sent
bit 25-24 INIT1TYPE<1:0>: Flash Initialization 1 Command Type bits
11 = Reserved
10 = INIT1 commands are sent in Quad Lane mode
01 = INIT1 commands are sent in Dual Lane mode
00 = INIT1 commands are sent in Single Lane mode
bit 24-16 INIT1CMD3<7:0>: Flash Initialization Command 3 bits
Third command of the Flash initialization.
Second command of the Flash initialization.
First command of the Flash initialization.
Note: Some Flash devices require write enable and sector unprotect commands before write/read operations and
this register is useful in working with those Flash types (XIP mode only)


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
INIT2SCHECK INIT2COUNT<1:0> INIT2TYPE<1:0>
23:16
INIT2CMD3<7:0>
15:8
INIT2CMD2<7:0>
7:0
INIT2CMD1<7:0>
Legend:

bit 28 INIT2SCHECK: Flash Initialization 2 Command Status Check bit
1 = Check the status after executing the INIT2 commands
0 = Do not check the status
bit 27-26 INIT2COUNT<1:0>: Flash Initialization 2 Command Count bits
11 = INIT2CMD1, INIT2CMD2, and INIT2CMD3 are sent
10 = INIT2CMD1 and INIT2CMD2 are sent, but INIT2CMD3 is still pending
01 = INIT2CMD1 is sent, but INIT2CMD2 and INIT2CMD3 are still pending
00 = No commands are sent
bit 25-24 INIT2TYPE<1:0>: Flash Initialization 2 Command Type bits
11 = Reserved
10 = INIT2 commands are sent in Quad Lane mode
01 = INIT2 commands are sent in Dual Lane mode
00 = INIT2 commands are sent in Single Lane mode
Third command of the Flash initialization.
Second command of the Flash initialization.
First command of the Flash initialization.
Note: Some Flash devices require write enable and sector unprotect commands before write/read operations and
this register is useful in working with those Flash types (XIP mode only)

23.0 INTER-INTEGRATED CIRCUIT Each I2C module offers the following key features:
(I2C) I2C interface supporting both master and slave
operation
Note: This data sheet summarizes the features I2C Slave mode supports 7-bit and 10-bit addressing
I2C Master mode supports 7-bit and 10-bit addressing
comprehensive reference source. To I2C port allows bidirectional transfers between
complement the information in this data master and slaves
sheet, refer to Section 24. Inter- Serial clock synchronization for the I2C port can be
Integrated Circuit (I2C) (DS60001116), used as a handshake mechanism to suspend and
which is available from the Documentation resume serial transfer (SCLREL control)
> Reference Manual section of the I2C supports multi-master operation; detects bus
Microchip PIC32 web site collision and arbitrates accordingly
(www.microchip.com/pic32). Provides support for address bit masking
The I2C module provides complete hardware support SMBus support
for both Slave and Multi-Master modes of the I2C serial Figure 23-1 illustrates the I2C module block diagram.
communication standard.
Each I2C module has a 2-pin interface:
SCLx pin is clock
SDAx pin is data

FIGURE 23-1: I2C BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx Clock
I2CxRSR
LSB
SDAx Address Match

Match Detect Write
I2CxMSK
Write Read
I2CxADD
Read
Start and Stop

Bit Detect
Write
Start and Stop

Bit Generation I2CxSTAT
Control Logic
Read
Collision Write
Detect
I2CxCON
Acknowledge
Generation Read
Clock
Stretching
Write
I2CxTRN
LSB
Shift Clock Read
Reload
Control
Write
BRG Down Counter I2CxBRG
Read
PBCLK2

23.1 I2C Control Registers
TABLE 23-1:
Virtual Address I2C1 THROUGH I2C5 REGISTER MAP
Bits
All Resets
Bit Range
(BF82_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000

0000 I2C1CON
15:0 ON SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
31:16 0000
0010 I2C1STAT
15:0 ACKSTAT TRSTAT ACKTIM BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
31:16 0000
0020 I2C1ADD
15:0 ADD<9:0> 0000
31:16 0000
0030 I2C1MSK
15:0 ADD<9:0> 0000
31:16 0000
0040 I2C1BRG

15:0 I2C1BRG<15:0> 0000
31:16 0000
0050 I2C1TRN
15:0 I2C1TXDATA<7:0> 0000
31:16 0000
0060 I2C1RCV
15:0 I2C1RXDATA<7:0> 0000
0200 I2C2CON
31:16 0000
0210 I2C2STAT
31:16 0000
0220 I2C2ADD
15:0 ADD<9:0> 0000
31:16 0000
0230 I2C2MSK
15:0 MSK<9:0> 0000
31:16 0000
0240 I2C2BRG
15:0 I2C2BRG<15:0> 0000
31:16 0000
0250 I2C2TRN
15:0 I2C2TXDATA<7:0> 0000
31:16 0000
0260 I2C2RCV
15:0 I2C2RXDATA<7:0> 0000
0400 I2C3CON
DS60001361E-page 363
31:16 0000
0410 I2C3STAT
31:16 0000
0420 I2C3ADD
15:0 ADD<9:0> 0000
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and
DS60001361E-page 364
TABLE 23-1: I2C1 THROUGH I2C5 REGISTER MAP (CONTINUED)

Virtual Address
Bits
All Resets
Bit Range
(BF82_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0430 I2C3MSK
15:0 ADD<9:0> 0000
31:16 0000
0440 I2C3BRG
15:0 I2C3BRG<15:0> 0000
31:16 0000
0450 I2C3TRN
15:0 I2C3TXDATA<7:0> 0000
31:16 0000
0460 I2C3RCV
15:0 I2C3RXDATA<7:0> 0000
0600 I2C4CON
31:16 0000
0610 I2C4STAT
31:16 0000
0620 I2C4ADD
15:0 ADD<9:0> 0000
31:16 0000
0630 I2C4MSK
15:0 ADD<9:0> 0000
31:16 0000
0640 I2C4BRG
15:0 I2C4BRG<15:0> 0000
31:16 0000
0650 I2C4TRN
15:0 I2C4TXDATA<7:0> 0000
31:16 0000
0660 I2C4RCV
15:0 I2C4RXDATA<7:0> 0000
0800 I2C5CON
31:16 0000
0810 I2C5STAT
31:16 0000
0820 I2C5ADD
15:0 ADD<9:0> 0000
31:16 0000
0830 I2C5MSK
15:0 ADD<9:0> 0000
31:16 0000
0840 I2C5BRG
15:0 I2C5BRG<15:0> 0000
31:16 0000
0850 I2C5TRN
15:0 I2C4TXDATA<7:0> 0000
31:16 0000
0860 I2C5RCV
15:0 I2C4RXDATA<7:0> 0000
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and
REGISTER 23-1: I2CXCON: I2C CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
15:8
ON SIDL SCLREL STRICT A10M DISSLW SMEN
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
7:0
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
Legend: HC = Cleared in Hardware


bit 22 PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 21 SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 20 BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)
1 = I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of the
I2COV bit (I2CxSTAT<6>)only if the RBF bit (I2CxSTAT<2>) = 0
0 = I2CxRCV is only updated when the I2COV bit (I2CxSTAT<6>) is clear
bit 19 SDAHT: SDA Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 18 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 18 AHEN: Address Hold Enable bit (Slave mode only)
1 = Following the 8th falling edge of SCL for a matching received address byte; SCKREL bit will be cleared
and the SCL will be held low.
0 = Address holding is disabled
bit 16 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the SCKREL bit
and SCL is held low
0 = Data holding is disabled
bit 15 ON: I2C Enable bit
1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I2C module; all I2C pins are controlled by PORT functions
1 = Discontinue module operation when device enters Idle mode

REGISTER 23-1: I2CXCON: I2C CONTROL REGISTER (CONTINUED)
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write 0 to initiate stretch and write 1 to release clock). Hardware clear at
beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write 1 to release clock). Hardware clear at beginning of slave
transmission.
bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate
addresses in reserved address space.
0 = Strict I2C Reserved Address Rule not enabled
bit 10 A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0 = General call address disabled
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Send NACK during Acknowledge
0 = Send ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0 = Receive sequence not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence.
0 = Repeated Start condition not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition not in progress

REGISTER 23-2: I2CXSTAT: I2C STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R-0, HS, HC R-0, HS, HC R/C-0, HS, HC U-0 U-0 R/C-0, HS R-0, HS, HC R-0, HS, HC
15:8
ACKSTAT TRSTAT ACKTIM BCL GCSTAT ADD10
R/C-0, HS, SC R/C-0, HS, SC R-0, HS, HC R/C-0, HS, HC R/C-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
7:0
IWCOL I2COV D_A P S R_W RBF TBF
Legend: HS = Hardware Set HC = Hardware Cleared SC = Software Cleared

-n = Value at POR 1 = Bit is set 0 = Bit is cleared C = Clearable bit

bit 15 ACKSTAT: Acknowledge Status bit
(when operating as I2C master, applicable to master transmit operation)
1 = NACK received from slave
0 = ACK received from slave
Hardware set or clear at end of slave Acknowledge.
bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13 ACKTIM: Acknowledge Time Status bit (Valid in I2C Slave mode only)
1 = I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
bit 8 ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
bit 7 IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I2C module is busy
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6 I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

REGISTER 23-2: I2CXSTAT: I2C STATUS REGISTER (CONTINUED)
bit 5 D_A: Data/Address bit (when operating as I2C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
bit 2 R_W: Read/Write Information bit (when operating as I2C slave)
1 = Read indicates data transfer is output from slave
0 = Write indicates data transfer is input to slave
Hardware set or clear after reception of I 2C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

24.0 UNIVERSAL ASYNCHRONOUS The primary features of the UART module are:
RECEIVER TRANSMITTER Full-duplex, 8-bit or 9-bit data transmission
(UART) Even, Odd or No Parity options (for 8-bit data)
One or two Stop bits
of the PIC32MZ Graphics (DA) Family of Hardware auto-baud feature
devices. It is not intended to be a Hardware flow control option
comprehensive reference source. To Fully integrated Baud Rate Generator (BRG) with
complement the information in this data 16-bit prescaler
sheet, refer to Section 21. Universal
Baud rates ranging from 76 bps to 25 Mbps at
Asynchronous Receiver Transmitter
100 MHz (PBCLK2)
(UART) (DS60001107), which is
available from the Documentation > 8-level deep First-In-First-Out (FIFO) transmit
Reference Manual section of the data buffer
Microchip PIC32 web site 8-level deep FIFO receive data buffer
(www.microchip.com/pic32). Parity, framing and buffer overrun error detection
The UART module is one of the serial I/O modules Support for interrupt-only on address detect
available in PIC32MZ DA family devices. The UART (9th bit = 1)
is a full-duplex, asynchronous communication Separate transmit and receive interrupts
channel that communicates with peripheral devices Loopback mode for diagnostic support
and personal computers through protocols, such as
RS-232, RS-485, LIN, and IrDA. The module also LIN Protocol support
supports the hardware flow control option, with IrDA encoder and decoder with 16x baud clock
UxCTS and UxRTS pins, and also includes an IrDA output for external IrDA encoder/decoder support
encoder and decoder. Auto-baud support
Ability to receive data during Sleep mode
Figure 24-1 illustrates a simplified block diagram of the
UART module.
FIGURE 24-1: UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
PBCLK2 11
10 IrDA
FRC
SYSCLK 01
PBCLK2 00 UxRTS/BCLKx
Hardware Flow Control
UxCTS
CLKSEL<1:0> UARTx Receiver UxRX

(UxMOD<18:17>)
UARTx Transmitter UxTX

DS60001361E-page 370
24.1 UART Control Registers

TABLE 24-1: UART1 THROUGH UART6 REGISTER MAP
All Resets
Bit Range
(BF82_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 SLPEN ACTIVE CLKSEL<1:0> RUNOVF 0000

2000 U1MODE(1)
15:0 ON SIDL IREN RTSMD UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
(1) 31:16 MASK<7:0> ADDR<7:0> 0000
2010 U1STA
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
31:16 0000
2020 U1TXREG
15:0 TX8 Transmit Register 0000
31:16 0000
2030 U1RXREG
15:0 RX8 Receive Register 0000
31:16 0000
2040 U1BRG(1)
15:0 Baud Rate Generator Prescaler 0000
2200 U2MODE(1)
31:16 MASK<7:0> ADDR<7:0> 0000
2210 U2STA(1)
31:16 0000
2220 U2TXREG
31:16 0000
2230 U2RXREG
(1) 31:16 0000
2240 U2BRG
2400 U3MODE(1)
31:16 MASK<7:0> ADDR<7:0> 0000

2410 U3STA(1)
31:16 0000
2420 U3TXREG
31:16 0000
2430 U3RXREG
(1) 31:16 0000
2440 U3BRG
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for more informa-
tion.
TABLE 24-1: UART1 THROUGH UART6 REGISTER MAP (CONTINUED)
All Resets
Bit Range
(BF82_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

2600 U4MODE(1)
31:16 MASK<7:0> ADDR<7:0> 0000
2610 U4STA(1)
31:16 0000
2620 U4TXREG
31:16 0000
2630 U4RXREG
(1) 31:16 0000
2640 U4BRG

2800 U5MODE(1)
31:16 MASK<7:0> ADDR<7:0> 0000
2810 U5STA(1)
31:16 0000
2820 U5TXREG
31:16 0000
2830 U5RXREG
31:16 0000
2840 U5BRG(1)
2A00 U6MODE(1)
31:16 MASK<7:0> ADDR<7:0> 0000
2A10 U6STA(1)
31:16 0000
2A20 U6TXREG
31:16 0000
2A30 U6RXREG
31:16
DS60001361E-page 371
0000
2A40 U6BRG(1)
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for more informa-
tion.
REGISTER 24-1: UxMODE: UARTx MODE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

R/W-0 R-0, HS, HC U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
23:16
SLPEN ACTIVE CLKSEL<1:0> RUNOVF
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
15:8 (1)
ON SIDL IREN RTSMD UEN<1:0>
7:0
WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL
Legend: HS = Hardware set HC = Hardware cleared


bit 23 SLPEN: Run During Sleep Enable bit
1 = UARTx BRG clock runs during Sleep mode
0 = UARTx BRG clock is turned off during Sleep mode
Note: SLPEN = 1 only applies if CLKSEL = FRC. All clocks, as well as the UART, are disabled in Deep
Sleep mode.
bit 22 ACTIVE: UARTx Module Running Status bit
1 = UARTx module is active (UxMODE register should not be updated)
0 = UARTx module is not active (UxMODE register can be updated)
bit 18-17 CLKSEL<1:0>: UARTx Module Clock Selection bits
11 = BRG clock is PBCLK2
10 = BRG clock is FRC
01 = BRG clock is SYSCLK (turned off in Sleep mode)
00 = BRG clock is PBCLK2 (turned off in Sleep mode)
bit 16 RUNOVF: Run During Overflow Condition Mode bit
1 = When an Overflow Error (OERR) condition is detected, the shift register continues to run to remain
synchronized
0 = When an Overflow Error (OERR) condition is detected, the shift register stops accepting new data
(Legacy mode)
bit 15 ON: UARTx Enable bit
1 = UARTx module is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN
control bits
0 = UARTx module is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx,
and LATx registers; UARTx power consumption is minimal
Note 1: These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices
(see Section 12.4 Peripheral Pin Select (PPS) for more information).

REGISTER 24-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

bit 12 IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 9-8 UEN<1:0>: UARTx Module Enable bits(1)
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up enabled
0 = Wake-up disabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character requires reception of Sync character (0x55);
cleared by hardware upon completion
0 = Baud rate measurement disabled or completed
bit 4 RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is 0
0 = UxRX Idle state is 1
bit 3 BRGH: High Baud Rate Enable bit
1 = High-Speed mode 4x baud clock enabled
0 = Standard Speed mode 16x baud clock enabled
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit
Note 1: These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices
(see Section 12.4 Peripheral Pin Select (PPS) for more information).

REGISTER 24-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
MASK<7:0>
23:16
ADDR<7:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1
15:8
UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/W-0 R-0
7:0
URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA
Legend:
bit 31-25 MASK<7:0>: UARTx Address Match Mask bits

These bits are used to mask the ADDR<7:0> bits.
11111111 = Corresponding ADDRx bits are used to detect the address match
Note: This setting allows the user to assign individual address as well as a group broadcast address
to a UART.
00000000 = Corresponding ADDRx bits are not used to detect the address match.
bit 23-16 ADDR<7:0>: Automatic Address Mask bits
When the ADDEN bit is 1, this value defines the address character to use for automatic address detection.
bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13 UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is 0):
1 = UxTX Idle state is 0
0 = UxTX Idle state is 1
If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is 1):

1 = IrDA encoded UxTX Idle state is 1
0 = IrDA encoded UxTX Idle state is 0
bit 12 URXEN: Receiver Enable bit
1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module
Note: The event of disabling an enabled receiver will release the RX pin to the PORT function;
however, the receive buffers will not be reset. Disabling the receiver has no effect on the receive
status flags.
bit 11 UTXBRK: Transmit Break bit
1 = Send Break on next transmission. Start bit followed by twelve 0 bits, followed by Stop bit; cleared by
hardware upon completion
0 = Break transmission is disabled or completed

REGISTER 24-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 10 UTXEN: Transmit Enable bit
1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset
Note: The event of disabling an enabled transmitter will release the TX pin to the PORT function and
reset the transmit buffers to empty. Any pending transmission is aborted and data characters in
the transmit buffers are lost. All transmit status flags are cleared and the TRMT bit is set
bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register is Empty bit (read-only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit
11 = Reserved
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full
00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character)
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Data is being received
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit.
This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit
resets the receiver buffer and RSR to empty state.
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed
bit 0 URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty

Figure 24-2 and Figure 24-3 illustrate typical receive
and transmit timing for the UART module.
FIGURE 24-2: UART RECEPTION
Char 1 Char 2-4 Char 5-10 Char 11-13
Read to
UxRXREG
Start 1 Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13

UxRX
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
FIGURE 24-3: TRANSMISSION (8-BIT OR 9-BIT DATA)

8 into TxBUF
Write to
UxTXREG
TSR
BCLK/16 Pull from Buffer
(Shift Clock)
UxTX Start Bit 0 Bit 1 Stop Start Bit 1
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10

25.0 PARALLEL MASTER PORT Key features of the PMP module include:
(PMP) 8-bit,16-bit interface
Up to 16 programmable address lines
Up to two Chip Select lines
devices. It is not intended to be a Programmable strobe options:
comprehensive reference source. To - Individual read and write strobes, or
complement the information in this data - Read/write strobe with enable strobe
sheet, refer to Section 13. Parallel Address auto-increment/auto-decrement
Master Port (PMP) (DS60001128), Programmable address/data multiplexing
which is available from the Documentation
Programmable polarity on control signals
> Reference Manual section of the
Microchip PIC32 web site Parallel Slave Port support:
(www.microchip.com/pic32). - Legacy addressable
- Address support
The PMP is a parallel 8-bit/16-bit input/output module
- 4-byte deep auto-incrementing buffer
specifically designed to communicate with a wide
variety of parallel devices, such as communications Programmable Wait states
peripherals, LCDs, external memory devices and Operate during Sleep and Idle modes
microcontrollers. Because the interface to parallel Separate configurable read/write registers or dual
peripherals varies significantly, the PMP module is buffers for Master mode
highly configurable. Fast bit manipulation using CLR, SET, and INV
registers
FIGURE 25-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
PBCLK2
Address Bus
Data Bus
PMA0 Control Lines

Parallel PMALL
Master Port
PMA1
PMALH
Up to 16-bit Address Flash

PMA<13:2> EEPROM
SRAM
PMA14
PMCS1
PMA15
PMCS2
PMRD
PMRD/PMWR
PMWR
FIFO
PMENB Microcontroller LCD
Buffer
PMD<7:0>
PMD<15:8>
8-bit/16-bit Data (with or without multiplexed addressing)

DS60001361E-page 378
25.1 Control Registers

TABLE 25-1: PARALLEL MASTER PORT REGISTER MAP
Virtual Address
Bits
All Resets
Bit Range
(BF82_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 RDSTART DUALBUF 0000

E000 PMCON
15:0 ON SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP CS2P CS1P WRSP RDSP 0000
31:16 0000
E010 PMMODE
15:0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000
31:16 0000
E020 PMADDR CS2 CS1 0000
15:0 ADDR<13:0>
ADDR15 ADDR14 0000
31:16 0000
E030 PMDOUT
15:0 DATAOUT<15:0> 0000
31:16 0000
E040 PMDIN
15:0 DATAIN<15:0> 0000
31:16 0000
E050 PMAEN
15:0 PTEN<15:0> 0000
31:16 0000
E060 PMSTAT
15:0 IBF IBOV IB3F IB2F IB1F IB0F OBE OBUF OB3E OB2E OB1E OB0E 008F
31:16 0000
E070 PMWADDR WCS2 WCS1 0000
15:0
WADDR15 WADDR14 WADDR<13:0> 0000
31:16 0000
E080 PMRADDR RCS2 RCS1 0000
15:0
RADDR15 RADDR14 RADDR<13:0> 0000
31:16 0000
E090 PMRDIN
15:0 RDATAIN<15:0> 0000

more information.
REGISTER 25-1: PMCON: PARALLEL PORT CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

R/W-0, HC U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
23:16
RDSTART DUALBUF
15:8 (1)
ON SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
7:0 (2) (2) (2) (2)
CSF<1:0> ALP CS2P CS1P WRSP RDSP
Legend:

bit 23 RDSTART: Start Read on PMP Bus bit
This bit is cleared by hardware at the end of the read cycle.
1 = Start a read cycle on the PMP bus
0 = No effect
bit 17 DUALBUF: Parallel Master Port Dual Read/Write Buffer Enable bit
This bit is only valid in Master mode.
1 = PMP uses separate registers for reads and writes
Reads: PMRADDR and PMRDIN
Writes: PMRWADDR and PMDOUT
0 = PMP uses legacy registers for reads and writes
Reads/Writes: PMADDR and PMRDIN
bit 15 ON: Parallel Master Port Enable bit(1)
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = All 16 bits of address are multiplexed on PMD<15:0>
10 = All 16 bits of address are multiplexed on PMD<7:0>
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>
00 = Address and data appear on separate pins
bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
bit 9 PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripherals SFRs in the
SYSCLK cycle immediately following the instruction that clears the modules ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.

REGISTER 25-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 8 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
bit 7-6 CSF<1:0>: Chip Select Function bits(2)
11 = Reserved
10 = PMCS1 and PMCS2 function as Chip Select
01 = PMCS1 functions as address bit 14; PMCS2 functions as Chip Select
00 = PMCS1 and PMCS2 function as address bits 14 and 15, respectively
bit 5 ALP: Address Latch Polarity bit(2)
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4 CS2P: Chip Select 0 Polarity bit(2)
1 = Active-high (PMCS2)
0 = Active-low (PMCS2)
bit 3 CS1P: Chip Select 0 Polarity bit(2)
1 = Active-high (PMCS1)
0 = Active-low (PMCS1)
bit 1 WRSP: Write Strobe Polarity bit
For Slave Modes and Master mode 2 (MODE<1:0> = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master mode 1 (MODE<1:0> = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0 RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 (MODE<1:0> = 00,01,10):
1 = Read Strobe active-high (PMRD)
0 = Read Strobe active-low (PMRD)
For Master mode 1 (MODE<1:0> = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)
Note 1: When using 1:1 PBCLK divisor, the user software should not read/write the peripherals SFRs in the
SYSCLK cycle immediately following the instruction that clears the modules ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.

REGISTER 25-2: PMMODE: PARALLEL PORT MODE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0>
7:0 (1) (1)
WAITB<1:0> WAITM<3:0> WAITE<1:0>(1)
Legend:

bit 15 BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11 = Reserved, do not use
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> =11 (Addressable Slave mode only)
01 = Interrupt generated at the end of the read/write cycle
00 = No Interrupt generated
bit 12-11 INCM<1:0>: Increment Mode bits
11 = Slave mode read and write buffers auto-increment (MODE<1:0> = 00 only)
10 = Decrement ADDR<15:0> by 1 every read/write cycle(2)
01 = Increment ADDR<15:0> by 1 every read/write cycle(2)
00 = No increment or decrement of address
bit 10 MODE16: 8/16-bit Mode bit
1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer
0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer
bit 9-8 MODE<1:0>: Parallel Port Mode Select bits
11 = Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, PMD<7:0> and PMD<8:15>(3))
10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, PMD<7:0> and PMD<8:15>(3))
01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)
bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1)
11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB
00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)
Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select
CS2 and CS1.
3: These pins are active when MODE16 = 1 (16-bit mode).

REGISTER 25-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1)
1111 = Wait of 16 TPB

0001 = Wait of 2 TPB
0000 = Wait of 1 TPB (default)
bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1)
11 = Wait of 4 TPB
10 = Wait of 3 TPB
01 = Wait of 2 TPB
For Read operations:

11 = Wait of 3 TPB
10 = Wait of 2 TPB
01 = Wait of 1 TPB
Note 1: Whenever WAITM<3:0> = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a
write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bits, A15 and A14, are not subject to automatic increment/decrement if configured as Chip Select
CS2 and CS1.
3: These pins are active when MODE16 = 1 (16-bit mode).

REGISTER 25-3: PMADDR: PARALLEL PORT ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

(1) (3)
15:8 CS2 CS1
ADDR<13:8>
ADDR15(2) ADDR14(4)
7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADDR<7:0>
Legend:

bit 15 CS2: Chip Select 2 bit(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
bit 15 ADDR<15>: Target Address bit 15(2)
bit 14 CS1: Chip Select 1 bit(3)
bit 14 ADDR<14>: Target Address bit 14(4)
bit 13-0 ADDR<13:0>: Address bits
Note 1: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01.

2: When the CSF<1:0> bits (PMCON<7:6>) = 00.
4: When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01.
Note: If the DUALBUF bit (PMCON<17>) = 0, the bits in this register control both read and write target
addressing. If the DUALBUF bit = 1, the bits in this register are not used. In this instance, use the
PMRADDR register for Read operations and the PMWADDR register for Write operations.

REGISTER 25-4: PMDOUT: PARALLEL PORT OUTPUT DATA REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
DATAOUT<15:8>
DATAOUT<7:0>
Legend:

bit 15-0 DATAOUT<15:0>: Port Data Output bits
This register is used for Read operations in the Enhanced Parallel Slave mode and Write operations for Dual
Buffer Master mode.
In Dual Buffer Master mode, the DUALBUF bit (PMPCON<17>) = 1, a write to the MSB triggers the trans-
action on the PMP port. When MODE16 = 1, MSB = DATAOUT<15:8>. When MODE16 = 0,
MSB = DATAOUT<7:0>.
Note: In Master mode, a read will return the last value written to the register. In Slave mode, a read will return
indeterminate results.

REGISTER 25-5: PMDIN: PARALLEL PORT INPUT DATA REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
DATAIN<15:8>
DATAIN<7:0>
Legend:

bit 15-0 DATAIN<15:0>: Port Data Input bits
This register is used for both Parallel Master Port mode and Enhanced Parallel Slave mode.
In Parallel Master mode, a write to the MSB triggers the write transaction on the PMP port. Similarly, a read
to the MSB triggers the read transaction on the PMP port.
When MODE16 = 1, MSB = DATAIN<15:8>. When MODE16 = 0, MSB = DATAIN<7:0>.
Note: This register is not used in Dual Buffer Master mode (i.e., DUALBUF bit (PMPCON<17>) = 1).

REGISTER 25-6: PMAEN: PARALLEL PORT PIN ENABLE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
PTEN<15:14>(1) PTEN<13:8>
7:0
PTEN<7:2> PTEN<1:0>(2)
Legend:

bit 15-14 PTEN<15:14>: PMCSx Address Port Enable bits
1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1(1)
0 = PMA15 and PMA14 function as port I/O
bit 13-2 PTEN<13:2>: PMP Address Port Enable bits
1 = PMA<13:2> function as PMP address lines
0 = PMA<13:2> function as port I/O
bit 1-0 PTEN<1:0>: PMALH/PMALL Address Port Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2)
0 = PMA1 and PMA0 pads function as port I/O
Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>).
2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by the ADRMUX<1:0> bits in the PMCON register.

REGISTER 25-7: PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R-0 R/W-0, HS, SC U-0 U-0 R-0 R-0 R-0 R-0
15:8
IBF IBOV IB3F IB2F IB1F IB0F
R-1 R/W-0, HS, SC U-0 U-0 R-1 R-1 R-1 R-1
7:0
OBE OBUF OB3E OB2E OB1E OB0E
Legend: HS = Hardware Set SC = Software Cleared


bit 15 IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14 IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte buffer occurred (must be cleared in software)
0 = No overflow occurred
bit 11-8 IBxF: Input Buffer x Status Full bits
1 = Input Buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input Buffer does not contain any unread data
bit 7 OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6 OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte buffer (must be cleared in software)
0 = No underflow occurred
bit 3-0 OBxE: Output Buffer x Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted

REGISTER 25-8: PMWADDR: PARALLEL PORT WRITE ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

(1) (3)
15:8 WCS2 WCS1
WADDR<13:8>
WADDR15(2) WADDR14(4)
WADDR<7:0>
Legend:

bit 15 WCS2: Chip Select 2 bit(1)
bit 15 WADDR<15>: Target Address bit 15(2)
bit 14 WCS1: Chip Select 1 bit(3)
bit 14 WADDR<14>: Target Address bit 14(4)
bit 13-0 WADDR<13:0>: Address bits

Note: This register is only used when the DUALBUF bit (PMCON<17>) is set to 1.

REGISTER 25-9: PMRADDR: PARALLEL PORT READ ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

(1) (3)
15:8 RCS2 RCS1
RADDR<13:8>
RADDR15(2) RADDR14(4)
RADDR<7:0>
Legend:

bit 15 RCS2: Chip Select 2 bit(1)
0 = Chip Select 2 is inactive (RADDR15 function is selected)
bit 15 RADDR<15>: Target Address bit 15(2)
bit 14 RCS1: Chip Select 1 bit(3)
0 = Chip Select 1 is inactive (RADDR14 function is selected)
bit 14 RADDR<14>: Target Address bit 14(4)
bit 13-0 RADDR<13:0>: Address bits

Note: This register is only used when the DUALBUF bit (PMCON<17>) is set to 1.

REGISTER 25-10: PMRDIN: PARALLEL PORT READ INPUT DATA REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
RDATAIN<15:8>
RDATAIN<7:0>
Legend:

bit 15-0 RDATAIN<15:0>: Port Read Input Data bits
Note: This register is only used when the DUALBUF bit (PMCON<17>) is set to 1 and exclusively for reads. If the
DUALBUF bit is 0, the PMDIN register (Register 25-5) is used for reads instead of PMRDIN.

26.0 EXTERNAL BUS INTERFACE With the EBI module, it is possible to connect
asynchronous SRAM and NOR Flash devices, as well
(EBI) as non-memory devices such as camera sensors and
Note: This data sheet summarizes the features LCDs.
of the PIC32MZ Graphics (DA) Family of Note 1: Once the EBI module is configured,
devices. It is not intended to be a external devices will be memory mapped
comprehensive reference source. To and can be access from KSEG2 memory
complement the information in this data space (see Figure 4-1 through Figure 4-2
sheet, refer to Section 47. External Bus in Section 4.0 Memory Organization
Interface (EBI), which is available from for more information). The MMU must be
the Documentation > Reference Manual enabled and the TLB must be set up to
section of the Microchip PIC32 web site access this memory (see Section 50.
(www.microchip.com/pic32). CPU for Devices with MIPS32
microAptiv and M-Class Cores
The External Bus Interface (EBI) module provides a
(DS60001192) in the PIC32 Family
high-speed, convenient way to interface external
Reference Manual for more
parallel memory devices to the PIC32MZ DA family
information).
device.
2: When using the EBI module, Graphics
LCD (GLCD) Controller functionality is
not available, as most of the I/O between
the EBI module and the GLCD is shared.
FIGURE 26-1: EBI SYSTEM BLOCK DIAGRAM
External Bus Interface
Bus Interface Memory Interface EBIA<23:0>
EBID<15:0>
SYSCLK Control
Registers Address Decoder EBIBS<1:0>
EBICS<3:0>
System
Data Control Registers EBIOE
Bus
FIFO
EBIRP
Static Memory Controller
EBIWE
Address
FIFO EBIRDY<3:1>

DS60001361E-page 392
26.1 EBI Control Registers

TABLE 26-1: EBI REGISTER MAP
All Resets
Bit Range
(BF8E_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 CSADDR<15:0> 2000

1014 EBICS0
15:0 0000
31:16 CSADDR<15:0> 1000
1018 EBICS1
15:0 0000
31:16 CSADDR<15:0> 2040
101C EBICS2
15:0 0000
31:16 CSADDR<15:0> 1040
1020 EBICS3
15:0 0000
31:16 0000
1054 EBIMSK0
15:0 REGSEL<2:0> MEMTYPE<2:0> MEMSIZE<4:0> 0020
31:16 0000
1058 EBIMSK1
31:16 0000
105C EBIMSK2
31:16 0000
1060 EBIMSK3
31:16 RDYMODE PAGESIZE<1:0> PAGEMODE TPRC<3:0> TBTA<2:0> 041C
1094 EBISMT0
15:0 TWP<5:0> TWR<1:0> TAS<1:0> TRC<5:0> 2D4B
1098 EBISMT1
15:0 TWP<5:0> TWR<1:0> TAS<1:0> TRC<5:0> 2D4B
109C EBISMT2
15:0 TWP<5:0> TWR<1:0> TAS<1:0> TRC<5:0> 2D4B
31:16 0000
10A0 EBIFTRPD
15:0 TRPD<11:0> 00C8

31:16 0000
10A4 EBISMCON
15:0 SMDWIDTH2<2:0> SMDWIDTH1<2:0> SMDWIDTH0<2:0> SMRP 0201
REGISTER 26-1: EBICSx: EXTERNAL BUS INTERFACE CHIP SELECT REGISTER (x = 0-3)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
CSADDR<15:8>
23:16
CSADDR<7:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:
bit 31-16 CSADDR<15:0>: Base Address for Device bits

Address in physical memory, which will select the external device.

REGISTER 26-2: EBIMSKx: EXTERNAL BUS INTERFACE ADDRESS MASK REGISTER (x = 0-3)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
REGSEL<2:0>
7:0
MEMTYPE<2:0> MEMSIZE<4:0>
Legend:

bit 10-8 REGSEL<2:0>: Timing Register Set for Chip Select x bits
111 = Reserved

011 = Reserved
010 = Use EBISMT2
001 = Use EBISMT1
000 = Use EBISMT0
bit 7-5 MEMTYPE<2:0>: Select Memory Type for Chip Select x bits
111 = Reserved

011 = Reserved
010 = NOR-Flash
001 = SRAM
000 = Reserved
bit 4-0 MEMSIZE<4:0>: Select Memory Size for Chip Select x bits
11111 = Reserved

01010 = Reserved
01001 = 16 MB
01000 = 8 MB
00111 = 4 MB
00110 = 2 MB
00101 = 1 MB
00100 = 512 KB
00011 = 256 KB
00010 = 128 KB
00001 = 64 KB (smaller memories alias within this range)
00000 = Chip Select is not used

REGISTER 26-3: EBISMTx: EXTERNAL BUS INTERFACE STATIC MEMORY TIMING REGISTER
(x = 0-2)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
RDYMODE PAGESIZE<1:0>
23:16
PAGEMODE TPRC<3:0>(1) TBTA<2:0>(1)
15:8
TWP<5:0>(1) TWR<1:0>(1)
7:0
TAS<1:0>(1) TRC<5:0>(1)
Legend:

bit 26 RDYMODE: Data Ready Device Select bit
The device associated with register set x is a data-ready device, and will use the EBIRDYx pin.
1 = EBIRDYx input is used
0 = EBIRDYx input is not used
bit 25-24 PAGESIZE<1:0>: Page Size for Page Mode Device bits
11 = 32-word page
10 = 16-word page
01 = 8-word page
00 = 4-word page
bit 23 PAGEMODE: Memory Device Page Mode Support bit
1 = Device supports Page mode
0 = Device does not support Page mode
bit 22-19 TPRC<3:0>: Page Mode Read Cycle Time bits(1)
Read cycle time is TPRC + 1 clock cycle.
bit 18-16 TBTA<2:0>: Data Bus Turnaround Time bits(1)
Clock cycles (0-7) for static memory between read-to-write, write-to-read, and read-to-read when Chip
Select changes.
bit 15-10 TWP<5:0>: Write Pulse Width bits(1)
Write pulse width is TWP + 1 clock cycle.
bit 9-8 TWR<1:0>: Write Address/Data Hold Time bits(1)
Number of clock cycles to hold address or data on the bus.
bit 7-6 TAS<1:0>: Write Address Setup Time bits(1)
Clock cycles for address setup time. A value of 0 is only valid in the case of SSRAM.
bit 5-0 TRC<5:0>: Read Cycle Time bits(1)
Read cycle time is TRC + 1 clock cycle.
Note 1: Refer to Section 47. External Bus Interface (EBI) in the PIC32 Family Reference Manual for the EBI
timing diagrams and additional information.

REGISTER 26-4: EBIFTRPD: EXTERNAL BUS INTERFACE FLASH TIMING REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
TRPD<11:8>
7:0
TRPD<7:0>
Legend:

bit 11-0 TRPD<11:0>: Flash Timing bits
These bits define the number of clock cycles to hold the external Flash memory in reset.

REGISTER 26-5: EBISMCON: EXTERNAL BUS INTERFACE STATIC MEMORY CONTROL

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
SMDWIDTH2<2:0> SMDWIDTH1<2:0> SMDWIDTH0<2:1>
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1
7:0
SMDWIDTH0<0> SMRP
Legend:

bit 15-13 SMDWIDTH2<2:0>: Static Memory Width for Register EBISMT2 bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = 8 bits
011 = Reserved
010 = Reserved
001 = Reserved
000 = 16 bits
bit 0 SMRP: Flash Reset/Power-down mode Select bit
After a Reset, the controller internally performs a power-down for Flash, and then sets this bit to 1.
1 = Flash is taken out of Power-down mode
0 = Flash is forced into Power-down mode

NOTES:

27.0 CRYPTO ENGINE Bulk ciphers that are handled by the Crypto Engine
include:
Note: This data sheet summarizes the AES:
features of the PIC32MZ Graphics (DA)
- 128-bit, 192-bit, and 256-bit key sizes
- CBC, ECB, CTR, CFB, and OFB modes
To complement the information in this DES/TDES:
data sheet, refer to Section 49. Crypto - CBC, ECB, CFB, and OFB modes
Engine (CE) and Random Number Authentication engines that are available through the
Generator (RNG) (DS60001246), Crypto Engine include:
which is available from the SHA-1
SHA-256
MD-5
AES-GCM
The Crypto Engine is intended to accelerate applica- HMAC operation (for all authentication engines)
tions that need cryptographic functions. By execut- The rate of data that can be processed by the Crypto
ing these functions in the hardware module, software Engine depends on a number of factors, including:
overhead is reduced, and actions such as encryp-
tion, decryption, and authentication can execute Which engine is in use
much more quickly. Whether the engines are used in parallel or in series
The Crypto Engine uses an internal descriptor-based The demands on source and destination memories
DMA for efficient programming of the security associ- by other parts of the system (i.e., CPU, DMA, etc.)
ation data and packet pointers (allowing scatter/ The speed of PBCLK5, which drives the Crypto
gather data fetching). An intelligent state machine Engine
schedules the crypto engines based on the protocol Table 27-1 provides typical performance for various
selection and packet boundaries. The hardware engines. Figure 27-1 illustrates the Crypto Engine
engines can perform the encryption and authentica- block diagram.
tion in sequence or in parallel.
Key features of the Crypto Engine are: TABLE 27-1: CRYPTO ENGINE
PERFORMANCE
Bulk ciphers and hash engines
Performance
Integrated DMA to off-load processing: Engine/
Factor
Maximum Mbps
- Buffer descriptor-based Algorithm (PBCLK5 = 100 MHz)
(Mbps/MHz)
- Secure association per buffer descriptor DES 14.4 1440
Some functions can execute in parallel TDES 6.6 660
AES-128 9.0 900
AES-192 7.9 790
AES-256 7.2 720
MD5 15.6 1560
SHA-1 13.2 1320
SHA-256 9.3 930
FIGURE 27-1: CRYPTO ENGINE BLOCK DIAGRAM
INB Packet AES

System FIFO RD
Bus
TDES
Local Bus
DMA Crypto
Controller FSM
SFR SHA-1
System SHA-256
Bus OUTB Packet
FIFO WR
MD5
PBCLK5

DS60001361E-page 400
27.1 Crypto Engine Control Registers

TABLE 27-2: CRYPTO ENGINE REGISTER MAP
All Resets
Bit Range
(BF8E_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 REVISION<7:0> VERSION<7:0> 0000

5000 CEVER
15:0 ID<15:0> 0000
31:16 0000
5004 CECON
15:0 SWAPOEN SWRST SWAPEN BDPCHST BDPPLEN DMAEN 0000
31:16 0000
5008 CEBDADDR BDPADDR<31:0>
15:0 0000
31:16 0000
500C CEBDPADDR BASEADDR<31:0>
15:0 0000
31:16 ERRMODE<2:0> ERROP<2:0> ERRPHASE<1:0> BDSTATE<3:0> START ACTIVE 0000
5010 CESTAT
15:0 BDCTRL<15:0> 0000
31:16 0000
5014 CEINTSRC
15:0 AREIF PKTIF CBDIF PENDIF 0000
31:16 0000
5018 CEINTEN
15:0 AREIE PKTIE CBDIE PENDIE 0000
31:16 0000
501C CEPOLLCON
15:0 BDPPLCON<15:0> 0000
31:16 0000
5020 CEHDLEN
15:0 HDRLEN<7:0> 0000
31:16 0000
5024 CETRLLEN
15:0 TRLRLEN<7:0> 0000
REGISTER 27-1: CEVER: CRYPTO ENGINE REVISION, VERSION, AND ID REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
REVISION<7:0>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
VERSION<7:0>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
ID<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
ID<7:0>
Legend:
bit 31-24 REVISION<7:0>: Crypto Engine Revision bits

bit 23-16 VERSION<7:0>: Crypto Engine Version bits
bit 15-0 ID<15:0>: Crypto Engine Identification bits

REGISTER 27-2: CECON: CRYPTO ENGINE CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R/W-0 R/W-0, HC R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
7:0
SWAPOEN SWRST SWAPEN BDPCHST BDPPLEN DMAEN


bit 7 SWAPOEN: Swap Output Data Enable bit
1 = Output data is byte swapped when written by dedicated DMA
0 = Output data is not byte swapped when written by dedicated DMA
bit 6 SWRST: Software Reset bit
1 = Initiate a software reset of the Crypto Engine
bit 5 SWAPEN: I/O Swap Enable bit
1 = TFDMA inputs and RFDMA outputs are swapped
0 = TFDMA inputs and RFDMA outputs are not swapped
bit 2 BDPCHST: Buffer Descriptor Processor (BDP) Fetch Enable bit
This bit should be enabled only after all DMA descriptor programming is completed.
1 = BDP descriptor fetch is enabled
0 = BDP descriptor fetch is disabled
bit 1 BDPPLEN: Buffer Descriptor Processor Poll Enable bit
This bit should be enabled only after all DMA descriptor programming is completed.
1 = Poll for descriptor until valid bit is set
0 = Do not poll
1 = Crypto Engine DMA is enabled
0 = Crypto Engine DMA is disabled

REGISTER 27-3: CEBDADDR: CRYPTO ENGINE BUFFER DESCRIPTOR REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
BDPADDR<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
BDPADDR<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
BDPADDR<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
BDPADDR<7:0>
Legend:
bit 31-0 BDPADDR<31:0>: Current Buffer Descriptor Process Address Status bits
These bits contain the current descriptor address that is being processed by the Buffer Descriptor Processor
(BDP).
REGISTER 27-4: CEBDPADDR: CRYPTO ENGINE BUFFER DESCRIPTOR PROCESSOR

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/w-0 R/w-0 R/w-0 R/w-0 R/w-0 R/w-0 R/w-0 R/w-0
31:24
BASEADDR<31:24>
23:16
BASEADDR<23:16>
15:8
BASEADDR<15:8>
7:0
BASEADDR<7:0>
Legend:
bit 31-0 BASEADDR<31:0>: DMA Base Address Status bits

These bits contain the base address of the DMA controller. After a reset, a fetch starts from this address.

REGISTER 27-5: CESTAT: CRYPTO ENGINE STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
ERRMODE<2:0> ERROP<2:0> ERRPHASE<1:0>
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
BDSTATE START ACTIVE
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
BDCTRL<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
BDCTRL<7:0>
Legend:
bit 31-29 ERRMOD<2:0>: Internal Error Mode Status bits

111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = CEK operation
010 = KEK operation
001 = Preboot authentication
bit 28-26 ERROP<2:0>: Internal Error Operation Status bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Authentication
011 = Reserved
010 = Decryption
001 = Encryption
000 = Reserved
bit 25-24 ERRPHASE<1:0>: Internal Error Phase of DMA Status bits
11 = Destination data
10 = Source data
01 = Security Association (SA) access
00 = Buffer Descriptor (BD) access
bit 21-18 BDSTATE<3:0>: Buffer Descriptor Processor State Status bits
These bits contain a number, which indicates the current state of the BDP:
1111 = Reserved

0111 = Reserved
0110 = SA fetch
0101 = Fetch BDP is disabled
0100 = Descriptor is done
0011 = Data phase
0010 = BDP is loading
0001 = Descriptor fetch request is pending
0000 = BDP is idle
bit 17 START: DMA Start Status bit
1 = DMA start has occurred
0 = DMA start has not occurred

REGISTER 27-5: CESTAT: CRYPTO ENGINE STATUS REGISTER (CONTINUED)
bit 16 ACTIVE: Buffer Descriptor Processor Status bit
1 = BDP is active
0 = BDP is idle
bit 15-0 BDCTRL<15:0>: Descriptor Control Word Status bits
These bits contain the current descriptor control word.

REGISTER 27-6: CEINTSRC: CRYPTO ENGINE INTERRUPT SOURCE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
7:0
AREIF PKTIF CBDIF PENDIF
Legend:

bit 3 AREIF: Access Response Error Interrupt bit
1 = Error occurred trying to access memory outside the Crypto Engine
0 = No error has occurred
bit 2 PKTIF: DMA Packet Completion Interrupt Status bit
1 = DMA packet was completed
0 = DMA packet was not completed
bit 1 CBDIF: BD Transmit Status bit
1 = Last BD transmit was processed
0 = Last BD transmit has not been processed
bit 0 PENDIF: Crypto Engine Interrupt Pending Status bit
1 = Crypto Engine interrupt is pending (this value is the result of an OR of all interrupts in the Crypto Engine)
0 = Crypto Engine interrupt is not pending

REGISTER 27-7: CEINTEN: CRYPTO ENGINE INTERRUPT ENABLE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
AREIE PKTIE BDPIE PENDIE(1)
Legend:

bit 3 AREIE: Access Response Error Interrupt Enable bit
1 = Access response error interrupts are enabled
0 = Access response error interrupts are not enabled
bit 2 PKTIE: DMA Packet Completion Interrupt Enable bit
1 = DMA packet completion interrupts are enabled
0 = DMA packet completion interrupts are not enabled
bit 1 BDPIE: DMA Buffer Descriptor Processor Interrupt Enable bit
1 = BDP interrupts are enabled
0 = BDP interrupts are not enabled
bit 0 PENDIE: Master Interrupt Enable bit(1)
1 = Crypto Engine interrupts are enabled
0 = Crypto Engine interrupts are not enabled
Note 1: The PENDIE bit is a Global enable bit and must be enabled together with the other interrupts desired.

REGISTER 27-8: CEPOLLCON: CRYPTO ENGINE POLL CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
BDPPLCON<15:8>
7:0
BDPPLCON<7:0>
Legend:

bit 15 BDPPLCON<15:0>: Buffer Descriptor Processor Poll Control bits
These bits determine the number of cycles that the DMA transmit BDP would wait before refetching the
descriptor control word if the previous descriptor fetched was disabled.

REGISTER 27-9: CEHDLEN: CRYPTO ENGINE HEADER LENGTH REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
HDRLEN<7:0>
Legend:

bit 7-0 HDRLEN<7:0>: DMA Header Length bits
For every packet, skip this length of locations and start filling the data.
REGISTER 27-10: CETRLLEN: CRYPTO ENGINE TRAILER LENGTH REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
TRLRLEN<7:0>
Legend:

bit 7-0 TRLRLEN<7:0>: DMA Trailer Length bits
For every packet, skip this length of locations at the end of the current packet and start putting the next
packet.

27.2 Crypto Engine Buffer Descriptors
Host software creates a linked list of buffer descriptors
and the hardware updates them. Table 27-3 provides a
list of the Crypto Engine buffer descriptors, followed by
format descriptions of each buffer descriptor (see
Figure 27-2 through Figure 27-10).
TABLE 27-3: CRYPTO ENGINE BUFFER DESCRIPTORS

Name (see Note 1)
31/2315/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BD_CTRL 31:24 DESC_EN CRY_MODE<2:0>
23:16 SA_FETCH_EN LAST_BD LIFM PKT_INT_EN CBD_INT_EN
15:8 BD_BUFLEN<15:8>
7:0 BD_BUFLEN<7:0>
BD_SA_ADDR 31:24 BD_SAADDR<31:24>
23:16 BD_SAADDR<23:16>
15:8 BD_SAADDR<15:8>
7:0 BD_SAADR<7:0>
BD_SCRADDR 31:24 BD_SRCADDR<31:24>
23:16 BD_SRCADDR<23:16>
15:8 BD_SRCADDR<15:8>
7:0 BD_SRCADDR<7:0>
BD_DSTADDR 31:24 BD_DSTADDR<31:24>
23:16 BD_DSTADDR<23:16>
15:8 BD_DSTADDR<15:8>
7:0 BD_DSTADDR<7:0>
BD_NXTPTR 31:24 BD_NXTADDR<31:24>
23:16 BD_NXTADDR<23:16>
15:8 BD_NXTADDR<15:8>
7:0 BD_NXTADDR<7:0>
BD_UPDPTR 31:24 BD_UPDADDR<31:24>
23:16 BD_UPDADDR<23:16>
15:8 BD_UPDADDR<15:8>
7:0 BD_UPDADDR<7:0>
BD_MSG_LEN 31:24 MSG_LENGTH<31:24>
23:16 MSG_LENGTH<23:16>
15:8 MSG_LENGTH<15:8>
7:0 MSG_LENGTH<7:0>
BD_ENC_OFF 31:24 ENCR_OFFSET<31:24>
23:16 ENCR_OFFSET<23:16>
Note 1: The buffer descriptor must be allocated in memory on a 64-bit boundary.

FIGURE 27-2: FORMAT OF BD_CTRL
Bit Bit
Bit Bit Bit Bit Bit Bit Bit
29/21/ 26/18/
Range 31/23/15/7 30/22/14/6 28/20/12/4 27/19/11/3 25/17/9/1 24/16/8/0
13/5 10/2
31-24 DESC_EN CRY_MODE<2:0>
23-16 SA_FETCH_EN LAST_BD LIFM PKT_INT_EN CBD_INT_EN
15-8 BD_BUFLEN<15:8>
7-0 BD_BUFLEN<7:0>
bit 31 DESC_EN: Descriptor Enable

1 = The descriptor is owned by hardware. After processing the BD, hardware resets this bit to 0.
0 = The descriptor is owned by software
bit 30 Unimplemented: Must be written as 0
bit 29-27 CRY_MODE<2:0>: Crypto Mode
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = CEK operation
010 = KEK operation
001 = Preboot authentication
bit 22 SA_FETCH_EN: Fetch Security Association From External Memory
1 = Fetch SA from the SA pointer. This bit needs to be set to 1 for every new packet.
0 = Use current fetched SA or the internal SA
bit 21-20 Unimplemented: Must be written as 0
bit 19 LAST_BD: Last Buffer Descriptors
1 = Last Buffer Descriptor in the chain
0 = More Buffer Descriptors in the chain
After the last BD, the CEBDADDR goes to the base address in CEBDPADDR.
bit 18 LIFM: Last In Frame
In case of Receive Packets (from H/W-> Host), this field is filled by the Hardware to indicate whether the
packet goes across multiple buffer descriptors. In case of transmit packets (from Host -> H/W), this field indi-
cates whether this BD is the last in the frame.
bit 17 PKT_INT_EN: Packet Interrupt Enable
Generate an interrupt after processing the current buffer descriptor, if it is the end of the packet.
bit 16 CBD_INT_EN: CBD Interrupt Enable
Generate an interrupt after processing the current buffer descriptor.
bit 15-0 BD_BUFLEN<15:0>: Buffer Descriptor Length
This field contains the length of the buffer and is updated with the actual length filled by the receiver.

FIGURE 27-3: FORMAT OF BD_SADDR

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31-24 BD_SAADDR<31:24>
23-16 BD_SAADDR<23:16>
15-8 BD_SAADDR<15:8>
7-0 BD_SAADDR<7:0>
bit 31-0 BD_SAADDR<31:0>: Security Association IP Session Address

The sessions SA pointer has the keys and IV values.
FIGURE 27-4: FORMAT OF BD_SADDR

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31-24 BD_SAADDR<31:24>
23-16 BD_SAADDR<23:16>
15-8 BD_SAADDR<15:8>
7-0 BD_SAADDR<7:0>
bit 31-0 BD_SAADDR<31:0>: Security Association IP Session Address

The sessions SA pointer has the keys and IV values.
FIGURE 27-5: FORMAT OF BD_SRCADDR

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31-24 BD_SCRADDR<31:24>
23-16 BD_SCRADDR<23:16>
15-8 BD_SCRADDR<15:8>
7-0 BD_SCRADDR<7:0>
bit 31-0 BD_SCRADDR: Buffer Source Address

The source address of the buffer that needs to be passed through the PE-CRDMA for encryption or
authentication. This address must be on a 32-bit boundary.

FIGURE 27-6: FORMAT OF BD_DSTADDR

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31-24 BD_DSTADDR<31:24>
23-16 BD_DSTADDR<23:16>
15-8 BD_DSTADDR<15:8>
7-0 BD_DSTADDR<7:0>
bit 31-0 BD_DSTADDR: Buffer Destination Address

The destination address of the buffer that needs to be passed through the PE-CRDMA for encryption
or authentication. This address must be on a 32-bit boundary.
FIGURE 27-7: FORMAT OF BD_NXTADDR

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31-24 BD_NXTADDR<31:24>
23-16 BD_NXTADDR<23:16>
15-8 BD_NXTADDR<15:8>
7-0 BD_NXTADDR<7:0>
bit 31-0 BD_NXTADDR: Next BD Pointer Address Has Next Buffer Descriptor
The next buffer can be a next segment of the previous buffer or a new packet.
FIGURE 27-8: FORMAT OF BD_UPDPTR

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31-24 BD_UPDADDR<31:24>
23-16 BD_UPDADDR<23:16>
15-8 BD_UPDADDR<15:8>
7-0 BD_UPDADDR<7:0>
bit 31-0 BD_UPDADDR: UPD Address Location

The update address has the location where the CRDMA results are posted. The updated results are
the ICV values, key output values as needed.

FIGURE 27-9: FORMAT OF BD_MSG_LEN

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31-24 MSG_LENGTH<31:24>
23-16 MSG_LENGTH<23:16>
15-8 MSG_LENGTH<15:8>
7-0 MSG_LENGTH<7:0>
bit 31-0 MSG_LENGTH: Total Message Length

Total message length for the hash and HMAC algorithms in bytes. Total number of crypto bytes in
case of GCM algorithm (LEN-C).
FIGURE 27-10: FORMAT OF BD_ENC_OFF

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31-24 ENCR_OFFSET<31:24>
bit 31-0 ENCR_OFFSET: Encryption Offset

Encryption offset for the multi-task test cases (both encryption and authentication). The number of
AAD bytes in the case of GCM algorithm (LEN-A).

27.3 Security Association Structure
Table 27-11 shows the Security Association Structure.
The Crypto Engine uses the Security Association to
determine the settings for processing a Buffer Descrip-
tor Processor. The Security Association contains:
Which algorithm to use
Whether to use engines in parallel (for both
authentication and encryption/decryption)
The size of the key
Authentication key
Encryption/decryption key
Authentication Initialization Vector (IV)
Encryption IV
FIGURE 27-11: CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE

Name
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
SA_CTRL 31:24 VERIFY NO_RX OR_EN ICVONLY IRFLAG
23:16 LNC LOADIV FB FLAGS ALGO<6>
15:8 ALGO<5:0> ENCTYPE KEYSIZE<1>
7:0 KEYSIZE<0> MULTITASK<2:0> CRYPTOALGO<3:0>
SA_AUTHKEY1 31:24 AUTHKEY<31:24>
23:16 AUTHKEY<23:16>
15:8 AUTHKEY<15:8>
7:0 AUTHKEY<7:0>
23:16 AUTHKEY<23:16>
15:8 AUTHKEY<15:8>
7:0 AUTHKEY<7:0>
23:16 AUTHKEY<23:16>
15:8 AUTHKEY<15:8>
7:0 AUTHKEY<7:0>
23:16 AUTHKEY<23:16>
15:8 AUTHKEY<15:8>
7:0 AUTHKEY<7:0>
23:16 AUTHKEY<23:16>
15:8 AUTHKEY<15:8>
7:0 AUTHKEY<7:0>
23:16 AUTHKEY<23:16>
15:8 AUTHKEY<15:8>
7:0 AUTHKEY<7:0>
23:16 AUTHKEY<23:16>
15:8 AUTHKEY<15:8>
7:0 AUTHKEY<7:0>
23:16 AUTHKEY<23:16>
15:8 AUTHKEY<15:8>
7:0 AUTHKEY<7:0>
SA_ENCKEY1 31:24 ENCKEY<31:24>
23:16 ENCKEY<23:16>
15:8 ENCKEY<15:8>
7:0 ENCKEY<7:0>

FIGURE 27-11: CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED)
Name
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
23:16 ENCKEY<23:16>
15:8 ENCKEY<15:8>
7:0 ENCKEY<7:0>
23:16 ENCKEY<23:16>
15:8 ENCKEY<15:8>
7:0 ENCKEY<7:0>
23:16 ENCKEY<23:16>
15:8 ENCKEY<15:8>
7:0 ENCKEY<7:0>
23:16 ENCKEY<23:16>
15:8 ENCKEY<15:8>
7:0 ENCKEY<7:0>
23:16 ENCKEY<23:16>
15:8 ENCKEY<15:8>
7:0 ENCKEY<7:0>
23:16 ENCKEY<23:16>
15:8 ENCKEY<15:8>
7:0 ENCKEY<7:0>
23:16 ENCKEY<23:16>
15:8 ENCKEY<15:8>
7:0 ENCKEY<7:0>
SA_AUTHIV1 31:24 AUTHIV<31:24>
23:16 AUTHIV<23:16>
15:8 AUTHIV<15:8>
7:0 AUTHIV<7:0>
23:16 AUTHIV<23:16>
15:8 AUTHIV<15:8>
7:0 AUTHIV<7:0>
23:16 AUTHIV<23:16>
15:8 AUTHIV<15:8>
7:0 AUTHIV<7:0>
23:16 AUTHIV<23:16>
15:8 AUTHIV<15:8>
7:0 AUTHIV<7:0>
23:16 AUTHIV<23:16>
15:8 AUTHIV<15:8>
7:0 AUTHIV<7:0>
23:16 AUTHIV<23:16>
15:8 AUTHIV<15:8>
7:0 AUTHIV<7:0>
23:16 AUTHIV<23:16>
15:8 AUTHIV<15:8>
7:0 AUTHIV<7:0>
23:16 AUTHIV<23:16>
15:8 AUTHIV<15:8>
7:0 AUTHIV<7:0>

FIGURE 27-11: CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED)
Name
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
SA_ENCIV1 31:24 ENCIV<31:24>
23:16 ENCIV<23:16>
15:8 ENCIV<15:8>
7:0 ENCIV<7:0>
23:16 ENCIV<23:16>
15:8 ENCIV<15:8>
7:0 ENCIV<7:0>
23:16 ENCIV<23:16>
15:8 ENCIV<15:8>
7:0 ENCIV<7:0>
23:16 ENCIV<23:16>
15:8 ENCIV<15:8>
7:0 ENCIV<7:0>

Table 27-12 shows the Security Association control The Crypto Engine fetches different structures for dif-
word structure. ferent flows and ensures that hardware fetches mini-
mum words from SA required for processing. The
structure is ready for hardware optimal data fetches.
FIGURE 27-12: FORMAT OF SA_CTRL

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31-24 VERIFY NO_RX OR_EN ICVONLY IRFLAG
23-16 LNC LOADIV FB FLAGS ALGO<6>
KEY
15-8 ALGO<5:0> ENC
SIZE<1>
KEY
7-0 MULTITASK<2:0> CRYPTOALGO<3:0>
SIZE<0>
bit 31-30 Reserved: Do not use

bit 29 VERIFY: NIST Procedure Verification Setting
1 = NIST procedures are to be used
0 = Do not use NIST procedures
bit 28 Reserved: Do not use
bit 27 NO_RX: Receive DMA Control Setting
1 = Only calculate ICV for authentication calculations
0 = Normal processing
bit 26 OR_EN: OR Register Bits Enable Setting
1 = OR the register bits with the internal value of the CSR register
0 = Normal processing
bit 25 ICVONLY: Incomplete Check Value Only Flag
This affects the SHA-1 algorithm only. It has no effect on the AES algorithm.
1 = Only three words of the HMAC result are available
0 = All results from the HMAC result are available
bit 24 IRFLAG: Immediate Result of Hash Setting
This bit is set when the immediate result for hashing is requested.
1 = Save the immediate result for hashing
0 = Do not save the immediate result
bit 23 LNC: Load New Keys Setting
1 = Load a new set of keys for encryption and authentication
0 = Do not load new keys
bit 22 LOADIV: Load IV Setting
1 = Load the IV from this Security Association
0 = Use the next IV
bit 21 FB: First Block Setting
This bit indicates that this is the first block of data to feed the IV value.
1 = Indicates this is the first block of data
0 = Indicates this is not the first block of data
bit 20 FLAGS: Incoming/Outgoing Flow Setting
1 = Security Association is associated with an outgoing flow
0 = Security Association is associated with an incoming flow
bit 19-17 Reserved: Do not use

Figure 27-12: Format of SA_CTRL (Continued)
bit 16-10 ALGO<6:0>: Type of Algorithm to Use

1xxxxxx = HMAC 1
x1xxxxx = SHA-256
xx1xxxx = SHA1
xxx1xxx = MD5
xxxx1xx = AES
xxxxx1x = TDES
xxxxxx1 = DES
bit 9 ENC: Type of Encryption Setting
1 = Encryption
0 = Decryption
bit 8-7 KEYSIZE<1:0>: Size of Keys in SA_AUTHKEYx or SA_ENCKEYx
11 = Reserved; do not use
10 = 256 bits
01 = 192 bits
00 = 128 bits(1)
bit 6-4 MULTITASK<2:0>: How to Combine Parallel Operations in the Crypto Engine
111 = Parallel pass (decrypt and authenticate incoming data in parallel)
101 = Pipe pass (encrypt the incoming data, and then perform authentication on the encrypted data)
011 = Reserved
010 = Reserved
001 = Reserved
000 = Encryption or authentication or decryption (no pass)
bit 3-0 CRYPTOALGO<3:0>: Mode of operation for the Crypto Algorithm
1111 = Reserved
1110 = AES_GCM (for AES processing)
1101 = RCTR (for AES processing)
1100 = RCBC_MAC (for AES processing)
1011 = ROFB (for AES processing)
1010 = RCFB (for AES processing)
1001 = RCBC (for AES processing)
1000 = REBC (for AES processing)
0111 = TOFB (for Triple-DES processing)
0110 = TCFB (for Triple-DES processing)
0101 = TCBC (for Triple-DES processing)
0100 = TECB (for Triple-DES processing)
0011 = OFB (for DES processing)
0010 = CFB (for DES processing)
0001 = CBC (for DES processing)
0000 = ECB (for DES processing)
Note 1: This setting does not alter the size of SA_AUTHKEYx or SA_ENCKEYx in the Security Association,
only the number of bits of SA_AUTHKEYx and SA_ENCKEYx that are used.

NOTES:

28.0 RANDOM NUMBER FIGURE 28-1: RANDOM NUMBER
GENERATOR (RNG) GENERATOR BLOCK
DIAGRAM
comprehensive reference source. To System Bus
sheet, refer to Section 49. Crypto
Engine (CE) and Random Number
Generator (RNG) (DS60001246), which
is available from the Documentation > SFR PRNG
Reference Manual section of the
PBCLK5
The Random Number Generator (RNG) core imple-
ments a thermal noise-based, True Random Number TRNG
Generator (TRNG) and a cryptographically secure
Pseudo-Random Number Generator (PRNG).
BIAS Corrector
The TRNG uses multiple ring oscillators and the inher-
ent thermal noise of integrated circuits to generate true
random numbers that can initialize the PRNG.
The PRNG is a flexible LSFR, which is capable of
manifesting a maximal length LFSR of up to 64-bits. Edge Comparator
The following are some of the key features of the
Random Number Generator:
TRNG:
- Up to 25 Mbps of random bits
Ring Ring
- Multi-Ring Oscillator based design Oscillator Oscillator
- Built-in Bias Corrector
PRNG:
- LSFR-based
- Up to 64-bit polynomial length
- Programmable polynomial
- TRNG can be seed value

DS60001361E-page 422
28.1 RNG Control Registers

TABLE 28-1: RANDOM NUMBER GENERATOR (RNG) REGISTER MAP
Bits
Virtual Address
All Resets
Bit Range
(BF8E_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 ID<15:0> xxxx

6000 RNGVER
15:0 VERSION<7:0> REVISION<7:0> xxxx
31:16 0000
6004 RNGCON
15:0 LOAD TRNGMODE CONT PRNGEN TRNGEN PLEN<7:0> 0064
31:16 FFFF
6008 RNGPOLY1 POLY<31:0>
15:0 0000
31:16 FFFF
600C RNGPOLY2 POLY<31:0>
15:0 0000
31:16 FFFF
6010 RNGNUMGEN1 RNG<31:0>
15:0 FFFF
31:16 FFFF
6014 RNGNUMGEN2 RNG<31:0>
15:0 FFFF
31:16 0000
6018 RNGSEED1 SEED<31:0>
15:0 0000
31:16 0000
601C RNGSEED2 SEED<31:0>
15:0 0000
31:16 0000
6020 RNGCNT
15:0 RCNT<6:0> 0000
REGISTER 28-1: RNGVER: RANDOM NUMBER GENERATOR VERSION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
ID<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
ID<7:0>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
VERSION<7:0>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
REVISION<7:0>
Legend:
bit 31-6 ID<15:0>: Block Identification bits

bit 15-8 VERSION<7:0>: Block Version bits
bit 7-0 REVISION<7:0>: Block Revision bits

REGISTER 28-2: RNGCON: RANDOM NUMBER GENERATOR CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
LOAD TRNGMODE(1) CONT PRNGEN TRNGEN
7:0
PLEN<7:0>
Legend:

bit 12 LOAD: Device Select bit
This bit is self-clearing and is used to load the seed from the TRNG (i.e., the random value) as a seed to
the PRNG.
bit 11 TRNGMODE: True Random Number Generator Mode bit(1)
1 = Enhanced TRNG mode is selected
0 = Normal TRNG mode is selected
bit 10 CONT: PRNG Number Shift Enable bit
1 = The PRNG random number is shifted every cycle
0 = The PRNG random number is shifted when the previous value is removed
bit 9 PRNGEN: PRNG Operation Enable bit
1 = PRNG operation is enabled
0 = PRNG operation is not enabled
bit 8 TRNGEN: TRNG Operation Enable bit
1 = TRNG operation is enabled
0 = TRNG operation is not enabled
bit 7-0 PLEN<7:0>: PRNG Polynomial Length bits
These bits contain the length of the polynomial used for the PRNG.
Note 1: This bit is effective only when the TRNGEN bit is set to 1.

REGISTER 28-3: RNGPOLYx: RANDOM NUMBER GENERATOR POLYNOMIAL REGISTER x

(x = 1 OR 2)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
POLY<31:24>
23:16
POLY<23:16>
15:8
POLY<15:8>
7:0
POLY<7:0>
Legend:
bit 31-0 POLY<31:0>: PRNG LFSR Polynomial MSb/LSb bits (RNGPOLY1 = LSb, RNGPOLY2 = MSb)
REGISTER 28-4: RNGNUMGENx: RANDOM NUMBER GENERATOR REGISTER x (x = 1 OR 2)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
RNG<31:24>
23:16
RNG<23:16>
15:8
RNG<15:8>
7:0
RNG<7:0>
Legend:
bit 31-0 RNG<31:0>: Current PRNG MSb/LSb Value bits (RNGNUMGEN1 = LSb, RNGNUMGEN2 = MSb)

REGISTER 28-5: RNGSEEDx: TRUE RANDOM NUMBER GENERATOR SEED REGISTER x

(x = 1 OR 2)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
SEED<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
SEED<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
SEED<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
SEED<7:0>
Legend:
bit 31-0 SEED<31:0>: TRNG MSb/LSb Value bits (RNGSEED1 = LSb, RNGSEED2 = MSb)
REGISTER 28-6: RNGCNT: TRUE RANDOM NUMBER GENERATOR COUNT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
RCNT<6:0>
Legend:

bit 6-0 RCNT<6:0>: Number of Valid TRNG MSB 32 bits

29.0 12-BIT HIGH-SPEED A simplified block diagram of the ADC module is
illustrated in Figure 29-1.
SUCCESSIVE APPROXIMATION
REGISTER (SAR) ANALOG-TO- The 12-bit HS SAR ADC has up to five dedicated
ADC modules (ADC0-ADC4) and one shared ADC
DIGITAL CONVERTER (ADC) module (ADC7). The dedicated ADC modules use a
Note: This data sheet summarizes the features single input (or its alternate) and are intended for
of the PIC32MZ DA family of devices. It is high-speed and precise sampling of time-sensitive or
not intended to be a comprehensive transient inputs. The the shared ADC module
reference source. To complement the incorporates a multiplexer on the input to facilitate a
information in this data sheet, refer to larger group of inputs, with slower sampling, and
Section 22. 12-bit High-Speed provides flexible automated scanning option through
Successive Approximation Register the input scan logic.
(SAR) Analog-to-Digital Converter For each ADC module, the analog inputs are
(ADC) (DS60001344) in the PIC32 connected to the S&H capacitor. The clock, sampling
Family Reference Manual, which is time, and output data resolution for each ADC
available from the Microchip web site module can be set independently. The ADC module
(www.microchip.com/PIC32). performs the conversion of the input analog signal
based on the configurations set in the registers.
The 12-bit High-Speed Successive Approximation When conversion is complete, the final result is
Register (SAR) Analog-to-Digital Converter (ADC) stored in the result buffer for the specific analog
includes the following features: input and is passed to the digital filter and digital
12-bit resolution comparator if configured to use data from this
Six ADC modules with dedicated Sample and particular sample. Input to ADCx mapping is
Hold (S&H) circuits illustrated in Figure 29-2.
Two dedicated ADC modules can be combined in
Turbo mode to provide double conversion rate EQUATION 29-1: ADC THROUGHPUT RATE
(clock sources for combined ADCs must be
synchronous) T AD
Up to 45 analog input sources, in addition to the FTP = --------------------------------------------
T SAMP + T CONV
internal CTMU, VBAT, internal voltage reference
and internal temperature sensor Where,
Single-ended and/or differential inputs TAD = the frequency of the individual ADC module
Can operate during Sleep mode
Supports touch sense applications
Six digital comparators Note 1: Prior to enabling the ADC module, the
Six digital filters supporting two modes: user application must copy the ADC
- Oversampling mode calibration data (DEVADC0-DEVADC4,
- Averaging mode DEVADC7; see Register 41-8) from the
16-word FIFO on ADC0 through ADC4 for Configuration memory into the ADC
increased throughput Configuration registers (ADC0CFG-
ADC4CFG, ADC7CFG).
Early interrupt generation resulting in faster
processing of converted data 2: If VDDIO is greater than 2.5V, set the
Designed for motor control, power conversion, AICPMPEN bit (ADCCON1<12>) and
and general purpose applications the IOANCPEN bit (CFGCON<7>) to 0.
If VDDIO is less than 2.5V, set both bits
Operation during Sleep and Idle modes
to 1.

FIGURE 29-1: ADC BLOCK DIAGRAM
AN0 00
AN45 01 AVDD AVSS VREF+ VREF-
00 01 10 11
ADCSEL<1:0>
N/C 10
N/C 11 TCLK
SH0ALT<1:0> CONCLKDIV<5:0>
(ADCTRGMODE<17:16>) VREFSEL<2:0>
AN5 1
VREFH VREFL TAD0-TAD4
VREFL 0 ADCDIV<6:0> TQ
(ADCxTIME<22:16>)
DIFF0<1>
(ADCIMCON1<1>) ADC0
TAD7 ADCDIV<6:0>
(ADCCON2<6:0>)
AN4 00
AN49 01
N/C 10
N/C 11
SH4ALT<1:0>
(ADCTRGMODE<25:24>)
AN9 1 ADC4
VREFL 0
DIFF4<1>
(ADCIMCON1<1>)
AN5
CTMUT (AN40)
VBAT (AN41)
AN38
IVREF (AN42)
AN39
IVTEMP (AN43)
ADC7
AN10 1
VREFL 0
DIFFx<1>
x = 5 to 43
(ADCIMCONy<z>)
y = 1 to 3,
z = 1 to 31 (Odd numbers) ADCDATA0
...
FIFO
ADCDATA43
Digital Filter Data

System Bus
Interrupt/Event
Digital Comparator
Triggers,
Turbo Channel,
Scan Control Logic
Capacitive Voltage Interrupt/Event
Divider (CVD)
Trigger
Interrupt
Status and Control
Registers

FIGURE 29-2: S&H BLOCK DIAGRAM
ADC0 ADC3
AN0 00 AN3 00
AN45 01 AN48 01
N/C 10 N/C 10
N/C 11 N/C 11
SAR SAR
SH0ALT<1:0> SH3ALT<1:0>
(ADCTRGMODE<17:16) (ADCTRGMODE<23:22)
AN5 1 AN8 1
VREFL 0 VREFL 0
DIFF0<1> (ADCIMCON1<1>) DIFF3<1> (ADCIMCON1<7>)
ADC1 ADC4
AN1 00 AN4 00
AN46 01 AN49 01
N/C 10 N/C 10
N/C 11 N/C 11
SAR SAR
SH1ALT<1:0> SH4ALT<1:0>
(ADCTRGMODE<19:18) (ADCTRGMODE<25:24)
AN6 1 AN9 1
VREFL 0 VREFL 0
DIFF1<1> (ADCIMCON1<3>) DIFF4<1> (ADCIMCON1<9>)
ADC2
AN2 00
AN47 01
N/C 10
N/C 11
SAR
SH2ALT<1:0>
(ADCTRGMODE<21:20)
AN7 1
VREFL 0
DIFF2<1> (ADCIMCON1<5>)
ADC7
AN5
CTMUT (AN40) AN6
VBAT (AN41)
IVREF (AN42)
IVTEMP (AN43)
AN38
CVDCPL<2:0>
(ADCCON2<28:26>) AN39
CVDEN
(ADCCON1<11>)
SAR
CVD
AN10 1 Capacitor
VREFL 0
DIFFx<1>

FIGURE 29-3: FIFO BLOCK DIAGRAM
ADCID<2:0>
ADCx ID
(ADCFSTAT<2:0>)
FEN
(ADCFSTAT<31>)
ADC4EN ADCFIFO DATA<31:0>

(ADCFSTAT<28>)
ADC4 ADCx ID Converted Data
FRDY
If data (ADCFSTAT<22>)
FIFO (16 Words) available in
FIFO FIEN
(ADCFSTAT<23>)
Interrupt
ADC0EN
(ADCFSTAT<24>)
FCNT<7:0>
(ADCFSTAT<15:8>)
ADC0 Number of data in FIFO

29.1 ADC Control Registers
TABLE 29-1: ADC REGISTER MAP

Bits
All Resets
Bit Range
Address
Virtual
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
B000 ADCCON1 31:16 TRBEN TRBERR TRBMST<2:0> TRBSLV<2:0> FRACT SELRES<1:0> STRGSRC<4:0> 0060
15:0 ON SIDL AICPMPEN CVDEN FSSCLKEN FSPBCLKEN IRQVS<2:0> STRGLVL 0000
B004 ADCCON2 31:16 BGVRRDY REFFLT EOSRDY CVDCPL<2:0> SAMC<9:0> 0000
15:0 BGVRIEN REFFLTIEN EOSIEN ADCEIOVR ADCEIS<2:0> ADCDIV<6:0> 0000
B008 ADCCON3 31:16 ADCSEL<1:0> CONCLKDIV<5:0> DIGEN7 DIGEN4 DIGEN3 DIGEN2 DIGEN1 DIGEN0 0000
15:0 VREFSEL<2:0> TRGSUSP UPDIEN UPDRDY SAMP RQCNVRT GLSWTRG GSWTRG ADINSEL<5:0> 0000
B00C ADCTRGMODE 31:16 SH4ALT<1:0> SH3ALT<1:0> SH2ALT<1:0> SH1ALT<1:0> SH0ALT<1:0> 0000
15:0 STRGEN4 STRGEN3 STRGEN2 STRGEN1 STRGEN0 SSAMPEN4 SSAMPEN3 SSAMPEN2 SSAMPEN1 SSAMPEN0 0000
B010 ADCIMCON1 31:16 DIFF15 SIGN15 DIFF14 SIGN14 DIFF13 SIGN13 DIFF12 SIGN12 DIFF11 SIGN11 DIFF10 SIGN10 DIFF9 SIGN9 DIFF8 SIGN8 0000
15:0 DIFF7 SIGN7 DIFF6 SIGN6 DIFF5 SIGN5 DIFF4 SIGN4 DIFF3 SIGN3 DIFF2 SIGN2 DIFF1 SIGN1 DIFF0 SIGN0 0000

B014 ADCIMCON2 31:16 DIFF31 SIGN31 DIFF30 SIGN30 DIFF29 SIGN29 DIFF28 SIGN28 DIFF27 SIGN27 DIFF26 SIGN26 DIFF25 SIGN25 DIFF24 SIGN24 0000
B018 ADCIMCON3 31:16 DIFF43 SIGN43 DIFF42 SIGN42 DIFF41 SIGN41 DIFF40 SIGN40 0000
B020 ADCGIRQEN1 31:16 AGIEN31 AGIEN30 AGIEN29 AGIEN28 AGIEN27 AGIEN26 AGIEN25 AGIEN24 AGIEN23 AGIEN22 AGIEN21 AGIEN20 AGIEN19 AGIEN18 AGIEN17 AGIEN16 0000
15:0 AGIEN15 AGIEN14 AGIEN13 AGIEN12 AGIEN11 AGIEN10 AGIEN9 AGIEN8 AGIEN7 AGIEN6 AGIEN5 AGIEN4 AGIEN3 AGIEN2 AGIEN1 AGIEN0 0000
B024 ADCGIRQEN2 31:16 0000
15:0 AGIEN43 AGIEN42 AGIEN41 AGIEN40 AGIEN39 AGIEN38 AGIEN37 AGIEN36 AGIEN35 AGIEN34 AGIEN33 AGIEN32 0000
B028 ADCCSS1 31:16 CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 0000
15:0 CSS15 CSS14 CSS13 CSS12 CSS11 CSS10 CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000
B02C ADCCSS2 31:16 0000
15:0 CSS43 CSS42 CSS41 CSS40 CSS39 CSS38 CSS37 CSS36 CSS35 CSS34 CSS33 CSS32 0000
B030 ADCDSTAT1 31:16 ARDY31 ARDY30 ARDY29 ARDY28 ARDY27 ARDY26 ARDY25 ARDY24 ARDY23 ARDY22 ARDY21 ARDY20 ARDY19 ARDY18 ARDY17 ARDY16 0000
15:0 ARDY15 ARDY14 ARDY13 ARDY12 ARDY11 ARDY10 ARDY9 ARDY8 ARDY7 ARDY6 ARDY5 ARDY4 ARDY3 ARDY2 ARDY1 ARDY0 0000
B034 ADCDSTAT2 31:16 0000
15:0 ARDY43 ARDY42 ARDY41 ARDY40 ARDY39 ARDY38 ARDY37 ARDY36 ARDY35 ARDY34 ARDY33 ARDY32 0000
B038 ADCCMPEN1 31:16 CMPE31 CMPE30 CMPE29 CMPE28 CMPE27 CMPE26 CMPE25 CMPE24 CMPE23 CMPE22 CMPE21 CMPE20 CMPE19 CMPE18 CMPE17 CMPE16 0000
15:0 CMPE15 CMPE14 CMPE13 CMPE12 CMPE11 CMPE10 CMPE9 CMPE8 CMPE7 CMPE6 CMPE5 CMPE4 CMPE3 CMPE2 CMPE1 CMPE0 0000
B03C ADCCMP1 31:16 DCMPHI<15:0> 0000
15:0 DCMPLO<15:0> 0000
DS60001361E-page 431
B044 ADCCMP2 31:16 DCMPHI<15:0> 0000
15:0 DCMPLO<15:0> 0000
Note 1: Before enabling the ADC, the user application must initialize the ADC calibration values by copying them from the factory-programmed DEVADCx Flash registers into the corresponding ADCxCFG registers.
DS60001361E-page 432
TABLE 29-1: ADC REGISTER MAP (CONTINUED)

Bits
All Resets
Bit Range
Address
Virtual
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
B04C ADCCMP3 31:16 DCMPHI<15:0> 0000

15:0 DCMPLO<15:0> 0000
B054 ADCCMP4 31:16 DCMPHI<15:0> 0000
15:0 DCMPLO<15:0> 0000
B05C ADCCMP5 31:16 DCMPHI<15:0> 0000
15:0 DCMPLO<15:0> 0000
B064 ADCCMP6 31:16 DCMPHI<15:0> 0000
15:0 DCMPLO<15:0> 0000
B068 ADCFLTR1 31:16 AFEN DATA16EN DFMODE OVRSAM<2:0> AFGIEN AFRDY CHNLID<4:0> 0000
15:0 FLTRDATA<15:0> 0000
B06C ADCFLTR2 31:16 AFEN DATA16EN DFMODE OVRSAM<2:0> AFGIEN AFRDY CHNLID<4:0> 0000
15:0 FLTRDATA<15:0> 0000
15:0 FLTRDATA<15:0> 0000
15:0 FLTRDATA<15:0> 0000
15:0 FLTRDATA<15:0> 0000
B07C ADCFLTR6 31:16 AFEN DATA16EN DFMODE OVRSAM<2:0> AFGIEN AFRDY CHNLID<4:0> 0000
15:0 FLTRDATA<15:0> 0000
B080 ADCTRG1 31:16 TRGSRC3<4:0> TRGSRC2<4:0> 0000
15:0 TRGSRC1<4:0> TRGSRC0<4:0> 0000

15:0 TRGSRC5<4:0> TRGSRC4<4:0> 0000
15:0 TRGSRC9<4:0> TRGSRC8<4:0> 0000
B0A0 ADCCMPCON1 31:16 CVDDATA<15:0> 0000
15:0 AINID<5:0> ENDCMP DCMPGIEN DCMPED IEBTWN IEHIHI IEHILO IELOHI IELOLO 0000
B0A4 ADCCMPCON2 31:16 0000
B0A8 ADCCMPCON3 31:16 0000
Bits
All Resets
Bit Range
Address
Virtual
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
B0AC ADCCMPCON4 31:16 0000

B0B0 ADCCMPCON5 31:16 0000
B0B4 ADCCMPCON6 31:16 0000
B0B8 ADCFSTAT 31:16 FEN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN FIEN FRDY FWROVERR 0000
15:0 FCNT<7:0> FSIGN ADCID<2:0> 0000
B0BC ADCFIFO 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
B0C0 ADCBASE 31:16 0000
15:0 ADCBASE<15:0> 0000

B0D0 ADCTRGSNS 31:16 0000
15:0 LVL11 LVL10 LVL9 LVL8 LVL7 LVL6 LVL5 LVL4 LVL3 LVL2 LVL1 LVL0 0000
B0D4 ADC0TIME 31:16 ADCEIS<2:0> SELRES<1:0> ADCDIV<6:0> 0300
15:0 SAMC<9:0> 0000
B0D8 ADC1TIME 31:16 ADCEIS<2:0> SELRES<1:0> ADCDIV<6:0> 0300
15:0 SAMC<9:0> 0000
B0DC ADC2TIME 31:16 ADCEIS<2:0> SELRES<1:0> ADCDIV<6:0> 0300
15:0 SAMC<9:0> 0000
B0E0 ADC3TIME 31:16 ADCEIS<2:0> SELRES<1:0> ADCDIV<6:0> 0300
15:0 SAMC<9:0> 0000
B0E4 ADC4TIME 31:16 ADCEIS<2:0> SELRES<1:0> ADCDIV<6:0> 0300
15:0 SAMC<9:0> 0000
B0F0 ADCEIEN1 31:16 EIEN31 EIEN30 EIEN29 EIEN28 EIEN27 EIEN26 EIEN25 EIEN24 EIEN23 EIEN22 EIEN21 EIEN20 EIEN19 EIEN18 EIEN17 EIEN16 0000
15:0 EIEN15 EIEN14 EIEN13 EIEN12 EIEN11 EIEN10 EIEN9 EIEN8 EIEN7 EIEN6 EIEN5 EIEN4 EIEN3 EIEN2 EIEN1 EIEN0 0000
B0F4 ADCEIEN2 31:16 0000
15:0 EIEN43 EIEN42 EIEN41 EIEN40 EIEN39 EIEN38 EIEN37 EIEN36 EIEN35 EIEN34 EIEN33 EIEN32 0000
B0F8 ADCEISTAT1 31:16 EIRDY31 EIRDY30 EIRDY29 EIRDY28 EIRDY27 EIRDY26 EIRDY25 EIRDY24 EIRDY23 EIRDY22 EIRDY21 EIRDY20 EIRDY19 EIRDY18 EIRDY17 EIRDY16 0000
15:0 EIRDY15 EIRDY14 EIRDY13 EIRDY12 EIRDY11 EIRDY10 EIRDY9 EIRDY8 EIRDY7 EIRDY6 EIRDY5 EIRDY4 EIRDY3 EIRDY2 EIRDY1 EIRDY0 0000
B0FC ADCEISTAT2 31:16 0000
15:0 EIRDY43 EIRDY42 EIRDY41 EIRDY40 EIRDY39 EIRDY38 EIRDY37 EIRDY36 EIRDY35 EIRDY34 EIRDY33 EIRDY32 0000
DS60001361E-page 433
B100 ADCANCON 31:16 WKUPCLKCNT<3:0> WKIEN7 WKIEN4 WKIEN3 WKIEN2 WKIEN1 WKIEN0 0000
15:0 WKRDY7 WKRDY4 WKRDY3 WKRDY2 WKRDY1 WKRDY0 ANEN7 ANEN4 ANEN3 ANEN2 ANEN1 ANEN0 0000
B600 ADC0CFG(1) 31:16 ADCCFG<31:16> 0000
15:0 ADCCFG<15:0> 0000
B604 ADC1CFG1) 31:16 ADCCFG<31:16> 0000
15:0 ADCCFG<15:0> 0000
DS60001361E-page 434

Bits
All Resets
Bit Range
Address
Virtual
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
B608 ADC2CFG1) 31:16 ADCCFG<31:16> 0000

15:0 ADCCFG<15:0> 0000
B60C ADC3CFG1) 31:16 ADCCFG<31:16> 0000
15:0 ADCCFG<15:0> 0000
B610 ADC4CFG1) 31:16 ADCCFG<31:16> 0000
15:0 ADCCFG<15:0> 0000
B61C ADC7CFG1) 31:16 ADCCFG<31:16> 0000
15:0 ADCCFG<15:0> 0000
B640 ADCSYSCFG1 31:16 AN<31:16> 0000
15:0 AN<15:0> 0000
B644 ADCSYSCFG2 31:16 0000
15:0 AN<43:32> 0000
BA00 ADCDATA0 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA04 ADCDATA1 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA08 ADCDATA2 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA0C ADCDATA3 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA10 ADCDATA4 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA14 ADCDATA5 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA18 ADCDATA6 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA1C ADCDATA7 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000

BA20 ADCDATA8 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA24 ADCDATA9 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA28 ADCDATA10 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA2C ADCDATA11 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA30 ADCDATA12 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
Bits
All Resets
Bit Range
Address
Virtual
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
BA34 ADCDATA13 31:16 DATA<31:16> 0000

15:0 DATA<15:0> 0000
BA38 ADCDATA14 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA3C ADCDATA15 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA40 ADCDATA16 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA44 ADCDATA17 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA48 ADCDATA18 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000

BA4C ADCDATA19 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA50 ADCDATA20 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA54 ADCDATA21 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA58 ADCDATA22 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA5C ADCDATA23 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA60 ADCDATA24 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA64 ADCDATA25 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA68 ADCDATA26 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA6C ADCDATA27 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA70 ADCDATA28 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
DS60001361E-page 435
BA74 ADCDATA29 31:16 DATA<31:16> 0000

15:0 DATA<15:0> 0000
BA78 ADCDATA30 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA7C ADCDATA31 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
DS60001361E-page 436

Bits
All Resets
Bit Range
Address
Virtual
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
BA80 ADCDATA32 31:16 DATA<31:16> 0000

15:0 DATA<15:0> 0000
BA84 ADCDATA33 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA88 ADCDATA34 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA8C ADCDATA35 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA90 ADCDATA36 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA94 ADCDATA37 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA98 ADCDATA38 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BA9C ADCDATA39 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BAA0 ADCDATA40 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BAA4 ADCDATA41 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BAA8 ADCDATA42 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
BAAC ADCDATA43 31:16 DATA<31:16> 0000
15:0 DATA<15:0> 0000
REGISTER 29-1: ADCCON1: ADC CONTROL REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
TRBEN TRBERR TRBMST<2:0> TRBSLV<2:0>
23:16
FRACT SELRES<1:0> STRGSRC<4:0>
R/W-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 U-0
15:8
ON SIDL AICPMPEN CVDEN FSSCLKEN FSPBCLKEN
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
7:0
IRQVS<2:0> STRGLVL
Legend: HC = Hardware Set HS = Hardware Cleared

bit 31 TRBEN: Turbo Channel Enable bit

1 = Enable the Turbo channel
0 = Disable the Turbo channel
bit 30 TRBERR: Turbo Channel Error Status bit
1 = An error occurred while setting the Turbo channel and Turbo channel function to be disabled regardless
of the TRBEN bit being set to 1.
0 = Turbo channel error did not occur
Note: The status of this bit is valid only after the TRBEN bit is set.
bit 29-27 TRBMST<2:0>: Turbo Master ADCx bits
111 = Reserved
110 = ADC4 is selected as the Turbo Master

000 = ADC0 is selected as the Turbo Master
bit 26-24 TRBSLV<2:0>: Turbo Slave ADCx bits
111 = Reserved
110 = ADC4 is selected as the Turbo Slave

000 = ADC0 is selected as the Turbo Slave
bit 23 FRACT: Fractional Data Output Format bit
1 = Fractional
0 = Integer
bit 22-21 SELRES<1:0>: Shared ADC (ADC7) Resolution bits
11 = 12 bits (default)
10 = 10 bits
01 = 8 bits
00 = 6 bits
Note: Changing the resolution of the ADC does not shift the result in the corresponding ADCDATAx
register. The result will still occupy 12 bits, with the corresponding lower unused bits set to 0.
For example, a resolution of 6 bits will result in ADCDATAx<5:0> being set to 0, and
ADCDATAx<11:6> holding the result.
Note 1: The rising edge of the module output signal triggers an ADC conversion. See Figure 16-1 in 16.0 Output
Compare and Figure 32-1 in 32.0 Comparator for more information.

REGISTER 29-1: ADCCON1: ADC CONTROL REGISTER 1 (CONTINUED)
bit 20-16 STRGSRC<4:0>: Scan Trigger Source Select bits
11111 = Reserved
11110 = Reserved
11101 = CTMU Event
11100 = Reserved

01110 = Reserved
01101 = CTMU Event
01100 = Comparator 2 (C2OUT) (1)
01010 = OCMP5 (1)
01001 = OCMP3 (1)
01000 = OCMP1 (1)
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00100 = INT0 External interrupt
00011 = Reserved
00010 = Global level software trigger (GLSWTRG)
00001 = Global software edge trigger (GSWTRG)
00000 = No Trigger
bit 15 ON: ADC Module Enable bit
1 = ADC module is enabled
0 = ADC module is disabled
Note: The ON bit should be set only after the ADC module has been configured.
bit 12 AICPMPEN: Analog Input Charge Pump Enable bit
1 = Analog input charge pump is enabled
0 = Analog input charge pump is disabled
Note 1: For proper analog operation at VDDIO less than 2.5V, the AICPMPEN bit and the IOANCPEN
(CFGCON<7>) bit must be set to `1'. These bits should not be set if VDDIO is greater than 2.5V.
2: ADC throughput rate performance is reduced as defined in the table below if the AICPMPEN
(ADCCON1<12>) bit and the IOANCPEN(CFGCON<7>) bit are set to '1'
bit 11 CVDEN: Capacitive Voltage Division Enable bit

1 = CVD operation is enabled
0 = CVD operation is disabled

bit 10 FSSCLKEN: Fast Synchronous System Clock to ADC Control Clock bit
1 = Fast synchronous system clock to ADC control clock is enabled
0 = Fast synchronous system clock to ADC control clock is disabled
bit 9 FSPBCLKEN: Fast Synchronous Peripheral Clock to ADC Control Clock bit
1 = Fast synchronous peripheral clock to ADC control clock is enabled
0 = Fast synchronous peripheral clock to ADC control clock is disabled
bit 6-4 IRQVS<2:0>: Interrupt Vector Shift bits

To determine interrupt vector address, this bit specifies the amount of left shift done to the ARDYx status
bits in the ADCDSTAT1 and ADCDSTAT2 registers, prior to adding with the ADCBASE register.
Interrupt Vector Address = Read Value of ADCBASE and Read Value of ADCBASE = Value written to
ADCBASE + x << IRQVS<2:0>, where x is the smallest active input ID from the ADCDSTAT1 or
ADCDSTAT2 registers (which has highest priority).
111 = Shift x left 7 bit position
bit 3 STRGLVL: Scan Trigger High Level/Positive Edge Sensitivity bit
1 = Scan trigger is high level sensitive. Once STRIG mode is selected (TRGSRCx<4:0> in the ADCTRGx
register), the scan trigger will continue for all selected analog inputs, until the STRIG option is removed.
0 = Scan trigger is positive edge sensitive. Once STRIG mode is selected (TRGSRCx<4:0> in the
ADCTRGx register), only a single scan trigger will be generated, which will complete the scan of all
selected analog inputs.


31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0, HS, HC R-0, HS, HC R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
BGVRRDY REFFLT EOSRDY CVDCPL<2:0> SAMC<9:8>
23:16
SAMC<7:0>
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
15:8
BGVRIEN REFFLTIEN EOSIEN ADCEIOVR ADCEIS<2:0>
7:0
ADCDIV<6:0>
Legend: HC = Hardware Set HS = Hardware Cleared r = Reserved

bit 31 BGVRRDY: Band Gap Voltage/ADC Reference Voltage Status bit

1 = Both band gap voltage and ADC reference voltages (VREF) are ready
0 = Either or both band gap voltage and ADC reference voltages (VREF) are not ready
Data processing is valid only after BGVRRDY is set by hardware, so the application code must check that
the BGVRRDY bit is set to ensure data validity. This bit set to 0 when ON (ADCCON1<15>) = 0.
bit 30 REFFLT: Band Gap/VREF/AVDD BOR Fault Status bit
1 = Fault in band gap or the VREF voltage while the ON bit (ADCCON1<15>) was set. Most likely a band
gap or VREF fault will be caused by a BOR of the analog VDDIO supply.
0 = Band gap and VREF voltage are working properly
This bit is cleared when the ON bit (ADCCON1<15>) = 0 and the BGVRRDY bit = 1.
bit 29 EOSRDY: End of Scan Interrupt Status bit
1 = All analog inputs are considered for scanning through the scan trigger (all analog inputs specified in
the ADCCSS1 and ADCCSS2 registers) have completed scanning
0 = Scanning has not completed
This bit is cleared when ADCCON2<31:24> are read in software.
bit 28-26 CVDCPL<2:0>: Capacitor Voltage Divider (CVD) Setting bit
111 = 7 * 2.5 pF = 17.5 pF
110 = 6 * 2.5 pF = 15 pF
101 = 5 * 2.5 pF = 12.5 pF
100 = 4 * 2.5 pF = 10 pF
011 = 3 * 2.5 pF = 7.5 pF
010 = 2 * 2.5 pF = 5 pF
001 = 1 * 2.5 pF = 2.5 pF
000 = 0 * 2.5 pF = 0 pF
bit 25-16 SAMC<9:0>: Sample Time for the Shared ADC (ADC7) bits
1111111111 = 1025 TAD7

0000000001 = 3 TAD7
0000000000 = 2 TAD7
Where TAD7 = period of the ADC conversion clock for the Shared ADC (ADC7) controlled by the
ADCDIV<6:0> bits.
bit 15 BGVRIEN: Band Gap/VREF Voltage Ready Interrupt Enable bit
1 = Interrupt will be generated when the BGVRDDY bit is set
0 = No interrupt is generated when the BGVRRDY bit is set

bit 14 REFFLTIEN: Band Gap/VREF Voltage Fault Interrupt Enable bit
1 = Interrupt will be generated when the REFFLT bit is set
0 = No interrupt is generated when the REFFLT bit is set
bit 13 EOSIEN: End of Scan Interrupt Enable bit
1 = Interrupt will be generated when EOSRDY bit is set
0 = No interrupt is generated when the EOSRDY bit is set
bit 12 ADCEIOVR: Early Interrupt Request Override bit
1 = Early interrupt generation is not overridden and interrupt generation is controlled by the ADCEIEN1
and ADCEIEN2 registers
0 = Early interrupt generation is overridden and interrupt generation is controlled by the ADCGIRQEN1
and ADCGIRQEN2 registers
bit 10-8 ADCEIS<2:0>: Shared ADC (ADC7) Early Interrupt Select bits
These bits select the number of clocks (TAD7) prior to the arrival of valid data that the associated interrupt
is generated.
111 = The data ready interrupt is generated 8 ADC clocks prior to end of conversion
110 = The data ready interrupt is generated 7 ADC clocks prior to end of conversion

001 = The data ready interrupt is generated 2 ADC module clocks prior to end of conversion
000 = The data ready interrupt is generated 1 ADC module clock prior to end of conversion
Note: All options are available when the selected resolution, set by the SELRES<1:0> bits
(ADCCON1<22:21>), is 12-bit or 10-bit. For a selected resolution of 8-bit, options from 000 to
101 are valid. For a selected resolution of 6-bit, options from 000 to 011 are valid.
bit 6-0 ADCDIV<6:0>: Shared ADC (ADC7) Clock Divider bits
1111111 = 254 * TQ = TAD7

0000011 = 6 * TQ = TAD7
0000010 = 4 * TQ = TAD7
0000001 = 2 * TQ = TAD7
0000000 = Reserved
The ADCDIV<6:0> bits divide the ADC control clock (TQ) to generate the clock for the Shared ADC, ADC7
(TAD7).


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
ADCSEL<1:0> CONCLKDIV<5:0>
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
DIGEN7 DIGEN4 DIGEN3 DIGEN2 DIGEN1 DIGEN0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC R/W-0 R-0, HS, HC
15:8
VREFSEL<2:0> TRGSUSP UPDIEN UPDRDY SAMP(1,2,3,4) RQCNVRT
R/W-0 R/W, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
GLSWTRG GSWTRG ADINSEL<5:0>
Legend: HC = Hardware Set HS = Hardware Cleared

bit 31-30 ADCSEL<1:0>: Analog-to-Digital Clock Source (TCLK) bits

11 = FRC
10 = REFCLK3
01 = System Clock (Tcy)
00 = PBCLK3
bit 29-24 CONCLKDIV<5:0>: Analog-to-Digital Control Clock (TQ) Divider bits
111111 = 64 * TCLK = TQ

000011 = 4 * TCLK = TQ
000010 = 3 * TCLK = TQ
000001 = 2 * TCLK = TQ
000000 = TCLK = TQ
bit 23 DIGEN7: Shared ADC (ADC7) Digital Enable bit
1 = ADC7 is digital enabled
0 = ADC7 is digital disabled
bit 20 DIGEN4: ADC4 Digital Enable bit
Note 1: The SAMP bit has the highest priority and setting this bit will keep the S&H circuit in Sample mode until the
bit is cleared. Also, usage of the SAMP bit will cause settings of SAMC<9:0> bits (ADCCON2<25:16>) to
be ignored.
2: The SAMP bit only connects Class 2 and Class 3 analog inputs to the shared ADC, ADC7. All Class 1
analog inputs are not affected by the SAMP bit.
3: The SAMP bit is not a self-clearing bit and it is the responsibility of application software to first clear this bit
and only after setting the RQCNVRT bit to start the analog-to-digital conversion.
4: Normally, when the SAMP and RQCNVRT bits are used by software routines, all TRGSRCx<4:0> bits and
STRGSRC<4:0> bits should be set to 00000 to disable all external hardware triggers and prevent them
from interfering with the software-controlled sampling command signal SAMP and with the software-con-
trolled trigger RQCNVRT.

bit 15-13 VREFSEL<2:0>: Voltage Reference (VREF) Input Selection bits
VREFSEL<2:0> ADREF+ ADREF-
111 AVDD Internal VREFL
110 Internal VREFH AVSS
101 Internal VREFH External VREFL
100 Internal VREFH Internal VREFL
011 Internal VREFH External VREFL
010 AVDD External VREFL
001 External VREFH AVss
000 AVDD AVss
bit 12 TRGSUSP: Trigger Suspend bit
1 = Triggers are blocked from starting a new analog-to-digital conversion, but the ADC module is not disabled
0 = Triggers are not blocked
bit 11 UPDIEN: Update Ready Interrupt Enable bit
1 = Interrupt will be generated when the UPDRDY bit is set by hardware
0 = No interrupt is generated
bit 10 UPDRDY: ADC Update Ready Status bit
1 = ADC SFRs can be updated
0 = ADC SFRs cannot be updated
Note: This bit is only active while the TRGSUSP bit is set and there are no more running conversions of
any ADC modules.
bit 9 SAMP: Class 2 and Class 3 Analog Input Sampling Enable bit(1,2,3,4)
1 = The ADC S&H amplifier is sampling
0 = The ADC S&H amplifier is holding
bit 8 RQCNVRT: Individual ADC Input Conversion Request bit
This bit and its associated ADINSEL<5:0> bits enable the user to individually request an analog-to-digital
conversion of an analog input through software.
1 = Trigger the conversion of the selected ADC input as specified by the ADINSEL<5:0> bits
0 = Do not trigger the conversion
Note: This bit is automatically cleared in the next ADC clock cycle.
be ignored.

bit 7 GLSWTRG: Global Level Software Trigger bit
1 = Trigger conversion for ADC inputs that have selected the GLSWTRG bit as the trigger signal, either
through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0>
bits in the ADCCON1 register
0 = Do not trigger an analog-to-digital conversion
bit 6 GSWTRG: Global Software Trigger bit
1 = Trigger conversion for ADC inputs that have selected the GSWTRG bit as the trigger signal, either
through the associated TRGSRC<4:0> bits in the ADCTRGx registers or through the STRGSRC<4:0>
bits in the ADCCON1 register
0 = Do not trigger an analog-to-digital conversion
Note: This bit is automatically cleared in the next ADC clock cycle.
bit 5-0 ADINSEL<5:0>: Analog Input Select bits
These bits select the analog input to be converted when the RQCNVRT bit is set. As a general rule:
111111 = Reserved

101101 = Reserved
101100 = IVTEMP
101011 = IVREF
101010 = VBAT
101000 = CTMU
100111 = AN39

000001 = AN1
000000 = AN0
be ignored.

REGISTER 29-4: ADCTRGMODE: ADC TRIGGERING MODE FOR DEDICATED ADC REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
31:24
SH4ALT<1:0>
23:16
SH3ALT<1:0> SH2ALT<1:0> SH1ALT<1:0> SH0ALT<1:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
STRGEN4 STRGEN3 STRGEN2 STRGEN1 STRGEN0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
SSAMPEN4 SSAMPEN3 SSAMPEN2 SSAMPEN1 SSAMPEN0
Legend:

bit 25-24 SH4ALT<1:0>: ADC4 Analog Input Select bit
11 = Reserved
10 = Reserved
01 = AN49
00 = AN4
11 = Reserved
10 = Reserved
01 = AN48
00 = AN3
11 = Reserved
10 = Reserved
01 = AN47
00 = AN2
11 = Reserved
10 = Reserved
01 = AN46
00 = AN1
11 = Reserved
10 = Reserved
01 = AN45
00 = AN0
bit 12 STRGEN4: ADC4 Presynchronized Triggers bit
1 = ADC4 uses presynchronized triggers
0 = ADC4 does not use presynchronized triggers

REGISTER 29-4: ADCTRGMODE: ADC TRIGGERING MODE FOR DEDICATED ADC REGISTER
bit 4 SSAMPEN4: ADC4 Synchronous Sampling bit
1 = ADC4 uses synchronous sampling for the first sample after being idle or disabled
0 = ADC4 does not use synchronous sampling
bit 2 SSAMPEN2: ADC2Synchronous Sampling bit

REGISTER 29-5: ADCIMCON1: ADC INPUT MODE CONTROL REGISTER 1

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
DIFF15 SIGN15 DIFF14 SIGN14 DIFF13 SIGN13 DIFF12 SIGN12
23:16
15:8
7:0
Legend:
bit 31 DIFF15: AN15 Mode bit

1 = AN15 is using Differential mode
0 = AN15 is using Single-ended mode
bit 30 SIGN:15 AN15 Signed Data Mode bit
1 = AN15 is using Signed Data mode
0 = AN15 is using Unsigned Data mode
bit 28 SIGN14: AN14 Signed Data Mode bit

REGISTER 29-5: ADCIMCON1: ADC INPUT MODE CONTROL REGISTER 1 (CONTINUED)
bit 17 DIFF8: AN 8 Mode bit



31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
23:16
15:8
7:0
Legend:





31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
15:8
7:0
Legend:



REGISTER 29-8: ADCGIRQEN1: ADC GLOBAL INTERRUPT ENABLE REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
AGIEN31 AGIEN30 AGIEN29 AGIEN28 AGIEN27 AGIEN26 AGIEN25 AGIEN24
23:16
15:8
7:0
Legend:
bit 31-0 AGIEN31:AGIEN0: ADC Global Interrupt Enable bits

1 = Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data
is ready (indicated by the ARDYx bit (x = 31-0) of the ADCDSTAT1 register)
0 = Interrupts are disabled
REGISTER 29-9: ADCGIRQEN2: ADC GLOBAL INTERRUPT ENABLE REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
AGIEN43 AGIEN42 AGIEN41 AGIEN40
7:0
Legend:

bit 11-0 AGIEN43:AGIEN32 ADC Global Interrupt Enable bits
1 = Interrupts are enabled for the selected analog input. The interrupt is generated after the converted data
is ready (indicated by the ARDYx bit (x = 43-32) of the ADCDSTAT2 register)

REGISTER 29-10: ADCCSS1: ADC COMMON SCAN SELECT REGISTER 1

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
CSS31 CSS30 CSS29 CSS28 CSS27 CSS26 CSS25 CSS24
23:16
15:8
7:0
Legend:
bit 31-0 CSS31:CSS0: Analog Common Scan Select bits

1 = Select ANx for input scan
0 = Skip ANx for input scan
Note 1: In addition to setting the appropriate bits in this register, Class 1 and Class 2 analog inputs must select the
STRIG input as the trigger source if they are to be scanned through the CSSx bits. Refer to the bit
descriptions in the ADCTRGx registers for selecting the STRIG option.
2: If a Class 1 or Class 2 input is included in the scan by setting the CSSx bit to 1 and by setting the
TRGSRCx<4:0> bits to STRIG mode (0b11), the user application must ensure that no other triggers are
generated for that input using the RQCNVRT bit in the ADCCON3 register or the hardware input or any
digital filter. Otherwise, the scan behavior is unpredictable.

REGISTER 29-11: ADCCSS2: ADC COMMON SCAN SELECT REGISTER 2

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CSS43 CSS42 CSS41 CSS40
7:0
Legend:

bit 11-0 CSS43:CSS32: Analog Common Scan Select bits
Analog inputs 43 to 32 are always Class 3, as there are only 32 triggers available.
1 = Select ANx for input scan
0 = Skip ANx for input scan

REGISTER 29-12: ADCDSTAT1: ADC DATA READY STATUS REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
31:24
ARDY31 ARDY30 ARDY29 ARDY28 ARDY27 ARDY26 ARDY25 ARDY24
23:16
15:8
7:0

bit 31-0 ARDY31:ARDY0: Conversion Data Ready for Corresponding Analog Input Ready bits
1 = This bit is set when converted data is ready in the data register
0 = This bit is cleared when the associated data register is read
REGISTER 29-13: ADCDSTAT2: ADC DATA READY STATUS REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
15:8
ARDY43 ARDY42 ARDY41 ARDY40
7:0


bit 11-0 ARDY43:ARDY32: Conversion Data Ready for Corresponding Analog Input Ready bits
1 = This bit is set when converted data is ready in the data register
0 = This bit is cleared when the associated data register is read

REGISTER 29-14: ADCCMPENx: ADC DIGITAL COMPARATOR x ENABLE REGISTER

(x = 1 THROUGH 6)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
CMPE31 CMPE30 CMPE29 CMPE28 CMPE27 CMPE26 CMPE25 CMPE24
23:16
15:8
7:0
Legend:
bit 31-0 CMPE31:CMPE0: ADC Digital Comparator x Enable bits

These bits enable conversion results corresponding to the Analog Input to be processed by the Digital
Comparator. CMPE0 enables AN0, CMPE1 enables AN1, and so on.
Note 1: CMPEx = ANx, where x = 0-31 (Digital Comparator inputs are limited to AN0 through AN31).
2: Changing the bits in this register while the Digital Comparator is enabled (ENDCMP = 1) can result in
unpredictable behavior.

REGISTER 29-15: ADCCMPx: ADC DIGITAL COMPARATOR x LIMIT VALUE REGISTER

(x = 1 THROUGH 6)
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
DCMPHI<15:8>(1,2,3)
23:16
DCMPHI<7:0>(1,2,3)
15:8
DCMPLO<15:8>(1,2,3)
7:0
DCMPLO<7:0>(1,2,3)
Legend:
bit 31-16 DCMPHI<15:0>: Digital Comparator x High Limit Value bits(1,2,3)

These bits store the high limit value, which is used by digital comparator for comparisons with ADC
converted data.
bit 15-0 DCMPLO<15:0>: Digital Comparator x Low Limit Value bits(1,2,3)
These bits store the low limit value, which is used by digital comparator for comparisons with ADC
converted data.
Note 1: Changing theses bits while the Digital Comparator is enabled (ENDCMP = 1) can result in unpredictable
behavior.
2: The format of the limit values should match the format of the ADC converted value in terms of sign and
fractional settings.
3: For Digital Comparator 0 used in CVD mode, the DCMPHI<15:0> and DCMPLO<15:0> bits must always
be specified in signed format, as the CVD output data is differential and is always signed.

REGISTER 29-16: ADCFLTRx: ADC DIGITAL FILTER x REGISTER (x = 1 THROUGH 6)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0, HS, HC
31:24
AFEN DATA16EN DFMODE OVRSAM<2:0> AFGIEN AFRDY
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
CHNLID<4:0>
15:8
FLTRDATA<15:8>
7:0
FLTRDATA<7:0>

bit 31 AFEN: Digital Filter x Enable bit

1 = Digital filter is enabled
0 = Digital filter is disabled and the AFRDY status bit is cleared
bit 30 DATA16EN: Filter Significant Data Length bit
1 = All 16 bits of the filter output data are significant
0 = Only the first 12 bits are significant, followed by four zeros
Note: This bit is significant only if DFMODE = 1 (Averaging Mode) and FRACT (ADCCON1<23>) = 1
(Fractional Output Mode).
bit DFMODE: ADC Filter Mode bit
1 = Filter x works in Averaging mode
0 = Filter x works in Oversampling Filter mode (default)
bit 28-26 OVRSAM<2:0>: Oversampling Filter Ratio bits
If DFMODE is 0:
111 = 128 samples (shift sum 3 bits to right, output data is in 15.1 format)
101 = 8 samples (shift sum 1 bit to right, output data is in 13.1 format)
011 = 256 samples (shift sum 4 bits to right, output data is 16 bits)
000 = 4 samples (shift sum 1 bit to right, output data is 13 bits)
If DFMODE is 1:
111 = 256 samples (256 samples to be averaged)
bit 25 AFGIEN: Digital Filter x Interrupt Enable bit
1 = Digital filter interrupt is enabled and is generated by the AFRDY status bit
0 = Digital filter is disabled

REGISTER 29-16: ADCFLTRx: ADC DIGITAL FILTER x REGISTER (x = 1 THROUGH 6)
bit 24 AFRDY: Digital Filter x Data Ready Status bit
1 = Data is ready in the FLTRDATA<15:0> bits
0 = Data is not ready
Note: This bit is cleared by reading the FLTRDATA<15:0> bits or by disabling the Digital Filter module
(by setting AFEN to 0).
bit 20-16 CHNLID<4:0>: Digital Filter Analog Input Selection bits
These bits specify the analog input to be used as the oversampling filter data source.
11111 = Reserved

01100 = Reserved
01011 = AN11

00001 = AN1
00000 = AN0
Note: Only the first 12 analog inputs, Class 1 (AN0-AN11) and Class 2 (AN5-AN11), can use a digital
filter.
bit 15-0 FLTRDATA<15:0>: Digital Filter x Data Output Value bits
The filter output data is as per the fractional format set in the FRACT bit (ADCCON1<23>). The FRACT bit
should not be changed while the filter is enabled. Changing the state of the FRACT bit after the operation
of the filter ended will not update the value of the FLTRDATA<15:0> bits to reflect the new format.

REGISTER 29-17: ADCTRG1: ADC TRIGGER SOURCE 1 REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
TRGSRC3<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
TRGSRC2<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
TRGSRC1<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
TRGSRC0<4:0>
Legend:

bit 28-24 TRGSRC3<4:0>: Trigger Source for Conversion of Analog Input AN3 Select bits
11111 = Reserved
11110 = Reserved
11101 = CTMU Event
11100 = Reserved

01110 = Reserved
01101 = CTMU Event
01010 = OCMP5 (1)
01001 = OCMP3 (1)
01000 = OCMP1 (1)
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00011 = STRIG
00000 = No Trigger
For STRIG, in addition to setting the trigger, it also requires programming of the STRGSRC<4:0> bits
(ADCCON1<20:16>) to select the trigger source, and requires the appropriate CSS bits to be set in the
ADCCSSx registers.
See bits 28-24 for bit value definitions.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
TRGSRC7<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
TRGSRC6<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
TRGSRC5<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
TRGSRC4<4:0>
Legend:

11111 = Reserved
11110 = Reserved
11101 = CTMU Event
11100 = Reserved

01110 = Reserved
01101 = CTMU Event
01010 = OCMP5 (1)
01001 = OCMP3 (1)
01000 = OCMP1 (1)
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00011 = STRIG
00000 = No Trigger
ADCCSSx registers.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
TRGSRC11<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
TRGSRC10<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
TRGSRC9<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
TRGSRC8<4:0>
Legend:

11111 = Reserved
11110 = Reserved
11101 = CTMU Event
11100 = Reserved

01110 = Reserved
01101 = CTMU Event
01010 = OCMP5 (1)
01001 = OCMP3 (1)
01000 = OCMP1 (1)
00111 = TMR5 match
00110 = TMR3 match
00101 = TMR1 match
00011 = STRIG
00000 = No Trigger
ADCCSSx registers.

REGISTER 29-20: ADCCMPCON1: ADC DIGITAL COMPARATOR 1 CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
CVDDATA<15:8>
23:16
CVDDATA<7:0>
U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
15:8
AINID<5:0>
R/W-0 R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
ENDCMP DCMPGIEN DCMPED IEBTWN IEHIHI IEHILO IELOHI IELOLO

bit 31-16 CVDDATA<15:0>: CVD Data Status bits

In CVD mode, these bits obtain the CVD differential output data (subtraction of CVD positive and negative
measurement), whenever a Digital Comparator interrupt is generated. The value in these bits is compliant
with the FRACT bit (ADCCON1<23>) and is always signed.
bit 13-8 AINID<5:0>: Digital Comparator 0 Analog Input Identification (ID) bits
When a digital comparator event occurs (DCMPED = 1), these bits identify the analog input being
monitored by Digital Comparator 0.
Note: In normal ADC mode, only analog inputs <31:0> can be processed by the Digital Comparator 0.
The Digital Comparator 0 also supports the CVD mode, in which all Class 2 and Class 3 analog
inputs may be stored in the AINID<5:0> bits.
111111 = Reserved

101100 = Reserved
101011 = AN43 is being monitored

bit 7 ENDCMP: Digital Comparator 0 Enable bit
1 = Digital Comparator 0 is enabled
0 = Digital Comparator 0 is not enabled, and the DCMPED status bit (ADCCMP0CON<5>) is cleared
bit 6 DCMPGIEN: Digital Comparator 0 Global Interrupt Enable bit
1 = A Digital Comparator 0 interrupt is generated when the DCMPED status bit (ADCCMP0CON<5>) is set
0 = A Digital Comparator 0 interrupt is disabled
bit 5 DCMPED: Digital Comparator 0 Output True Event Status bit
The logical conditions under which the digital comparator gets True are defined by the IEBTWN, IEHIHI,
IEHILO, IELOHI, and IELOLO bits.
Note: This bit is cleared by reading the AINID<5:0> bits or by disabling the Digital Comparator module
(by setting ENDCMP to 0).
1 = Digital Comparator 0 output true event has occurred (output of Comparator is 1)
0 = Digital Comparator 0 output is false (output of comparator is 0)
bit 4 IEBTWN: Between Low/High Digital Comparator 0 Event bit
1 = Generate a digital comparator event when DCMPLO<15:0> DATA<31:0> < DCMPHI<15:0>
0 = Do not generate a digital comparator event

REGISTER 29-20: ADCCMPCON1: ADC DIGITAL COMPARATOR 1 CONTROL REGISTER
bit 3 IEHIHI: High/High Digital Comparator 0 Event bit
1 = Generate a Digital Comparator 0 Event when DCMPHI<15:0> DATA<31:0>
0 = Do not generate an event
bit 2 IEHILO: High/Low Digital Comparator 0 Event bit
1 = Generate a Digital Comparator 0 Event when DATA<31:0> < DCMPHI<15:0>
bit 1 IELOHI: Low/High Digital Comparator 0 Event bit
1 = Generate a Digital Comparator 0 Event when DCMPLO<15:0> DATA<31:0>
bit 0 IELOLO: Low/Low Digital Comparator 0 Event bit
1 = Generate a Digital Comparator 0 Event when DATA<31:0> < DCMPLO<15:0>

REGISTER 29-21: ADCCMPCONx: ADC DIGITAL COMPARATOR x CONTROL REGISTER

(x = 2 THROUGH 6)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
15:8
AINID<4:0>
R/W-0 R/W-0 R-0, HS, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
ENDCMP DCMPGIEN DCMPED IEBTWN IEHIHI IEHILO IELOHI IELOLO


bit 12-8 AINID<4:0>: Digital Comparator x Analog Input Identification (ID) bits
When a digital comparator event occurs (DCMPED = 1), these bits identify the analog input being
monitored by the Digital Comparator.
Note: Only analog inputs <31:0> can be processed by the Digital Comparator module x (x = 1-5).

bit 7 ENDCMP: Digital Comparator x Enable bit
1 = Digital Comparator x is enabled
0 = Digital Comparator x is not enabled, and the DCMPED status bit (ADCCMPxCON<5>) is cleared
bit 6 DCMPGIEN: Digital Comparator x Global Interrupt Enable bit
1 = A Digital Comparator x interrupt is generated when the DCMPED status bit (ADCCMPxCON<5>) is set
0 = A Digital Comparator x interrupt is disabled
bit 5 DCMPED: Digital Comparator x Output True Event Status bit
The logical conditions under which the digital comparator gets True are defined by the IEBTWN, IEHIHI,
IEHILO, IELOHI and IELOLO bits.
Note: This bit is cleared by reading the AINID<5:0> bits (ADCCMP0CON<13:8>) or by disabling the
Digital Comparator module (by setting ENDCMP to 0).
1 = Digital Comparator x output true event has occurred (output of Comparator is 1)
0 = Digital Comparator x output is false (output of Comparator is 0)
bit 4 IEBTWN: Between Low/High Digital Comparator x Event bit
1 = Generate a digital comparator event when the DCMPLO<15:0> bits DATA<31:0> bits
< DCMPHI<15:0> bits
0 = Do not generate a digital comparator event
bit 3 IEHIHI: High/High Digital Comparator x Event bit
1 = Generate a Digital Comparator x Event when the DCMPHI<15:0> bits DATA<31:0> bits
bit 2 IEHILO: High/Low Digital Comparator x Event bit
1 = Generate a Digital Comparator x Event when the DATA<31:0> bits < DCMPHI<15:0> bits

REGISTER 29-21: ADCCMPCONx: ADC DIGITAL COMPARATOR x CONTROL REGISTER
(x = 2 THROUGH 6) (CONTINUED)
bit 1 IELOHI: Low/High Digital Comparator x Event bit
1 = Generate a Digital Comparator x Event when the DCMPLO<15:0> bits DATA<31:0> bits
bit 0 IELOLO: Low/Low Digital Comparator x Event bit
1 = Generate a Digital Comparator x Event when the DATA<31:0> bits < DCMPLO<15:0> bits

REGISTER 29-22: ADCFSTAT: ADC FIFO STATUS REGISTER

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FEN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN
R/W-0 R-0, HS, HC R-0, HS, HC U-0 U-0 U-0 U-0 U-0
23:16
FIEN FRDY FWROVERR
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
FCNT<7:0>
R-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
7:0
FSIGN ADCID<2:0>
Legend:
bit 31 FEN: FIFO Enable bit

1 = FIFO is enabled
0 = FIFO is disabled; no data is being saved into the FIFO
bit 28-24 ADC4EN:ADC0EN: ADCx Enable bits (x = 0 through 4)
1 = Converted output data of ADCx is stored in the FIFO
0 = Converted output data of ADCx is not stored in the FIFO
Note: While using FIFO, the output data is additionally stored in the respective output data register
(ADCDATAx).
bit 23 FIEN: FIFO Interrupt Enable bit
1 = FIFO interrupts are enabled; an interrupt is generated once the FRDY bit is set
0 = FIFO interrupts are disabled
bit 22 FRDY: FIFO Data Ready Interrupt Status bit
1 = FIFO has data to be read
0 = No data is available in the FIFO
Note: This bit is cleared when the FIFO output data in ADCFIFO has been read and there is no
additional data ready in the FIFO (that is, the FIFO is empty).
bit 21 FWROVERR: FIFO Write Overflow Error Status bit
1 = A write overflow error in the FIFO has occurred (circular FIFO)
0 = A write overflow error in the FIFO has not occurred
Note: This bit is cleared after ADCFSTAT<23:16> are read by software.
bit 15-8 FCNT<7:0>: FIFO Data Entry Count Status bit
The value in these bits indicates the number of data entries in the FIFO.
bit 7 FSIGN: FIFO Sign Setting bit
This bit reflects the sign of data stored in the ADCFIFO register.
bit 2-0 ADCID<2:0>: ADCx Identifier bits (x = 0 through 6)
These bits specify the ADC module whose data is stored in the FIFO.
111 = Reserved
110 = Reserved
100 = Converted data of ADC4 is store in FIFO

000 = Converted data of ADC0 is stored in FIFO

REGISTER 29-23: ADCFIFO: ADC FIFO DATA REGISTER

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
DATA<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
DATA<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
DATA<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
DATA<7:0>
Legend:
bit 31-0 DATA<31:0>: FIFO Data Output Value bits
Note: When an alternate input is used as the input source for a dedicated ADC module, the data output is still read
from the Primary input Data Output Register.

REGISTER 29-24: ADCBASE: ADC BASE REGISTER

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
ADCBASE<15:8>
7:0
ADCBASE<7:0>
Legend:

bit 15-0 ADCBASE<15:0>: ADC ISR Base Address bits
This register, when read, contains the base address of the user's ADC ISR jump table. The interrupt vector
address is determined by the IRQVS<2:0> bits of the ADCCON1 register specifying the amount of left
shift done to the ARDYx status bits in the ADCDSTAT1 and ADCDSTAT2 registers, prior to adding with
ADCBASE register.
Interrupt Vector Address = Read Value of ADCBASE and Read Value of ADCBASE = Value written to
ADCBASE + x << IRQVS<2:0>, where x is the smallest active analog input ID from the ADCDSTAT1 or
ADCDSTAT2 registers (which has highest priority).

REGISTER 29-25: ADCDATAx: ADC OUTPUT DATA REGISTER x (x = 0 THROUGH 43)

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
DATA<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
DATA<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
DATA<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
DATA<7:0>
Legend:
bit 31-0 DATA<31:0>: ADC Converted Data Output bits.
Note 1: When an alternate input is used as the input source for a dedicated ADC module, the data output is still
read from the Primary input Data Output Register.
2: Reading the ADCDATAx register value after changing the FRACT bit converts the data into the format
specified by FRACT bit.

REGISTER 29-26: ADCTRGSNS: ADC TRIGGER LEVEL/EDGE SENSITIVITY REGISTER

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
LVL11 LVL10 LVL9 LVL8
7:0
LVL7 LVL6 LVL5 LVL4 LVL3 LVL2 LVL1 LVL0
Legend:

bit 11-0 LVL11:LVL0: Trigger Level and Edge Sensitivity bits
1 = Analog input is sensitive to the high level of its trigger (level sensitivity implies retriggering as long as
the trigger signal remains high)
0 = Analog input is sensitive to the positive edge of its trigger (this is the value after a reset)
Note 1: This register specifies the trigger level for analog inputs 0 to 11.
2: The higher analog input ID belongs to Class 3, and therefore, is only scan triggered. All Class 3 analog
inputs use the Scan Trigger, for which the level/edge is defined by the STRGLVL bit (ADCCON1<3>).

REGISTER 29-27: ADCxTIME: DEDICATED ADCx TIMING REGISTER (x = 0 THROUGH 4)

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
31:24
ADCEIS<2:0> SELRES<1:0>
23:16
ADCDIV<6:0>
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
SAMC<9:8>
7:0
SAMC<7:0>
Legend:

bit 28-26 ADCEIS<2:0>: ADCx Early Interrupt Select bits
111 = The data ready interrupt is generated 8 ADC clocks prior to the end of conversion

000 = The data ready interrupt is generated 1 ADC clock prior to the end of conversion
Note: All options are available when the selected resolution, specified by the SELRES<1:0> bits
(ADCxTIME<25:24>), is 12-bit or 10-bit. For a selected resolution of 8-bit, options from 000
to 101 are valid. For a selected resolution of 6-bit, options from 000 to 011 are valid.
bit 25-24 SELRES<1:0>: ADCx Resolution Select bits
11 = 12 bits
10 = 10 bits
01 = 8 bits
00 = 6 bits
Note: Changing the resolution of the ADC does not shift the result in the corresponding ADCDATAx
register. The result will still occupy 12 bits, with the corresponding lower unused bits set to 0.
For example, a resolution of 6 bits will result in ADCDATAx<5:0> being set to 0, and
ADCDATAx<11:6> holding the result.
bit 22-16 ADCDIV<6:0>: ADCx Clock Divisor bits
These bits divide the ADC control clock with period TQ to generate the clock for ADCx (TADx).
1111111 = 254 * TQ = TADx

0000011 = 6 * TQ = TADx
0000010 = 4 * TQ = TADx
0000001 = 2 * TQ = TADx
0000000 = Reserved
bit 9-0 SAMC<9:0>: ADCx Sample Time bits
Where TADx = period of the ADC conversion clock for the dedicated ADC controlled by the ADCDIV<6:0>
bits.
1111111111 = 1025 TADx

0000000001 = 3 TADx
0000000000 = 2 TADx

REGISTER 29-28: ADCEIEN1: ADC EARLY INTERRUPT ENABLE REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
EIEN31 EIEN30 EIEN29 EIEN28 EIEN27 EIEN26 EIEN25 EIEN24
23:16
15:8
7:0
Legend: HS = Hardware Set C = Clearable bit

bit 31-0 EIEN31:EIEN0: Early Interrupt Enable for Analog Input bits
1 = Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early
interrupt event occurs (indicated by the EIRDYx bit ('x' = 31-0) of the ADCEISTAT1 register)
REGISTER 29-29: ADCEIEN2: ADC EARLY INTERRUPT ENABLE REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
EIEN43 EIEN42 EIEN41 EIEN40
7:0
Legend: HS = Hardware Set C = Clearable bit


bit 11-0 EIEN43:EIEN32: Early Interrupt Enable for Analog Input bits
1 = Early Interrupts are enabled for the selected analog input. The interrupt is generated after the early
interrupt event occurs (indicated by the EIRDYx bit ('x' = 43-32) of the ADCEISTAT2 register)

REGISTER 29-30: ADCEISTAT1: ADC EARLY INTERRUPT STATUS REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
EIRDY31 EIRDY30 EIRDY29 EIRDY28 EIRDY27 EIRDY26 EIRDY25 EIRDY24
23:16
15:8
7:0

bit 31-0 EIRDY31:EIRDY0: Early Interrupt for Corresponding Analog Input Ready bits
1 = This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be
generated if early interrupts are enabled in the ADCEIEN1 register. For the Class 1 analog inputs, this
bit will set as per the configuration of the ADCEIS<2:0> bits in the ADCxTIME register. For the shared
ADC module, this bit will be set as per the configuration of the ADCEIS<2:0> bits in the ADCCON2
register.

REGISTER 29-31: ADCEISTAT2: ADC EARLY INTERRUPT STATUS REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
15:8
EIRDY43 EIRDY42 EIRDY41 EIRDY40
7:0


bit 11-0 EIRDY43:EIRDY32: Early Interrupt for Corresponding Analog Input Ready bits
1 = This bit is set when the early interrupt event occurs for the specified analog input. An interrupt will be
generated if early interrupts are enabled in the ADCEIEN2 register. For the Class 1 analog inputs, this
bit will set as per the configuration of the ADCEIS<2:0> bits in the ADCxTIME register. For the shared
ADC module, this bit will be set as per the configuration of the ADCEIS<2:0> bits in the ADCCON2
register.

REGISTER 29-32: ADCANCON: ADC ANALOG WARM-UP CONTROL REGISTER

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
WKUPCLKCNT<3:0>
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
WKIEN7 WKIEN4 WKIEN3 WKIEN2 WKIEN1 WKIEN0
R-0, HS, HC U-0 U-0 R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC
15:8
WKRDY7 WKRDY4 WKRDY3 WKRDY2 WKRDY1 WKRDY0
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
ANEN7 ANEN4 ANEN3 ANEN2 ANEN1 ANEN0


bit 27-24 WKUPCLKCNT<3:0>: Wake-up Clock Count bits
These bits represent the number of ADC clocks required to warm-up the ADC module before it can
perform conversion. Although the clocks are specific to each ADC, the WKUPCLKCNT bit is common to
all ADC modules.
1111 = 215 = 32,768 clocks

0110 = 26 = 64 clocks
0101 = 25 = 32 clocks
0100 = 24 = 16 clocks
0011 = 24 = 16 clocks
0010 = 24 = 16 clocks
0001 = 24 = 16 clocks
0000 = 24 = 16 clocks
bit 23 WKIEN7: Shared ADC (ADC7) Wake-up Interrupt Enable bit
1 = Enable interrupt and generate interrupt when the WKRDY7 status bit is set
0 = Disable interrupt
bit 20-16 WKIEN4:WKIEN0: ADC4-ADC0 Wake-up Interrupt Enable bit
1 = Enable interrupt and generate interrupt when the WKRDYx status bit is set
0 = Disable interrupt
bit 15 WKRDY7: Shared ADC (ADC7) Wake-up Status bit
1 = ADC7 Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting
ANEN7 to 1
0 = ADC7 Analog and Bias circuitry is not ready
Note: This bit is cleared by hardware when the ANEN7 bit is cleared
bit 12-8 WKRDY4:WKRDY0: ADC4-ADC0 Wake-up Status bit
1 = ADCx Analog and Bias circuitry ready after the wake-up count number 2WKUPEXP clocks after setting
ANENx to 1
0 = ADCx Analog and Bias circuitry is not ready
Note: These bits are cleared by hardware when the ANENx bit is cleared

REGISTER 29-32: ADCANCON: ADC ANALOG WARM-UP CONTROL REGISTER (CONTINUED)
bit 7 ANEN7: Shared ADC (ADC7) Analog and Bias Circuitry Enable bit
1 = Analog and bias circuitry enabled. Once the analog and bias circuit is enabled, the ADC module needs
a warm-up time, as defined by the WKUPCLKCNT<3:0> bits.
0 = Analog and bias circuitry disabled
bit 4-0 ANEN4:ANEN0: ADC4-ADC0 Analog and Bias Circuitry Enable bits
1 = Analog and bias circuitry enabled. Once the analog and bias circuit is enabled, the ADC module needs
a warm-up time, as defined by the WKUPCLKCNT<3:0> bits.
0 = Analog and bias circuitry disabled

REGISTER 29-33: ADCxCFG: ADCx CONFIGURATION REGISTER (x = 1 THROUGH 4 AND 7)

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
ADCCFG<31:24>
23:16
ADCCFG<23:16>
15:8
ADCCFG<15:8>
7:0
ADCCFG<7:0>
Legend:
bit 31-0 ADCCFG<31:0>: ADC Module Configuration Data bits

Prior to enabling the ADC, these registers should be written with the corresponding value stored in
DEVADCx in software during ADC initialization.
Note: These bits can only change when the applicable ANENx bit in the ADCANCON register is cleared. These
are calibration values determined at product test time and are provided to the user through DEVADCx fuse
bits (see Register 41-8).

REGISTER 29-34: ADCSYSCFG1: ADC SYSTEM CONFIGURATION REGISTER 1

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0, HC, HS R-0, HC, HS R-0, HC, HS R-0, HC, HS R-0, HC, HS R-0, HC, HS R-0, HC, HS R-0, HC, HS
31:24
AN<31:23>
23:16
AN<23:16>
15:8
AN<15:8>
7:0
AN<7:0>

bit 31-0 AN<31:0>: ADC Analog Input bits

These bits reflect the system configuration and are updated during boot-up time. By reading these read-
only bits, the user application can determine whether or not an analog input in the device is available.
REGISTER 29-35: ADCSYSCFG2: ADC SYSTEM CONFIGURATION REGISTER 2

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R-0, HC, HS R-0, HC, HS R-0, HC, HS R-0, HC, HS
15:8
AN<43:40>
7:0
AN<39:32>
Legend: HS = Hardware Set HC = Cleared by Software


bit 12-0 AN<43:32>: ADC Analog Input bits
These bits reflect the system configuration and are updated during boot-up time. By reading these read-
only bits, the user application can determine whether or not an analog input in the device is available.

30.0 CONTROLLER AREA - FIFO can be a transmit message FIFO or a
receive message FIFO
NETWORK (CAN)
- User-defined priority levels for message
Note: This data sheet summarizes the FIFOs used for transmission
features of the PIC32MZ Graphics (DA) - 32 acceptance filters for message filtering
Family of devices. It is not intended to - Four acceptance filter mask registers for
be a comprehensive reference source. message filtering
To complement the information in this
- Automatic response to remote transmit request
data sheet, refer to Section 34.
Controller Area Network (CAN) - DeviceNet addressing support
(DS60001154), which is available from Additional Features:
the Documentation > Reference Manual - Loopback, Listen All Messages and Listen
section of the Microchip PIC32 web site Only modes for self-test, system diagnostics
(www.microchip.com/pic32). and bus monitoring
- Low-power operating modes
The Controller Area Network (CAN) module supports
the following key features: - CAN module is a bus master on the PIC32
System Bus
Standards Compliance:
- Use of DMA is not required
- Full CAN 2.0B compliance
- Dedicated time-stamp timer
- Programmable bit rate up to 1 Mbps
- Dedicated DMA channels
Message Reception and Transmission:
- Data-only Message Reception mode
- 32 message FIFOs
Figure 30-1 illustrates the general structure of the CAN
- Each FIFO can have up to 32 messages for a
module.
total of 1024 messages
FIGURE 30-1: PIC32 CAN MODULE BLOCK DIAGRAM
CxTX
PBCLK5
32 Filters
(x = 1-2) 4 Masks
CxRX CPU
CAN Module
System Bus
Message
Buffer Size
System RAM 2 or 4 Words
Up to 32 Message Buffers
Message Buffer 31 Message Buffer 31 Message Buffer 31

FIFO0 FIFO1 FIFO31
CAN Message FIFO (up to 32 FIFOs)

DS60001361E-page 484
30.1 CAN Control Registers

Note: The i shown in register names denotes
CAN1 or CAN2.
TABLE 30-1: CAN1 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 ABAT REQOP<2:0> OPMOD<2:0> CANCAP 0480

0000 C1CON
15:0 ON SIDLE CANBUSY DNCNT<4:0> 0000
31:16 WAKFIL SEG2PH<2:0> 0000
0010 C1CFG
15:0 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> SJW<1:0> BRP<5:0> 0000
31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE MODIE CTMRIE RBIE TBIE 0000
0020 C1INT
15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF MODIF CTMRIF RBIF TBIF 0000
31:16 0000
0030 C1VEC
15:0 FILHIT<4:0> ICODE<6:0> 0040
31:16 TXBO TXBP RXBP TXWARN RXWARN EWARN 0000
0040 C1TREC
15:0 TERRCNT<7:0> RERRCNT<7:0> 0000
31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
0050 C1FSTAT
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
0060 C1RXOVF
31:16 CANTS<15:0> 0000
0070 C1TMR
15:0 CANTSPRE<15:0> 0000
31:16 SID<10:0> - MIDE EID<17:16> xxxx
0080 C1RXM0
15:0 EID<15:0> xxxx
31:16 SID<10:0> - MIDE EID<17:16> xxxx
0090 C1RXM1
15:0 EID<15:0> xxxx
31:16 SID<10:0> - MIDE EID<17:16> xxxx

00A0 C1RXM2
15:0 EID<15:0> xxxx
31:16 SID<10:0> - MIDE EID<17:16> xxxx
00B0 C1RXM3
15:0 EID<15:0> xxxx
31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000
00C0 C1FLTCON0
00D0 C1FLTCON1
00E0 C1FLTCON2
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for more
information.
TABLE 30-1: CAN1 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES (CONTINUED)
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

00F0 C1FLTCON3
0100 C1FLTCON4
0110 C1FLTCON5
0120 C1FLTCON6
0130 C1FLTCON7
0140- C1RXFn 31:16 SID<10:0> - EXID EID<17:16> xxxx

0330 (n = 0-31) 15:0 EID<15:0> xxxx
31:16 0000
0340 C1FIFOBA C1FIFOBA<31:0>
15:0 0000
C1FIFOCONn 31:16 FSIZE<4:0> 0000
0350
(n = 0) 15:0 FRESET UINC DONLY TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
RXN
31:16 TXNFULLIE TXHALFIE TXEMPTYIE RXOVFLIE RXFULLIE RXHALFIE 0000
C1FIFOINTn EMPTYIE
0360
(n = 0) RXN
15:0 TXNFULLIF TXHALFIF TXEMPTYIF RXOVFLIF RXFULLIF RXHALFIF 0000
EMPTYIF
C1FIFOUAn 31:16 0000
0370 C1FIFOUA<31:0>
(n = 0) 15:0 0000
C1FIFOCIn 31:16 0000
0380
(n = 0) 15:0 C1FIFOCI<4:0> 0000
31:16 FSIZE<4:0> 0000
15:0 FRESET UINC DONLY TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
RXN
31:16 TXNFULLIE TXHALFIE TXEMPTYIE RXOVFLIE RXFULLIE RXHALFIE 0000
C1FIFOCONn EMPTYIE
C1FIFOINTn RXN
0390-
C1FIFOUAn 15:0 TXNFULLIF TXHALFIF TXEMPTYIF RXOVFLIF RXFULLIF RXHALFIF
EMPTYIF
0000
0B40
C1FIFOCIn
(n = 1-31) 31:16 C1FIFOUA<31:0>
0000
15:0 0000
DS60001361E-page 485
31:16 0000
15:0 C1FIFOCI<4:0> 0000
information.
DS60001361E-page 486

TABLE 30-2: CAN2 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES
Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 ABAT REQOP<2:0> OPMOD<2:0> CANCAP 0480

1000 C2CON
15:0 ON SIDLE CANBUSY DNCNT<4:0> 0000
31:16 WAKFIL SEG2PH<2:0> 0000
1010 C2CFG
15:0 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> SJW<1:0> BRP<5:0> 0000
31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE MODIE CTMRIE RBIE TBIE 0000
1020 C2INT
15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF MODIF CTMRIF RBIF TBIF 0000
31:16 0000
1030 C2VEC
15:0 FILHIT<4:0> ICODE<6:0> 0040
31:16 TXBO TXBP RXBP TXWARN RXWARN EWARN 0000
1040 C2TREC
15:0 TERRCNT<7:0> RERRCNT<7:0> 0000
1050 C2FSTAT
1060 C2RXOVF
31:16 CANTS<15:0> 0000
1070 C2TMR
15:0 CANTSPRE<15:0> 0000
31:16 SID<10:0> - MIDE EID<17:16> xxxx
1080 C2RXM0
15:0 EID<15:0> xxxx
31:16 SID<10:0> - MIDE EID<17:16> xxxx
10A0 C2RXM1
15:0 EID<15:0> xxxx
31:16 SID<10:0> - MIDE EID<17:16> xxxx
10B0 C2RXM2
15:0 EID<15:0> xxxx
31:16 SID<10:0> - MIDE EID<17:16> xxxx
10B0 C2RXM3
15:0 EID<15:0> xxxx
31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0>
0000
1010 C2FLTCON0
10D0 C2FLTCON1
10E0 C2FLTCON2
10F0 C2FLTCON3
information.
TABLE 30-2: CAN2 REGISTER SUMMARY FOR PIC32MZXXXXECF AND PIC32MZXXXXECH DEVICES (CONTINUED)
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

1100 C2FLTCON4
15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0: 0000
1110 C2FLTCON5
1120 C2FLTCON6
1130 C2FLTCON7
1140- C2RXFn 31:16 SID<10:0> - EXID EID<17:16> xxxx
1330 (n = 0-31) 15:0 EID<15:0> xxxx

31:16 0000
1340 C2FIFOBA C2FIFOBA<31:0>
15:0 0000
C2FIFOCONn 31:16 FSIZE<4:0> 0000
1350
(n = 0) 15:0 FRESET UINC DONLY TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
RXN 0000
31:16 TXNFULLIE TXHALFIE TXEMPTYIE RXOVFLIE RXFULLIE RXHALFIE
C2FIFOINTn EMPTYIE
1360
(n = 0) RXN 0000
15:0 TXNFULLIF TXHALFIF TXEMPTYIF RXOVFLIF RXFULLIF RXHALFIF
EMPTYIF
C2FIFOUAn 31:16 0000
1370 C2FIFOUA<31:0>
(n = 0) 15:0 0000
C2FIFOCIn 31:16 0000
1380
(n = 0) 15:0 C2FIFOCI<4:0> 0000
31:16 FSIZE<4:0> 0000
15:0 FRESET UINC DONLY TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
RXN 0000
31:16 TXNFULLIE TXHALFIE TXEMPTYIE RXOVFLIE RXFULLIE RXHALFIE
C2FIFOCONn EMPTYIE
C2FIFOINTn RXN 0000
1390-
C2FIFOUAn 15:0 TXNFULLIF TXHALFIF TXEMPTYIF RXOVFLIF RXFULLIF RXHALFIF
EMPTYIF
1B40
C2FIFOCIn
(n = 1-31) 31:16 C2FIFOUA<31:0>
0000
15:0 0000
DS60001361E-page 487
31:16 0000
15:0 C2FIFOCI<4:0> 0000
information.
REGISTER 30-1: CiCON: CAN MODULE CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 S/HC-0 R/W-1 R/W-0 R/W-0
31:24
ABAT REQOP<2:0>
R-1 R-0 R-0 R/W-0 U-0 U-0 U-0 U-0
23:16
OPMOD<2:0> CANCAP
R/W-0 U-0 R/W-0 U-0 R-0 U-0 U-0 U-0
15:8
ON(1) SIDLE CANBUSY
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
DNCNT<4:0>
Legend: HC = Hardware Clear S = Settable bit

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit
U = Unimplemented bit -n = Bit Value at POR: (0, 1, x = Unknown)

bit 27 ABAT: Abort All Pending Transmissions bit
1 = Signal all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions aborted
bit 26-24 REQOP<2:0>: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved - Do not use
101 = Reserved - Do not use
100 = Set Configuration mode
011 = Set Listen Only mode
010 = Set Loopback mode
001 = Set Disable mode
000 = Set Normal Operation mode
bit 23-21 OPMOD<2:0>: Operation Mode Status bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit
1 = CANTMR value is stored on valid message reception and is stored with the message
0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power
bit 15 ON: CAN On bit(1)
1 = CAN module is enabled
0 = CAN module is disabled
Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.

REGISTER 30-1: CiCON: CAN MODULE CONTROL REGISTER (CONTINUED)
bit 13 SIDLE: CAN Stop in Idle bit
1 = CAN Stops operation when system enters Idle mode
0 = CAN continues operation when system enters Idle mode
bit 11 CANBUSY: CAN Module is Busy bit
1 = The CAN module is active
0 = The CAN module is completely disabled
bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits
10011-11111 = Invalid Selection (compare up to 18-bits of data with EID)
10010 = Compare up to data byte 2 bit 6 with EID17 (CiRXFn<17>)

00001 = Compare up to data byte 0 bit 7 with EID0 (CiRXFn<0>)
00000 = Do not compare data bytes
Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.

REGISTER 30-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
23:16
WAKFIL SEG2PH<2:0>(1,4)
15:8 (1) (2)
SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0>
7:0 (3)
SJW<1:0> BRP<5:0>
Legend: HC = Hardware Clear S = Settable bit

R = Readable bit W = Writable bit P = Programmable bit r = Reserved bit
U = Unimplemented bit -n = Bit Value at POR: (0, 1, x = Unknown)

bit 22 WAKFIL: CAN Bus Line Filter Enable bit
1 = Use CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits(1,4)
111 = Length is 8 x TQ

bit 15 SEG2PHTS: Phase Segment 2 Time Select bit(1)
1 = Freely programmable
0 = Maximum of SEG1PH or Information Processing Time, whichever is greater
bit 14 SAM: Sample of the CAN Bus Line bit(2)
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits(4)

Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.

2: 3 Time bit sampling is not allowed for BRP < 2.
3: SJW SEG2PH.
4: The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).
Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).

REGISTER 30-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED)
bit 10-8 PRSEG<2:0>: Propagation Time Segment bits(4)

bit 7-6 SJW<1:0>: Synchronization Jump Width bits(3)
bit 5-0 BRP<5:0>: Baud Rate Prescaler bits
111111 = TQ = (2 x 64)/TPBCLK5
111110 = TQ = (2 x 63)/TPBCLK5

000001 = TQ = (2 x 2)/TPBCLK5
000000 = TQ = (2 x 1)/TPBCLK5
Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.

2: 3 Time bit sampling is not allowed for BRP < 2.
3: SJW SEG2PH.
4: The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).
(CiCON<23:21>) = 100).

REGISTER 30-3: CiINT: CAN INTERRUPT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
31:24
IVRIE WAKIE CERRIE SERRIE RBOVIE
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
MODIE CTMRIE RBIE TBIE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
15:8 (1)
IVRIF WAKIF CERRIF SERRIF RBOVIF
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
MODIF CTMRIF RBIF TBIF
Legend:
bit 31 IVRIE: Invalid Message Received Interrupt Enable bit

1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 30 WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit
bit 29 CERRIE: CAN Bus Error Interrupt Enable bit
bit 28 SERRIE: System Error Interrupt Enable bit
bit 27 RBOVIE: Receive Buffer Overflow Interrupt Enable bit
bit 19 MODIE: Mode Change Interrupt Enable bit
bit 18 CTMRIE: CAN Timestamp Timer Interrupt Enable bit
bit 17 RBIE: Receive Buffer Interrupt Enable bit
bit 16 TBIE: Transmit Buffer Interrupt Enable bit
bit 15 IVRIF: Invalid Message Received Interrupt Flag bit
1 = An invalid messages interrupt has occurred
0 = An invalid message interrupt has not occurred
Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON<15>).

REGISTER 30-3: CiINT: CAN INTERRUPT REGISTER (CONTINUED)
bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit
1 = A bus wake-up activity interrupt has occurred
0 = A bus wake-up activity interrupt has not occurred
bit 13 CERRIF: CAN Bus Error Interrupt Flag bit
1 = A CAN bus error has occurred
0 = A CAN bus error has not occurred
bit 12 SERRIF: System Error Interrupt Flag bit
1 = A system error occurred (typically an illegal address was presented to the System Bus)
0 = A system error has not occurred
bit 11 RBOVIF: Receive Buffer Overflow Interrupt Flag bit
1 = A receive buffer overflow has occurred
0 = A receive buffer overflow has not occurred
bit 3 MODIF: CAN Mode Change Interrupt Flag bit
1 = A CAN module mode change has occurred (OPMOD<2:0> has changed to reflect REQOP)
0 = A CAN module mode change has not occurred
bit 2 CTMRIF: CAN Timer Overflow Interrupt Flag bit
1 = A CAN timer (CANTMR) overflow has occurred
0 = A CAN timer (CANTMR) overflow has not occurred
bit 1 RBIF: Receive Buffer Interrupt Flag bit
1 = A receive buffer interrupt is pending
0 = A receive buffer interrupt is not pending
bit 0 TBIF: Transmit Buffer Interrupt Flag bit
1 = A transmit buffer interrupt is pending
0 = A transmit buffer interrupt is not pending
Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON<15>).

REGISTER 30-4: CiVEC: CAN INTERRUPT CODE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
15:8
FILHIT<4:0>
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
7:0 (1)
ICODE<6:0>
Legend:

bit 12-8 FILHIT<4:0>: Filter Hit Number bit
11111 = Filter 31
11110 = Filter 30

00001 = Filter 1
00000 = Filter 0
bit 6-0 ICODE<6:0>: Interrupt Flag Code bits(1)
1001000-1111111 = Reserved
1001000 = Invalid message received (IVRIF)
1000111 = CAN module mode change (MODIF)
1000110 = CAN timestamp timer (CTMRIF)
1000101 = Bus bandwidth error (SERRIF)
1000100 = Address error interrupt (SERRIF)
1000011 = Receive FIFO overflow interrupt (RBOVIF)
1000010 = Wake-up interrupt (WAKIF)
1000001 = Error Interrupt (CERRIF)
1000000 = No interrupt
0100000-0111111 = Reserved
0011111 = FIFO31 Interrupt (CiFSTAT<31> set)

Note 1: These bits are only updated for enabled interrupts.

REGISTER 30-5: CiTREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
TXBO TXBP RXBP TXWARN RXWARN EWARN
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
TERRCNT<7:0>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
RERRCNT<7:0>
Legend:

bit 21 TXBO: Transmitter in Error State Bus OFF (TERRCNT 256)
bit 20 TXBP: Transmitter in Error State Bus Passive (TERRCNT 128)
bit 19 RXBP: Receiver in Error State Bus Passive (RERRCNT 128)
bit 18 TXWARN: Transmitter in Error State Warning (128 > TERRCNT 96)
bit 17 RXWARN: Receiver in Error State Warning (128 > RERRCNT 96)
bit 16 EWARN: Transmitter or Receiver is in Error State Warning
bit 15-8 TERRCNT<7:0>: Transmit Error Counter
bit 7-0 RERRCNT<7:0>: Receive Error Counter
REGISTER 30-6: CiFSTAT: CAN FIFO STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
Legend:
bit 31-0 FIFOIP<31:0>: FIFOn Interrupt Pending bits

1 = One or more enabled FIFO interrupts are pending
0 = No FIFO interrupts are pending

REGISTER 30-7: CiRXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
Legend:
bit 31-0 RXOVF<31:0>: FIFOn Receive Overflow Interrupt Pending bit

1 = FIFO has overflowed
0 = FIFO has not overflowed
REGISTER 30-8: CiTMR: CAN TIMER REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
CANTS<15:8>
23:16
CANTS<7:0>
15:8
CANTSPRE<15:8>
7:0
CANTSPRE<7:0>
Legend:
bit 31-0 CANTS<15:0>: CAN Time Stamp Timer bits

This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit
(CiCON<20>) is set.
bit 15-0 CANTSPRE<15:0>: CAN Time Stamp Timer Prescaler bits
1111 1111 1111 1111 = CAN time stamp timer (CANTS) increments every 65,535 system clocks

0000 0000 0000 0000 = CAN time stamp timer (CANTS) increments every system clock
Note 1: CiTMR will be frozen when CANCAP = 0.

2: The CiTMR prescaler count will be reset on any write to CiTMR (CANTSPRE will be unaffected).

REGISTER 30-9: CiRXMN: CAN ACCEPTANCE FILTER MASK N REGISTER (N = 0, 1, 2 OR 3)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
SID<10:3>
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
23:16
SID<2:0> MIDE EID<17:16>
15:8
EID<15:8>
7:0
EID<7:0>
Legend:
bit 31-21 SID<10:0>: Standard Identifier bits

1 = Include bit, SIDx, in filter comparison
0 = Bit SIDx is dont care in filter operation
bit 19 MIDE: Identifier Receive Mode bit
1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter
0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message
SID) or if (FILTER SID/EID) = (Message SID/EID))
bit 17-0 EID<17:0>: Extended Identifier bits
1 = Include bit, EIDx, in filter comparison
0 = Bit EIDx is dont care in filter operation
(CiCON<23:21>) = 100).

REGISTER 30-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0

Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
FLTEN3 MSEL3<1:0> FSEL3<4:0>
23:16
15:8
7:0
Legend:
bit 31 FLTEN3: Filter 3 Enable bit

1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL3<1:0>: Filter 3 Mask Select bits
11 = Acceptance Mask 3 selected
bit 28-24 FSEL3<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31


Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is 0.

REGISTER 30-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED)




Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
23:16
15:8
7:0
Legend:








Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
23:16
15:8
7:0
Legend:








Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
23:16
15:8
7:0
Legend:







,4

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
23:16
15:8
7:0
Legend:








Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
23:16
15:8
7:0
Legend:








Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
23:16
15:8
7:0
Legend:








Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
23:16
15:8
7:0
Legend:


bit 23 FLTEN30: Filter 30Enable bit
bit 22-21 MSEL30<1:0>: Filter 30Mask Select bits





REGISTER 30-18: CiRXFn: CAN ACCEPTANCE FILTER N REGISTER 7 (n = 0 THROUGH 31)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
SID<10:3>
R/W-x R/W-x R/W-x U-0 R/W-0 U-0 R/W-x R/W-x
23:16
SID<2:0> EXID EID<17:16>
15:8
EID<15:8>
7:0
EID<7:0>
Legend:
bit 31-21 SID<10:0>: Standard Identifier bits

1 = Message address bit SIDx must be 1 to match filter
0 = Message address bit SIDx must be 0 to match filter
bit 19 EXID: Extended Identifier Enable bits
1 = Match only messages with extended identifier addresses
0 = Match only messages with standard identifier addresses
bit 17-0 EID<17:0>: Extended Identifier bits
1 = Message address bit EIDx must be 1 to match filter
0 = Message address bit EIDx must be 0 to match filter
Note: This register can only be modified when the filter is disabled (FLTENn = 0).

REGISTER 30-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
CiFIFOBA<31:24>
23:16
CiFIFOBA<23:16>
15:8
CiFIFOBA<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0(1) R-0(1)
7:0
CiFIFOBA<7:0>
Legend:
bit 31-0 CiFIFOBA<31:0>: CAN FIFO Base Address bits

These bits define the base address of all message buffers. Individual message buffers are located based
on the size of the previous message buffers. This address is a physical address. Note that bits <1:0> are
read-only and read 0, forcing the messages to be 32-bit word-aligned in device RAM.
Note 1: This bit is unimplemented and will always read 0, which forces word-alignment of messages.
(CiCON<23:21>) = 100).

REGISTER 30-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER (n = 0 THROUGH 31)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
FSIZE<4:0>(1)
U-0 S/HC-0 S/HC-0 R/W-0 U-0 U-0 U-0 U-0
15:8 (1)
FRESET UINC DONLY
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
TXEN TXABAT(2) TXLARB(3) TXERR(3) TXREQ RTREN TXPR<1:0>
Legend:

bit 20-16 FSIZE<4:0>: FIFO Size bits(1)
11111 = FIFO is 32 messages deep

00000 = FIFO is 1 message deep
bit 14 FRESET: FIFO Reset bits
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should
poll if this bit is clear before taking any action
0 = No effect
bit 13 UINC: Increment Head/Tail bit
TXEN = 1: (FIFO configured as a Transmit FIFO)
When this bit is set the FIFO head will increment by a single message
TXEN = 0: (FIFO configured as a Receive FIFO)
When this bit is set the FIFO tail will increment by a single message
bit 12 DONLY: Store Message Data Only bit(1)
This bit is not used and has no effect.
1 = Only data bytes will be stored in the FIFO
0 = Full message is stored, including identifier
bit 7 TXEN: TX/RX Buffer Selection bit
1 = FIFO is a Transmit FIFO
0 = FIFO is a Receive FIFO
Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:21>) = 100).
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the FIFO is reset.

REGISTER 30-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER (n = 0 THROUGH 31)
bit 6 TXABAT: Message Aborted bit(2)
1 = Message was aborted
0 = Message completed successfully
bit 5 TXLARB: Message Lost Arbitration bit(3)
1 = Message lost arbitration while being sent
0 = Message did not loose arbitration while being sent
bit 4 TXERR: Error Detected During Transmission bit(3)
1 = A bus error occured while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3 TXREQ: Message Send Request
Setting this bit to 1 requests sending a message.
The bit will automatically clear when all the messages queued in the FIFO are successfully sent
Clearing the bit to 0 while set (1) will request a message abort.
This bit has no effect.
bit 2 RTREN: Auto RTR Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
bit 1-0 TXPR<1:0>: Message Transmit Priority bits
11 = Highest Message Priority
10 = High Intermediate Message Priority
01 = Low Intermediate Message Priority
00 = Lowest Message Priority
Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:21>) = 100).
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the FIFO is reset.

REGISTER 30-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER (n = 0 THROUGH 31)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
TXNFULLIE TXHALFIE TXEMPTYIE
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
15:8
TXNFULLIF(1) TXHALFIF TXEMPTYIF(1)
U-0 U-0 U-0 U-0 R/W-0 R-0 R-0 R-0
7:0 (1) (1)
RXOVFLIF RXFULLIF RXHALFIF RXNEMPTYIF(1)
Legend:

bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit
1 = Interrupt enabled for FIFO not full
0 = Interrupt disabled for FIFO not full
bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO empty
0 = Interrupt disabled for FIFO empty
bit 19 RXOVFLIE: Overflow Interrupt Enable bit
1 = Interrupt enabled for overflow event
0 = Interrupt disabled for overflow event
bit 18 RXFULLIE: Full Interrupt Enable bit
1 = Interrupt enabled for FIFO full
0 = Interrupt disabled for FIFO full
bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 16 RXNEMPTYIE: Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO not empty
0 = Interrupt disabled for FIFO not empty
bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a Transmit Buffer)
1 = FIFO is not full
0 = FIFO is full
TXEN = 0: (FIFO configured as a Receive Buffer)
Unused, reads 0
Note 1: This bit is read-only and reflects the status of the FIFO.

REGISTER 30-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER (n = 0 THROUGH 31)
bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
1 = FIFO is half full
0 = FIFO is > half full
Unused, reads 0
bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1)
1 = FIFO is empty
0 = FIFO is not empty, at least 1 message queued to be transmitted
Unused, reads 0
bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit
Unused, reads 0
1 = Overflow event has occurred
0 = No overflow event occured
bit 2 RXFULLIF: Receive FIFO Full Interrupt Flag bit(1)
Unused, reads 0
1 = FIFO is full
0 = FIFO is not full
bit 1 RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1)
Unused, reads 0
1 = FIFO is half full
0 = FIFO is < half full
bit 0 RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit(1)
Unused, reads 0
1 = FIFO is not empty, has at least 1 message
0 = FIFO is empty
Note 1: This bit is read-only and reflects the status of the FIFO.

REGISTER 30-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER (n = 0 THROUGH 31)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
CiFIFOUAn<31:24>
23:16
CiFIFOUAn<23:16>
15:8
CiFIFOUAn<15:8>
R-x R-x R-x R-x R-x R-x R-0(1) R-0(1)
7:0
CiFIFOUAn<7:0>
Legend:
bit 31-0 CiFIFOUAn<31:0>: CAN FIFO User Address bits

A read of this register will return the address where the next message is to be written (FIFO head).
A read of this register will return the address where the next message is to be read (FIFO tail).
Note 1: This bit will always read 0, which forces byte-alignment of messages.
Note: This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when
the module is not in Configuration mode.
REGISTER 30-23: CiFIFOCIN: CAN MODULE MESSAGE INDEX REGISTER (n = 0 THROUGH 31)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
7:0
CiFIFOCI<4:0>
Legend:

bit 4-0 CiFIFOCIn<4:0>: CAN Side FIFO Message Index bits
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
A read of this register will return an index to the message that the FIFO will use to save the next message.

31.0 ETHERNET CONTROLLER Supports RMII and MII PHY interface
Supports MIIM PHY management interface
Note: This data sheet summarizes the features Supports both manual and automatic Flow Control
RAM descriptor-based DMA operation for both
receive and transmit path
complement the information in this data Fully configurable interrupts
sheet, refer to Section 35. Ethernet Configurable receive packet filtering
Controller (DS60001155), which is - CRC check
available from the Documentation > - 64-byte pattern match
- Broadcast, multicast and unicast packets
(www.microchip.com/pic32). - Magic Packet
- 64-bit hash table
The Ethernet controller is a bus master module that - Runt packet
interfaces with an off-chip Physical Layer (PHY) to
Supports packet payload checksum calculation
implement a complete Ethernet node in a system.
Supports various hardware statistics counters
Key features of the Ethernet Controller include:
Figure 31-1 illustrates a block diagram of the Ethernet
Supports 10/100 Mbps data transfer rates controller.
Supports full-duplex and half-duplex operation
FIGURE 31-1: ETHERNET CONTROLLER BLOCK DIAGRAM

FIFO
TX
TX DMA TX BM
TX Bus TX Function
Master
TX Flow Control
System Bus
MII/RMII
IF
RX Flow
Control
FIFO
RX
RX DMA RX BM
MAC External
PHY
RX Bus RX Filter RX Function
Master
Checksum MIIM
IF
Fast Peripheral Bus
DMA MAC Control

Control and
Registers Configuration
Ethernet DMA
Registers
Host IF
PBCLK5
Ethernet Controller

Table 31-1 and Table 31-2 show two interfaces and the
associated pins that can be used with the Ethernet
Controller.
TABLE 31-1: MII MODE DEFAULT

INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 1)
Pin Name Description
EMDC Management Clock
EMDIO Management I/O
ETXCLK Transmit Clock
ETXEN Transmit Enable
ETXD0 Transmit Data
ETXD1 Transmit Data
ETXD2 Transmit Data
ETXD3 Transmit Data
ETXERR Transmit Error
ERXCLK Receive Clock
ERXDV Receive Data Valid
ERXD0 Receive Data
ERXD1 Receive Data
ERXD2 Receive Data
ERXD3 Receive Data
ERXERR Receive Error
ECRS Carrier Sense
ECOL Collision Indication
TABLE 31-2: RMII MODE DEFAULT

INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 1)
Pin Name Description
EMDC Management Clock
EMDIO Management I/O
ETXEN Transmit Enable
ETXD0 Transmit Data
ETXD1 Transmit Data
EREFCLK Reference Clock
ECRSDV Carrier Sense Receive Data Valid
ERXD0 Receive Data
ERXD1 Receive Data
ERXERR Receive Error
Note: Ethernet controller pins that are not used

by selected interface can be used by
other peripherals.

31.1 Ethernet Control Registers
TABLE 31-3:
Virtual Address ETHERNET CONTROLLER REGISTER SUMMARY
Bits
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 PTV<15:0> 0000

2000 ETHCON1
15:0 ON SIDL TXRTS RXEN AUTOFC MANFC BUFCDEC 0000
31:16 0000
2010 ETHCON2
15:0 RXBUFSZ<6:0> 0000
31:16 TXSTADDR<31:16> 0000
2020 ETHTXST
15:0 TXSTADDR<15:2> 0000
31:16 RXSTADDR<31:16> 0000
2030 ETHRXST
15:0 RXSTADDR<15:2> 0000
31:16 0000
2040 ETHHT0 HT<31:0>

15:0 0000
31:16 0000
2050 ETHHT1 HT<63:32>
15:0 0000
31:16 0000
2060 ETHPMM0 PMM<31:0>
15:0 0000
31:16 0000
2070 ETHPMM1 PMM<63:32>
15:0 0000
31:16 0000
2080 ETHPMCS
15:0 PMCS<15:0> 0000
31:16 0000
2090 ETHPMO
15:0 PMO<15:0> 0000
31:16 0000
20A0 ETHRXFC CRC CRC RUNT NOT
15:0 HTEN MPEN NOTPM PMMODE<3:0> RUNTEN UCEN MCEN BCEN 0000
ERREN OKEN ERREN MEEN
31:16 RXFWM<7:0> 0000
20B0 ETHRXWM
15:0 RXEWM<7:0> 0000
31:16 0000
20C0 ETHIEN TX RX EW FW RX PK RX TX TX RX RX
15:0 0000
BUSEIE BUSEIE MARKIE MARKIE DONEIE TPENDIE ACTIE DONEIE ABORTIE BUFNAIE OVFLWIE
31:16 0000
20D0 ETHIRQ
15:0 TXBUSE RXBUSE EWMARK FWMARK RXDONE PKTPEND RXACT TXDONE TXABORT RXBUFNA RXOVFLW 0000
DS60001361E-page 523
31:16 BUFCNT<7:0> 0000

20E0 ETHSTAT
15:0 BUSY TXBUSY RXBUSY 0000
ETH 31:16 0000
2100
RXOVFLOW 15:0 RXOVFLWCNT<15:0> 0000
Note 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and
2: Reset values default to the factory programmed value.
DS60001361E-page 524
TABLE 31-3: ETHERNET CONTROLLER REGISTER SUMMARY (CONTINUED)

Virtual Address
Bits
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
ETH 31:16 0000

2110
FRMTXOK 15:0 FRMTXOKCNT<15:0> 0000
ETH 31:16 0000
2120
SCOLFRM 15:0 SCOLFRMCNT<15:0> 0000
ETH 31:16 0000
2130
MCOLFRM 15:0 MCOLFRMCNT<15:0> 0000
ETH 31:16 0000
2140
FRMRXOK 15:0 FRMRXOKCNT<15:0> 0000
ETH 31:16 0000
2150
FCSERR 15:0 FCSERRCNT<15:0> 0000
ETH 31:16 0000
2160
ALGNERR 15:0 ALGNERRCNT<15:0> 0000
31:16 0000
EMAC1
2200 SOFT SIM RESET RESET RESET RESET
CFG1 15:0 LOOPBACK TXPAUSE RXPAUSE PASSALL RXENABLE 800D
RESET RESET RMCS RFUN TMCS TFUN
31:16 0000
EMAC1
2210 EXCESS BP PAD CRC
CFG2 15:0 NOBKOFF LONGPRE PUREPRE AUTOPAD VLANPAD DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082
DFR NOBKOFF ENABLE ENABLE
EMAC1 31:16 0000
2220
IPGT 15:0 B2BIPKTGP<6:0> 0012
EMAC1 31:16 0000
2230
IPGR 15:0 NB2BIPKTGP1<6:0> NB2BIPKTGP2<6:0> 0C12
EMAC1 31:16 0000
2240
CLRT 15:0 CWINDOW<5:0> RETX<3:0> 370F
EMAC1 31:16 0000
2250
MAXF 15:0 MACMAXF<15:0> 05EE
31:16 0000
EMAC1
2260 RESET SPEED
SUPP 15:0 1000
RMII RMII
EMAC1 31:16 0000
2270
TEST 15:0 TESTBP TESTPAUSE SHRTQNTA 0000
31:16 0000
EMAC1
2280 RESET
MCFG 15:0 CLKSEL<3:0> NOPRE SCANINC 0020
MGMT
EMAC1 31:16 0000
2290
MCMD 15:0 SCAN READ 0000
EMAC1 31:16 0000
22A0
MADR 15:0 PHYADDR<4:0> REGADDR<4:0> 0100
TABLE 31-3: ETHERNET CONTROLLER REGISTER SUMMARY (CONTINUED)
All Resets
Bit Range
(BF88_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
EMAC1 31:16 0000

22B0
MWTD 15:0 MWTD<15:0> 0000
EMAC1 31:16 0000
22C0
MRDD 15:0 MRDD<15:0> 0000
EMAC1 31:16 0000
22D0
MIND 15:0 LINKFAIL NOTVALID SCAN MIIMBUSY 0000
EMAC1 31:16 xxxx
2300
SA0(2) 15:0 STNADDR6<7:0> STNADDR5<7:0> xxxx
EMAC1 31:16 xxxx
2310
EMAC1 31:16 xxxx
2320

DS60001361E-page 525
REGISTER 31-1: ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
PTV<15:8>
23:16
PTV<7:0>
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
ON SIDL TXRTS RXEN(1)
R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0
7:0
AUTOFC MANFC BUFCDEC
Legend:
bit 31-16 PTV<15:0>: PAUSE Timer Value bits

PAUSE Timer Value used for Flow Control.
This register should only be written when RXEN (ETHCON1<8>) is not set.
These bits are only used for Flow Control operations.
bit 15 ON: Ethernet ON bit
1 = Ethernet module is enabled
0 = Ethernet module is disabled
bit 13 SIDL: Ethernet Stop in Idle Mode bit
1 = Ethernet module transfers are paused during Idle mode
0 = Ethernet module transfers continue during Idle mode
bit 9 TXRTS: Transmit Request to Send bit
1 = Activate the TX logic and send the packet(s) defined in the TX EDT
0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)
After the bit is written with a 1, it will clear to a 0 whenever the transmit logic has finished transmitting
the requested packets in the Ethernet Descriptor Table (EDT). If a 0 is written by the CPU, the transmit
logic finishes the current packets transmission and then stops any further.
This bit only affects TX operations.
bit 8 RXEN: Receive Enable bit(1)
1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter
configuration
0 = Disable RX logic, no packets are received in the RX buffer
This bit only affects RX operations.
Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to 0), and then the RX changes applied.

REGISTER 31-1: ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED)
bit 7 AUTOFC: Automatic Flow Control bit
1 = Automatic Flow Control is enabled
0 = Automatic Flow Control is disabled
Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used to
automatically enable and disable the Flow Control, respectively. When the number of received buffers
BUFCNT (ETHSTAT<16:23>) rises to the full watermark, Flow Control is automatically enabled. When
the BUFCNT falls to the empty watermark, Flow Control is automatically disabled.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 4 MANFC: Manual Flow Control bit
1 = Manual Flow Control is enabled
0 = Manual Flow Control is disabled
Setting this bit will enable manual Flow Control. If set, the Flow Control logic will send a PAUSE frame
using the PAUSE timer value in the PTV register. It will then resend a PAUSE frame every 128 *
PTV<15:0>/2 TX clock cycles until the bit is cleared.
Note: For 10 Mbps operation, TX clock runs at 2.5 MHz. For 100 Mbps operation, TX clock runs at
25 MHz.
When this bit is cleared, the Flow Control logic will automatically send a PAUSE frame with a 0x0000
PAUSE timer value to disable Flow Control.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 0 BUFCDEC: Descriptor Buffer Count Decrement bit
The BUFCDEC bit is a write-1 bit that reads as 0. When written with a 1, the Descriptor Buffer Counter,
BUFCNT, will decrement by one. If BUFCNT is incremented by the RX logic at the same time that this bit
is written, the BUFCNT value will remain unchanged. Writing a 0 will have no effect.
This bit is only used for RX operations.
Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to 0), and then the RX changes applied.

REGISTER 31-2: ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
RXBUFSZ<6:4>
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
7:0
RXBUFSZ<3:0>
Legend:

bit 10-4 RXBUFSZ<6:0>: RX Data Buffer Size for All RX Descriptors (in 16-byte increments) bits
1111111 = RX data Buffer size for descriptors is 2032 bytes


0000000 = Reserved
Note 1: This register is only used for RX operations.

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.

REGISTER 31-3: ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START

ADDRESS REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
TXSTADDR<31:24>
23:16
TXSTADDR<23:16>
15:8
TXSTADDR<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
7:0
TXSTADDR<7:2>
Legend:
bit 31-2 TXSTADDR<31:2>: Starting Address of First Transmit Descriptor bits

This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be 00).
Note 1: This register is only used for TX operations.

2: This register will be updated by hardware with the last descriptor used by the last successfully transmitted
packet.
REGISTER 31-4: ETHRXST: ETHERNET CONTROLLER RX PACKET DESCRIPTOR START

ADDRESS REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
RXSTADDR<31:24>
23:16
RXSTADDR<23:16>
15:8
RXSTADDR<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
7:0
RXSTADDR<7:2>
Legend:
bit 31-2 RXSTADDR<31:2>: Starting Address of First Receive Descriptor bits

This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be 00).

2: This register will be updated by hardware with the last descriptor used by the last successfully transmitted
packet.

REGISTER 31-5: ETHHT0: ETHERNET CONTROLLER HASH TABLE 0 REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
HT<31:24>
23:16
HT<23:16>
15:8
HT<15:8>
7:0
HT<7:0>
Legend:
bit 31-0 HT<31:0>: Hash Table Bytes 0-3 bits

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit
(ETHRXFC<15>) = 0.
REGISTER 31-6: ETHHT1: ETHERNET CONTROLLER HASH TABLE 1 REGISTER

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
HT<63:56>
23:16
HT<55:48>
15:8
HT<47:40>
7:0
HT<39:32>
Legend:
bit 31-0 HT<63:32>: Hash Table Bytes 4-7 bits

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit
(ETHRXFC<15>) = 0.

REGISTER 31-7: ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
PMM<31:24>
23:16
PMM<23:16>
15:8
PMM<15:8>
7:0
PMM<7:0>
Legend:
bit 31-24 PMM<31:24>: Pattern Match Mask 3 bits


2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit
(ETHRXFC<11:8>) = 0.
REGISTER 31-8: ETHPMM1: ETHERNET CONTROLLER PATTERN MATCH MASK 1 REGISTER

Bit Range Bit
24/16/8/0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

31:24
PMM<63:56>
23:16
PMM<55:48>
15:8
PMM<47:40>
7:0
PMM<39:32>
Legend:


(ETHRXFC<11:8>) = 0.

REGISTER 31-9: ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM

REGISTER
Bit Range Bit
24/16/8/0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
PMCS<15:8>
7:0
PMCS<7:0>
Legend:

bit 15-8 PMCS<15:8>: Pattern Match Checksum 1 bits
bit 7-0 PMCS<7:0>: Pattern Match Checksum 0 bits

(ETHRXFC<11:8>) = 0.
REGISTER 31-10: ETHPMO: ETHERNET CONTROLLER PATTERN MATCH OFFSET REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
PMO<15:8>
7:0
PMO<7:0>
Legend:

bit 15-0 PMO<15:0>: Pattern Match Offset 1 bits

(ETHRXFC<11:8>) = 0.

REGISTER 31-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
HTEN MPEN NOTPM PMMODE<3:0>
7:0
CRCERREN CRCOKEN RUNTERREN RUNTEN UCEN NOTMEEN MCEN BCEN
Legend:

bit 15 HTEN: Enable Hash Table Filtering bit
1 = Enable Hash Table Filtering
0 = Disable Hash Table Filtering
bit 14 MPEN: Magic Packet Enable bit
1 = Enable Magic Packet Filtering
0 = Disable Magic Packet Filtering
bit 12 NOTPM: Pattern Match Inversion bit
1 = The Pattern Match Checksum must not match for a successful Pattern Match to occur
0 = The Pattern Match Checksum must match for a successful Pattern Match to occur
This bit determines whether Pattern Match Checksum must match in order for a successful Pattern Match
to occur.
bit 11-8 PMMODE<3:0>: Pattern Match Mode bits
1001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Packet = Magic Packet)(1,3)
(Hash Table Filter match)(1,1)
(Destination Address = Broadcast Address)(1)
(Destination Address = Broadcast Address)(1)
(Destination Address = Unicast Address)(1)
(Destination Address = Unicast Address)(1)
(Destination Address = Station Address)(1)
(Destination Address = Station Address)(1)
0001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches)(1)
0000 = Pattern Match is disabled; pattern match is always unsuccessful
Note 1: XOR = True when either one or the other conditions are true, but not both.
2: This Hash Table Filter match is active regardless of the value of the HTEN bit.
3: This Magic Packet Filter match is active regardless of the value of the MPEN bit.


REGISTER 31-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION
REGISTER (CONTINUED)
bit 7 CRCERREN: CRC Error Collection Enable bit
1 = The received packet CRC must be invalid for the packet to be accepted
0 = Disable CRC Error Collection filtering
This bit allows the user to collect all packets that have an invalid CRC.
bit 6 CRCOKEN: CRC OK Enable bit
1 = The received packet CRC must be valid for the packet to be accepted
0 = Disable CRC filtering
This bit allows the user to reject all packets that have an invalid CRC.
bit 5 RUNTERREN: Runt Error Collection Enable bit
1 = The received packet must be a runt packet for the packet to be accepted
0 = Disable Runt Error Collection filtering
This bit allows the user to collect all packets that are runt packets. For this filter, a runt packet is defined as
any packet with a size of less than 64 bytes (when CRCOKEN = 0) or any packet with a size of less than
64 bytes that has a valid CRC (when CRCOKEN = 1).
bit 4 RUNTEN: Runt Enable bit
1 = The received packet must not be a runt packet for the packet to be accepted
0 = Disable Runt filtering
This bit allows the user to reject all runt packets. For this filter, a runt packet is defined as any packet with a
size of less than 64 bytes.
bit 3 UCEN: Unicast Enable bit
1 = Enable Unicast Filtering
0 = Disable Unicast Filtering
This bit allows the user to accept all unicast packets whose Destination Address matches the Station
Address.
bit 2 NOTMEEN: Not Me Unicast Enable bit
1 = Enable Not Me Unicast Filtering
0 = Disable Not Me Unicast Filtering
This bit allows the user to accept all unicast packets whose Destination Address does not match the Station
Address.
bit 1 MCEN: Multicast Enable bit
1 = Enable Multicast Filtering
0 = Disable Multicast Filtering
This bit allows the user to accept all Multicast Address packets.
bit 0 BCEN: Broadcast Enable bit
1 = Enable Broadcast Filtering
0 = Disable Broadcast Filtering
This bit allows the user to accept all Broadcast Address packets.
Note 1: XOR = True when either one or the other conditions are true, but not both.
2: This Hash Table Filter match is active regardless of the value of the HTEN bit.
3: This Magic Packet Filter match is active regardless of the value of the MPEN bit.


REGISTER 31-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
RXFWM<7:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
RXEWM<7:0>
Legend:

bit 23-16 RXFWM<7:0>: Receive Full Watermark bits
The software controlled RX Buffer Full Watermark Pointer is compared against the RX BUFCNT to
determine the full watermark condition for the FWMARK interrupt and for enabling Flow Control when
automatic Flow Control is enabled. The Full Watermark Pointer should always be greater than the Empty
Watermark Pointer.
bit 7-0 RXEWM<7:0>: Receive Empty Watermark bits
The software controlled RX Buffer Empty Watermark Pointer is compared against the RX BUFCNT to
determine the empty watermark condition for the EWMARK interrupt and for disabling Flow Control when
automatic Flow Control is enabled. The Empty Watermark Pointer should always be less than the Full
Watermark Pointer.
Note: This register is only used for RX operations.

REGISTER 31-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
TXBUSEIE(1) RXBUSEIE(2) EWMARKIE(2) FWMARKIE(2)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RXDONEIE(2) PKTPENDIE(2) RXACTIE(2) TXDONEIE(1) TXABORTIE(1) RXBUFNAIE(2) RXOVFLWIE(2)
Legend:

bit 14 TXBUSEIE: Transmit BVCI Bus Error Interrupt Enable bit(1)
1 = Enable TXBUS Error Interrupt
0 = Disable TXBUS Error Interrupt
bit 13 RXBUSEIE: Receive BVCI Bus Error Interrupt Enable bit(2)
1 = Enable RXBUS Error Interrupt
0 = Disable RXBUS Error Interrupt
bit 9 EWMARKIE: Empty Watermark Interrupt Enable bit(2)
1 = Enable EWMARK Interrupt
0 = Disable EWMARK Interrupt
bit 8 FWMARKIE: Full Watermark Interrupt Enable bit(2)
1 = Enable FWMARK Interrupt
0 = Disable FWMARK Interrupt
bit 7 RXDONEIE: Receiver Done Interrupt Enable bit(2)
1 = Enable RXDONE Interrupt
0 = Disable RXDONE Interrupt
bit 6 PKTPENDIE: Packet Pending Interrupt Enable bit(2)
1 = Enable PKTPEND Interrupt
0 = Disable PKTPEND Interrupt
bit 5 RXACTIE: RX Activity Interrupt Enable bit(2)
1 = Enable RXACT Interrupt
0 = Disable RXACT Interrupt
bit 3 TXDONEIE: Transmitter Done Interrupt Enable bit(1)
1 = Enable TXDONE Interrupt
0 = Disable TXDONE Interrupt
bit 2 TXABORTIE: Transmitter Abort Interrupt Enable bit(1)
1 = Enable TXABORT Interrupt
0 = Disable TXABORT Interrupt
bit 1 RXBUFNAIE: Receive Buffer Not Available Interrupt Enable bit(2)
1 = Enable RXBUFNA Interrupt
0 = Disable RXBUFNA Interrupt
bit 0 RXOVFLWIE: Receive FIFO Overflow Interrupt Enable bit(2)
1 = Enable RXOVFLW Interrupt
0 = Disable RXOVFLW Interrupt
Note 1: This bit is only used for TX operations.

2: This bit is only used for RX operations.

REGISTER 31-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
TXBUSE RXBUSE EWMARK FWMARK
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RXDONE PKTPEND RXACT TXDONE TXABORT RXBUFNA RXOVFLW
Legend:

bit 14 TXBUSE: Transmit BVCI Bus Error Interrupt bit(2)
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the TX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a 1 to the CLR register.
bit 13 RXBUSE: Receive BVCI Bus Error Interrupt bit(2)
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the RX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a 1 to the CLR register.
bit 9 EWMARK: Empty Watermark Interrupt bit(2)
1 = Empty Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in the
RXEWM bit (ETHRXWM<0:7>) value. It is cleared by BUFCNT bit (ETHSTAT<16:23>)
being incremented by hardware. Writing a 0 or a 1 has no effect.
bit 8 FWMARK: Full Watermark Interrupt bit(2)
1 = Full Watermark pointer reached
This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the RXFWM
bit (ETHRXWM<16:23>) field. It is cleared by writing the BUFCDEC (ETHCON1<0>) bit to decrement
the BUFCNT counter. Writing a 0 or a 1 has no effect.

2: This bit is are only used for RX operations.
Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.

REGISTER 31-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
bit 7 RXDONE: Receive Done Interrupt bit(2)
1 = RX packet was successfully received
This bit is set whenever an RX packet is successfully received. It is cleared by either a Reset or CPU
write of a 1 to the CLR register.
bit 6 PKTPEND: Packet Pending Interrupt bit(2)
1 = RX packet pending in memory
0 = RX packet is not pending in memory
This bit is set when the BUFCNT counter has a value other than 0. It is cleared by either a Reset or by
writing the BUFCDEC bit to decrement the BUFCNT counter. Writing a 0 or a 1 has no effect.
bit 5 RXACT: Receive Activity Interrupt bit(2)
1 = RX packet data was successfully received
This bit is set whenever RX packet data is stored in the RXBM FIFO. It is cleared by either a Reset or
CPU write of a 1 to the CLR register.
bit 3 TXDONE: Transmit Done Interrupt bit(2)
1 = TX packet was successfully sent
This bit is set when the currently transmitted TX packet completes transmission, and the Transmit Status
Vector is loaded into the first descriptor used for the packet. It is cleared by either a Reset or CPU write
of a 1 to the CLR register.
bit 2 TXABORT: Transmit Abort Condition Interrupt bit(2)
1 = TX abort condition occurred on the last TX packet
This bit is set when the MAC aborts the transmission of a TX packet for one of the following reasons:
Jumbo TX packet abort
Underrun abort
Excessive defer abort
Late collision abort
Excessive collisions abort
This bit is cleared by either a Reset or CPU write of a 1 to the CLR register.
bit 1 RXBUFNA: Receive Buffer Not Available Interrupt bit(2)
1 = RX Buffer Descriptor Not Available condition has occurred
This bit is set by a RX Buffer Descriptor Overrun condition. It is cleared by either a Reset or a CPU write
of a 1 to the CLR register.
bit 0 RXOVFLW: Receive FIFO Over Flow Error bit(2)
1 = RX FIFO Overflow Error condition has occurred
RXOVFLW is set by the RXBM Logic for an RX FIFO Overflow condition. It is cleared by either a Reset
or CPU write of a 1 to the CLR register.

2: This bit is are only used for RX operations.
Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or

REGISTER 31-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
BUFCNT<7:0>(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
7:0
ETHBUSY(5) TXBUSY(2,6) RXBUSY(3,6)
Legend:

bit 23-16 BUFCNT<7:0>: Packet Buffer Count bits(1)
Number of packet buffers received in memory. Once a packet has been successfully received, this register
is incremented by hardware based on the number of descriptors used by the packet. Software decrements
the counter (by writing to the BUFCDEC bit (ETHCON1<0>) for each descriptor used) after a packet has
been read out of the buffer. The register does not roll over (0xFF to 0x00) when hardware tries to increment
the register and the register is already at 0xFF. Conversely, the register does not roll under (0x00 to 0xFF)
when software tries to decrement the register and the register is already at 0x0000. When software attempts
to decrement the counter at the same time that the hardware attempts to increment the counter, the counter
value will remain unchanged.
When this register value reaches 0xFF, the RX logic will halt (only if automatic Flow Control is enabled)
awaiting software to write the BUFCDEC bit in order to decrement the register below 0xFF.
If automatic Flow Control is disabled, the RXDMA will continue processing and the BUFCNT will saturate at
a value of 0xFF.
When this register is non-zero, the PKTPEND status bit will be set and an interrupt may be generated,
depending on the value of the ETHIEN bit <PKTPENDIE> register.
When the ETHRXST register is written, the BUFCNT counter is automatically cleared to 0x00.
Note: BUFCNT will not be cleared when ON is set to 0. This enables software to continue to utilize
and decrement this count.
bit 7 ETHBUSY: Ethernet Module busy bit(4,5)
1 = Ethernet logic has been turned on (ON (ETHCON1<15>) = 1) or is completing a transaction
0 = Ethernet logic is idle
This bit indicates that the module has been turned on or is completing a transaction after being turned off.
Note 1: This bit is only used for RX operations.

2: This bit is only affected by TX operations.
3: This bit is only affected by RX operations.
4: This bit is affected by TX and RX operations.
5: This bit will be set when the ON bit (ETHCON1<15>) = 1.
6: This bit will be cleared when the ON bit (ETHCON1<15>) = 0.

REGISTER 31-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED)
bit 6 TXBUSY: Transmit Busy bit(2,6)
1 = TX logic is receiving data
0 = TX logic is idle
This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarily
reflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC.
bit 5 RXBUSY: Receive Busy bit(3,6)
1 = RX logic is receiving data
0 = RX logic is idle
This bit indicates that a packet is currently being received. A change in this status bit is not necessarily
reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter.
Note 1: This bit is only used for RX operations.

2: This bit is only affected by TX operations.
3: This bit is only affected by RX operations.
4: This bit is affected by TX and RX operations.
5: This bit will be set when the ON bit (ETHCON1<15>) = 1.
6: This bit will be cleared when the ON bit (ETHCON1<15>) = 0.

REGISTER 31-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW STATISTICS

REGISTER
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
RXOVFLWCNT<15:8>
7:0
RXOVFLWCNT<7:0>
Legend:

bit 15-0 RXOVFLWCNT<15:0>: Dropped Receive Frames Count bits
Increment counter for frames accepted by the RX filter and subsequently dropped due to internal receive
error (RXFIFO overrun). This event also sets the RXOVFLW bit (ETHIRQ<0>) interrupt flag.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are 0.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or

REGISTER 31-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK

STATISTICS REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
FRMTXOKCNT<15:8>
7:0
FRMTXOKCNT<7:0>
Legend:

bit 15-0 FRMTXOKCNT<15:0>: Frame Transmitted OK Count bits
Increment counter for frames successfully transmitted.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are 0.

REGISTER 31-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES

STATISTICS REGISTER
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
SCOLFRMCNT<15:8>
7:0
SCOLFRMCNT<7:0>
Legend:

bit 15-0 SCOLFRMCNT<15:0>: Single Collision Frame Count bits
Increment count for frames that were successfully transmitted on the second try.

bytes 0/1 are 0.

REGISTER 31-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES

STATISTICS REGISTER
Bit Bit
Range Bit Bit Bit Bit Bit Bit Bit
24/16/8/0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
MCOLFRMCNT<15:8>
7:0
MCOLFRMCNT<7:0>
Legend:

bit 15-0 MCOLFRMCNT<15:0>: Multiple Collision Frame Count bits
Increment count for frames that were successfully transmitted after there was more than one collision.

0/1 are 0.

REGISTER 31-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK

STATISTICS REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
FRMRXOKCNT<15:8>
7:0
FRMRXOKCNT<7:0>
Legend:

bit 15-0 FRMRXOKCNT<15:0>: Frames Received OK Count bits
Increment count for frames received successfully by the RX Filter. This count will not be incremented if
there is a Frame Check Sequence (FCS) or Alignment error.

bytes 0/1 are 0.

REGISTER 31-21: ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR

STATISTICS REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
FCSERRCNT<15:8>
7:0
FCSERRCNT<7:0>
Legend:

bit 15-0 FCSERRCNT<15:0>: FCS Error Count bits
Increment count for frames received with FCS error and the frame length in bits is an integral multiple of
8 bits.

0/1 are 0.
clearing any bits in this register should be only done for debug/test purposes.

REGISTER 31-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
ALGNERRCNT<15:8>
7:0
ALGNERRCNT<7:0>
Legend:

bit 15-0 ALGNERRCNT<15:0>: Alignment Error Count bits
Increment count for frames with alignment errors. Note that an alignment error is a frame that has an FCS
error and the frame length in bits is not an integral multiple of 8 bits (a.k.a., dribble nibble)

0/1 are 0.
clearing any bits in this register should be only done for debug/test purposes.

REGISTER 31-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-1 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8 SOFT SIM RESET RESET RESET RESET

RESET RESET RMCS RFUN TMCS TFUN
U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1
7:0 TX RX RX
LOOPBACK PASSALL
PAUSE PAUSE ENABLE
Legend:

bit 15 SOFTRESET: Soft Reset bit
Setting this bit will put the MACMII in reset. Its default value is 1.
bit 14 SIMRESET: Simulation Reset bit
Setting this bit will cause a reset to the random number generator within the Transmit Function.
bit 11 RESETRMCS: Reset MCS/RX bit
Setting this bit will put the MAC Control Sub-layer/Receive domain logic in reset.
bit 10 RESETRFUN: Reset RX Function bit
Setting this bit will put the MAC Receive function logic in reset.
bit 9 RESETTMCS: Reset MCS/TX bit
Setting this bit will put the MAC Control Sub-layer/TX domain logic in reset.
bit 8 RESETTFUN: Reset TX Function bit
Setting this bit will put the MAC Transmit function logic in reset.
bit 4 LOOPBACK: MAC Loopback mode bit
1 = MAC Transmit interface is loop backed to the MAC Receive interface
0 = MAC normal operation
bit 3 TXPAUSE: MAC TX Flow Control bit
1 = PAUSE Flow Control frames are allowed to be transmitted
0 = PAUSE Flow Control frames are blocked
bit 2 RXPAUSE: MAC RX Flow Control bit
1 = The MAC acts upon received PAUSE Flow Control frames
0 = Received PAUSE Flow Control frames are ignored
bit 1 PASSALL: MAC Pass all Receive Frames bit
1 = The MAC will accept all frames regardless of type (Normal vs. Control)
0 = The received Control frames are ignored
bit 0 RXENABLE: MAC Receive Enable bit
1 = Enable the MAC receiving of frames
0 = Disable the MAC receiving of frames
Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 25/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
15:8 EXCESS BPNOBK NOBK
LONGPRE PUREPRE
DFR OFF OFF
7:0 AUTO VLAN PAD CRC
DELAYCRC HUGEFRM LENGTHCK FULLDPLX
PAD(1,2) PAD(1,2) ENABLE(1,3) ENABLE
Legend:

bit 14 EXCESSDER: Excess Defer bit
1 = The MAC will defer to carrier indefinitely as per the Standard
0 = The MAC will abort when the excessive deferral limit is reached
bit 13 BPNOBKOFF: Backpressure/No Backoff bit
1 = The MAC after incidentally causing a collision during backpressure will immediately retransmit without
backoff reducing the chance of further collisions and ensuring transmit packets get sent
0 = The MAC will not remove the backoff
bit 12 NOBKOFF: No Backoff bit
1 = Following a collision, the MAC will immediately retransmit rather than using the Binary Exponential Back-
off algorithm as specified in the Standard
0 = Following a collision, the MAC will use the Binary Exponential Backoff algorithm
bit 9 LONGPRE: Long Preamble Enforcement bit
1 = The MAC only allows receive packets which contain preamble fields less than 12 bytes in length
0 = The MAC allows any length preamble as per the Standard
bit 8 PUREPRE: Pure Preamble Enforcement bit
1 = The MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with
errors in its preamble is discarded
0 = The MAC does not perform any preamble checking
bit 7 AUTOPAD: Automatic Detect Pad Enable bit(1,2)
1 = The MAC will automatically detect the type of frame, either tagged or untagged, by comparing the two
octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly
0 = The MAC does not perform automatic detection
Note 1: Table 31-4 provides a description of the pad function based on the configuration of this register.
2: This bit is ignored if the PADENABLE bit is cleared.
3: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
8-bit accesses are not allowed and are ignored by the hardware

bit 6 VLANPAD: VLAN Pad Enable bit(1,2)
1 = The MAC will pad all short frames to 64 bytes and append a valid CRC
0 = The MAC does not perform padding of short frames
bit 5 PADENABLE: Pad/CRC Enable bit(1,3)
1 = The MAC will pad all short frames
0 = The frames presented to the MAC have a valid length
bit 4 CRCENABLE: CRC Enable1 bit
1 = The MAC will append a CRC to every frame whether padding was required or not. Must be set if the
PADENABLE bit is set.
0 = The frames presented to the MAC have a valid CRC
bit 3 DELAYCRC: Delayed CRC bit
This bit determines the number of bytes, if any, of proprietary header information that exist on the front of the
IEEE 802.3 frames.
1 = Four bytes of header (ignored by the CRC function)
0 = No proprietary header
bit 2 HUGEFRM: Huge Frame enable bit
1 = Frames of any length are transmitted and received
0 = Huge frames are not allowed for receive or transmit
bit 1 LENGTHCK: Frame Length checking bit
1 = Both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field
represents a length then the check is performed. Mismatches are reported on the transmit/receive
statistics vector.
0 = Length/Type field check is not performed
bit 0 FULLDPLX: Full-Duplex Operation bit
1 = The MAC operates in Full-Duplex mode
0 = The MAC operates in Half-Duplex mode
Note 1: Table 31-4 provides a description of the pad function based on the configuration of this register.
2: This bit is ignored if the PADENABLE bit is cleared.
3: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.
8-bit accesses are not allowed and are ignored by the hardware
TABLE 31-4: PAD OPERATION

Type AUTOPAD VLANPAD PADENABLE Action
Any x x 0 No pad, check CRC
Any 0 0 1 Pad to 60 Bytes, append CRC
Any x 1 1 Pad to 64 Bytes, append CRC
Any 1 0 1 If untagged: Pad to 60 Bytes, append CRC
If VLAN tagged: Pad to 64 Bytes, append CRC

REGISTER 31-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET

GAP REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
B2BIPKTGP<6:0>
Legend:

bit 6-0 B2BIPKTGP<6:0>: Back-to-Back Interpacket Gap bits
This is a programmable field representing the nibble time offset of the minimum possible period between
the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value
should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the
desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which rep-
resents the minimum IPG of 0.96 s (in 100 Mbps) or 9.6 s (in 10 Mbps). In Half-Duplex mode, the rec-
ommended setting is 0x12 (18d), which also represents the minimum IPG of 0.96 s (in 100 Mbps) or 9.6
s (in 10 Mbps).

REGISTER 31-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK

INTERPACKET GAP REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
NB2BIPKTGP1<6:0>
7:0
NB2BIPKTGP2<6:0>
Legend:

bit 14-8 NB2BIPKTGP1<6:0>: Non-Back-to-Back Interpacket Gap Part 1 bits
This is a programmable field representing the optional carrierSense window referenced in section
4.2.3.2.1 Deference of the IEEE 80.23 Specification. If carrier is detected during the timing of IPGR1, the
MAC defers to carrier. If, however, carrier becomes after IPGR1, the MAC continues timing IPGR2 and
transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to
IPGR2. Its recommend value is 0xC (12d).
bit 6-0 NB2BIPKTGP2<6:0>: Non-Back-to-Back Interpacket Gap Part 2 bits
This is a programmable field representing the non-back-to-back Inter-Packet-Gap. Its recommended value
is 0x12 (18d), which represents the minimum IPG of 0.96 s (in 100 Mbps) or 9.6 s (in 10 Mbps).

REGISTER 31-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY

LIMIT REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1
15:8
CWINDOW<5:0>
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
7:0
RETX<3:0>
Legend:

bit 13-8 CWINDOW<5:0>: Collision Window bits
This is a programmable field representing the slot time or collision window during which collisions occur in
properly configured networks. Since the collision window starts at the beginning of transmission, the pre-
amble and SFD is included. Its default of 0x37 (55d) corresponds to the count of frame bytes at the end of
the window.
bit 3-0 RETX<3:0>: Retransmission Maximum bits
This is a programmable field specifying the number of retransmission attempts following a collision before
aborting the packet due to excessive collisions. The Standard specifies the maximum number of attempts
(attemptLimit) to be 0xF (15d). Its default is 0xF.

REGISTER 31-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
MACMAXF<15:8>(1)
7:0
MACMAXF<7:0>(1)
Legend:

bit 15-0 MACMAXF<15:0>: Maximum Frame Length bits(1)
These bits reset to 0x05EE, which represents a maximum receive frame of 1518 octets. An untagged
maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If
a shorter/longer maximum length restriction is desired, program this 16-bit field.
Note 1: If a proprietary header is allowed, this bit should be adjusted accordingly. For example, if 4-byte headers
are prepended to frames, MACMAXF could be set to 1527 octets. This would allow the maximum VLAN
tagged frame plus the 4-byte header.

REGISTER 31-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
15:8
RESETRMII(1) SPEEDRMII(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:

bit 11 RESETRMII: Reset RMII Logic bit(1)
1 = Reset the MAC RMII module
0 = Normal operation.
bit 8 SPEEDRMII: RMII Speed bit(1)
This bit configures the Reduced MII logic for the current operating speed.
1 = RMII is running at 100 Mbps
0 = RMII is running at 10 Mbps
Note 1: This bit is only used for the RMII module.

REGISTER 31-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
7:0
TESTBP TESTPAUSE(1) SHRTQNTA(1)
Legend:

bit 2 TESTBP: Test Backpressure bit
1 = The MAC will assert backpressure on the link. Backpressure causes preamble to be transmitted, raising
carrier sense. A transmit packet from the system will be sent during backpressure.
bit 1 TESTPAUSE: Test PAUSE bit(1)
1 = The MAC Control sub-layer will inhibit transmissions, just as if a PAUSE Receive Control frame with a
non-zero pause time parameter was received
bit 0 SHRTQNTA: Shortcut PAUSE Quanta bit(1)
1 = The MAC reduces the effective PAUSE Quanta from 64 byte-times to 1 byte-time
Note 1: This bit is only used for testing purposes.

REGISTER 31-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT

CONFIGURATION REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
RESETMGMT
U-0 U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CLKSEL<3:0>(1) NOPRE SCANINC
Legend:

bit 15 RESETMGMT: Test Reset MII Management bit
1 = Reset the MII Management module
0 = Normal Operation
bit 5-2 CLKSEL<3:0>: MII Management Clock Select 1 bits(1)
These bits are used by the clock divide logic in creating the MII Management Clock (MDC), which the IEEE
802.3 Specification defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz.
bit 1 NOPRE: Suppress Preamble bit
1 = The MII Management will perform read/write cycles without the 32-bit preamble field. Some PHYs
support suppressed preamble
0 = Normal read/write cycles are performed
bit 0 SCANINC: Scan Increment bit
1 = The MII Management module will perform read cycles across a range of PHYs. The read cycles will start
from address 1 through the value set in EMAC1MADR<PHYADDR>
0 = Continuous reads of the same PHY
Note 1: Table 31-5 provides a description of the clock divider encoding.
TABLE 31-5: MIIM CLOCK SELECTION

MIIM Clock Select EMAC1MCFG<5:2>
TPBCLK5 divided by 4 000x
TPBCLK5 divided by 6 0010
Undefined Any other combination

REGISTER 31-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
7:0
SCAN READ
Legend:

bit 1 SCAN: MII Management Scan Mode bit
1 = The MII Management module will perform read cycles continuously (for example, useful for monitoring
the Link Fail)
0 = Normal Operation
bit 0 READ: MII Management Read Command bit
1 = The MII Management module will perform a single read cycle. The read data is returned in the
EMAC1MRDD register
0 = The MII Management module will perform a write cycle. The write data is taken from the EMAC1MWTD
register

REGISTER 31-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
15:8
PHYADDR<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
REGADDR<4:0>
Legend:

bit 12-8 PHYADDR<4:0>: MII Management PHY Address bits
This field represents the 5-bit PHY Address field of Management cycles. Up to 31 PHYs can be addressed
(0 is reserved).
bit 4-0 REGADDR<4:0>: MII Management Register Address bits
This field represents the 5-bit Register Address field of Management cycles. Up to 32 registers can be
accessed.

REGISTER 31-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE

DATA REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
MWTD<15:8>
7:0
MWTD<7:0>
Legend:

bit 15-0 MWTD<15:0>: MII Management Write Data bits
When written, a MII Management write cycle is performed using the 16-bit data and the preconfigured PHY
and Register addresses from the EMAC1MADR register.
REGISTER 31-35: EMAC1MRDD: ETHERNET CONTROLLER MAC MII MANAGEMENT READ DATA
REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
MRDD<15:8>
7:0
MRDD<7:0>
Legend:

bit 15-0 MRDD<15:0>: MII Management Read Data bits
Following a MII Management Read Cycle, the 16-bit data can be read from this location.

REGISTER 31-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
LINKFAIL NOTVALID SCAN MIIMBUSY
Legend:

bit 3 LINKFAIL: Link Fail bit
When 1 is returned - indicates link fail has occurred. This bit reflects the value last read from the PHY status
register.
bit 2 NOTVALID: MII Management Read Data Not Valid bit
When 1 is returned - indicates an MII management read cycle has not completed and the Read Data is not
yet valid.
bit 1 SCAN: MII Management Scanning bit
When 1 is returned - indicates a scan operation (continuous MII Management Read cycles) is in progress.
bit 0 MIIMBUSY: MII Management Busy bit
When 1 is returned - indicates MII Management module is currently performing an MII Management Read
or Write cycle.

REGISTER 31-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
15:8
STNADDR6<7:0>
7:0
STNADDR5<7:0>


bit 15-8 STNADDR6<7:0>: Station Address Octet 6 bits
These bits hold the sixth transmitted octet of the station address.
These bits hold the fifth transmitted octet of the station address.
Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
2: This register is loaded at reset from the factory preprogrammed station address.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
STNADDR4<7:0>
7:0
STNADDR3<7:0>


These bits hold the fourth transmitted octet of the station address.
These bits hold the third transmitted octet of the station address.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
STNADDR2<7:0>
7:0
STNADDR1<7:0>

bit 31-16 Reserved: Maintain as 0; ignore read

These bits hold the second transmitted octet of the station address.
These bits hold the most significant (first transmitted) octet of the station address.

32.0 COMPARATOR The Analog Comparator module consists of two
comparators that can be configured in a variety of
Note: This data sheet summarizes the features ways.
of the PIC32MZ Graphics (DA) Family of Key features of the Analog Comparator module are:
comprehensive reference source. To Differential inputs
complement the information in this data Rail-to-rail operation
sheet, refer to Section 19. Selectable output polarity
Comparator (DS60001110), which is Selectable inputs:
available from the Documentation > - Analog inputs multiplexed with I/O pins
- On-chip internal absolute voltage reference
(www.microchip.com/pic32). - Comparator voltage reference (CVREF)
Selectable interrupt generation
A block diagram of the comparator module is illustrated
in Figure 32-1.
FIGURE 32-1: COMPARATOR BLOCK DIAGRAM
C1INB CCH<1:0> (CM1CON<1:0>)
C1INC
COE (CM1CON<14>)
C1IND
CMP1 C1OUT
CREF
(CM1CON<4>)
CPOL
(CM1CON<13>)
COUT (CM1CON<8>)
C1INA
and Trigger to ADC
C1OUT
D Q (CMSTAT<2>)
C2INB CCH<1:0> (CM2CON<1:0>)
PBCLK3
C2INC
COE (CM2CON<14>)
C2IND
CMP2 C2OUT
CREF
(CM2CON<4>)
CPOL
(CM2CON<13>)
COUT (CM2CON<8>) and
C2INA
Trigger to ADC
CVREF(1) C2OUT
D Q (CMSTAT<1>)
PBCLK3
IVREF (1.2V)
Note 1: Internally connected. See Section 33.0 Comparator Voltage Reference (CVREF) for more information.

DS60001361E-page 566
32.1 Comparator Control Registers

TABLE 32-1: COMPARATOR REGISTER MAP
All Resets
Bit Range
(BF84_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
C000 CM1CON
15:0 ON COE CPOL COUT EVPOL<1:0> CREF CCH<1:0> 00C3
31:16 0000
C010 CM2CON
15:0 ON COE CPOL COUT EVPOL<1:0> CREF CCH<1:0> 00C3
31:16 0000
C060 CMSTAT
15:0 SIDL C2OUT C1OUT 0000
more information.
REGISTER 32-1: CMxCON: COMPARATOR CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R-0
15:8 (1)
ON COE CPOL COUT
R/W-1 R/W-1 U-0 R/W-0 U-0 U-0 R/W-1 R/W-1
7:0
EVPOL<1:0> CREF CCH<1:0>
Legend:

bit 15 ON: Comparator ON bit
1 = Module is enabled. Setting this bit does not affect the other bits in this register
0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this
register
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is driven on the output CxOUT pin
0 = Comparator output is not driven on the output CxOUT pin
bit 13 CPOL: Comparator Output Inversion bit(1)
1 = Output is inverted
0 = Output is not inverted
bit 8 COUT: Comparator Output bit
1 = Output of the Comparator is a 1
0 = Output of the Comparator is a 0
bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
10 = Comparator interrupt is generated on a high-to-low transition of the comparator output
01 = Comparator interrupt is generated on a low-to-high transition of the comparator output
00 = Comparator interrupt generation is disabled
bit 4 CREF: Comparator Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CVREF
0 = Comparator non-inverting input is connected to the CXINA pin
bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator
11 = Comparator inverting input is connected to the IVREF
10 = Comparator inverting input is connected to the CxIND pin
01 = Comparator inverting input is connected to the CxINC pin
00 = Comparator inverting input is connected to the CxINB pin
Note 1: Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.

REGISTER 32-2: CMSTAT: COMPARATOR STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
15:8
SIDL
U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0
7:0
C2OUT C1OUT
Legend:

bit 13 SIDL: Stop in IDLE Control bit
1 = All Comparator modules are disabled in IDLE mode
0 = All Comparator modules continue to operate in the IDLE mode
bit 1 C2OUT: Comparator Output bit
1 = Output of Comparator 2 is a 1
bit 0 C1OUT: Comparator Output bit

33.0 COMPARATOR VOLTAGE The resistor ladder is segmented to provide two ranges
of voltage reference values and has a power-down
REFERENCE (CVREF) function to conserve power when the reference is not
Note: This data sheet summarizes the being used. The modules supply reference can be pro-
features of the PIC32MZ Graphics (DA) vided from either device VDDIO/VSS or an external
Family of devices. It is not intended to voltage reference. The CVREF output is available for
be a comprehensive reference source. the comparators and typically available for pin output.
To complement the information in this The comparator voltage reference has the following
data sheet, refer to Section 20. Com- features:
parator Voltage Reference (CVREF)
High and low range selection
(DS60001109), which is available from
the Documentation > Reference Manual Sixteen output levels available for each range
section of the Microchip PIC32 web site Internally connected to comparators to conserve
(www.microchip.com/pic32). device pins
Output can be connected to a pin
The CVREF module is a 16-tap, resistor ladder network
that provides a selectable reference voltage. Although A block diagram of the CVREF module is illustrated in
its primary purpose is to provide a reference for the Figure 33-1.
analog comparators, it also may be used independently
of them.
FIGURE 33-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+ CVRSRC
AVDD
CVRSS = 0 8R
CVR<3:0> CVREF
CVREN R
R
16-to-1 MUX
16 Steps
CVREFOUT
CVRCON<CVROE>
R
R
R
CVRR 8R
CVRSS = 1
VREF-
AVSS
CVRSS = 0

DS60001361E-page 570
33.1 Comparator Voltage Reference Control Registers

TABLE 33-1: COMPARATOR VOLTAGE REFERENCE REGISTER MAP
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
0E00 CVRCON
15:0 ON CVROE CVRR CVRSS CVR<3:0> 0000
Note 1: The register in this table has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for
more information.
REGISTER 33-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
ON
7:0
CVROE CVRR CVRSS CVR<3:0>
Legend:

bit 15 ON: Comparator Voltage Reference On bit
Setting this bit does not affect other bits in the register.
0 = Module is disabled and does not consume current.
Clearing this bit does not affect the other bits in the register.
bit 6 CVROE: CVREFOUT Enable bit
1 = Voltage level is output on CVREFOUT pin
0 = Voltage level is disconnected from CVREFOUT pin
bit 5 CVRR: CVREF Range Selection bit
1 = 0 to 0.67 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size
bit 4 CVRSS: CVREF Source Selection bit
1 = Comparator voltage reference source, CVRSRC = (VREF+) (VREF-)
0 = Comparator voltage reference source, CVRSRC = AVDD AVSS
bit 3-0 CVR<3:0>: CVREF Value Selection 0 CVR<3:0> 15 bits
When CVRR = 1:
CVREF = (CVR<3:0>/24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC)

NOTES:

34.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect (HLVD) module is a
programmable circuit that allows the user to specify
(HLVD)
both the device voltage trip point and the direction of
Note: This data sheet summarizes the change.
features of the PIC32MZ Graphics (DA) The HLVD module provides the following features:
Hysteresis detection
To complement the information in this Low-to-high or high-to-low voltage change
data sheet, refer to Section 38. detection
High/Low-Voltage Detect (HLVD) Generation of Non-Maskable Interrupts (NMI)
(DS60001408), which is available from LVDIN pin to provide external voltage trip point
the Documentation > Reference Manual
FIGURE 34-1: HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
Externally Generated
Trip Point
VDDIO
VDDIO
HLVDIN HLVDL<3:0>
ON VDIR
16-to-1 MUX
HLVD Event to
NMI
Band Gap
Reference
ON

DS60001361E-page 574

TABLE 34-1: HIGH/LOW-VOLTAGE DETECT REGISTER MAP
All Resets
Bit Range
(BF80_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 0000
1800 HLVDCON
15:0 ON VDIR BGVST HLEVT HLEVTOUTDIS HLVDL<3:0> 0000
Note 1: The register in this table has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.2 CLR, SET, and INV Registers for
more information.
H
REGISTER 34-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

R/W-0 U-0 U-0 U-0 R/W-0 HS,HC,R-0 r-1 HS,HC,R-0
15:8
ON VDIR BGVST HLEVT
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
HLEVTOUTDIS(2) HLVDL<3:0> (1)
Legend: HS = Hardware Set HC = Hardware Cleared r = Reserved bit


bit 15 ON: HLVD Module Enable bit
1 = HLVD module is enabled
0 = HLVD module is disabled
bit 11 VDIR: Voltage Change Direction Select bit
1 = Event occurs when voltage equals or exceeds the trip point (HLVDL<3:0>)
0 = Event occurs when voltage equals or falls below the trip point (HLVDL<3:0>)
bit 10 BGVST: Band Gap Reference Voltages Stable Status bit
1 = Indicates internal band gap voltage references is stable
0 = Indicates internal band gap voltage reference is not stable
This bit is readable when the HLVD module is disabled (ON = 0).
bit 8 HLEVT: High/Low-Voltage Detection Event Status bit
1 = Indicates HLVD Event is active
0 = Indicates HLVD Event is not active
bit 7 HLEVTOUTDIS: High/Low-Voltage Detection Event Output Disable bit(2)
1 = Enables HLVD Event output
0 = Disable HLVD Event output
Note 1: To avoid false HLVD events, all HLVD module setting changes should occur only when the module is
disabled (ON = 0). See Table 44-6 in 44.0 Electrical Characteristics for the actual trip points.
2: Once this bit is set to '1', it can only be cleared by disabling or enabling the HLVD module (or through the
HLVDMD bit).

REGISTER 34-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
bit 3-0 HLVDL<3:0>: High/Low-Voltage Detection Limit Select bits(1)
1111 = Selects analog input on HLVDIN
1110 = Selects trip point 14
Note 1: To avoid false HLVD events, all HLVD module setting changes should occur only when the module is
disabled (ON = 0). See Table 44-6 in 44.0 Electrical Characteristics for the actual trip points.
2: Once this bit is set to '1', it can only be cleared by disabling or enabling the HLVD module (or through the
HLVDMD bit).

35.0 CHARGE TIME The CTMU module includes the following key features:
MEASUREMENT UNIT (CTMU) Up to 35 channels available for capacitive or time
measurement input
Note: This data sheet summarizes the features On-chip precision current source
of the PIC32MZ Graphics (DA) Family
16-edge input trigger sources
family of devices. It is not intended to be a
comprehensive reference source. To Selection of edge or level-sensitive inputs
complement the information in this data Polarity control for each edge source
sheet, refer to Section 37. Charge Time Control of edge sequence
Measurement Unit (CTMU) Control of response to edges
(DS60001167), which is available from the High precision time measurement
Time delay of external or internal signal asynchro-
nous to system clock
Integrated temperature sensing diode
The Charge Time Measurement Unit (CTMU) is a Control of current source during auto-sampling
flexible analog module that has a configurable current Four current source ranges
source with a digital configuration circuit built around it.
Time measurement resolution of one nanosecond
The CTMU can be used for differential time
measurement between pulse sources and can be used A block diagram of the CTMU is shown in Figure 35-1.
for generating an asynchronous pulse. By working with
other on-chip analog modules, the CTMU can be used
for high resolution time measurement, measure
capacitance, measure relative changes in capacitance
or generate output pulses with a specific time delay.
The CTMU is ideal for interfacing with capacitive-based
sensors.
FIGURE 35-1: CTMU BLOCK DIAGRAM
CTMUICON
ITRIM<5:0>
IRNG<1:0>
Current Source
CTED1 Edge
Control CTMU ADC
Logic EDG1STAT
CTED2 EDG2STAT TGEN Control Trigger
Current Logic
Control
Timer1
OC1-OC4
CTMUP Pulse CTPLS
IC1-IC6
Generator
CMP1-CMP2
CTMUI
PBCLK3 (To ADC S&H capacitor)
CTMUT
(To ADC)
C2INB
Temperature
Sensor
CDELAY
Comparator 2
External capacitor
for pulse generation
Current Control Selection TGEN EDG1STAT, EDG2STAT
CTMUT 0 EDG1STAT = EDG2STAT

CTMUI 0 EDG1STAT EDG2STAT
CTMUP 1 EDG1STAT EDG2STAT
No Connect 1 EDG1STAT = EDG2STAT

DS60001361E-page 578
35.1 CTMU Control Registers

TABLE 35-1: CTMU REGISTER MAP
All Resets
Bit Range
(BF84_#)
Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL<3:0> 0000
C200 CTMUCON
15:0 ON CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG ITRIM<5:0> IRNG<1:0> 0000
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 CLR, SET and INV Registers for
more information.
REGISTER 35-1: CTMUCON: CTMU CONTROL REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
EDG1MOD EDG1POL EDG1SEL<3:0> EDG2STAT EDG1STAT
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
23:16
EDG2MOD EDG2POL EDG2SEL<3:0>
15:8
ON CTMUSIDL TGEN(1) EDGEN EDGSEQEN IDISSEN(2) CTTRIG
7:0
ITRIM<5:0> IRNG<1:0>
Legend:
bit 31 EDG1MOD: Edge1 Edge Sampling Select bit

1 = Input is edge-sensitive
0 = Input is level-sensitive
bit 30 EDG1POL: Edge 1 Polarity Select bit
1 = Edge1 programmed for a positive edge response
0 = Edge1 programmed for a negative edge response
bit 29-26 EDG1SEL<3:0>: Edge 1 Source Select bits
1111 = Reserved
1110 = C2OUT pin is selected
1100 = IC6 Capture Event is selected
0110 = OC4 Capture Event is selected
0011 = CTED1 pin is selected
0001 = OC1 Compare Event is selected
0000 = Timer1 Event is selected
bit 25 EDG2STAT: Edge2 Status bit
Indicates the status of Edge2 and can be written to control edge source
1 = Edge2 has occurred
0 = Edge2 has not occurred
Note 1: When this bit is set for Pulse Delay Generation, the EDG2SEL<2:0> bits must be set to 1110 to select
the C2OUT pin.
2: The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion
cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor
before conducting the measurement. The IDISSEN bit, when set to 1, performs this function. The ADC
module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor
array.
3: Refer to the CTMU Current Source Specifications (Table 44-20) in Section 44.0 Electrical
Characteristics for current values.
4: This bit setting is not available for the CTMU temperature diode.

REGISTER 35-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
bit 24 EDG1STAT: Edge1 Status bit
Indicates the status of Edge1 and can be written to control edge source
1 = Edge1 has occurred
0 = Edge1 has not occurred
bit 23 EDG2MOD: Edge2 Edge Sampling Select bit
1 = Input is edge-sensitive
0 = Input is level-sensitive
bit 22 EDG2POL: Edge 2 Polarity Select bit
1 = Edge2 programmed for a positive edge response
0 = Edge2 programmed for a negative edge response
bit 21-18 EDG2SEL<3:0>: Edge 2 Source Select bits
1111 = Reserved
1100 = PBCLK3
0001 = OC1 Compare Event is selected
0000 = Timer1 Event is selected
bit 15 ON: ON Enable bit
0 = Module is disabled
bit 13 CTMUSIDL: Stop-in-Idle Mode bit
bit 12 TGEN: Time Generation Enable bit(1)
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11 EDGEN: Edge Enable bit
1 = Edges are not blocked
0 = Edges are blocked
bit 10 EDGSEQEN: Edge Sequence Enable bit
1 = Edge1 must occur before Edge2 can occur
0 = No edge sequence is needed
the C2OUT pin.
array.

REGISTER 35-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED)
bit 9 IDISSEN: Analog Current Source Control bit(2)
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8 CTTRIG: Trigger Control bit
1 = Trigger output is enabled
0 = Trigger output is disabled
bit 7-2 ITRIM<5:0>: Current Source Trim bits
011111 = Maximum positive change from nominal current
011110

000001 = Minimum positive change from nominal current
000000 = Nominal current output specified by IRNG<1:0>
111111 = Minimum negative change from nominal current

100010
100001 = Maximum negative change from nominal current
bit 1-0 IRNG<1:0>: Current Range Select bits(3)
11 = 100 times base current
10 = 10 times base current
01 = Base current level
00 = 1000 times base current(4)
the C2OUT pin.
array.

NOTES:

36.0 GRAPHICS LCD (GLCD) Key features of the GLCD Controller include:
CONTROLLER Up to 50 MHz Pixel Clock
Up to 800x480 (WVGA) with Overlay (application
Note 1: This data sheet summarizes the features dependent). Still Image up to 1280x1024 (SXGA)
Color depths: 8, 16(1), 18, and 24 bits
comprehensive reference source. To Up to three design timing layers, each including:
complement the information in this data - Configurable Alpha blending
sheet, refer to Section 54. Graphics - Configurable Stride and Pitch
LCD Controller (DS60001379), which Input formats: RGBA8888, ARGB8888, RGB888,
is available from the Documentation > RGB565, RGBA5551, YUYV, RGB332, LUT8,
Reference Manual section of the and Gray-scale
Microchip PIC32 web site Output formats: RGB888, RGB666, BT.656
Dithering for 18-bit displays
The Graphics LCD (GLCD) Controller is designed to High-quality YUV conversion
directly interface with display glasses, using a built-in Global color palette look-up table (CLUT) supporting
analog drive, to individually control pixels on the 256 colors
screen. Global gamma correction, brightness and contrast
The GLCD Controller transfers display data from a support
memory device and formats it for a display device. The Programmable cursors supporting 16 colors
memory may be internal RAM or DDR2. Programmable polarity on HSYNC, VSYNC, DE,
The parallel interface at the pins will operate at stan- and PCLK
dard 3.3V output, requires 28 pins for 24-bit color, and Integrated DMA to offload the CPU
is shared by general purpose I/O functions. Programmable (level/edge) interrupt on HSYNC and
VSYNC
Note 1: 16-bit color depth is supported through
the GLCDMODE bit (CFGCON2<30>).
When set, functions shared with GD0,
GD1, GD2, GD8, GD9, GD16, GD17,
GD18 are available for general purpose
use.
A block diagram of the GLCD Controller interface is
provided in Figure 36-1.

DS60001361E-page 584
FIGURE 36-1: GRAPHICS LCD CONTROLLER BLOCK DIAGRAM

Slave Control Registers
Layer 1 Layer 2 Layer 3 GEN

Color VSYNC
Palette and Dithering Cursors Formatting HSYNC
Gamma GCLK
GD<23:0>(1)
S Stride/Pitch Stride/Pitch Stride/Pitch
y
s
t
e Alpha Alpha Alpha
m Blending Blending Blending
B
u
s DMA Engine DMA Engine DMA Engine
Master Master Arbiter
Note 1: R<7:0> = GD<7:0>; G<7:0> = GD<15:8>; B<7:0> = GD<23:16>.

36.1 Graphics LCD Controller Control Registers
TABLE 36-1:
Virtual Address GRAPHICS LCD CONTROLLER REGISTER MAP
All Resets
Bit Range
(BF8E_#)
Register
Name
Bit 31/15 Bit 30/14 Bit 29/13 Bit 28/12 Bit 27/11 Bit 26/10 Bit 25/9 Bit 24/8 Bit 23/7 Bit 22/6 Bit 21/5 Bit 20/4 Bit 19/3 Bit 118/2 Bit 17/1 Bit 16/0
CURSOR VSYNC HSYNC VSYNC PCLK PGRAMP FORCE

31:16 LCDEN DEPOL DITHER 0000
GLCD EN POL POL CYC POL EN BLANK
A000
MODE YUV FORMAT
15:0 RGBSEQ<2:0> 0000
OUTPUT CLK
GLCD 31:16 0401
A004
CLKCON 15:0 LPREFETCH<5:0> CLKDIV<5:0> 0000
GLCD 31:16 RED<7:0> GREEN<7:0> 0000
A008
BGCOLOR 15:0 BLUE<7:0> ALPHA<7:0> 0000
31:16 RESX<10:0> 0000

A00C GLCDRES
15:0 RESY<10:0> 0000
GLCD 31:16 FPORCHX<10:0> 0000
A014
FPORCH 15:0 FPORCHY<10:0> 0000
GLCD 31:16 BLANKINGX<10:0> 0000
A018
BLANKING 15:0 BLANKINGY<10:0> 0000
GLCD 31:16 BPORCHX<10:0> 0000
A01C
BPORCH 15:0 BPORCHY<10:0> 0000
GLCD 31:16 CURSORX<10:0> 0000
A020
CURSOR 15:0 CURSORY<10:0> 0000
DISA FORCE MUL
GLCD 31:16 LAYEREN ALPHA<7:0> 0000
A030 BIFIL ALPHA ALPHA
L0MODE
15:0 DESTBLEND<3:0> SRCBLEND<3:0> COLORMODE<3:0> 0000
GLCD 31:16 STARTX<10:0> 0000
A034
L0START 15:0 STARTY<10:0> 0000
GLCD 31:16 SIZEX<10:0> 0000
A038
L0SIZE 15:0 SIZEY<10:0> 0000
GLCD 31:16 BASEADDR<31:16> 0000
A03C
L0BADDR 15:0 BASEADDR<15:0> 0000
GLCD 31:16 0000
DS60001361E-page 585
A040
L0STRIDE 15:0 STRIDE<15:0> 0000
GLCD 31:16 RESX<10:0> 0000
A044
L0RES 15:0 RESY<10:0> 0000
DISA FORCE MUL 0000
GLCD 31:16 LAYEREN ALPHA<7:0>
L1MODE
Note 1: For the PIXELxy bits, x = 0-31 and y = 0-31 (i.e., GLCDCURDATA0 contains PIXEL00 through PIXEL07 with PIXEL00 in the most significant nibble).
DS60001361E-page 586
TABLE 36-1: GRAPHICS LCD CONTROLLER REGISTER MAP (CONTINUED)

Virtual Address
All Resets
Bit Range
(BF8E_#)
Register
Name
Bit 31/15 Bit 30/14 Bit 29/13 Bit 28/12 Bit 27/11 Bit 26/10 Bit 25/9 Bit 24/8 Bit 23/7 Bit 22/6 Bit 21/5 Bit 20/4 Bit 19/3 Bit 118/2 Bit 17/1 Bit 16/0
GLCD 31:16 STARTX<10:0> 0000

A054
GLCD 31:16 SIZEX<10:0> 0000
A058
L1SIZE 15:0 SIZEY<10:0> 0000
GLCD 31:16 BASEADDR<31:16> 0000
A05C
GLCD 31:16 0000
A060
GLCD 31:16 RESX<10:0> 0000
A064
L1RES 15:0 RESY<10:0> 0000
DISA FORCE MUL 0000
GLCD 31:16 LAYEREN ALPHA<7:0>
L2MODE
GLCD 31:16 STARTX<10:0> 0000
A074
GLCD 31:16 SIZEX<10:0> 0000
A078
L2SIZE 15:0 SIZEY<10:0> 0000
GLCD 31:16 BASEADDR<31:16> 0000
A07C
GLCD 31:16 0000
A080
31:16 RESX<10:0> 0000
A084 GLCDL2RES
15:0 RESY<10:0> 0000
31:16 IRQCON 0000
A0F8 GLCDINT
15:0 HSYNCINT VSYNCINT 0001

31:16 0000
A0FC GLCDSTAT
15:0 LROW VSYNC HSYNC DE ACTIVE 0000
A400 31:16 RED<7:0> 0000
GLCDCLUTx
through
('x' = 0-255) 15:0 GREEN<7:0> BLUE<7:0> 0000
A7FC
A800 GLCD 31:16 PIXELxy<3:0>(1) PIXELxy<3:0>(1) PIXELxy<3:0>(1) PIXELxy<3:0>(1) 0000
through CURDATAx
A9FC (x = 0-127) 15:0 PIXELxy<3:0>(1) PIXELxy<3:0>(1) PIXELxy<3:0>(1) PIXELxy<3:0>(1) 0000
AA00 GLCD 31:16 RED<7:0> 0000
through CURLUTx
AA40 (x = 0-15) 15:0 GREEN<7:0> BLUE<7:0> 0000
Note 1: For the PIXELxy bits, x = 0-31 and y = 0-31 (i.e., GLCDCURDATA0 contains PIXEL00 through PIXEL07 with PIXEL00 in the most significant nibble).
REGISTER 36-1: GLCDMODE: GRAPHICS LCD CONTROLLER MODE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
31:24 CURSOR VSYNC HSYNC
LCDEN DEPOL DITHER
EN POL POL
R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0
23:16 VSYNC PGRAMP FORCE
PCLKPOL
CYC EN BLANK
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8 YUV FORMAT

OUTPUT CLK
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
7:0
RGBSEQ<2:0>
Legend:
bit 31 LCDEN: LCD Controller Module Enable bit

1 = LCD Controller module is enabled
0 = LCD Controller module is not enabled
bit 30 CURSOREN: Programmable Cursor Enable bit
1 = Programmable cursor is enabled
0 = Programmable cursor is enabled
bit 28 VSYNCPOL: Vertical Sync Polarity bit
1 = VSYNC polarity is negative
0 = VSYNC polarity is positive
bit 27 HSYNCPOL: Horizontal Sync Polarity bit
1 = HSYNC polarity is negative
0 = HSYNC polarity is positive
bit 26 DEPOL: DE Polarity bit
1 = DE polarity is negative
0 = DE polarity is positive
bit 24 DITHER: Dithering Enable bit
1 = Dithering is enabled
0 = Dithering is not enabled
bit 23 VSYNCCYC: Vertical Sync for Single Cycle Per Line Enable bit
1 = VSYNC for a single cycle per line is enabled
0 = VSYNC for a single cycle per line is not enabled
bit 22 PCLKPOL: Pixel Clock Out Polarity bit
1 = Pixel clock out polarity is negative
0 = Pixel clock out polarity is positive
bit 20 PGRAMPEN: Palette Gamma Ramp Enable bit
1 = Palette gamma ramp is enabled
0 = Palette gamma ramp is not enabled

REGISTER 36-1: GLCDMODE: GRAPHICS LCD CONTROLLER MODE REGISTER (CONTINUED)
bit 19 FORCEBLANK: Force Output to Blank bit
1 = Forces output to blank
0 = No effect
bit 9 YUVOUTPUT: YUV Output Enable bit
1 = YUV is enabled
0 = RGB is enabled
bit 8 FORMATCLK: Formatting Clock Divide Enable bit
1 = Formatting clock is not divided
0 = Formatting clock is divided
bit 7-5 RGBSEQ<2:0>: RGB Sequential Modes bit
111 = BT.656
110 = YUYV
101 = Reserved
100 = Reserved
011 = Reserved
010 = Reserved
001 = Reserved
000 = Parallel RGB (RGB888, RGB666, RGB332)

REGISTER 36-2: GLCDCLKCON: GRAPHICS LCD CONTROLLER CLOCK CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
LPREFETCH<5:0>
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CLKDIV<5:0>
Legend:

bit 13-8 LPREFETCH<5:0>: Lines Prefetch bits
These bits represent the number of lines to be prefetched before starting the frame (through DMA). The
maximum value is 2LPREFETCH = 32.
bit 5-0 CLKDIV<5:0>: Clock Divider bits
111111 = Reserved
111110 = Reserved

011111 = Divided by 31

Note: If the value of CLKDIV<5:0> is even, GCLK = (REFCLKO5/CLKDIV) with a duty cycle of 50%.
If the value of CLKDIV<5:0> is odd, PCLK = (REFCLKO5/CLKDIV) with a duty cycle of 60% to
40%.

REGISTER 36-3: GLCDBGCOLOR: GRAPHICS LCD CONTROLLER BACKGROUND COLOR

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
RED<7:0>
23:16
GREEN<7:0>
15:8
BLUE<7:0>
7:0
ALPHA<7:0>
Legend:
bit 31-24 RED<7:0>: Color Red as Background bits

These bits specify that the color red is to be used as the background color.
bit 23-16 GREEN<7:0>: Color Green as Background bits
These bits specify that the color green is to be used as the background color.
bit 15-8 BLUE<7:0>: Color Blue as Background bits
These bits specify that the color blue is to be used as the background color.
bit 7-0 ALPHA<7:0>: Color Alpha as Background bits
These bits specify that the color alpha is to be used as the background color.
Note: If all of the bits in this register are set (RED, GREEN, BLUE and ALPHA), RGBA color is used as the
background.
REGISTER 36-4: GLCDRES: GRAPHICS LCD CONTROLLER RESOLUTION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
RESX<10:8>
23:16
RESX<7:0>
15:8
RESY<10:8>
7:0
RESY<7:0>
Legend:

bit 26-16 RESX<10:0>: X Dimension Pixel Resolution bits
These bits specify the pixel resolution for the X dimension.
bit 10-0 RESY<10:0>: Y Dimension Pixel Resolution bits
These bits specify the pixel resolution for the Y dimension.

REGISTER 36-5: GLCDFPORCH: GRAPHICS LCD CONTROLLER FRONT PORCH REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
FPORCHX<10:8>
23:16
FPORCHX<7:0>
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
FPORCHY<10:8>
7:0
FPORCHY<7:0>
Legend:

bit 26-16 FPORCHX<10:0>: X Dimension Front Porch Lines bits
These bits specify the front porch X dimension lines.
bit 10-0 FPORCHY<10:0>: Y Dimension Front Porch Pixel Clocks bits
These bits specify the front porch Y dimension pixel clocks.
REGISTER 36-6: GLCDBLANKING: GRAPHICS LCD CONTROLLER BLANKING REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
BLANKINGX<10:8>
23:16
BLANKINGX<7:0>
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
BLANKINGY<10:8>
7:0
BLANKINGY<7:0>
Legend:

bit 26-16 BLANKINGX<10:0>: X Dimension Blanking Period bits
These bits specify the HSYNC pulse length for the X dimension blanking period.
bit 10-0 BLANKINGY<10:0>: Y Dimension Blanking Period bits
These bits specify the VSYNC lines for the Y dimension blanking period.

REGISTER 36-7: GLCDBPORCH: GRAPHICS LCD CONTROLLER BACK PORCH REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
BPORCHX<10:8>
23:16
BPORCHX<7:0>
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
BPORCHY<10:8>
7:0
BPORCHY<7:0>
Legend:

bit 26-16 BPORCHX<10:0>: X Dimension Back Porch Lines bits
These bits specify the front porch X dimension lines.
bit 10-0 BPORCHY<10:0>: Y Dimension Back Porch Pixel Clocks bits
These bits specify the front porch Y dimension pixel clocks.
REGISTER 36-8: GLCDCURSOR: GRAPHICS LCD CONTROLLER CURSOR REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
CURSORX<10:8>
23:16
CURSORX<7:0>
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
CURSORY<10:8>
7:0
CURSORY<7:0>
Legend:

bit 26-16 CURSORX<10:0>: Cursor X Dimension Position bits
These bits specify the X dimension position of the cursor
bit 10-0 CURSORY<10:0>: Cursor Y Dimension Position bits
These bits specify the Y dimension position of the cursor

REGISTER 36-9: GLCDLxMODE: GRAPHICS LCD CONTROLLER LAYER x MODE REGISTER

(x = 0-2)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
31:24 FORCE MUL
LAYEREN DISABIFIL
ALPHA ALPHA
23:16
ALPHA<7:0>
15:8
DESTBLEND<3:0> SRCBLEND<3:0>
7:0
COLORMODE<3:0>
Legend:
bit 31 LAYEREN: Layer Enable bit

1 = Layer is enabled
0 = Layer is not enabled
bit 30 DISABIFIL: Disable Bilinear Filtering bit
1 = Bilinear filtering is enabled
0 = Bilinear filtering is not enabled
bit 29 FORCEALPHA: Force Alpha with Global Alpha bit
1 = Force alpha with global alpha is enabled
0 = Force alpha with global alpha is not enabled
bit 28 MULALPHA: Premultiply Image Alpha bit
1 = Premultiply image alpha is enabled
0 = Premultiply image alpha is not enabled
bit 23-16 ALPHA<7:0>: Layer Alpha bits
These bits contain the Layer Alpha value ranging from 0 to 0xFF.
bit 15-12 DESTBLEND<3:0>: Destinary Blending Function bits
1111 = Reserved
1110 = Reserved
1101 = Blend inverted destination
1100 = Reserved
1011 = Reserved
1010 = Blend alpha destination
1001 = Reserved
1000 = Reserved
0111 = Blend inverted source and inverted global
0110 = Blend inverted global
0101 = Blend inverted source
0100 = Blend alpha source and alpha global
0011 = Blend alpha global
0010 = Blend alpha source
0001 = Blend white
0000 = Blend black

REGISTER 36-9: GLCDLxMODE: GRAPHICS LCD CONTROLLER LAYER x MODE REGISTER
(x = 0-2) (CONTINUED)
bit 11-8 SRCBLEND<3:0>: Source Blending Function bits
1111 = Reserved
1110 = Reserved
1101 = Blend inverted destination
1100 = Reserved
1011 = Reserved
1010 = Blend alpha destination
1001 = Reserved
1000 = Reserved
0111 = Blend inverted source and inverted global
0110 = Blend inverted global
0101 = Blend inverted source
0100 = Blend alpha source and alpha global
0011 = Blend alpha global
0010 = Blend alpha source
0001 = Blend white
0000 = Blend black
bit 3-0 COLORMODE<3:0>: Color Mode bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = RGB888 color format
1010 = YUYV color format
1001 = L4 gray scale/palette format
0110 = 32-bit ARGB8888 color format
0101 = 16-bit RGB565 color format
0100 = 8-bit RGB332 color format
0011 = Reserved
0010 = 32-bit RGBA8888 color format
0001 = 16-bit RGBA5551 color format
0000 = 8-bit color palette look-up table (LUT8)

REGISTER 36-10: GLCDLxSTART: GRAPHICS LCD CONTROLLER LAYER x START REGISTER

(x = 0-2)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
STARTX<10:8>
23:16
STARTX<7:0>
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
STARTY<10:8>
7:0
STARTY<7:0>
Legend:

bit 26-16 STARTX<10:0>: Layer Start X Dimension bits
These bits specify the pixel offset of the starting X dimension of the layer.
bit 10-0 STARTY<10:0>: Layer Start Y Dimension bits
These bits specify the pixel offset of the starting Y dimension of the layer.
REGISTER 36-11: GLCDLxSIZE: GRAPHICS LCD CONTROLLER LAYER x SIZE REGISTER

(x = 0-2)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
SIZEX<10:8>
23:16
SIZEX<7:0>
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
SIZEY<10:8>
7:0
SIZEY<7:0>
Legend:

bit 26-16 SIZEX<10:0>: Layer Size X Dimension bits
These bits specify the pixel size of the layer in the X dimension.
bit 10-0 SIZEY<10:0>: Layer size Y Dimension bits
These bits specify the pixel size of the layer in the Y dimension.

REGISTER 36-12: GLCDLxBADDR: GRAPHICS LCD CONTROLLER LAYER x BASE ADDRESS

REGISTER (x = 0-2)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
BASEADDR<31:24>
23:16
BASEADDR<23:16>
15:8
BASEADDR<15:8>
7:0
BASEADDR<7:0>
Legend:
bit 31-0 BASEADDR<31:0>: Base Address of the Framebuffer bits

These bits specify the base address of the framebuffer.
REGISTER 36-13: GLCDLxSTRIDE: GRAPHICS LCD CONTROLLER LAYER x STRIDE REGISTER

(x = 0-2)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

15:8
STRIDE<15:8>
7:0
STRIDE<7:0>
Legend:

bit 15-0 STRIDE<15:0>: Layer Stride bits
These bits specify the distance from line to line in bytes.

REGISTER 36-14: GLCDLxRES: GRAPHICS LCD CONTROLLER LAYER x RESOLUTION

REGISTER (x = 0-2)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
RESX<10:8>
23:16
RESX<7:0>
15:8
RESY<10:8>
7:0
RESY<7:0>
Legend:

bit 26-16 RESX<10:0>: X Dimension Layer Pixel Resolution bits
These bits specify the layer pixel resolution in the X dimension.
bit 10-0 RESY<10:0>: Y Dimension Layer Pixel Resolution bits
These bits specify the layer pixel resolution in the Y dimension.

REGISTER 36-15: GLCDINT: GRAPHICS LCD CONTROLLER INTERRUPT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
IRQCON
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
7:0
HSYNCINT VSYNCINT
Legend:
bit 31 IRQCON: IRQ Triggering Control bit

1 = Edge triggering is enabled
0 = Level triggering is enabled

bit 1 HYSNNCINT: HSYNC Interrupt Enable bit
1 = HSYNC interrupt is enabled
0 = HSYNC interrupt is not enabled
bit 0 VSYNCINT: VSYNC Interrupt Enable bit

1 = VSYNC interrupt is enabled
0 = VSYNC interrupt is not enabled

REGISTER 36-16: GLCDSTAT: GRAPHICS LCD CONTROLLER STATUS REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 R-0 U-0 R-0 R-0 R-0 R-0
7:0
LROW VSYNC HSYNC DE ACTIVE
Legend:

bit 5 LROW: Last Row bit
1 = Last row is currently being displayed
0 = Last row is not currently being displayed
bit 3 VSYNC: VSYNC Signal Level bit

This bit returns the VSYNC signal level.
bit 2 HSYNC: HSYNC Signal Level bit

This bit returns the HSYNC signal level.
bit 1 DE: DE Signal Level bit

This bit returns the DE signal level.
bit 0 ACTIVE: Active bit

1 = LCD Controller is not in active vertical blanking
0 = LCD Controller is in active vertical blanking

REGISTER 36-17: GLCDCLUTx: GRAPHICS LCD CONTROLLER GLOBAL COLOR LOOKUP TABLE
REGISTER x (x=0-255)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
RED<7:0>
15:8
GREEN<7:0>
7:0
BLUE<7:0>
Legend:

bit 23-16 RED<7:0>: Global Color Lookup Table Red Component bits
bit 15-8 GREEN<7:0>: Global Color Lookup Table Green Component bits
bit 7-0 BLUE<7:0>: Global Color Lookup Table Blue Component bits

REGISTER 36-18: GLCDCURDATAx: GRAPHICS LCD CONTROLLER CURSOR DATA n

REGISTER (n = 0-127)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 (1) (1)
PIXELxy<3:0> PIXELxy<3:0>
23:16 (1)
PIXELxy<3:0> PIXELxy<3:0>(1)
15:8 (1) (1)
PIXELxy<3:0> PIXELxy<3:0>
7:0 (1)
PIXELxy<3:0> PIXELxy<3:0>(1)
Legend:
bit 31-28 PIXELxy<3:0>: Pixel xy Color Lookup bits(1)

Note 1: For the PIXELxy bits, x = 0-31 and y = 0-31 (i.e., GLCDCURDATA0 contains PIXEL00 through PIXEL07
with PIXEL00 in the most significant nibble).

REGISTER 36-19: GLCDCURLUTx: GRAPHICS LCD CONTROLLER CURSOR LUT REGISTER x

(x = 0-15)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
RED<7:0>
15:8
GREEN<7:0>
7:0
BLUE<7:0>
Legend:

bit 23-16 RED<7:0>: Cursor Lookup Table Red Component bit
bit 15-8 GREEN<7:0>: Cursor Lookup Table Green Component bit
bit 7-0 BLUE<7:0>: Cursor Lookup Table Blue Component bit
Note: The bits in this register contain the 8-bit RGB color value (0-255).

37.0 2-D GRAPHICS PROCESSING Key features of the 2-D Graphics Processing Unit
include:
UNIT (GPU)
64-bit bus access to memory (higher throughput)
Note: This data sheet summarizes the features Global clock gating (low power)
of the PIC32MZ Graphics (DA) Family of Command buffers
Programmable raster operations (ROP2, ROP3
and ROP4) with full alpha blending and
complement the information in this data transparency
sheet, refer to the documents listed in the
Fixed Functions:
section of the Microchip PIC32 web site - Line draw
(www.microchip.com/pic32). - Rectangle fill
- Rectangle clear
The 2-D Graphics Processing Unit manipulates and - Bit blit (stretch/shrink/filter)
alters the contents of the frame buffer in system RAM
Source data formats:
or DDR2 memory to accelerate the generation of
images for eventual pixel display. Hardware accelera- - RGB888, RGB555 RGB565, RBG323, and 1-bit
tion is brought to numerous 2-D applications, such as monochrome
graphics user interfaces (menus, objects etc.,), touch Destination data formats:
screen user interfaces, Flash animation and gaming - RGB888, RGB555, and RGB565
among others. YUV to RGB conversion
The 2-D GPU also provides accelerated on-the-fly Dithering
rendering of vertical and horizontal lines, rectangles, Rotation
copying of a rectangular area between different Clipping
locations on the screen, drawing text, and Text rendering
decompressing compressed data on the existing
Note 1: For RGB source formats, their related
display data. Once initiated, the hardware will perform
swizzle formats (ARGB, RGBA, ABGR,
the rendering through DMA, which makes the CPU
BGRA) are also supported.
available for other tasks.
2: The GPU is enabled and ready out of
A block diagram showing the interface for the 2-D
POR. However, the GPU can be soft
Graphics Processing Unit is provided in Figure 37-1.
Reset at run-time using the GPURESET
Note: For this peripheral, no hardware interface bit (CFGAPP2<0>). Make sure that the
is documented. Use the accompanying GPUMD bit is set to '0' and wait 10 s
software driver to manage this module. before toggling the GPURESET bit to
achieve proper soft Reset.
FIGURE 37-1: 2-D GRAPHICS PROCESSING UNIT BLOCK DIAGRAM
Graphics Controller
System Bus 64-bit System Bus CPU Core
Host Interface
Memory Controller
2-D Pipeline
Graphics
Pixel
Pipeline
2-D Drawing and Scaling Engine Engine
Front End

NOTES:

38.0 DDR2 SDRAM CONTROLLER The DDR2 SDRAM Controller implements the controls
for an external memory bus interface using the Dual
Note: This data sheet summarizes the features Data Rate version 2 (DDR2) protocol and electrical
of the PIC32MZ Graphics (DA) Family of interface that adheres to the JEDEC Standard
devices. It is not intended to be a JESD79-2F (Nov. 2009).
comprehensive reference source. To The component consists of a DDR2 SDRAM Controller
complement the information in this data Core with configurable options and a DDR2 Physical
sheet, refer to Section 55. DDR SDRAM Interface.
Controller (DS60001321), which is
available from the Documentation > A block diagram showing how these components
Reference Manual section of the Micro- interface is provided in Figure 38-1.
chip PIC32 web site (www.microchip.com/
pic32).
FIGURE 38-1: DDR2 SDRAM CONTROLLER BLOCK DIAGRAM
MFMPLL DDR2 SDRAM Controller LDO or PMIC

SYSCLK
VDDR1V8 VTT
DDR2
Memory(1)
DDR2-PHY
DDR2 Control DDRVREF
Control Registers
Registers DDRCKE
DDRCK
Target Manager DDRCK
DDRCS0
Target 0 DDRRAS
(CPU)
DDRCAS
DDR2
System Bus
Data PHY DDRWE

Controller DDRA<15:0>
Target 1 Arbiter
Target 2 DDRBA<2:0>
and
(DMA and other FIFOs DDRUDQS
initators) DDRUDQS
DDRLDQS
Target 3 DDRLDQS
Target 4 DDRDQ<15:0>
(GLCD and GPU) DDRUDM
DDRLDM
DDRODT
Note 1: DDR2 memory is internal in 169-pin LFBGA and 176-pin LQFP packages and is external in 288-pin LFBGA packages.

DS60001361E-page 606

TABLE 38-1: DDR SDRAM CONTROLLER REGISTER SUMMARY
Virtual Address
Bits
All Resets
Bit Range
(BF8E_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
DDR 31:16 0000

8000
TSEL 15:0 TSEL<7:0> 0000
DDR 31:16 0000
8004
MINLIM 15:0 MINLIMIT<4:0> 0000
DDR 31:16 0000
8008
RQPER 15:0 RQPER<7:0> 0000
DDR 31:16 0000
800C
MINCMD 15:0 MINCMD<7:0> 0000
DDR 31:16 0000
8010
MEMCON 15:0 INITDN STINIT 0000
AP
DDR 31:16 CLHADDR<4:0> CSADDR<4:0> 0000
8014 CHRGEN
MEMCFG0
15:0 BNKADDR<4:0> RWADDR<4:0> 0000
DDR 31:16 0000
8018
MEMCFG1 15:0 RWADDRMSK<12:0> 0000
DDR 31:16 0000
801C
MEMCFG2 15:0 CLADDRHMSK<12:0> 0000
DDR 31:16 0000
8020
MEMCFG3 15:0 CLADDRLMSK<12:0> 0000
DDR 31:16 0000
8024
MEMCFG4 15:0 CSADDRMSK<2:0> BNKADDRMSK<2:0> 0000
DDR 31:16 MAXREFS<2:0> REFDLY<7:0> 0000
8028
REFCFG 15:0 REFCNT<15:0> 0000
PCHRG
31:16 SLFREFDLY<9:4> 0000
DDR PWRDN
802C
PWRCFG ASLF APWR
15:0 SLFREFDLY<3:0> PWRDNDLY<7:0> 0000
REFEN DNEN
DDR 31:16 RMWDLY<3:0> R2WDLY>3:0> W2WCSDLY<3:0> W2WDLY<3:0> 0000
8030
DLYCFG0 15:0 R2RCSDLY<3:0> R2RDLY<3:0> W2RCSDLY<3:0> W2RDLY<3:0> 0000
SLFREF NXTDAT W2R W2R W2PCHRG
DDR 31:16 PWRDNEXDLY<5:0> PWRDNMINDLY<3:0> 0000
8034 EXDLY8 AVDLY4 CSDLY4 DLY4> DLY4
DLYCFG1
15:0 SLFREFEXDLY<7:0> SLFREFMINDLY<7:0> 0000
DDR 31:16 RBENDDLY<3:0> PCHRG2RASDLY<3:0> RAS2CASDLY<3:0> RAS2RASDLY<3:0> 0000
8038
DLYCFG2 15:0 W2PCHRGDLY<3:0> R2PCHRGDLY<3:0> PCHRGALLDLY<3:0> 0000
DDR 31:16 FAWTDLY<5:0> 0000
803C
DLYCFG3 15:0 RAS2RASSBNKDLY<5:0> RAS2PCHRGDLY<4:0> 0000
DDR 31:16 ODTWLEN<2:0> ODTRLEN<2:0> 0000
8040
ODTCFG 15:0 ODTWDLY<3:0> ODTRDLY<3:0> ODTCSEN<7:0> 0000
BIGEN-
DDR 31:16 MAXBURST<3:0> RDATENDLY<3:0> 0000
8044 DIAN
XFERCFG
15:0 NXTDATAVDLY<3:0> NXTDATRQDLY<3:0> 0000
TABLE 38-1: DDR SDRAM CONTROLLER REGISTER SUMMARY (CONTINUED)
All Resets
Bit Range
(BF8E_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
DDR 31:16 0000

8048
CMDISSUE 15:0 VALID NUMHOSTCMDS<3:0> 0000
DDR 31:16 ODTWEN 0000
804C
ODTENCFG 15:0 ODTREN 0000
31:16 0000
DDR
8050 HALF
MEMWIDTH 15:0 0000
RATE
WEN
31:16 MDALCMD<7:0> CASCMD2 RASCMD2 CSCMD2<7:3> 0000
DDR CMD2
8080
CMD10 CLKEN WEN CLKEN
15:0 CSCMD2<2:0> CASCMD1 RASCMD1 CSCMD1<7:0> 0000
CMD2 CMD1 CMD1
WEN
DDR CMD2
8084

CMD2 CMD1 CMD1
WEN
DDR CMD2
8088
CMD2 CMD1 CMD1
WEN
DDR CMD2
808C
CMD2 CMD1 CMD1
WEN
DDR CMD2
8090
CMD2 CMD1 CMD1
WEN
DDR CMD2
8094
CMD2 CMD1 CMD1
WEN
31:16 MDALCMD<7:0> CASCMD2 RASCMD2 CSCMD<27:3> 0000
DDR CMD2
8098
CMD2 CMD1 CMD1
WEN
DDR CMD2
809C
DS60001361E-page 607

CMD2 CMD1 CMD1
WEN
DDR CMD2
80A0
CMD2 CMD1 CMD1
WEN
DDR CMD2
80A4
CMD2 CMD1 CMD1
DS60001361E-page 608

Virtual Address
Bits
All Resets
Bit Range
(BF8E_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
WEN
DDR CMD2
80A8
CMD2 CMD1 CMD1
WEN
DDR CMD2
80AC
CMD2 CMD1 CMD1
WEN
DDR CMD2
80B0
CMD2 CMD1 CMD1
WEN
DDR CMD2
80B4
CMD2 CMD1 CMD1
WEN
31:16 MDALCMD<7:0> CASCMD2 RASCMD2 CSCMD<27:3> 0000
DDR CMD2
80B8
CMD2 CMD1 CMD1
WEN
DDR CMD2
80BC
CMD2 CMD1 CMD1
DDR 31:16 WAIT<8:5> 0000
80C0
CMD20 15:0 WAIT<4:0> BNKADDRCMD<2:0> MDADDRHCMD<7:0> 0000
DDR 31:16 WAIT<8:5> 0000
80C4
DDR 31:16 WAIT<8:5> 0000
80C8
DDR 31:16 WAIT<8:5> 0000
80CC
DDR 31:16 WAIT<8:5> 0000
80D0
DDR 31:16 WAIT<8:5> 0000
80D4
DDR 31:16 WAIT<8:5> 0000
80D8
DDR 31:16 WAIT<8:5> 0000
80DC
DDR 31:16 WAIT<8:5> 0000
80E0
DDR 31:16 WAIT<8:5> 0000
80E4
All Resets
Bit Range
(BF8E_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
DDR 31:16 WAIT<8:5> 0000

80E8
DDR 31:16 WAIT<8:5> 0000
80EC
DDR 31:16 WAIT<8:5> 0000
80F0
DDR 31:16 WAIT<8:5> 0000
80F4
DDR 31:16 WAIT<8:5> 0000
80F8
DDR 31:16 WAIT<8:5> 0000
80FC

SCL
31:16 SCLEN 0000
DDR START
9100
SCLSTART SCL SCL
15:0 0000
UBPASS LBPASS
DDR 31:16 0000
910C
SCLLAT 15:0 DDRCLKDLY<3:0> CAPCLKDLY<3:0> 0000
DDR 31:16 ODTCSW 0000
9118
SCLCFG0 15:0 RCASLAT<3:0> DDR2 BURST8 0000
31:16 0000
DDR
911C DBL
SCLCFG1 15:0 WCASLAT<3:0> SCLSEN 0000
REFDLY
31:16 PREAMBDLY<1:0> RCVREN DRVSTRPFET<3:0> DRVSTRNFET<3:0> 0000
DDR
9120 HALF WR NOEXT EOEN ADDC DAT
PHYPADCON 15:0 ODTPUCAL<1:0> ODTPDCAL<1:0> ODTEN ODTSEL 0000
RATE CMDDLY DLL CLKCYC DRVSEL DRVSEL
DIS
DDR 31:16 DLYSTVAL<3:0> RECALIBCNT<17:8> 0000
9124 RECALIB
PHYDLLR
15:0 RECALIBCNT<7:0> 0000
9140 31:16 0000
DDR
PHYCLKDLY SCL SCL
15:0 CLKDLYDELTA<2:0> 0000
UBPASS LBPASS
DS60001361E-page 609
REGISTER 38-1: DDRTSEL: DDR TARGET SELECT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
TSEL<7:0>
Legend:

bit 7-0 TSEL<7:0>: Target Select bits
These bits select the target to program arbitration parameters. This field must be set before an arbitration
parameter is programmed for a target. The value in this field represents the target number (0-4) multiplied
by the field size of the arbitration parameter.

REGISTER 38-2: DDRMINLIM: DDR MINIMUM BURST LIMIT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
MINLIMIT<4:0>
Legend:

bit 4-0 MINLIMIT<4:0>: Minimum Burst Limit bits
These bits determine the minimum number of DDR bursts (two cycles per burst) that a target must have
uninterrupted access to without interference from another target.
Note: The TSEL<7:0> bits (DDRTSEL<7:0>) must be programmed with the target number multiplied by the size of
the MINLIMIT field (5) before this register is used to program the minimum burst limit for that target.

REGISTER 38-3: DDRRQPER: DDR REQUEST PERIOD REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
RQPER<7:0>
Legend:

bit 7-0 RQPER<7:0>: Request Period bits
These bits in conjunction with the MINCMD<7:0> bits (DDRMINCMD<7:0>), determine the percentage of
total bandwidth that is allocated to the target. If the number of DDR bursts specified by MINCMD<7:0> are
not serviced for the target when it has been requesting access for (RQPER<7:0> * 4) number of clocks, the
target's requests are treated with high priority until this condition becomes satisfied.

REGISTER 38-4: DDRMINCMD: DDR MINIMUM COMMAND REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
MINCMD<7:0>
Legend:

bit 7-0 MINCMD<7:0>: Minimum Command bits
These bits in conjunction with the RQPER<7:0> bits (DDRRQPER<7:0>) determine the percentage of total
bandwidth that is allocated to the target. If the number of DDR bursts specified by MINCMD<7:0> are not
serviced for the target when it has been requesting access for (RQPER<7:0> * 4) number of clocks, then
the target's requests are treated with high priority until this condition becomes satisfied.

REGISTER 38-5: DDRMEMCON: DDR MEMORY CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
7:0
INITDN STINIT
Legend:

bit 1 INITDN: Memory Initialize Done bit
Set by software after memory initialization is completed to enable controller for regular operation.
1 = All commands have been issued; the controller is enabled for regular operation
0 = Controller not enabled for regular operation
bit 0 STINIT: Memory Initialize Start bit
Set by software after the memory initialization commands are loaded into the DDRCMD registers to start
memory initialization.
1 = Start memory initialization
0 = Do not start memory initialization

REGISTER 38-6: DDRMEMCFG0: DDR MEMORY CONFIGURATION REGISTER 0

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
APCHRGEN CLHADDR<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
CSADDR<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
BNKADDR<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RWADDR<4:0>
Legend:

bit 30 APCHRGEN: Automatic Precharge Enable bit
When set, this bit issues an auto-precharge command to close the bank at the end of every user
command. If the command accesses more than one bank before completing, all banks accessed are auto-
precharged.
1 = Issue an auto-precharged command
0 = Do not issue an auto-precharged command
bit 28-24 CLHADDR<4:0>: Column Address Shift bits
These bits specify how many bits the controller address must be right-shifted to put the high part of the col-
umn address to the immediate left of the low part of the column address. Used in conjunction with CLAD-
DRHMSK (DDRMEMCFG2<26:0>) and CLADDRLMASK (DDRMEMCFG3<26:0>).
bit 20-16 CSADDR<4:0>: Chip Select Shift bits
These bits specify which bits of user address space are used to derive the Chip Select address for the
DDR memory. Used in conjunction with CSADDRMASK (DDRMEMCFG4<10:8>).
bit 12-8 BNKADDR<4:0>: Bank Address Select Shift bits
These bits specify which bits of user address space are used to derive the bank address for the DDR
memory. Used in conjunction with BNKADDRMASK (DDRMEMCFG4<2:0>).
bit 4-0 RWADDR<4:0>: Row Address Select Shift bits
These bits specify which bits of user address space are used to derive the row address for the DDR mem-
ory. Used in conjunction with RWADDRMSK (DDRMEMCFG1<12:0>).


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
RWADDRMSK<12:8>
7:0
RWADDRMSK<7:0>
Legend:

bit 12-0 RWADDRMSK<12:0>: Row Address Mask bits
These bits, which are used in conjunction with the RWADDR<4:0> bits (DDRMEMCFG0<4:0>), specify
which bits of user address space are used to derive the row address for the DDR memory.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CLADDRHMSK<12:8>
7:0
CLADDRHMSK<7:0>
Legend:

bit 12-0 CLADDRHMSK<12:0>: Column Address High Mask bits
These bits, which are used in conjunction with the CLADDR<4:0> bits (DDRMEMCFG0<28:24>) and the
CLADDRLMASK<12:0> bits (DDRMEMCFG3<12:0>), specify which bits of user address space are used
to derive the column address for the DDR memory.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CLADDRLMSK<12:8>
7:0
CLADDRLMSK<7:0>
Legend:

bit 12-0 CLADDRLMSK<12:0>: Column Address Low Mask bits
These bits, which are used in conjunction with the CLADDR<4:0> bits (DDRMEMCFG0<28:24>) and the
CLADDRHMASK<12:0> bits (DDRMEMCFG2<12:0>), specify which bits of user address space are used
to derive the column address for the DDR memory.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
15:8
CSADDRMSK<2>
R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
7:0
CSADDRMSK<1:0> BNKADDRMSK<2:0>
Legend:

bit 8-6 CSADDRMSK<2:0>: Chip Select Address Mask bits
These bits, which are used in conjunction with the CSADDR<4:0> bits (DDRMEMCFG0<20:16>), deter-
mine which bits of user address space are used to derive the Chip Select address for the DDR memory.
bit 2-0 BNKADDRMSK<2:0>: Bank Address Mask bits
These bits, which are used in conjunction with the BNKADDR<4:0> bits (DDRMEMCFG0<12:8>), deter-
mine which bits of user address space are used to derive the bank address for the DDR memory.

REGISTER 38-11: DDRREFCFG: DDR REFRESH CONFIGURATION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
MAXREFS<2:0>
23:16
REFDLY<7:0>
15:8
REFCNT<15:8>
7:0
REFCNT<7:0>
Legend:

bit 26-24 MAXREFS<2:0>: Maximum Pending Refreshes bits
These bits specify the maximum number of refreshes that may be pending at any time. If there is any idle
time when one or more refreshes are pending, the pending refreshes are issued continuously until a new
request is received. If there is no idle time while MAXREFS <2:0> refreshes are pending, subsequent
requests are stopped until at least one burst of pending refreshes can be issued.
bit 23-16 REFDLY<7:0>: Minimum Refresh-to-Refresh Delay bits
These bits specify the minimum number of clocks required between refreshes.
bit 15-0 REFCNT<15:0>: Refresh Count bits
These bits specify the number of clock cycles corresponding to the average periodic refresh interval.

REGISTER 38-12: DDRPWRCFG: DDR POWER CONFIGURATION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
PCHRGPWRDN SLFREFDLY<9:4>
15:8
SLFREFDLY<3:0> PWDNDLY<7:4>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
7:0
PWDNDLY<3:0> ASLFREFEN APWRDNEN
Legend:

bit 22 PCHRGPWDN: Precharge Power Down Only bit
Allow automatic entry into Precharge Power Down mode but not into active Power Down mode. If any rows
are open they will be Precharged before DDR SDRAM is put into Precharge Power Down mode.
1 = Allow automatic entry into Precharge Power Down mode.
0 = Do not allow automatic entry into Precharge Power Down mode.
bit 21-12 SLFREFDLY<9:0>: Self Refresh Delay bits
Specifies the minimum number of clock cycles of idle time the controller needs to wait before automatic
entry into Self Refresh mode. Value represents number of clocks multiplied by 1024.
111111111 = 2111452 clocks
.
000000001 = 1024 clocks
bit 11-4 PWDNDLY<7:0>: Refresh Count bits
Specifies the minimum number of clock cycles of idle time the controller needs to wait before automatic entry
into Power Down mode (Active or Precharge). Value represents number of clocks multiplied by 4.
11111111 = 1020 clocks
.
00000001 = 4 clocks
bit 3 ASLFREFEN: Automatic Self Refresh Enable bit
1 = Allow automatic entry into Self Refresh mode.
0 = Do not allow automatic entry into Self Refresh mode.
bit 2 APWRDNEN: Automatic Power Down Enable bit
1 = Allow automatic entry into Power Down mode.
0 = Do not allow automatic entry into Power Down mode.

REGISTER 38-13: DDRDLYCFG0: DDR DELAY CONFIGURATION REGISTER 0

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
RMWDLY<3:0> R2WDLY<3:0>
23:16
W2WCSDLY<3:0> W2WDLY<3:0>
15:8
R2RCSDLY<3:0> R2RDLY<3:0>
7:0
W2RCSDLY<3:0> W2RDLY<3:0>
Legend:
bit 31-28 RMWDLY<3:0>: Read-Modify-Write Delay bits

These bits specify the minimum number of clocks required between the read and write commands issued
for a read-modify-write operation.
bit 27-24 R2WDLY<3:0>: Read-to-Write Delay bits
These bits specify the minimum number of clocks required between a read command and write command.
Commands may be to the same or different Chip Selects.
bit 23-20 W2WCSDLY<3:0>: Write-to-Write Chip Select Delay bits
These bits specify the minimum number of clocks required between two write commands to different Chip
Selects.
bit 19-16 W2WDLY<3:0>: Write-to-Write Delay bits
These bits specify the minimum number of clocks required between two write commands to the same Chip
Select.
bit 15-12 R2RCSDLY<3:0>: Read-to-Read Chip Select Delay bits
These bits specify the minimum number of clocks required between two read commands to different Chip
Selects.
bit 11-8 R2RDLY<3:0>: Read-to-Read Delay bits
These bits specify the minimum number of clocks required between two read commands to the same Chip
Select.
bit 7-4 W2RCSDLY<3:0>: Write-to-Read Chip Select Delay bits
These bits specify the minimum number of clocks required between a write command and a read com-
mand to different Chip Selects.
bit 3-0 W2RDLY<3:0>: Write-to-Read Delay bits
These bits specify the minimum number of clocks required between a write command and a read com-
mand to the same Chip Select.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24 SLFREF NXTDAT W2RCS W2PCHRG-
W2RDLY<4> PWRDNEXDLY<5:4>
EXDLY<8> AVDLY<4> DLY<4> DLY<4>
23:16
PWRDNEXDLY<3:0> PWRDNMINDLY <3:0>
15:8
SLFREFEXDLY<7:0>
7:0
SLFREFMINDLY<7:0>
Legend:

bit 30 SLFREFEXDLY: Self Refresh Exit Delay bit 8
This bit specifies the minimum number of clocks required before normal operation after exiting Self Refresh
mode.
bit 29 NXTDATAVDLY: Next Data Available Delay bit 4
These bits specify the minimum number of clock cycles required between a Write command and the write
data transfer handshake signal next data request. Also, see the NXTDATAVDLY<3:0> bits
(DDRXFERCFG<7:4>).
bit 28 W2RCSDLY: Write-to-Read Chip Select Delay bit 4
This bit specify the minimum number of clocks required between a write command and a read command to
different Chip Selects. Also, see W2RCSDLY<3:0> (DDRDLYCFG0<7:4>).
bit 27 W2RDLY: Write-to-Read Delay bit 4
This bit specifies the minimum number of clocks required between a write command and a read command
to the same Chip Select. Also, see W2RDLY<3:0> (DDRDLYCFG0<3:0>).
bit 26 W2PCHRGDLY: Write to Precharge Delay bit 4
These bits specify the minimum number of clocks required from a Write command to a Precharge com-
mand to the same bank as the write. Also, see WPCHRGDLY<3:0> (DDRDLYCFG2<15:12>).
bit 25-20 PWRDNEXDLY<5:0>: Power Down Exit Delay bits
These bits specify the minimum number of clocks required before normal operation after exiting Power Down
mode.
bit 19-16 PWRDNMINDLY<3:0>: Power Down Minimum Delay bits
These bits specify the minimum number of clocks to stay in Power Down mode after entering it.
bit 15-8 SLFREFEXDLY<7:0>: Self Refresh Exit Delay bits
These bits specify the minimum number of clocks required before normal operation after exiting Self Refresh
mode.
bit 7-0 SLFREFMINDLY<7:0>: Self Refresh Minimum Delay bits
These bits specify the minimum number of clocks to stay in Self Refresh mode after entering it.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
RBENDDLY<3:0> PCHRG2RASDLY<3:0>
23:16
RAS2CASDLY<3:0> RAS2RASDLY <3:0>
15:8
W2PCHRGDLY<3:0> R2PCHRGDLY<3:0>
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
PCHRGALLDLY<3:0>
Legend:
bit 31-28 RBENDDLY<3:0>: Read Burst End Delay bits

These bits specify the minimum number of clocks required from issue of a Read command to the read data
burst completion.
bit 27-24 PCHRG2RASDLY<3:0>: Precharge-to-RAS Delay bits
These bits specify the minimum number of clocks required from a Precharge command to a RAS command
to the same bank.
bit 23-20 RAS2CASDLY<3:0>: RAS-to-CAS Delay bits
These bits specify the minimum number of clocks required from a RAS command to a CAS command to
the same bank.
bit 19-16 RAS2RASDLY<3:0>: Write-to-Read Delay bits
These bits specify the minimum number of clocks required from a RAS command to a RAS command to a
different bank on the same Chip Select.
bit 15-12 W2PCHRGDLY<3:0>: Write-to-Precharge Delay bits 3-0
These bits specify the minimum number of clocks required from a Write command to a Precharge command
to the same bank as the write.
An overflow bit (DDRDLYCFG1<26>) is provided for delays greater than 15 clock cycles.
bit 11-8 R2PCHRGDLY<3:0>: Read-to-Precharge Delay bits
These bits specify the minimum number of clocks required from a read command to a Precharge command
to the same bank as the read.
bit 3-0 PCHRGALLDLY<3:0>: Precharge All Delay bits
These bits specify the minimum number of clocks required from a Precharge all banks command to an
Activate or Refresh command.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
FAWTDLY<5:0>
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
RAS2RASSBNKDLY<5:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RAS2PCHRGDLY<4:0>
Legend:

bit 21-16 FAWTDLY<5:0>: Four Activate Window Time Delay bits
These bits specify the minimum number of clocks within which only four banks may be opened.
bit 13-8 RAS2RASSBNKDLY<5:0>: RAS-to-RAS Same Bank Delay bits
These bits specify the minimum number of clocks required between RAS commands to the same bank.
bit 4-0 RAS2PCHRGDLY<4:0>: RAS-to-Precharge Delay bits
These bits specify the minimum number of clocks required from a RAS command to a Precharge command
to the same bank.

REGISTER 38-17: DDRODTCFG: DDR ON-DIE TERMINATION CONFIGURATION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
23:16
ODTWLEN<2:0> ODTRLEN<2:0>
15:8
OTDWDLY<3:0> OTDRDLY<3:0>
7:0
OTDCSEN<7:0>
Legend:

bit 22-20 ODTWLEN<2:0>: On-Die Termination Write Length bits
These bits specify the number of clocks ODT is turned on for writes.
bit 18-16 ODTRLEN<2:0>: On-Die Termination Read Length bits
These bits specify the number of clocks ODT is turned on for reads.
bit 15-12 ODTWDLY<3:0>: On-Die Termination Write Delay bits
These bits specify the number of clocks after a Write command before turning on ODT to the DDR.
bit 11-8 ODTRDLY<3:0>: On-Die Termination Read Delay bits
These bits specify the number of clocks after a Read command before turning on ODT to the DDR.
bit 7-0 ODTCSEN<7:0>: On-Die Termination Chip Select Enable bits
These bits are used with the DDRODTENCFG register (Register 38-20) to program the ODT control for
each Chip Select. The value in this field represents the number of Chip Selects multiplied by the Chip
Select number to be programmed.

REGISTER 38-18: DDRXFERCFG: DDR TRANSFER CONFIGURATION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0
31:24
BIGENDIAN MAXBURST<3:0>
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
RDATENDLY<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

7:0
NXTDATAVDLY<3:0> NXTDATRQDLY<3:0>
Legend:
bit 31 BIGENDIAN: Big Endian bit

1 = Data is big endian format
0 = Data is little endian format
bit 27-24 MAXBURST<3:0>: Maximum Command Burst Count bits
These bits specify the maximum number of commands that can be written to the DDR controller in Burst
mode.
bit 19-16 RDATENDLY<3:0>: PHY Read Data Enable Delay bits
These bits specify the minimum number of clocks Required between issuing a Read command to the PHY
and when the read data enable signal to the PHY is asserted.
bit 7-4 NXTDATAVDLY<3:0>: Next Data Available Delay bits
These bits specify the minimum number of clock cycles required between issuing a Read command and
the read data being received.
bit 3-0 NXTDATRQDLY<3:0>: Next Data Request Delay bits
These bits specify the minimum number of clock cycles required between issuing a Write command and
the write data transfer handshake signal next data request.

REGISTER 38-19: DDRCMDISSUE: DDR COMMAND ISSUE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0
7:0
VALID NUMHOSTCMDS<3:0>


bit 4 VALID: Host Command Valid bit
When written with a '1', this bit indicates to the controller that the data in the Host command registers are
valid, and should be transmitted to the SDRAM. This bit is cleared by hardware when all data has been
transmitted.
bit 3-0 NUMHOSTCMDS<3:0>: Number of Host Commands bits
The number of Host commands to be transmitted to the SDRAM.

REGISTER 38-20: DDRODTENCFG: DDR ON-DIE TERMINATION ENABLE CONFIGURATION

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
23:16
ODTWEN
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
7:0
ODTREN
Legend:

bit 16 ODTWEN: On-Die Termination Write Enable bit
1 = The Chip Select represented by the OTDCSEN<7:0> bits (DDRODTCFG<7:0>) has ODT enabled for
data reads
0 = The Chip Select represented by the OTDCSEN<7:0> bits (DDRODTCFG<7:0>) has ODT disabled for
data reads
bit 0 ODTREN: On-Die Termination Read Enable bit
1 = The Chip Select represented by the OTDCSEN<7:0> bits (DDRODTCFG<7:0>) has ODT enabled for
data writes
0 = The Chip Select represented by the OTDCSEN<7:0> bits (DDRODTCFG<7:0>) has ODT disabled for
data writes

REGISTER 38-21: DDRMEMWIDTH: DDR MEMORY WIDTH REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
7:0
HALFRATE
Legend:

bit 3 HALFRATE: Half-rate Mode bit
The PIC32 always operates in Half-rate mode. This bit must be set during initialization.
1 = Half-rate mode
0 = Full-rate mode

REGISTER 38-22: DDRCMD1x: DDR HOST COMMAND 1 REGISTER x (x = 0 THROUGH 15)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
MDALCMD<7:0>
23:16
WENCMD2 CASCMD2 RASCMD2 CSCMD2<7:3>
15:8
CSCMD2<2:0> CLKENCMD2 WENCMD1 CASCMD1 RASCMD1 CSCMD1<7>
7:0
CSCMD1<6:0> CLKENCMD1
Legend:
bit 31-24 MDALCMD<7:0>: Mode Address Low Command bits

These bits specify the value to be driven on the SDRAM address bits 7 through 0 when issuing the command.
bit 23 WENCMD2: Write Enable Command 2 bit
This bit specifies the value to be driven on WE_N on the second and subsequent cycles of issuing the com-
mand
bit 22 CASCMD2: Column Address Strobe Command 2 bit
This bit specifies the value to be driven on CAS_N on the second and subsequent cycles of issuing the com-
mand
bit 21 RASCMD2: Row Address Strobe Command 2 bit
This bit specifies the value to be driven on RAS_N on the second and subsequent cycles of issuing the com-
mand
bit 20-13 CSCMD2<7:0>: Chip Select Command 2 bits
These bits specify the value to be driven on the CS_N signals (maximum of 8) on the second and subsequent
cycles of issuing the command.
bit 12 CLKENCMD2: Clock Enable Command 2 bit
This bit specifies the value to be driven on CKE on the second and subsequent cycles of issuing the com-
mand.
bit 11 WENCMD1: Write Enable Command 1 bit
This bit specifies the value to be driven on the WE_N on the first cycle of issuing the command.
bit 10 CASCMD1: Column Address Strobe Command 1 bit
This bit specifies the value to be driven on the CAS_N on the first cycle of issuing the command.
bit 9 RASCMD1: Row Address Strobe Command 1 bit
This bit specifies the value to be driven on the RAS_N on the first cycle of issuing the command.
bit 8-1 CSCMD1<7:0>: Chip Select Command 1 bit
These bits specify the value to be driven on the CS_N signals (maximum of 8) on the first cycle of issuing the
command.
bit 0 CLKENCMD1: Clock Enable Command 1 bit
This bit specifies the value to be driven on CKE on the first cycle of issuing the command.

REGISTER 38-23: DDRCMD2x: DDR HOST COMMAND 2 REGISTER x (x = 0 THROUGH 15)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
WAIT<8:5>
15:8
WAIT<4:0> BNKADDRCMD<2:0>
7:0
MDADDRHCMD<7:0>
Legend:

bit 19-11 WAIT<8:0>: Wait Command bits
These bits specify the number of clock cycles to wait after issuing a command before issuing the next
command.
bit 10-8 BNKADDRCMD<2:0>: Bank Address Command bit
These bits specify the value to be driven on the bank address bits when issuing the command.
bit 7-0 MDADDRHCMD<7:0>: Mode Address High Command bits
These bits specify the value to be driven on the SDRAM address bits 15 through 8 when issuing the
command.

REGISTER 38-24: DDRSCLSTART: DDL SELF CALIBRATION LOGIC START REGISTER

Bit Bit Bit
Bit Bit Bit Bit Bit Bit
29/21/13/ 27/19/11/ 26/18/10/
Range 31/23/15/7 30/22/14/6 28/20/12/4 25/17/9/1 24/16/8/0
5 3 2
U-0 U-0 U-0 R/W-0 U-0 W-0 U-0 R/W-0
31:24
SCLSTART SCLEN
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-0 R-0
7:0 SCLUBPASS(1) SCLLB-
PASS(1)
Legend:

bit 28 SCLSTART: Start Self Calibration Logic bit
1 = Start self calibration
0 = Do not start self calibration
bit 26 SCLEN: Self Calibration Logic Enable bit
1 = Enable dynamic self calibration logic
0 = Disable dynamic self calibration logic
bit 1 SCLUBPASS: Self Calibration Logic Upper Data Byte Status bit(1)
1 = Self calibration logic for upper data byte is passed
0 = Self calibration logic for upper data byte is failed
bit 0 SCLLBPASS: Self Calibration Logic Lower Data Byte Status bit(1)
1 = Self calibration logic for lower data byte is passed
Note 1: This bit is set by hardware when the SCL process has passed and is complete.

REGISTER 38-25: DDRSCLLAT: DDL SELF CALIBRATION LOGIC LATENCY REGISTER
Bit Bit Bit
Bit Bit Bit Bit Bit Bit
29/21/13/ 27/19/11/ 26/18/10/
Range 31/23/15/7 30/22/14/6 28/20/12/4 25/17/9/1 24/16/8/0
5 3 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R/W-0 R/W-1 R/W-1 R/W-0 U-0 U-0 R/W-1 R/W-0
7:0
DDRCLKDLY<3:0> CAPCLKDLY<3:0>
Legend:

bit 7-4 DDRCLKDLY<3:0>: DDR Clock Delay bit
Recommended value is 4.
bit 3-0 CAPCLKDLY<3:0>: Capture Clock Delay bit
Recommended value is 3.

REGISTER 38-26: DDRSCLCFG0: DDR SCL CONFIGURATION REGISTER 0

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1
31:24
ODTCSW
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R/W-1 R/W-0 R/W-1 R/W-1 U-0 U-0 R/W-0 R/W-1
7:0
RCASLAT<3:0> DDR2 BURST8
Legend:

bit 24 ODTCSW: On-Die Termination Chip Select Write bit
1 = ODT is turned on to the DRAM on CS0 during writes performed by the SCL
0 = ODT is turned off to the DRAM on CS0 during writes performed by the SCL.
bit 7-4 RCASLAT<3:0>: Read CAS Latency bits
DRAM read CAS latency in clock cycles
bit 1 DDR2: DDR2 bit
1 = DDR2 is connected
0 = DDR2 is not connected
bit 0 BURST8: PHY Burst 8 bit
1 = DRAM is in burst 8 mode while running SCL test
0 = DRAM is in burst 4 mode while running SCL test

REGISTER 38-27: DDRSCLCFG1: DDR SCL CONFIGURATION REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
15:8
DBLREFDLY WCASLAT<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1
7:0
SCLCSEN
Legend:

bit 12 DBLREFDLY: Double Reference Delay bit
Determines whether the PHY will delay an SCL operation following an acknowledge by one or two time
intervals. The time interval is a function of the hardware design.
1 = SCL operation delay doubled
0 = SCL operation delay not doubled
bit 11-8 WCASLAT<3:0>: Write CAS Latency bits
DRAM write CAS latency in clock cycles.
bit 0 SCLCSEN: SCL Chip Select Enable bit
1 = Run SCL on Chip Select 0
0 = Do not run SCL on Chip Select 0

REGISTER 38-28: DDRPHYPADCON: DDR PHY PAD CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 R/W-1 R/W-0 R/W-1 U-0 U-0 U-0 U-0
31:24
PREAMBDLY<1:0> RCVREN
23:16
DRVSTRPFET<3:0> DRVSTRNFET<3:0>
U-0 R/W-1 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8 WR EOEN
HALFRATE NOEXTDLL
CMDDLY CLKCYC
7:0 ADDC DAT
ODTPUCAL<1:0> ODTPDCAL<1:0> ODTEN ODTSEL
DRVDLY DRVSEL
Legend:

bit 30-29 PREAMBDLY<1:0>: Preamble Delay bits
Controls the length of the preamble for writes.
11 = Reserved
10 = 1 cycle preamble
01 = 1.5 cycle preamble
00 = 2 cycle preamble
bit 28 RCVREN: Receiver Enable bit
1 = Pad receivers on bidirectional I/Os are turned on
0 = Pad receivers on bidirectional I/Os are turned off
bit 23-20 DRVSTRPFET<3:0>: PFET Drive Strength bits
Pad PFET driver output impedance adjustment control
1111 = Maximum drive strength

0000 = Minimum drive strength.
bit 19-16 DRVSTRNFET<3:0>: NFET Drive Strength bits
Pad NFET driver output impedance adjustment control
1111 = Maximum drive strength

0000 = Minimum drive strength.
bit 14 HALFRATE: Half Rate bit
1 = Controller clock is running at half rate with respect to PHY
0 = Controller clock is running at full rate with respect to PHY
bit 13 WRCMDDLY: Write Command Delay bit
This bit should be set to 1 if Write Latency (WL) is an even number.
1 = Write command delay
0 = No Write command delay

REGISTER 38-28: DDRPHYPADCON: DDR PHY PAD CONTROL REGISTER (CONTINUED)
bit 9 NOEXTDLL: No External DLL bit
1 = Use internal digital DLL.
0 = Use external DLL.
bit 8 EOENCLKCYC: Extra Output Enable bit
1 = Drive pad output enables for an extra clock cycle after a write burst
0 = Do not drive pad output enables for an extra clock cycle after a write burst
bit 7-6 ODTPUCAL<1:0>: On-Die Termination Pull-up Calibration bits
11 = Maximum ODT impedance

00 = Minimum ODT impedance
bit 5-4 ODTPFDCAL<1:0>: On-Die Termination Pull-down Calibration bits
11 = Maximum ODT impedance

00 = Minimum ODT impedance
bit 3 ADDCDRVSEL: Address and Control Pads Drive Strength Select bit
1 = Full drive strength
0 = 60% driver strength
bit 2 DATDRVSEL: Data Pad Drive Strength Select bit
1 = Full Drive Strength
0 = 60% Drive Strength
bit 1 ODTEN: On-Die Termination Enable bit
1 = ODT Enabled
0 = ODT Disabled
bit 0 ODTSEL: On-Die Termination Select bit
1 = 150 ohm On-Die Termination
0 = 75 ohm On-Die Termination

REGISTER 38-29: DDRPHYDLLR: DDR PHY DLL RECALIBRATE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
31:24
DLYSTVAL<3:0> DISRECALIB RECALIBCNT<17:16>
23:16
RECALIBCNT<15:8>
15:8
RECALIBCNT<7:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0

Legend:
bit 31-28 DLYSTVAL<3:0>: Delay Start Value bits

Start value of the digital DLL master delay line. Recommended value is 0011.
bit 26 DISRECALIB: Disable Recalibration bit
1 = Do not recalibrate the digital DLL after the first time
0 = Recalibrate the digital DLL in accordance with the value of the RECALIBCNT<17:0> bits
bit 25-8 RECALIBCNT<17:0>: Recalibration Count bits
Determines the period of recalibration of the digital DLL in units of (256 * PHY clock cycles).

REGISTER 38-30: DDRPHYCLKDLY: DDR CLOCK DELTA DELAY REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0
7:0
SCLUBPASS(1) SCLLBPASS(1) CLKDLYDELTA<2:0>
Legend:

bit 5 SCLUBPASS: Self Calibration Logic Upper Data Byte Status bit (1)
1 = Self calibration logic for upper data byte is passed
0 = Self calibration logic for upper data byte is failed
bit 4 SCLLBPASS: Self Calibration Logic Lower Data Byte Status bit(1)
0 = Self calibration logic for lower data byte is failed
bit 2-0 CLKDLYDELTA<2:0>: DDR Clock Delay Delta bits
These bits indicate the SCL latency setting programmed per byte lane.
111 = 7 DDR clocks
110 = 6 DDR clocks

000 = 0 DDR clocks
Note: These bits are automatically programmed by the SCL logic and can also be programmed by the
user. This bit is specifically useful in case of SCL retires.
Note 1: These bits indicate the same status as the SCLLBPASS (DDRSCLSTART<0>) and
SCLUBPASS (DDRSCLSTART<0>) bits.

39.0 SECURE DIGITAL HOST - SD Host Controller Simplified Specification,
version 2.00
CONTROLLER (SDHC)
- Physical Layer Simplified Specification,
Note: This data sheet summarizes the features version 2.00
of the PIC32MZ Graphics (DA) Family - SDIO Simplified Specification, version 2.00
family of devices. It is not intended to be a eMMC Standard: JESD84-A441
Default and High-Speed modes of operation
sheet, refer to Section 57. Secure Digi- 1-bit or 4-bit data transfers
tal Host Controller (SDHC) Built-in clock divider
(DS60001334), which is available from PIO and ADMA modes of data transfer
the Documentation > Reference Manual 3.3V operation
section of the Microchip PIC32 web site Interrupt support
Stop at block gap
The SDHC module uses a 32-bit System Bus master A block diagram of the SDHC module is provided in
and slave interface to connect the Host system and Figure 39-1.
standard card interface on the device side.
Note: Transmit and receive buffer addresses in
The core has a built-in DMA controller so that data can ADMA mode should be word-aligned.
be automatically transferred between system memory When multiple descriptors are used to
and the SD/SDIO/eMMC card without intervention from transfer a single block, all but the last
the CPU. descriptor should have a transfer size in
The SDHC module includes the following features: multiples of four.
SD Association specification compliance:
FIGURE 39-1: SECURE DIGITAL HOST CONTROLLER (SDHC) BLOCK DIAGRAM
SDHC Host SDWP

Slave System Bus Control State
Registers Machine SDCD
System Bus
SDCMD
SDCK
Master System Bus DMA Engine TX/RX
Engine
SDDATA0
FIFOs SDDATA1
REFCLKO4(1) Clock Control SDDATA2

PBCLK5(2) and Clock Tuning
SDDATA4
Note 1: When configuring the REFCLKO4 clock source, a value of 0 for the ROTRIM<8:0> bits must be selected. REFCLKO4 must be
turned on before SDHC Special Function Registers (SFR) access.
2: This clock source is only used for SDHC Special Function Register (SFR) access.

DS60001361E-page 642

TABLE 39-1: SDHC SFR SUMMARY
Bits
All Resets
Bit Range
Address
Register
Virtual
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
SDHC 31:16 BCOUNT<15:0> 0000

C004
BLKCON 15:0 BSIZE<9:0> 0000
SDHC 31:16 ARG<31:16> 0000

C008
ARG 15:0 ARG<15:0> 0000
SDHC 31:16 CIDX<5:0> CTYPE<1:0> DPSEL CIDXCEN CCRCCEN RESPTYPE<1:0> 0000

C00C
MODE 15:0 BSEL DTXDSEL ACEN<1:0> BCEN DMAEN 0000
SHDC 31:16 RESP<31:16> 0000

C010
RESP0 15:0 RESP<15:0> 0000
SHDC 31:16 RESP<31:16> 0000

C014
RESP1 15:0 RESP<15:0> 0000
SHDC 31:16 RESP<31:16> 0000

C018
RESP2 15:0 RESP<15:0> 0000
SHDC 31:16 RESP<31:16> 0000

C01C
RESP3 15:0 RESP<15:0> 0000
SHDC 31:16 DATA<31:16> 0000

C020
DATA 15:0 DATA<15:0> 0000
SDHC 31:16 CMDSLVL DATA3SLVL DATA2SLVL DATA1SLVL DATA0SLVL WPSLVL CDSLVL CARDST CARDINS 0000
C024
STAT1 15:0 BREN BWEN RDACTIVE WRACTIVE DLACTIVE CINHDAT CINHCMD 0000
SDHC 31:16 WKONREM WKONINS WKONINT INTBG RDWTCON CONTREQ SBGREQ 0000
C028
CON1 15:0 SDBP CDSSEL CDTLVL DMASEL<1:0> HSEN DTXWIDTH 0000
SDHC 31:16 SWRDATA SWRCMD SWRALL DTOC<3:0> 0000

C02C
CON2 15:0 SDCLKDIV<7:0> SDCLKEN ICLKSTABLE ICLKEN 0000
SDHC 31:16 ADEIF ACEIF CLEIF DEBEIF DCRCEIF DTOEIF CIDXEIF CEBEIF CCRCEIF CTOEIF 0000
C030
INTSTAT 15:0 EIF CARDIF CARDRIF CARDIIF BRRDYIF BWRDYIF DMAIF BGIF TXCIF CCIF 0000
SDHC 31:16 ADEIE AACEIE CLEIE DEBEIE DCRCEIE DTOEIE CIDXEIE CDEBEIE CCRCEIE CTOEIE 0000
C034
INTEN 15:0 FTZIE CARDIE CARDRIE CARDIIE BRRDYIE BWRDYIE DMAIE BGIE TXCIE CCE 0000
SDHC 31:16 ADEISE ACEISE CLEISE DEBEISE DCRCEISE DTOEISE CIDXEISE CEBEISE CEBEISE CCRCEISE 0000
C038
INTSEN 15:0 FTZEISE CARDISE CARDRISE CARDIISE BRRDYISE BWRDYISE DMAISE BGISE TXCISE CCISE 0000
SDHC 31:16 0000

C03C
STAT2 15:0 CNISSE ACIDXE ACEBE ACCRCE ACTOE ACNEXEC 0000
SDHC 31:16 SLOTTYPE<1:0> ASYNCINT VOLT3V3 SRESUME HISPEED ADMA2 MBLEN<1:0> 0000
C040
CAP 15:0 BASECLK<7:0> TOCLKU TOCLKFREQ<5:0> 0000
SDHC 31:16 0000

C048
MAXCAP 15:0 MC3V3<7:0> 0000
31:16 FEAE FEACE FECLE FEDEBE FEDCRCE FEDTOE FEIDXE FECEBE FECCRCE FECTOE 0000
C050 SDHCFE
15:0 FECNIACE FEACIDXE FEACEBE FEACCRCE FEACTOE FEACNEE 0000
Legend: = unimplemented; read as 0.
TABLE 39-1: SDHC SFR SUMMARY (CONTINUED)
Bits
All Resets
Bit Range
Register
Address
Virtual
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
SDHC 31:16 0000

C054
AESTAT 15:0 ALMERR AERRST<1:0> 0000
SDHC 31:16 ADDR<31:16> 0000

C058
AADDR 15:0 ADDR<15:0> 0000
Legend: = unimplemented; read as 0.

DS60001361E-page 643
REGISTER 39-1: SDHCBLKCON: SDHC BLOCK CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
BCOUNT<15:8>(1)
23:16
BCOUNT<7:0>(1)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
BSIZE<9:8>(2)
7:0 (2)
BSIZE<7:0>
Legend:
bit 31-16 BCOUNT<31:0>: Blocks Count for Current Transfer bits(1)

These bits represent the number of blocks. The software sets this value between 1 and 65,535 blocks and
the SDHC decrements the count after each block transfer and stops when the count reaches zero.
0xFFFF = 65,535 blocks
0x0002 = 2 blocks
0x0001 = 1 block
0x0000 = Stop count Blocks Count for Current Transfer bits
bit 9-0 BSIZE<9:0>: Transfer Block Size bits(2)
These bits specify the block size of the data transfer for CMD17, CMD18, CMD24, CMD25, and CMD53.
0x200 = 512 bytes
0x1FF = 511 bytes

0x002 = 2 bytes
0x001 = 1 byte
0x000 = No data transfer
Note 1: These bits are only used when the BCEN bit (SDHCMODE<1>) is set to '1' and is valid only for multiple
block transfers. The BCOUNT<15:0> bits need not be set if the BSIZE bit (SDHCMODE<5>) is set to '0'.
2: These bits can only be accessed when no transactions are in progress. Read operations during transfers
will return an invalid value and write operations to these bits will be ignored.

REGISTER 39-2: SDHCARG: SDHC ARGUMENT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
ARG<31:24>
23:16
ARG<23:16>
15:8
ARG<15:8>
7:0
ARG<7:0>
Legend:
bit 31-0 ARG<31:0>: Command Argument bits

REGISTER 39-3: SDHCMODE: SDHC MODE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
CIDX<5:0>(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
23:16
CTYPE<1:0> DPSEL CIDXCEN(2) CCRCCEN(3) RESPTYPE<1:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
BSEL DTXDSEL ACEN<1:0> BCEN DMAEN
Legend:

bit 29-24 CIDX<5:0>: Command Index bits(1)
These bits represent the command number (0-63).
bit 23-22 CTYPE<1:0>: Command Type bits
11 = Abort
10 = Resume
01 = Suspend
00 = Normal
bit 21 DPSEL: Data Present Select bit
1 = Data is present
0 = Data is not present
bit 20 CIDXCEN: Command Index Check Enable bit(2)
1 = Command index check is enabled
0 = Command index check is disabled
bit 19 CCRCCEN: Command CRC Check Enable bit(3)
1 = Command CRC check is enabled
0 = Command CRC check is disabled
bit 17-16 RESPTYPE<1:0>: Response Type Select bits
11 = Response length 48; check busy after response
10 = Response length 48
01 = Response length 136
00 = No response
bit 5 BSEL: Multiple/Single Block Select bit
1 = Multiple block, set when issuing multiple transfer commands using DAT lines
0 = Single block
Note 1: Refer to bits 45-40 of the command format in the SD Host Controller Simplified Specification (version
2.00).
2: If these bits are set to '1', the SDHC will check the index field in the response to see if it has the same
value as the CIDX<5:0> bits, if not, it will be reported as a command index error.
3: If these bits are set to '1', the SDHC will check the CRC field in the response and reports a command CRC
error upon a CRC error detection.

REGISTER 39-3: SDHCMODE: SDHC MODE REGISTER (CONTINUED)
bit 4 DTXDSEL: Data Transfer Direction Select bit
1 = Read (card to SDHC)
0 = Write (SDHC to card)
bit 3-2 ACEN<1:0>: Auto CMD12 Enable bits
Auto CMD12 is used to stop multiple-block read/write operations.
11 = Reserved
10 = Reserved
01 = Auto CMD12 is enabled
00 = Auto CMD 12 is disabled
bit 1 BCEN: Block Count Enable Bit
1 = Block count is enabled
0 = Block count is disabled
1 = DMA (ADMA) is used to transfer data
0 = CPU is used to transfer data
Note 1: Refer to bits 45-40 of the command format in the SD Host Controller Simplified Specification (version
2.00).
2: If these bits are set to '1', the SDHC will check the index field in the response to see if it has the same
value as the CIDX<5:0> bits, if not, it will be reported as a command index error.
3: If these bits are set to '1', the SDHC will check the CRC field in the response and reports a command CRC
error upon a CRC error detection.

REGISTER 39-4: SDHCRESPx: SDHC RESPONSE REGISTER x (x = 0-3)

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
RESP<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
RESP<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
RESP<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
RESP<7:0>
Legend:
bit 31-0 RESP<31:0>: Response bits

These bits indicate the bit positions of Responses [31:0] defined in the SD Host Controller Simplified
Specification (version 2.00). Refer to Table 39-2 for full bit definitions.
TABLE 39-2: RESPONSE BIT DEFINITION FOR EACH RESPONSE TYPE

Response Type (see Note 1) Response Meaning Response Register
R1, R1b (normal response) Card status SDHCRESP0<31:0>
R1b (Auto CMD12 response) Card status for Auto CMD12 SDHCRESP3<31:0>
R2 (CID, CSD register) CID or CSD register SDHCRESP0<31:0>
SDHCRESP1<31:0>
SDHCRESP2<31:0>
SDHCRESP3<31:0>
R3 (OCR register) OCR register for memory SDHCRESP0<31:0>
R4 (OCR register) OCR register for I/O, etc. SDHCRESP0<31:0>
R5, R5b SDIO response SDHCRESP0<31:0>
R6 (published RCA response) New published RCA<31:16>, etc. SDHCRESP0<31:0>
Note 1: For additional information, refer to the SD Host Controller Simplified Specification (version 2.00), the
Physical Layer Simplified Specification (version 2.00), and the SDIO Simplified Specification (version
2.00). These documents are available for download by visiting the SD Association web site at:
http://www.sdcard.org/downloads/pls/simplified_specs/archive/index.html

REGISTER 39-5: SDHCDATA: SDHC DATA REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
DATA<31:24>
23:16
DATA<23:16>
15:8
DATA<15:8>
7:0
DATA<7:0>
Legend:
bit 31-0 DATA<31:0>: Buffer Data bits

These bits are used to access bits 31 through 0 of the internal data buffer.

REGISTER 39-6: SDHCSTAT1: SDHC STATUS REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-x, HC
31:24
CMDSLVL
R-x, HC R-x, HC R-x, HC R-x, HC R-x, HC R-x, HC R-x, HC R-x, HC
23:16
DATA3SLVL DATA2SLVL DATA1SLVL DATA0SLVL WPSLVL CDSLVL CARDST CARDINS
U-0 U-0 U-0 U-0 R-0, HC R-0, HC R-0, HC R-0, HC
15:8
BREN BWEN RDACTIVE WRACTIVE
U-0 U-0 U-0 U-0 U-0 R-0, HC R-0, HC R-0, HC
7:0
DLACTIVE CINHDAT CINHCMD


bit 24 CMDSLVL: Command Line Signal Level bit
1 = CMD line is high
0 = CMD line is low
bit 23 DATA3SLVL: DATA3 Signal Level bit
1 = DAT3 line is high
0 = DAT3 line is low
bit 19 WPSLVL: Write-protect Signal Level bit
1 = Write-protect is disabled
0 = Write-protect is enabled
bit 18 CDSLVL: Card Detect Signal Level bit
1 = Card is not present
0 = Card is present
bit 17 CARDST: Card State Stable bit
1 = No card or inserted
0 = Reset or debouncing
bit 16 CARDINS: Card Inserted bit
1 = Card inserted
0 = Reset or debouncing or no card
bit 11 BREN: Buffer Read Enable bit
1 = Buffer read is enabled
0 = Buffer read is disabled
Note: This register is used to recover from errors and for debugging.

REGISTER 39-6: SDHCSTAT1: SDHC STATUS REGISTER 1 (CONTINUED)
bit 10 BWEN: Buffer Write Enable bit
1 = Buffer write is enabled
0 = Buffer write is disabled
bit 9 RDACTIVE: Read Transfer Active bit
1 = Data is being transferred
0 = No valid data
bit 8 WRACTIVE: Write Transfer Active bit
1 = Data is being transferred
0 = No valid data
bit 2 DLACTIVE: DAT Line Active bit
1 = DAT line is active
0 = DAT line is inactive
bit 1 CINHDAT: Command Inhibit (DAT) bit
1 = A command that uses the DAT line cannot be issued
0 = A command that uses the DAT line can be issued
bit 0 CINHCMD: Command Inhibit (CMD) bit
1 = A command cannot be issued
0 = A command can only be issued using the CMD line
Note: This register is used to recover from errors and for debugging.

REGISTER 39-7: SDHCCON1: SDHC CONTROL REGISTER 1

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
WKONREM WKONINS WKONINT
U-0 U-0 U-0 U-0 R/W-0 R/W-0 HC, R/W-0 R/W-0
23:16
INTBG RDWTCON CONTREQ SBGREQ
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
15:8
SDBP
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
7:0
CDSSEL CDTLVL DMASEL<1:0> HSEN DTXWIDTH


bit 26 WKONREM: Wake-up Event Enable on SD Card Removal bit
1 = Wake-up event is enabled
0 = Wake-up event is disabled
bit 25 WKONINS: Wake-up Event Enable on SD Card Insertion bit
bit 24 WKONINT: Wake-up Event Enable on SD Card Interrupt bit
bit 19 INTBG: Interrupt at Block Gap bit
bit 18 RDWTCON: Read Wait Control bit
1 = Read wait control is enabled
0 = Read wait control is disabled
bit 17 CONTREQ: Continue Request bit
A write to this bit is ignored if STOPREQ is set to 1.
1 = Restart
0 = No effect
bit 16 SBGREQ: Stop at Block Gap Request bit
1 = Stop
0 = Transfer
bit 8 SDBP: SD Bus Power bit
1 = Bus power is on
0 = Bus power is off
bit 7 CDSSEL: Card Detect Signal Selection bit
1 = The card detect test level is select (for test purposes)
0 = SDCDx is selected (for normal use)
bit 6 CDTLVL: Card Detect Test Level bit
1 = Card is inserted
0 = Card is not inserted

REGISTER 39-7: SDHCCON1: SDHC CONTROL REGISTER 1 (CONTINUED)
bit 4-3 DMASEL<1:0>: DMA Select bits
11 = Reserved
10 = 32-bit address ADMA2 is selected
01 = Reserved
00 = Reserved
bit 2 HSEN: High-Speed Enable bit
1 = High-Speed mode is enabled
0 = Normal Speed mode is enabled
bit 1 DTXWIDTH: Data Transfer Width bit
1 = 4-bit mode
0 = 1-bit mode

REGISTER 39-8: SDHCCON2: SDHC CONTROL REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0, HC R/W-0, HC R/W-0, HC
31:24
SWRDATA SWRCMD SWRALL
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
DTOC<3:0>
15:8
SDCLKDIV<7:0>
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
7:0 ICLK
SDCLKEN ICLKEN
STABLE


bit 26 SWRDATA: Software Reset for DATA Line bit
1 = DMA and part of the data logic are reset
0 = Continue operation
bit 25 SWRCMD: Software Reset for CMD Line bit
1 = Clears Present State and Interrupt Status registers and CMD bits
0 = Continue operation
bit 24 SWRALL: Software Reset for All bit
1 = Issue reset command and reinitialize the SD card
0 = Divided Clock mode is selected
bit 19-16 DTOC<3:0>: Data Time-out Counter Value bits
1111 = Reserved
1110 = Time-out clock x 227

bit 15-8 SDCLKDIV<7:0>: SDCLK Divider Select bits
When 8-bit Divided Clock mode is selected:
0x80 - Base clock divided by 256
0x00 - Base clock
bit 2 SDCLKEN: SD Clock Enable bit
1 = SD clock is enabled
0 = SD clock is disabled
bit 1 ICLKSTABLE: Internal Clock Stable bit
1 = Internal clock is ready
0 = Internal clock is not ready
bit 0 ICLKEN: Internal Clock Enable bit
1 = Oscillate
0 = Stop

REGISTER 39-9: SDHCINTSTAT: SDHC INTERRUPT STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HC R/W-0, HC
31:24
ADEIF ACEIF
R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
23:16
CLEIF DEBEIF DCRCEIF DTOEIF CIDXEIF CEBEIF CCRCEIF CTOEIF
R-0, HC U-0 U-0 U-0 U-0 U-0 U-0 R-0, HC
15:8
EIF CARDIF
7:0
CARDRIF CARDIIF BRRDYIF BWRDYIF DMAIF BGIF TXCIF CEIF


bit 25 ADEIF: ADMA Error Interrupt Flag bit
1 = ADMA error has occurred
0 = ADMA error has not occurred
bit 24 ACEIF: Auto CMD12 Error Interrupt Flag bit
1 = Auto CMD12 error has occurred
0 = Auto CMD12 error has not occurred
bit 23 CLEIF: Current-Limit Error Interrupt Flag bit
1 = Current-limit error has occurred
0 = Current-limit error has not occurred
bit 22 DEBEIF: Data End Bit Error Interrupt Flag bit
1 = Data End bit error has occurred
0 = Data End bit error has not occurred
bit 21 DCRCEIF: Data CRC Error Interrupt Flag bit
1 = Data CRC error has occurred
0 = Data CRC error has not occurred
bit 20 DTOEIF: Data Time-out Error Interrupt Flag bit
1 = Data time-out error has occurred
0 = Data time-out error has not occurred
bit 19 CIDXEIF: Command Index Error Interrupt Flag bit
1 = Command index error has occurred
0 = Command index error has not occurred
bit 18 CEBEIF: Command End Bit Error Interrupt Flag bit
1 = End bit error was generated
0 = End bit error was not generated
bit 17 CCRCEIF: Command CRC Error Interrupt Flag bit
1 = Command CRC error has occurred
0 = Command CRC error has not occurred
bit 16 CTOEIF: Command Time-out Error Interrupt Flag bit
1 = Command time-out error has occurred
0 = Command time-out error has not occurred
bit 15 EIF: Error Interrupt Flag bit
This bit is set if any or all bits, 0 through 9, in this register are set.
1 = Error was detected
0 = No error was detected

REGISTER 39-9: SDHCINTSTAT: SDHC INTERRUPT STATUS REGISTER (CONTINUED)
bit 8 CARDIF: Card Interrupt Status bit
1 = Generate card interrupt
0 = Do not generate card interrupt
bit 7 CARDRIF: Card Removal Interrupt Flag bit
1 = Card has been removed
0 = Card state is stable or debouncing
bit 6 CARDIIF: Card Insertion Interrupt Flag bit
1 = Card has been inserted
0 = Card state is stable or debouncing
bit 5 BRRDYIF: Buffer Read Ready Interrupt Flag bit
1 = Ready to read buffer
0 = Not ready to read buffer
bit 4 BWRDYIF: Buffer Write Ready Interrupt Flag bit
1 = Ready to write buffer
0 = Not ready to write buffer
bit 3 DMAIF: DMA Interrupt Status bit
1 = DMA interrupt was generated
0 = DMA interrupt was not generated
bit 2 BGIF: Block Gap Interrupt Flag bit
1 = Transaction stopped at block gap
0 = No block gap event has occurred
bit 1 TXEIF: Transfer Complete Interrupt Flag bit
1 = Command execution has completed
0 = Command execution has not completed
bit 0 CEIF: Command Complete Interrupt Flag bit
1 = Command is complete
0 = Command is not complete

REGISTER 39-10: SDHCINTEN: SDHC INTERRUPT FLAG ENABLE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HC R/W-0, HC
31:24
ADEFIE ACEFIE
23:16
CLEFIE DEBEFIE DCRCEFIE DTOEFIE CIDXEFIE CDEBEFIE CCRCEFIE CTOEFIE
R-0, HC U-0 U-0 U-0 U-0 U-0 U-0 R-0, HC
15:8
FTZIE CARDIE
7:0
CARDRIE CARDIIE BRRDYIE BWRDYIE DMAIE BGIE TXEIE CEIE


bit 25 ADEFIE: ADMA Interrupt Flag Error Enable bit
1 = ADMA error interrupt flag is enabled
0 = ADMA error interrupt flag is masked
bit 24 ACEFIE: Auto CMD12 Interrupt Flag Error Enable bit
1 = Auto CMD12 error interrupt flag is enabled
0 = Auto CMD12 error interrupt flag is masked
bit 23 CLEFIE: Current-Limit Interrupt Flag Error Enable bit
1 = Current-limit error interrupt flag is enabled
0 = Current-limit error interrupt flag is masked
bit 22 DEBEFIE: Data End Bit Interrupt Flag Error Enable bit
1 = Data End bit error interrupt flag is enabled
0 = Data End error interrupt flag is masked
bit 21 DCRCEFIE: Data CRC Interrupt Flag Error Enable bit
1 = Data CRC error interrupt flag is enabled
0 = Data CRC error interrupt flag is masked
bit 20 DTOEFIE: Data Time-out Interrupt Flag Error Enable bit
1 = Data time-out error interrupt flag is enabled
0 = Data time-out error interrupt flag is masked
bit 19 CIDXEFIE: Command Index Interrupt Flag Error Enable bit
1 = Command index error interrupt flag is enabled
0 = Command index error interrupt flag is masked
bit 18 CDEBEFIE: Command End Bit Interrupt Flag Error Enable bit
1 = Command End bit error interrupt flag is enabled
0 = Command End bit error interrupt flag is masked
bit 17 CCRCEFIE: Command CRC Interrupt Flag Error Enable bit
1 = Command CRC error interrupt flag is enabled
0 = Command CRC error interrupt flag is masked
bit 16 CTOEFIE: Command Time-out Interrupt Flag Error Enable bit
1 = Command time-out error interrupt flag is enabled
0 = Command time-out error interrupt flag is masked
bit 15 FTZIE: Fixed to Zero Interrupt Flag Enable bit

REGISTER 39-10: SDHCINTEN: SDHC INTERRUPT FLAG ENABLE REGISTER (CONTINUED)
bit 8 CARDIE: Card Interrupt Flag Enable bit
1 = Card interrupt flag is enabled
0 = Card interrupt flag is masked
bit 7 CARDRIE: Card Removal Interrupt Flag Enable bit
1 = Card removal interrupt flag is enabled
0 = Card removal interrupt flag is masked
bit 6 CARDIIE: Card Insertion Interrupt Flag Enable bit
1 = Card insertion interrupt flag is enabled
0 = Card insertion interrupt flag is masked
bit 5 BRRDYIE: Buffer Read Ready Interrupt Flag Enable bit
1 = Buffer read ready interrupt flag is enabled
0 = Buffer read ready interrupt flag is masked
bit 4 BWRDYIE: Buffer Write Ready Interrupt Flag Enable bit
1 = Buffer write ready interrupt flag is enabled
0 = Buffer write ready interrupt flag is masked
bit 3 DMAIE: DMA Interrupt Flag Enable bit
1 = DMA interrupt flag is enabled
0 = DMA interrupt flag is masked
bit 2 BGIE: Block Gap Interrupt Flag Enable bit
1 = Block gap event interrupt flag is enabled
0 = Block gap event interrupt flag is masked
bit 1 TXEIE: Transfer Complete Interrupt Flag Enable bit
1 = Transfer complete interrupt flag is enabled
0 = Transfer complete interrupt flag is masked
bit 0 CEIE: Command Complete Interrupt Flag Enable bit
1 = Command complete interrupt flag is enabled
0 = Command complete interrupt flag is masked

REGISTER 39-11: SDHCINTSEN: SDHC INTERRUPT SIGNAL ENABLE REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HC R/W-0, HC
31:24
ADEISE ACEISE
23:16
CLEISE DEBEISE DCRCEISE DTOEISE CIDXEISE CEBEISE CCRCEISE CTOEISE
R-0, HC U-0 U-0 U-0 U-0 U-0 U-0 R-0, HC
15:8
FTZEISE CARDISE
7:0
CARDRISE CARDIISE BRRDYISE BWRDYISE DMAISE BGISE TXEISE CEISE


bit 25 ADEISE: ADMA Error Interrupt Signal Enable bit
1 = ADMA error signal is enabled
0 = ADMA error signal is masked
bit 24 ACEISE: Auto CMD12 Error Interrupt Signal Enable bit
1 = Auto CMD12 error signal is enabled
0 = Auto CMD12 error signal is masked
bit 23 CLEISE: Current-Limit Error Interrupt Signal Enable bit
1 = Current-limit error signal is enabled
0 = Current-limit error signal is masked
bit 22 DEBEISE: Data End Bit Error Interrupt Signal Enable bit
1 = Data end bit error signal is enabled
0 = Data end bit error signal is masked
bit 21 DCRCEISE: Data CRC Error Interrupt Signal Enable bit
1 = Data CRC error signal is enabled
0 = Data CRC error signal is masked
bit 20 DTOEISE: Data Time-out Error Interrupt Signal Enable bit
1 = Data time-out error signal is enabled
0 = Data time-out error signal is masked
bit 19 CIDXEISE: Command Index Error Interrupt Signal Enable bit
1 = Command index error signal is enabled
0 = Command index error signal is masked
bit 18 CEBEISE: Command End Bit Error Interrupt Signal Enable bit
1 = Command End bit error signal is enabled
0 = Command End bit error signal is masked
bit 17 CCRCEISE: Command CRC Error Interrupt Signal Enable bit
1 = Command CRC error signal is enabled
0 = Command CRC error signal is masked
bit 16 CTOEISE: Command Time-out Error Interrupt Signal Enable bit
1 = Command time-out error signal is enabled
0 = Command time-out error signal is masked
bit 15 FTZEISE: Fixed to Zero Error Interrupt Signal Enable bit

REGISTER 39-11: SDHCINTSEN: SDHC INTERRUPT SIGNAL ENABLE REGISTER (CONTINUED)
bit 8 CARDISE: Card Interrupt Signal Enable bit
1 = Card interrupt signal is enabled
0 = Card interrupt signal is masked
bit 7 CARDRISE: Card Removal Interrupt Signal Enable bit
1 = Card removal signal is enabled
0 = Card removal signal is masked
bit 6 CARDIISE: Card Insertion Interrupt Signal Enable bit
1 = Card insertion signal is enabled
0 = Card insertion signal is masked
bit 5 BRRDYISE: Buffer Read Ready Interrupt Signal Enable bit
1 = Buffer read ready signal is enabled
0 = Buffer read ready signal is masked
bit 4 BWRDYISE: Buffer Write Ready Interrupt Signal Enable bit
1 = Buffer write ready signal is enabled
0 = Buffer write ready signal is masked
bit 3 DMAISE: DMA Interrupt Signal Enable bit
1 = DMA interrupt signal is enabled
0 = DMA interrupt signal is masked
bit 2 BGISE: Block Gap Interrupt Signal Enable bit
1 = Block gap event signal is enabled
0 = Block gap event signal is masked
bit 1 TXEISE: Transfer Complete Interrupt Signal Enable bit
1 = Transfer complete signal is enabled
0 = Transfer complete signal is masked
bit 0 CEISE: Command Complete Interrupt Signal Enable bit
1 = Command complete signal is enabled
0 = Command complete signal is masked

REGISTER 39-12: SDHCSTAT2: SDHC STATUS REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R-0, HC U-0 U-0 R-0, HC R-0, HC R-0, HC R-0, HC R-0, HC
7:0
CNISSE ACIDXE ACEBE ACCRCE ACTOE ACNEXEC


bit 7 CNISSE: Command Not Issued by Auto CMD12 Error bit
1 = Command was not issued
0 = No error
bit 4 ACIDXE: Auto CMD12 Index Error bit
1 = Index error was generated
0 = Index error was not generated
bit 3 ACEBE: Auto CMD12 End Bit Error bit
1 = End bit error was generated
0 = End bit error was not generated
bit 2 ACCRCE: Auto CMD12 CRC Error bit
1 = CRC error was generated
0 = CRC error was not generated
bit 1 ACTOE: Auto CMD12 Time-out Error bit
1 = Time-out error was generated
0 = Time-out error was not generated
bit 0 ACNEXEC: Auto CMD12 Not Executed bit
1 = Auto CMD12 was not executed
0 = Auto CMD12 was executed

REGISTER 39-13: SDHCCAP: SDHC CAPABILITIES REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-1, HS
31:24
VOLT3V3
R-x, HS U-0 R-x, HS U-0 R-x, HS U-0 R-0, HS R-0, HS
23:16
SRESUME HISPEED ADMA2 MBLEN<1:0>
U-0 U-0 R-x, HS R-x, HS R-x, HS R-x, HS R-x, HS R-x, HS
15:8
BASECLK<5:0>
R-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
TOCLKU TOCLKFREQ<5:0>
Legend: HS = Hardware settable


bit 24 VOLT3V3: 3.3V Voltage Support bit
1 = Voltage of 3.3V is supported
bit 23 SRESUME: Suspend/Resume Support bit
1 = Suspend/resume is supported
0 = Suspend/resume is not supported
bit 21 HISPEED: High-speed Support bit
1 = High speed is supported
0 = High speed is not supported
bit 19 ADMA2: ADMA2 Support bit
1 = ADMA2 is supported
0 = ADMA2 is not supported
bit 17-16 MBLEN<1:0>: Maximum Block Length bits
11 = Reserved
10 = 2048
01 = 1024
00 = 512
bit 13-8 BASECLK<5:0>: Base Clock Frequency for SDCLK bits
111111 = 63 MHz
111110 = 62 MHz
111101 = 61 MHz

000010 = 2 MHz
000001 = 1 MHz
000000 = Reserved
bit 7 TOCLKU: Time-out Clock Unit bit
1 = Time-out clock unit is in kHz
0 = Time-out clock unit is in MHz

REGISTER 39-13: SDHCCAP: SDHC CAPABILITIES REGISTER (CONTINUED)
bit 5-0 TOCLKFREQ<5:0>: Time-out Clock Frequency bits
The TOCLKU bit defines the unit, either kHz or MHz, of these bit values.
111111 = 63 kHz or 63 MHz
111110 = 62 kHz or 62 MHz
111101 = 61 kHz or 61 MHz

000010 = 2 kHz or 2 MHz
000001 = 1 kHz or 1 MHz
000000 = Reserved

REGISTER 39-14: SDHCMAXCAP: SDHC MAXIMUM CURRENT CAPABILITIES REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

R-x, HS R-x, HS R-x, HS R-x, HS R-x, HS R-x, HS R-x, HS R-x, HS
7:0
MC3V3<7:0>


bit 7-0 MC3V3<7:0>: Maximum Current for 3.3V bits
11111111 = 1020 mA
11111110 = 1016 mA
11111101 = 1012 mA

00000011 = 12 mA
00000010 = 8 mA
00000001 = 4 mA
00000000 = Reserved

REGISTER 39-15: SDHCFE: SDHC FORCE EVENT REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC W-0, HC
31:24
FEADE FEACE
W-0, HC W-0, HC W-0, HC W-0, HC W-0, HC W-0, HC W-0, HC W-0, HC
23:16
FECLE FEDEBE FEDCRCE FEDTOE FEIDXE FECEBE FECCRCE FECTOE
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

W-0 U-0 U-0 W-0 W-0 W-0 W-0 W-0
7:0
FECNIACE FEACIDXE FEACEBE FEACCRCE FEACTOE FEACNEE
Legend:

bit 25 FEADE: Force Event for ADMA Error bit
1 = Interrupt was generated
0 = Interrupt was not generated
bit 24 FEACE: Force Event for Auto CMD 12 Error bit
bit 23 FECLE: Force Event for Current-Limit Error bit
bit 22 FEDEBE: Force Event for Data End Bit Error bit
bit 21 FEDCRCE: Force Event for Data CRC Error bit
bit 20 FEDTOE: Force Event for Data Time-out Error bit
bit 19 FEIDXE: Force Event for Command Index Error bit
bit 18 FECEBE: Force Event for Command End Bit Error bit
bit 17 FECCRCE: Force Event for Command CRC Error bit
bit 16 FECTOE: Force Event for Command Time-out Error bit

REGISTER 39-15: SDHCFE: SDHC FORCE EVENT REGISTER (CONTINUED)
bit 7 FECNIACE: Force Event for Command Not Issued by Auto CMD12 Error bit
bit 4 FEACIDXE: Force Event for Auto CMD12 Index Error bit
bit 3 FEACEBE: Force Event for Auto CMD12 End Bit Error bit
bit 2 FEACCRCE: Force Event for Auto CMD12 CRC Error bit
bit 1 FEACTOE: Force Event for Auto CMD12 Time-out Error bit
bit 0 FEACNEE: Force Event for Auto CMD12 Not Executed Error bit

REGISTER 39-16: SDHCADESTAT: SDHC ADMA ERROR STATUS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8

U-0 U-0 U-0 U-0 U-0 R-0, HC R-0, HC R-0, HC
7:0
ADLMERR ADERRST<1:0>


bit 2 ADLMERR: ADMA Length Mismatch Error bit
1 = Length mismatch error has occurred
0 = Length mismatch error has not occurred
bit 1-0 ADERRST<1:0>: ADMA Error State bits
11 = Data transfer error
10 = Reserved
01 = Fetch descriptor error
00 = Stop DMA error
REGISTER 39-17: SDHCAADDR: SDHC ADMA ADDRESS REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
ADDR<31:24>
23:16
ADDR<23:16>
15:8
ADDR<15:8>
7:0
ADDR<7:0>
Legend:
bit 31-0 ADDR<31:0>: ADMA Address Register bits

These bits contain the address of the executing command of the ADMA descriptor table.

NOTES:

40.0 POWER-SAVING FEATURES Some peripherals can continue to operate at limited
functionality in Sleep mode. These peripherals
Note: This data sheet summarizes the features include I/O pins that detect a change in the input
of the PIC32MZ Graphics (DA) Family of signal, WDT, ADC, UART and peripherals that use
devices. It is not intended to be a an external clock input or the internal LPRC
comprehensive reference source. To com- oscillator (e.g., RTCC, Timer1 and Input Capture).
plement the information in this data I/O pins continue to sink or source current in the
sheet, refer to Section 10. Power- same manner as they do when the device is not in
Saving Features (DS60001130), which Sleep
is available from the Documentation >
Reference Manual section of the The processor will exit, or wake-up, from Sleep on one
Microchip PIC32 web site of the following events:
(www.microchip.com/pic32). On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
This section describes the power-saving features on
greater than the current CPU priority.
the PIC32MZ DA devices. These devices have multiple
power domains and offer various methods and modes On any form of device Reset
that allow the user to balance the power consumption On a WDT time-out
with device performance. If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
40.1 Power Saving with CPU Running peripheral bus clocks will start running and the device
When the CPU is running, power consumption can be will enter into Idle mode.
controlled by reducing the CPU clock frequency,
40.2.2 IDLE MODE
lowering the speed of PBCLK7, or selecting a lower
power clock source (i.e., LPRC or SOSC). In Idle mode, the CPU is Halted; however, all clocks are
still enabled. This allows peripherals to continue to
In addition, the Peripheral Bus Scaling mode is available
operate. Peripherals can be individually configured to
for each peripheral bus where peripherals are clocked at
Halt when entering Idle by setting their respective SIDL
reduced speed by selecting a higher divider for the
bit. Latency, when exiting Idle mode, is very low due to
associated PBCLKx, or by disabling the clock
the CPU oscillator source remaining active.
completely.
The device enters Idle mode when the SLPEN bit
40.2 Power-Saving with CPU Halted (OSCCON<4>) is clear and a WAIT instruction is
Peripherals and the CPU can be Halted or disabled to executed.
further reduce power consumption.
The processor will wake or exit from Idle mode on the
40.2.1 SLEEP MODE following events:
Sleep mode has the lowest power consumption of the On any interrupt event for which the interrupt source
device power-saving operating modes. The CPU and is enabled. The priority of the interrupt event must
most peripherals are Halted and the associated clocks be greater than the current priority of the CPU. If the
are disabled. Select peripherals can continue to priority of the interrupt event is lower than or equal
operate in Sleep mode and can be used to wake the to current priority of the CPU, the CPU will remain
device from Sleep. See the individual peripheral Halted and the device will remain in Idle mode.
module sections for descriptions of behavior in Sleep On any form of device Reset
mode. On a WDT time-out interrupt
Sleep mode includes the following characteristics:
There can be a wake-up delay based on the
oscillator selection
The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode
The BOR circuit remains operative during Sleep
mode
The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode

40.2.3 DEEP SLEEP MODE 40.2.4 VBAT MODE
Deep Sleep mode brings the device into its lowest VBAT mode is similar to Deep Sleep mode, except that
power consumption state without requiring the use of the device is powered from the VBAT pin. VBAT mode
external switches to remove power from the device. is controlled strictly by hardware, without any software
Deep Sleep intervention. Device enters VBAT mode upon VDDCORE
In this mode, the CPU, RAM and most peripherals Power-on Reset (refer to Table 44-4 for definitions of
are powered down. Power is maintained to the VPORCORE and VBATSW). An external power source
DSGPR0 register and one or more of the RTCC, must be connected to the VBAT pin before power is
DSWDT and DSGPR1 through DSGPR32 removed from VDDIO/VDDCORE to enter VBAT mode.
registers. VBAT is the lowest battery-powered mode that can
maintain an RTCC. Wake-up from VBAT mode can only
Which of these peripherals is active depends on the occur when VDDIO/VDDCORE is reapplied. The wake-up
state of the following register bits when Deep Sleep will appear to be a POR to the rest of the device.
mode is entered:
In VBAT mode, the Deep Sleep Watchdog Timer is dis-
RTCDIS (DSCON<12>) abled. The RTCC and DSGPR1 through DSGPR32
This bit must be set to disable the RTCC in Deep registers may be enabled or disabled depending on the
Sleep mode (see Register 40-1). state of the RTCDIS bit (DSCON<12>) and the
DSWDTEN (DEVCFG2<27>) DSGPREN bit (DSCON<13>), respectively. Deep
This Configuration bit must be set to enable the Sleep Persistent General Purpose Register 0
DSWDT register in Deep Sleep mode (see (DSGPR0) is always enabled in VBAT mode.
Register 41-5)
40.2.5 XLP POWER-SAVING MODES
DSGPREN (DSCON<13>)
This bit must be set to enable the DSGPR1 Figure 40-1 shows a block diagram of the system
through DSGPR32 registers in Deep Sleep mode domain for XLP devices and the related power-saving
(see Register 40-1). features. The various blocks are controlled by the
following Configuration bit settings and SFRs:
Note: The Deep Sleep Control registers can
only be accessed after the system unlock DSBOREN (DEVCFG2<20>)
sequence has been performed. In addi- DSEN (DSCON<15>)
tion, the Deep Sleep Control registers DSGPREN (DSCON<13>)
must be written twice. DSWDTEN (DEVCFG2<27>)
In addition to the conditionally enabled peripherals DSWDTOSC (DEVCFG2<26>)
described above, the MCLR filter and INT0 pin are RELEASE (DSCON<0>)
enabled in Deep Sleep mode. RTCCLKSEL (RTCCON <9:8>)
RTCDIS (DSCON<12>)
SLPEN (OSCCON<4>)
VREGS (PWRCON<0>)

FIGURE 40-1: XLP DEVICE BLOCK DIAGRAM
RTCDIS
RTCCLKSEL
VBAT
Timers SOSCI
Low-Power LPRC
VREG RTCC
SOSC
VDDCORE
DSWDT SOSCO
VBPOR
DSBOREN DSBOR DSWDTEN DSWDTOSC
POR
DSGPR1-32 DSGPREN
BOR
MCLR DSGPR0
MCLR
Deep Sleep
Monitors Persistent General
Purpose Registers
Regulators
Main VREG CPU SRAM Peripherals
Flash VREG
DSEN Idle/Sleep (SLPEN)

VREGS Program Flash RELEASE I/O Lock Logic
Memory
Peripheral I/O

DS60001361E-page 672
40.3 Deep Sleep (DSCTRL) Control Registers

TABLE 40-1: POWER-SAVING MODES REGISTER SUMMARY
All Resets(1)
Bit Range
(BF8C_#)
Register
Name(2)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
0200 DSCON 31:16 0000

15:0 DSEN DSGPREN RTCDIS RTCCWDIS DSBOR RELEASE 0000
0210 DSWAKE 31:16 0000
15:0 DSINT0 DSFLT DSWDT DSRTC DSMCLR 0000
0220 DSGPR0(1) 31:16 Deep Sleep Persistent General Purpose bits <31:16> 0000
15:0 Deep Sleep Persistent General Purpose bits <15:0> 0000
0240 DSGPR1 31:16 Deep Sleep Persistent General Purpose bits <31:16> 0000
024C DSGPR4 31:16 Deep Sleep Persistent General Purpose bits <31:16> 0000
Legend: = unimplemented, read as 0.
Note 1: The DSGPR0 register is persistent in all device modes of operation.
2: The Deep Sleep Control registers can only be accessed after the system unlock sequence has been performed. In addition, these registers must be written twice.
Bits
Virtual Address
All Resets(1)
Bit Range
(BF8C_#)
Register
Name(2)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

DS60001361E-page 673
02A0 DSGPR25 31:16 Deep Sleep Persistent General Purpose bits <31:16> 0000
DS60001361E-page 674

Bits
Virtual Address
All Resets(1)
Bit Range
(BF8C_#)
Register
Name(2)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
02AC DSGPR28 31:16 Deep Sleep Persistent General Purpose bits <31:16> 0000
02B0 DSGPR29 31:16 Deep Sleep Persistent General Purpose bits <31:16> 0000
02BC DSGPR32 31:16 Deep Sleep Persistent General Purpose bits <31:16> 0000
REGISTER 40-1: DSCON: DEEP SLEEP CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

HC, R/W-y U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
15:8 (1)
DSEN DSGPREN RTCDIS RTCCWDIS
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
7:0
DSBOR(2) RELEASE
Legend: HC = Hardware Cleared y = Value set from Configuration bits on POR


bit 15 DSEN: Deep Sleep Enable bit(1)
1 = Deep Sleep mode is entered on a WAIT instruction
0 = Sleep mode is entered on a WAIT instruction
bit 13 DSGPREN: General Purpose Registers Enable bit
1 = General purpose register retention is enabled in Deep Sleep mode
0 = No general purpose register retention in Deep Sleep mode
bit 12 RTCDIS: RTCC Module Disable bit
1 = RTCC module is not enabled
0 = RTCC module is enabled
bit 8 RTCCWDIS: RTCC Wake-up Disable bit
1 = Wake-up from RTCC is disabled
0 = Wake-up from RTCC is enabled
bit 1 DSBOR: Deep Sleep BOR Event Status bit(2)
1 = DSBOREN was enabled and VDDCORE dropped below the DSBOR threshold during Deep Sleep(2)
0 = DSBOREN was disabled, or VDDCORE did not drop below the DSBOR threshold during Deep Sleep
bit 0 RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, the I/O pins maintain their previous states
0 = Release I/O pins and allow their respective TRIS and LAT bits to control their states
Note 1: To enter Deep Sleep mode, Sleep mode must be executed after setting the DSEN bit.
2: Unlike all other events, a Deep Sleep Brown-out Reset (BOR) event will not cause a wake-up from Deep
Sleep mode; this bit is present only as a status bit.

REGISTER 40-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS
15:8
DSINT0
R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 U-0
7:0
DSFLT DSWDT DSRTC DSMCLR


bit 8 DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
bit 7 DSFLT: Deep Sleep Fault Detected bit
1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been
corrupted
0 = No Fault was detected during Deep Sleep
bit 4 DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time-out during Deep Sleep
bit 3 DSRTC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
bit 2 DSMCLR: MCLR Event bit
1 = The MCLR pin was active and was asserted during Deep Sleep
0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep
Note: All bits in this register are cleared when the DSEN bit (DSCON<15>) is set.

REGISTER 40-3: DSGPRX: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER x
(x = 0 THROUGH 32)
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
Deep Sleep Persistent General Purpose bits
23:16
15:8
7:0
Legend:
bit 31-0 Deep Sleep Persistent General Purpose bits
Note: The contents of the DSGPR0 register are retained, even in Deep Sleep and VBAT modes. The DSPGR1
through DSPGR32 registers are disabled by default in Deep Sleep and VBAT modes, but can be enabled
with the DSGPREN bit (DSCON<13>). All register bits are reset only in the case of a VDDCORE Power-on
Reset (POR) event outside of Deep Sleep mode.

40.4 Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum
power consumption state. The control and status
registers associated with the peripheral are also
disabled, so writes to those registers do not have
effect and read values are invalid.
To disable a peripheral, the associated PMDx bit must
be set to 1. To enable a peripheral, the associated
PMDx bit must be cleared (default). See Table 40-2 for
more information.
Note: Disabling a peripheral module while it's
ON bit is set, may result in undefined
behavior. The ON bit for the associated
peripheral module must be cleared prior to
disable a module via the PMDx bits.

TABLE 40-2: PERIPHERAL MODULE DISABLE REGISTER SUMMARY
All Resets(1)
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 HLVDMD 0000

0040 PMD1
15:0 CVRMD CTMUMD ADCMD 0000
31:16 0000
0050 PMD2
15:0 CMP2MD CMP1MD 0000
31:16 OC9MD OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000
0060 PMD3
15:0 IC9MD IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD 0000
31:16 0000
0070 PMD4
15:0 T9MD T8MD T7MD T6MD T5MD T4MD T3MD T2MD T1MD 0000
31:16 CAN2MD CAN1MD USBMD I2C5MD I2C4MD I2C3MD I2C2MD I2C1MD 0000
0080 PMD5
15:0 SPI6MD SPI5MD SPI4MD SPI3MD SPI2MD SPI1MD U6MD U5MD U4MD U3MD U2MD U1MD 0000
31:16 ETHMD SQI1MD SDHCMD GLCDMD GPUMD EBIMD PMPMD 0000

0090 PMD6
15:0 REFO5MD REFO4MD REFO3MD REFO2MD REFO1MD 0000
31:16 DDR2CMD CRYPTMD RNGMD 1000
00A0 PMD7
15:0 DMAMD 0000
Note 1: Reset values are dependent on the device variant.
DS60001361E-page 679
TABLE 40-3: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS

Peripheral PMDx Bit Name Register Name and Bit Location
ADC ADCMD PMD1<0>
CTMU CTMUMD PMD1<8>
Comparator Voltage Reference CVRMD PMD1<12>
High/Low-Voltage Detect HLVDMD PMD1<20>
Comparator 1 CMP1MD PMD2<0>
Comparator 2 CMP2MD PMD2<1>
Input Capture 1 IC1MD PMD3<0>
Output Compare 1 OC1MD PMD3<16>
Timer1 T1MD PMD4<0>
Timer2 T2MD PMD4<1>
Timer3 T3MD PMD4<2>
Timer4 T4MD PMD4<3>
Timer5 T5MD PMD4<4>
Timer6 T6MD PMD4<5>
Timer7 T7MD PMD4<6>
Timer8 T8MD PMD4<7>
Timer9 T9MD PMD4<8>
UART1 U1MD PMD5<0>
UART2 U2MD PMD5<1>
UART3 U3MD PMD5<2>
UART4 U4MD PMD5<3>
UART5 U5MD PMD5<4>
UART6 U6MD PMD5<5>
SPI1 SPI1MD PMD5<8>
SPI2 SPI2MD PMD5<9>
Note 1: The USB module must not be busy after clearing the associated ON bit and prior to setting the USBMD
bit.
2: This peripheral is not available on all devices. Refer to the pin feature tables (Table 2 through Table 4) to
determine availability.

TABLE 40-3: PERIPHERAL MODULE DISABLE BITS AND LOCATIONS (CONTINUED)
Peripheral PMDx Bit Name Register Name and Bit Location
SPI3 SPI3MD PMD5<10>
I2C1 I2C1MD PMD5<16>
(1)
USB USBMD PMD5<24>
CAN1 CAN1MD PMD5<28>
CAN2 CAN2MD PMD5<29>
Reference Clock Output 1 REFO1MD PMD6<8>
PMP PMPMD PMD6<16>
EBI EBIMD PMD6<17>
2-D GPU GPUMD PMD6<18>
GLCD GLCDMD PMD6<20>
SDHC SDHCMD PMD6<21>
SQI1 SQI1MD PMD6<23>
Ethernet ETHMD PMD6<28>
DMA DMAMD PMD7<4>
RNG RNGMD PMD7<20>
Crypto(2) CRYPTMD PMD7<22>
DDR2 SDRAM Controller(2) DDR2CMD PMD7<28>
Note 1: The USB module must not be busy after clearing the associated ON bit and prior to setting the USBMD
bit.
2: This peripheral is not available on all devices. Refer to the pin feature tables (Table 2 through Table 4) to
determine availability.

40.4.1 CONTROLLING CONFIGURATION
CHANGES
Because peripherals can be disabled during run time,
some restrictions on disabling peripherals are needed
to prevent accidental configuration changes. PIC32MZ
DA devices include two features to prevent alterations
to enabled or disabled peripherals:
Control Register Lock Sequence
Configuration Bit Select Lock
40.4.1.1 Control Register Lock

Under normal operation, writes to the PMDx registers
are not allowed. Attempted writes appear to execute
normally, but the contents of the registers remain
unchanged. To change these registers, they must be
unlocked in hardware. The register lock is controlled by
the PMDLOCK Configuration bit (CFGCON<12>).
Setting the PMDLOCK bit prevents writes to the control
registers and clearing the PMDLOCK bit allows writes.
To set or clear the PMDLOCK bit, an unlock sequence
must be executed. Refer to Section 42. Oscillators
with Enhanced PLL (DS60001250) in the PIC32
Family Reference Manual for details.
40.4.1.2 Configuration Bit Select Lock

As an additional level of safety, the device can be con-
figured to prevent more than one write session to the
PMDx registers. The PMDL1WAY Configuration bit
(DEVCFG3<28>) blocks the PMDLOCK bit from being
cleared after it has been set once. If the PMDLOCK bit
remains set, the register unlock procedure does not
execute, and the PPS control registers cannot be writ-
ten to. The only way to clear the bit and re-enable PMD
functionality is to perform a device Reset.

41.0 SPECIAL FEATURES The following run-time programmable Configuration
registers provide additional configuration control:
Note: This data sheet summarizes the features CFGCON: Configuration Control Register
CFGEBIA: External Bus Interface Address Pin
devices. However, it is not intended to be
Configuration Register
a comprehensive reference source. To
complement the information in this data CFGEBIC: External Bus Interface Control Pin
sheet, refer to Section 32. Configuration Register
Configuration (DS60001124) and CFGPG: Permission Group Configuration
Section 33. Programming and Register
Diagnostics (DS60001129), which are CFGCON2: Configuration Control Register 2
available from the Documentation > CFGMPLL: Memory PLL Configuration Register
Microchip PIC32 web site In addition, the DEVID register (see Register 41-15)
(www.microchip.com/pic32). provides device and revision information and the
DEVSN0 and DEVSN1 registers contain a unique
PIC32MZ DA devices include several features serial number of the device (see Register 41-16).
intended to maximize application flexibility and reliabil-
Note: Do not use word program operation
ity and minimize cost through elimination of external
(NVMOP<3:0> = 0001) when program-
components. These are:
ming the device words that are described
Flexible device configuration in this chapter.
Joint Test Action Group (JTAG) interface
In-Circuit Serial Programming (ICSP)
Internal temperature sensor
41.1 Configuration Bits

PIC32MZ DA devices contain two Boot Flash memo-
ries (Boot Flash 1 and Boot Flash 2), each with an
associated configuration space. These configuration
spaces can be programmed to contain various device
configurations. Configuration space that is aliased by
the Lower Boot Alias memory region is used to provide
values for the following Configuration registers. See
4.1.1 Boot Flash Sequence and Configuration
Spaces for more information.
DEVSIGN0/ADEVSIGN0: Device Signature Word
0 Register
DEVCP0/ADEVCP0: Device Code-Protect 0
Register
DEVCFG0/ADEVCFG0: Device Configuration
Word 0
Word 1
Word 2
Word 3
Word 4
DEVADCx: Device ADC Calibration Word x (x =
0-4, 7)

DS60001361E-page 684
41.2 Registers

TABLE 41-1: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
All Resets
Bit Range
(BFC0_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 SWDTPS<4;0> xxxx

FFBC DEVCFG4
15:0 xxxx
31:16 IOL1WAY PMDL1WAY PGL1WAY FETHIO FMIIEN EXTDDRSIZE<3:0> xxxx
FFC0 DEVCFG3
15:0 USERID<15:0> xxxx
31:16 UPLLFSEL FDSEN DSWDTEN DSWDTOSC DSWDTPS<4:0> DSBOREN VBATBOREN FPLLODIV<2:0> xxxx
FFC4 DEVCFG2
15:0 FPLLMULT<6:0> FPLLICLK FPLLRNG<2:0> FPLLIDIV<2:0> xxxx
31:16 FDMTEN DMTCNT<4:0> FWDTWINSZ<1:0> FWDTEN WINDIS WDTSPGM WDTPS<4:0> xxxx
FFC8 DEVCFG1
15:0 FCKSM<1:0> OSCIOFNC POSCMOD<1:0> IESO FSOSCEN DMTINTV<2:0> FNOSC<2:0> xxxx
xxxx
31:16 EJTAGBEN POSCAGC POSCTYPE<1:0> POSCBOOST POSCGAIN<1:0> SOSCBOOST SOSCGAIN<1:0>
FFCC DEVCFG0
15:0 SMCLR DBGPER<2:0> FSLEEP FECCCON<1:0> BOOTISA TRCEN ICESEL<1:0> JTAGEN DEBUG<1:0> xxxx
31:16 xxxx
FFD0 DEVCP3
15:0 xxxx
31:16 xxxx
FFD4 DEVCP2
15:0 xxxx
31:16 xxxx
FFD8 DEVCP1
15:0 xxxx
31:16 CP xxxx
FFDC DEVCP0
15:0 xxxx
31:16 xxxx
FFE0 DEVSIGN3
15:0 xxxx
31:16 xxxx
FFE4 DEVSIGN2
15:0 xxxx
31:16 xxxx
FFE8 DEVSIGN1
15:0 xxxx
31:16 0 xxxx
FFEC DEVSIGN0
15:0 xxxx
TABLE 41-2: ADEVCFG: ALTERNATE DEVICE CONFIGURATION WORD SUMMARY
All Resets
Bit Range
(BFC0_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 SWDTPS<4;0> xxxx

FF3C DEVCFG4
15:0 xxxx
31:16 IOL1WAY PMDL1WAY PGL1WAY FETHIO FMIIEN EXTDDRSIZE<3:0> xxxx
FF40 ADEVCFG3
15:0 USERID<15:0> xxxx
31:16 UPLLFSEL FDSEN DSWDTEN DSWDTOSC DSWDTPS<4:0> DSBOREN VBATBOREN FPLLODIV<2:0> xxxx
FF44 ADEVCFG2
15:0 FPLLMULT<6:0> FPLLICLK FPLLRNG<2:0> FPLLIDIV<2:0> xxxx
31:16 FDMTEN DMTCNT<4:0> FWDTWINSZ<1:0> FWDTEN WINDIS WDTSPGM WDTPS<4:0> xxxx
FF48 ADEVCFG1
15:0 FCKSM<1:0> OSCIOFNC POSCMOD<1:0> IESO FSOSCEN DMTINTV<2:0> FNOSC<2:0> xxxx
31:16 EJTAGBEN POSCAGC POSCTYPE<1:0> POSCBOOST POSCGAIN<1:0> SOSCBOOST SOSCGAIN<1:0> xxxx
FF4C ADEVCFG0
15:0 SMCLR DBGPER<2:0> FSLEEP FECCCON<1:0> BOOTISA TRCEN ICESEL<1:0> JTAGEN DEBUG<1:0> xxxx
31:16 xxxx
FF50 ADEVCP3

15:0 xxxx
31:16 xxxx
FF54 ADEVCP2
15:0 xxxx
31:16 xxxx
FF58 ADEVCP1
15:0 xxxx
31:16 CP xxxx
FF5C ADEVCP0
15:0 xxxx
31:16 xxxx
FF60 ADEVSIGN3
15:0 xxxx
31:16 xxxx
FF64 ADEVSIGN2
15:0 xxxx
31:16 xxxx
FF68 ADEVSIGN1
15:0 xxxx
31:16 0 xxxx
FF6C ADEVSIGN0
15:0 xxxx
DS60001361E-page 685
DS60001361E-page 686

TABLE 41-3: DEVICE ID, REVISION, AND CONFIGURATION SUMMARY
Virtual Address
Bits
All Resets(1)
Bit Range
(BF80_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 ICACLK OCACLK 0000

0000 CFGCON
15:0 IOLOCK PMDLOCK PGLOCK USBSSEN IOANCPEN ECCCON<1:0> JTAGEN TROEN TDOEN 000B
31:16 VER<3:0> DEVID<27:16> xxxx
0020 DEVID
15:0 DEVID<15:0> xxxx
31:16 0000
0030 SYSKEY SYSKEY<31:0>
15:0 0000
31:16 EBIA23EN EBIA22EN EBIA21EN EBIA20EN EBIA19EN EBIA18EN EBIA17EN EBIA16EN 0000
00C0 CFGEBIA
15:0 EBIA15EN EBIA14EN EBIA13EN EBIA12EN EBIA11EN EBIA10EN EBIA9EN EBIA8EN EBIA7EN EBIA6EN EBIA5EN EBIA4EN EBIA3EN EBIA2EN EBIA1EN EBIA0EN 0000
EBI EBI EBI EBI EBI EBI EBI
31:16 EBIRPEN 0000
00D0 CFGEBIC RDYINV3 RDYINV2 RDYINV1 RDYEN3 RDYEN2 RDYEN1 RDYLVL
15:0 EBIWEEN EBIOEEN EBIBSEN1 EBIBSEN0 EBICSEN3 EBICSEN2 EBICSEN1 EBICSEN0 EBIDEN1 EBIDEN0 0000
31:16 GPUPG<1:0> GLCDPG<1:0> CRYPTPG<1:0> FCPG<1:0> SQI1PG<1:0> SDHCPG<1:0> ETHPG<1:0> 0000
00E0 CFGPG
15:0 CAN2PG<1:0> CAN1PG<1:0> USBPG<1:0> DMAPG<1:0> CPUPG<1:0> 0000
31:16 GLCDPINEN GLCDMODE SDCDEN SDWPEN SDWRFTHR<9:0> 0000
00F0 CFGCON2
15:0 SDRDFTHR<9:0> SDWPPOL GPURESET 0000
MPLL MPLL
31:16 MPLLRDY MPLLDIS MPLLODIV2<2:0> MPLLODIV1<2:0> 7F40
0100 CFGMPLL VREGRDY VREGDIS
15:0 MPLLMULT<7:0> INTVREFCON<1:0> MPLLIDIV<5:0> FFFF
Note 1: Reset values are dependent on the specific device.
TABLE 41-4: DEVICE SERIAL NUMBER SUMMARY

Virtual Address
Bits
All Resets(1)
Bit Range
(BFC5_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 Device Serial Number <31:16> xxxx

4020 DEVSN0
4024 DEVSN1
4028 DEVSN2
402C DEVSN3
TABLE 41-5: DEVICE ADC CALIBRATION SUMMARY

All Resets(1)
Bit Range
(BFC5_#)
Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
31:16 ADC Calibration Data <31:16> xxxx

4000 DEVADC0
4004 DEVADC1
4008 DEVADC2
400C DEVADC3
4010 DEVADC4

401C DEVADC7
Legend: x = unknown value on Reset.
DS60001361E-page 687
REGISTER 41-1: DEVSIGN0/ADEVSIGN0: DEVICE SIGNATURE WORD 0 REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-0 r-1 r-1 r-1 r-1 r-1 r-1 r-1
31:24

r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
23:16

r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:8

r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
7:0


bit 31 Reserved: Write as 0

bit 30-0 Reserved: Write as 1
Note: The DEVSIGN1 through DEVSIGN3 and ADEVSIGN1 through ADEVSIGN3 registers are used for Quad
Word programming operation when programming the DEVSIGN0/ADESIGN0 registers, and do not contain
any valid information.
REGISTER 41-2: DEVCP0/ADEVCP0: DEVICE CODE-PROTECT 0 REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-1 r-1 r-1 R/P r-1 r-1 r-1 r-1
31:24
CP
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
23:16

r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:8

r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
7:0

Legend: r = Reserved bit P = Programmable bit


bit 28 CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external programming device.
1 = Protection is disabled
0 = Protection is enabled
Note: The DEVCP1 through DEVCP3 and ADEVCP1 through ADEVCP3 registers are used for Quad Word
programming operation when programming the DEVCP0/ADEVCP0 registers, and do not contain any valid
information.

REGISTER 41-3: DEVCFG0/ADEVCFG0: DEVICE CONFIGURATION WORD 0

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-x R/P r-1 r-1 r-1 r-1 r-1 r-1
31:24
EJTAGBEN POSCACG POSCTYPE<1:0>
r-1 r-1 R/P R/P R/P R/P R/P R/P
23:16
POSCBOOST POSCGAIN<1:0> SOSCBOOST SOSCGAIN<1:0>
R/P R/P R/P R/P r-y R/P R/P R/P
15:8
SMCLR DBGPER<2:0> FSLEEP FECCCON<1:0>
r-1 R/P R/P R/P R/P R/P R/P R/P
7:0
BOOTISA TRCEN ICESEL<1:0> JTAGEN(1) DEBUG<1:0>
Legend: r = Reserved bit y = Value set from Configuration bits on POR

R = Readable bit P = Programmable bit U = Unimplemented bit, read as 0
bit 31 Reserved: The reset value of this bit is the same as DEVSIGN0<31>.
bit 30 EJTAGBEN: EJTAG Boot Enable bit
1 = Normal EJTAG functionality
0 = Reduced EJTAG functionality
bit 27 POSCAGC: Primary Oscillator Auto Gain Control bit
1 = POSC Auto Gain Control Enabled
0 = POSC Auto Gain Control Disabled/Manual Gain Control Enabled
bit 25-24 POSCTYPE: Primary Oscillator Type bits
NOTE: These bits are used to control the gain loop, which differs based on the crystal frequency.
11 = 12 MHz Crystal
10 = 24 MHz Crystal
01 = Resonator
00 = 8 MHz Crystal
bit 21 POSCBOOST: Primary Oscillator Boost Kick Start Enable bit
1 = Boost the kick start of the oscillator
0 = Normal start of the oscillator
bit 20-19 POSCGAIN<1:0>: Primary Oscillator Gain Control bits
11 = Gain Level 3 (highest)
10 = Gain Level 2
01 = Gain Level 1
00 = Gain Level 0 (lowest)
bit 18 SOSCBOOST: Secondary Oscillator Boost Kick Start Enable bit
1 = Boost the kick start of the oscillator
0 = Normal start of the oscillator
bit 17-16 SOSCGAIN<1:0>: Secondary Oscillator Gain Control bits
11 = Gain Level 3 (highest)
10 = Gain Level 2
01 = Gain Level 1
00 = Gain Level 0 (lowest)
bit 15 SMCLR: Soft Master Clear Enable bit
1 = MCLR pin generates a normal system Reset
0 = MCLR pin generates a POR Reset
Note 1: This bit sets the value of the JTAGEN bit in the CFGCON register. When this fuse bit is set to 0 at start-
up, the JTAGEN bit in the CFGCON register is ignored at run-time.

REGISTER 41-3: DEVCFG0/ADEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 14-12 DBGPER<2:0>: Debug Mode CPU Access Permission bits
1xx = Allow CPU access to Permission Group 2 permission regions
x1x = Allow CPU access to Permission Group 1 permission regions
xx1 = Allow CPU access to Permission Group 0 permission regions
0xx = Deny CPU access to Permission Group 2 permission regions
x0x = Deny CPU access to Permission Group 1 permission regions
xx0 = Deny CPU access to Permission Group 0 permission regions
When the CPU is in Debug mode and the CPU1PG<1:0> bits (CFGPG<1:0>) are set to a denied permission
group as defined by DBGPER<2:0>, the transaction request is assigned Group 3 permissions.
bit 11 Reserved: This bit is controlled by debugger/emulator development tools and should not be modified by the
user.
bit 10 FSLEEP: Flash Sleep Mode bit

1 = Flash is powered down when the device is in Sleep mode
0 = Flash power down is controlled by the VREGS bit (PWRCON<0>)
bit 9-8 FECCCON<1:0>: Dynamic Flash ECC Configuration bits
Upon a device Reset, the value of these bits is copied to the ECCCON<1:0> bits (CFGCON<5:4>).
11 = ECC and dynamic ECC are disabled (ECCCON<1:0> bits are writable)
10 = ECC and dynamic ECC are disabled (ECCCON<1:0> bits are locked)
01 = Dynamic Flash ECC is enabled (ECCCON<1:0> bits are locked)
00 = Flash ECC is enabled (ECCCON<1:0> bits are locked; disables word Flash writes)
bit 6 BOOTISA: Boot ISA Selection bit
1 = Boot code and Exception code is MIPS32
(ISAONEXC bit is set to 0 and the ISA<1:0> bits are set to 10 in the CP0 Config3 register)
0 = Boot code and Exception code is microMIPS
(ISAONEXC bit is set to 1 and the ISA<1:0> bits are set to 11 in the CP0 Config3 register)
bit 5 TRCEN: Trace Enable bit
1 = Trace features in the CPU are enabled
0 = Trace features in the CPU are disabled
bit 4-3 ICESEL<1:0>: In-Circuit Emulator/Debugger Communication Channel Select bits
11 = PGEC1/PGED1 pair is used
10 = PGEC2/PGED2 pair is used
01 = Reserved
00 = Reserved
bit 2 JTAGEN: JTAG Enable bit(1)
1 = JTAG is enabled
0 = JTAG is disabled
bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to 11 if code-protect is enabled)
1x = Debugger is disabled
0x = Debugger is enabled
Note 1: This bit sets the value of the JTAGEN bit in the CFGCON register. When this fuse bit is set to 0 at start-
up, the JTAGEN bit in the CFGCON register is ignored at run-time.


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
31:24
FDMTEN DMTCNT<4:0> FWDTWINSZ<1:0>
23:16
FWDTEN WINDIS WDTSPGM WDTPS<4:0>
R/P R/P r-1 r-1 r-1 R/P R/P R/P
15:8
FCKSM<1:0> OSCIOFNC POSCMOD<1:0>
7:0
IESO FSOSCEN DMTINV<2:0> FNOSC<2:0>

bit 31 FDMTEN: Deadman Timer enable bit

1 = Deadman Timer is enabled and cannot be disabled by software
0 = Deadman Timer is disabled and can be enabled by software
bit 30-26 DMTCNT<4:0>: Deadman Timer Count Select bits
11111 = Reserved

11000 = Reserved
10111 = 231 (2147483648)
10110 = 230 (1073741824)
10101 = 229 (536870912)
10100 = 228 (268435456)

00001 = 29 (512)
00000 = 28 (256)
bit 25-24 FWDTWINSZ<1:0>: Watchdog Timer Window Size bits
11 = Window size is 25%
10 = Window size is 37.5%
bit 23 FWDTEN: Watchdog Timer Enable bit
1 = Watchdog Timer is enabled and cannot be disabled by software
0 = Watchdog Timer is not enabled; it can be enabled in software
bit 22 WINDIS: Watchdog Timer Window Enable bit
1 = Watchdog Timer is in non-Window mode
0 = Watchdog Timer is in Window mode
bit 21 WDTSPGM: Watchdog Timer Stop During Flash Programming bit
1 = Watchdog Timer stops during Flash programming
0 = Watchdog Timer runs during Flash programming (for read/execute while programming Flash
applications)

bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
bit 15-14 FCKSM<1:0>: Clock Switching and Monitoring Selection Configuration bits
11 = Clock switching is enabled and clock monitoring is enabled
10 = Clock switching is disabled and clock monitoring is enabled
01 = Clock switching is enabled and clock monitoring is disabled
00 = Clock switching is disabled and clock monitoring is disabled
bit 10 OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output disabled
0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the
External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00)
bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits
11 = POSC disabled
10 = HS Oscillator mode selected
01 = Reserved
00 = EC mode selected
bit 7 IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6 FSOSCEN: Secondary Oscillator Enable bit
1 = Enable SOSC
0 = Disable SOSC
bit 5-3 DMTINV<2:0>: Deadman Timer Count Window Interval bits
111 = Window/Interval value is 127/128 counter value
000 = Window/Interval value is zero

bit 2-0 FNOSC<2:0>: Oscillator Selection bits
111 = SPLL
110 = Reserved
101 = LPRC
100 = SOSC
011 = Reserved
010 = POSC (HS, EC)
001 = SPLL
000 = FRC divided by FRCDIV<2:0> bits (FRCDIV)


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-1 R/P r-1 R/P R/P R/P R/P R/P
31:24
UPLLFSEL FDSEN DSWDTEN DSWDTOSC DSWDTPS<4:3>
23:16
DSWDTPS<2:0> DSBOREN VBATBOREN FPLLODIV<2:0>
r-1 R/P R/P R/P R/P R/P R/P R/P
15:8
FPLLMULT<6:0>
R/P R/P R/P R/P r-1 R/P R/P R/P
7:0
FPLLICLK FPLLRNG<2:0> FPLLIDIV<2:0>


bit 30 UPLLFSEL: USB PLL Input Frequency Select bit
1 = UPLL input clock is 24 MHz
0 = UPLL input clock is 12 MHz
bit 28 FDSEN: Deep Sleep Enable bit
1 = Deep Sleep mode is entered on a WAIT instruction
0 = Sleep mode is entered on a WAIT instruction
bit 27 DSWDTEN: Deep Sleep Watchdog Timer Enable bit
1 = Enable the Deep Sleep Watchdog Timer (DSWDT) during Deep Sleep mode
0 = Disable the DSWDT during Deep Sleep mode
bit 26 DSWDTOSC: Deep Sleep Watchdog Timer Reference Clock Select bit
1 = Select the LPRC Oscillator as the DSWDT reference clock
0 = Select the Secondary Oscillator as the DSWDT reference clock

bit 25-21 DSWDTPS<4:0>: Deep Sleep Watchdog Timer Postscale Select bits
11111 = 1:236
11110 = 1:235
11101 = 1:234
11100 = 1:233
11011 = 1:232
11010 = 1:231
11001 = 1:230
11000 = 1:229
10111 = 1:228
10110 = 1:227
10101 = 1:226
10100 = 1:225
10011 = 1:224
10010 = 1:223
10001 = 1:222
10000 = 1:221
01111 = 1:220
01110 = 1:219
01101 = 1:218
01100 = 1:217
01011 = 1:216
01010 = 1:215
01001 = 1:214
01000 = 1:213
00111 = 1:212
00110 = 1:211
00101 = 1:210
00100 = 1:29
00011 = 1:28
00010 = 1:27
00001 = 1:26
00000 = 1:25
bit 20 DSBOREN: Deep Sleep BOR Enable bit
1 = Enable BOR during Deep Sleep mode
0 = Disable BOR during Deep Sleep mode
bit 19 VBATBOREN: VBAT BOR Enable bit
1 = Enable BOR during VBAT mode
0 = Disable BOR during VBAT mode
bit 18-16 FPLLODIV<2:0>: Default System PLL Output Divisor bits
111 = PLL output divided by 32

bit 14-8 FPLLMULT<6:0>: System PLL Feedback Divider bits

bit 7 FPLLICLK: System PLL Input Clock Select bit
1 = FRC is selected as input to the System PLL
0 = POSC is selected as input to the System PLL
bit 6-4 FPLLRNG<2:0>: System PLL Divided Input Clock Frequency Range bits
111 = Reserved
110 = Reserved
101 = 34-64 MHz
100 = 21-42 MHz
011 = 13-26 MHz
010 = 8-16 MHz
001 = 5-10 MHz
000 = Bypass
bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits
111 = Divide by 8
110 = Divide by 7
101 = Divide by 6
100 = Divide by 5
011 = Divide by 4
010 = Divide by 3
001 = Divide by 2
000 = Divide by 1


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-1 r-1 R/P R/P R/P r-1 R/P R/P
31:24
IOL1WAY PMDL1WAY PGL1WAY FETHIO FMIIEN
r-1 r-1 r-1 r-1 R/P R/P R/P R/P
23:16
EXTDDRSIZE<3:0>
15:8
USERID<15:8>
7:0
USERID<7:0>


bit 29 IOL1WAY: Peripheral Pin Select Configuration bit
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
bit 28 PMDL1WAY: Peripheral Module Disable Configuration bit
bit 27 PGL1WAY: Permission Group Lock One Way Configuration bit
bit 25 FETHIO: Ethernet I/O Pin Selection Configuration bit
1 = Default Ethernet I/O pins
0 = Alternate Ethernet I/O pins
This bit is ignored for devices that do not have an alternate Ethernet pin selection.
bit 24 FMIIEN: Ethernet MII Enable Configuration bit
1 = MII is enabled
0 = RMII is enabled
bit 19-16 EXTDDRSIZE<3:0>: External DDR2 SDRAM Size bits
This field is used to configure the DDR2 memory map. Refer to Table 4-1 for address mapping details.
1111 = 128 MB
1110 = 128 MB

0111 = 128 MB
0110 = 64 MB
0101 = 32 MB
0100 = 16 MB
0011 = 8 MB
0010 = 4 MB
0001 = 2 MB
0000 = 1 MB
bit 15-0 USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSP and JTAG


Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-1 r-1 r-1 R/P R/P R/P R/P R/P
31:24
SWDTPS<4:0>
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
23:16

r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
15:8

r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
7:0



bit 29-24 SWDTPS<4:0>: Sleep Mode Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100

REGISTER 41-8: DEVADCx: DEVICE ADC CALIBRATION WORD x (x = 0-4, 7)

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R R R R R R R R
31:24
ADCFG<31:24>
R R R R R R R R
23:16
ADCFG<23:16>
R R R R R R R R
15:8
ADCFG<15:8>
R R R R R R R R
7:0
ADCFG<7:0>
Legend:
bit 31-0 ADCFG<31:0>: Calibration Data for the ADC Module bits
This data must be copied to the corresponding ADCxCFG register. Refer to Section 28.0 Pipelined
Analog-to-Digital Converter (ADC) for more information.

REGISTER 41-9: CFGCON: CONFIGURATION CONTROL REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
23:16
ICACLK(1) OCACLK(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0
15:8 (1) (1) (1)
IOLOCK PMDLOCK PGLOCK USBSSEN(1)
R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 U-0 R/W-1
7:0
IOANCPEN ECCCON<1:0> JTAGEN(2) TROEN TDOEN
Legend:

bit 17 ICACLK: Input Capture Alternate Clock Selection bit(1)
1 = Input Capture modules use an alternative Timer pair as their timebase clock
0 = All Input Capture modules use Timer2/3 as their timebase clock
bit 16 OCACLK: Output Compare Alternate Clock Selection bit(1)
1 = Output Compare modules use an alternative Timer pair as their timebase clock
0 = All Output Compare modules use Timer2/3 as their timebase clock
bit 13 IOLOCK: Peripheral Pin Select Lock bit(1)
1 = Peripheral Pin Select is locked. Writes to PPS registers is not allowed.
0 = Peripheral Pin Select is not locked. Writes to PPS registers is allowed.
bit 12 PMDLOCK: Peripheral Module Disable bit(1)
1 = Peripheral module is locked. Writes to PMD registers is not allowed.
0 = Peripheral module is not locked. Writes to PMD registers is allowed.
bit 11 PGLOCK: Permission Group Lock bit(1)
1 = Permission Group registers are locked. Writes to PG registers are not allowed.
0 = Permission Group registers are not locked. Writes to PG registers are allowed.
bit 8 USBSSEN: USB Suspend Sleep Enable bit(1)
Enables features for USB PHY clock shutdown in Sleep mode.
1 = USB PHY clock is shut down when Sleep mode is active
0 = USB PHY clock continues to run when Sleep is active
Note 1: To change this bit, the unlock sequence must be performed. Refer to Section 42. Oscillators with
Enhanced PLL (DS60001250) in the PIC32 Family Reference Manual for details.
2: The JTAGEN bit is only available at run-time when the JTAGEN (DEVCFG0<2>) fuse bit is set at start-up.

REGISTER 41-9: CFGCON: CONFIGURATION CONTROL REGISTER (CONTINUED)
bit 7 IOANCPEN: I/O Analog Charge Pump Enable bit
1 = Charge pumps are enabled
0 = Charge pumps are disabled
Note 1: For proper analog operation at VDD is less than 2.5V, the AICPMPEN bit (ADCCON1<12>) must
be = 1 and the IOANCPEN bit must be set to 1; however, the charge pumps will consume addi-
tional current. These bits should not be set if VDD is greater than 2.5V.
2: ADC throughput rate performance is reduced as defined in the table below if ADCCON1<AICP-
MPEN> = 1 and CFGCON<IOANCPEN> = 1.
bit 5-4 ECCCON<1:0>: Flash ECC Configuration bits

11 = ECC and dynamic ECC are disabled (ECCCON<1:0> bits are writable)
10 = ECC and dynamic ECC are disabled (ECCCON<1:0> bits are locked)
01 = Dynamic Flash ECC is enabled (ECCCON<1:0> bits are locked)
00 = Flash ECC is enabled (ECCCON<1:0> bits are locked; disables word Flash writes)
bit 3 JTAGEN: JTAG Port Enable bit(2)
1 = Enable the JTAG port
0 = Disable the JTAG port
bit 2 TROEN: Trace Output Enable bit
1 = Enable trace outputs and start trace clock (trace probe must be present)
0 = Disable trace outputs and stop trace clock
bit 0 TDOEN: TDO Enable for 2-Wire JTAG
1 = 2-wire JTAG protocol uses TDO
0 = 2-wire JTAG protocol does not use TDO
Note 1: To change this bit, the unlock sequence must be performed. Refer to Section 42. Oscillators with
Enhanced PLL (DS60001250) in the PIC32 Family Reference Manual for details.
2: The JTAGEN bit is only available at run-time when the JTAGEN (DEVCFG0<2>) fuse bit is set at start-up.

REGISTER 41-10: CFGEBIA: EXTERNAL BUS INTERFACE ADDRESS PIN CONFIGURATION

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24

23:16
EBIA23EN EBIA22EN EBIA21EN EBIA20EN EBIA19EN EBIA18EN EBIA17EN EBIA16EN
15:8
7:0
Legend:

bit 23-0 EBIA23EN:EBIA0EN: EBI Address Pin Enable bits
1 = EBIAx pin is enabled for use by EBI
0 = EBIAx pin has is available for general use
Note: When EBIMD = 1, the bits in this register are ignored and the pins are available for general use.

REGISTER 41-11: CFGEBIC: EXTERNAL BUS INTERFACE CONTROL PIN CONFIGURATION

REGISTER
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0
31:24 EBI EBI EBI EBI EBI EBI
RDYINV3 RDYINV2 RDYINV1 RDYEN3 RDYEN2 RDYEN1
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
23:16
EBIRDYLVL EBIRPEN
U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
15:8
EBIWEEN EBIOEEN EBIBSEN1 EBIBSEN0
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
7:0
EBICSEN3 EBICSEN2 EBICSEN1 EBICSEN0 EBIDEN1 EBIDEN0
Legend:
bit 31 EBIRDYINV3: EBIRDY3 Inversion Control bit

1 = Invert EBIRDY3 pin before use
0 = Do not invert EBIRDY3 pin before use
bit 27 EBIRDYEN3: EBIRDY3 Pin Enable bit
1 = EBIRDY3 pin is enabled for use by the EBI module
0 = EBIRDY3 pin is available for general use
bit 17 EBIRDYLVL: EBIRDYx Pin Sensitivity Control bit
1 = Use level detect for EBIRDYx pins
0 = Use edge detect for EBIRDYx pins
bit 16 EBIRPEN: EBIRP Pin Sensitivity Control bit
1 = EBIRP pin is enabled for use by the EBI module
0 = EBIRP pin is available for general use
bit 13 EBIWEEN: EBIWE Pin Enable bit
1 = EBIWE pin is enabled for use by the EBI module
0 = EBIWE pin is available for general use

REGISTER 41-11: CFGEBIC: EXTERNAL BUS INTERFACE CONTROL PIN CONFIGURATION
REGISTER (CONTINUED)
bit 12 EBIOEEN: EBIOE Pin Enable bit
1 = EBIOE pin is enabled for use by the EBI module
0 = EBIOE pin is available for general use
bit 9 EBIBSEN1: EBIBS1 Pin Enable bit
1 = EBIBS1 pin is enabled for use by the EBI module
0 = EBIBS1 pin is available for general use
bit 8 EBIBSEN0: EBIBS0 Pin Enable bit
1 = EBIBS0 pin is enabled for use by the EBI module
0 = EBIBS0 pin is available for general use
bit 7 EBICSEN3: EBICS3 Pin Enable bit
1 = EBICS3 pin is enabled for use by the EBI module
0 = EBICS3 pin is available for general use
bit 1 EBIDEN1: EBI Data Upper Byte Pin Enable bit
1 = EBID<15:8> pins are enabled for use by the EBI module
0 = EBID<15:8> pins have reverted to general use
bit 0 EBIDEN01: EBI Data Upper Byte Pin Enable bit
1 = EBID<7:0> pins are enabled for use by the EBI module
0 = EBID<7:0> pins have reverted to general use

REGISTER 41-12: CFGPG: PERMISSION GROUP CONFIGURATION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
GPUPG<1:0> GLCDPG<1:0> CRYPTPG<1:0>
23:16
FCPG<1:0> SQI1PG<1:0> SDHCPG<1:0> ETHPG<1:0>
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
15:8
CAN2PG<1:0> CAN1PG<1:0> USBPG<1:0>
U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
7:0
DMAPG<1:0> CPUPG<1:0>
Legend:

bit 29-28 GPUPG<1:0>: 2D Graphics Processing Unit Permission Group bits
11 = Initiator is assigned to Permission Group 3
bit 27-26 GLCDPG<1:0>: Graphics LCD Controller Permission Group bits
Same definition as bits 29-28.
bit 25-24 CRYPTPG<1:0>: Crypto Engine Permission Group bits
bit 23-22 FCPG<1:0>: Flash Control Permission Group bits
bit 21-20 SQI1PG<1:0>: SQI Module Permission Group bits
bit 19-18 SDHCPG<1:0>: Secure Digital Host Controller Permission Group bits
bit 17-16 ETHPG<1:0>: Ethernet Module Permission Group bits
bit 15-14 CAN2PG<1:0>: CAN2 Module Permission Group bits
bit 13-12 CAN1PG<1:0>: CAN1 Module Permission Group bits
bit 9-8 USBPG<1:0>: USB Module Permission Group bits
bit 5-4 DMAPG<1:0>: DMA Module Permission Group bits
bit 1-0 CPUPG<1:0>: CPU Permission Group bits

REGISTER 41-13: CFGCON2: CONFIGURATION CONTROL REGISTER 2

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
31:24
GLCDPINEN GLCDMODE(1) SDCDEN SDWPEN SDWRFTHR<9:8>
23:16
SDWRFTHR<7:0>
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
SDRDFTHR<9:4>
R/W-0 R/W-0 R/W-0 R/W-0 r-1 R/W-0 U-0 R/W-0
7:0
SDRDFTHR<3:0> SDWPPOL GPURESET
Legend:
bit 31 GLCDPINEN: Graphics Display Pin Enable bit

1 = GLCD pins are used by the GLCD module
0 = GLCD pins are available for general purpose use
bit 30 GLCDMODE: Graphics Display Mode bit(1)
1 = GLCD pins are set to RGB565 mode. Other GDx pins are available for general purpose use.
0 = GLCD pins are set to RGB888 mode
bit 29 SDCDEN: SD Card Detect Pin Enable bit
1 = SDCD pin is enabled for use by SDHC
0 = SDCD pin is available for general purpose use
bit 28 SDWPEN: SD card Write Protect Enable bit
1 = SDWP pin is enabled for use by SDHC
0 = SDWP pin is available for general purpose use
bit 25-16 SDWRFTHR<9:0>: SDHC Write FIFO Threshold bits
SDHC FIFO threshold value in bytes (FIFO size is 512 bytes).
bit 13-4 SDRDFTHR<9:0>: SDHC Read FIFO Threshold bits
SDHC FIFO threshold value in bytes (FIFO size is 512 bytes).
bit 2 SDWPPOL: SD card Write Protect Polarity bit
1 = SDWP pin is Active-High
0 = SDWP pin is Active-Low
Note: This bit supports SD cards with different write-protect polarity types.
bit 0 GPURESET: GPU Reset Bit
1 = Release RESET to the GPU module
0 = Hold GPU in RESET.
Note: This bit is only used if the GPU functionality is to be enabled or disabled at run-time. Writing to
this bit requires the GPUMD bit (PMD6<18>) be set to '0' (GPU is enabled).
Note 1: To use GLCD in RGB888 mode, the GLCDMODE bit should be set to 0, which will turn-off the general
purpose I/O functionality on six additional pins. Refer to the specific package in Device Pin Tables for
information on GDx pin sharing.

REGISTER 41-14: CFGMPLL: MEMORY PLL CONFIGURATION REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
31:24
MPLLRDY MPLLDIS MPLLODIV2<2:0> MPLLODIV1<2:0>
R-0 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0
23:16 MPLL MPLL

VREGRDY VREGDIS
15:8
MPLLMULT<7:0>
7:0
INTVREFCON<1:0> MPLLIDIV<5:0>
Legend:
bit 31 MPLLRDY: Memory PLL Status bit

1 = MPLL clock is stable and is ready for use
0 = MPLL clock is not ready. Initializing DDR2 SDRAM when the clock is not ready will result in undefined
behavior.
bit 30 MPLLDIS: MPLL Disable bit
1 = MPLL is disabled
0 = MPLL is enabled
Note: Clear this bit only after the MPLLVREGRDY bit is set to 1.
bit 29-27 MPLLODIV2<2:0>: MPLL Output Divider 2 bits
111 = MPLL second stage output is divided by 7
000 = Reserved
Note: The Value in this field should be less than MPLLODIV1. Unless it is necessary, setting these bits
to '001' (MPLL second stage output is divided by 1) will produce less clock jitter.
bit 26-24 MPLLODIV1<2:0>: MPLL Output Divider 1 bits
See bits 29-27 for available selections.
bit 23 MPLLVREGRDY: MPLL Voltage Regulator Ready bit
1 = MPLL voltage regulator is ready for use
0 = MPLL voltage regulator is not ready or is disabled
bit 22 MPLLVREGDIS: MPLL Voltage regulator Disable bit
1 = MPLL voltage regulator is disabled
0 = MPLL voltage regulator is enabled

REGISTER 41-14: CFGMPLL: MEMORY PLL CONFIGURATION REGISTER (CONTINUED)
bit 15-8 MPLLMULT<7:0>: MPLL Multiplier bits
11111111 = Reserved
11111110 = Reserved

10100001 = Reserved
10100000 = Multiply by 160
10011111 = Multiply by 159

00001111 = Reserved

00000000 = Reserved
bit 7-6 INTVREFCON<1:0>: Internal DDRVREF Control bits
11 = Enable the internal DDRVREF circuit
10 = Disable the internal DDRVREF circuit and drive the DDRVREF pin to VSS1V8
01 = Disable the internal DDRVREF circuit and drive the DDRVREF pin to VDDR1V8
00 = Use the external DDRVREF circuit
Note: Set the INTVREFCON<1:0> bits to the desired state before applying VDDR1V8.
bit 5-0 MPLLIDIV<5:0>: MPLL Input Divider bits
111111 = MPLL input clock is divider by 63

000000 = Reserved

REGISTER 41-15: DEVID: DEVICE AND REVISION ID REGISTER

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R R R R R R R R
31:24 (1) (1)
VER<3:0> DEVID<27:24>
R R R R R R R R
23:16 (1)
DEVID<23:16>
R R R R R R R R
15:8 (1)
DEVID<15:8>
R R R R R R R R
7:0
DEVID<7:0>(1)
Legend:
bit 31-28 VER<3:0>: Revision Identifier bits(1)

bit 27-0 DEVID<27:0>: Device ID(1)
Note 1: See the PIC32 Flash Programming Specification (DS60001145) for a list of Revision and Device ID values.
REGISTER 41-16: DEVSNx: DEVICE SERIAL NUMBER REGISTER x (x = 0, 1)

31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R R R R R R R R
31:24
SN<31:24>
R R R R R R R R
23:16
SN<23:16>
R R R R R R R R
15:8
SN<15:8>
R R R R R R R R
7:0
SN<7:0>
Legend:
bit 31-0 SN<31:0>: Device Unique Serial Number bits

41.3 High-Voltage Detect (HVD1V8) on 41.6 Programming and Diagnostics
VDDR1V8 PIC32MZ DA devices provide a complete range of pro-
The High-Voltage Detect (HVD) module monitors the gramming and diagnostic features that can increase
DDR2 PHY voltage at the VDDR1V8 supply voltage the flexibility of any application using them. These
(1.8V). If a dangerously high voltage is detected, the features allow system designers to include:
device is held in reset as long as the HVD condition Simplified field programmability using two-wire
persists. In-Circuit Serial Programming (ICSP)
interfaces
Recovery from an HVD event is indicated by the
HVD1V8R bit (RCON<29>). Debugging using ICSP
Programming and debugging capabilities using
41.4 On-Chip Voltage Regulator the EJTAG extension of JTAG
JTAG boundary scan testing for device and board
The core and digital logic for all PIC32MZ DA devices diagnostics
is designed to operate at a nominal 1.8V. To simplify
PIC32 devices incorporate two programming and diag-
system designs, devices in the PIC32MZ DA family
nostic modules, and a trace controller, that provide a
incorporate an on-chip regulator providing the required
range of functions to the application developer.
core logic voltage from VDDIO.
FIGURE 41-1: BLOCK DIAGRAM OF
41.4.1 ON-CHIP REGULATOR AND POR
PROGRAMMING,
It takes a fixed delay for the on-chip regulator to generate DEBUGGING AND TRACE
an output. During this time, designated as TPU, code
PORTS
execution is disabled. TPU is applied every time the
device resumes operation after any power-down,
including Sleep mode. PGEC1
PGED1
41.4.2 ON-CHIP REGULATOR AND BOR
ICSP
PIC32MZ DA devices also have a simple brown-out Controller
capability. If the voltage supplied to the regulator is PGEC2
inadequate to maintain a regulated level, the regulator PGED2
Reset circuitry will generate a Brown-out Reset. This
event is captured by the BOR flag bit (RCON<1>). The
ICESEL
brown-out voltage levels are specific in Section 44.1
DC Characteristics.
TDI
41.5 On-chip Temperature Sensor TDO JTAG

Core
TCK Controller
PIC32MZ DA devices include a temperature sensor
that provides accurate measurement of a devices TMS
junction temperature (see Section 44.2 AC
Characteristics and Timing Parameters for more JTAGEN DEBUG<1:0>
information).
The temperature sensor is connected to the ADC TRCLK
module and can be measured using the shared S&H
circuit (see Section 29.0 12-bit High-Speed TRD0
Successive Approximation Register (SAR) Analog- TRD1 Instruction Trace
to-Digital Converter (ADC) for more information). Controller
TRD2
TRD3
DEBUG<1:0>

42.0 INSTRUCTION SET
The PIC32MZ Graphics (DA) Family family instruction
set complies with the MIPS32 Release 2 instruction
set architecture. The PIC32MZ DA device family does
not support the following features:
Core extend instructions
Coprocessor 2 instructions
Note: Refer to MIPS32 Architecture for

Programmers Volume II: The MIPS32
Instruction Set at www.imgtec.com for
more information.

NOTES:

43.0 DEVELOPMENT SUPPORT 43.1 MPLAB X Integrated Development
Environment Software
The PIC microcontrollers (MCU) and dsPIC digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
Integrated Development Environment hardware development tool that runs on Windows,
Linux and Mac OS X. Based on the NetBeans IDE,
- MPLAB X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE In-Circuit Emulator X IDE is also suitable for the needs of experienced
In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit 3
Color syntax highlighting
Device Programmers
Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
Low-Cost Demonstration/Development Boards, Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
Third-party development tools Live parsing
User-Friendly, Customizable Interface:
Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
Call graph window
Project-Based Workspaces:
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
File History and Bug Tracking:
Local file history feature
Built-in support for Bugzilla issue tracker

43.2 MPLAB XC Compilers 43.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchips 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
43.5 MPLAB Assembler, Linker and
Support for the entire device instruction set
Librarian for Various Device
Support for fixed-point and floating-point data
Families
Command-line interface
Rich directive set MPLAB Assembler produces relocatable machine
Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
43.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:
The MPASM Assembler generates relocatable object Support for the entire device instruction set
files for the MPLINK Object Linker, Intel standard HEX Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol Command-line interface
reference, absolute LST files that contain source lines Rich directive set
and generated machine code, and COFF files for Flexible macro language
debugging.
MPLAB X IDE compatibility
The MPASM Assembler features include:
Integration into MPLAB X IDE projects
User-defined macros to streamline
assembly code
Conditional assembly for multipurpose
source files
Directives that allow complete control over the
assembly process

43.6 MPLAB X SIM Software Simulator 43.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchips most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB
buffer and logic analyzer display extend the power of IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineers PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 43.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
43.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchips next generation high-speed emulator for connected to the design engineers PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar-
programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati-
with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineers to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming (ICSP).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 43.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDIOMIN and VDDIOMAX for
The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display
downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod-
significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

43.11 Demonstration/Development 43.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent and Olimex
interfaces, LCD displays, potentiometers and additional Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM and dsPICDEM
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ security
ICs, CAN, IrDA, PowerSmart battery management,
SEEVAL evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

44.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MZ DA electrical characteristics. Additional information will be provided
in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MZ DA devices are listed below. Exposure to these maximum rating conditions
for extended periods may affect device reliability. Functional operation of the device at these or any other conditions,
above the parameters indicated in the operation listings of this specification, is not implied.
ABSOLUTE MAXIMUM RATINGS

(see Note1)
Ambient temperature under bias.............................................................................................................. .-40C to +85C
Storage temperature .............................................................................................................................. -65C to +150C
Voltage on VDDIO, VDDCORE, and VBAT with respect to VSS ...................................................................... -0.3V to +4.0V
Voltage on VDDR1V8 pin with respect to VSS1V8 ..................................................................................... -0.5V to +1.98V
Voltage on DDR2 pins with respect to VSS1V8 ....................................................................... -0.3V to (VDDR1V8 + 0.3V)
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)...................................... -0.3V to (VDDIO + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDDIO 2.2V (Note 3)..................................... -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDDIO < 2.2V (Note 3)..................................... -0.3V to +3.6V
Voltage on D+ or D- pin with respect to VUSB3V3 .................................................................... -0.3V to (VUSB3V3 + 0.3V)
Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V
Maximum current out of VSS pin(s) .......................................................................................................................200 mA
Maximum current into VDDIO pin(s) (Note 2).........................................................................................................200 mA
Maximum current sunk/sourced by DDR2 pin.........................................................................................................22 mA
Maximum current sunk/sourced by any 4x I/O pin (Note 4)....................................................................................15 mA
Maximum current sunk/sourced by any 8x I/O pin (Note 4)....................................................................................25 mA
Maximum current sunk/sourced by any 12x I/O pin (Note 4)..................................................................................33 mA
Maximum current sunk by all ports (Note 5) .........................................................................................................150 mA
Maximum current sourced by all ports (Note 2, Note 5).......................................................................................150 mA
Note 1: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 44-2).
3: See the pin name tables (Table 5 through Table 7) for the 5V tolerant pins.
4: Characterized, but not tested. Refer to parameters DO10, DO20, and DO20a for the 4x, 8x, and 12x I/O
pin lists.
5: Excludes DDR2 pins.

44.1 DC Characteristics
TABLE 44-1: OPERATING MIPS VS. VOLTAGE
VDDCORE Max. Frequency
VDDIO Range
Range Temp. Range
Characteristic (in Volts) Comments
(in Volts) (in C) PIC32MZ DA Devices
(Note 1)
(Note 1)
DC5 2.2V-3.6V 1.7V-1.9V -40C to +85C 200 MHz
Note 1: Overall functional device operation below operating voltages guaranteed (but not characterized) until
Reset is issued. All device Analog modules, when enabled, will function, but with degraded performance
below operating voltages. Refer to Table 44-5 for Reset values.
TABLE 44-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min. Typ. Max. Unit
Industrial Temperature Devices
Operating Junction Temperature Range TJ -40 +125 C
Operating Ambient Temperature Range TA -40 +85 C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDDIO x (IDD S IOH) PD PINT + PI/O W
I/O Pin Power Dissipation:
PI/O = S (({VDDIO VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation PDMAX (TJ TA)/JA W
TABLE 44-3: THERMAL PACKAGING CHARACTERISTICS

Characteristics Symbol Typ. Max. Unit Notes
Package Thermal Resistance, 169-pin LFBGA (11x11x1.4 mm) JA 25 C/W 1
Package Thermal Resistance, 169-pin LFBGA (11x11x1.56 mm) JA 24 C/W 1,2
Package Thermal Resistance, 176-pin LQFP (20x20x1.45 mm) JA 17 C/W 1
Package Thermal Resistance, 176-pin LQFP (20x20x1.45 mm) JA 19 C/W 1,2
Package Thermal Resistance, 288-pin LFBGA (15x15x1.4 mm) JA 22 C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
2: Devices with internal DDR2 SDRAM.

TABLE 44-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
DC CHARACTERISTICS VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Operating temperature -40C TA +85C for Industrial
Param.
Symbol Characteristics Min. Typ. Max. Units Conditions
No.
Operating Voltage
DC10 VDDIO I/O Supply Voltage (Note 1) 2.2 3.6 V
DC11 VDDCORE Core Supply Voltage (Note 1) 1.7 1.8 1.9 V
DC12 SVDDIO/ VDDIO/VDDCORE Rise Rate
300 ms to 3 s @
SVDDCORE to Ensure Internal 0.000011 1.1 V/s
3.3v
Power-on Reset Signal (Note 2)
DC13 VBAT Battery Supply Voltage 2.2 3.6 V
DC14 VDDR1V8 DDR Memory Supply Voltage 1.7 1.8 1.9 V
0.49 x 0.50 x 0.51 x
DC15 DDRVREF DDR Reference Voltage V
VDDR1V8 VDDR1V8 VDDR1V8
Note 1: Overall functional device operation below operating voltages guaranteed (but not characterized) until Reset
is issued. All device Analog modules, when enabled, will function, but with degraded performance below
operating voltages. Refer to Table 44-5 for Reset values.
2: Voltage on VDDIO must always be greater than or equal to VDDCORE during power-up.
TABLE 44-5: ELECTRICAL CHARACTERISTICS: RESETS

DC CHARACTERISTICS (Note 1) VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Param.
No.
RST10 VPORIO VDDIO POR Voltage VSS +
1.75 V
(Note 2) 0.3
RST11 VPORCORE VDDCORE POR Voltage
/VBATSW (Note 2) VSS +
1.7 V
VDDCORE to VBAT Switch 0.3
Voltage (Note 3)
RST12 VBORIO BOR Event on VDDIO transition
1.92 2.2 V
high-to-low (Note 4)
RST13 VPORBAT POR Event on VBAT (Note 4) 1.35 2.2 V
RST14 VHVD1V8 High Voltage Detect on
2.16 2.24 V
VDDR1V8 pins
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: This is the limit to which VDDIO/VDDCORE must be lowered to ensure Power-on Reset.
3: Device enters VBAT mode upon VDDCORE Power-on Reset.
4: Overall functional device operation below operating voltages guaranteed (but not characterized) until Reset
is issued. All device Analog modules, when enabled, will function, but with degraded performance below
operating voltages.

TABLE 44-6: LOW-VOLTAGE DETECT CHARACTERISTICS
Param
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
LV10 VHLVD HLVD Voltage on HLVDL<3:0> = 0100(1) 3.52 V
VDDIO Transition HLVDL<3:0> = 0101 3.29 V
HLVDL<3:0> = 0110 3.00 V
HLVDL<3:0> = 0111 2.79 V
HLVDL<3:0> = 1000 2.70 V
HLVDL<3:0> = 1001 2.50 V
HLVDL<3:0> = 1010 2.40 V
HLVDL<3:0> = 1011 2.30 V
HLVDL<3:0> = 1100 2.20 V
HLVDL<3:0> = 1101 2.12 V
HLVDL<3:0> = 1110 2.00 V
LV11 VTHL Voltage on HLVDIN HLVDL<3:0> = 1111 1.20 V
Pin Transition
Note 1: Trip points for values of LVD<3:0>, from 0000 to 0011, are not implemented.

TABLE 44-7: DC CHARACTERISTICS: OPERATING CURRENT (IDD = IDDIO + IDDCORE)

DC CHARACTERISTICS(1,2) VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Parameter
Typical(3) Maximum Units Conditions
No.
I/O Operating Current (IDDIO): Peripherals Enabled (PMDx=0, ON(PBxDIV<15>)=1)
DC20 1.4 2.1 mA 8 MHz
DC21 3.5 4.1 mA 100 MHz(4)
DC22 5.6 6.5 mA 200 MHz
DC23 5.6 6.5 mA 200 MHz (L1 Cache and Prefetch modules disabled)(4)
I/O Operating Current (IDDCORE): Peripherals Enabled (PMDx=0, ON(PBxDIV<15>)=1)
DC20a 20 34 mA 8 MHz
DC21a 97 118 mA 100 MHz(4)
DC22a 152 180 mA 200 MHz
DC23a 128 153 mA 200 MHz (L1 Cache and Prefetch modules disabled)(4)
I/O Operating Current (IDDIO): Peripherals Disabled (PMDx=1, ON(PBxDIV<15>)=0)
DC24 1.4 2.1 mA 8 MHz
DC25 3.5 4.1 mA 100 MHz(4)
DC26 5.6 6.5 mA 200 MHz
DC27 5.6 6.5 mA 200 MHz (L1 Cache and Prefetch modules disabled)(4)
I/O Operating Current (IDDCORE): Peripherals Disabled (PMDx=1, ON(PBxDIV<15>)=0)
DC24a 19 33 mA 8 MHz
DC25a 90 109 mA 100 MHz(4)
DC26a 146 177 mA 200 MHz
DC27a 121 147 mA 200 MHz (L1 Cache and Prefetch modules disabled)(4)
Note 1: A devices IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as Peripheral Bus Clock (PBCLK) frequency, number of peripheral modules enabled, internal code
execution pattern, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an
impact on the current consumption.
2: The test conditions for IDD measurements are as follows:
VDDR1V8 = 1.8V
Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
OSC2/CLKO is configured as an I/O input pin
USB PLL is disabled (USBMD = 1), VUSB3V3 is connected to VSS
CPU, Program Flash, and SRAM data memory are operational, Program Flash memory Wait states
are equal to two
No peripheral modules are operating (ON bit = 0)
L1 Cache and Prefetch modules are enabled, unless otherwise specified in conditions.
No peripheral modules are operating, (ON bit = 0)
WDT, DMT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
All I/O pins are configured as inputs and pulled to VSS
MCLR = VDDIO
CPU executing while(1) statement from Flash
RTCC and JTAG are disabled
I/O Analog Charge Pump is disabled (IOANCPEN bit (CFGCON<7>) = 0)
ADC Input Charge Pump is disabled (AICPMPEN bit (ADCCON1<12> = 0)
All Peripheral Bus Clocks, except PBCLK7, are disabled (ON bit (PBxDIV<15>) = 0, x = 2 through 6)
3: Data in Typical column is at 3.3V, +25C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: This parameter is characterized, but not tested in manufacturing.

TABLE 44-8: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

Parameter
No.
Idle Current (IIDLE): Core Off, Clock on Base Current (1)
DC30 19 35 mA 8 MHz(3)
DC31 55 70 mA 100 MHz(3)
DC32 90 123 mA 200 MHz
Note 1: The test conditions for IIDLE current measurements are as follows:
VDDR1V8 = 1.8V
USB PLL is disabled (USBPMD = 1), VUSB3V3 is connected to VSS, PBCLKx divisor = 1:2 (x 7)
CPU is in Idle mode (CPU core Halted)
No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared (except
USBPMD)
MCLR = VDDIO
I/O Analog Charge Pump is disabled (IOANCPEN bit (CFGCON<7>) = 0)
ADC Input Charge Pump is disabled (AICPMPEN bit (ADCCON1<12> = 0)
2: Data in Typical column is at 3.3V, +25C unless otherwise stated. Parameters are for design guidance
only and are not tested.

TABLE 44-9: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

DC
CHARACTERISTICS(1,2) VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Param.
No.
Power-Down Current (IPD) (Note 1)
DC40k 9 14 mA -40C
DC40l 9.5 14 mA +25C Sleep(1)
DC40m 15 25 mA +85C
Module Differential Current
DC44a 50 350 A 3.6V Watchdog Timer Current: IWDT(3)
DC44b 3.5 5 mA 3.6V ADC Current: IADC(3,4)
DC44c 50 350 A 3.6V Deadman Timer Current: IDMT
Note 1: The test conditions for IPD current measurements are as follows:
USB PLL is disabled (USBMD = 1), VUSB3V3 is connected to VSS
CPU is in Sleep mode
L1 Cache and Prefetch modules are disabled
No peripheral modules are operating, (ON bit = 0), and the associated PMD bit is set. All clocks are
disabled ON bit (PBxDIV<15>) = 0 (x 1,7)
MCLR = VDDIO
Voltage regulator is in Stand-by mode (VREGS = 0; IOANCPEN = 0)
2: Data in the Typical column is at 3.3V, unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: Voltage regulator is operational (VREGS = 1).

TABLE 44-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Param.
Symbol Characteristics Min. Typ.(1) Max. Units Conditions
No.
VIL Input Low Voltage
DI10 I/O Pins with PMP VSS 0.15*VDDIO V
I/O Pins VSS 0.2*VDDIO V
DI18 SDAx, SCLx VSS 0.3*VDDIO V SMBus disabled
(Note 4)
DI19 SDAx, SCLx VSS 0.8 V SMBus enabled
(Note 4)
VIH Input High Voltage
DI20 I/O Pins not 5V-tolerant(5) 0.65*VDDIO VDDIO V (Note 4)
I/O Pins 5V-tolerant with 0.65*VDDIO 5.5 V (Note 4)
PMP(5)
I/O Pins 5V-tolerant(5) 0.65*VDDIO 5.5 V
DI28a SDAx, SCLx on non-5V 0.65*VDDIO VDDIO V SMBus disabled
tolerant pins(5) (Note 4)
DI29a SDAx, SCLx on non-5V 2.1 VDDIO V SMBus enabled,
tolerant pins(5) 2.2V VPIN 5.5
(Note 4)
DI28b SDAx, SCLx on 5V tolerant 0.65*VDDIO 5.5 V SMBus disabled
pins(5) (Note 4)
DI29b SDAx, SCLx on 5V tolerant 2.1 5.5 V SMBus enabled,
pins(5 2.2V VPIN 5.5
(Note 4)
DI30 ICNPU Change Notification -400 -300 -50 A VDDIO = 3.3V, VPIN =
Pull-up Current VSS
DI31 ICNPD Change Notification 50 175 400 A VDDIO = 3.3V, VPIN =
Pull-down Current(4) VDDIO
IIL Input Leakage Current
(Note 3)
DI50 I/O Ports +1 A VSS VPIN VDDIO,
Pin at high-impedance
DI51 Analog Input Pins +1 A VSS VPIN VDDIO,
Pin at high-impedance
DI55 MCLR(2) +1 A VSS VPIN VDDIO
DI56 OSC1 +1 A VSS VPIN VDDIO,
HS mode
Note 1: Data in Typical column is at 3.3V, +25C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
5: See the pin name tables (Table 5 through Table 7) for the 5V-tolerant pins.

TABLE 44-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Param. Sym. Characteristic Min. Typ. Max. Units Conditions(1)
Output Low Voltage
I/O Pins
4x Sink Driver Pins -
RA0-RA3, RA9, RA10, RA14, RA15
RB0, RB4, RB6, RB7, RB10, RB11, RB12,
RB14
RC12-RC15 0.4 V IOL 10 mA, VDDIO = 3.3V
RD6, RD7, RD11, RD14
RE8, RE9
RF2, RF3, RF8, RF12
RG15
RH0, RH1, RH4-RH14
RJ0-RJ2, RJ8, RJ9, RJ11
Output Low Voltage
I/O Pins:
DO10 VOL RA4, RA5
RB2, RB3, RB5, RB8, RB9, RB13, RB14,
RB15
RC1-RC4
0.4 V IOL 15 mA, VDDIO = 3.3V
RD0-RD3, RD9, RD10, RD12, RD13
RE0-RE7
RF0, RF1, RF4, RF5, RF13
RG0, RG1, RG6, RG7, RG8, RG9
RH2, RH3, RH7, RH15
RJ3-RJ7, RJ10, RJ12-RJ15
RK0-RK7
Output Low Voltage
I/O Pins:
0.4 V IOL 20 mA, VDDIO = 3.3V
RA6, RA7
RD4, RD5
RG12-RG14
Note 1: Parameters are characterized, but not tested.

TABLE 44-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED)
Output High Voltage
I/O Pins
RB0, RB4, RB6, RB7, RB10, RB11, RB12,
RB14
RC12-RC15 2.4 V IOH -10 mA, VDDIO = 3.3V
RE8, RE9
RF2, RF3, RF8, RF12
RG15
RH0, RH1, RH4-RH14
Output High Voltage
I/O Pins:
DO20 VOH RA4, RA5
RB2, RB3, RB5, RB8, RB9, RB13, RB14,
RB15
RC1-RC4
2.4 V IOH -15 mA, VDDIO = 3.3V
RE0-RE7
RH2, RH3, RH7, RH15
RK0-RK7
Output High Voltage
I/O Pins:
12x Source Driver Pins -
2.4 V IOH -20 mA, VDDIO = 3.3V
RA6, RA7
RD4, RD5
RG12-RG14

TABLE 44-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS (CONTINUED)
Output High Voltage 1.5 V IOH -14 mA, VDDIO = 3.3V
I/O Pins
4x Sink Driver Pins - 2.0 V IOH -12 mA, VDDIO = 3.3V
RB0, RB4, RB6, RB7, RB10, RB11, RB12,
RB14
RC12-RC15
RE8, RE9 3.0 V IOH -7 mA, VDDIO = 3.3V
RF2, RF3, RF8, RF12
RG15
RH0, RH1, RH4-RH14
I/O Pins:
8x Sink Driver Pins - 2.0 V IOH -18 mA, VDDIO = 3.3V
DO20a VOH1 RA4, RA5
RB2, RB3, RB5, RB8, RB9, RB10, RB13,
RB14, RB15
RC1-RC4
RE0-RE7 3.0 V IOH -10 mA, VDDIO = 3.3V
RH2, RH3, RH7, RH15
RK0-RK7
I/O Pins:
12x Source Driver Pins - 2.0 V IOH -25 mA, VDDIO = 3.3V
RA6, RA7
RD4, RD5 3.0 V IOH -14 mA, VDDIO = 3.3V
RG12-RG14

TABLE 44-12: DC CHARACTERISTICS: I/O PIN INPUT INJECTION CURRENT SPECIFICATIONS
Param.
No.
DI60a IICL Input Low Injection 0 -5(2,5) mA This parameter applies
Current to all pins, with the
exception of RB10.
Maximum IICH current
for this exception is
0 mA.
DI60b IICH Input High Injection 0 +5(3,4,5) mA This parameter applies
Current to all pins, with the
exception of all 5V toler-
ant pins, SOSCI, and
RB10. Maximum IICH
current for these
exceptions is 0 mA.
DI60c IICT Total Input Injection -20(6) +20(6) mA Absolute instantaneous
Current (sum of all I/O sum of all input
and control pins) injection currents from
all I/O pins
( | IICL + | IICH | ) IICT
Note 1: Data in Typical column is at 3.3V, +25C unless otherwise stated. Parameters are for design guidance
2: VIL source < (VSS - 0.3). Characterized but not tested.
3: VIH source > (VDDIO + 0.3) for non-5V tolerant pins only.
4: Digital 5V tolerant pins do not have an internal high side diode to VDDIO, and therefore, cannot tolerate any
positive input injection current.
5: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source >
(VDDIO + 0.3) or VIL source < (VSS - 0.3)).
6: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the absolute instantaneous sum of the input injection currents from all pins do not exceed the spec-
ified limit. If Note 2, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 3, IICH = ((IICH source - (VDDIO + 0.3)) /
RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) VSOURCE (VDDIO +
0.3), injection current = 0.

TABLE 44-13: DDR2 SDRAM CONTROLLER I/O SPECIFICATIONS

Param.
No.
DDR1 VOH Output High VDDR1V8 V
Voltage 0.28
DDR2 VOL Output Low 0.28 V
Voltage
DDR5 VIH Input High Voltage DDRVREF + VDDR1V8 + 0.3
0.125
DDR6 VIL Input Low Voltage 0.3 DDRVREF
0.125
Note 1: These parameters are characterized but not tested.
TABLE 44-14: SD HOST CONTROLLER I/O SPECIFICATIONS

Param.
No.
SD10 VOH Output High Voltage 2.4 V IOH 20 mA, VDDIO = 3.3V
SD11 VOL Output Low Voltage 0.4 V IOL 20 mA, VDDIO = 3.3V
SD12 VIH Input High Voltage 0.65*VDDIO VDDIO V
SD13 VIL Input Low Voltage VSS 0.2*VDDIO V

TABLE 44-15: DC CHARACTERISTICS: PROGRAM MEMORY(3)

Param.
Sym. Characteristics Min. Typ.(1) Max. Units Conditions
No.
D130a EP Cell Endurance 10,000 E/W Without ECC
D130b 20,000 E/W With ECC
D131 VPR VDDCORE for Read VDDCOREMIN VDDCOREMAX V
D132 VPEW VDDCORE for Erase or Write VDDCOREMIN VDDCOREMAX V
D134a TRETD Characteristic Retention 10 Year Without ECC
D134b 20 Year With ECC
D135 IDDP Supply Current during 30 mA
Programming
D136 TRW Row Write Cycle Time (Notes 2, 4) 66813 FRC Cycles
D137 TQWW Quad Word Write Cycle Time
773 FRC Cycles
(Note 4)
D138 TWW Word Write Cycle Time (Note 4) 383 FRC Cycles
D139 TCE Chip Erase Cycle Time (Note 4) 515373 FRC Cycles
D140 TPFE All Program Flash (Upper and Lower
256909 FRC Cycles
regions) Erase Cycle Time (Note 4)
D141 TPBE Program Flash (Upper or Lower
128453 FRC Cycles
regions) Erase Cycle Time (Note 4)
D142 TPGE Page Erase Cycle Time (Note 4) 128453 FRC Cycles
Note 1: Data in Typical column is at 3.3V, +25C unless otherwise stated.
2: The minimum PBCLK5 for row programming is 4 MHz.
3: Refer to the PIC32 Flash Programming Specification (DS60001145) for operating conditions during
programming and erase cycles.
4: This parameter depends on FRC accuracy (see Table 44-27) and FRC tuning values (see the OSCTUN register:
Register 8-2).
TABLE 44-16: DC CHARACTERISTICS: PROGRAM FLASH MEMORY WAIT STATES

Required Flash Wait States(1) SYSCLK Units Conditions
With ECC:
0 Wait states 0 < SYSCLK 60
MHz
1 Wait state 60 < SYSCLK 120
Without ECC:
MHz
1 Wait state 74 < SYSCLK 140
Note 1: To use Wait states, the Prefetch module must be enabled (PREFEN<1:0> 00) and the PFMWS<2:0>
bits must be written with the desired Wait state value.

TABLE 44-17: DC CHARACTERISTICS: DDR2 SDRAM MEMORY

Param.
No. Symbol Characteristics Min. Typ. Max. Units Conditions
(Note 1)
DDRM12 IDD0 Operating Current, One Bank 90 mA Note 2
Active Precharge
DDRM13 IDD1 Operating Current, One Back 100 mA Note 2
Active-Read Precharge
DDRM14 IDD2 Precharge Power-Down Current 8 mA Note 3
DDRM15 IDD3 Precharge Stand-by Current 45 mA Note 2
DDRM16 IDD4 Precharge Quiet Stand-by Current 35 mA Note 4
DDRM17 IDD5 Active Power-Down Current 12 mA Note 3
DDRM18 IDD6 Active Stand-by Current 65 mA Note 2
DDRM19 IDD7 Operating Burst Read Current 140 mA Note 2
DDRM20 IDD8 Operating Burst Write Current 165 mA Note 2
DDRM21 IDD9 Burst Refresh Current 95 mA Note 2
DDRM22 IDD10 Self-Refresh Current 6 mA Note 5
DDRM23 IDD11 Operating Bank Interleave Read 200 mA Note 6
Current
Note 1: These parameters are characterized, but not tested in manufacturing. The specifications are only valid
after the memory is initialized.
2: DDRCKE is high, DDRCS0 is high between valid commands. Address, control, and data bus inputs are
switching.
3: DDRCKE is low. Other control and address inputs are stable. Data bus inputs are floating.
4: DDRCKE is high and DDRCS0 is high. Other control and address inputs are stable. Data bus inputs are
floating.
5: DDRCKE is low and DDRCK/DDRCK are low. Other control and address inputs are floating. Data bus
inputs are floating.
6: DDRCKE is high and DDRCS0 is high between valid commands. Address bus inputs are stable. Data bus
inputs are switching.

TABLE 44-18: COMPARATOR SPECIFICATIONS

Param.
Symbol Characteristics Min. Typ. Max. Units Comments
No.
D300 VIOFF Input Offset Voltage 10 mV AVDD = VDDIO,
AVSS = VSS
D301 VICM Input Common Mode Voltage 0 2.5 V AVDD = VDDIO,
AVSS = VSS
(Note 2)
D302 CMRR Common Mode Rejection Ratio 55 dB Max VICM = (VDDIO - 1)V
(Note 2)
D303 TRESP Response Time 150 ns AVDD = VDDIO,
AVSS = VSS
(Notes 1,2)
D304 ON2OV Comparator Enabled to Output 10 s Comparator module is
Valid configured before setting
the comparator ON bit
(Note 2)
D305 IVREF Internal Voltage Reference 1.2 V
D306 VHYST Input Hysteresis Voltage 48 120 192 mV
Note 1: Response time measured with one comparator input at (VDDIO 1.5)/2, while the other input transitions
from VSS to VDDIO.
2: These parameters are characterized but not tested.
3: The Comparator module is functional at VBORIOMIN < VDDIO < VDDIOMIN, but with degraded performance.
Unless otherwise stated, module functionality is guaranteed, but not characterized.

TABLE 44-19: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Param.
Symbol Characteristics Min. Typ. Max. Units Comments
No.
D312 TSET Internal 4-bit DAC 10 s See Note 1
Comparator Reference
Settling time
D313 DACREFH CVREF Input Voltage AVSS AVDD V CVRSRC with CVRSS = 0
Reference Range VREF- VREF+ V CVRSRC with CVRSS = 1
D314 DVREF CVREF Programmable 0 0.625 x V 0 to 0.625 DACREFH with
Output Range DACREFH DACREFH/24 step size
0.25 x 0.719 x V 0.25 x DACREFH to 0.719
DACREFH DACREFH DACREFH with DACREFH/32
step size
D315 DACRES Resolution DACREFH/24 CVRCON<CVRR> = 1
DACREFH/32 CVRCON<CVRR> = 0
D316 DACACC Absolute Accuracy(2) 1/4 LSB DACREFH/24,
CVRCON<CVRR> = 1
1/2 LSB DACREFH/32,
CVRCON<CVRR> = 0
Note 1: Settling time was measured while CVRR = 1 and CVR<3:0> transitions from 0000 to 1111. This param-
eter is characterized, but is not tested in manufacturing.
2: These parameters are characterized but not tested.

TABLE 44-20: CTMU CURRENT SOURCE SPECIFICATIONS

DC CHARACTERISTICS Standard Operating Conditions: VDDIO = 2.2V to 3.6V,
VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Param
No.
CTMU CURRENT SOURCE
CTMUI1 IOUT1 Base Range(1) 0.55 A CTMUICON<9:8> = 01
CTMUI2 IOUT2 10x Range(1) 5.5 A CTMUICON<9:8> = 10
CTMUI3 IOUT3 100x Range(1) 55 A CTMUICON<9:8> = 11
CTMUI4 IOUT4 1000x Range(1) 550 A CTMUICON<9:8> = 00
CTMUFV1 VF Temperature Diode Forward 0.598 V TA = +25C,
Voltage(1,2) CTMUICON<9:8> = 01
0.658 V TA = +25C,
CTMUICON<9:8> = 10
0.721 V TA = +25C,
CTMUICON<9:8> = 11
CTMUFV2 VFVR Temperature Diode Rate of -1.92 mV/C CTMUICON<9:8> = 01
Change(1,2) -1.74 mV/C CTMUICON<9:8> = 10
-1.56 mV/C CTMUICON<9:8> = 11
Note 1: Nominal value at center point of current trim range (CTMUICON<15:10> = 000000).
2: Parameters are characterized but not tested in manufacturing. Measurements taken with the following
conditions:
VREF+ = AVDD = 3.3V
ADC module configured for conversion speed of 500 ksps
All PMD bits are cleared (PMDx = 0)
Executing a while(1) statement
Device operating from the FRC with no PLL
TABLE 44-21: GLCD CONTROLLER DC SPECIFICATIONS

Param.
No.
GD10 VOH Output High Voltage 2.4 V IOH 20 mA, VDDIO = 3.3V
GD11 VOL Output Low Voltage 0.4 V IOL 20 mA, VDDIO = 3.3V
GD12 VIH Input High Voltage 0.65*VDDIO VDDIO V
GD13 VIL Input Low Voltage VSS 0.2*VDDIO V

44.2 AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MZ DA device AC characteristics and timing
parameters.
FIGURE 44-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 for all pins except OSC2 Load Condition 2 for OSC2 (in EC mode)
VDDIO/2
RL Pin CL
VSS
CL
Pin RL = 464
VSS
TABLE 44-22: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

AC CHARACTERISTICS VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Param.
No.
DO50 COSCO OSC2 Pin 15 pF In HS mode when the external
clock is used to drive OSC1
DO56 CL All I/O pins 50 pF EC mode for OSC2
DO58 CB SCLx, SDAx 400 pF In I2C mode
DO59 CSQI All SQI pins 10 pF
Note 1: Data in Typical column is at 3.3V, +25C unless otherwise stated. Parameters are for design guidance

FIGURE 44-2: EXTERNAL CLOCK TIMING
OS20 OS30 OS31
OSC1
OS30 OS31
TABLE 44-23: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.
No.
OS10 FOSC External CLKI Frequency DC 64 MHz EC (Note 2)
(External clocks allowed only
in EC and ECPLL modes)
OS13 Oscillator Crystal Frequency 4 32 MHz HS (Note 2)
OS15 32 32.768 100 kHz SOSC (Note 2)
OS20 TOSC TOSC = 1/FOSC See parameter
OS10 for FOSC
value
OS30 TOSL, External Clock In (OSC1) 0.375 x TOSC ns EC (Note 2)
TOSH High or Low Time
OS31 TOSR, External Clock In (OSC1) 7.5 ns EC (Note 2)
TOSF Rise or Fall Time
OS40 TOST Oscillator Start-up Timer Period 1024 TOSC (Note 2)
(Only applies to HS, HSPLL,
and SOSC Clock Oscillator
modes)
OS41 TFSCM Primary Clock Fail Safe 2 ms (Note 2)
Time-out Period
OS42 GM External Oscillator 400 A/V VDDIO = 3.3V,
Transconductance TA = +25C
(Note 2)
Note 1: Data in Typical column is at 3.3V, +25C unless otherwise stated. Parameters are characterized but are
not tested.

TABLE 44-24: SYSTEM TIMING REQUIREMENTS
Param.
No.
OS51 FSYS System Frequency DC 200 MHz USB module disabled
30 200 MHz USB module enabled
OS55a FPB Peripheral Bus Frequency DC 100 MHz For PBCLKx, x < 7
OS55b DC 200 MHz For PBCLK7
OS56 FREF Reference Clock Frequency 50 MHz For REFCLK1, REFCLK3,
REFCLK4, REFCLKO1,
REFCLK3, and REFCLK4
pins
TABLE 44-25: SPLL CLOCK TIMING SPECIFICATIONS

Param.
Symbol Characteristics(1) Min. Typ. Max. Units Conditions
No.
OS50 FIN PLL Input Frequency Range 5 64 MHz ECPLL, HSPLL, FRCPLL
modes
OS52 TLOCK PLL Start-up Time (Lock Time) 100 s
OS53 DCLK CLKO Stability(2) -0.25 +0.25 % Measured over 100 ms
(Period Jitter or Cumulative) period
OS54 FVCO PLL VCO Frequency Range 350 700 MHz
OS54a FPLL PLL Output Frequency Range 10 200 MHz
Note 1: These parameters are characterized, but not tested in manufacturing.
2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for
individual time-bases on communication clocks, use the following formula:
D CLK
EffectiveJitter = --------------------------------------------------------------
PBCLK2
----------------------------------------------------------
CommunicationClock
For example, if PBCLK2 = 100 MHz and SPI bit rate = 50 MHz, the effective jitter is as follows:
D CLK D CLK
EffectiveJitter = -------------- = -------------
-
100 1.41
---------
50

TABLE 44-26: MPLL CLOCK TIMING REQUIREMENTS

Param.
Symbol Characteristic(1) Min. Typ. Max. Units Conditions
No.
MP10 MFIN MPLL Input Frequency 8 64 MHz
MP11 MFVCO MPLL Vco Frequency Range 400 1600 MHz
MP12 MFMPLL MPLL Output Frequency 8 400 MHz
MP13 MLOCK MPLL Start-up Time (Lock Time) 1500 x s
1/MFIN
MP14 MPJ MPLL Period Jitter 0.015 %
MP15 MCJ MPLL Cycle Jitter 0.02 %
MP16 MLTJ MPLL Long-term Jitter 0.5 %
Note 1: These parameters are characterized, but not test in manufacturing.

TABLE 44-27: INTERNAL FRC ACCURACY

Param.
Characteristics Min. Typ. Max. Units Conditions
No.
Internal FRC Accuracy @ 8.00 MHz(1)
F20 FRC -5 +5 % 0C TA +85C
-8 +8 % -40C TA +85C
Note 1: Frequency calibrated at +25C and 3.3V. The TUN bits can be used to compensate for temperature drift.
TABLE 44-28: INTERNAL LPRC ACCURACY

Param.
No.
LPRC @ 31.25 kHz(1)
F21 LPRC -8 +8 % 0C TA +85C
-25 +25 % -40C TA +85C
Note 1: Change of LPRC frequency as VDDIO changes.
TABLE 44-29: INTERNAL BACKUP FRC (BFRC) ACCURACY

Param.
No.
Internal BFRC Accuracy @ 8 MHzl
F22 BFRC -30 +30 %

FIGURE 44-3: I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
DO31
DO32
Note: Refer to Figure 44-1 for load conditions.
TABLE 44-30: I/O TIMING REQUIREMENTS

Param.
Symbol Characteristics(2) Min. Typ.(1) Max. Units Conditions
No.
DO31 TIOR Port Output Rise Time
I/O Pins:
RA3, RA9, RA10, RA14, RA15 9.5 ns CLOAD = 50 pF
RB0-7, RB11, RB13
RC12-RC15
RD0, RD6-RD7, RD11, RD14
RE8, RE9
RF2, RF3, RF8
RG15 6 ns CLOAD = 20 pF
RH0, RH1, RH4-RH6, RH8-RH13
Port Output Rise Time

I/O Pins:
RA0-RA2, RA4, RA5 8 ns CLOAD = 50 pF
RB8-RB10, RB12, RB14, RB15
RC1-RC4
RD1-RD5, RD9, RD10, RD12,
RD13, RD15
RE4-RE7
RG0, RG1, RG6-RG9 6 ns CLOAD = 20 pF
RH2, RH3, RH7, RH14, RH15
RK0-RK7
Port Output Rise Time
I/O Pins: 3.5 ns CLOAD = 50 pF
RA6, RA7
RE0-RE3
RF1 2 ns CLOAD = 20 pF
RG12-RG14

TABLE 44-30: I/O TIMING REQUIREMENTS (CONTINUED)
Param.
No.
DO32 TIOF Port Output Fall Time
I/O Pins:
RA3, RA9, RA10, RA14, RA15 9.5 ns CLOAD = 50 pF
RB0-7, RB11, RB13
RC12-RC15
RD0, RD6-RD7, RD11, RD14
RE8, RE9
RF2, RF3, RF8
RG15 6 ns CLOAD = 20 pF
RH0, RH1, RH4-RH6, RH8-RH13
Port Output Fall Time

I/O Pins:
RA0-RA2, RA4, RA5 8 ns CLOAD = 50 pF
RB8-RB10, RB12, RB14, RB15
RC1-RC4
RD1-RD5, RD9, RD10, RD12,
RD13, RD15
RE4-RE7
RG0, RG1, RG6-RG9 6 ns CLOAD = 20 pF
RH2, RH3, RH7, RH14, RH15
RK0-RK7
Port Output Fall Time
I/O Pins: 3.5 ns CLOAD = 50 pF
RA6, RA7
RE0-RE3
RF1 2 ns CLOAD = 20 pF
RG12-RG14
DI35 TINP INTx Pin High or Low Time 5 ns
DI40 TRBP CNx High or Low Time (input) 5 ns

FIGURE 44-4: POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled

Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDDCORE
VPORCORE
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code

SY00
(TPU)
(Note 1)

Clock Sources = (HS, HSPLL, and SOSC)
VDDCORE
VPORCORE (TSYSDLY)
SY02
Power-up Sequence
(Note 2)

SY00 OS40
(TPU) (TOST)
(Note 1)
Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDDIO < VDDIOMIN).
2: Includes interval voltage regulator stabilization delay.

FIGURE 44-5: EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR
(SY20)
VBORIO
TBOR (TSYSDLY)
(SY30) SY02
Reset Sequence
Clock Sources = (HS, HSPLL, and SOSC) (TSYSDLY)

SY02
Reset Sequence

TOST
(OS40)
TABLE 44-31: RESETS TIMING

Param.
No.
SY00 TPU Power-up Period 400 600 s
SY02 TSYSDLY System Delay Period: s +
Time Required to Reload Device 8 SYSCLK
Configuration Fuses plus SYSCLK cycles
Delay before First instruction is
Fetched.
SY20 TMCLR MCLR Pulse Width (low) 2 s
SY30 TBOR BOR Pulse Width (low) 1 s
2: Data in Typical column is at 3.3V, +25C unless otherwise stated. Characterized by design but not tested.

FIGURE 44-6: TIMER1-TIMER9 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRx
TABLE 44-32: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

Param.
No.
TA10 TTXH TxCK Synchronous, [(12.5 ns or 1 TPBCLK3) ns Must also meet
High Time with prescaler /N] + 20 ns parameter TA15
(Note 3)
Asynchronous, 10 ns
with prescaler
TA11 TTXL TxCK Synchronous, [(12.5 ns or 1 TPBCLK3) ns Must also meet
Low Time with prescaler /N] + 20 ns parameter TA15
(Note 3)
Asynchronous, 10 ns
with prescaler
TA15 TTXP TxCK Synchronous, [(Greater of 20 ns or ns VDDIO > 2.7V
Input Period with prescaler 2 TPBCLK3)/N] + 30 ns (Note 3)
[(Greater of 20 ns or ns VDDIO < 2.7V
2 TPBCLK3)/N] + 50 ns (Note 3)
Asynchronous, 20 ns VDDIO > 2.7V
with prescaler 50 ns VDDIO < 2.7V
OS60 FT1 SOSC1/T1CK Oscillator 32 50 kHz
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON<1>))
TA20 TCKEXTMRL Delay from External TxCK 1 TPBCLK3
Clock Edge to Timer
Increment
Note 1: Timer1 is a Type A.
3: N = Prescale Value (1, 8, 64, 256).

TABLE 44-33: TIMER2-TIMER9 EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
Symbol Characteristics(1) Min. Max. Units Conditions
No.
TB10 TTXH TxCK Synchronous, with [(12.5 ns or 1 TPBCLK3) ns Must also N = prescale
High Time prescaler /N] + 25 ns meet value
parameter (1, 2, 4, 8,
TB15 16, 32, 64,
TB11 TTXL TxCK Synchronous, with [(12.5 ns or 1 TPBCLK3) ns Must also 256)
Low Time prescaler /N] + 25 ns meet
parameter
TB15
TB15 TTXP TxCK Synchronous, with [(Greater of [(25 ns or ns VDDIO >
Input prescaler 2 TPBCLK3)/N] + 30 ns 2.7V
Period [(Greater of [(25 ns or ns VDDIO <
2 TPBCLK3)/N] + 50 ns 2.7V
TB20 TCKEXTMRL Delay from External TxCK 1 TPBCLK3
Clock Edge to Timer Increment
FIGURE 44-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICx
IC10 IC11
IC15
TABLE 44-34: INPUT CAPTURE MODULE TIMING REQUIREMENTS

Param.
Symbol Characteristics(1) Min. Max. Units Conditions
No.
IC10 TCCL ICx Input Low Time [(12.5 ns or 1 TPBCLK3) ns Must also N = prescale
/N] + 25 ns meet value (1, 4, 16)
parameter
IC15.
IC11 TCCH ICx Input High Time [(12.5 ns or 1 TPBCLK3) ns Must also
/N] + 25 ns meet
parameter
IC15.
IC15 TCCP ICx Input Period [(25 ns or 2 TPBCLK3) ns
/N] + 50 ns

FIGURE 44-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM mode) OC11 OC10
TABLE 44-35: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

Param.
No.
OC10 TCCF OCx Output Fall Time ns See parameter DO32
OC11 TCCR OCx Output Rise Time ns See parameter DO31
FIGURE 44-9: OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx OCx is tri-stated
TABLE 44-36: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS

Param
Symbol Characteristics(1) Min, Typ.(2) Max, Units Conditions
No.
OC15 TFD Fault Input to PWM I/O Change 50 ns
OC20 TFLT Fault Input Pulse Width 50 ns

FIGURE 44-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11 SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP20 SP21
SDOx MSb Bit 14 - - - - - -1 LSb
SP31 SP30
SDIx MSb In Bit 14 - - - -1 LSb In
SP40 SP41

TABLE 44-37: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS

Param.
No.
SP10 TSCL SCKx Output Low Time (Note 3) TSCK/2 ns Note 5
SP11 TSCH SCKx Output High Time (Note 3) TSCK/2 ns Note 5
SP15 TSCK SPI Clock Speed (Note 5) 25 MHz SPI1, SPI3, SPI4, SPI6
50 MHz SPI2 on RPG7, RPG8
25 MHz SPI2 on other I/O
50 MHz SPI5 on RPC1, RPC4
SP20 TSCF SCKx Output Fall Time (Note 4) ns See parameter DO32
SP21 TSCR SCKx Output Rise Time (Note 4) ns See parameter DO31
SP30 TDOF SDOx Data Output Fall Time ns See parameter DO32
(Note 4)
SP31 TDOR SDOx Data Output Rise Time ns See parameter DO31
(Note 4)
SP35 TSCH2DOV, SDOx Data Output Valid after 7 ns VDDIO > 2.7V
TSCL2DOV SCKx Edge 10 ns VDDIO < 2.7V
SP40 TDIV2SCH, Setup Time of SDIx Data Input to 5 ns
TDIV2SCL SCKx Edge
SP41 TSCH2DIL, Hold Time of SDIx Data Input 5 ns
TSCL2DIL to SCKx Edge
3: The minimum clock period for SCKx is 20 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 30 pF load on all SPIx pins.
5: To achieve maximum data rate, VDDIO must be greater than or equal to 3.0V and the SMP bit
(SPIxCON<9>) must be set to 1.

FIGURE 44-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11 SP10 SP21 SP20
SCKX
(CKP = 1)
SP35
SP20 SP21
SDOX MSb Bit 14 - - - - - -1 LSb
SP30,SP31
SDIX MSb In Bit 14 - - - -1 LSb In

SP40 SP41

TABLE 44-38: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

Param.
No.
SP10 TSCL SCKx Output Low Time (Note 3) TSCK/2 ns Note 5
SP11 TSCH SCKx Output High Time (Note 3) TSCK/2 ns Note 5
SP15 TSCK SPI Clock Speed (Note 5) 25 MHz SSPI1, SPI3, SPI4, SPI6
50 MHz SPI2 on RPG7, RPG8
50 MHz SPI5 on RPC1, RPC4
SP20 TSCF SCKx Output Fall Time (Note 4) ns See parameter DO32
SP21 TSCR SCKx Output Rise Time (Note 4) ns See parameter DO31
(Note 4)
(Note 4)
TSCL2DOV SCKx Edge 10 VDDIO < 2.7V
SP36 TDOV2SC, SDOx Data Output Setup to
7 ns
TDOV2SCL First SCKx Edge
SP40 TDIV2SCH, Setup Time of SDIx Data Input to 7 ns VDDIO > 2.7V
TDIV2SCL SCKx Edge 10 VDDIO < 2.7V
SP41 TSCH2DIL, Hold Time of SDIx Data Input 7 ns VDDIO > 2.7V
TSCL2DIL to SCKx Edge 10 ns VDDIO < 2.7V
3: The minimum clock period for SCKx is 20 ns. Therefore, the clock generated in Master mode must not
violate this specification.
5: To achieve maximum data rate, VDDIO must be greater than or equal to 3.0V and the SMP bit (SPIx-
CON<9>) must be set to 1.

FIGURE 44-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP50 SP52
SCKX
(CKP = 0)
SP71 SP70
SP73 SP72
SCKX
(CKP = 1)
SP72 SP73
SP35
SDOX MSb Bit 14 - - - - - -1 LSb
SP30,SP31 SP51
SDIX MSb In Bit 14 - - - -1 LSb In

SP40 SP41
TABLE 44-39: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

Operating temperature -40C TA +85C for
Industrial
Param.
No.
SP70 TSCL SCKx Input Low Time (Note 3) TSCK/2 ns Note 5
SP71 TSCH SCKx Input High Time (Note 3) TSCK/2 ns Note 5
SP72 TSCF SCKx Input Fall Time ns See parameter DO32
SP73 TSCR SCKx Input Rise Time ns See parameter DO31
SP30 TDOF SDOx Data Output Fall Time (Note 4) ns See parameter DO32
SP31 TDOR SDOx Data Output Rise Time (Note 4) ns See parameter DO31
SP40 TDIV2SCH, Setup Time of SDIx Data Input 5 ns
TDIV2SCL to SCKx Edge
SP50 TSSL2SCH, SSx to SCKx or SCKx Input 88 ns
TSSL2SCL
SP51 TSSH2DOZ SSx to SDOx Output 2.5 12 ns
High-Impedance (Note 3)
3: The minimum clock period for SCKx is 20 ns.
5: TSCK is 40 ns for SPI1, SPI3, SPI4, and SPI6 and it is 20 ns for SPI2 and SPI5.

TABLE 44-39: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS (CONTINUED)
Operating temperature -40C TA +85C for
Industrial
Param.
No.
SP52 TSCH2SSH SSx after SCKx Edge 10 ns
TSCL2SSH
FIGURE 44-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

SP60
SSx
SP50 SP52
SCKx
(CKP = 0)
SP71 SP70 SP73 SP72
SCKx
(CKP = 1)
SP35
SP72 SP73
SDOx MSb Bit 14 - - - - - -1 LSb
SP30,SP31 SP51
SDIx
SDI
MSb In Bit 14 - - - -1 LSb In
SP40 SP41

TABLE 44-40: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
(x = 1, 3, 4, 6)
Param.
No.
SP70 TSCL SCKx Input Low Time (Note 3) TSCK/2 ns Note 5
SP71 TSCH SCKx Input High Time (Note 3) TSCK/2 ns Note 5
SP72 TSCF SCKx Input Fall Time 10 ns
SP73 TSCR SCKx Input Rise Time 10 ns
(Note 4)
(Note 4)
SP40 TDIV2SCH, Setup Time of SDIx Data Input 0 ns
TDIV2SCL to SCKx Edge
SP50 TSSL2SCH, SSx to SCKx or SCKx Input 88 ns
TSSL2SCL
SP51 TSSH2DOZ SSx to SDOX Output 2.5 12 ns
High-Impedance
(Note 4)
SP52 TSCH2SSH SSx after SCKx Edge 10 ns
TSCL2SSH
SP60 TSSL2DOV SDOx Data Output Valid after 12.5 ns
SSx Edge

FIGURE 44-14: SQI SERIAL INPUT TIMING CHARACTERISTICS
T CPH
CE#
T CEH T CHS
T CHH T CES
SCK
T DS TDH T SCKF
T SCKR
SIO MSB LSB
FIGURE 44-15: SQI SERIAL OUTPUT TIMING CHARACTERISTICS
CE#
T SCKH TSCKL
SCK
T OH
TCLZ T CHZ
SIO MSB LSB
TV
TABLE 44-41: SQI TIMING REQUIREMENTS

Param.
No.
SQ10 FCLK Serial Clock Frequency 80 MHz DMA Read mode, SDR mode
(1/TSQI) 66 MHz DMA Read mode, DDR mode
100 MHz PIO Write mode, SDR mode
SQ11 TSCKH Serial Clock High Time 6 ns
SQ12 TSCKL Serial Clock Low Time 6 ns
SQ13 TSCKR Serial Clock Rise Time 0.25 ns
SQ14 TSCKF Serial Clock Fall Time 0.25 ns
SQ15 TCSS (TCES) CS Active Setup Time 5 ns
SQ16 TCSH (TCEH) CS Active Hold Time 5 ns
SQ17 TCHS CS Not Active Setup Time 3 ns
SQ18 TCHH CS Not Active Hold Time 3 ns
SQ19 TCPH CS High Time 6 ns
SQ20 TCHZ CS High to High-Z Data Out 6 ns
SQ21 TCLZ SCK Low to Low-Z Data Out 0 ns
SQ22 TDS Data In Setup Time 3 ns
SQ23 TDH Data In Hold Time 4 ns
SQ24 TOH Data Out Hold 0 ns
SQ25 TOV (TV) Data Out Valid 6 ns

FIGURE 44-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31 IM34
IM30 IM33
SDAx
Start Condition Stop Condition

FIGURE 44-17: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20 IM11 IM21

IM10
SCLx
IM11 IM26
IM10 IM25 IM33
SDAx
In
IM40 IM40 IM45
SDAx
Out
TABLE 44-42: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)

Param.
Symbol Characteristics Min.(1) Max. Units Conditions
No.
IM10 TLO:SCL Clock Low Time 100 kHz mode TPBCLK2 * (BRG + 2) s
400 kHz mode TPBCLK2 * (BRG + 2) s
1 MHz mode TPBCLK2 * (BRG + 2) s
(Note 2)
IM11 THI:SCL Clock High Time 100 kHz mode TPBCLK2 * (BRG + 2) s
400 kHz mode TPBCLK2 * (BRG + 2) s
(Note 2)
IM20 TF:SCL SDAx and SCLx 100 kHz mode 300 ns CB is specified to be
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode 100 ns
(Note 2)
Note 1: BRG is the value of the I2C Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: The typical value for this parameter is 104 ns.

TABLE 44-42: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
Param.
Symbol Characteristics Min.(1) Max. Units Conditions
No.
IM21 TR:SCL SDAx and SCLx 100 kHz mode 1000 ns CB is specified to be
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode 300 ns
(Note 2)
IM25 TSU:DAT Data Input 100 kHz mode 250 ns
Setup Time 400 kHz mode 100 ns
1 MHz mode 100 ns
(Note 2)
IM26 THD:DAT Data Input 100 kHz mode 0 s
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode 0 0.3 s
(Note 2)
IM30 TSU:STA Start Condition 100 kHz mode TPBCLK2 * (BRG + 2) s Only relevant for
Setup Time 400 kHz mode TPBCLK2 * (BRG + 2) s Repeated Start
condition
(Note 2)
IM31 THD:STA Start Condition 100 kHz mode TPBCLK2 * (BRG + 2) s After this period, the
Hold Time 400 kHz mode TPBCLK2 * (BRG + 2) s first clock pulse is
generated
(Note 2)
IM33 TSU:STO Stop Condition 100 kHz mode TPBCLK2 * (BRG + 2) s
Setup Time 400 kHz mode TPBCLK2 * (BRG + 2) s
(Note 2)
IM34 THD:STO Stop Condition 100 kHz mode TPBCLK2 * (BRG + 2) ns
Hold Time 400 kHz mode TPBCLK2 * (BRG + 2) ns
1 MHz mode TPBCLK2 * (BRG + 2) ns
(Note 2)
IM40 TAA:SCL Output Valid 100 kHz mode 3500 ns
from Clock 400 kHz mode 1000 ns
1 MHz mode 350 ns
(Note 2)
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 s The amount of time
400 kHz mode 1.3 s the bus must be free
before a new
1 MHz mode 0.5 s
transmission can start
(Note 2)
IM50 CB Bus Capacitive Loading pF See parameter DO58
IM51 TPGD Pulse Gobbler Delay 52 312 ns See Note 3
Note 1: BRG is the value of the I2C Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: The typical value for this parameter is 104 ns.

FIGURE 44-18: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31 IS34
IS30 IS33
SDAx
Start Stop
Condition Condition
FIGURE 44-19: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20 IS11 IS21

IS10
SCLx
IS30 IS26
IS31 IS25 IS33
SDAx
In
IS40 IS40 IS45
SDAx
Out
TABLE 44-43: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

Param.
Symbol Characteristics Min. Max. Units Conditions
No.
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 s PBCLK must operate at a
minimum of 800 kHz
400 kHz mode 1.3 s PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode 0.5 s
(Note 1)
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 s PBCLK must operate at a
minimum of 800 kHz
400 kHz mode 0.6 s PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode 0.5 s
(Note 1)
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

TABLE 44-43: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
Param.
Symbol Characteristics Min. Max. Units Conditions
No.
IS20 TF:SCL SDAx and SCLx 100 kHz mode 300 ns CB is specified to be from
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode 100 ns
(Note 1)
IS21 TR:SCL SDAx and SCLx 100 kHz mode 1000 ns CB is specified to be from
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode 300 ns
(Note 1)
IS25 TSU:DAT Data Input 100 kHz mode 250 ns
1 MHz mode 100 ns
(Note 1)
IS26 THD:DAT Data Input 100 kHz mode 0 ns
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode 0 0.3 s
(Note 1)
IS30 TSU:STA Start Condition 100 kHz mode 4700 ns Only relevant for Repeated
Setup Time 400 kHz mode 600 ns Start condition
1 MHz mode 250 ns
(Note 1)
IS31 THD:STA Start Condition 100 kHz mode 4000 ns After this period, the first
Hold Time 400 kHz mode 600 ns clock pulse is generated
1 MHz mode 250 ns
(Note 1)
IS33 TSU:STO Stop Condition 100 kHz mode 4000 ns
1 MHz mode 600 ns
(Note 1)
IS34 THD:STO Stop Condition 100 kHz mode 4000 ns
Hold Time 400 kHz mode 600 ns
1 MHz mode 250 ns
(Note 1)
IS40 TAA:SCL Output Valid from 100 kHz mode 0 3500 ns
Clock 400 kHz mode 0 1000 ns
1 MHz mode 0 350 ns
(Note 1)
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 s The amount of time the bus
400 kHz mode 1.3 s must be free before a new
transmission can start
1 MHz mode 0.5 s
(Note 1)
IS50 CB Bus Capacitive Loading pF See parameter DO58
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

FIGURE 44-20: CANx MODULE I/O TIMING CHARACTERISTICS
CiTx Pin
Old Value New Value
(output)
CA10 CA11
CiRx Pin
(input)
CA20
TABLE 44-44: CANx MODULE I/O TIMING REQUIREMENTS

Param
Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions
No.
CA10 TioF Port Output Fall Time ns See parameter DO32
CA11 TioR Port Output Rise Time ns See parameter DO31
CA20 Tcwf Pulse Width to Trigger 700 ns
CAN Wake-up Filter
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in Typ column is at 3.3V, +25C unless otherwise stated. Parameters are for design guidance only
and are not tested.

TABLE 44-45: ADC MODULE SPECIFICATIONS

Param.
No.
Device Supply
AD01 AVDD Module VDDIO Supply Greater of Lesser of
VDDIO 0.3 VDDIO + V
or 2.3 0.3 or 3.6
AD02 AVSS Module VSS Supply VSS VSS + 0.3 V
Reference Inputs
AD05 VREFH Reference Voltage High VREFL + 1.8 AVDD V (Note 1)
AD06 VREFL Reference Voltage Low AVSS VREFH 1.8 V (Note 1)
AD07 VREF Absolute Reference 1.8 AVDD V (Note 2)
Voltage (VREFH VREFL)
AD08 IREF Current Drain 102 A ADC is operating or is in
Stand-by.
Analog Input
AD12 VINH-VINL Full-Scale Input Span VREFL VREFH V
AD13 VINL Absolute VINL Input AVSS VREFL V
Voltage
AD14 VINH Absolute VINH Input AVSS VREFH V
Voltage
ADC Accuracy Measurements with External VREF+/VREF-
AD20c Nr Resolution 6 12 bits Selectable 6, 8, 10, 12
Resolution Ranges
AD21c INL Integral Nonlinearity 3 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD22c DNL Differential Nonlinearity 1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD23c GERR Gain Error 8 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD24c EOFF Offset Error 2 LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD25c Monotonicity Guaranteed (Note 2)
Dynamic Performance
AD31b SINAD Signal to Noise and 65 dB Single-ended (Notes 2,3)
Distortion
AD34b ENOB Effective Number of bits 10.5 bits (Notes 2,3)
Note 1: These parameters are not characterized or tested in manufacturing.
2: These parameters are characterized, but not tested in manufacturing.
3: Characterized with a 1 kHz sine wave.
4: The ADC module is functional at VBORIOMIN < VDDIO < VDDIOMIN, but with degraded performance. Unless
otherwise stated, module functionality is guaranteed, but not characterized.

TABLE 44-46: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS

AC CHARACTERISTICS(2) VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Param.
No.
Clock Parameters
AD50 TAD ADC Clock Period 20 6250 ns
Throughput Rate
AD51 FTP Sample Rate for 3.125 Msps 12-bit resolution Source Impedance 200
ADC0-ADC4 3.57 Msps 10-bit resolution Source Impedance 200
(Class 1 Inputs) 4.16 Msps 8-bit resolution Source Impedance 200
5 Msps 6-bit resolution Source Impedance 200
Sample Rate for 2.94 Msps 12-bit resolution Source Impedance 200
ADC7 3.33 Msps 10-bit resolution Source Impedance 200
(Class 2 and Class 3.84 Msps 8-bit resolution Source Impedance 200
3 Inputs) 4.55 Msps 6-bit resolution Source Impedance 200
Timing Parameters
AD60 TSAMP Sample Time for 3 Source Impedance 200, Max ADC clock
ADC0-ADC4 4 Source Impedance 500, Max ADC clock
TAD
(Class 1 Inputs) 5 Source Impedance 1 K, Max ADC clock
13 Source Impedance 5 K, Max ADC clock
Sample Time for 4 Source Impedance 200, Max ADC clock
ADC7 5 Source Impedance 500, Max ADC clock
TAD
(Class 2 and Class 6 Source Impedance 1 K, Max ADC clock
3 Inputs) 14 Source Impedance 5 K, Max ADC clock
Sample Time for
See
ADC7
Table TAD CVDEN (ADCCON1<11>) = 1
(Class 2 and Class
44-47
3 Inputs)
AD62 TCONV Conversion Time 13 12-bit resolution
(after sample time is 11 10-bit resolution
TAD
complete) 9 8-bit resolution
7 6-bit resolution
AD65 TWAKE Wake-up time from 500 TAD
Low-Power Mode Lesser of 500 TAD or 20 s.
20 s
2: The ADC module is functional at VBORIOMIN < VDDIO < VDDIOMIN, but with degraded performance.
Unless otherwise stated, module functionality is guaranteed, but not characterized.

TABLE 44-47: ADC SAMPLE TIMES WITH CVD ENABLED
AC CHARACTERISTICS(2) VDDCORE = 1.7V to 1.9V (unless otherwise stated)
Param.
No.
AD60a TSAMP Sample Time for Source Impedance 200
ADC7 (Class 2 and 8 CVDCPL<2:0> (ADCCON2<28:26>) = 001
Class 3 Inputs) with 9 CVDCPL<2:0> (ADCCON2<28:26>) = 010
the CVDEN bit 11 CVDCPL<2:0> (ADCCON2<28:26>) = 011
TAD
(ADCCON1<11>) = 1 12 CVDCPL<2:0> (ADCCON2<28:26>) = 100
14 CVDCPL<2:0> (ADCCON2<28:26>) = 101
16 CVDCPL<2:0> (ADCCON2<28:26>) = 110
17 CVDCPL<2:0> (ADCCON2<28:26>) = 111
Source Impedance 500
10 CVDCPL<2:0> (ADCCON2<28:26>) = 001
12 CVDCPL<2:0> (ADCCON2<28:26>) = 010
14 CVDCPL<2:0> (ADCCON2<28:26>) = 011
TAD
16 CVDCPL<2:0> (ADCCON2<28:26>) = 100
18 CVDCPL<2:0> (ADCCON2<28:26>) = 101
19 CVDCPL<2:0> (ADCCON2<28:26>) = 110
21 CVDCPL<2:0> (ADCCON2<28:26>) = 111
Source Impedance 1 K
13 CVDCPL<2:0> (ADCCON2<28:26>) = 001
16 CVDCPL<2:0> (ADCCON2<28:26>) = 010
18 CVDCPL<2:0> (ADCCON2<28:26>) = 011
TAD
21 CVDCPL<2:0> (ADCCON2<28:26>) = 100
23 CVDCPL<2:0> (ADCCON2<28:26>) = 101
26 CVDCPL<2:0> (ADCCON2<28:26>) = 110
28 CVDCPL<2:0> (ADCCON2<28:26>) = 111
Source Impedance 5 K
41 CVDCPL<2:0> (ADCCON2<28:26>) = 001
48 CVDCPL<2:0> (ADCCON2<28:26>) = 010
56 CVDCPL<2:0> (ADCCON2<28:26>) = 011
TAD
63 CVDCPL<2:0> (ADCCON2<28:26>) = 100
70 CVDCPL<2:0> (ADCCON2<28:26>) = 101
78 CVDCPL<2:0> (ADCCON2<28:26>) = 110
85 CVDCPL<2:0> (ADCCON2<28:26>) = 111
2: The ADC module is functional at VBORIOMIN < VDDIO < VDDIOMIN, but with degraded performance. Unless
otherwise stated, module functionality is guaranteed, but not characterized.

TABLE 44-48: TEMPERATURE SENSOR SPECIFICATIONS

Param.
No.
TS10 VTS Rate of Change 5 mV/C
TS11 TR Resolution -2 +2 C
TS12 IVTEMP Voltage Range 0.5 1.5 V
TS13 TMIN Minimum Temperature -40 C IVTEMP = 0.5V
TS14 TMAX Maximum Temperature 160 C IVTEMP = 1.5V
Note 1: The temperature sensor is functional at VBORIOMIN < VDDIO < VDDIOMIN, but with degraded performance.
Unless otherwise stated, module functionality is tested, but not characterized.

FIGURE 44-21: PARALLEL SLAVE PORT TIMING
PMCSx
PS5
PMRD
PS6
PMWR
PS4 PS7
PMD<x:0>
PS1
PS3
PS2
TABLE 44-49: PARALLEL SLAVE PORT REQUIREMENTS

Para
m.No.
PS1 TdtV2wrH Data In Valid before PMWR or PMCSx 20 ns

Inactive (setup time)
PS2 TwrH2dtI PMWR or PMCSx Inactive to Data-in 40 ns
Invalid (hold time)
PS3 TrdL2dtV PMRD and PMCSx Active to Data-out 60 ns
Valid
PS4 TrdH2dtI PMRD Activeor PMCSx Inactive to 0 10 ns
Data-out Invalid
PS5 Tcs PMCSx Active Time TPBCLK2 + 40 ns
PS6 TWR PMWR Active Time TPBCLK2 + 25 ns
PS7 TRD PMRD Active Time TPBCLK2 + 25 ns

FIGURE 44-22: PARALLEL MASTER PORT READ TIMING DIAGRAM
TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2
PBCLK2
PM4
PMA<x:0> Address
PM6
PMD<x:0> Address<7:0>
Address<7:0> Data
Data
PM2
PM7
PM3
PMRD
PM5
PMWR
PM1
PMALL/PMALH
PMCSx
TABLE 44-50: PARALLEL MASTER PORT READ TIMING REQUIREMENTS

Param.
No.
PM1 TLAT PMALL/PMALH Pulse Width 1 TPBCLK2
PM2 TADSU Address Out Valid to PMALL/ 2 TPBCLK2
PMALH Invalid (address setup
time)
PM3 TADHOLD PMALL/PMALH Invalid to 1 TPBCLK2
Address Out Invalid (address
hold time)
PM4 TAHOLD PMRD Inactive to Address Out 5 ns
Invalid
(address hold time)
PM5 TRD PMRD Pulse Width 1 TPBCLK2
PM6 TDSU PMRD or PMENB Active to Data 15 ns
In Valid (data setup time)
PM7 TDHOLD PMRD or PMENB Inactive to 5 ns
Data In Invalid (data hold time)

FIGURE 44-23: PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2 TPBCLK2
PBCLK2
PMA<x:0> Address
PM2 + PM3
PMD<x:0> Address<7:0> Data
PM12
PM13
PMRD
PM11
PMWR
PM1
PMALL/PMALH
PMCSx
TABLE 44-51: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS

Param.
No.
PM11 TWR PMWR Pulse Width 1 TPBCLK2
PM12 TDVSU Data Out Valid before PMWR or 2 TPBCLK2
PMENB goes Inactive (data setup
time)
PM13 TDVHOLD PMWR or PMEMB Invalid to Data 1 TPBCLK2
Out Invalid (data hold time)

TABLE 44-52: USB OTG ELECTRICAL SPECIFICATIONS

Param.
No.
USB313 VUSB3V3 USB Voltage 3.0 3.6 V Voltage on VUSB3V3
must be in this range for
proper USB operation
Low-Speed and Full-Speed Modes
USB315 VILUSB Input Low Voltage for USB Buffer 0.8 V
USB316 VIHUSB Input High Voltage for USB Buffer 2.0 V
USB318 VDIFS Differential Input Sensitivity 0.2 V The difference between
D+ and D- must exceed
this value while VCM is
met
USB319 VCM Differential Common Mode Range 0.8 2.5 V
USB321 VOL Voltage Output Low 0.0 0.3 V 1.425 k load
connected to VUSB3V3
USB322 VOH Voltage Output High 2.8 3.6 V 14.25 k load
connected to ground
Hi-Speed Mode
USB323 VHSDI Differential input signal level 150 mV
USB324 VHSSQ SQ detection threshold 100 150 mV
USB325 VHSCM Common mode voltage range -50 500 mV
USB326 VHSOH Data signaling high 360 440 mV
USB327 VHSOL Data signaling low -10 10 mV
USB328 VCHIRPJ Chirp J level 700 1100 mV
USB329 VCHIRPK Chirp K level -900 -500 mV
USB330 ZHSDRV Driver output resistance 45

TABLE 44-53: ETHERNET MODULE SPECIFICATIONS
Param.
Characteristic Min. Typ. Max. Units Conditions
No.
MIIM Timing Requirements
ET1 MDC Duty Cycle 40 60 %
ET2 MDC Period 400 ns
ET3 MDIO Output Setup and Hold 10 10 ns See Figure 44-24
ET4 MDIO Input Setup and Hold 0 300 ns See Figure 44-25
MII Timing Requirements
ET5 TX Clock Frequency 25 MHz
ET6 TX Clock Duty Cycle 35 65 %
ET7 ETXDx, ETEN, ETXERR Output Delay 0 25 ns See Figure 44-26
ET8 RX Clock Frequency 25 MHz
ET9 RX Clock Duty Cycle 35 65 %
ET10 ERXDx, ERXDV, ERXERR Setup and Hold 10 30 ns See Figure 44-27
RMII Timing Requirements
ET11 Reference Clock Frequency 50 MHz
ET12 Reference Clock Duty Cycle 35 65 %
ET13 ETXDx, ETEN, Setup and Hold 2 16 ns
ET14 ERXDx, ERXDV, ERXERR Setup and Hold 2 16 ns
FIGURE 44-24: MDIO SOURCED BY THE PIC32 DEVICE
VIHMIN
MDC
VILMAX
VIHMIN
MDIO
VILMAX
ET3 (Hold)
(Setup) ET3
FIGURE 44-25: MDIO SOURCED BY THE PHY
VIHMIN
MDC
VILMAX
VIHMIN
MDIO
VILMAX
ET4

FIGURE 44-26: TRANSMIT SIGNAL TIMING RELATIONSHIPS AT THE MII
VIHMIN
VILMAX
TX Clock
VIHMIN
ETXD<3:0>, VILMAX
ETEN,
ETXERR
ET7
FIGURE 44-27: RECEIVE SIGNAL TIMING RELATIONSHIPS AT THE MII
VIHMIN
RX Clock VILMAX
VIHMIN
ERXD<3:0>, VILMAX
ERXDV,
ERXERR
(Setup) ET10
ET10 (Hold)

FIGURE 44-28: EBI PAGE READ TIMING
tEBI-RC tEBI-PRC tEBI-PRC tEBI-PRC
SYSCLK
tEBICO tEBICO
EBIA<x:2> ADDRESS
tEBICO tEBICO tEBICO tEBICO tEBICO
EBIA<1:0> 00 01 10 11
tEBICO tEBICO
EBICSx
tEBICO tEBICO
EBIBSx 00
tEBICO tEBICO
EBIOE
tEBIDH tEBIDH tEBIDH tEBIDH

tEBIDS tEBIDS tEBIDS tEBIDS
EBID<15:0> READ DATA READ DATA READ DATA READ DATA
FIGURE 44-29: EBI WRITE TIMING
tEBI-AS tEBI-WP tEBI-WR
SYSCLK
tEBICO tEBICO
EBIA<x:0> ADDRESS
tEBICO tEBICO
EBICSx
tEBICO tEBICO
EBIBSx BYTE SELECTS
EBIOE
tEBICO tEBICO
EBIWE
tEBIDO tEBIDO
EBID<15:0> WRITE DATA

TABLE 44-54: EBI TIMING REQUIREMENTS
Param.
No.
EB10 TEBICLK Internal EBI Clock Period 5 ns
(SYSCLK)
EB11 TEBIRC EBI Read Cycle Time 10 ns
(TRC<5:0>)
EB12 TEBIPRC EBI Page Read Cycle Time 10 ns
(TPRC<3:0>)
EB13 TEBIAS EBI Write Address Setup (TAS<1:0>) 5 ns
EB14 TEBIWP EBI Write Pulse Width 5 ns
(TWP<5:0>)
EB15 TEBIWR EBI Write Recovery Time 5 ns
(TWR<1:0>)
EB16 TEBICO EBI Output Control Signal Delay 5 ns See Note 1
EB17 TEBIDO EBI Output Data Signal Delay 5 ns See Note 1
EB18 TEBIDS EBI Input Data Setup 2.5 ns See Note 1
EB19 TEBIDH EBI Input Data Hold 1.5 ns See Note 1, 2
Note 1: Maximum pin capacitance = 10 pF.
2: Hold time from EBI Address change is 0 ns.
TABLE 44-55: GLCD CONTROLLER TIMING SPECIFICATIONS

Param.
No.
GD20 tGCLK Pixel Clock Frequency 50 MHz

TABLE 44-56: DDR2 SDRAM CONTROLLER TIMING SPECIFICATIONS

Param.
Symbol Characteristic(1) Min. Typ. Max. Units Conditions
No.
DDR10 tCK Clock Frequency 5 ns
DDR11 tDUTY Duty Cycle 48 50 52 %
DDR12 tRCD Active to Read/Write Command 20 ns
Delay Time
DDR13 tRP Precharge to Active Command 20 ns
Period
DDR14 tRC Active to Ref/Active Command 110 120 ns
Period
DDR15 tRAS Active to Precharge Command 40 70000 ns Note 1
Period
DDR16 tRFC Auto Refresh to Active/Auto Refresh 130 ns Note 2
Command Period
DDR17 tREFI Average Periodic Refresh Interval 7.8 s Note 2
DDR18 tCKE DDRCKE Minimum High and Low 6 ntCK
Pulse Width
DDR19 tRRD Active to active command period for 10 ns Note 3
1 KB page size
DDR20 tFAW Four Activate Window for 1 KB 35 ns
Page Size
DDR21 tWR Write Recovery Time 25 ns
DDR22 tWTR Internal Write to Read Command 10 ns Note 4
Delay
DDR23 tRTP Internal Read To Precharge 10 ns Note 1
Command Delay
DDR24 tXSRD Exit Self Refresh to a Read 200 ntCK
Command
DDR25 tXP Exit Precharge Power Down to Any 6 ntCK
Command
DDR26 tMRD Mode Register Set Command Cycle 4 ntCK
Time
DDR27 RL Read Latency CL ntCK
DDR28 CL CAS Latency 3 4 ntCK
DDR29 WL Write Latency RL 1 ntCK
DDR30 BL Burst Length 8 ntCK
Note 1: This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP
and tRAS(min) have been satisfied.
2: If refresh timing is violated, data corruption may occur and the data must be rewritten with valid data
before a valid READ can be executed.
3: A minimum of two clocks (2 * ntCK) is required regardless of operating frequency.
4: tWTR is at least two clocks (2 * ntCK) independent of operation frequency.

TABLE 44-57: SD HOST CONTROLLER DEFAULT MODE TIMING SPECIFICATIONS
Param.
No.
SD20 tSDCK Clock Frequency 25 MHz
SD21 tDUTY Duty Cycle 50 %
SD22 tHIGH Clock High Time 10 ns
SD23 tLOW Clock Low Time 10 ns
SD24 tRISE Clock Rise Time 10 ns
SD25 tFALL Clock Fall Time 10 ns
SD26 tSETUP Input Setup Time 5 ns
SD27 tHOLD Input Hold Time 5 ns
TABLE 44-58: SD HOST CONTROLLER HIGH-SPEED MODE TIMING SPECIFICATIONS

Param.
No.
SD30 tSDCK Clock Frequency 50 MHz
SD31 tDUTY Duty Cycle 50 %
SD32 tHIGH Clock High Time 7 ns
SD33 tLOW Clock Low Time 7 ns
SD34 tRISE Clock Rise Time 3 ns
SD35 tFALL Clock Fall Time 3 ns
SD36 tSETUP Input Setup Time 6 ns
SD37 tHOLD Input Hold Time 2 ns

FIGURE 44-30: EJTAG TIMING CHARACTERISTICS
TTCKeye
TTCKhigh TTCKlow
Trf
TCK
Trf
TMS
TDI
TTsetup TThold Trf

Trf
TDO
TTRST*low
TTDOout TTDOzstate
TRST*
Defined Undefined
Trf
TABLE 44-59: EJTAG TIMING REQUIREMENTS

Param.
Symbol Description(1) Min. Max. Units Conditions
No.
EJ1 TTCKCYC TCK Cycle Time 25 ns
EJ2 TTCKHIGH TCK High Time 10 ns
EJ3 TTCKLOW TCK Low Time 10 ns
EJ4 TTSETUP TAP Signals Setup Time Before 5 ns
Rising TCK
EJ5 TTHOLD TAP Signals Hold Time After 3 ns
Rising TCK
EJ6 TTDOOUT TDO Output Delay Time from 5 ns
Falling TCK

TABLE 44-59: EJTAG TIMING REQUIREMENTS
Param.
Symbol Description(1) Min. Max. Units Conditions
No.
EJ7 TTDOZSTATE TDO 3-State Delay Time from 5 ns
Falling TCK
EJ8 TTRSTLOW TRST Low Time 25 ns
EJ9 TRF TAP Signals Rise/Fall Time, All ns
Input and Output


45.0 AC AND DC CHARACTERISTICS GRAPHS
Note: The graphs provided are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested
or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 45-1: VOH 4x DRIVER PINS FIGURE 45-3: VOH 8x DRIVER PINS
VOH(V) VOH(V)
0.050 0.090
0.045 0.080
0.040
0.070
0.035
0.060
0.030
IOH(A)
0.050
IOH(A)
0.025
0.040
0 020
0.020

0.030
0.015
AbsoluteMaximum 0.020
0.010
AbsoluteMaximum
0.010
0.005
0.000
0.000 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
FIGURE 45-2: VOL 4x DRIVER PINS FIGURE 45-4: VOL 8x DRIVER PINS
VOL(V) VOL(V)
0.050 0.090
0.045 0.080
0.040 0.070
0.035
0.060
0.030
0.050
IOL(A)
IOL(A)
0.025
0.040
DS60001361E-page 777
0 020
0.020
0.030
0.015 AbsoluteMaximum AbsoluteMaximum
0.020
0.010
0.005 0.010
0.000 0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
DS60001361E-page 778
FIGURE 45-5: VOH 12x DRIVER PINS FIGURE 45-7: TYPICAL TEMPERATURE SENSOR VOLTAGE

VOH(V) 1.550
0.140
1.350
0.120
Voltage (V)
1.150
0.100
0.080 0.950
IOH(A)
0.060
0 750
0.750
0.040
0.550
0.020 AbsoluteMaximum
0.350
0.000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
Temperature (Celsius)
FIGURE 45-6: VOL 12x DRIVER PINS
VOL(V)
0.140
0.120
0.100
0.080
IOL(A)
0.060
0.040
AbsoluteMaximum
0.020
0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50
46.0 PACKAGING INFORMATION
46.1 Package Marking Information
169-Lead LFBGA (11x11x1.56 mm) Example
XXXXXXXXXX PIC32MZ2064
XXXXXXXXXX DAG-169I/HF
XXXXXXXXXX e3
YYWWNNN 0510017
169-Lead LFBGA (11x11 mm) Example
XXXXXXXXXX DAG-169I/6JX
XXXXXXXXXX e3
YYWWNNN 0510017
176-Lead LQFP (20x20x1.45 mm) Example
XXXXXXXXXX DAG-176I/2J
XXXXXXXXXX e3
YYWWNNN 0510017
288-Lead LFBGA (15x15x1.4 mm) Example
XXXXXXXXXX DAG-288I/4J
XXXXXXXXXX e3
YYWWNNN 0510017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week 01)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e)3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

46.2 Package Details
The following sections give the technical details of the packages.
169-Ball Low Profile Fine Pitch Ball Grid Array (HF) - 11x11x1.4 mm Body [LFBGA]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
169X
0.15 C
0.10 C
D A
(A2)
NOTE 1 B
2X
0.10 C
2X
0.10 C NOTE 1 (DATUM B) A1
A1 CORNER (DATUM A) (A3)
A
TOP VIEW
A1 CORNER C
D1 SEATING
PLANE
NOTE 1
N
SIDE VIEW
E1
166X b
BOTTOM VIEW 0.10 C A B
0.05 C
Microchip Technology Drawing C04-365B Sheet 1 of 2

169-Ball Low Profile Fine Pitch Ball Grid Array (HF) - 11x11x1.4 mm Body [LFBGA]
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals (Balls) N 169
Pitch e 0.80 BSC
Overall Height A 1.17 1.285 1.40
Terminal (Ball) Height A1 0.25 0.325 0.40
Mold Cap Thickness (A2) 0.70 REF
Substrate Thickness (A3) 0.26 REF
Overall Length D 11.00 BSC
Overall Width E 11.00 BSC
Overall Ball Pitch D1 9.60
Overall Ball Pitch E1 9.60
Ball Diameter b 0.40 0.45 0.50
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.


169-Ball Low Profile Ball Grid Array (6JX) - 11x11 mm Body [LFBGA]
169X
0.15 C
D
0.20 C
D
4 A
NOTE 1 A1
B
1 2 3 4 5 6 7 8 9 10 11 12 13
A
E
4 B
C
D
E
F
G E
H
(DATUM B) J
K
(DATUM A) L
2X M
0.10 C N
2X (A3)
0.10 C TOP VIEW
(A2)
A
D1
C
SEATING
1 2 3 4 5 6 7 8 9 10 11 12 13 PLANE
N
M SIDE VIEW
L
K
J
H
G e E1
F
E
D
C
B
A
NOTE 1 169X b
0.15 C A B
e 0.08 C
BOTTOM VIEW
Microchip Technology Drawing C04-439A Sheet 1 of 2

Units MILLIMETERS
Number of Terminals N 169
Pitch e 0.80 BSC
Overall Height A 1.33 1.445 1.56
Standoff A1 0.40 0.45 0.50
Mold Thickness A2 0.86 REF
Substrate Thickness A3 0.26 REF
Overall Terminal Spacing D1 9.60 BSC
Overall Terminal Spacing E1 9.60 BSC
Terminal Diameter b 0.40 0.45 0.50
Notes:
1. Pin A1 visual index feature may vary, but must be located within the hatched area.

1 2 3 4 5 6 7 8 9 10 11 12 13
B
C
E
D
E
F
G C2
H
J G
K
L
M
N
X
E
SILK SCREEN
C1
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Contact Pitch E 0.80 BSC
Overall Contact Pad Spacing C1 9.60
Overall Contact Pad Spacing C2 9.60
Contact Pad Width (X169) X1 0.50
Contact Pad to Contact Pad G 0.30
Notes:
Microchip Technology Drawing C04-2439A

176-Lead Low Profile Quad Flat Pack (2J) - 20x20x1.4 mm Body [LQFP]
With 7x7 mm Exposed Pad
D A SEATING PLANE
D1 C 176X
D1 0.08 C
2 B
N
NOTE 1
12
SEE DETAIL B
E1
2
E2
E
(DATUM B) E1
(DATUM A)
(L1)
4X
0.20 C
4X
1
0.20 C
D2
TOP VIEW
SIDE VIEW
D3
e
2
X
X = A OR B
E3 e
DETAIL A
SEE DETAIL A
1 2
NOTE 1
N
176X b
0.07 C A B
BOTTOM VIEW

176-Lead Low Profile Quad Flat Pack (2J) - 20x20x1.4 mm Body [LQFP]
With 7x7 mm Exposed Pad
2
R1
R2
A A2 c
SEATING
PLANE
C 3
A1
L
Units MILLIMETERS Units MILLIMETERS

Dimension Limits MIN NOM MAX Dimension Limits MIN NOM MAX
Number of Leads N 176 Lead Width b 0.13 0.16 0.23
Pitch e 0.40 BSC Lead Thickness c 0.09 - 0.20
Overall Height A - - 1.60 Lead Length L 0.45 0.60 0.75
Standoff A1 0.05 - 0.15 Footprint (L1) 1.00 REF
Molded Package Height A2 1.35 1.40 1.45 Bend Radius R1 0.08 - -
Overall Length D 22.00 BSC Bend Radius R2 0.08 - 0.20
Molded Package Length D1 20.00 BSC Foot Angle 0 3.5 7
Overall Lead Pitch D2 17.20 BSC Lead Angle 1 0 - -
Exposed Pad Length D3 6.90 7.00 7.10 Mold Draft Angle 2 11 12 13
Overall Width E 22.00 BSC Mold Draft Angle 3 11 12 13
Molded Package Width E1 20.00 BSC
Overall Lead Pitch E2 17.20 BSC
Exposed Pad Width E3 6.90 7.00 7.10
Notes:
2. Dimensions D1 and E1 do not include mold protrusion. Allowable Protrusion is 0.25mm per side.
D1 and E1 are maximum body size dimensions including mold mismatch.
3. Dimension b does not include dambar protrusion. Allowable dam bar protrusion shall not cause
the lead width to exceed the maximum b dimension by more than 0.08mm
Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion
and adjacent lead is 0.07mm for 0.40mm pitch packages.



288 Ball Low Profile Fine Pitch Ball Grid Array (4J) - 15x15x1.4 mm Body [LFBGA]
Units MILLIMETERS
Number of Terminals (Balls) N 288
Pitch e 0.80 BSC
Overall Height A - - 1.40
Terminal (Ball) Height A1 0.30 0.35 0.40
Mold Cap Height (A2) 0.70 REF
Substrate Thickness (A3) 0.26 REF
Overall Ball Pitch D1 13.60 BSC
Overall Ball Pitch E1 13.60 BSC
Ball Diameter b 0.40 0.45 0.50
Notes:



APPENDIX A: REVISION HISTORY Revision B (November 2015)
In this revision, the document status has been updated
Revision A (July 2015) from Advance Information to Preliminary.
This is the initial released version of the document. This revision includes the following major changes,
which are referenced by their respective chapter in
Table A-1.
In addition, minor updates to text and formatting were
incorporated throughout the document.
TABLE A-1: MAJOR SECTION UPDATES

Section Name Update Description
32-bit Graphics Applications The pin names for 169-pin devices were updated (see Table 5).
MCUs (up to 2 MB Live Update The pin names for 288-pin devices were updated (see Table 7).
Flash, 640 KB SRAM, and 32
MB DDR2 SDRAM) with XLP
Technology
4.0 Memory Organization The Boot Flash Sequence and Configuration Word Summary tables were updated
(see Table 4-3 and Table 4-4).
The BFxSEQ3/ABFxSEQ3: Boot Flash x Sequence Word 0 Register was
updated (see Register 4-1).
6.0 Resets The All Resets values were updated for the RCON register in the Resets Register
Map (see Table 6-1).
7.0 CPU Exceptions and The OFF199 register was added to the Interrupt Register Map (see Table 7-3).
Interrupt Controller
8.0 Oscillator Configuration The All Resets values for the OSCON and PB6DIV registers were updated in the
Oscillator Register Map (see Table 8-2).
The PLLODIV<2:0> bit values in the SPLLCON register were updated (see
Register 8-3).
10.0 Direct Memory Access The All Resets values were updated in the DMA Channel 0 through Channel 7
(DMA) Controller Register Map (see Table 10-3).
11.0 Hi-Speed USB with On- The All Resets value for bits 15:0 of the USBOTG register was updated in the USB
The-Go (OTG) Register Map 1 (see Table 11-1).
The value at POR was updated for bits 24 and 13 of the USBCRCON register (see
Register 11-30).
12.0 I/O Ports The TRISC bits in the PORTC Register Map were updated (see Table 12-5).
The ANSH3 bit was added to the ANSELH register in the PORTH Register Map
(see Table 12-10).
The RPD15R register was removed from the Peripheral Pin Select Output Register
Map (see Table 12-14).
18.0 Watchdog Timer (WDT) The All Resets value for bits 15:0 of the WDTCON register in the Watchdog Timer
Register Map was updated (see Table 18-1).
21.0 Serial Peripheral The All Resets value for bits 15:0 of the SPI1STAT and SPI1CON2 registers in the
Interface (SPI) and Inter-IC Watchdog Timer Register Map were updated (see Table 21-1).
Sound (I2S)
22.0 Serial Quad Interface The All Resets value for bits 15:0 of the SQI1XCON1 register in the Serial
(SQI) Quadrature Interface (SQI) Register Map was updated (see Table 22-1).
25.0 Parallel Master Port The All Resets value for bits 15:0 of the PMSTAT register in the Parallel Master
(PMP) Port Register Map was updated (see Table 25-1).
26.0 External Bus Interface The All Resets values were updated in the EBI Register Map (see Table 26-2).
(EBI)

TABLE A-1: MAJOR SECTION UPDATES (CONTINUED)
29.0 12-bit High-Speed The All Resets values for the ADCCON1 and ADCxTIME registers were updated
Successive Approximation and the Virtual Addresses for the ADCxCFG, ADCSYSCFGx, and ADCDATAx
Register (SAR) Analog-to- registers were updated in the ADC Register Map (see Table 29-1).
Digital Converter (ADC)
34.0 High/Low-Voltage Detect The chapter was renamed and the introduction was updated.
(HLVD) The HLVDCON register was updated (see Table 34-1 and Register 34-1).
High/Low-Voltage Detect (HLVD) Module Block Diagram was updated (see
Figure 34-1)
36.0 Graphics LCD (GLCD) The Graphics LCD Controller Register Map was updated (see Table 36-1).
Controller These registers were updated:
Register 36-2: GLCDCLKCON: Graphics LCD Controller Clock Control
Register
Register 36-4: GLCDRES: Graphics LCD Controller Resolution Register
Register 36-5: GLCDFPORCH: Graphics LCD Controller Front Porch
Register
Register 36-6: GLCDBLANKING: Graphics LCD Controller Blanking
Register
Register 36-7: GLCDBPORCH: Graphics LCD Controller Back Porch
Register
Register 36-8: GLCDCURSOR: Graphics LCD Controller Cursor Register
Register 36-10: GLCDLxstart: graphics lcd controller layer x start
register (x = 0-2)
Register 36-11: GLCDLxsize: graphics lcd controller layer x size register
(x = 0-2)
Register 36-14: GLCDLxres: graphics lcd controller layer x resolution
register (x = 0-2)
37.0 2-D Graphics The introduction was updated.
Processing Unit (GPU)
39.0 Secure Digital Host The SDHC block diagram was updated (see Figure 39-1).
Controller (SDHC) The SDHC Register Map was updated (see Table 39-1).
The bit values for the CDSLVL bit in the SDHCSTAT1 register were updated (see
Register 39-6).
The SDHCCAP register was updated (see Register 39-13).
40.0 Power-Saving Features 40.2.3 Deep Sleep Mode was updated.
References to High-Voltage Detect were removed in the PMD Register Summary
(Table 40-2) and the PMD Bits and Locations (Table 40-3).
41.0 Special Features The CFGCON2 register was updated (see Table 41-3 and Register 41-12).
44.0 Electrical The following tables were updated:
Characteristics Table 44-1: Operating MIPS vs. Voltage
Table 44-3: Thermal Packaging Characteristics
Table 44-4: DC Temperature and Voltage Specifications
Table 44-8: DC Characteristics: Operating Current (Idd)
Table 44-9: DC Characteristics: Idle Current (Iidle)
Table 44-10: DC Characteristics: Power-Down Current (Ipd)
Table 44-12: DC Characteristics: I/O Pin Output Specifications
Table 44-38: SPIx Master Mode (CKE = 0) Timing Requirements
Table 44-39: SPIx Module Master Mode (CKE = 1) Timing Requirements
Table 44-53: USB OTG Electrical Specifications

Revision C (October/November 2016)
All instances of VDD1V8 were changed to: VDDR1V8 and
VDD were changed to VDDIO throughout the data sheet.
All instances of V-Temp specifications were removed
throughout the data sheet.
This revision includes the following major changes,
Table A-2.

32-bit Graphics Applications The Operating Conditions were updated from 2.0V to 3.6V to 2.2V to 3.6V.
MCUs (up to 2 MB Live Update All Device Pin Tables were updated (see Table 5 through Table 7).
Technology
1.0 Device Overview Note 1 was added to the Timer1 through Timer9 and RTCC Pinout I/O
Descriptions (see Table 1-7).
Note 2 and the pin numbers for the Power, Ground, and Voltage Reference Pinout
I/O Descriptions were updated (see Table 1-23).
2.0 Guidelines for Getting The Recommended Minimum Connection diagram was updated (see Figure 2-1).
Started with 32-bit 2.9.1.3 EMI/EMC/EFT (IEC 61000-4-4 and IEC 61000-4-2) Suppression
Microcontrollers Considerations was added.
3.0 CPU The SB bit was updated in the Configuration Register; CP0 Register 16, Select 0
(see Register 3-1).
4.0 Memory Organization 4.3 Timing Parameters was updated.
6.0 Resets Note 1 was added to the Resets Register Map (see Table 6-1).
8.0 Oscillator Configuration The DIVSPLLRDY bit was removed from the CLKSTAT register (see Table 8-2 and
Register 8-8).
Updated bit 5-0 center frequency values from -2% to -4% and +2% to +4% (see
Register 8-2).
12.0 I/O Ports The CNCON registers in the Port Register Maps were updated (see Table 12-3
through Table 12-12).
The SIDL bit was removed from the CNCONx registers (see Register 12-3).
20.0 Real-Time Clock and A note regarding the RTCC pin was added in the key features.
Calendar (RTCC)
22.0 Serial Quad Interface Note 1 in the SQI Module Block Diagram was updated ( see Figure 22-1).
(SQI)
26.0 External Bus Interface Note 2 was added on EBI module usage with the Graphics LCD (GLCD)
(EBI) Controller.
Table 26-1: EBI Module Features was removed.
Note 1 was removed from the External Bus Interface Address Mask register (see
Register 26-2).

TABLE A-2: MAJOR SECTION UPDATES (CONTINUED)
29.0 12-bit High-Speed EQUATION 29-1: ADC Throughput Rate and notes were added.
Successive Approximation Note 1 was added to the ADC Register Map (see Table 29-1).
Register (SAR) Analog-to-
Digital Converter (ADC) A note was added to the SELRES bits in the ADCCON1 and the ADCxTIME
registers (see Register 29-1 and Register 29-27, respectively).
The AICPMPEN bit was added to the ADC Control Register 1 (see Table 29-1 and
Register 29-1).
The bit values and the note for the CHNLID bits in the ADCFLTRx register were
updated (see Register 29-16).
The bit values for the ADCID bits in the ADCFSTAT register were updated (see
Register 29-22).
The ADCCFG bit definition and the note were updated in the ADCxCFG register
(see Register 29-33).
34.0 High/Low-Voltage Detect The SIDL bit was removed from the HLVDCON register (see Table 34-1 and
(HLVD) Register 34-1).
36.0 Graphics LCD (GLCD) The bit positions of FORCEALPHA and DISABIFIL in the GLCDLxMODE register
Controller were switched (see Table 36-1 and Register 36-9).
38.0 DDR2 SDRAM The DDRPHYPADCON register was updated (see Table 38-1 and Register 38-28).
Controller The values at POR were updated in the following registers:
Register 38-18
Register 38-25
Register 38-26
Register 38-28
39.0 Secure Digital Host Note 1 in the Secure Digital Host Controller (SDHC) Block Diagram was updated
Controller (SDHC) (see Figure 39-1).
40.0 Power-Saving Features The WAKEDIS bit was removed from the Deep Sleep Control register (see
Table 40-1 and Register 40-1).
41.0 Special Features DEVSN2 and DEVSN3 were added to the Device Serial Number Summary (see
Table 41-4).
The Device ADC Calibration Summary was added (see Table 41-5).
Note 2 was added to the JTAGEN bit in the CFGCON register (see Register 41-9).
44.0 Electrical The Operating Conditions were updated from 2.0V - 3.6V to 2.2V - 3.6V for VDDIO
Characteristics and 1.7V - 1.9V for VDDCORE throughout the chapter.
The Absolute Maximum Ratings were updated.
Updated VDDIO values from 0.8*VDDIO to 0.65*VDDIO.(see Table 44-10, Table 44-
15, Table 44-22).
Updated thermal packaging characteristics (see Table 44-3).
Updated typical DC characteristics (see Table 44-7).
Updated Updated SD Host Controller timing specs - min. standard operating
conditions (see Table 44-58 and Table 44-59).
All tables were updated.
46.0 Packaging Information Updated packaging dimensions (see 46.1 Package Marking Information).
Added information for 6JX packaging (see 46.1 Package Marking Information
and 46.2 Package Details).
Product Identification System The package marking for V-Temp devices was changed to V.

Revision D (March 2017)
Table A-3.

32-bit Graphics Applications Table 5, updated pin B4 to VDDCORE and B6 to VDDIO.
MCUs (up to 2 MB Live Update
Technology
4.0 Memory Organization Figure 4-1, updated KSEG3 from cacheable to not cacheable
6.0 Resets Updated Figure 6-1.
8.0 Oscillator Configuration Table 8-1, added SYSCLK to peripheral EBI.
26.0 External Bus Interface Figure 26-1, changed PBCLK8 to SYSCLK.
(EBI)
29.0 12-bit High-Speed Register 29-1, bit 12, updated notes and added table.
Successive Approximation
Register (SAR) Analog-to-
Digital Converter (ADC)
38.0 DDR2 SDRAM Table 38-1, swapped register names DRVSTRPFET and DRVSTRNFET.
Controller Table 38-1, added offset address 9140.
Register 38-28, swapped register names and definitions DRVSTRPFET and
DRVSTRNFET.
Added Register 38-30,
40.0 Power-Saving Features Register 40-1, updated command to instruction..Updated 40.2.4 VBAT Mode
41.0 Special Features Register 41-5, updated command to instruction..
Register 41-9, bit 7, updated notes and added table.
44.0 Electrical Updated 44.1 DC Characteristics
Characteristics Updated Table 44-4 and Table 44-5.
Table 44-18, Added parameter D306.
Table 44-56, updated values for parameters DDR10, DDR19, DDR22, and
DDR23.

Revision E (May 2017)
Table A-4.

32-bit Graphics Applications Table 6, updated the value of pin 168 from CVREFOUT/AN5/RPB10/RB10 to
MCUs (up to 2 MB Live Update AN5/RPB10/RB10
Technology
25.0 Parallel Master Port Table 25-1, updated Virtual Address column heading from BF80 to BF82. Updated
(PMP) virtual addresses from 70xx to E0xx.
36.0 Graphics LCD (GLCD) Updated resolutions in Key features list.
Controller
39.0 Secure Digital Host Added eMMC Standard: JESD84-A441 to features list.
Controller (SDHC)
44.0 Electrical Table 44-7, Table 44-8, Table 44-9, Table 44-10, Table 44-11, Table 44-16,
Characteristics Table 44-18 updated various DC Characteristics parameters.
Table 44-27, Table 44-28, Table 44-29 updated various AC Characteristics
parameters.
Appendix A: Revision Revision C intro - corrected initial occurrence of VDDR1V8 TO VDD1V8.
History

INDEX
A Configuring Analog Port Pins............................................ 252
Controller Area Network (CAN) ........................................ 483
AC Characteristics ............................................................ 735
ADC Specifications ................................................... 761 CP0 Register 16, Select 1) ................................................. 52
Analog-to-Digital Conversion Requirements............. 762 CP0 Register 16, Select 2) ................................................. 54
CP0 Register 16, Select 3) ................................................. 53
DDR2 SDRAM Timing Requirements ....................... 738
EBI Timing Requirements ................. 729, 734, 772, 774 CPU
EJTAG Timing Requirements ................................... 775 Architecture Overview ................................................ 47
Coprocessor 0 Registers ............................................ 48
Ethernet .................................................................... 769
Internal BFRC Accuracy ........................................... 739 Core Exception Types .............................................. 124
Internal FRC Accuracy.............................................. 739 EJTAG Debug Support............................................... 50
Power Management ................................................... 50
Internal RC Accuracy ................................................ 739
OTG Electrical Specifications ................................... 768 CPU Module ................................................................. 39, 45
Parallel Master Port Read Requirements ................. 766 Crypto
Buffer Descriptors..................................................... 410
Parallel Master Port Write ......................................... 767
Parallel Master Port Write Requirements.................. 767 Format of SA_CTRL ................................................. 418
Parallel Slave Port Requirements ............................. 765 Security Association Structure.................................. 415
Crypto Engine ........................................................... 399, 605
PLL Clock Timing...................................................... 737
Assembler Customer Change Notification Service............................. 805
MPASM Assembler................................................... 714 Customer Notification Service .......................................... 805
Customer Support............................................................. 805
B
D
Block Diagrams
DC Characteristics............................................................ 718
Comparator I/O Operating Modes............................. 565
I/O Pin Input Specifications .............................. 724, 728
Comparator Voltage Reference ................................ 569
I/O Pin Output Specifications.................................... 725
CPU ............................................................................ 46
Idle Current (IIDLE) .................................................... 722
Crypto Engine ........................................... 399, 603, 605
Power-Down Current (IPD)........................................ 723
CTMU Configurations
Program Memory...................................................... 730
Time Measurement ........................................... 577
Temperature and Voltage Specifications.................. 719
DMA .......................................................................... 177
Development Support ....................................................... 713
Ethernet Controller.................................................... 521
Direct Memory Access (DMA) Controller.......................... 177
Graphics LCD (GLCD) Controller ............................. 584
High/Low-Voltage Detect (HLVD) ............................. 573 E
Input Capture ............................................................ 289
Electrical Characteristics .................................................. 717
Inter-Integrated Circuit (I2C) ..................................... 362
AC............................................................................. 735
Interrupt Controller .................................................... 123
High/Low-Voltage Detect.......................................... 720
JTAG Programming, Debugging and Trace Ports .... 710
Errata .................................................................................. 15
Output Compare Module........................................... 293
Ethernet Controller............................................................ 521
PIC32 CAN Module................................................... 483
ETHPMM0 (Ethernet Controller Pattern Match Mask 0)... 531
PMP Pinout and Connections to External Devices ... 377
ETHPMM1 (Ethernet Controller Pattern Match Mask 1)... 531
Prefetch Module........................................................ 173
External Bus Interface (EBI) ............................................. 391
Prefetch Module Block Diagram ............................... 173
External Clock
Random Number Generator (RNG) .......................... 421
Timer1 Timing Requirements ................................... 744
Reset System............................................................ 115
Timer2, 3, 4, 5 Timing Requirements ....................... 745
RTCC ........................................................................ 313
Timing Requirements ............................................... 736
Serial Quad Interface (SQI) ...................................... 333
SPI Module ............................................................... 323 F
Timer1....................................................................... 279
Flash Program Memory ............................................ 105, 115
Timer2/3/4/5 (16-Bit) ................................................. 283 RTSP Operation ....................................................... 105
Typical Multiplexed Port Structure ............................ 251
UART ........................................................................ 369 G
WDT and Power-up Timer ................................ 307, 311 Graphics LCD (GLCD) Controller ..................................... 583
Brown-out Reset (BOR)
and On-Chip Voltage Regulator................................ 710 H
High-Voltage Detect (HVD)............................................... 117
C
Hi-Speed USB On-The-Go (OTG) .................................... 201
C Compilers
MPLAB C18 .............................................................. 714 I
Charge Time Measurement Unit. See CTMU. I/O Ports ........................................................................... 251
Comparator Parallel I/O (PIO) ...................................................... 252
Specifications............................................ 729, 732, 733 Write/Read Timing.................................................... 252
Comparator Module .......................................................... 565 Input Change Notification ................................................. 252
Comparator Voltage Reference (CVref ............................. 569 Instruction Set................................................................... 711
Configuration Bit ............................................................... 683 Inter-Integrated Circuit (I2C) ............................................. 361

Internet Address................................................................ 805 System Bus Target 0 .................................................. 72
Interrupt Controller System Bus Target 1 ...................................... 89, 90, 91
IRG, Vector and Bit Location .................................... 126 System Bus Target 10 ................................................ 85
System Bus Target 11 ................................................ 86
M System Bus Target 12 ................................................ 87
Memory Maps System Bus Target 13 ................................................ 88
Devices with 2048 KB Program Memory .................... 56 System Bus Target 2 .................................................. 75
Memory Organization.......................................................... 55 System Bus Target 3 .................................................. 76
Layout ......................................................................... 55 System Bus Target 4 .................................................. 77
Microchip Internet Web Site .............................................. 805 System Bus Target 5 .................................................. 79
MPLAB ASM30 Assembler, Linker, Librarian ................... 714 System Bus Target 6 .................................................. 81
MPLAB Integrated Development Environment Software .. 713 System Bus Target 7 .................................................. 82
MPLAB PM3 Device Programmer..................................... 715 System Bus Target 8 .................................................. 83
MPLAB REAL ICE In-Circuit Emulator System ................. 715 System Bus Target 9 .................................................. 84
MPLINK Object Linker/MPLIB Object Librarian ................ 714 System Control ......................................................... 116
Timer1-Timer9 .................................................. 280, 285
O UART1-5................................................................... 370
Oscillator Configuration..................................................... 157 USB .................................................................. 203, 209
Output Compare................................................................ 293 Registers
[pin name]R (Peripheral Pin Select Input) ................ 277
P
AD1CON1 (A/D Control 1)........................................ 322
Packaging ......................................................................... 785 AD1CON1 (ADC Control 1) ...................................... 322
Details ....................................................................... 786 ADCANCON (ADC Analog Warm-up Control Register) .
Marking ..................................................................... 785 479
Parallel Master Port (PMP) ............................................... 377 ADCBASE (ADC Base) ............................................ 472
Pinout I/O Descriptions (table) . 18, 19, 20, 21, 24, 25, 26, 27, ADCCMP1CON (ADC Digital Comparator 1 Control
28, 29, 30, 31, 32, 33, 34, 36, 38 Register) ........................................................... 466
Power-on Reset (POR) ADCCMPENx (ADC Digital Comparator x Enable Reg-
and On-Chip Voltage Regulator ................................ 710 ister (x = 1 through 6))..................................... 459
Power-Saving Features..................................................... 669 ADCCMPx (ADC Digital Comparator x Limit Value Reg-
with CPU Running..................................................... 669 ister (x = 1 through 6))..................................... 460
Prefetch Module ................................................................ 173 ADCCMPxCON (ADC Digital Comparator x Control
R Register (x = 1 through 6)) .............................. 468
ADCCON1 (ADC Control Register 1) ....................... 437
Random Number Generator (RNG) .................................. 421
Real-Time Clock and Calendar (RTCC)............................ 313
Register
ADCCSS1 (ADC Common Scan Select Register 1). 456
GLCDLxBADDR (Graphics LCD Controller Layer x
ADCCSS2 (ADC Common Scan Select Register 2). 457
Base Address) .................................................. 596
ADCDATAx (ADC Output Data Register (x = 0 through
Register Map
44)) ................................................................... 473
Comparator ............................................................... 566
ADCDSTAT1 (ADC Data Ready Status Register 1). 458
Comparator Voltage Reference ........................ 570, 574
ADCDSTAT2 (ADC Data Ready Status Register 2). 458
Device ADC Calibration Summary ............................ 687
ADCEIEN1 (ADC Early Interrupt Enable Register 1) 476
Device Configuration Word Summary............... 684, 685
ADCEIEN2 (ADC Early Interrupt Enable Register 2) 476
Device Serial Number Summary............................... 686
ADCEISTAT2 (ADC Early Interrupt Status Register 2) ..
DMA Channel 0-3 ..................................................... 179
478
DMA CRC ................................................................. 178
ADCFLTRx (ADC Digital Filter x Register (x = 1
DMA Global............................................................... 178
through 6)) ........................................................ 461
EBI ............................................................................ 392
ADCGIRQEN1 (ADC Interrupt Enable Register 1) ... 455
Flash Controller......................................... 106, 300, 308
ADCIMCON1 (ADC Input Mode Control Register 1) 447
I2C1 Through I2C5 ................................................... 363
Input Capture 1-9 ...................................................... 291
Interrupt..................................................................... 134
ADCIRQEN2 (ADC Interrupt Enable Register 2)...... 455
Oscillator Configuration............................................. 161
ADCSYSCFG1 (ADC System Configuration Register 1)
Output Compare1-9 .................................................. 295
482
Parallel Master Port .................................................. 378
ADCSYSCFG2 (ADC System Configuration Register 2)
Peripheral Pin Select Input ....................................... 270
482
Peripheral Pin Select Output..................................... 274
ADCTRG1 (ADC Trigger Source 1 Register) ........... 463
PORTA...................................................................... 260
PORTB...................................................................... 261
PORTH ..................................................................... 267
ADCTRGMODE (ADC Triggering Mode for Dedicated
PORTK.............................................................. 268, 269
ADC)................................................................. 445
Prefetch..................................................................... 174
ADCTRGSNS (ADC Trigger Level/Edge Sensitivity) 474
RTCC ........................................................................ 314
ADCxCFG (ADCx Configuration Register x (x = 1
SPI1 through SPI6 .................................................... 324
through 6)) ........................................................ 481
System Bus ................................................................. 71

ADCxTIME (Dedicated ADCx Timing Register x (x = 0 EMAC1CFG2 (Ethernet Controller MAC Configuration 2)
through 4)) ........................................................ 475 549
ALRMDATE (Alarm Date Value) ............................... 322 EMAC1CLRT (Ethernet Controller MAC Collision Win-
ALRMDATECLR (ALRMDATE Clear)....................... 322 dow/Retry Limit)................................................ 553
ALRMDATESET (ALRMDATE Set) .......................... 322 EMAC1IPGR (Ethernet Controller MAC Non-Back-to-
ALRMTIME (Alarm Time Value) ............................... 321 Back Interpacket Gap)...................................... 552
ALRMTIMECLR (ALRMTIME Clear)......................... 322 EMAC1IPGT (Ethernet Controller MAC Back-to-Back In-
ALRMTIMEINV (ALRMTIME Invert) ......................... 322 terpacket Gap).................................................. 551
ALRMTIMESET (ALRMTIME Set) ............................ 322 EMAC1MADR (Ethernet Controller MAC MII Manage-
CFGCON (Configuration Control Register)............... 700 ment Address) .................................................. 559
CFGCON2 (Configuration Control Register 2).......... 706 EMAC1MAXF (Ethernet Controller MAC Maximum
CFGMPLL (Memory PLL Configuration)................... 707 Frame Length) .................................................. 554
CHECON (Cache Control) ........................................ 176 EMAC1MCFG (Ethernet Controller MAC MII Manage-
CM1CON (Comparator 1 Control) ............................ 567 ment Configuration) .......................................... 557
CMSTAT (Comparator Control Register).................. 568 EMAC1MCMD (Ethernet Controller MAC MII Manage-
CNCONx (Change Notice Control for PORTx) ......... 278 ment Command)............................................... 558
CONFIG (CP0 Register 16, Select 0) ......................... 51 EMAC1MIND (Ethernet Controller MAC MII Manage-
CONFIG1 (CONFIG1 Register ................................... 52 ment Indicators)................................................ 561
CONFIG2 EMAC1MRDD (Ethernet Controller MAC MII Manage-
(CONFIG2 Register ............................................ 54 ment Read Data) .............................................. 560
CONFIG2 (CONFIG2 Register ................................... 54 EMAC1MWTD (Ethernet Controller MAC MII Manage-
CONFIG3 (CONFIG3 Register ................................... 53 ment Write Data) .............................................. 560
CTMUCON (CTMU Control) ..................................... 579 EMAC1SA0 (Ethernet Controller MAC Station Address
CVRCON (Comparator Voltage Reference Control). 571 0) ...................................................................... 562
DCHxCON (DMA Channel x Control) ....................... 190 EMAC1SA1 (Ethernet Controller MAC Station Address
DCHxCPTR (DMA Channel x Cell Pointer) .............. 198 1) ...................................................................... 563
DCHxCSIZ (DMA Channel x Cell-Size) .................... 198 EMAC1SA2 (Ethernet Controller MAC Station Address
DCHxDAT (DMA Channel x Pattern Data) ............... 199 2) ...................................................................... 564
DCHxDPTR (Channel x Destination Pointer)............ 197 EMAC1SUPP (Ethernet Controller MAC PHY Support).
DCHxDSA (DMA Channel x Destination 555
Start Address) ................................................... 195 EMAC1TEST (Ethernet Controller MAC Test) ......... 556
DCHxDSIZ (DMA Channel x Destination Size)......... 196 ETHALGNERR (Ethernet Controller Alignment Errors
DCHxECON (DMA Channel x Event Control)........... 192 Statistics) .......................................................... 547
DCHxINT (DMA Channel x Interrupt Control) ........... 193 ETHCON1 (Ethernet Controller Control 1) ............... 526
DCHxSPTR (DMA Channel x Source Pointer) ......... 197 ETHCON2 (Ethernet Controller Control 2) ............... 528
DCHxSSA (DMA Channel x Source Start Address) . 195 ETHFCSERR (Ethernet Controller Frame Check Se-
DCHxSSIZ (DMA Channel x Source Size) ............... 196 quence Error Statistics) .................................... 546
DCRCCON (DMA CRC Control) ............................... 187 ETHFRMRXOK (Ethernet Controller Frames Received
DCRCDATA (DMA CRC Data) ................................. 189 OK Statistics).................................................... 545
DCRCXOR (DMA CRCXOR Enable)........................ 189 ETHFRMTXOK (Ethernet Controller Frames Transmit-
Description ........................................................ 644, 661 ted OK Statistics).............................................. 542
DEVCFG0/ADEVCFG0 (Device Configuration Word 0) . ETHHT0 (Ethernet Controller Hash Table 0)............ 530
689 ETHHT1 (Ethernet Controller Hash Table 1)............ 530
DEVCFG1 (Device Configuration Word 1................. 691 ETHIEN (Ethernet Controller Interrupt Enable) ........ 536
DEVCFG2 (Device Configuration Word 2................. 694 ETHIRQ (Ethernet Controller Interrupt Request)...... 537
DEVCFG3 (Device Configuration Word 3......... 697, 698 ETHMCOLFRM (Ethernet Controller Multiple Collision
DEVID (Device and Revision ID) ................ 62, 688, 709 Frames Statistics)............................................. 544
DMAADDR (DMA Address) ...................................... 186 ETHPM0 (Ethernet Controller Pattern Match Offset) 532
DMAADDR (DMR Address) ...................................... 186 ETHPMCS (Ethernet Controller Pattern Match Check-
DMACON (DMA Controller Control) ......................... 185 sum) ................................................................. 532
DMASTAT (DMA Status) .......................................... 186 ETHRXFC (Ethernet Controller Receive Filter Configura-
DMSTAT (Deadman Timer Status) ........................... 303 tion) .................................................................. 533
DMTCLR (Deadman Timer Clear) ............................ 302 ETHRXOVFLOW (Ethernet Controller Receive Overflow
DMTCNT (Deadman Timer Count) ........................... 304 Statistics) .......................................................... 541
DMTCON (Deadman Timer Control) ........................ 301 ETHRXST (Ethernet Controller RX Packet Descriptor
DMTPRECLR (Deadman Timer Preclear) ................ 301 Start Address)................................................... 529
EBICSx (External Bus Interface Chip Select) .. 393, 396, ETHRXWM (Ethernet Controller Receive Watermarks) .
702, 703 535
EBIMSKx (External Bus Interface Address Mask) .... 394 ETHSCOLFRM (Ethernet Controller Single Collision
EBISMCON (External Bus Interface Static Memory Con- Frames Statistics)............................................. 543
trol).................................................................... 397 ETHSTAT (Ethernet Controller Status) .................... 539
EBISMTx (External Bus Interface Static Memory Timing) ETHTXST (Ethernet Controller TX Packet Descriptor
395 Start Address)................................................... 529
EMAC1CFG1 (Ethernet Controller MAC Configuration 1) GLCDBGCOLOR (Graphics LCD Controller Background
548 Color)................................................................ 590

GLCDBLANKING (Graphics LCD Controller Blanking)... RTCTIME (RTC Time Value).................................... 319
591 SBFLAG (System Bus Status Flag).......... 93, 94, 95, 96
GLCDBPORCH (Graphics LCD Controller Back Porch). SBTxECLRM (System Bus Target x Multiple Error Clear
592 100
GLCDCLKCON (Graphics LCD Controller Clock Control) SBTxECLRS (System Bus Target x Single Error Single)
589 100
GLCDCURSOR (Graphics LCD Controller Cursor) .. 592 SBTxECON (System Bus Target x Error Control)..... 99
GLCDFPORCH (Graphics LCD Controller Front Porch). SBTxELOG1 (System Bus Target x Error Log 1)...... 97
591 SBTxELOG2 (System Bus Target x Error Log 2)...... 99
GLCDINT (Graphics LCD Controller Cursor Data) ... 601 SBTxRDy (System Bus Target x Region y Read Per-
GLCDINT (Graphics LCD Controller Cursor LUT) .... 602 missions) .......................................................... 102
GLCDINT (Graphics LCD Controller Interrupt) ......... 598 SBTxREGy (System Bus Target x Region y) ........ 101
GLCDLxMODE (Graphics LCD Controller Layer x SBTxWRy (System Bus Target x Region y Write Per-
Mode)................................................................ 593 missions) .......................................................... 103
GLCDLxRES (Graphics LCD Controller Layer x Resolu- SPIxCON (SPI Control) ............................................ 326
tion .................................................................... 597 SPIxCON2 (SPI Control 2) ....................................... 329
GLCDLxSIZE (Graphics LCD Controller Layer x Size) . SPIxSTAT (SPI Status)............................................. 330
595 SPLLCON (System PLL Control).............................. 166
GLCDLxSTART (Graphics LCD Controller Layer x SQI1XCON1 (SQI XIP Control 1) ............................. 336
Start) ................................................................. 595 SQI1XCON2 (SQI XIP Control Register 2)............... 338
GLCDLxSTRIDE (Graphics LCD Controller Layer x T1CON (Type A Timer Control) ................................ 281
Stride) ....................................................... 596, 600 TxCON (Type B Timer Control) ................................ 287
GLCDRES (Graphics LCD Controller Resolution) .... 590 U1STAT (USB Status) ..... 610, 611, 612, 613, 614, 615,
GLCDSTAT (Graphics LCD Controller Status) ......... 599 616, 617, 618, 619, 620, 621, 622, 623, 624, 625,
GLDCMODE (Graphics LCD Controller Mode)......... 587 626, 627, 628, 629, 630, 631, 632, 635, 636, 637,
I2CxCON (I2C Control) ............................................. 365 639
I2CxSTAT (I2C Status) ............................................. 367 USBCRCON (USB Clock/Reset Control) ................. 249
ICxCON (Input Capture x Control) ............................ 292 USBCSR0 (USB Control Status 0) ........................... 210
IFSx (Interrupt Flag Status)....................................... 153 USBCSR1 (USB Control Status 1) ........................... 212
INTCON (Interrupt Control) ....................................... 149 USBCSR2 (USB Control Status 2) ........................... 213
INTSTAT (Interrupt Status) ....................................... 152 USBCSR3 (USB Control Status 3) ........................... 215
IPCx (Interrupt Priority Control)................................. 154 USBDMAINT (USB DMA Interrupt) .......................... 240
IPTMR Interrupt Proximity Timer) ............................. 152 USBDMAxA (USB DMA Channel x Memory Address) .
NVMADDR (Flash Address) ..................................... 109 242
NVMBWP (Flash Boot (Page) Write-protect) ............ 112 USBDMAxC (USB DMA Channel x Control)........... 241
NVMCON (Programming Control Register) .............. 107 USBDMAxN (USB DMA Channel x Count)............. 242
NVMCON2 (Programming Control Register 2) ......... 114 USBDPBFD (USB Double Packet Buffer Disable) ... 243
NVMDATA (Flash Data)............................................ 110 USBEOFRST (USB End-of-Frame/Soft Reset Control) .
NVMKEY (Programming Unlock) .............................. 109 237
NVMPWP (Program Flash Write-Protect) ................. 111 USBExRPC (USB Endpoint x Request Packet Count
NVMSRCADDR (Source Data Address)................... 110 (Host Mode Only)) ............................................ 243
OCxCON (Output Compare x Control) ..................... 297 USBExRXA (USB Endpoint x Receive Address) .... 239
OSCCON (Oscillator Control) ................................... 163 USBExTXA (USB Endpoint x Transmit Address).... 238
OSCTUN (FRC Tuning) ............................................ 165 USBFIFOA (USB FIFO Address).............................. 234
PMADDR (Parallel Port Address) ............................. 383 USBHWVER (USB Hardware Version) .................... 235
PMAEN (Parallel Port Pin Enable) ............................ 386 USBIE0CSR0 (USB Indexed Endpoint Control Status 0
PMCON (Parallel Port Control) ................................. 379 (Endpoint 0))..................................................... 217
PMDIN (Parallel Port Input Data) ...................... 385, 390 USBIE0CSR2 (USB Indexed Endpoint Control Status 2
PMDOUT (Parallel Port Output Data) ....................... 384 (Endpoint 0))..................................................... 219
PMMODE (Parallel Port Mode) ................................. 381 USBIE0CSR3 (USB Indexed Endpoint Control Status 3
PMRADDR (Parallel Port Read Address) ................. 389 (Endpoint 0))..................................................... 220
PMSTAT (Parallel Port Status (Slave Modes Only) .. 387 USBIENCSR0 (USB Indexed Endpoint Control Status 0
PMWADDR (Parallel Port Write Address)................. 388 (Endpoint 1-7)).................................................. 221
PRECON (Prefetch Module Control) ........................ 175 USBIENCSR1 (USB Indexed Endpoint Control Status 1
PRISS (Priority Shadow Select)................................ 150 (Endpoint 1-7)).................................................. 224
PSCNT (Post Status Configure DMT Count Status) . 304 USBIENCSR2 (USB Indexed Endpoint Control Status 2
PSINTV (Post Status Configure DMT Interval Status) .... (Endpoint 1-7)).................................................. 227
305 USBIENCSR3 (USB Indexed Endpoint Control Status 3
REFOxCON (Reference Oscillator Control (x = 1-4)).... (Endpoint 1-7)).................................................. 228
168 USBINFO (USB Information) .................................... 236
REFOxTRIM (Reference Oscillator Trim (x = 1-4)) . 169 USBLPMR1 (USB Link Power Management Control 1) .
RPnR (Peripheral Pin Select Output)........................ 277 245
RSWRST (Software Reset) ...................... 119, 120, 122 USBLPMR2 (USB Link Power Management Control 2) .
RTCCON (RTCC Control)......................................... 315 247
RTCDATE (RTC Date Value) ................................... 320 USBTMCON1 (USB Timing Control 1) ..................... 244

USBTMCON2 (USB Timing Control 2) ..................... 244 SPIx Slave Mode (CKE = 0) ..................................... 751
WDTCON (Watchdog Timer Control) ............... 309, 675 SPIx Slave Mode (CKE = 1) ..................................... 752
Revision History ................................................................ 779 Timer1, 2, 3, 4, 5 External Clock .............................. 744
RTCALRM (RTC ALARM Control) .................................... 317 UART Reception....................................................... 376
UART Transmission (8-bit or 9-bit Data) .................. 376
S Timing Requirements
Serial Peripheral Interface (SPI) ....................................... 323 CLKO and I/O ........................................................... 740
Serial Quad Interface (SQI) .............................................. 333 Timing Specifications
Software Simulator (MPLAB SIM)..................................... 715 CAN I/O Requirements............................................. 760
Special Features ............................................................... 683 I2Cx Bus Data Requirements (Master Mode)........... 756
I2Cx Bus Data Requirements (Slave Mode)............. 758
T Input Capture Requirements .................................... 745
Timer1 Module .................................................................. 279 Output Compare Requirements................................ 746
Timer2/3, Timer4/5, Timer6/7, and Timer8/9 Modules...... 283 Simple OCx/PWM Mode Requirements ................... 746
Timing Diagrams SPIx Master Mode (CKE = 0) Requirements............ 748
CAN I/O..................................................................... 760 SPIx Master Mode (CKE = 1) Requirements............ 750
EJTAG ...................................................................... 775 SPIx Slave Mode (CKE = 1) Requirements.............. 753
External Clock........................................................... 736 SPIx Slave Mode Requirements (CKE = 0).............. 751
I/O Characteristics .................................................... 740
I2Cx Bus Data (Master Mode) .................................. 756 U
I2Cx Bus Data (Slave Mode) .................................... 758 UART ................................................................................ 369
I2Cx Bus Start/Stop Bits (Master Mode) ................... 756 USB Interface Diagram..................................................... 202
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 758
Input Capture (CAPx)................................................ 745 V
OCx/PWM ................................................................. 746 Voltage Regulator (On-Chip) ............................................ 710
Output Compare (OCx)............................................. 746
Parallel Master Port Read......................................... 766 W
Parallel Master Port Write ......................................... 767 Watchdog Timer and Power-up Timer SFR Summary ..... 672
Parallel Slave Port .................................................... 765 WWW Address ................................................................. 805
SPIx Master Mode (CKE = 0) ................................... 747 WWW, On-Line Support ..................................................... 15
SPIx Master Mode (CKE = 1) ................................... 749

NOTES:

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www.microchip.com. This web site is used as a means through several channels:
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC32 MZ XX XX DA A XXX T - I / BG - XXX Example:

PIC32MZ0512DAA176-I/2J:
Microchip Brand Graphics MCU Family, PIC32,
Architecture MIPS32 microAptiv MPU core,
512 KB program memory,
Flash Memory Size 176-pin, Industrial temperature,
LQFP package.
RAM Size
Family
Key Feature Set
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Flash Memory Family
Architecture MZ = MIPS32 microAptiv MPU Core
Flash Memory Size 10 = 1024 KB

20 = 2048 KB
RAM Size 25 = 256 KB

64 = 640 KB
Family DA = Graphics MCU Family
Key Feature A = PIC32 DA Family Features, no Crypto, no DDR memory

B = PIC32 DA Family Features, with Crypto, no DDR memory
G = PIC32 DA Family Features, no Crypto, with DDR memory
H = PIC32 DA Family Features, with Crypto, with DDR memory
Pin Count 169 = 169-pin

176 = 176-pin
288 = 288-pin
Temperature Range I = -40C to +85C (Industrial)
Package HF = 169-Lead (11x11x1.4 mm) LFBGA (Low Profile Fine Pitch Ball Grid Array)
6J = 169-Lead (11x11x1.56 mm) LFBGA (Low Profile Fine Pitch Ball Grid Array)
2J = 176-Lead (22x22x1.4 mm) LQFP (Low Profile Quad Flat Pack)
4J = 288-Lead (15x15x1.4 mm) LFBGA (Low Profile Fine Pitch Ball Grid Array)
Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)

ES = Engineering Sample

Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
ensure that your application meets with your specifications. CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
MICROCHIP MAKES NO REPRESENTATIONS OR KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries.
arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company,
devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
the buyers risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A.
suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
intellectual property rights unless otherwise stated. CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
Microchip received ISO/TS-16949:2009 certification for its worldwide the U.S.A.
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California Silicon Storage Technology is a registered trademark of Microchip
and India. The Companys quality system processes and procedures Technology Inc. in other countries.
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and GestIC is a registered trademark of Microchip Technology
analog products. In addition, Microchips quality system for the design Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
and manufacture of development systems is ISO 9001:2000 certified.
Inc., in other countries.
All other trademarks mentioned herein are property of their
QUALITY MANAGEMENT SYSTEM respective companies.

2015-2017, Microchip Technology Incorporated, All Rights
CERTIFIED BY DNV Reserved.
ISBN:978-1-5224-1745-3
== ISO/TS 16949 ==

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PIC32MZ Graphics (DA) Family

32-bit Graphics Applications MCUs (up to 2 MB Live Update Flash,

Operating Conditions Advanced Analog Features

2015-2017 Microchip Technology Inc. DS60001361E-page 1

USB 2.0 HS OTG

160 47 9/9/9 6 6 2 5 45 2 Y Y 5 Y Y Y Y Y Y Y Y 120 Y Y

TABLE 2: 169-PIN LFBGA PIC32MZ DA TABLE 3: 176-PIN LQFP PIC32MZ DA

Program Memory (KB

Data Memory (KB

PIC32MZ1025DAA169 N 8/24 PIC32MZ1025DAA176 N 8/24

TABLE 4: 288-PIN LFBGA PIC32MZ DA

Data Memory (KB)

DS60001361E-page 2 2015-2017 Microchip Technology Inc.

2015-2017 Microchip Technology Inc. DS60001361E-page 3

DS60001361E-page 4 2015-2017 Microchip Technology Inc.

2015-2017 Microchip Technology Inc. DS60001361E-page 5

176-PIN LQFP (TOP VIEW)

Pin Full Pin Name Pin Full Pin Name

DS60001361E-page 6 2015-2017 Microchip Technology Inc.

176-PIN LQFP (TOP VIEW)

Pin Full Pin Name Pin Full Pin Name

2015-2017 Microchip Technology Inc. DS60001361E-page 7

176-PIN LQFP (TOP VIEW)

Pin Full Pin Name Pin Full Pin Name

DS60001361E-page 8 2015-2017 Microchip Technology Inc.

2015-2017 Microchip Technology Inc. DS60001361E-page 9

DS60001361E-page 10 2015-2017 Microchip Technology Inc.

2015-2017 Microchip Technology Inc. DS60001361E-page 11

DS60001361E-page 12 2015-2017 Microchip Technology Inc.

2015-2017 Microchip Technology Inc. DS60001361E-page 13

DS60001361E-page 14 2015-2017 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

2015-2017 Microchip Technology Inc. DS60001361E-page 15

Section 1. Introduction (DS60001127)

DS60001361E-page 16 2015-2017 Microchip Technology Inc.

FIGURE 1-1: PIC32MZ DA FAMILY BLOCK DIAGRAM

microAptiv Core PORTK

2015-2017 Microchip Technology Inc. DS60001361E-page 17

TABLE 1-1: ADC PINOUT I/O DESCRIPTIONS

DS60001361E-page 18 2015-2017 Microchip Technology Inc.

TABLE 1-2: OSCILLATOR PINOUT I/O DESCRIPTIONS

TABLE 1-3: IC1 THROUGH IC9 PINOUT I/O DESCRIPTIONS

2015-2017 Microchip Technology Inc. DS60001361E-page 19

TABLE 1-4: OC1 THROUGH OC9 PINOUT I/O DESCRIPTIONS

TABLE 1-5: EXTERNAL INTERRUPTS PINOUT I/O DESCRIPTIONS

DS60001361E-page 20 2015-2017 Microchip Technology Inc.

TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS

2015-2017 Microchip Technology Inc. DS60001361E-page 21

DS60001361E-page 22 2015-2017 Microchip Technology Inc.

2015-2017 Microchip Technology Inc. DS60001361E-page 23

DS60001361E-page 24 2015-2017 Microchip Technology Inc.

TABLE 1-8: UART1 THROUGH UART6 PINOUT I/O DESCRIPTIONS

2015-2017 Microchip Technology Inc. DS60001361E-page 25

TABLE 1-9: SPI1 THROUGH SPI 6 PINOUT I/O DESCRIPTIONS

DS60001361E-page 26 2015-2017 Microchip Technology Inc.

TABLE 1-10: I2C1 THROUGH I2C5 PINOUT I/O DESCRIPTIONS

TABLE 1-11: COMPARATOR 1, COMPARATOR 2 AND CVREF PINOUT I/O DESCRIPTIONS

2015-2017 Microchip Technology Inc. DS60001361E-page 27