Ds PIC33 EP

dsPIC33EPXXXGS70X/80X FAMILY
16-Bit Digital Signal Controllers for Digital Power Applications with

Interconnected High-Speed PWM, ADC, PGA and Comparators
Operating Conditions Advanced Analog Features

• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS • High-Speed ADC module:
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS - 12-bit with four dedicated SAR ADC cores
and one shared SAR ADC core
Flash Architecture - Configurable resolution (up to 12-bit) for each
• Dual Partition Flash Program Memory with ADC core
LiveUpdate: - Up to 3.25 Msps conversion rate per channel
- Supports programming while operating at 12-bit resolution
- Supports partition soft swap - 11 to 22 single-ended inputs
- Dedicated result buffer for each analog channel
Core: 16-Bit dsPIC33E CPU - Flexible and independent ADC trigger sources
• Code-Efficient (C and Assembly) Architecture - Two digital comparators
• Two 40-Bit Wide Accumulators - Two oversampling filters for increased
• Single-Cycle (MAC/MPY) with Dual Data Fetch resolution
• Single-Cycle Mixed-Sign MUL plus • Four Rail-to-Rail Comparators with Hysteresis:
Hardware Divide - Dedicated 12-bit Digital-to-Analog Converter
• 32-Bit Multiply Support (DAC) for each analog comparator
• Four Additional Working Register Sets (reduces - Up to two DAC reference outputs
context switching) - Up to two external reference inputs
• Two Programmable Gain Amplifiers:
Clock Management
- Single-ended or independent ground reference
• ±0.9% Internal Oscillator
- Five selectable gains (4x, 8x, 16x, 32x and 64x)
• Programmable PLLs and Oscillator Clock Sources
- 40 MHz gain bandwidth
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT) Interconnected SMPS Peripherals
• Fast Wake-up and Start-up
• Reduces CPU Interaction to Improve Performance
Power Management • Flexible PWM Trigger Options for
ADC Conversions
• Low-Power Management modes (Sleep,
Idle, Doze) • High-Speed Comparator Truncates PWM
(15 ns typical):
• Integrated Power-on Reset and Brown-out Reset
- Supports Cycle-by-Cycle Current-mode control
• 0.5 mA/MHz Dynamic Current (typical)
- Current Reset mode (variable frequency)
• 20 μA IPD Current (typical)
High-Speed PWM Timers/Output Compare/Input Capture

• Eight PWM Generators (two outputs per generator) • Five 16-Bit and up to Two 32-Bit Timers/Counters
• Individual Time Base and Duty Cycle for each PWM • Four Output Compare (OC) modules, Configurable
as Timers/Counters
• 1.04 ns PWM Resolution (frequency, duty cycle,
dead time and phase) • Four Input Capture (IC) modules
• Supports Center-Aligned, Redundant, Complementary
and True Independent Output modes
• Independent Fault and Current-Limit Inputs
• Output Override Control
• PWM Support for AC/DC, DC/DC, Inverters, PFC
and Lighting
 2016-2018 Microchip Technology Inc. DS70005258C-page 1

Communication Interfaces Qualification and Class B Support
• Two UART modules (15 Mbps): • AEC-Q100 REVG (Grade 1, -40°C to +125°C)
- Supports LIN/J2602 protocols and IrDA® • Class B Safety Library, IEC 60730
• Three Variable Width SPI modules with Operating • The 6x6x0.55 mm UQFN Package is Designed
modes: and Optimized to ease IPC9592B 2nd Level
- 3-wire SPI Temperature Cycle Qualification
- 8x16 or 8x8 FIFO mode
- I2S mode Debugger Development Support
• Two I2C modules (up to 1 Mbaud) with SMBus • In-Circuit and In-Application Programming
Support • Five Program and Three Complex
• Up to Two CAN modules Data Breakpoints
• Four-Channel DMA • IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace and Run-Time Watch
Input/Output
• Constant-Current Source (10 µA nominal) Digital Peripherals
• Sink/Source up to 12 mA/15 mA, respectively;
• Four Configurable Logic Cells
Pin-Specific for Standard VOH/VOL
• Peripheral Trigger Generator
• 5V Tolerant Pins
• Selectable, Open-Drain Pull-ups and Pull-Downs
• External Interrupts on all I/O Pins
• Peripheral Pin Select (PPS) to allow Function
Remap with Six Virtual I/Os
12-Bit
General Purpose I/O (GPIO)
Remappable Peripherals
Constant-Current Source
Program Memory Bytes
ADC
Analog Comparator
External Interrupts(3)
RAM (Bytes)
DAC Output
Packages
Output Compare
Reference Clock
Analog Inputs
Input Capture
S&H Circuits
DMA
PGA
Pins
CLC
PTG
I2C
Device
Timers(1)
PWM(2)
UART
CAN
SPI
dsPIC33EP128GS702 28 128K 8K 20 5 4 4 2 3 8x2 4 0 1 2 4 1 11 5 2 0 4 1 1 SOIC,

QFN-S,
UQFN
dsPIC33EP64GS804 44 64K 8K 33 5 4 4 2 3 8x2 4 2 1 2 4 1 17 5 2 4 4 1 1
QFN,
dsPIC33EP128GS704 44 128K 8K 33 5 4 4 2 3 8x2 4 0 1 2 4 1 17 5 2 0 4 1 1
TQFP
dsPIC33EP128GS804 44 128K 8K 33 5 4 4 2 3 8x2 4 2 1 2 4 1 17 5 2 4 4 1 1
dsPIC33EP64GS805 48 64K 8K 33 5 4 4 2 3 8x2 4 2 1 2 4 1 17 5 2 4 4 1 1
dsPIC33EP128GS705 48 128K 8K 33 5 4 4 2 3 8x2 4 0 1 2 4 1 17 5 2 0 4 1 1 TQFP
dsPIC33EP128GS805 48 128K 8K 33 5 4 4 2 3 8x2 4 2 1 2 4 1 17 5 2 4 4 1 1
dsPIC33EP64GS806 64 64K 8K 51 5 4 4 2 3 8x2 4 2 1 2 4 1 22 5 2 4 4 2 1
dsPIC33EP128GS706 64 128K 8K 51 5 4 4 2 3 8x2 4 0 1 2 4 1 22 5 2 0 4 2 1 TQFP
dsPIC33EP128GS806 64 128K 8K 51 5 4 4 2 3 8x2 4 2 1 2 4 1 22 5 2 4 4 2 1
dsPIC33EP64GS708 80 64K 8K 67 5 4 4 2 3 8x2 4 0 1 2 4 1 22 5 2 0 4 2 1
dsPIC33EP64GS808 80 64K 8K 67 5 4 4 2 3 8x2 4 2 1 2 4 1 22 5 2 4 4 2 1
TQFP
dsPIC33EP128GS708 80 128K 8K 67 5 4 4 2 3 8x2 4 0 1 2 4 1 22 5 2 0 4 2 1
dsPIC33EP128GS808 80 128K 8K 67 5 4 4 2 3 8x2 4 2 1 2 4 1 22 5 2 4 4 2 1
Note 1: The external clock for Timer1, Timer2 and Timer3 is remappable.
2: PWM4 through PWM8 are remappable on 28/44/48-pin devices; on 64-pin devices, only PWM7/PWM8 are remappable.
3: External interrupts, INT0 and INT4, are not remappable.
DS70005258C-page 2  2016-2018 Microchip Technology Inc.

Pin Diagrams
28-Pin SOIC
MCLR 1 28 AVDD
RA0 2 27 AVSS
RA1 3 26 RA3
RA2 4 25 RA4
dsPIC33EP128GS702
RB0 5 24 RB14
RB9 6 23 RB13
AVDD 7 22 RB12
VSS 8 21 RB11
RB1 9 20 VCAP
RB2 10 19 VSS
RB3 11 18 RB7
RB4 12 17 RB6
VDD 13 16 RB5
RB8 14 15 RB15
Pin Pin Function Pin Pin Function
1 MCLR 15 PGEC3/SCL2/RP47/RB15
2 AN0/CMP1A/PGA1P1/RP16/RA0 16 TDO/AN19/PGA2N2/RP37/RB5
3 AN1/CMP1B/PGA1P2/PGA2P1/RP17/RA1 17 PGED1/TDI/AN20/SCL1/RP38/RB6
4 AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2 18 PGEC1/AN21/SDA1/RP39/RB7
5 AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0 19 VSS
6 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9 20 VCAP
7 AVDD 21 TMS/PWM3H/RP43/RB11
8 VSS 22 TCK/PWM3L/RP44/RB12
9 OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1 23 PWM2H/RP45/RB13
10 OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1) 24 PWM2L/RP46/RB14
11 PGED2/DACOUT1/AN18/INT0/RP35/RB3 25 PWM1H/RP20/RA4
12 PGEC2/ADTRG31/EXTREF1/RP36/RB4 26 PWM1L/RP19/RA3
13 VDD 27 AVSS
14 PGED3/SDA2/FLT31/RP40/RB8 28 AVDD
Legend: Shaded pins are up to 5 VDC tolerant.

RPn represents remappable peripheral functions. See Table 11-12 and Table 11-13 for the complete list of remappable sources.
Note 1: At device power-up (POR), a pulse with an amplitude around 2V and a duration greater than 500 µs, may be observed on this
device pin independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being
driven can endure this active duration.

Pin Diagrams (Continued)
28-Pin QFN-S, UQFN
MCLR
AVDD
AVSS
RA3
RA4
RA1
RA0
28 27 26 25 24 23 22
RA2 1 21 RB14
RB0 2 20 RB13
RB9 3 19 RB12
AVDD 4 dsPIC33EP128GS702 18 RB11
VSS 5 17 VCAP
RB1 6 16 VSS
RB2 7 15 RB7
8 9 10 11 12 13 14
RB6
RB3
RB4
RB8
RB15
RB5
VDD
1 AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2 15 PGEC1/AN21/SDA1/RP39/RB7
2 AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0 16 VSS
3 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9 17 VCAP
4 AVDD 18 TMS/PWM3H/RP46/RB11
5 VSS 19 TCK/PWM3L/RP44/RB12
6 OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1 20 PWM2H/RP45/RB13
7 OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1) 21 PWM2L/RP46/RB14
8 PGED2/DACOUT1/AN18/INT0/RP35/RB3 22 PWM1H/RP20/RA4
9 PGEC2/ADTRG31/EXTREF1/RP36/RB4 23 PWM1L/RP19/RA3
10 VDD 24 AVSS
11 PGED3/SDA2/FLT31/RP40/RB8 25 AVDD
12 PGEC3/SCL2/RP47/RB15 26 MCLR
13 TDO/AN19/PGA2N2/RP37/RB5 27 AN0/CMP1A/PGA1P1/RP16/RA0
14 PGED1/TDI/AN20/SCL1/RP38/RB6 28 AN1/CMP1B/PGA1P2/PGA2P1/RP17/RA1


44-Pin QFN, TQFP
RB15
RC8
RC7
RC2
RB5
RB8
RB4
RB3
RB6
VDD
VSS
44
43
42
41
40
39
38
37
36
35
34
RB7 1 33 RB2
RC4 2 32 RB1
RC5 3 31 RC1
RC6 4 30 VSS
RC3 5 29 VDD
VSS 6 dsPIC33EPXXXGSX04 28 RC10
VCAP 7 27 RC9
RB11 8 26 AVDD
RB12 9 25 RB9
RB13 10 24 RB0
RB14 11 23 RA2
12
13
14
15
16
17
18
19
20
21
22
RC13
RC12
RA4
RA3
RC0
MCLR
RA0
RA1
AVSS
AVDD
AVDD
1 PGEC1/AN21/SDA1/RP39/RB7 23 AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2
2 AN1ALT/RP52/RC4 24 AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0
3 AN0ALT/RP53/RC5 25 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
4 AN17/RP54/RC6 26 AVDD
5 RP51/RC3 27 AN11/PGA1N3/RP57/RC9
6 VSS 28 EXTREF2/AN10/PGA1P4/RP58/RC10
7 VCAP 29 VDD
8 TMS/PWM3H/RP43/RB11 30 VSS
9 TCK/PWM3L/RP44/RB12 31 AN8/CMP4C/PGA2P4/RP49/RC1
10 PWM2H/RP45/RB13 32 OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
11 PWM2L/RP46/RB14 33 OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1)
12 PWM1H/RP20/RA4 34 PGED2/DACOUT1/AN18/INT0/RP35/RB3
13 PWM1L/RP19/RA3 35 PGEC2/ADTRG31/RP36/RB4
14 FLT12/RP48/RC0 36 EXTREF1/AN9/CMP4D/RP50/RC2
15 FLT11/RP61/RC13 37 ASDA1/RP55/RC7
16 AVSS 38 ASCL1/RP56/RC8
17 AVDD 39 VSS
18 MCLR 40 VDD
19 AVDD 41 PGED3/SDA2/FLT31/RP40/RB8
20 AN14/PGA2N3/RP60/RC12 42 PGEC3/SCL2/RP47/RB15


48-Pin TQFP
RD14
RB15
RC8
RC7
RC2
RB6
RB5
RB8
RB4
RB3
VDD
VSS
48
47
46
45
44
43
42
41
40
39
38
37
RB7 1 36 RB2
RC4 2 35 RB1
RC5 3 34 RC1
RC6 4 33 N/C
RC3 5 32 Vss
VSS 6 dsPIC33EPXXXGSX05 31 VDD
VCAP 7 30 RC10
RD4 8 29 RC9
RB11 9 28 AVDD
RB12 10 27 RB9
RB13 11 26 RB0
RB14 12 25 RA2
13
14
15
16
17
18
19
20
21
22
23
24
RC0
MCLR
AVSS
AVDD
AVDD
RC13
RD10
RC12
RA4
RA3
RA0
RA1
1 PGEC1/AN21/SDA1/RP39/RB7 25 AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2
2 AN1ALT/RP52/RC4 26 AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0
3 AN0ALT/RP53/RC5 27 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
4 AN17/RP54/RC6 28 AVDD
5 RP51/RC3 29 AN11/PGA1N3/RP57/RC9
6 VSS 30 EXTREF2/AN10/PGA1P4/RP58/RC10
7 VCAP 31 VDD
8 RP68/RD4 32 VSS
9 TMS/PWM3H/RP43/RB11 33 N/C
10 TCK/PWM3L/RP44/RB12 34 AN8/CMP4C/PGA2P4/RP49/RC1
11 PWM2H/RP45/RB13 35 OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
12 PWM2L/RP46/RB14 36 OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1)
13 PWM1H/RP20/RA4 37 PGED2/DACOUT1/AN18/INT0/RP35/RB3
14 PWM1L/RP19/RA3 38 PGEC2/ADTRG31/RP36/RB4
15 FLT12/RP48/RC0 39 EXTREF1/AN9/CMP4D/RP50/RC2
17 CLC4OUT/FLT10/RP74/RD10 41 ASCL1/RP56/RC8
18 AVSS 42 VSS
19 AVDD 43 VDD
20 MCLR 44 CLC3OUT/RD14


RD15
RB14
RB13
RB12
RB11
VCAP
RD1
RD4
RC3
RD6
RD5
RC6
RC5
RC4
RB7
VDD
64-Pin TQFP
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RD3 1 48 RB6
RA4 2 47 RD0
RA3 3 46 RB5
RC0 4 45 RD11
RC13 5 44 RB15
RD10 6 43 RB8
MCLR 7 42 RD8
RD12 8 41 VSS
dsPIC33EPXXXGSX06
VSS 9 40 RD9
VDD 10 39 RD14
AVDD 11 38 VDD
RC12 12 37 RC8
RA0 13 36 RC7
RA1 14 35 RC2
RA2 15 34 RC14
RB0 16 33 RB4
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RB9
RD7
RD13
RC9
RC10
RC1
RB1
RB2
RD2
RC15
RB3
AVSS
VSS
AVDD
AVDD
VDD
1 PWM4L/RP67/RD3 33 PGEC2/ADTRG31/RP36/RB4
2 PWM1H/RP20/RA4 34 RP62/RC14
3 PWM1L/RP19/RA3 35 EXTREF1/AN9/CMP4D/RP50/RC2
5 FLT11/RP61/RC13 37 ASCL1/RP56/RC8
6 CLC4OUT/FLT10/RP74/RD10 38 VDD
8 T5CK/FLT9/RP76/RD12 40 SCK3/RP73/RD9
9 VSS 41 VSS
10 VDD 42 AN5/CMP2D/CMP3B/ISRC3/RP72RD8
13 AN0/CMP1A/PGA1P1/RP16/RA0 45 INT4/RP75/RD11
14 AN1/CMP1B/PGA1P2/PGA2P1/RP17/RA1 46 TDO/AN19/PGA2N2/RP37/RB5
15 AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2 47 T4CK/RP64/RD0
16 AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0 48 PGED1/TDI/AN20/SCL1/RP38/RB6
17 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9 49 PGEC1/AN21/SDA1/RP39/RB7
18 AVDD 50 AN1ALT/RP52/RC4
20 AVSS 52 AN17/RP54/RC6
21 AN15/RP71/RD7 53 AN12/ISRC1/RP69/RD5
22 DACOUT2/AN13/RD13 54 PWM5H/RP70/RD6
23 AN11/PGA1N3/RP57/RC9 55 PWM5L/RP51/RC3
24 EXTREF2/AN10/PGA1P4/RP58/RC10 56 VCAP
25 VSS 57 VDD
26 VDD 58 PWM6H/RP68/RD4
27 AN8/CMP4C/PGA2P4/RP49/RC1 59 PWM6L/RD15
28 OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1 60 TMS/PWM3H/RP43/RB11
29 OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1) 61 TCK/PWM3L/RP44/RB12
30 AN16/RP66/RD2 62 PWM2H/RP45/RB13
31 ASDA2/RP63/RC15 63 PWM2L/RP46/RB14
32 PGED2/DACOUT1/AN18/ASCL2/INT0/RP35/RB3 64 PWM4H/RP65/RD1

RD15
RB14
RB13
RB12
RE15
RE14
RE13
RE12
RB11
VCAP
RD1
RD4
RC3
RD6
RD5
RC6
RC5
RC4
RB7
VDD
80-Pin TQFP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RD3 1 60 RB6
RA4 2 59 RD0
RA3 3 58 RB5
RE0 4 57 RD11
RE1 5 56 RB15
RC0 6 55 RB8
RC13 7 54 RD8
RD10 8 53 RE11
MCLR 9 52 RE10
RD12 10 dsPIC33EPXXXGSX08 51 VSS
VSS 11 50 RD9
VDD 12 49 RD14
RE2 13 48 VDD
RE3 14 47 RC8
AVDD 15 46 RC7
RC12 16 45 RC2
RA0 17 44 RE9
RA1 18 43 RE8
RA2 19 42 RC14
RB0 20 41 RB4
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RB9
RE4
RE5
RD7
RD13
RC9
RC10
RC1
RB1
RB2
RD2
RE6
RE7
RC15
RB3
AVSS
VSS
AVDD
AVDD
VDD
1 PWM4L/RP67/RD3 41 PGEC2/ADTRG31/RP36/RB4
2 PWM1H/RP20/RA4 42 RP62/RC14
3 PWM1L/RP19/RA3 43 RE8
4 PWM8L/RE0 44 RE9
5 PWM8H/RE1 45 EXTREF1/AN9/CMP4D/RP50/RC2
7 FLT11/RP61/RC13 47 ASCL1/RP56/RC8
8 CLC4OUT/FLT10/RP74/RD10 48 VDD
10 T5CK/FLT9/RP76/RD12 50 SCK3/RP73/RD9
11 VSS 51 VSS
12 VDD 52 FLT21/RE10
13 FLT17/RE2 53 FLT22/RE11
14 FLT18/RE3 54 AN5/CMP2D/CMP3B/ISRC3/RP72/RD8
17 AN0/CMP1A/PGA1P1/RP16/RA0 57 INT4/RP75/RD11
18 AN1/CMP1B/PGA1P2/PGA2P1/RP17/RA1 58 TD0/AN19/PGA2N2/RP37/RB5
19 AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2 59 T4CK/RP64/RD0
20 AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0 60 PGED1/TDI/AN20/SCL1/RP38/RB6
21 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9 61 PGEC1/AN21/SDA1/RP39/RB7
22 RE4 62 AN1ALT/RP52/RC4
23 RE5 63 RE12
24 AVDD 64 RE13
26 AVSS 66 AN17/RP54/RC6
27 AN15/RP71/RD7 67 AN12/ISRC1/RP69/RD5
28 DACOUT2/AN13/RD13 68 PWM5H/RP70/RD6
29 AN11/PGA1N3/RP57/RC9 69 PWM5L/RP51/RC3
30 EXTREF2/AN10/PGA1P4/RP58/RC10 70 VCAP
31 VSS 71 VDD
32 VDD 72 PWM6H/RP68/RD4
33 AN8/CMP4C/PGA2P4/RP49/RC1 73 PWM6L/RD15
34 OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1 74 PWM7L/RE14
35 OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1) 75 PWM7H/RE15
36 AN16/RP66/RD2 76 TMS/PWM3H/RP43/RB11
37 FLT19/RE6 77 TCK/PWM3L/RP44/RB12
38 FLT20/RE7 78 PWM2H/RP45/RB13
39 ASDA2/RP63/RC15 79 PWM2L/RP46/RB14
40 PGED2/DACOUT1/AN18/ASCL2/INT0/RP35/RB3 80 PWM4H/RP65/RD1

Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 17
3.0 CPU............................................................................................................................................................................................ 23
4.0 Memory Organization ................................................................................................................................................................. 33
5.0 Flash Program Memory.............................................................................................................................................................. 63
6.0 Resets ....................................................................................................................................................................................... 71
7.0 Interrupt Controller ..................................................................................................................................................................... 75
8.0 Direct Memory Access (DMA) .................................................................................................................................................... 91
9.0 Oscillator Configuration ............................................................................................................................................................ 105
10.0 Power-Saving Features............................................................................................................................................................ 117
11.0 I/O Ports ................................................................................................................................................................................... 127
12.0 Timer1 ...................................................................................................................................................................................... 171
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 175
14.0 Input Capture............................................................................................................................................................................ 179
15.0 Output Compare....................................................................................................................................................................... 183
16.0 High-Speed PWM..................................................................................................................................................................... 189
17.0 Peripheral Trigger Generator (PTG) Module............................................................................................................................ 217
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 233
19.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 249
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 257
21.0 Configurable Logic Cell (CLC).................................................................................................................................................. 263
22.0 High-Speed, 12-Bit Analog-to-Digital Converter (ADC)............................................................................................................ 277
23.0 Controller Area Network (CAN) Module (dsPIC33EPXXXGS80X Devices Only) .................................................................... 311
24.0 High-Speed Analog Comparator .............................................................................................................................................. 337
25.0 Programmable Gain Amplifier (PGA) ....................................................................................................................................... 345
26.0 Constant-Current Source ......................................................................................................................................................... 349
27.0 Special Features ...................................................................................................................................................................... 351
28.0 Instruction Set Summary .......................................................................................................................................................... 365
29.0 Development Support............................................................................................................................................................... 375
30.0 Electrical Characteristics .......................................................................................................................................................... 379
31.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 439
32.0 Packaging Information.............................................................................................................................................................. 443
Appendix A: Revision History............................................................................................................................................................. 469
Index ................................................................................................................................................................................................. 471
The Microchip Website ...................................................................................................................................................................... 479
Customer Change Notification Service .............................................................................................................................................. 479
Customer Support .............................................................................................................................................................................. 479
Product Identification System ............................................................................................................................................................ 481

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Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of
the dsPIC33EPXXXGS70X/80X prod-
uct page of the Microchip website
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.
• “dsPIC33E Enhanced CPU” (DS70005158)

• “dsPIC33E/PIC24E Program Memory” (DS70000613)
• “Data Memory” (DS70595)
• “Dual Partition Flash Program Memory” (DS70005156)
• “Flash Programming” (DS70609)
• “Reset” (DS70602)
• “Interrupts” (DS70000600)
• “Direct Memory Access (DMA)” (DS70348)
• “Oscillator Module” (DS70005131)
• “Watchdog Timer and Power-Saving Modes” (DS70615)
• “I/O Ports” (DS70000598)
• “Timers” (DS70362)
• “Input Capture with Dedicated Timer” (DS70000352)
• “Output Compare with Dedicated Timer” (DS70005159)
• “High-Speed PWM Module” (DS70000323)
• “Peripheral Trigger Generator (PTG)” (DS70000669)
• “Serial Peripheral Interface (SPI) with Audio Codec Support” (DS70005136)
• “Inter-Integrated Circuit (I2C)” (DS70000195)
• “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582)
• “Configurable Logic Cell (CLC)” (DS70005298)
• “12-Bit High-Speed, Multiple SARs A/D Converter (ADC)” (DS70005213)
• “Enhanced Controller Area Network (ECAN™)” (DS70353)
• “High-Speed Analog Comparator Module” (DS70005128)
• “Programmable Gain Amplifier (PGA)” (DS70005146)
• “Device Configuration” (DS70000618)
• “Watchdog Timer and Power-Saving Modes” (DS70615)
• “CodeGuard™ Intermediate Security” (DS70005182)
• “Programming and Diagnostics” (DS70608)

NOTES:

1.0 DEVICE OVERVIEW This document contains device-specific information for
the dsPIC33EPXXXGS70X/80X Digital Signal Controller
Note 1: This data sheet summarizes the features (DSC) devices.
of the dsPIC33EPXXXGS70X/80X family dsPIC33EPXXXGS70X/80X devices contain extensive
of devices. It is not intended to be a Digital Signal Processor (DSP) functionality with a
comprehensive resource. To comple- high-performance, 16-bit MCU architecture.
ment the information in this data sheet,
refer to the related section of the Figure 1-1 shows a general block diagram of the core
“dsPIC33/PIC24 Family Reference and peripheral modules. Table 1-1 lists the functions of
Manual”, which is available from the the various pins shown in the pinout diagrams.
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific
register and bit information.
FIGURE 1-1: dsPIC33EPXXXGS70X/80X FAMILY BLOCK DIAGRAM
CPU
Refer to Figure 3-1 for CPU diagram details.
PORTA
16
PORTB
Power-up
Timer
16
Timing Oscillator
Start-up
Generation Timer
OSC1/CLKI PORTC
POR/BOR
MCLR
Watchdog
Timer PORTD
VDD, VSS
AVDD, AVSS
Peripheral Modules
PORTE
CAN Input Output
PGA1, I2C1,
Modules PTG ADC Captures Compares
PGA2 I2C2
1-2 1-4 1-4
Remappable
Pins
Constant Analog Ports

CLC PWMs Timers UART1,
Current Comparators SPI1-3
Source 1-4 8x2 1-5 UART2
1-4

TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Buffer
Pin Name(1) PPS Description
Type Type
AN0-AN21 I Analog No Analog input channels.
AN0ALT-AN1ALT I Analog No Alternate analog input channels.
C1RXR I ST Yes CAN1 receive.
C2RXR I ST Yes CAN2 receive.
C1TX O ST Yes CAN1 transmit.
C2TX O ST Yes CAN2 transmit.
CLKI I ST/ No External clock source input. Always associated with OSC1 pin
CMOS function.
CLKO O — No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1 I ST/ No Oscillator crystal input. ST buffer when configured in RC mode; CMOS
CMOS otherwise.
OSC2 I/O — No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
CLC1OUT O DIG Yes CLC1 output.
CLC2OUT O DIG Yes CLC2 output.
CLC3OUT O DIG No(4) CLC3 output.
CLC4OUT O DIG No(4) CLC4 output.
REFCLKO O — Yes Reference clock output.
IC1-IC4 I ST Yes Capture Inputs 1 through 4.
OCFA I ST Yes Compare Fault A input (for compare channels).
OC1-OC4 O — Yes Compare Outputs 1 through 4.
INT0 I ST No External Interrupt 0.
INT1 I ST Yes External Interrupt 1.
RA0-RA4 I/O ST No PORTA is a bidirectional I/O port.
RB0-RB15 I/O ST No PORTB is a bidirectional I/O port.
RC0-RC15 I/O ST No PORTC is a bidirectional I/O port.
RD0-RD15 I/O ST No PORTD is a bidirectional I/O port.
RE0-RE15 I/O ST No PORTE is a bidirectional I/O port.
T1CK I ST Yes Timer1 external clock input.
T4CK I ST No Timer4 external clock input.
T5CK I ST No Timer5 external clock input.
U1CTS I ST Yes UART1 Clear-to-Send.
U1RTS O — Yes UART1 Ready-to-Send.
U1RX I ST Yes UART1 receive.
U1TX O — Yes UART1 transmit.
BCLK1 O ST Yes UART1 IrDA® baud clock output.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select
1: Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability.
2: PWM4H/L through PWM8H/L are fixed on dsPIC33EPXXXGS708/808 devices. PWM4H/L through
PWM6H/L are fixed on dsPIC33EPXXXGS706/806 devices.
3: The SCK3 pin is fixed on dsPIC33EPXXXGS706/806 and dsPIC33EPXXXGS708/808 devices.
4: PPS is available on dsPIC33EPXXXGS702 devices only.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer
Type Type
U2CTS I ST Yes UART2 Clear-to-Send.

U2RTS O — Yes UART2 Ready-to-Send.
U2RX I ST Yes UART2 receive.
U2TX O — Yes UART2 transmit.
BCLK2 O ST Yes UART2 IrDA baud clock output.
SCK1 I/O ST Yes Synchronous serial clock input/output for SPI1.
SDI1 I ST Yes SPI1 data in.
SDO1 O — Yes SPI1 data out.
SS1 I/O ST Yes SPI1 slave synchronization or frame pulse I/O.
SCK2 I/O ST Yes Synchronous serial clock input/output for SPI2.
SCK3 I/O ST Yes(3) Synchronous serial clock input/output for SPI3.
SCL1 I/O ST No Synchronous serial clock input/output for I2C1.
SDA1 I/O ST No Synchronous serial data input/output for I2C1.
ASCL1 I/O ST No Alternate synchronous serial clock input/output for I2C1.
ASDA1 I/O ST No Alternate synchronous serial data input/output for I2C1.
SCL2 I/O ST No Synchronous serial clock input/output for I2C2.
SDA2 I/O ST No Synchronous serial data input/output for I2C2.
ASCL2 I/O ST No Alternate synchronous serial clock input/output for I2C2.
ASDA2 I/O ST No Alternate synchronous serial data input/output for I2C2.
TMS I ST No JTAG Test mode select pin.
TCK I ST No JTAG test clock input pin.
TDI I ST No JTAG test data input pin.
TDO O — No JTAG test data output pin.
FLT1-FLT8 I ST Yes PWM Fault Inputs 1 through 8.
FLT9-FLT12 I ST No PWM Fault Inputs 9 through 12.
FLT17-FLT22 I ST No PWM Fault Inputs 17 through 22.
FLT31 I ST No PWM Fault Input 31 (Class B Fault).
PWM1L-PWM3L O — No PWM Low Outputs 1 through 3.
PWM1H-PWM3H O — No PWM High Outputs 1 through 3.
PWM4L-PWM8L(2) O — Yes PWM Low Outputs 4 through 8.
PWM4H-PWM8H(2) O — Yes PWM High Outputs 4 through 8.
SYNCI1, SYNCI2 I ST Yes PWM Synchronization Inputs 1 and 2.
SYNCO1, SYNCO2 O — Yes PWM Synchronization Outputs 1 and 2.

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer
Type Type
CMP1A-CMP4A I Analog No Comparator Channels 1A through 4A inputs.
CMP1B-CMP4B I Analog No Comparator Channels 1B through 4B inputs.
CMP1C-CMP4C I Analog No Comparator Channels 1C through 4C inputs.
CMP1D-CMP4D I Analog No Comparator Channels 1D through 4D inputs.
ACMP1-ACMP4 O — Yes Analog Comparator Outputs 1-4.
DACOUT1, O — No DAC Output Voltages 1 and 2.
DACOUT2
EXTREF1, EXTREF2 I Analog No External Voltage Reference Inputs 1 and 2 for the Reference DACs.
PGA1P1-PGA1P4 I Analog No PGA1 Positive Inputs 1 through 4.
PGA1N1-PGA1N3 I Analog No PGA1 Negative Inputs 1 through 3.
PGA2P1-PGA2P4 I Analog No PGA2 Positive Inputs 1 through 4.
PGA2N1-PGA2N3 I Analog No PGA2 Negative Inputs 1 through 3.
ADTRG31 I ST No External ADC trigger source.
PGED1 I/O ST No Data I/O pin for Programming/Debugging Communication Channel 1.
PGEC1 I ST No Clock input pin for Programming/Debugging Communication Channel 1.
MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD P P No Positive supply for analog modules. This pin must be connected at all
times.
AVSS P P No Ground reference for analog modules. This pin must be connected at
all times.
VDD P — No Positive supply for peripheral logic and I/O pins.
VCAP P — No CPU logic filter capacitor connection.
VSS P — No Ground reference for logic and I/O pins.

2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors
STARTED WITH 16-BIT DIGITAL The use of decoupling capacitors on every pair of
SIGNAL CONTROLLERS power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Note 1: This data sheet summarizes the features
Consider the following criteria when using decoupling
of the dsPIC33EPXXXGS70X/80X family
capacitors:
of devices. It is not intended to be a
comprehensive reference source. To • Value and type of capacitor: Recommendation
complement the information in this data of 0.1 µF (100 nF), 10-20V. This capacitor should
sheet, refer to the related section of be a low-ESR and have resonance frequency in
the “dsPIC33/PIC24 Family Reference the range of 20 MHz and higher. It is
Manual”, which is available from the recommended to use ceramic capacitors.
Microchip website (www.microchip.com). • Placement on the printed circuit board: The
2: Some registers and associated bits decoupling capacitors should be placed as close
described in this section may not be to the pins as possible. It is recommended to
available on all devices. Refer to place the capacitors on the same side of the
Section 4.0 “Memory Organization” in board as the device. If space is constricted, the
this data sheet for device-specific register capacitor can be placed on another layer on the
and bit information. PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
2.1 Basic Connection Requirements
• Handling high-frequency noise: If the board is
Getting started with the dsPIC33EPXXXGS70X/80X experiencing high-frequency noise, above tens
family requires attention to a minimal set of device pin of MHz, add a second ceramic-type capacitor in
connections before proceeding with development. The parallel to the above described decoupling
following is a list of pin names which must always be capacitor. The value of the second capacitor can
connected: be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
• All VDD and VSS pins
capacitor. In high-speed circuit designs, consider
(see Section 2.2 “Decoupling Capacitors”)
implementing a decade pair of capacitances as
• All AVDD and AVSS pins close to the power and ground pins as possible.
regardless if ADC module is not used (see For example, 0.1 µF in parallel with 0.001 µF.
Section 2.2 “Decoupling Capacitors”)
• Maximizing performance: On the board layout
• VCAP from the power supply circuit, run the power and
(see Section 2.3 “CPU Logic Filter Capacitor return traces to the decoupling capacitors first,
Connection (VCAP)”) and then to the device pins. This ensures that the
• MCLR pin decoupling capacitors are first in the power chain.
(see Section 2.4 “Master Clear (MCLR) Pin”) Equally important is to keep the trace length
• PGECx/PGEDx pins between the capacitor and the power pins to a
used for In-Circuit Serial Programming™ (ICSP™) minimum, thereby reducing PCB track
and debugging purposes (see Section 2.5 “ICSP inductance.
Pins”)
• OSC1 and OSC2 pins
when external oscillator source is used (see
Section 2.6 “External Oscillator Pins”)

FIGURE 2-1: RECOMMENDED The placement of this capacitor should be close to the
MINIMUM CONNECTION VCAP pin. It is recommended that the trace length not
exceed one-quarter inch (6 mm). See Section 27.4
“On-Chip Voltage Regulator” for details.
10 µF 0.1 µF
VDD Tantalum Ceramic
2.4 Master Clear (MCLR) Pin
VDD
VCAP
VSS
R
R1
The MCLR pin provides two specific device
MCLR functions:
• Device Reset
C
• Device Programming and Debugging.
dsPIC33EP
During device programming and debugging, the
VSS VDD
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
VDD VSS
0.1 µF 0.1 µF debuggers drive the MCLR pin. Consequently,
AVDD
AVSS
Ceramic
VDD
VSS
Ceramic specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
0.1 µF 0.1 µF specific values of R and C will need to be adjusted
Ceramic Ceramic
based on the application and PCB requirements.
L1(1)
For example, as shown in Figure 2-2, it is recom-
Note 1: As an option, instead of a hard-wired connection, an mended that the capacitor, C, be isolated from the
inductor (L1) can be substituted between VDD and MCLR pin during programming and debugging
AVDD to improve ADC noise rejection. The inductor operations.
impedance should be less than 1 and the inductor
capacity greater than 10 mA. Place the components as shown in Figure 2-2, within
Where: one-quarter inch (6 mm) from the MCLR pin.
F CNV
f = -------------- (i.e., ADC Conversion Rate/2) FIGURE 2-2: EXAMPLE OF MCLR PIN
2
CONNECTIONS
1
f = -----------------------
 2 LC 
VDD
1 2
L =  ----------------------
  2f C  R(1)
R1(2)
MCLR
2.2.1 TANK CAPACITORS
JP
On boards with power traces running longer than six dsPIC33EP
inches in length, it is suggested to use a tank capacitor C
for integrated circuits, including DSCs, to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
Note 1: R  10 k is recommended. A suggested
nects the power supply source to the device and the
starting value is 10 k. Ensure that the
maximum current drawn by the device in the applica- MCLR pin VIH and VIL specifications are met.
tion. In other words, select the tank capacitor so that it 2: R1  470 will limit any current flowing into
meets the acceptable voltage sag at the device. Typical MCLR from the external capacitor, C, in the
values range from 4.7 µF to 47 µF. event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
2.3 CPU Logic Filter Capacitor Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
Connection (VCAP)
A low-ESR (< 0.5Ω) capacitor is required on the VCAP
pin, which is used to stabilize the voltage regulator
output voltage. The VCAP pin must not be connected to
VDD and must have a capacitor greater than 4.7 µF
(10 µF is recommended), 16V connected to ground. The
type can be ceramic or tantalum. See Section 30.0
“Electrical Characteristics” for additional information.

2.5 ICSP Pins 2.6 External Oscillator Pins
The PGECx and PGEDx pins are used for ICSP and Many DSCs have options for at least two oscillators: a
debugging purposes. It is recommended to keep the high-frequency primary oscillator and a low-frequency
trace length between the ICSP connector and the ICSP secondary oscillator. For details, see Section 9.0
pins on the device as short as possible. If the ICSP con- “Oscillator Configuration” for details.
nector is expected to experience an ESD event, a The oscillator circuit should be placed on the same
series resistor is recommended, with the value in the side of the board as the device. Also, place the
range of a few tens of Ohms, not to exceed 100 Ohms. oscillator circuit close to the respective oscillator pins,
Pull-up resistors, series diodes and capacitors on the not exceeding one-half inch (12 mm) distance
PGECx and PGEDx pins are not recommended as they between them. The load capacitors should be placed
will interfere with the programmer/debugger communi- next to the oscillator itself, on the same side of the
cations to the device. If such discrete components are board. Use a grounded copper pour around the
an application requirement, they should be removed oscillator circuit to isolate them from surrounding
from the circuit during programming and debugging. circuits. The grounded copper pour should be routed
Alternatively, refer to the AC/DC characteristics and directly to the MCU ground. Do not run any signal
timing requirements information in the respective traces or power traces inside the ground pour. Also, if
device Flash programming specification for information using a two-sided board, avoid any traces on the
on capacitive loading limits and pin Voltage Input High other side of the board where the crystal is placed. A
(VIH) and Voltage Input Low (VIL) requirements. suggested layout is shown in Figure 2-3.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device FIGURE 2-3: SUGGESTED PLACEMENT
matches the physical connections for the ICSP OF THE OSCILLATOR
to MPLAB® PICkit™ 3, MPLAB ICD 3, or MPLAB CIRCUIT
REAL ICE™.
For more information on MPLAB ICD 2, MPLAB ICD 3 Main Oscillator
and REAL ICE connection requirements, refer to the
following documents that are available on the Guard Ring
Microchip website.
• “Using MPLAB® ICD 3 In-Circuit Debugger” Guard Trace
(poster) (DS51765)
• “Development Tools Design Advisory” (DS51764) Oscillator Pins
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide for MPLAB X IDE” (DS50002085)
• “Using MPLAB® REAL ICE™ In-Circuit Emulator”
(poster) (DS51749)

2.7 Oscillator Value Conditions on 2.9 Targeted Applications
Device Start-up • Power Factor Correction (PFC)
If the PLL of the target device is enabled and - Interleaved PFC
configured for the device start-up oscillator, the - Critical Conduction PFC
maximum oscillator source frequency must be limited - Bridgeless PFC
to 3 MHz < FIN < 5.5 MHz to comply with device PLL
• DC/DC Converters
start-up conditions. This means that if the external
oscillator frequency is outside this range, the - Buck, Boost, Forward, Flyback, Push-Pull
application must start up in the FRC mode first. The - Half/Full-Bridge
default PLL settings, after a POR with an oscillator - Phase-Shift Full-Bridge
frequency outside this range, will violate the device - Resonant Converters
operating speed. • DC/AC
Once the device powers up, the application firmware - Half/Full-Bridge Inverter
can initialize the PLL SFRs, CLKDIV and PLLFBD, to a
- Resonant Inverter
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching Examples of typical application connections are shown
must be enabled in the device Configuration Word. in Figure 2-4 through Figure 2-6.
2.8 Unused I/Os

Unused I/O pins should be configured as outputs and
driven to a logic low state.
Alternatively, connect a 1k to 10k resistor between VSS
and unused pins, and drive the output to logic low.
FIGURE 2-4: INTERLEAVED PFC
VOUT+
|VAC|
k1 k2
k4 VAC k3
VOUT-
FET FET
Driver Driver
PGA/ADC Channel PWM PGA/ADC PWM PGA/ADC ADC

Channel Channel Channel
dsPIC33EPXXXGS70X/80X
ADC Channel

FIGURE 2-5: PHASE-SHIFTED FULL-BRIDGE CONVERTER
VIN+
Gate 6
Gate 3
Gate 1
VOUT+
S1 S3
VOUT-
Gate 2
Gate 4 Gate 5
VIN-
Gate 5
Gate 6
FET k2
Driver
k1
Analog
Gate 1 Ground
FET PWM PGA/ADC PWM ADC

Driver Channel Channel
S1
Gate 3
FET dsPIC33EPXXXGS70X/80X
Driver
S3 PWM
Gate 2
Gate 4

FIGURE 2-6: OFF-LINE UPS
VDC
Push-Pull Converter Full-Bridge Inverter
VOUT+
VBAT +
VOUT-
GND
GND
FET FET FET FET FET FET

Driver Driver k2 k1 Driver Driver Driver Driver k4 k5
PWM PWM PGA/ADC ADC PWM PWM PWM PWM

or
Analog Comp.
k3 ADC
dsPIC33EPXXXGS70X/80X
ADC ADC
ADC PWM
FET
k6 Driver
Battery Charger

3.0 CPU 3.2 Instruction Set
The instruction set for dsPIC33EPXXXGS70X/80X
devices has two classes of instructions: the MCU class
of instructions and the DSP class of instructions. These
two instruction classes are seamlessly integrated into the
comprehensive reference source. To
architecture and execute from a single execution unit.
complement the information in this data
The instruction set includes many addressing modes and
sheet, refer to “dsPIC33E Enhanced
was designed for optimum C compiler efficiency.
CPU” (DS70005158) in the “dsPIC33/
PIC24 Family Reference Manual”, which
is available from the Microchip website 3.3 Data Space Addressing
(www.microchip.com). The base Data Space can be addressed as up to
2: Some registers and associated bits 4K words or 8 Kbytes, and is split into two blocks,
described in this section may not be referred to as X and Y data memory. Each memory block
available on all devices. Refer to has its own independent Address Generation Unit
Section 4.0 “Memory Organization” in (AGU). The MCU class of instructions operates solely
this data sheet for device-specific register through the X memory AGU, which accesses the entire
and bit information. memory map as one linear Data Space. Certain DSP
instructions operate through the X and Y AGUs to sup-
The dsPIC33EPXXXGS70X/80X family CPU has a 16-bit port dual operand reads, which splits the data address
(data) modified Harvard architecture with an enhanced space into two parts. The X and Y Data Space boundary
instruction set, including significant support for Digital is device-specific.
Signal Processing (DSP). The CPU has a 24-bit
instruction word with a variable length opcode field. The upper 32 Kbytes of the Data Space memory map
The Program Counter (PC) is 23 bits wide and can optionally be mapped into Program Space (PS) at
addresses up to 4M x 24 bits of user program memory any 16K program word boundary. The program-to-Data
space. Space mapping feature, known as Program Space
Visibility (PSV), lets any instruction access Program
An instruction prefetch mechanism helps maintain Space as if it were Data Space. Refer to “Data
throughput and provides predictable execution. Most Memory” (DS70595) in the “dsPIC33/PIC24 Family
instructions execute in a single-cycle effective execu- Reference Manual” for more details on PSV and table
tion rate, with the exception of instructions that change accesses.
the program flow, the double-word move (MOV.D)
instruction, PSV accesses and the table instructions. On dsPIC33EPXXXGS70X/80X devices, overhead-free
Overhead-free program loop constructs are supported circular buffers (Modulo Addressing) are supported in
using the DO and REPEAT instructions, both of which both X and Y address spaces. The Modulo Addressing
are interruptible at any point. removes the software boundary checking overhead for
DSP algorithms. The X AGU Circular Addressing can be
3.1 Registers used with any of the MCU class of instructions. The
X AGU also supports Bit-Reversed Addressing to
The dsPIC33EPXXXGS70X/80X devices have sixteen, greatly simplify input or output data re-ordering for
16-bit Working registers in the programmer’s model. Each radix-2 FFT algorithms.
of the Working registers can act as a Data, Address or
Address Offset register. The 16th Working register (W15) 3.4 Addressing Modes
operates as a Software Stack Pointer for interrupts and
calls. The CPU supports these addressing modes:
In addition, the dsPIC33EPXXXGS70X/80X devices • Inherent (no operand)
include four Alternate Working register sets which consist • Relative
of W0 through W14. The Alternate Working registers can • Literal
be made persistent to help reduce the saving and restor-
• Memory Direct
ing of register content during Interrupt Service Routines
(ISRs). The Alternate Working registers can be assigned • Register Direct
to a specific Interrupt Priority Level (IPL1 through IPL7) by • Register Indirect
configuring the CTXTx<2:0> bits in the FALTREG Config- Each instruction is associated with a predefined
uration register. The Alternate Working registers can also addressing mode group, depending upon its functional
be accessed manually by using the CTXTSWP instruction. requirements. As many as six addressing modes are
The CCTXI<2:0> and MCTXI<2:0> bits in the CTXTSTAT supported for each instruction.
register can be used to identify the current, and most
recent, manually selected Working register sets.

FIGURE 3-1: dsPIC33EPXXXGS70X/80X FAMILY CPU BLOCK DIAGRAM
X Address Bus
Y Data Bus
X Data Bus
16 16 16
16
Interrupt Data Latch Data Latch

PSV and Table
Controller Data Access Y Data X Data
8 16
24 Control Block RAM RAM
Address Address 16 24
24 Latch Latch
16 16
Y Address Bus
24
PCU PCH PCL X RAGU
Program Counter 16 X WAGU
Stack Loop
Control Control
Address Latch Logic Logic
Y AGU
Program Memory
16 EA MUX
Data Latch
16
ROM Latch
16 24
IR
24
Literal Data
16
16-Bit
Working Register Arrays 16
16 16
Divide
DSP Support
Engine
16-Bit ALU
Control Signals Instruction

Decode and 16 16
to Various Blocks
Control
Power, Reset Ports

and Oscillator
Modules
Peripheral
Modules

3.5 Programmer’s Model In addition to the registers contained in the programmer’s
model, the dsPIC33EPXXXGS70X/80X devices contain
The programmer’s model for the dsPIC33EPXXXGS70X/ control registers for Modulo Addressing, Bit-Reversed
80X family is shown in Figure 3-2. All registers in the Addressing and interrupts. These registers are
programmer’s model are memory-mapped and can be described in subsequent sections of this document.
manipulated directly by instructions. Table 3-1 lists a
description of each register. All registers associated with the programmer’s model
are memory-mapped, as shown in Table 3-1.
TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

Register(s) Name Description
W0 through W15(1) Working Register Array
W0 through W14(1) Alternate 1 Working Register Array
(1)
W0 through W14 Alternate 4 Working Register Array
ACCA, ACCB 40-Bit DSP Accumulators
PC 23-Bit Program Counter
SR ALU and DSP Engine STATUS Register
SPLIM Stack Pointer Limit Value Register
TBLPAG Table Memory Page Address Register
DSRPAG Extended Data Space (EDS) Read Page Register
RCOUNT REPEAT Loop Counter Register
DCOUNT DO Loop Counter Register
DOSTARTH(2), DOSTARTL(2) DO Loop Start Address Register (High and Low)
DOENDH, DOENDL DO Loop End Address Register (High and Low)
CORCON Contains DSP Engine, DO Loop Control and Trap Status bits
Note 1: Memory-mapped W0 through W14 represent the value of the register in the currently active CPU context.
2: The DOSTARTH and DOSTARTL registers are read-only.

FIGURE 3-2: PROGRAMMER’S MODEL
D15 D0
D15 D0
D15 D0
D15 D0
D15 D0
W0 (WREG) W0 W0 W0 W0
W0-W3 W1 W1 W1 W1 W1
W2 W2 W2 W2 W2
W3 W3 W3 W3 W3
W4 W4 W4 W4 W4
Alternate
DSP Operand W5 W5 W5 W5 W5 Working/Address
Registers W6 W6 W6 W6 W6 Registers
Working/Address
Registers W7 W7 W7 W7 W7
W8 W8 W8 W8 W8
DSP Address W9 W9 W9 W9 W9
Registers W10 W10 W10 W10 W10
W11 W11 W11 W11 W11
W12 W12 W12 W12 W12
W13 W13 W13 W13 W13
Frame Pointer/W14 W14 W14 W14 W14
Stack Pointer/W15 0
PUSH.S and POP.S Shadows

SPLIM 0 Stack Pointer Limit
Nested DO Stack
AD39 AD31 AD15 AD0
DSP ACCA
Accumulators ACCB
PC23 PC0
0 0 Program Counter
7 0
TBLPAG Data Table Page Address
9 0
DSRPAG X Data Space Read Page Address
15 0
RCOUNT REPEAT Loop Counter
15 0
DCOUNT DO Loop Counter and Stack
23 0
0 DOSTART 0 DO Loop Start Address and Stack
23 0
0 DOEND 0 DO Loop End Address and Stack
15 0
CORCON CPU Core Control Register
SRL
OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C STATUS Register

3.6 CPU Resources 3.6.1 KEY RESOURCES
Many useful resources are provided on the main prod- • “dsPIC33E Enhanced CPU” (DS70005158) in the
uct page of the Microchip website for the devices listed “dsPIC33/PIC24 Family Reference Manual”
in this data sheet. This product page contains the latest • Code Samples
updates and additional information. • Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools

3.7 CPU Control Registers
REGISTER 3-1: SR: CPU STATUS REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0
OA OB SA(3) SB(3) OAB SAB DA DC
bit 15 bit 8
R/W-0(2) R/W-0(2) R/W-0(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0

(1) (1)
IPL2 IPL1 IPL0(1) RA N OV Z C
bit 7 bit 0
Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’= Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 OA: Accumulator A Overflow Status bit

1 = Accumulator A has overflowed
0 = Accumulator A has not overflowed
bit 14 OB: Accumulator B Overflow Status bit
1 = Accumulator B has overflowed
0 = Accumulator B has not overflowed
bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(3)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(3)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulator A or B has overflowed
0 = Neither Accumulator A or B has overflowed
bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulator A or B is saturated or has been saturated at some time
0 = Neither Accumulator A or B is saturated
bit 9 DA: DO Loop Active bit
1 = DO loop is in progress
0 = DO loop is not in progress
bit 8 DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
2: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.

REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop is in progress
0 = REPEAT loop is not in progress
bit 3 N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the magnitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1 Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0 C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
IPL<3> = 1.
3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.

REGISTER 3-2: CORCON: CORE CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
VAR — US1 US0 EDT(1) DL2 DL1 DL0
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3(2) SFA RND IF
bit 7 bit 0

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 VAR: Variable Exception Processing Latency Control bit

1 = Variable exception processing latency is enabled
0 = Fixed exception processing latency is enabled
bit 14 Unimplemented: Read as ‘0’
bit 13-12 US<1:0>: DSP Multiply Unsigned/Signed Control bits
11 = Reserved
10 = DSP engine multiplies are mixed-sign
01 = DSP engine multiplies are unsigned
00 = DSP engine multiplies are signed
bit 11 EDT: Early DO Loop Termination Control bit(1)
1 = Terminates executing DO loop at the end of current loop iteration
0 = No effect
bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits
111 = Seven DO loops are active
•
•
•
001 = One DO loop is active
000 = Zero DO loops are active
bit 7 SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation is enabled
0 = Accumulator A saturation is disabled
bit 6 SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation is enabled
0 = Accumulator B saturation is disabled
bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data Space write saturation is enabled
0 = Data Space write saturation is disabled
bit 4 ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: This bit is always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

REGISTER 3-2: CORCON: CORE CONTROL REGISTER (CONTINUED)
bit 2 SFA: Stack Frame Active Status bit
1 = Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG
0 = Stack frame is not active; W14 and W15 address the base Data Space
bit 1 RND: Rounding Mode Select bit
1 = Biased (conventional) rounding is enabled
0 = Unbiased (convergent) rounding is enabled
bit 0 IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode is enabled for DSP multiply
0 = Fractional mode is enabled for DSP multiply
Note 1: This bit is always read as ‘0’.

REGISTER 3-3: CTXTSTAT: CPU W REGISTER CONTEXT STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
— — — — — CCTXI2 CCTXI1 CCTXI0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0

— — — — — MCTXI2 MCTXI1 MCTXI0
bit 7 bit 0
Legend:
bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 CCTXI<2:0>: Current (W Register) Context Identifier bits
111 = Reserved
•
•
•
101 = Reserved
100 = Alternate Working Register Set 4 is currently in use
000 = Default register set is currently in use
bit 2-0 MCTXI<2:0>: Manual (W Register) Context Identifier bits
111 = Reserved
•
•
•
101 = Reserved
100 = Alternate Working Register Set 4 was most recently manually selected
000 = Default register set was most recently manually selected

3.8 Arithmetic Logic Unit (ALU) 3.9 DSP Engine
The dsPIC33EPXXXGS70X/80X family ALU is 16 bits The DSP engine consists of a high-speed 17-bit x 17-bit
wide and is capable of addition, subtraction, bit shifts and multiplier, a 40-bit barrel shifter and a 40-bit adder/
logic operations. Unless otherwise mentioned, arithmetic subtracter (with two target accumulators, round and
operations are two’s complement in nature. Depending saturation logic).
on the operation, the ALU can affect the values of the The DSP engine can also perform inherent accumulator-
Carry (C), Zero (Z), Negative (N), Overflow (OV) and to-accumulator operations that require no additional
Digit Carry (DC) Status bits in the SR register. The C data. These instructions are, ADD, SUB and NEG.
and DC Status bits operate as Borrow and Digit Borrow
bits, respectively, for subtraction operations. The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
The ALU can perform 8-bit or 16-bit operations, below:
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W • Fractional or Integer DSP Multiply (IF)
register array or data memory, depending on the • Signed, Unsigned or Mixed-Sign DSP Multiply
addressing mode of the instruction. Likewise, output (USx)
data from the ALU can be written to the W register array • Conventional or Convergent Rounding (RND)
or a data memory location. • Automatic Saturation On/Off for ACCA (SATA)
Refer to the “16-Bit MCU and DSC Programmer’s • Automatic Saturation On/Off for ACCB (SATB)
Reference Manual” (DS70000157) for information on • Automatic Saturation On/Off for Writes to Data
the SR bits affected by each instruction. Memory (SATDW)
The core CPU incorporates hardware support for both • Accumulator Saturation mode Selection
multiplication and division. This includes a dedicated (ACCSAT)
hardware multiplier and support hardware for 16-bit
divisor division. TABLE 3-2: DSP INSTRUCTIONS
3.8.1 MULTIPLIER SUMMARY
Using the high-speed, 17-bit x 17-bit multiplier, the ALU Algebraic ACC
Instruction
supports unsigned, signed or mixed-sign operation in Operation Write-Back
several MCU Multiplication modes: CLR A=0 Yes
• 16-bit x 16-bit signed ED A = (x – y)2 No
• 16-bit x 16-bit unsigned EDAC A = A + (x – y) 2
No
• 16-bit signed x 5-bit (literal) unsigned MAC A = A + (x • y) Yes
• 16-bit signed x 16-bit unsigned MAC A=A+ x2 No
• 16-bit unsigned x 5-bit (literal) unsigned
MOVSAC No change in A Yes
• 16-bit unsigned x 16-bit signed
MPY A=x•y No
• 8-bit unsigned x 8-bit unsigned
MPY A = x2 No
3.8.2 DIVIDER MPY.N A=–x•y No
The divide block supports 32-bit/16-bit and 16-bit/16-bit MSC A=A–x•y Yes
signed and unsigned integer divide operations with the
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both
the 16-bit divisor (Wn) and any W register (aligned)
pair (W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.

4.0 MEMORY ORGANIZATION User application access to the program memory space
is restricted to the lower half of the address range
Note: This data sheet summarizes the features (0x000000 to 0x7FFFFF). The exception is the use of
of the dsPIC33EPXXXGS70X/80X family TBLRD operations, which use TBLPAG<7> to permit
of devices. It is not intended to be a access to calibration data and Device ID sections of the
comprehensive reference source. To com- configuration memory space.
plement the information in this data sheet, The program memory maps for dsPIC33EPXXXGS70X/
refer to “dsPIC33E/PIC24E Program 80X devices not operating in Dual Partition mode are
Memory” (DS70000613) in the “dsPIC33/ shown in Figure 4-1 and Figure 4-2.
PIC24 Family Reference Manual”, which is
available from the Microchip website The dsPIC33EPXXXGS70X/80X devices can operate
(www.microchip.com). in a Dual Partition Flash Program Memory mode,
where the user Program Flash Memory is arranged as
The dsPIC33EPXXXGS70X/80X family architecture two separate address spaces, one for each of the
features separate program and data memory spaces, Flash partitions. The Active Partition always starts at
and buses. This architecture also allows the direct address, 0x000000, and contains half of the available
access of program memory from the Data Space (DS) Flash memory (64k/128k, depends on device). The
during code execution. Inactive Partition always starts at address, 0x400000,
and implements the remaining half of Flash memory.
4.1 Program Address Space As shown in Figure 4-3 and Figure 4-4, the Active and
Inactive Partitions are identical, and both contain
The program address memory space of the unique copies of the Reset vector, Interrupt Vector
dsPIC33EPXXXGS70X/80X family devices is 4M Tables (IVT and AIVT if enabled) and the Flash
instructions. The space is addressable by a 24-bit Configuration Words.
value derived either from the 23-bit PC during program
execution, or from table operation or Data Space
remapping, as described in Section 4.9 “Interfacing
Program and Data Memory Spaces”.

4.2 Unique Device Identifier (UDID) The UDID is stored in five read-only locations,
located between 800F00h and 800F08h in the
All dsPIC33EPXXXGS70X/80X family devices are device configuration space. Table 4-1 lists the
individually encoded during final manufacturing with addresses of the identifier words and shows their
a Unique Device Identifier or UDID. This feature contents.
allows for manufacturing traceability of Microchip
Technology devices in applications where this is a
TABLE 4-1: UDID ADDRESSES
requirement. It may also be used by the application
manufacturer for any number of things that may Name Address Bits 23:16 Bits 15:8 Bits 7:0
require unique identification, such as:
UDID1 800F00 UDID Word 1
• Tracking the device UDID2 800F02 UDID Word 2
• Unique serial number
• Unique security key
The UDID comprises five 24-bit program words.
When taken together, these fields form a unique
120-bit identifier.
FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EP64GS70X/80X DEVICES
GOTO Instruction 0x000000

Reset Address 0x000002
0x000004
Interrupt Vector Table 0x0001FE
User Memory Space
0x000200
User Program
Flash Memory
(22,016 instructions) 0x00AF7E
0x00AF80
Device Configuration
0x00AFFE
0x00B000
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
Reserved
0x800EFE
0x800F00
UDID
0x800F08
Configuration Memory Space
0x800F0A
Reserved
0x800F7E
0x800F80
User OTP Memory
0x800FFC
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID 0xFF0002
0xFF0004
Reserved
0xFFFFFE
Note: Memory areas are not shown to scale.

GOTO Instruction 0x000000

Reset Address 0x000002
0x000004
Interrupt Vector Table 0x0001FE
User Memory Space

0x000200
User Program
Flash Memory
(44,032 instructions) 0x01577E
0x015780
0x0157FE
0x015800
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
Reserved
0x800F7E
0x800F80
User OTP Memory
0x800FFC
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID 0xFF0002
0xFF0004
Reserved
0xFFFFFE

(DUAL PARTITION)
0x000000
GOTO Instruction
0x000002
Reset Address
0x000004
Interrupt Vector Table
0x0001FE
0x000200
Active Program
Flash Memory
Active Partition
(11,008 instructions)
0x00577E
0x005780
0x0057FE
0x005800
User Memory Space
Unimplemented
(Read ‘0’s)
0x3FFFFE
0x400000
GOTO Instruction
0x400002
Reset Address
0x400004
0x4001FE
0x400200 Inactive Partition
Inactive Program
Flash Memory
0x40577E
0x405780
0x4057FE
Unimplemented 0x405800
(Read ‘0’s) 0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
Reserved
0x800F7E
0x800F80
User OTP Memory
0x800FFC
0x800100
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID
0xFF0002
0xFF0004
Reserved
0xFFFFFE

(DUAL PARTITION)
0x000000
GOTO Instruction
0x000002
Reset Address
0x000004
0x0001FE
Active Program 0x000200
Flash Memory
(22,016 instructions) Active Partition
0x00AB7E
0x00AB80
0x00ABFE
0x00AC00
User Memory Space
Unimplemented
(Read ‘0’s)
0x3FFFFE
0x400000
GOTO Instruction
0x400002
Reset Address
0x400004
0x4001FE
0x400200 Inactive Partition
Inactive Program
Flash Memory
0x40AB7E
0x40AB80
0x40ABFE
Unimplemented 0x40AC00
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
Reserved
0x800F7E
0x800F80
User OTP Memory
0x800FFC
0x800100
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
DEVID
0xFF0002
0xFF0004
Reserved
0xFFFFFE

4.2.1 PROGRAM MEMORY 4.2.2 INTERRUPT AND TRAP VECTORS
ORGANIZATION All dsPIC33EPXXXGS70X/80X family devices reserve
The program memory space is organized in word- the addresses between 0x000000 and 0x000200 for
addressable blocks. Although it is treated as 24 bits hard-coded program execution vectors. A hardware
wide, it is more appropriate to think of each address of Reset vector is provided to redirect code execution
the program memory as a lower and upper word, with from the default value of the PC on device Reset to the
the upper byte of the upper word being unimplemented. actual start of code. A GOTO instruction is programmed
The lower word always has an even address, while the by the user application at address, 0x000000, of Flash
upper word has an odd address (Figure 4-5). memory, with the actual address for the start of code at
address, 0x000002, of Flash memory.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or A more detailed discussion of the Interrupt Vector
decremented by two, during code execution. This Tables (IVTs) is provided in Section 7.1 “Interrupt
arrangement provides compatibility with data memory Vector Table”.
space addressing and makes data in the program
memory space accessible.
FIGURE 4-5: PROGRAM MEMORY ORGANIZATION
msw most significant word least significant word PC Address

Address (lsw Address)
23 16 8 0
0x000001 00000000 0x000000
0x000003 00000000 0x000002
0x000005 00000000 0x000004
0x000007 00000000 0x000006
Program Memory
Instruction Width
‘Phantom’ Byte
(read as ‘0’)

4.3 Data Address Space All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
The dsPIC33EPXXXGS70X/80X family CPU has a care must be taken when mixing byte and word
separate 16-bit wide data memory space. The Data operations, or translating from 8-bit MCU code. If a
Space is accessed using separate Address Generation misaligned read or write is attempted, an address error
Units (AGUs) for read and write operations. The data trap is generated. If the error occurred on a read, the
memory map is shown in Figure 4-6. instruction underway is completed. If the error occurred
All Effective Addresses (EAs) in the data memory space on a write, the instruction is executed but the write does
are 16 bits wide and point to bytes within the Data not occur. In either case, a trap is then executed,
Space. This arrangement gives a base Data Space allowing the system and/or user application to examine
address range of 64 Kbytes or 32K words. the machine state prior to execution of the address
Fault.
The lower half of the data memory space (i.e., when
EA<15> = 0) is used for implemented memory All byte loads into any W register are loaded into the
addresses, while the upper half (EA<15> = 1) is LSB; the MSB is not modified.
reserved for the Program Space Visibility (PSV). A Sign-Extend (SE) instruction is provided to allow user
dsPIC33EPXXXGS70X/80X family devices implement applications to translate 8-bit signed data to 16-bit
up to 12 Kbytes of data memory. If an EA points to a signed values. Alternatively, for 16-bit unsigned data,
location outside of this area, an all-zero word or byte is user applications can clear the MSB of any W register
returned. by executing a Zero-Extend (ZE) instruction on the
appropriate address.
4.3.1 DATA SPACE WIDTH
4.3.3 SFR SPACE
The data memory space is organized in byte-
addressable, 16-bit wide blocks. Data is aligned in data The first 4 Kbytes of the Near Data Space, from
memory and registers as 16-bit words, but all Data 0x0000 to 0x0FFF, is primarily occupied by Special
Space EAs resolve to bytes. The Least Significant Function Registers (SFRs). These are used by the
Bytes (LSBs) of each word have even addresses, while dsPIC33EPXXXGS70X/80X family core and peripheral
the Most Significant Bytes (MSBs) have odd modules for controlling the operation of the device.
addresses. SFRs are distributed among the modules that they
control and are generally grouped together by module.
4.3.2 DATA MEMORY ORGANIZATION Much of the SFR space contains unused addresses;
AND ALIGNMENT these are read as ‘0’.
To maintain backward compatibility with PIC ® MCU
Note: The actual set of peripheral features and
devices and improve Data Space memory usage
interrupts varies by the device. Refer to
efficiency, the dsPIC33EPXXXGS70X/80X family
the corresponding device tables and
instruction set supports both word and byte operations.
pinout diagrams for device-specific
As a consequence of byte accessibility, all Effective
information.
Address calculations are internally scaled to step
through word-aligned memory. For example, the core
4.3.4 NEAR DATA SPACE
recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] results in a value of Ws + 1 The 8-Kbyte area, between 0x0000 and 0x1FFF, is
for byte operations and Ws + 2 for word operations. referred to as the Near Data Space. Locations in this
space are directly addressable through a 13-bit absolute
A data byte read, reads the complete word that
address field within all memory direct instructions. Addi-
contains the byte, using the LSb of any EA to determine
tionally, the whole Data Space is addressable using MOV
which byte to select. The selected byte is placed onto
instructions, which support Memory Direct Addressing
the LSB of the data path. That is, data memory and
mode with a 16-bit address field, or by using Indirect
registers are organized as two parallel, byte-wide
Addressing mode using a Working register as an
entities with shared (word) address decode, but
Address Pointer.
separate write lines. Data byte writes only write to the
corresponding side of the array or register that matches
the byte address.

FIGURE 4-6: DATA MEMORY MAP FOR dsPIC33EP64GS70X/80X DEVICES
MSB LSB
Address 16 Bits Address
MSB LSB
0x0001 0x0000
4-Kbyte
SFR Space
SFR Space 0x0FFE
0x0FFF
0x1001 0x1000
8-Kbyte
Near
X Data RAM (X) Data Space
8-Kbyte 0x1FFF 0x1FFE

SRAM Space 0x2001 0x2000
Y Data RAM (Y)
0x2FFF 0x2FFE
0x3001 0x3000
0x8001 0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF 0xFFFE

4.3.5 X AND Y DATA SPACES 4.4 Memory Resources
The dsPIC33EPXXXGS70X/80X core has two Data Many useful resources are provided on the main
Spaces, X and Y. These Data Spaces can be considered product page of the Microchip website for the devices
either separate (for some DSP instructions) or as one listed in this data sheet. This product page contains the
unified linear address range (for MCU instructions). The latest updates and additional information.
Data Spaces are accessed using two Address Genera-
tion Units (AGUs) and separate data paths. This feature 4.4.1 KEY RESOURCES
allows certain instructions to concurrently fetch two
• “dsPIC33E/PIC24E Program Memory”
words from RAM, thereby enabling efficient execution of
(DS70000613) in the “dsPIC33/PIC24 Family
DSP algorithms, such as Finite Impulse Response (FIR)
Reference Manual”
filtering and Fast Fourier Transform (FFT).
• Code Samples
The X Data Space is used by all instructions and
• Application Notes
supports all addressing modes. X Data Space has
separate read and write data buses. The X read data • Software Libraries
bus is the read data path for all instructions that view • Webinars
Data Space as combined X and Y address space. It is • All Related “dsPIC33/PIC24 Family Reference
also the X data prefetch path for the dual operand DSP Manual” Sections
instructions (MAC class). • Development Tools
The Y Data Space is used in concert with the X Data
Space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide
two concurrent data read paths.
Both the X and Y Data Spaces support Modulo Address-
ing mode for all instructions, subject to addressing mode
restrictions. Bit-Reversed Addressing mode is only
supported for writes to X Data Space.
All data memory writes, including in DSP instructions,
view Data Space as combined X and Y address space.
The boundary between the X and Y Data Spaces is
device-dependent and is not user-programmable.

4.5 Special Function Register Maps
TABLE 4-2: SFR BLOCK 000h

Register Address All Resets Register Address All Resets Register Address All Resets
Core WREG14 01C 0000000000000000 DOSTARTL 03A xxxxxxxxxxxxxxx0

WREG0 000 0000000000000000 WREG15 01E 0000100000000000 DOSTARTH 03C 0000000000xxxxxx
WREG1 002 0000000000000000 SPLIM 020 xxxxxxxxxxxxxxx0 DOENDL 03E xxxxxxxxxxxxxxx0
WREG2 004 0000000000000000 ACCAL 022 xxxxxxxxxxxxxxxx DOENDH 040 0000000000xxxxxx
WREG3 006 0000000000000000 ACCAH 024 xxxxxxxxxxxxxxxx SR 042 0000000000000000
WREG4 008 0000000000000000 ACCAU 026 00000000xxxxxxxx CORCON 044 0000000000100000
WREG5 00A 0000000000000000 ACCBL 028 xxxxxxxxxxxxxxxx MODCON 046 0000000000000000
WREG6 00C 0000000000000000 ACCBH 02A xxxxxxxxxxxxxxxx XMODSRT 048 xxxxxxxxxxxxxxx0
WREG7 00E 0000000000000000 ACCBU 02C 00000000xxxxxxxx XMODEND 04A xxxxxxxxxxxxxxx1
WREG8 010 0000000000000000 PCL 02E 0000000000000000 YMODSRT 04C xxxxxxxxxxxxxxx0
WREG9 012 0000000000000000 PCH 030 0000000000000000 YMODEND 04E xxxxxxxxxxxxxxx1
WREG10 014 0000000000000000 DSRPAG 032 0000000000000001 XBREV 050 xxxxxxxxxxxxxxxx
WREG11 016 0000000000000000 DSWPAG 034 0000000000000001 DISICNT 052 00xxxxxxxxxxxxxx
WREG12 018 0000000000000000 RCOUNT 036 xxxxxxxxxxxxxxxx TBLPAG 054 00000000xxxxxxxx
WREG13 01A 0000000000000000 DCOUNT 038 xxxxxxxxxxxxxxxx CTXTSTAT 05A 0000000000000000
Legend: x = unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.

Timers TMR5HLD 116 xxxxxxxxxxxxxxxx IC2CON2 14A 0000000000001101

TMR1 100 xxxxxxxxxxxxxxxx TMR5 118 xxxxxxxxxxxxxxxx IC2BUF 14C xxxxxxxxxxxxxxxx
PR1 102 1111111111111111 PR4 11A 1111111111111111 IC2TMR 14E 0000000000000000
T1CON 104 0000000000000000 PR5 11C 1111111111111111 IC3CON1 150 0000000000000000
TMR2 106 xxxxxxxxxxxxxxxx T4CON 11E 0000000000000000 IC3CON2 152 0000000000001101
TMR3HLD 108 xxxxxxxxxxxxxxxx T5CON 120 0000000000000000 IC3BUF 154 xxxxxxxxxxxxxxxx
TMR3 10A xxxxxxxxxxxxxxxx Input Capture IC3TMR 156 0000000000000000
PR2 10C 1111111111111111 IC1CON1 140 0000000000000000 IC4CON1 158 0000000000000000
PR3 10E 1111111111111111 IC1CON2 142 0000000000001101 IC4CON2 15A 0000000000001101
T2CON 110 0000000000000000 IC1BUF 144 xxxxxxxxxxxxxxxx IC4BUF 15C xxxxxxxxxxxxxxxx
T3CON 112 0000000000000000 IC1TMR 146 0000000000000000 IC4TMR 15E 0000000000000000
TMR4 114 xxxxxxxxxxxxxxxx IC2CON1 148 0000000000000000

I2C1 and I2C2 U1STA 222 0000000010010000 SPI1BRGH 252 0000000000000000

I2C1CONL 200 0001000000000000 U1TXREG 224 0000000xxxxxxxxx SPI1IMSKL 254 0000000000000000
I2C1CONH 202 0000000000000000 U1RXREG 226 0000000000000000 SPI1IMSKH 256 0000000000000000
I2C1STAT 204 0000000000000000 U1BRG 228 0000000000000000 SPI1URDTL 258 0000000000000000
I2C1ADD 206 0000000000000000 U2MODE 230 0000000000000000 SPI1URDTH 25A 0000000000000000
I2C1MSK 208 0000000000000000 U2STA 232 0000000010010000 SPI2CON1L 260 0000000000000000
I2C1BRG 20A 0000000000000000 U2TXREG 234 0000000xxxxxxxxx SPI2CON1H 262 0000000000000000
I2C1TRN 20C 0000000011111111 U2RXREG 236 0000000000000000 SPI2CON2L 264 0000000000000000
I2C1RCV 20E 0000000000000000 U2BRG 238 0000000000000000 SPI2CON2H 266 0000000000000000
I2C2CON1 210 0001000000000000 SPI SPI2STATL 268 0000000000101000
I2C2CON2 212 0000000000000000 SPI1CON1L 240 0000000000000000 SPI2STATH 26A 0000000000000000
I2C2STAT 214 0000000000000000 SPI1CON1H 242 0000000000000000 SPI2BUFL 26C 0000000000000000
I2C2ADD 216 0000000000000000 SPI1CON2L 244 0000000000000000 SPI2BUFH 26E 0000000000000000
I2C2MSK 218 0000000000000000 SPI1CON2H 246 0000000000000000 SPI3STAT 270 000xxxxxxxxxxxxx
I2C2BRG 21A 0000000000000000 SPI1STATL 248 0000000000101000 SPI2BRGH 272 0000000000000000
I2C2TRN 21C 0000000011111111 SPI1STATH 24A 0000000000000000 SPI2IMSKL 274 0000000000000000
I2C2RCV 21E 0000000000000000 SPI1BUFL 24C 0000000000000000 SPI2IMSKH 276 0000000000000000
UART1 and UART2 SPI1BUFH 24E 0000000000000000 SPI2URDTL 278 0000000000000000
U1MODE 220 0000000000000000 SPI1BRGL 250 000xxxxxxxxxxxxx SPI2URDTH 27A 0000000000000000

ADC ADCMP0ENH 33A 0000000000000000 ADTRIG4L 390 0000000000000000

ADCON1L 300 0000000000000000 ADCMP0LO 33C 0000000000000000 ADTRIG4H 392 0000000000000000
ADCON1H 302 0000000001100000 ADCMP0HI 33E 0000000000000000 ADCMP0CON 3A0 0000000000000000
ADCON2L 304 0000000000000000 ADCMP1ENL 340 0000000000000000 ADCMP1CON 3A4 0000000000000000
ADCON2H 306 0000000000000000 ADCMP1ENH 342 0000000000000000 ADBASE 3C0 0000000000000000
ADCON3L 308 0000000000000000 ADCMP1LO 344 0000000000000000 ADLVLTRGL 3D0 0000000000000000
ADCON3H 30A 0000000000000000 ADCMP1HI 346 0000000000000000 ADLVLTRGH 3D2 0000000000000000
ADCON4L 30C 0000000000000000 ADFL0DAT 368 0000000000000000 ADCORE0L 3D4 0000000000000000
ADCON4H 30E 0000000000000000 ADFL0CON 36A 0000000000000000 ADCORE0H 3D6 0000001100000000
ADMOD0L 310 0000000000000000 ADFL1DAT 36C 0000000000000000 ADCORE1L 3D8 0000000000000000
ADMOD0H 312 0000000000000000 ADFL1CON 36E 0000000000000000 ADCORE1H 3DA 0000001100000000
ADMOD1L 314 0000000000000000 ADTRIG0L 380 0000000000000000 ADCORE2L 3DC 0000000000000000
ADIEL 320 0000000000000000 ADTRIG0H 382 0000000000000000 ADCORE2H 3DE 0000001100000000
ADIEH 322 0000000000000000 ADTRIG1L 384 0000000000000000 ADCORE3L 3E0 0000000000000000
ADCSS1L 328 0000000000000000 ADTRIG1H 386 0000000000000000 ADCORE3H 3E2 0000001100000000
ADCSS1H 32A 0000000000000000 ADTRIG2L 388 0000000000000000 ADEIEL 3F0 0000000000000000
ADSTATL 330 0000000000000000 ADTRIG2H 38A 0000000000000000 ADEIEH 3F2 0000000000000000
ADSTATH 332 0000000000000000 ADTRIG3L 38C 0000000000000000 ADEISTATL 3F8 0000000000000000
ADCMP0ENL 338 0000000000000000 ADTRIG3H 38E 0000000000000000 ADEISTATH 3FA 0000000000000000

ADC (Continued) C1FCTRL 486 0000000000000000 C1RXM2EID 4BA xxxxxxxxxxxxxxxx

ADCON5L 400 0000000000000000 C1FIFO 488 0000000000000000 C1RXF1SID 4C4 xxxxxxxxxxxxxxxx
ADCON5H 402 0000000000000000 C1INTF 48A 0000000000000000 C1RXF1EID 4C6 xxxxxxxxxxxxxxxx
ADCAL0L 404 0000000000000000 C1INTE 48C 0000000000000000 C1RXF2SID 4C8 xxxxxxxxxxxxxxxx
ADCAL0H 406 0000000000000000 C1EC 48E 0000000000000000 C1RXF2EID 4CA xxxxxxxxxxxxxxxx
ADCAL1H 40A 0000000000000000 C1CFG1 490 0000000000000000 C1RXF3SID 4CC xxxxxxxxxxxxxxxx
ADCBUF0 40C 0000000000000000 C1CFG2 492 0x000xxxxxxxxxxx C1RXF3EID 4CE xxxxxxxxxxxxxxxx
ADCBUF1 40E 0000000000000000 C1FEN1 494 1111111111111111 C1RXF4SID 4D0 xxxxxxxxxxxxxxxx
ADCBUF2 410 0000000000000000 C1FMSKSEL1 498 0000000000000000 C1RXF4EID 4D2 xxxxxxxxxxxxxxxx
ADCBUF3 412 0000000000000000 C1FMSKSEL2 49A 0000000000000000 C1RXF5SID 4D4 xxxxxxxxxxxxxxxx
ADCBUF4 414 0000000000000000 CAN (WIN (C1CTRL<0>) = 0) C1RXF5EID 4D6 xxxxxxxxxxxxxxxx
ADCBUF5 416 0000000000000000 C1RXFUL1 4A0 0000000000000000 C1RXF6SID 4D8 xxxxxxxxxxxxxxxx
ADCBUF6 418 0000000000000000 C1RXFUL2 4A2 0000000000000000 C1RXF6EID 4DA xxxxxxxxxxxxxxxx
ADCBUF7 41A 0000000000000000 C1RXOVF1 4A8 0000000000000000 C1RXF7SID 4DC xxxxxxxxxxxxxxxx
ADCBUF8 41C 0000000000000000 C1RXOVF2 4AA 0000000000000000 C1RXF7EID 4DE xxxxxxxxxxxxxxxx
ADCBUF9 41E 0000000000000000 C1TR01CON 4B0 0000000000000000 C1RXF8SID 4E0 xxxxxxxxxxxxxxxx
ADCBUF10 420 0000000000000000 C1TR23CON 4B2 0000000000000000 C1RXF8EID 4E2 xxxxxxxxxxxxxxxx
ADCBUF11 422 0000000000000000 C1TR45CON 4B4 0000000000000000 C1RXF9SID 4E4 xxxxxxxxxxxxxxxx
ADCBUF12 424 0000000000000000 C1TR67CON 4B6 xxxxxxxxxxxxxxxx C1RXF9EID 4E6 xxxxxxxxxxxxxxxx
ADCBUF13 426 0000000000000000 C1RXD 4C0 xxxxxxxxxxxxxxxx C1RXF10SID 4E8 xxxxxxxxxxxxxxxx
ADCBUF14 428 0000000000000000 C1TXD 4C2 xxxxxxxxxxxxxxxx C1RXF10EID 4EA xxxxxxxxxxxxxxxx
ADCBUF15 42A 0000000000000000 CAN (WIN (C1CTR1<0>) = 1) C1RXF11SID 4EC xxxxxxxxxxxxxxxx
ADCBUF16 42C 0000000000000000 C1BUFPNT1 4A0 0000000000000000 C1RXF11EID 4EE xxxxxxxxxxxxxxxx
ADCBUF17 42E 0000000000000000 C1BUFPNT2 4A2 0000000000000000 C1RXF12SID 4F0 xxxxxxxxxxxxxxxx
ADCBUF18 430 0000000000000000 C1BUFPNT3 4A4 0000000000000000 C1RXF12EID 4F2 xxxxxxxxxxxxxxxx
ADCBUF19 432 0000000000000000 C1BUFPNT4 4A6 0000000000000000 C1RXF13SID 4F4 xxxxxxxxxxxxxxxx
ADCBUF20 434 0000000000000000 C1RXM0SID 4B0 xxxxxxxxxxxxxxxx C1RXF13EID 4F6 xxxxxxxxxxxxxxxx
ADCBUF21 436 0000000000000000 C1RXM0EID 4B2 xxxxxxxxxxxxxxxx C1RXF14SID 4F8 xxxxxxxxxxxxxxxx
CAN (WIN (C1CTRL<0>) = 0 OR 1) C1RXM1SID 4B4 xxxxxxxxxxxxxxxx C1RXF14EID 4FA xxxxxxxxxxxxxxxx
C1CTRL1 480 000010010000000 C1RXM1EID 4B6 xxxxxxxxxxxxxxxx C1RXF15SID 4FC xxxxxxxxxxxxxxxx
C1CTRL2 482 000000000000000 CAN C1RXF15EID 4FE xxxxxxxxxxxxxxxx
C1VEC 484 000000001000000 C1RXM2SID 4B8 xxxxxxxxxxxxxxxx

PGA PGA2CAL 50A 0000000000000000 CMP2DAC 546 0000000000000000

ISRCCON 500 0000000000000000 Comparators CMP3CON 548 0000000000000000
PGA1CON 504 0000000000000000 CMP1CON 540 0000000000000000 CMP3DAC 54A 0000000000000000
PGA1CAL 506 0000000000000000 CMP1DAC 542 0000000000000000 CMP4CON 54C 0000000000000000
PGA2CON 508 0000000000000000 CMP2CON 544 0000000000000000 CMP4DAC 54E 0000000000000000

SPI RPOR8 678 0000000000000000 RPINR7 6AE 0000000000000000

SPI3CON1L 600 0000000000000000 RPOR9 67A 0000000000000000 RPINR8 6B0 0000000000000000
SPI3CON1H 602 0000000000000000 RPOR10 67C 0000000000000000 RPINR11 6B6 0000000000000000
SPI3CON2L 604 0000000000000000 RPOR11 67E 0000000000000000 RPINR12 6B8 0000000000000000
SPI3CON2H 606 0000000000000000 RPOR12 680 0000000000000000 RPINR13 6BA 0000000000000000
SPI3STATL 608 0000000000101000 RPOR13 682 0000000000000000 RPINR18 6C4 0000000000000000
SPI3STATH 60A 0000000000000000 RPOR14 684 0000000000000000 RPINR19 6C6 0000000000000000
SPI3BUFL 60C 0000000000000000 RPOR15 686 0000000000000000 RPINR20 6C8 0000000000000000
SPI3BUFH 60E 0000000000000000 RPOR17 68A 0000000000000000 RPINR21 6CA 0000000000000000
SPI3BRGL 610 000xxxxxxxxxxxxx RPOR18 68C 0000000000000000 RPINR22 6CC 0000000000000000
SPI3BRGH 612 0000000000000000 RPOR19 68E 0000000000000000 RPINR23 6CE 0000000000000000
SPI3IMSKL 614 0000000000000000 RPOR20 690 0000000000000000 RPINR26 6D4 0000000000000000
SPI3IMSKH 616 0000000000000000 RPOR21 692 0000000000000000 RPINR29 6DA 0000000000000000
SPI3URDTL 618 0000000000000000 RPOR22 694 0000000000000000 RPINR30 6DC 0000000000000000
SPI3URDTH 61A 0000000000000000 RPOR23 696 0000000000000000 RPINR37 6EA 0000000000000000
RPOR0 668 0000000000000000 RPOR24 698 0000000000000000 RPINR38 6EC 0000000000000000
RPOR1 66A 0000000000000000 RPOR25 69A 0000000000000000 RPINR42 6F4 0000000000000000
RPOR2 66C 0000000000000000 RPOR26 69C 0000000000000000 RPINR43 6F6 0000000000000000
RPOR3 66E 0000000000000000 RPINR0 6A0 0000000000000000 RPINR45 6FA 0000000000000000
RPOR4 670 0000000000000000 RPINR1 6A2 0000000000000000 RPINR46 6FC 0000000000000000
RPOR5 672 0000000000000000 RPINR2 6A4 0000000000000000
RPOR6 674 0000000000000000 RPINR3 6A6 0000000000000000

NVM C2INTF 78A 0000000000000000 C2RXF1SID 7C4 xxxxxxxxxxxxxxxx

NVMCON 728 0000000000000000 C2INTE 78C 0000000000000000 C2RXF1EID 7C6 xxxxxxxxxxxxxxxx
NVMADR 72A 0000000000000000 C2EC 78E 0000000000000000 C2RXF2SID 7C8 xxxxxxxxxxxxxxxx
NVMADRU 72C 0000000000000000 C2CFG1 790 0000000000000000 C2RXF2EID 7CA xxxxxxxxxxxxxxxx
NVMKEY 72E 0000000000000000 C2CFG2 792 0x000xxxxxxxxxxx C2RXF3SID 7CC xxxxxxxxxxxxxxxx
NVMSRCADR 730 0000000000000000 C2FEN1 794 1111111111111111 C2RXF3EID 7CE xxxxxxxxxxxxxxxx
NVMSRCADRH 732 0000000000000000 C2FMSKSEL1 798 0000000000000000 C2RXF4SID 7D0 xxxxxxxxxxxxxxxx
System Control C2FMSKSEL2 79A 0000000000000000 C2RXF4EID 7D2 xxxxxxxxxxxxxxxx
RCON 740 0x00x0x01x0xxxxx CAN (WIN (C1CTR1<0>) = 0) C2RXF5SID 7D4 xxxxxxxxxxxxxxxx
OSCCON 742 0000000000000000 C2RXFUL1 7A0 0000000000000000 C2RXF5EID 7D6 xxxxxxxxxxxxxxxx
CLKDIV 744 0000000000000000 C2RXFUL2 7A2 0000000000000000 C2RXF6SID 7D8 xxxxxxxxxxxxxxxx
PLLFBD 746 0000000000000000 C2RXOVF1 7A8 0000000000000000 C2RXF6EID 7DA xxxxxxxxxxxxxxxx
OSCTUN 748 0000000000000000 C2RXOVF2 7AA 0000000000000000 C2RXF7SID 7DC xxxxxxxxxxxxxxxx
LFSR 74C 0000000000000000 C2TR01CON 7B0 0000000000000000 C2RXF7EID 7DE xxxxxxxxxxxxxxxx
REFOCON 74E 0000000000000000 C2TR23CON 7B2 0000000000000000 C2RXF8SID 7E0 xxxxxxxxxxxxxxxx
ACLKCON 750 0000000001000000 C2TR45CON 7B4 0000000000000000 C2RXF8EID 7E2 xxxxxxxxxxxxxxxx
PMD C2TR67CON 7B6 xxxxxxxxxxxxxxxx C2RXF9SID 7E4 xxxxxxxxxxxxxxxx
PMD1 760 0000000000000000 C2RXD 7C0 xxxxxxxxxxxxxxxx C2RXF9EID 7E6 xxxxxxxxxxxxxxxx
PMD2 762 0000000000000000 C2TXD 7C2 xxxxxxxxxxxxxxxx C2RXF10SID 7E8 xxxxxxxxxxxxxxxx
PMD3 764 0000000000000000 CAN (WIN (C1CTR1<0>) = 1) C2RXF10EID 7EA xxxxxxxxxxxxxxxx
PMD4 766 0000000000000000 C2BUFPNT1 7A0 0000000000000000 C2RXF11SID 7EC xxxxxxxxxxxxxxxx
PMD6 76A 0000000000000000 C2BUFPNT2 7A2 0000000000000000 C2RXF11EID 7EE xxxxxxxxxxxxxxxx
PMD7 76C 0000000000000000 C2BUFPNT3 7A4 0000000000000000 C2RXF12SID 7F0 xxxxxxxxxxxxxxxx
PMD8 76E 0000000000000000 C2BUFPNT4 7A6 0000000000000000 C2RXF12EID 7F2 xxxxxxxxxxxxxxxx
CAN (WIN (C1CTR1<0>) = 0 or 1) C2RXM0SID 7B0 xxxxxxxxxxxxxxxx C2RXF13SID 7F4 xxxxxxxxxxxxxxxx
C2CTRL1 780 0000010010000000 C2RXM0EID 7B2 xxxxxxxxxxxxxxxx C2RXF13EID 7F6 xxxxxxxxxxxxxxxx
C2CTRL2 782 0000000000000000 C2RXM1SID 7B4 xxxxxxxxxxxxxxxx C2RXF14SID 7F8 xxxxxxxxxxxxxxxx
C2VEC 784 0000000001000000 C2RXM1EID 7B6 xxxxxxxxxxxxxxxx C2RXF14EID 7FA xxxxxxxxxxxxxxxx
C2FCTRL 786 0000000000000000 C2RXM2SID 7B8 xxxxxxxxxxxxxxxx C2RXF15SID 7FC xxxxxxxxxxxxxxxx
C2FIFO 788 0000000000000000 C2RXM2EID 7BA xxxxxxxxxxxxxxxx C2RXF15EID 7FE xxxxxxxxxxxxxxxx

Interrupt Controller IEC9 832 0000000000000000 IPC26 874 0000000001000100

IFS0 800 0000000000000000 IEC10 834 0000000000000000 IPC27 876 0100010000000000
IFS1 802 0000000000000000 IEC11 836 0000000000000000 IPC28 878 0100010001000100
IFS2 804 0000000000000000 IPC0 840 0100010001000100 IPC29 87A 0000000001000100
IFS3 806 0000000000000000 IPC1 842 0100010001000000 IPC35 886 0100010000000000
IFS4 808 0000000000000000 IPC2 844 0100010001000100 IPC36 888 0000000000000000
IFS5 80A 0000000000000000 IPC3 846 0100000001000100 IPC37 88A 0100000000000000
IFS6 80C 0000000000000000 IPC4 848 0100010001000100 IPC38 88C 0100010001000100
IFS7 80E 0000000000000000 IPC5 84A 0000000000000100 IPC39 88E 0100010001000100
IFS8 810 0000000000000000 IPC6 84C 0100010001000000 IPC40 890 0100010001000100
IFS9 812 0000000000000000 IPC7 84E 0100010001000100 IPC41 892 0100010001000100
IFS10 814 0000000000000000 IPC8 850 0000000001000100 IPC42 894 0000000001000100
IFS11 816 0000000000000000 IPC9 852 0000010001000000 IPC43 896 0000010001000000
IEC0 820 0000000000000000 IPC11 856 0000000000000000 IPC44 898 0100010001000000
IEC1 822 0000000000000000 IPC12 858 0000010001000000 IPC45 89A 0000000000000100
IEC2 824 0000000000000000 IPC13 85A 0000010000000000 IPC46 89C 0100010000000000
IEC3 826 0000000000000000 IPC14 85C 0000000001000000 IPC47 89E 0000010001000100
IEC4 828 0000000000000000 IPC16 860 0000010001000000 INTCON1 8C0 0000000000000000
IEC5 82A 0000000000000000 IPC18 864 0000000001000000 INTCON2 8C2 0000000000000000
IEC6 82C 0000000000000000 IPC23 86E 0100010000000000 INTCON3 8C4 0000000000000000
IEC7 82E 0000000000000000 IPC24 870 0000010001000100 INTCON4 8C6 0000000000000000
IEC8 830 0000000000000000 IPC25 872 0100000000000000 INTTREG 8C8 0000000000000000

Output Compare OC3R 91A xxxxxxxxxxxxxxxx CLC2CONH 9CE 0000000000000000

OC1CON1 900 0000000000000000 OC3TMR 91C 0000000000000000 CLC2SEL 9D0 0000000000000000
OC1CON2 902 0000000000001100 OC4CON1 91E 0000000000000000 CLC2GLSL 9D4 0000000000000000
OC1RS 904 xxxxxxxxxxxxxxxx OC4CON2 920 0000000000001100 CLC2GLSH 9D6 0000000000000000
OC1R 906 xxxxxxxxxxxxxxxx OC4RS 922 xxxxxxxxxxxxxxxx CLC3CONL 9D8 0000000000000000
OC1TMR 908 0000000000000000 OC4R 924 xxxxxxxxxxxxxxxx CLC3CONH 9DA 0000000000000000
OC2CON1 90A 0000000000000000 OC4TMR 926 0000000000000000 CLC3SEL 9DC 0000000000000000
OC2CON2 90C 0000000000001100 CLC CLC3GLSL 9E0 0000000000000000
OC2RS 90E xxxxxxxxxxxxxxxx CLC1CONL 9C0 0000000000000000 CLC3GLSH 9E2 0000000000000000
OC2R 910 xxxxxxxxxxxxxxxx CLC1CONH 9C2 0000000000000000 CLC4CONL 9E4 0000000000000000
OC2TMR 912 0000000000000000 CLC1SEL 9C4 0000000000000000 CLC4CONH 9E6 0000000000000000
OC3CON1 914 0000000000000000 CLC1GLSL 9C8 0000000000000000 CLC4SEL 9E8 0000000000000000
OC3CON2 916 0000000000001100 CLC1GLSH 9CA 0000000000000000 CLC4GLSL 9EC 0000000000000000
OC3RS 918 xxxxxxxxxxxxxxxx CLC2CONL 9CC 0000000000000000 CLC4GLSH 9EE 0000000000000000

TABLE 4-12: SFR BLOCK A00h
PTG PTGADJ AD2 0000000000000000 PTGQUE7 AE6 xxxxxxxxxxxxxxxx

PTGCST AC0 0000000000000000 PTGL0 AD4 0000000000000000 PTGQUE8 AE8 xxxxxxxxxxxxxxxx
PTGCON AC2 0000000000000000 PTGQPTR AD6 0000000000000000 PTGQUE9 AEA xxxxxxxxxxxxxxxx
PTGBTE AC4 0000000000000000 PTGQUE0 AD8 xxxxxxxxxxxxxxxx PTGQUE10 AEC xxxxxxxxxxxxxxxx
PTGHOLD AC6 0000000000000000 PTGQUE1 ADA xxxxxxxxxxxxxxxx PTGQUE11 AEE xxxxxxxxxxxxxxxx
PTGT0LIM AC8 0000000000000000 PTGQUE2 ADC xxxxxxxxxxxxxxxx PTGQUE12 AF0 xxxxxxxxxxxxxxxx
PTGT1LIM ACA 0000000000000000 PTGQUE3 ADE xxxxxxxxxxxxxxxx PTGQUE13 AF2 xxxxxxxxxxxxxxxx
PTGSDLIM ACC 0000000000000000 PTGQUE4 AE0 xxxxxxxxxxxxxxxx PTGQUE14 AF4 xxxxxxxxxxxxxxxx
PTGC0LIM ACE 0000000000000000 PTGQUE5 AE2 xxxxxxxxxxxxxxxx PTGQUE15 AF6 xxxxxxxxxxxxxxxx
PTGC1LIM AD0 0000000000000000 PTGQUE6 AE4 xxxxxxxxxxxxxxxx
TABLE 4-13: SFR BLOCK B00h

DMA DMA1STBL B18 0000000000000000 DMA3REQ B32 0000000000000000

DMA0CON B00 0000000000000000 DMA1STBH B1A 0000000000000000 DMA3STAL B34 0000000000000000
DMA0REQ B02 0000000000000000 DMA1PAD B1C 0000000000000000 DMA3STAH B36 0000000000000000
DMA0STAL B04 0000000000000000 DMA1CNT B1E 0000000000000000 DMA3STBL B38 0000000000000000
DMA0STAH B06 0000000000000000 DMA2CON B20 0000000000000000 DMA3STBH B3A 0000000000000000
DMA0STBL B08 0000000000000000 DMA2REQ B22 0000000000000000 DMA3PAD B3C 0000000000000000
DMA0STBH B0A 0000000000000000 DMA2STAL B24 0000000000000000 DMA3CNT B3E 0000000000000000
DMA0PAD B0C 0000000000000000 DMA2STAH B26 0000000000000000 DMAPWC BF0 0000000000000000
DMA0CNT B0E 0000000000000000 DMA2STBL B28 0000000000000000 DMARQC BF2 0000000000000000
DMA1CON B10 0000000000000000 DMA2STBH B2A 0000000000000000 DMAPPS BF4 0000000000000000
DMA1REQ B12 0000000000000000 DMA2PAD B2C 0000000000000000 DMALCA BF6 0000000000001111
DMA1STAL B14 0000000000000000 DMA2CNT B2E 0000000000000000 DSADRL BF8 0000000000000000
DMA1STAH B16 0000000000000000 DMA3CON B30 0000000000000000 DSADRH BFA 0000000000000000

TABLE 4-14: SFR BLOCK C00h-D00h
PWM FCLCON3 C64 0000000000000000 IOCON6 CC2 1100000000000000

PTCON C00 0000000000000000 PDC3 C66 0000000000000000 FCLCON6 CC4 0000000000000000
PTCON2 C02 0000000000000000 PHASE3 C68 0000000000000000 PDC6 CC6 0000000000000000
PTPER C04 1111111111111000 DTR3 C6A 0000000000000000 PHASE6 CC8 0000000000000000
SEVTCMP C06 0000000000000000 ALTDTR3 C6C 0000000000000000 DTR6 CCA 0000000000000000
MDC C0A 0000000000000000 SDC3 C6E 0000000000000000 ALTDTR6 CCC 0000000000000000
STCON C0E 0000000000000000 SPHASE3 C70 0000000000000000 SDC6 CCE 0000000000000000
STCON2 C10 0000000000000000 TRIG3 C72 0000000000000000 SPHASE6 CD0 0000000000000000
STPER C12 1111111111111000 TRGCON3 C74 0000000000000000 TRIG6 CD2 0000000000000000
SSEVTCMP C14 0000000000000000 STRIG3 C76 0000000000000000 TRGCON6 CD4 0000000000000000
CHOP C1A 0000000000000000 PWMCAP3 C78 0000000000000000 STRIG6 CD6 0000000000000000
PWMKEY C1E xxxxxxxxxxxxxxxx LEBCON3 C7A 0000000000000000 PWMCAP6 CD8 0000000000000000
PWM Generator LEBDLY3 C7C 0000000000000000 LEBCON6 CDA 0000000000000000
PWMCON1 C20 0000000000000000 AUXCON3 C7E 0000000000000000 LEBDLY6 CDC 0000000000000000
IOCON1 C22 1100000000000000 PWMCON4 C80 0000000000000000 AUXCON6 CDE 0000000000000000
FCLCON1 C24 0000000000000000 IOCON4 C82 1100000000000000 PWMCON7 CE0 0000000000000000
PDC1 C26 0000000000000000 FCLCON4 C84 0000000000000000 IOCON7 CE2 1100000000000000
PHASE1 C28 0000000000000000 PDC4 C86 0000000000000000 FCLCON7 CE4 0000000000000000
DTR1 C2A 0000000000000000 PHASE4 C88 0000000000000000 PDC7 CE6 0000000000000000
ALTDTR1 C2C 0000000000000000 DTR4 C8A 0000000000000000 PHASE7 CE8 0000000000000000
SDC1 C2E 0000000000000000 ALTDTR4 C8C 0000000000000000 DTR7 CEA 0000000000000000
SPHASE1 C30 0000000000000000 SDC4 C8E 0000000000000000 ALTDTR7 CEC 0000000000000000
TRIG1 C32 0000000000000000 SPHASE4 C90 0000000000000000 SDC7 CEE 0000000000000000
TRGCON1 C34 0000000000000000 TRIG4 C92 0000000000000000 SPHASE7 CF0 0000000000000000
STRIG1 C36 0000000000000000 TRGCON4 C94 0000000000000000 TRIG7 CF2 0000000000000000
PWMCAP1 C38 0000000000000000 STRIG4 C96 0000000000000000 TRGCON7 CF4 0000000000000000
LEBCON1 C3A 0000000000000000 PWMCAP4 C98 0000000000000000 STRIG7 CF6 0000000000000000
LEBDLY1 C3C 0000000000000000 LEBCON4 C9A 0000000000000000 PWMCAP7 CF8 0000000000000000
AUXCON1 C3E 0000000000000000 LEBDLY4 C9C 0000000000000000 LEBCON7 CFA 0000000000000000
PWMCON2 C40 0000000000000000 AUXCON4 C9E 0000000000000000 LEBDLY7 CFC 0000000000000000
IOCON2 C42 1100000000000000 PWMCON5 CA0 0000000000000000 AUXCON7 CFE 0000000000000000
FCLCON2 C44 0000000000000000 IOCON5 CA2 1100000000000000 PWMCON8 D00 0000000000000000
PDC2 C46 0000000000000000 FCLCON5 CA4 0000000000000000 IOCON8 D02 1100000000000000
PHASE2 C48 0000000000000000 PDC5 CA6 0000000000000000 FCLCON8 D04 0000000000000000
DTR2 C4A 0000000000000000 PHASE5 CA8 0000000000000000 PDC8 D06 0000000000000000
ALTDTR2 C4C 0000000000000000 DTR5 CAA 0000000000000000 PHASE8 D08 0000000000000000
SDC2 C4E 0000000000000000 ALTDTR5 CAC 0000000000000000 ALTDTR8 D0C 0000000000000000
SPHASE2 C50 0000000000000000 SDC5 CAE 0000000000000000 SDC8 D0E 0000000000000000
TRIG2 C52 0000000000000000 SPHASE5 CB0 0000000000000000 SPHASE8 D10 0000000000000000
TRGCON2 C54 0000000000000000 TRIG5 CB2 0000000000000000 TRIG8 D12 0000000000000000
STRIG2 C56 0000000000000000 TRGCON5 CB4 0000000000000000 TRGCON8 D14 0000000000000000
PWMCAP2 C58 0000000000000000 STRIG5 CB6 0000000000000000 STRIG8 D16 0000000000000000
LEBCON2 C5A 0000000000000000 PWMCAP5 CB8 0000000000000000 PWMCAP8 D18 0000000000000000
LEBDLY2 C5C 0000000000000000 LEBCON5 CBA 0000000000000000 LEBCON8 D1A 0000000000000000
AUXCON2 C5E 0000000000000000 LEBDLY5 CBC 0000000000000000 LEBDLY8 D1C 0000000000000000
PWMCON3 C60 0000000000000000 AUXCON5 CBE 0000000000000000 AUXCON8 D1E 0000000000000000
IOCON3 C62 1100000000000000 PWMCON6 CC0 0000000000000000

TABLE 4-15: SFR BLOCK E00h-F00h
PORTA ANSELB E1E 0000001011101111 CNPDD E3C 0000000000000000

TRISA E00 0000000000011111 PORTC ANSELD E3E 0010000110100100
PORTA E02 0000000000000000 TRISC E20 1111011111111111 PORTE
LATA E04 0000000000000000 PORTC E22 0000000000000000 TRISE E40 1111111111111111
ODCA E06 0000000000000000 LATC E24 0000000000000000 PORTE E42 0000000000000000
CNENA E08 0000000000000000 ODCC E26 0000000000000000 LATE E44 0000000000000000
CNPUA E0A 0000000000000000 CNENC E28 0000000000000000 ODCE E46 0000000000000000
CNPDA E0C 0000000000000000 CNPUC E2A 0000000000000000 CNENE E48 0000000000000000
ANSELA E0E 0000000000000111 CNPDC E2C 0000000000000000 CNPUE E4A 0000000000000000
PORTB ANSELC E2E 0001011001110110 CNPDE E4C 0000000000000000
TRISB E10 1111101111111111 PORTD ANSELE E4E 0000000000000000
PORTB E12 0000000000000000 TRISD E30 1111111111111111 CPU
LATB E14 0000000000000000 PORTD E32 0000000000000000 VISI F88 0000000000000000
ODCB E16 0000000000000000 LATD E34 0000000000000000 JTAG
CNENB E18 0000000000000000 ODCD E36 0000000000000000 JDATAH FF0 0000000000000000
CNPUB E1A 0000000000000000 CNEND E38 0000000000000000 JDATAL FF2 0000000000000000
CNPDB E1C 0000000000000000 CNPUD E3A 0000000000000000

4.5.1 PAGED MEMORY SCHEME The paged memory scheme provides access to
multiple 32-Kbyte windows in the PSV memory. The
The dsPIC33EPXXXGS70X/80X family architecture
Data Space Read Page (DSRPAG) register, in combi-
extends the available Data Space through a paging
nation with the upper half of the Data Space address,
scheme, which allows the available Data Space to be
can provide up to 8 Mbytes of PSV address space. The
accessed using MOV instructions in a linear fashion for
paged data memory space is shown in Figure 4-8.
pre- and post-modified Effective Addresses (EAs).
The upper half of the base Data Space address is The Program Space (PS) can be accessed with a
used in conjunction with the Data Space Read Page DSRPAG of 0x200 or greater. Only reads from PS are
(DSRPAG) register to form the Program Space supported using the DSRPAG register.
Visibility (PSV) address.
The Data Space Read Page (DSRPAG) register is
located in the SFR space. Construction of the PSV
address is shown in Figure 4-7. When DSRPAG<9> = 1
and the base address bit, EA<15> = 1, the
DSRPAG<8:0> bits are concatenated onto EA<14:0>
to form the 24-bit PSV read address.
FIGURE 4-7: PROGRAM SPACE VISIBILITY (PSV) READ ADDRESS GENERATION
Byte
16-Bit DS EA Select
EA<15> = 0 No EDS Access 0 EA

(DSRPAG = don’t care)
EA<15>
DSRPAG<9> 1 EA
=1
Select
DSRPAG
Generate
PSV Address 1 DSRPAG<8:0>
9 Bits 15 Bits
24-Bit PSV EA Byte

Select
Note: DS read access when DSRPAG = 0x000 will force an address error trap.

FIGURE 4-8: PAGED DATA MEMORY SPACE
Program Space Table Address Space

(Instruction & Data) (TBLPAG<7:0>)
DS_Addr<15:0>
DS70005258C-page 52
0x0000
(TBLPAG = 0x00)
lsw Using
Program Memory TBLRDL/TBLWTL,
DS_Addr<14:0> (lsw – <15:0>) MSB Using
0x00_0000 TBLRDH/TBLWTH
0x0000 0xFFFF
(DSRPAG = 0x200)
Local Data Space No Writes Allowed
DS_Addr<15:0> 0x7FFF
PSV
0x0000
Program
SFR Registers Memory
0x0FFF (lsw) 0x0000
0x1000 0x0000 (TBLPAG = 0x7F)
(DSRPAG = 0x2FF) lsw Using
8-Kbyte TBLRDL/TBLWTL,
No Writes Allowed 0x7F_FFFF
RAM MSB Using
0x7FFF
0x0000 TBLRDH/TBLWTH
0x2FFF 0xFFFF
0x3000 (DSRPAG = 0x300)
0x7FFF No Writes Allowed Program Memory
0x8000 0x7FFF (MSB – <23:16>)
32-Kbyte PSV 0x00_0000
PSV Window Program
0xFFFF Memory
(MSB)
0x0000
(DSRPAG = 0x3FF)
No Writes Allowed
0x7FFF
0x7F_FFFF
 2016-2018 Microchip Technology Inc.

When a PSV page overflow or underflow occurs, address within the PSV window. This creates a linear
EA<15> is cleared as a result of the register indirect EA PSV address space, but only when using Register
calculation. An overflow or underflow of the EA in the Indirect Addressing modes.
PSV pages can occur at the page boundaries when: Exceptions to the operation described above arise
• The initial address, prior to modification, when entering and exiting the boundaries of Page 0
addresses the PSV page and PSV spaces. Table 4-16 lists the effects of overflow
• The EA calculation uses Pre- or Post-Modified and underflow scenarios at different boundaries.
Register Indirect Addressing; however, this does In the following cases, when overflow or underflow
not include Register Offset Addressing occurs, the EA<15> bit is set and the DSRPAG is not
In general, when an overflow is detected, the DSRPAG modified; therefore, the EA will wrap to the beginning of
register is incremented and the EA<15> bit is set to keep the current page:
the base address within the PSV window. When an • Register Indirect with Register Offset Addressing
underflow is detected, the DSRPAG register is decre- • Modulo Addressing
mented and the EA<15> bit is set to keep the base
• Bit-Reversed Addressing
TABLE 4-16: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0 AND

PSV SPACE BOUNDARIES(2,3,4)
Before After
O/U,
Operation DS Page DS Page
R/W DSxPAG DSxPAG
EA<15> Description EA<15> Description
O, DSRPAG = 0x2FF 1 PSV: Last lsw DSRPAG = 0x300 1 PSV: First MSB
Read [++Wn] page page
or
O, [Wn++] DSRPAG = 0x3FF 1 PSV: Last MSB DSRPAG = 0x3FF 0 See Note 1
Read page
U, DSRPAG = 0x001 1 PSV page DSRPAG = 0x001 0 See Note 1
Read
[--Wn]
U, DSRPAG = 0x200 1 PSV: First lsw DSRPAG = 0x200 0 See Note 1
or
Read page
[Wn--]
U, DSRPAG = 0x300 1 PSV: First MSB DSRPAG = 0x2FF 1 PSV: Last lsw
Read page page
Legend: O = Overflow, U = Underflow, R = Read, W = Write
Note 1: The Register Indirect Addressing now addresses a location in the base Data Space (0x0000-0x7FFF).
2: An EDS access, with DSRPAG = 0x000, will generate an address error trap.
3: Only reads from PS are supported using DSRPAG.
4: Pseudolinear Addressing is not supported for large offsets.

4.5.2 EXTENDED X DATA SPACE The Software Stack Pointer always points to the first
available free word and fills the software stack, work-
The lower portion of the base address space range,
ing from lower toward higher addresses. Figure 4-9
between 0x0000 and 0x7FFF, is always accessible,
illustrates how it pre-decrements for a stack pop
regardless of the contents of the Data Space Read
(read) and post-increments for a stack push (writes).
Page register. It is indirectly addressable through the
register indirect instructions. It can be regarded as When the PC is pushed onto the stack, PC<15:0> are
being located in the default EDS Page 0 (i.e., EDS pushed onto the first available stack word, then
address range of 0x000000 to 0x007FFF with the base PC<22:16> are pushed into the second available stack
address bit, EA<15> = 0, for this address range). How- location. For a PC push during any CALL instruction,
ever, Page 0 cannot be accessed through the upper the MSB of the PC is zero-extended before the push,
32 Kbytes, 0x8000 to 0xFFFF, of base Data Space in as shown in Figure 4-9. During exception processing,
combination with DSRPAG = 0x000. Consequently, the MSB of the PC is concatenated with the lower eight
DSRPAG is initialized to 0x001 at Reset. bits of the CPU STATUS Register, SR. This allows the
contents of SRL to be preserved automatically during
Note 1: DSRPAG should not be used to access interrupt processing.
Page 0. An EDS access with DSRPAG
set to 0x000 will generate an address Note 1: To maintain system Stack Pointer (W15)
error trap. coherency, W15 is never subject to
(EDS) paging, and is therefore, restricted
2: Clearing the DSRPAG in software has no
to an address range of 0x0000 to
effect.
0xFFFF. The same applies to W14 when
The remaining PSV pages are only accessible using used as a Stack Frame Pointer (SFA = 1).
the DSRPAG register in combination with the upper 2: As the stack can be placed in, and can
32 Kbytes, 0x8000 to 0xFFFF, of the base address, access X and Y spaces, care must be
where base address bit, EA<15> = 1. taken regarding its use, particularly with
regard to local automatic variables in a C
4.5.3 SOFTWARE STACK
development environment
The W15 register serves as a dedicated Software
Stack Pointer (SSP), and is automatically modified by
exception processing, subroutine calls and returns; FIGURE 4-9: CALL STACK FRAME
however, W15 can be referenced by any instruction in
the same manner as all other W registers. This simpli- 0x0000 15 0
fies reading, writing and manipulating the Stack Pointer CALL SUBR
(for example, creating stack frames).
Stack Grows Toward
Note: To protect against misaligned stack

Higher Address
accesses, W15<0> is fixed to ‘0’ by the

hardware. PC<15:1> W15 (before CALL)
W15 is initialized to 0x1000 during all Resets. This b‘000000000’ PC<22:16>
address ensures that the SSP points to valid RAM in all <Free Word> W15 (after CALL)
dsPIC33EPXXXGS70X/80X devices and permits stack
availability for non-maskable trap exceptions. These can
occur before the SSP is initialized by the user software.
You can reprogram the SSP during initialization to any
location within Data Space.

4.6 Instruction Addressing Modes 4.6.2 MCU INSTRUCTIONS
The addressing modes shown in Table 4-17 form the The three-operand MCU instructions are of the form:
basis of the addressing modes optimized to support the Operand 3 = Operand 1 <function> Operand 2
specific features of individual instructions. The address-
where Operand 1 is always a Working register (that is,
ing modes provided in the MAC class of instructions differ
the addressing mode can only be Register Direct),
from those in the other instruction types.
which is referred to as Wb. Operand 2 can be a W
register fetched from data memory or a 5-bit literal. The
4.6.1 FILE REGISTER INSTRUCTIONS
result location can either be a W register or a data
Most file register instructions use a 13-bit address field (f) memory location. The following addressing modes are
to directly address data present in the first 8192 bytes supported by MCU instructions:
of data memory (Near Data Space). Most file register
• Register Direct
instructions employ a Working register, W0, which is
denoted as WREG in these instructions. The destina- • Register Indirect
tion is typically either the same file register or WREG • Register Indirect Post-Modified
(with the exception of the MUL instruction), which writes • Register Indirect Pre-Modified
the result to a register or register pair. The MOV instruc- • 5-Bit or 10-Bit Literal
tion allows additional flexibility and can access the
entire Data Space. Note: Not all instructions support all the
addressing modes given above. Individ-
ual instructions can support different
subsets of these addressing modes.
TABLE 4-17: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description
File Register Direct The address of the file register is specified explicitly.
Register Direct The contents of a register are accessed directly.
Register Indirect The contents of Wn form the Effective Address (EA).
Register Indirect Post-Modified The contents of Wn form the EA. Wn is post-modified (incremented
or decremented) by a constant value.
Register Indirect Pre-Modified Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.

4.6.3 MOVE AND ACCUMULATOR 4.6.4 MAC INSTRUCTIONS
INSTRUCTIONS The dual source operand DSP instructions (CLR, ED,
Move instructions, and the DSP accumulator class EDAC, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
of instructions, provide a greater degree of address- to as MAC instructions, use a simplified set of addressing
ing flexibility than other instructions. In addition to the modes to allow the user application to effectively
addressing modes supported by most MCU manipulate the Data Pointers through register indirect
instructions, move and accumulator instructions also tables.
support Register Indirect with Register Offset The two-source operand prefetch registers must be
Addressing mode, also referred to as Register Indexed members of the set {W8, W9, W10, W11}. For data
mode. reads, W8 and W9 are always directed to the X RAGU,
Note: For the MOV instructions, the addressing and W10 and W11 are always directed to the Y AGU.
mode specified in the instruction can differ The Effective Addresses generated (before and after
for the source and destination EA. How- modification) must therefore, be valid addresses within
ever, the 4-bit Wb (Register Offset) field is X Data Space for W8 and W9, and Y Data Space for
shared by both source and destination (but W10 and W11.
typically only used by one). Note: Register Indirect with Register Offset
In summary, the following addressing modes are Addressing mode is available only for W9
supported by move and accumulator instructions: (in X space) and W11 (in Y space).
• Register Direct In summary, the following addressing modes are

• Register Indirect supported by the MAC class of instructions:
• Register Indirect Post-modified • Register Indirect
• Register Indirect Pre-modified • Register Indirect Post-Modified by 2
• Register Indirect with Register Offset (Indexed) • Register Indirect Post-Modified by 4
• Register Indirect with Literal Offset • Register Indirect Post-Modified by 6
• 8-Bit Literal • Register Indirect with Register Offset (Indexed)
• 16-Bit Literal
4.6.5 OTHER INSTRUCTIONS
Note: Not all instructions support all the
addressing modes given above. Individual Besides the addressing modes outlined previously,
instructions may support different subsets some instructions use literal constants of various sizes.
of these addressing modes. For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ULNK, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as a NOP, do not have
any operands.

4.7 Modulo Addressing 4.7.1 START AND END ADDRESS
Modulo Addressing mode is a method of providing an The Modulo Addressing scheme requires that a
automated means to support circular data buffers using starting and ending address be specified and loaded
hardware. The objective is to remove the need for into the 16-bit Modulo Buffer Address registers:
software to perform data address boundary checks XMODSRT, XMODEND, YMODSRT and YMODEND
when executing tightly looped code, as is typical in (see Table 4-2).
many DSP algorithms. Note: Y space Modulo Addressing EA calcula-
Modulo Addressing can operate in either Data or tions assume word-sized data (LSb of
Program Space (since the Data Pointer mechanism is every EA is always clear).
essentially the same for both). One circular buffer can be
The length of a circular buffer is not directly specified. It is
supported in each of the X (which also provides the point-
determined by the difference between the corresponding
ers into Program Space) and Y Data Spaces. Modulo
start and end addresses. The maximum possible length of
Addressing can operate on any W Register Pointer. How-
the circular buffer is 32K words (64 Kbytes).
ever, it is not advisable to use W14 or W15 for Modulo
Addressing since these two registers are used as the 4.7.2 W ADDRESS REGISTER SELECTION
Stack Frame Pointer and Stack Pointer, respectively.
The Modulo and Bit-Reversed Addressing Control
In general, any particular circular buffer can be config- register, MODCON<15:0>, contains enable flags, as well
ured to operate in only one direction, as there are certain as a W register field to specify the W Address registers.
restrictions on the buffer start address (for incrementing The XWM and YWM fields select the registers that
buffers) or end address (for decrementing buffers), operate with Modulo Addressing:
based upon the direction of the buffer.
• If XWM = 1111, X RAGU and X WAGU Modulo
The only exception to the usage restrictions is for Addressing is disabled
buffers that have a power-of-two length. As these
• If YWM = 1111, Y AGU Modulo Addressing is
buffers satisfy the start and end address criteria, they
disabled
can operate in a Bidirectional mode (that is, address
boundary checks are performed on both the lower and The X Address Space Pointer W (XWM) register, to
upper address boundaries). which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 4-2). Modulo Addressing is
enabled for X Data Space when XWM is set to any
value other than ‘1111’ and the XMODEN bit is set
(MODCON<15>).
The Y Address Space Pointer W (YWM) register, to
which Modulo Addressing is to be applied, is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
Data Space when YWM is set to any value other than
‘1111’ and the YMODEN bit (MODCON<14>) is set.
FIGURE 4-10: MODULO ADDRESSING OPERATION EXAMPLE

Byte MOV #0x1100, W0
Address MOV W0, XMODSRT ;set modulo start address
0x1100 MOV #0x1163, W0
MOV W0, MODEND ;set modulo end address
MOV #0x8001, W0
MOV W0, MODCON ;enable W1, X AGU for modulo
MOV #0x0000, W0 ;W0 holds buffer fill value
MOV #0x1110, W1 ;point W1 to buffer

0x1163
DO AGAIN, #0x31 ;fill the 50 buffer locations
MOV W0, [W1++] ;fill the next location
Start Addr = 0x1100 AGAIN: INC W0, W0 ;increment the fill value
End Addr = 0x1163
Length = 0x0032 words

4.7.3 MODULO ADDRESSING 4.8.1 BIT-REVERSED ADDRESSING
APPLICABILITY IMPLEMENTATION
Modulo Addressing can be applied to the Effective Bit-Reversed Addressing mode is enabled when all of
Address (EA) calculation associated with any W these situations are met:
register. Address boundaries check for addresses • BWMx bits (W register selection) in the MODCON
equal to: register are any value other than ‘1111’ (the stack
• The upper boundary addresses for incrementing cannot be accessed using Bit-Reversed
buffers Addressing)
• The lower boundary addresses for decrementing • The BREN bit is set in the XBREV register
buffers • The addressing mode used is Register Indirect
It is important to realize that the address boundaries with Pre-Increment or Post-Increment
check for addresses less than or greater than the upper If the length of a bit-reversed buffer is M = 2N bytes,
(for incrementing buffers) and lower (for decrementing the last ‘N’ bits of the data buffer start address must
buffers) boundary addresses (not just equal to). be zeros.
Address changes can therefore, jump beyond
XB<14:0> is the Bit-Reversed Addressing modifier, or
boundaries and still be adjusted correctly.
‘pivot point’, which is typically a constant. In the case of
Note: The modulo corrected Effective Address an FFT computation, its value is equal to half of the FFT
is written back to the register only when data buffer size.
Pre-Modify or Post-Modify Addressing
Note: All bit-reversed EA calculations assume
mode is used to compute the Effective
word-sized data (LSb of every EA is
Address. When an address offset (such as
always clear). The XB value is scaled
[W7 + W2]) is used, Modulo Addressing
accordingly to generate compatible (byte)
correction is performed, but the contents of
addresses.
the register remain unchanged.
When enabled, Bit-Reversed Addressing is executed
4.8 Bit-Reversed Addressing only for Register Indirect with Pre-Increment or Post-
Increment Addressing and word-sized data writes. It
Bit-Reversed Addressing mode is intended to simplify does not function for any other addressing mode or for
data reordering for radix-2 FFT algorithms. It is byte-sized data and normal addresses are generated
supported by the X AGU for data writes only. instead. When Bit-Reversed Addressing is active, the
The modifier, which can be a constant value or register W Address Pointer is always added to the address
contents, is regarded as having its bit order reversed. modifier (XB) and the offset associated with the
The address source and destination are kept in normal Register Indirect Addressing mode is ignored. In
order. Thus, the only operand requiring reversal is the addition, as word-sized data is a requirement, the LSb
modifier. of the EA is ignored (and always clear).
Note: Modulo Addressing and Bit-Reversed
Addressing can be enabled simultaneously
using the same W register, but Bit-
Reversed Addressing operation will always
take precedence for data writes when
enabled.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the Bit-Reversed Pointer.

FIGURE 4-11: BIT-REVERSED ADDRESSING EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0
Bit Locations Swapped Left-to-Right

Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0

Bit-Reversed Address
Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer
TABLE 4-18: BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY)

Normal Address Bit-Reversed Address
A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal
0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 0 0 0 8
0 0 1 0 2 0 1 0 0 4
0 0 1 1 3 1 1 0 0 12
0 1 0 0 4 0 0 1 0 2
0 1 0 1 5 1 0 1 0 10
0 1 1 0 6 0 1 1 0 6
0 1 1 1 7 1 1 1 0 14
1 0 0 0 8 0 0 0 1 1
1 0 0 1 9 1 0 0 1 9
1 0 1 0 10 0 1 0 1 5
1 0 1 1 11 1 1 0 1 13
1 1 0 0 12 0 0 1 1 3
1 1 0 1 13 1 0 1 1 11
1 1 1 0 14 0 1 1 1 7
1 1 1 1 15 1 1 1 1 15

4.9 Interfacing Program and Data Table instructions allow an application to read or write
Memory Spaces to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
The dsPIC33EPXXXGS70X/80X family architecture need to be updated periodically. It also allows access
uses a 24-bit wide Program Space (PS) and a 16-bit to all bytes of the program word. The remapping
wide Data Space (DS). The architecture is also a method allows an application to access a large block of
modified Harvard scheme, meaning that data can also data on a read-only basis, which is ideal for look-ups
be present in the Program Space. To use this data from a large table of static data. The application can
successfully, it must be accessed in a way that preserves only access the least significant word of the program
the alignment of information in both spaces. word.
Aside from normal execution, the architecture of the
dsPIC33EPXXXGS70X/80X family devices provides
two methods by which Program Space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the Program Space
• Remapping a portion of the Program Space into
the Data Space (Program Space Visibility)
TABLE 4-19: PROGRAM SPACE ADDRESS CONSTRUCTION

Access Program Space Address
Access Type
Space <23> <22:16> <15> <14:1> <0>
Instruction Access User 0 PC<22:1> 0
(Code Execution) 0xxx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0>
(Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx
Configuration TBLPAG<7:0> Data EA<15:0>
1xxx xxxx xxxx xxxx xxxx xxxx
FIGURE 4-12: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1) 0 Program Counter 0
23 Bits
EA 1/0
Table Operations(2) 1/0 TBLPAG
8 Bits 16 Bits
24 Bits
User/Configuration Byte Select

Space Select
Note 1: The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain
word alignment of data in the Program and Data Spaces.
2: Table operations are not required to be word-aligned. Table Read operations are permitted in the
configuration memory space.

4.9.1 DATA ACCESS FROM PROGRAM • TBLRDH (Table Read High):
MEMORY USING TABLE - In Word mode, this instruction maps the entire
INSTRUCTIONS upper word of a program address (P<23:16>)
to a data address. The ‘phantom’ byte
The TBLRDL and TBLWTL instructions offer a direct
(D<15:8>) is always ‘0’.
method of reading or writing the lower word of any
address within the Program Space without going - In Byte mode, this instruction maps the upper
through Data Space. The TBLRDH and TBLWTH or lower byte of the program word to D<7:0>
instructions are the only method to read or write the of the data address in the TBLRDL instruc-
upper eight bits of a Program Space word as data. tion. The data is always ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
The PC is incremented by two for each successive
24-bit program word. This allows program memory In a similar fashion, two table instructions, TBLWTH
addresses to directly map to Data Space addresses. and TBLWTL, are used to write individual bytes or
Program memory can thus be regarded as two 16-bit words to a Program Space address. The details of
wide word address spaces, residing side by side, each their operation are explained in Section 5.0 “Flash
with the same address range. TBLRDL and TBLWTL Program Memory”.
access the space that contains the least significant For all table operations, the area of program memory
data word. TBLRDH and TBLWTH access the space that space to be accessed is determined by the Table Page
contains the upper data byte. register (TBLPAG). TBLPAG covers the entire program
Two table instructions are provided to move byte or memory space of the device, including user application
word-sized (16-bit) data to and from Program Space. and configuration spaces. When TBLPAG<7> = 0, the
Both function as either byte or word operations. table page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
• TBLRDL (Table Read Low): space.
- In Word mode, this instruction maps the lower
word of the Program Space location (P<15:0>)
to a data address (D<15:0>)
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
FIGURE 4-13: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space
TBLPAG
02
23 15 0
0x000000 23 16 8 0
00000000
00000000
0x020000 00000000
0x030000 00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
0x800000
the user memory area.

NOTES:

5.0 FLASH PROGRAM MEMORY manufacture boards with unprogrammed devices and
then program the device just before shipping the
Note 1: This data sheet summarizes the features product. This also allows the most recent firmware or a
of the dsPIC33EPXXXGS70X/80X family custom firmware to be programmed.
of devices. It is not intended to be a Enhanced In-Circuit Serial Programming uses an
comprehensive reference source. To com- on-board bootloader, known as the Program Executive,
plement the information in this data sheet, to manage the programming process. Using an SPI data
refer to “Dual Partition Flash Program frame format, the Program Executive can erase,
Memory” (DS70005156) in the “dsPIC33/ program and verify program memory. For more informa-
PIC24 Family Reference Manual”, which is tion on Enhanced ICSP, see the device programming
available from the Microchip website specification.
(www.microchip.com)
RTSP is accomplished using TBLRD (Table Read) and
2: Some registers and associated bits TBLWT (Table Write) instructions. With RTSP, the user
described in this section may not be application can write program memory data with a
available on all devices. Refer to single program memory word and erase program mem-
Section 4.0 “Memory Organization” in ory in blocks or ‘pages’ of 512 instructions (1536 bytes)
this data sheet for device-specific register at a time.
and bit information.
The dsPIC33EPXXXGS70X/80X family devices contain 5.1 Table Instructions and Flash
internal Program Flash Memory for storing and Programming
executing application code. The memory is readable,
Regardless of the method used, all programming of
writable and erasable during normal operation over the
Flash memory is done with the Table Read and Table
entire VDD range.
Write instructions. These instructions allow direct read
Flash memory can be programmed in three ways: and write access to the program memory space, from
• In-Circuit Serial Programming™ (ICSP™) the data memory, while the device is in normal operating
programming capability mode. The 24-bit target address in the program memory
is formed using bits<7:0> of the TBLPAG register and
• Enhanced In-Circuit Serial Programming
the Effective Address (EA) from a W register, specified
(Enhanced ICSP)
in the table instruction, as shown in Figure 5-1. The
• Run-Time Self-Programming (RTSP) TBLRDL and the TBLWTL instructions are used to read or
ICSP allows for a dsPIC33EPXXXGS70X/80X family write to bits<15:0> of program memory. TBLRDL and
device to be serially programmed while in the end TBLWTL can access program memory in both Word and
application circuit. This is done with a programming Byte modes. The TBLRDH and TBLWTH instructions are
clock and programming data (PGECx/PGEDx) line, used to read or write to bits<23:16> of program memory.
and three other lines for power (VDD), ground (VSS) and TBLRDH and TBLWTH can also access program memory
Master Clear (MCLR). This allows customers to in Word or Byte mode.
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
24 Bits
Using
0 Program Counter 0
Program Counter
Working Reg EA
Using
1/0 TBLPAG Reg
Table Instruction
8 Bits 16 Bits
User/Configuration Byte
Space Select 24-Bit EA Select

5.2 RTSP Operation FIGURE 5-2: UNCOMPRESSED/
COMPRESSED FORMAT
The dsPIC33EPXXXGS70X/80X family Flash program
memory array is organized into rows of 64 instructions 15 7 0
or 192 bytes. RTSP allows the user application to erase Even Byte
a single page (8 rows or 512 instructions) of memory at LSW1
Address
Increasing
a time and to program one row at a time. It is possible 0x00 MSB1
Address
to program two instructions at a time as well.
LSW2
The page erase and single row write blocks are
edge-aligned, from the beginning of program 0x00 MSB2
memory, on boundaries of 1536 bytes and 192 bytes,
respectively. Figure 30-14 in Section 30.0 “Electrical UNCOMPRESSED FORMAT (RPDF = 0)
Characteristics” lists the typical erase and
programming times.
Row programming is performed by loading 192 bytes 15 7 0
into data memory and then loading the address of the Even Byte
LSW1
Increasing
first byte in that row into the NVMSRCADR register. Address
Address
Once the write has been initiated, the device will MSB2 MSB1
automatically load the write latches and increment the
NVMSRCADR and the NVMADR(U) registers until LSW2
all bytes have been programmed. The RPDF bit
(NVMCON<9>) selects the format of the stored data in COMPRESSED FORMAT (RPDF = 1)
RAM to be either compressed or uncompressed. See
Figure 5-2 for data formatting. Compressed data helps
to reduce the amount of required RAM by using the 5.3 Programming Operations
upper byte of the second word for the MSB of the
A complete programming sequence is necessary for
second instruction.
programming or erasing the internal Flash in RTSP
The basic sequence for RTSP word programming is to mode. The processor stalls (waits) until the program-
use the TBLWTL and TBLWTH instructions to load two of ming operation is finished. Setting the WR bit
the 24-bit instructions into the write latches found in (NVMCON<15>) starts the operation and the WR bit is
configuration memory space. Refer to Figure 4-1 automatically cleared when the operation is finished.
through Figure 4-4 for write latch addresses. Program-
ming is performed by unlocking and setting the control 5.3.1 PROGRAMMING ALGORITHM FOR
bits in the NVMCON register. FLASH PROGRAM MEMORY
All erase and program operations may optionally use Programmers can program two adjacent words
the NVM interrupt to signal the successful completion (24 bits x 2) of Program Flash Memory at a time on
of the operation. For example, when performing Flash every other word address boundary (0x000000,
write operations on the Inactive Partition in Dual 0x000004, 0x000008, etc.). To do this, it is necessary to
Partition mode, where the CPU remains running, it is erase the page that contains the desired address of the
necessary to wait for the NVM interrupt before location the user wants to change. For protection against
programming the next block of Flash program memory. accidental operations, the write initiate sequence for
NVMKEY must be used to allow any erase or program
operation to proceed. After the programming command
has been executed, the user application must wait for
the programming time until programming is complete.
The two instructions following the start of the
programming sequence should be NOPs.

5.4 Dual Partition Flash Configuration For robustness of operation, in order to execute the
BOOTSWP instruction, it is necessary to execute the
For dsPIC33EPXXXGS70X/80X devices operating in NVM unlocking sequence as follows:
Dual Partition Flash Program Memory modes, the
Inactive Partition can be erased and programmed with- 1. Write 0x55 to NVMKEY.
out stalling the processor. The same programming 2. Write 0xAA to NVMKEY.
algorithms are used for programming and erasing the 3. Execute the BOOTSWP instruction.
Flash in the Inactive Partition, as described in If the unlocking sequence is not performed, the
Section 5.2 “RTSP Operation”. On top of the page BOOTSWP instruction will be executed as a forced NOP
erase option, the entire Flash memory of the Inactive and a GOTO instruction, following the BOOTSWP instruc-
Partition can be erased by configuring the tion, will be executed, causing the PC to jump to that
NVMOP<3:0> bits in the NVMCON register. location in the current operating partition.
Note 1: The application software to be loaded The SFTSWP and P2ACTIV bits in the NVMCON
into the Inactive Partition will have the register are used to determine a successful swap of the
address of the Active Partition. The Active and Inactive Partitions, as well as which partition
bootloader firmware will need to offset is active. After the BOOTSWP and GOTO instructions, the
the address by 0x400000 in order to write SFTSWP bit should be polled to verify the partition
to the Inactive Partition. swap has occurred and then cleared for the next panel
swap event.
5.4.1 FLASH PARTITION SWAPPING
The Boot Sequence Number is used for determining 5.4.2 DUAL PARTITION MODES
the Active Partition at start-up and is encoded within While operating in Dual Partition mode, the
the FBTSEQ Configuration register bits. Unlike most dsPIC33EPXXXGS70X/80X family devices have the
Configuration registers, which only utilize the lower option for both partitions to have their own defined
16 bits of the program memory, FBTSEQ is a 24-bit security segments, as shown in Figure 27-4. Alterna-
Configuration Word. The Boot Sequence Number tively, the device can operate in Protected Dual Partition
(BSEQ) is a 12-bit value and is stored in FBTSEQ mode, where Partition 1 becomes permanently erase/
twice. The true value is stored in bits, FBTSEQ<11:0>, write-protected. Protected Dual Partition mode allows for
and its complement is stored in bits, FBTSEQ<23:12>. a “Factory Default” mode, which provides a fail-safe
At device Reset, the sequence numbers are read and backup image to be stored in Partition 1.
the partition with the lowest sequence number dsPIC33EPXXXGS70X/80X family devices can also
becomes the Active Partition. If one of the Boot operate in Privileged Dual Partition mode, where addi-
Sequence Numbers is invalid, the device will select the tional security protections are implemented to allow for
partition with the valid Boot Sequence Number, or protection of intellectual property when multiple parties
default to Partition 1 if both sequence numbers are have software within the device. In Privileged Dual Par-
invalid. See Section 27.0 “Special Features” for more tition mode, both partitions place additional restrictions
information. on the FBSLIM register. These prevent changes to the
The BOOTSWP instruction provides an alternative size of the Boot Segment and General Segment,
means of swapping the Active and Inactive Partitions ensuring that neither segment will be altered.
(soft swap) without the need for a device Reset. The
BOOTSWP must always be followed by a GOTO instruc- 5.5 Flash Memory Resources
tion. The BOOTSWP instruction swaps the Active and
Inactive Partitions, and the PC vectors to the location Many useful resources are provided on the main
specified by the GOTO instruction in the newly Active product page of the Microchip website for the devices
Partition. listed in this data sheet. This product page contains the
latest updates and additional information.
It is important to note that interrupts should temporarily
be disabled while performing the soft swap sequence 5.5.1 KEY RESOURCES
and that after the partition swap, all peripherals and
interrupts which were enabled remain enabled. Addi- • “Dual Partition Flash Program Memory”
tionally, the RAM and stack will maintain state after the (DS70005156) in the “dsPIC33/PIC24 Family
switch. As a result, it is recommended that applications Reference Manual”
using soft swaps jump to a routine that will reinitialize • Code Samples
the device in order to ensure the firmware runs as • Application Notes
expected. The Configuration registers will have no • Software Libraries
effect during a soft swap. • Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections

5.6 Control Registers There are two NVM Address registers: NVMADRU and
NVMADR. These two registers, when concatenated,
Five SFRs are used to write and erase the Program form the 24-bit Effective Address (EA) of the selected
Flash Memory: NVMCON, NVMKEY, NVMADR, word/row for programming operations, or the selected
NVMADRU and NVMSRCADR/H. page for erase operations. The NVMADRU register is
The NVMCON register (Register 5-1) selects the used to hold the upper eight bits of the EA, while the
operation to be performed (page erase, word/row NVMADR register is used to hold the lower 16 bits of
program, Inactive Partition erase), initiates the program the EA.
or erase cycle and is used to determine the Active For row programming operation, data to be written to
Partition in Dual Partition modes. Program Flash Memory is written into data memory
NVMKEY (Register 5-4) is a write-only register that is space (RAM) at an address defined by the
used for write protection. To start a programming or NVMSRCADR register (location of first element in row
erase sequence, the user application must programming data).
consecutively write 0x55 and 0xAA to the NVMKEY
register.

REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER
R/SO-0(1) R/W-0(1) R/W-0(1) R/W-0 R/C-0 R-0 R/W-0 R/C-0
WR WREN WRERR NVMSIDL(2) SFTSWP (6)
P2ACTIV (6)
RPDF URERR
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1)

(3,4) (3,4) (3,4)
— — — — NVMOP3 NVMOP2 NVMOP1 NVMOP0(3,4)
bit 7 bit 0
Legend: C = Clearable bit SO = Settable Only bit

bit 15 WR: Write Control bit(1)

1 = Initiates a Flash Memory Program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit(1)
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit(1)
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12 NVMSIDL: NVM Stop in Idle Control bit(2)
1 = Flash voltage regulator goes into Standby mode during Idle mode
0 = Flash voltage regulator is active during Idle mode
bit 11 SFTSWP: Partition Soft Swap Status bit(6)
1 = Partitions have been successfully swapped using the BOOTSWP instruction (soft swap)
0 = Awaiting successful partition swap using the BOOTSWP instruction or a device Reset will determine
the Active Partition based on the FBTSEQ register
bit 10 P2ACTIV: Partition 2 Active Status bit(6)
1 = Partition 2 Flash is mapped into the active region
0 = Partition 1 Flash is mapped into the active region
bit 9 RPDF: Row Programming Data Format bit
1 = Row data to be stored in RAM is in compressed format
0 = Row data to be stored in RAM is in uncompressed format
Note 1: These bits can only be reset on a POR.

2: If this bit is set, power consumption will be further reduced (IIDLE) and upon exiting Idle mode, there is a
delay (TVREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.
6: Only applicable when operating in Dual Partition mode.
7: The specific Boot mode depends on bits<1:0> of the programmed data:
11 = Single Partition Flash mode
10 = Dual Partition Flash mode
01 = Protected Dual Partition Flash mode
00 = Reserved

REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER (CONTINUED)
bit 8 URERR: Row Programming Data Underrun Error bit
1 = Indicates row programming operation has been terminated
0 = No data underrun error is detected
bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,3,4)
1111 = Reserved
1110 = User memory bulk erase operation
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Boot memory double-word program operation in a Dual Partition Flash mode(7)
0101 = Reserved
0100 = Inactive Partition memory erase operation
0011 = Memory page erase operation
0010 = Memory row program operation
0001 = Memory double-word program operation(5)
0000 = Reserved
Note 1: These bits can only be reset on a POR.

2: If this bit is set, power consumption will be further reduced (IIDLE) and upon exiting Idle mode, there is a
delay (TVREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.
6: Only applicable when operating in Dual Partition mode.
7: The specific Boot mode depends on bits<1:0> of the programmed data:
11 = Single Partition Flash mode
10 = Dual Partition Flash mode
01 = Protected Dual Partition Flash mode
00 = Reserved

REGISTER 5-2: NVMADR: NONVOLATILE MEMORY LOWER ADDRESS REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
NVMADR<15:8>
bit 15 bit 8

NVMADR<7:0>
bit 7 bit 0
Legend:
bit 15-0 NVMADR<15:0>: Nonvolatile Memory Lower Write Address bits

Selects the lower 16 bits of the location to program or erase in Program Flash Memory. This register
may be read or written to by the user application.
REGISTER 5-3: NVMADRU: NONVOLATILE MEMORY UPPER ADDRESS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

NVMADRU<23:16>
bit 7 bit 0
Legend:

bit 7-0 NVMADRU<23:16>: Nonvolatile Memory Upper Write Address bits
Selects the upper eight bits of the location to program or erase in Program Flash Memory. This register
may be read or written to by the user application.

REGISTER 5-4: NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0

NVMKEY<7:0>
bit 7 bit 0
Legend:

bit 7-0 NVMKEY<7:0>: NVM Key Register bits (write-only)
REGISTER 5-5: NVMSRCADR: NVM SOURCE DATA ADDRESS REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
NVMSRCADR<15:8>
bit 15 bit 8

NVMSRCADR<7:0>
bit 7 bit 0
Legend:
bit 15-0 NVMSRCADR<15:0>: NVM Source Data Address bits

The RAM address of the data to be programmed into Flash when the NVMOP<3:0> bits are set to row
programming.

6.0 RESETS A simplified block diagram of the Reset module is
shown in Figure 6-1.
Note 1: This data sheet summarizes the Any active source of Reset will make the SYSRST
features of the dsPIC33EPXXXGS70X/ signal active. On system Reset, some of the registers
80X family of devices. It is not intended to associated with the CPU and peripherals are forced to
be a comprehensive reference source. To a known Reset state, and some are unaffected.
sheet, refer to “Reset” (DS70602) in the Note: Refer to the specific peripheral section or
“dsPIC33/PIC24 Family Reference Man- Section 4.0 “Memory Organization” of
ual”, which is available from the Microchip this data sheet for register Reset states.
website (www.microchip.com)
All types of device Reset set a corresponding status bit
2: Some registers and associated bits in the RCON register to indicate the type of Reset (see
described in this section may not be Register 6-1).
A POR clears all the bits, except for the BOR and POR
bits (RCON<1:0>) that are set. The user application
this data sheet for device-specific register
can set or clear any bit, at any time, during code
execution. The RCON bits only serve as status bits.
The Reset module combines all Reset sources and Setting a particular Reset status bit in software does
controls the device Master Reset Signal, SYSRST. The not cause a device Reset to occur.
following is a list of device Reset sources: The RCON register also has other bits associated with
• POR: Power-on Reset the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
• BOR: Brown-out Reset
of this manual.
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction Note: The status bits in the RCON register
should be cleared after they are read so
• WDTO: Watchdog Timer Time-out Reset
that the next RCON register value after a
• CM: Configuration Mismatch Reset device Reset is meaningful.
• TRAPR: Trap Conflict Reset
For all Resets, the default clock source is determined
• IOPUWR: Illegal Condition Device Reset
by the FNOSC<2:0> bits in the FOSCSEL Configura-
- Illegal Opcode Reset tion register. The value of the FNOSCx bits is loaded
- Uninitialized W Register Reset into the NOSC<2:0> (OSCCON<10:8>) bits on Reset,
- Security Reset which in turn, initializes the system clock.
FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator SYSRST
VDD
VDD Rise POR

Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
Security Reset
Configuration Mismatch

6.1 Reset Resources 6.1.1 KEY RESOURCES
Many useful resources are provided on the main • “Reset” (DS70602) in the “dsPIC33/PIC24 Family
product page of the Microchip website for the devices Reference Manual”
listed in this data sheet. This product page contains the • Code Samples
latest updates and additional information. • Application Notes
• Webinars
Manual” Sections

REGISTER 6-1: RCON: RESET CONTROL REGISTER(1)
R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0
TRAPR IOPUWR — — VREGSF — CM VREGS
bit 15 bit 8

(2)
EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend:
bit 15 TRAPR: Trap Reset Flag bit

1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or Uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or Uninitialized W register Reset has not occurred
bit 11 VREGSF: Flash Voltage Regulator Standby During Sleep bit
1 = Flash voltage regulator is active during Sleep
0 = Flash voltage regulator goes into Standby mode during Sleep
bit 9 CM: Configuration Mismatch Flag bit
1 = A Configuration Mismatch Reset has occurred
0 = A Configuration Mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Standby During Sleep bit
1 = Voltage regulator is active during Sleep
0 = Voltage regulator goes into Standby mode during Sleep
bit 7 EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software RESET (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the WDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.

REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 3 SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up from Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
bit 1 BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the WDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.

7.0 INTERRUPT CONTROLLER 7.1.1 ALTERNATE INTERRUPT VECTOR
TABLE
Note 1: This data sheet summarizes the
The Alternate Interrupt Vector Table (AIVT), shown in
features of the dsPIC33EPXXXGS70X/
Figure 7-2, is available only when the Boot Segment is
80X family of devices. It is not intended to
defined and the AIVT has been enabled. To enable the
be a comprehensive reference source. To
Alternate Interrupt Vector Table, the Configuration bit,
AIVTDIS in the FSEC register, must be programmed
sheet, refer to “Interrupts” (DS70000600)
and the AIVTEN bit must be set (INTCON2<8> = 1).
in the “dsPIC33/PIC24 Family Reference
When the AIVT is enabled, all interrupt and exception
Manual”, which is available from the
processes use the alternate vectors instead of the
default vectors. The AIVT begins at the start of the last
2: Some registers and associated bits page of the Boot Segment, defined by BSLIM<12:0>.
described in this section may not be The second half of the page is no longer usable space.
available on all devices. Refer to The Boot Segment must be at least two pages to
Section 4.0 “Memory Organization” in enable the AIVT.
and bit information. Note: Although the Boot Segment must be
enabled in order to enable the AIVT,
The dsPIC33EPXXXGS70X/80X family interrupt application code does not need to be
controller reduces the numerous peripheral interrupt present inside of the Boot Segment. The
request signals to a single interrupt request signal to AIVT (and IVT) will inherit the Boot
the dsPIC33EPXXXGS70X/80X family CPU. Segment code protection.
The interrupt controller has the following features: The AIVT supports debugging by providing a means to
• Six Processor Exceptions and Software Traps switch between an application and a support environ-
• Seven User-Selectable Priority Levels ment without requiring the interrupt vectors to be
• Interrupt Vector Table (IVT) with a Unique Vector reprogrammed. This feature also enables switching
for each Interrupt or Exception Source between applications for evaluation of different
software algorithms at run time.
• Fixed Priority within a Specified User Priority
Level
7.2 Reset Sequence
• Fixed Interrupt Entry and Return Latencies
• Alternate Interrupt Vector Table (AIVT) for Debug A device Reset is not a true exception because the
Support interrupt controller is not involved in the Reset process.
The dsPIC33EPXXXGS70X/80X family devices clear
7.1 Interrupt Vector Table their registers in response to a Reset, which forces the
PC to zero. The device then begins program execution
The dsPIC33EPXXXGS70X/80X family Interrupt Vector at location, 0x000000. A GOTO instruction at the Reset
Table (IVT), shown in Figure 7-1, resides in program address can redirect program execution to the
memory, starting at location, 000004h. The IVT con- appropriate start-up routine.
tains six non-maskable trap vectors and up to
246 sources of interrupts. In general, each interrupt Note: Any unimplemented or unused vector
source has its own vector. Each interrupt vector locations in the IVT should be
contains a 24-bit wide address. The value programmed programmed with the address of a default
into each interrupt vector location is the starting interrupt handler routine that contains a
address of the associated Interrupt Service Routine RESET instruction.
(ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 takes priority over interrupts at any other
vector address.

FIGURE 7-1: dsPIC33EPXXXGS70X/80X FAMILY INTERRUPT VECTOR TABLE
Decreasing Natural Order Priority

Reset – GOTO Instruction 0x000000
Reset – GOTO Address 0x000002
Oscillator Fail Trap Vector 0x000004
Address Error Trap Vector 0x000006
Generic Hard Trap Vector 0x000008
Stack Error Trap Vector 0x00000A
Math Error Trap Vector 0x00000C
Reserved 0x00000E
Generic Soft Trap Vector 0x000010
Reserved 0x000012
Interrupt Vector 0 0x000014
: :
: :
: :
Interrupt Vector 52 0x00007C
IVT
Interrupt Vector 53 0x00007E

Interrupt Vector 54 0x000080 See Table 7-1 for
: : Interrupt Vector Details
: :
: :
Interrupt Vector 116 0x0000FC
Interrupt Vector 117 0x0000FE
: :
: :
: :
Interrupt Vector 244 0x0001FC
Interrupt Vector 245 0x0001FE
START OF CODE 0x000200
Note: In Dual Partition Flash modes, each partition has a dedicated Interrupt Vector Table.

FIGURE 7-2: dsPIC33EPXXXGS70X/80X ALTERNATE INTERRUPT VECTOR TABLE(2)
Decreasing Natural Order Priority Reserved BSLIM<12:0>(1) + 0x000000

Reserved BSLIM<12:0>(1) + 0x000002
Oscillator Fail Trap Vector BSLIM<12:0>(1) + 0x000004
Address Error Trap Vector BSLIM<12:0>(1) + 0x000006
Generic Hard Trap Vector BSLIM<12:0>(1) + 0x000008
Stack Error Trap Vector BSLIM<12:0>(1) + 0x00000A
Math Error Trap Vector BSLIM<12:0>(1) + 0x00000C
Reserved BSLIM<12:0>(1) + 0x00000E
Generic Soft Trap Vector BSLIM<12:0>(1) + 0x000010
Reserved BSLIM<12:0>(1) + 0x000012
Interrupt Vector 0 BSLIM<12:0>(1) + 0x000014
: :
: :
: :
AIVT
Interrupt Vector 52 BSLIM<12:0>(1) + 0x00007C

Interrupt Vector 53 BSLIM<12:0>(1) + 0x00007E
Interrupt Vector 54 BSLIM<12:0>(1) + 0x000080 See Table 7-1 for
: : Interrupt Vector Details
: :
: :
Interrupt Vector 116 BSLIM<12:0>(1) + 0x0000FC
Interrupt Vector 117 BSLIM<12:0>(1) + 0x0000FE
: :
: :
: :
Interrupt Vector 244 BSLIM<12:0>(1) + 0x0001FC
Interrupt Vector 245 BSLIM<12:0>(1) + 0x0001FE
Note 1: The address depends on the size of the Boot Segment defined by BSLIM<12:0>.
[(BSLIM<12:0> – 1) x 0x400] + Offset.
2: In Dual Partition Flash modes, each partition has a dedicated Alternate Interrupt Vector
Table (if enabled).

TABLE 7-1: INTERRUPT VECTOR DETAILS
Vector IRQ Interrupt Bit Location
Interrupt Source IVT Address
# # Flag Enable Priority
Highest Natural Order Priority
INT0 – External Interrupt 0 8 0 0x000014 IFS0<0> IEC0<0> IPC0<2:0>
INT0IF INT0IE INT0IP<2:0>
IC1 – Input Capture 1 9 1 0x000016 IFS0<1> IEC0<1> IPC0<6:4>
IC1IF IC1IE IC1IP<2:0>
OC1 – Output Compare 1 10 2 0x000018 IFS0<2> IEC0<2> IPC0<10:8>
OC1IF OC1IE OC1IP<2:0>
T1 – Timer1 11 3 0x00001A IFS0<3> IEC0<3> IPC0<14:12>
T1IF T1IE T1IP<2:0>
DMA0 – DMA Channel 0 12 4 0x00001C IFS0<4> IEC0<4> IPC1<2:0>
DMA0IF DMA0IE DMA0IP<2:0>
IC2 – Input Capture 2 13 5 0x00001E IFS0<5> IEC0<5> IPC1<6:4>
T2 – Timer2 15 7 0x000022 IFS0<7> IEC0<7> IPC1<14:12>
T2IF T2IE T2IP<2:0>
T3 – Timer3 16 8 0x000024 IFS0<8> IEC0<8> IPC2<2:0>
T3IF T3IE T3IP<2:0>
SPI1TX – SPI1 Transfer Done 17 9 0x000026 IFS0<9> IEC0<9> IPC2<6:4>
SPI1TXIF SPI1TXIE SPI1TXIP<2:0>
SPI1RX – SPI1 Receive Done 18 10 0x000028 IFS0<10> IEC0<10> IPC2<10:8>
SPI1RXIF SPI1RXIE SPI1RXIP<2:0>
U1RX – UART1 Receiver 19 11 0x00002A IFS0<11> IEC0<11> IPC2<14:12>
U1RXIF U1RXIE U1RXIP<2:0>
U1TX – UART1 Transmitter 20 12 0x00002C IFS0<12> IEC0<12> IPC3<2:0>
U1TXIF U1TXIE U1TXIP<2:0>
ADC – ADC Global Convert Done 21 13 0x00002E IFS0<13> IEC0<13> IPC3<6:4>
ADCIF ADCIE ADCIP<2:0>
DMA1 – DMA Channel 1 22 14 0x000030 IFS0<14> IEC0<14> IPC3<10:8>
NVM – NVM Write Complete 23 15 0x000032 IFS0<15> IEC0<15> IPC3<14:12>
NVMIF NVMIE NVMIP<2:0>
SI2C1 – I2C1 Slave Event 24 16 0x000034 IFS1<0> IEC1<0> IPC4<2:0>
SI2C1IF SI2C1IE SI2C1IP<2:0>
MI2C1 – I2C1 Master Event 25 17 0x000036 IFS1<1> IEC1<1> IPC4<6:4>
MI2C1IF MI2C1IE MI2C1IP<2:0>
AC1 – Analog Comparator 1 Interrupt 26 18 0x000038 IFS1<2> IEC1<2> IPC4<10:8>
AC1IF AC1IE AC1IP<2:0>
CN – Input Change Interrupt 27 19 0x00003A IFS1<3> IEC1<3> IPC4<14:12>
CNIF CNIE CNIP<2:0>
INT1 – External Interrupt 1 28 20 0x00003C IFS1<4> IEC1<4> IPC5<2:0>
Reserved 29-31 21-23 0x00003E-0x000043 — — —
DMA2 – DMA Channel 2 32 24 0x00044 IFS1<8> IEC1<8> IPC6<2:0>

TABLE 7-1: INTERRUPT VECTOR DETAILS (CONTINUED)
T4 – Timer4 35 27 0x00004A IFS1<11> IEC1<11> IPC6<14:12>
T4IF T4IE T4IP<2:0>
T5 – Timer5 36 28 0x00004C IFS1<12> IEC1<12> IPC7<2:0>
T5IF T5IE T5IP<2:0>
INT2 – External Interrupt 2 37 29 0x00004E IFS1<13> IEC1<13> IPC7<6:4>
U2RX – UART2 Receiver 38 30 0x000050 IFS1<14> IEC1<14> IPC7<10:8>
U2RXIF U2RXIE U2RXIP<2:0>
U2TX – UART2 Transmitter 39 31 0x000052 IFS1<15> IEC1<15> IPC7<14:12>
U2TXIF U2TXIE U2TXIP<2:0>
SPI2TX – SPI2 Transfer Done 40 32 0x000054 IFS2<0> IEC2<0> IPC8<2:0>
SPI2RX – SPI2 Receive Done 41 33 0x000056 IFS2<1> IEC2<1> IPC8<6:4>
C1RX – CAN1 RX Data Ready 42 34 0x000058 IFS2<2> IEC2<2> IPC8<10:8>
C1RXIF C1RXIE C1RXIP<2:0>
C1 – CAN1 Combined Error 43 35 0x000059 IFS2<3> IEC2<3> IPC8<14:12>
C1IF C1IE C1IP<2:0>
DMA3 – DMA Channel 3 44 36 0x00005A IFS2<4> IEC2<4> IPC9<2:0>
IC3 – Input Capture 3 45 37 0x00005E IFS2<5> IEC2<5> IPC9<6:4>
IC4 – Input Capture 4 46 38 0x000060 IFS2<6> IEC2<6> IPC9<10:8>
Reserved 47-56 39-48 0x000062-0x000074 — — —
SI2C2 – I2C2 Slave Event 57 49 0x000076 IFS3<1> IEC3<1> IPC12<6:4>
SI2C2IF SI2C2IE SI2C2IP<2:0>
MI2C2 – I2C2 Master Event 58 50 0x000078 IFS3<2> IEC3<2> IPC12<10:8>
MI2C2IF MI2C2IE MI2C2IP<2:0>
Reserved 59-61 51-53 0x00007A-0x00007E — — —
INT4 – External Interrupt 4 62 54 0x000080 IFS3<6> IEC3<6> IPC13<10:8>
C2RX – CAN2 RX Data Ready 63 55 0x000082 IFS3<7> IEC3<7> IPC13<14:12>
C2RXIF C2RXIE C2RXIP<2:0>
C2 – CAN 2 Combined Error 64 56 0x000083 IFS3<8> IEC3<8> IPC14<2:0>
C2IF C2IE C2IP<2:0>
PSEM – PWM Special Event Match 65 57 0x000086 IFS3<9> IEC3<9> IPC14<6:4>
PSEMIF PSEMIE PSEMIP<2:0>
Reserved 66-72 58-64 0x000088-0x000094 — — —
U1E – UART1 Error Interrupt 73 65 0x000096 IFS4<1> IEC4<1> IPC16<6:4>
U1EIF U1EIE U1EIP<2:0>
U2E – UART2 Error Interrupt 74 66 0x000098 IFS4<2> IEC4<2> IPC16<10:8>
U2EIF U2EIE U2EIP<2:0>
Reserved 75-77 67-69 0x00009A-0x0000A2 — — —
C1TX – CAN1 TX Data Request 78 70 0x0000A0 IFS4<6> IEC4<6> IPC17<10:8>
C1TXIF C1TXIE C1TXIP<2:0>
C2TX – CAN2 TX Data Request 79 71 0x0000A IFS4<7> IEC4<7> IPC17<14:12>
C2TXIF C2TXIE C2TXIP<2:0>
Reserved 80 72 0x0000A4 — — —

PSES – PWM Secondary Special 81 73 0x0000A6 IFS4<9> IEC4<9> IPC18<6:4>
Event Match PSESIF PSESIE PSESIP<2:0>
Reserved 82-97 74-89 0x0000A8-0x0000C6 — — —
SPI3TX – SPI3 Transfer Done 98 90 0x0000C8 IFS5<10> IEC5<10> IPC22<10:8>
SPI3RX – SPI3 Receive Done 99 91 0x0000CA IFS5<10> IEC5<11> IPC22<14:12>
Reserved 100-101 92-93 0x0000CC-0x0000CE — — —
PWM1 – PWM1 Interrupt 102 94 0x0000D0 IFS5<14> IEC5<14> IPC23<10:8>
PWM1IF PWM1IE PWM1IP<2:0>
PWM6 – PWM6 Interrupt 107 99 0x0000DA IFS6<3> IEC6<3> IPC24<14:12>
PWM7 – PWM7 Interrupt 108 100 0x0000DC IFS6<4> IEC6<4> IPC25<2:0>
PWM8 – PWM8 Interrupt 109 101 0x0000DE IFS6<5> IEC6<5> IPC25<6:4>
Reserved 110 102 0x0000E0 — — —
AC2 – Analog Comparator 2 Interrupt 111 103 0x0000E2 IFS6<7> IEC6<7> IPC25<14:12>
Reserved 114-117 106-109 0x0000E8-0x0000EE — — —
AN0 Conversion Done 118 110 0x0000F0 IFS6<14> IEC6<14> IPC27<10:8>
AN0IF AN0IE AN0IP<2:0>
AN5 Conversion Done 123 115 0x0000FA IFS7<3> IEC7<3> IPC28<14:12>
AN6 Conversion Done 124 116 0x0000FC IFS7<4> IEC7<4> IPC29<2:0>
AN7 Conversion Done 125 117 0x0000FE IFS7<5> IEC7<5> IPC29<6:4>
Reserved 126-131 118-123 0x000100-0x00010A — — —

SPI1 Error Interrupt 132 124 0x00010C IFS7<12> IEC7<12> IPC31<2:0>
SPI1IF SPI1IE SPI1IP<2:0>
SPI2 Error Interrupt 133 125 0x00010E IFS7<13> IEC7<13> IPC31<6:4>
SPI3 Error Interrupt 134 126 0x000110 IFS7<13> IEC7<13> IPC31<10:8>
Reserved 135-145 127-137 0x000112-0x000126 — — —
CLC1 Interrupt 146 138 0x000128 IFS8<10> IEC8<10> IPC34<10:8>
CLC1IF CLC1IE CLC1IP<2:0>
CLC2 Interrupt 147 139 0x00012A IFS8<11> IEC8<11> IPC34<14:12>
CLC3 Interrupt 148 140 0x00012C IFS8<12> IEC8<12> IPC35<2:0>
CLC4 Interrupt 149 141 0x00012E IFS8<13> IEC8<13> IPC35<6:4>
ICD – ICD Application 150 142 0x000130 IFS8<14> IEC8<14> IPC35<10:8>
ICDIF ICDIE ICDIP<2:0>
JTAG – JTAG Programming 151 143 0x000132 IFS8<15> IEC8<15> IPC35<14:12>
JTAGIF JTAGIE JTAGIP<2:0>
Reserved 152 144 0x000134 — — —
PTGSTEP – PTG Step 153 145 0x000136 IFS9<1> IEC9<1> IPC36<6:4>
PTGSTEPIF PTGSTEPIE PTGSTEP<2:0>
PTGWDT – PTG WDT Time-out 154 146 0x000138 IFS9<2> IEC9<2> IPC36<10:8>
PTGWDTIF PTGWDTIE PTGWDT<2:0>
PTG0 – PTG Interrupt Trigger 0 155 147 0x00013A IFS9<3> IEC9<3> IPC36<14:12>
PTG0IF PTG0IE PTG0IP<2:0>
PTG1 – PTG Interrupt Trigger 1 156 148 0x00013C IFS9<4> IEC9<4> IPC37<2:0>
PTG2 – PTG Interrupt Trigger 2 157 149 0x00013E IFS9<5> IEC9<5> IPC37<6:4>
PTG3 – PTG Interrupt Trigger 3 158 150 0x000140 IFS9<6> IEC9<6> IPC37<10:8>
AN8 Conversion Done 159 151 0x000142 IFS9<7> IEC9<7> IPC37<14:12>
AN12 Conversion Done 163 155 0x00014A IFS9<11> IEC9<11> IPC38<14:12>
AN13 Conversion Done 164 156 0x00014C IFS9<12> IEC9<12> IPC39<2:0>
AN14 Conversion Done 165 157 0x00014E IFS9<13> IEC9<13> IPC39<6:4>

AN20 Conversion Done 171 163 0x00015A IFS10<3> IEC10<3> IPC40<14:12>
AN21 Conversion Done 172 164 0x00015C IFS10<4> IEC10<4> IPC41<2:0>
Reserved 173-180 165-172 0x00015C-0x00016C — — —
I2C1 – I2C1 Bus Collision 181 173 0x00016E IFS10<13> IEC10<13> IPC43<6:4>
I2C1IF I2C1IE I2C1IP<2:0>
I2C2 – I2C2 Bus Collision 182 174 0x000170 IFS10<14> IEC10<14> IPC43<10:8>
I2C2IF I2C2IE I2C2IP<2:0>
Reserved 183-184 175-176 0x000172-0x000174 — — —
ADCMP0 – ADC Digital Comparator 0 185 177 0x000176 IFS11<1> IEC11<1> IPC44<6:4>
ADCMP0IF ADCMP0IE ADCMP0IP<2:0>
ADCMP1 – ADC Digital Comparator 1 186 178 0x000178 IFS11<2> IEC11<2> IPC44<10:8>
ADCMP1IF ADCMP1IE ADCMP1IP<2:0>
ADFLTR0 – ADC Filter 0 187 179 0x00017A IFS11<3> IEC11<3> IPC44<14:12>
ADFLTR0IF ADFLTR0IE ADFLTR0IP<2:0>
ADFLTR1 – ADC Filter 1 188 180 0x00017C IFS11<4> IEC11<4> IPC45<2:0>
ADFLTR1IF ADFLTR1IE ADFLTR1IP<2:0>
Reserved 189-253 181-245 0x00017E-0x000192 — — —

7.3 Interrupt Resources 7.4.3 IECx
Many useful resources are provided on the main prod- The IECx registers maintain all of the interrupt enable
uct page of the Microchip website for the devices listed bits. These control bits are used to individually enable
in this data sheet. This product page contains the latest interrupts from the peripherals or external signals.
updates and additional information.
7.4.4 IPCx
7.3.1 KEY RESOURCES The IPCx registers are used to set the Interrupt Priority
• “Interrupts” (DS70000600) in the Level (IPL) for each source of interrupt. Each user
“dsPIC33/PIC24 Family Reference Manual” interrupt source can be assigned to one of seven
priority levels.
• Code Samples
• Application Notes 7.4.5 INTTREG
The INTTREG register contains the associated
• Webinars interrupt vector number and the new CPU Interrupt
• All Related “dsPIC33/PIC24 Family Reference Priority Level, which are latched into the Vector
Manual” Sections Number of Pending Interrupt bits (VECNUM<7:0>) and
• Development Tools New CPU Interrupt Priority Level bits (ILR<3:0>) fields
in the INTTREG register. The new Interrupt Priority
7.4 Interrupt Control and Status Level is the priority of the pending interrupt.
Registers The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence as they are
dsPIC33EPXXXGS70X/80X family devices implement listed in Table 7-1. For example, the INT0 (External
the following registers for the interrupt controller: Interrupt 0) is shown as having Vector Number 8 and a
• INTCON1 natural order priority of 0. Thus, the INT0IF bit is found
• INTCON2 in IFS0<0>, the INT0IE bit in IEC0<0> and the
INT0IP<2:0> bits in the first position of IPC0
• INTCON3
(IPC0<2:0>).
• INTCON4
• INTTREG 7.4.6 STATUS/CONTROL REGISTERS
Although these registers are not specifically part of the
7.4.1 INTCON1 THROUGH INTCON4
interrupt control hardware, two of the CPU Control
Global interrupt control functions are controlled from registers contain bits that control interrupt functionality.
INTCON1, INTCON2, INTCON3 and INTCON4. For more information on these registers, refer to
INTCON1 contains the Interrupt Nesting Disable bit “dsPIC33E Enhanced CPU” (DS70005158) in the
(NSTDIS), as well as the control and status flags for the “dsPIC33/PIC24 Family Reference Manual”.
processor trap sources. • The CPU STATUS Register, SR, contains the
The INTCON2 register controls external interrupt IPL<2:0> bits (SR<7:5>). These bits indicate the
request signal behavior, contains the Global Interrupt current CPU Interrupt Priority Level. The user
Enable bit (GIE) and the Alternate Interrupt Vector Table software can change the current CPU Interrupt
Enable bit (AIVTEN). Priority Level by writing to the IPLx bits.
INTCON3 contains the status flags for the Auxiliary • The CORCON register contains the IPL3 bit
PLL and DO stack overflow status trap sources. which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
The INTCON4 register contains the Software so that trap events cannot be masked by the user
Generated Hard Trap Status bit (SGHT). software.
7.4.2 IFSx All Interrupt registers are described in Register 7-3
through Register 7-7 in the following pages.
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.

REGISTER 7-1: SR: CPU STATUS REGISTER(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0
OA OB SA SB OAB SAB DA DC
bit 15 bit 8
R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0

IPL2(2) IPL1(2) IPL0(2) RA N OV Z C
bit 7 bit 0

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)

111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
Note 1: For complete register details, see Register 3-1.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
IPL<3> = 1.

REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1)
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
VAR — US1 US0 EDT DL2 DL1 DL0
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3(2) SFA RND IF
bit 7 bit 0

bit 15 VAR: Variable Exception Processing Latency Control bit

1 = Variable exception processing is enabled
0 = Fixed exception processing is enabled
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU Interrupt Priority Level is greater than 7
0 = CPU Interrupt Priority Level is 7 or less
Note 1: For complete register details, see Register 3-2.


REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1
NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL —
bit 7 bit 0
Legend:
bit 15 NSTDIS: Interrupt Nesting Disable bit

1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14 OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13 OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12 COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11 COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10 OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap is disabled
bit 9 OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
bit 8 COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B is enabled
bit 7 SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6 DIV0ERR: Divide-by-Zero Error Status bit
1 = Math error trap was caused by a divide-by-zero
0 = Math error trap was not caused by a divide-by-zero
bit 4 MATHERR: Math Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
bit 3 ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred

REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 2 STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1 OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred

R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0
GIE DISI SWTRAP — — — — AIVTEN
bit 15 bit 8
U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

— — — INT4EP — INT2EP INT1EP INT0EP
bit 7 bit 0
Legend:
bit 15 GIE: Global Interrupt Enable bit

1 = Interrupts and associated IE bits are enabled
0 = Interrupts are disabled, but traps are still enabled
bit 14 DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13 SWTRAP: Software Trap Status bit
1 = Software trap is enabled
0 = Software trap is disabled
bit 8 AIVTEN: Alternate Interrupt Vector Table Enable
1 = Uses Alternate Interrupt Vector Table
0 = Uses standard Interrupt Vector Table
bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — NAE
bit 15 bit 8
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0

— — — DOOVR — — — APLL
bit 7 bit 0
Legend:

bit 8 NAE: NVM Address Error Soft Trap Status bit
1 = NVM address error soft trap has occurred
0 = NVM address error soft trap has not occurred
bit 4 DOOVR: DO Stack Overflow Soft Trap Status bit
1 = DO stack overflow soft trap has occurred
0 = DO stack overflow soft trap has not occurred
bit 0 APLL: Auxiliary PLL Loss of Lock Soft Trap Status bit
1 = APLL lock soft trap has occurred
0 = APLL lock soft trap has not occurred

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — SGHT
bit 7 bit 0
Legend:

bit 0 SGHT: Software Generated Hard Trap Status bit
1 = Software generated hard trap has occurred
0 = Software generated hard trap has not occurred

REGISTER 7-7: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
— — — — ILR<3:0>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

VECNUM<7:0>
bit 7 bit 0
Legend:

bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
bit 7-0 VECNUM<7:0>: Vector Number of Pending Interrupt bits
11111111 = 255, Reserved; do not use
•
•
•
00001001 = 9, IC1 – Input Capture 1
00001000 = 8, INT0 – External Interrupt 0
00000110 = 6, Generic soft error trap
00000100 = 4, Math error trap
00000011 = 3, Stack error trap
00000010 = 2, Generic hard trap
00000001 = 1, Address error trap
00000000 = 0, Oscillator fail trap

8.0 DIRECT MEMORY ACCESS The DMA Controller transfers data between Peripheral
Data registers and Data Space SRAM.
(DMA)
In addition, DMA can access the entire data memory
Note 1: This data sheet summarizes the features space. The data memory bus arbiter is utilized when
of the dsPIC33EPXXXGS70X/80X family either the CPU or DMA attempts to access SRAM,
of devices. It is not intended to be a resulting in potential DMA or CPU Stalls.
comprehensive reference source. To com-
The DMA Controller supports four independent
plement the information in this data
channels. Each channel can be configured for transfers
sheet, refer to “Direct Memory Access
to or from selected peripherals. The peripherals
(DMA)” (DS70348) in the “dsPIC33/
supported by the DMA Controller include:
PIC24 Family Reference Manual”, which
is available from the Microchip website • CAN
(www.microchip.com). • UART
2: Some registers and associated bits • Input Capture
described in this section may not be • Output Compare
available on all devices. Refer to • Timers
Refer to Table 8-1 for a complete list of supported
peripherals.
FIGURE 8-1: PERIPHERAL TO DMA CONTROLLER
Data Memory
PERIPHERAL DMA Arbiter
(see Figure 4-10)
SRAM

In addition, DMA transfers can be triggered by timers as • Peripheral Indirect Addressing mode (peripheral
well as external interrupts. Each DMA channel is uni- generates destination address)
directional. Two DMA channels must be allocated to read • CPU Interrupt after Half or Full Block Transfer
and write to a peripheral. If more than one channel Complete
receives a request to transfer data, a simple fixed priority • Byte or Word Transfers
scheme, based on channel number, dictates which
• Fixed Priority Channel Arbitration
channel completes the transfer and which channel, or
channels, are left pending. Each DMA channel moves a • Manual (software) or Automatic (peripheral DMA
block of data, after which, it generates an interrupt to the requests) Transfer Initiation
CPU to indicate that the block is available for processing. • One-Shot or Auto-Repeat Block Transfer modes
The DMA Controller provides these functional • Ping-Pong mode (automatic switch between two
capabilities: SRAM Start addresses after each block transfer
complete)
• Four DMA Channels
• DMA Request for each Channel can be Selected
• Register Indirect with Post-Increment Addressing from any Supported Interrupt Source
mode
• Debug Support Features
• Register Indirect without Post-Increment
Addressing mode The peripherals that can utilize DMA are listed in
Table 8-1.
TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS

DMAxPAD Register DMAxPAD Register
Peripheral to DMA DMAxREQ Register
(Values to Read from (Values to Write to
Association IRQSEL<7:0> Bits
Peripheral) Peripheral)
INT0 – External Interrupt 0 00000000 — —
IC1 – Input Capture 1 00000001 0x0144 (IC1BUF) —
IC2 – Input Capture 2 00000101 0x014C (IC2BUF) —
IC3 – Input Capture 3 00100101 0x0154 (IC3BUF) —
IC4 – Input Capture 4 00100110 0x015C (IC4BUF) —
OC1 – Output Compare 1 00000010 — 0x0906 (OC1R)
0x0904 (OC1RS)
0x090E (OC2RS)
OC3 – Output Compare 3 00011001 — 0x091A (OC3R)
0x0918 (OC3RS)
0x0922 (OC4RS)
TMR2 – Timer2 00000111 — —
TMR3 – Timer3 00001000 — —
TMR4 – Timer4 00011011 — —
TMR5 – Timer5 00011100 — —
UART1RX – UART1 Receiver 00001011 0x0226 (U1RXREG) —
UART1TX – UART1 Transmitter 00001100 — 0x0224 (U1TXREG)
UART2RX – UART2 Receiver 00011110 0x0236 (U2RXREG) —
UART2TX – UART2 Transmitter 00011111 — 0x0234 (U2TXREG)
CAN1 – RX Data Ready 00100010 0x04C0 (C1RXD) —
CAN1 – TX Data Request 01000110 — 0x04C2 (C1TXD)
CAN2 – RX Data Ready 00110111 0x07C0(C2RXD) —
CAN2 – TX Data Request 01000111 — 0x07C2 (C2TXD)

FIGURE 8-2: DMA CONTROLLER BLOCK DIAGRAM
SRAM Peripheral Indirect Address
DMA Controller
DMA IRQ to DMA
DMA Ready and Interrupt
Control
DMA
Arbiter Channels Peripheral 1 Controller
Modules
0 1 2 3 CPU DMA
DMA X-Bus
CPU Peripheral X-Bus
CPU DMA CPU DMA

Non-DMA DMA DMA
CPU Ready Ready
Peripheral
Peripheral 2 Peripheral 3
IRQ to DMA and IRQ to DMA and

Interrupt Controller Interrupt Controller
Modules Modules
Note: CPU and DMA address buses are not shown for clarity.

8.1 DMA Controller Registers Additional status registers (DMAPWC, DMARQC,
DMAPPS, DMALCA and DSADRL/H) are common to all
Each DMA Controller Channel x (where x = 0 through 3) DMA Controller channels. These status registers pro-
contains the following registers: vide information on write and request collisions, as well
• 16-Bit DMA Channel x Control Register (DMAxCON) as on last address and channel access information.
• 16-Bit DMA Channel x IRQ Select Register The interrupt flags (DMAxIF) are located in an IFSx
(DMAxREQ) register in the interrupt controller. The corresponding
• 32-Bit DMA Channel x Start Address Register A interrupt enable control bits (DMAxIE) are located in an
(DMAxSTAL/H) IECx register in the interrupt controller and the
• 32-Bit DMA Channel x Start Address Register B corresponding interrupt priority control bits (DMAxIP)
(DMAxSTBL/H) are located in an IPCx register in the interrupt controller.
• 16-Bit DMA Channel x Peripheral Address Register
(DMAxPAD)
• 14-Bit DMA Channel x Transfer Count Register
(DMAxCNT)
REGISTER 8-1: DMAxCON: DMA CHANNEL x CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
CHEN SIZE DIR HALF NULLW — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

— — AMODE1 AMODE0 — — MODE1 MODE0
bit 7 bit 0
Legend:
bit 15 CHEN: DMA Channel Enable bit

1 = Channel is enabled
0 = Channel is disabled
bit 14 SIZE: DMA Data Transfer Size bit
1 = Byte
0 = Word
bit 13 DIR: Transfer Direction bit (source/destination bus select)
1 = Reads from RAM address, writes to peripheral address
0 = Reads from peripheral address, writes to RAM address
bit 12 HALF: Block Transfer Interrupt Select bit
1 = Initiates interrupt when half of the data has been moved
0 = Initiates interrupt when all of the data has been moved
bit 11 NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to RAM write (DIR bit must also be clear)
0 = Normal operation
bit 5-4 AMODE<1:0>: DMA Channel Addressing Mode Select bits
11 = Reserved
10 = Peripheral Indirect mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes are enabled (one block transfer from/to each DMA buffer)
10 = Continuous, Ping-Pong modes are enabled
01 = One-Shot, Ping-Pong modes are disabled
00 = Continuous, Ping-Pong modes are disabled

REGISTER 8-2: DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER
R/S-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
(1)
FORCE — — — — — — —
bit 15 bit 8

IRQSEL<7:0>
bit 7 bit 0
Legend: S = Settable bit

bit 15 FORCE: Force DMA Transfer bit(1)

1 = Forces a single DMA transfer (Manual mode)
0 = Automatic DMA transfer initiation by DMA request
bit 7-0 IRQSEL<7:0>: DMA Peripheral IRQ Number Select bits
01000111 = CAN2 – TX data request
01000110 = CAN1 – TX data request
00110111 = CAN2 – RX data ready
00100110 = IC4 – Input Capture 4
00100010 = CAN1 – RX data ready
00011111 = UART2TX – UART2 transmitter
00011110 = UART2RX – UART2 receiver
00011100 = TMR5 – Timer5
00011011 = TMR4 – Timer4
00011010 = OC4 – Output Compare 4
00001100 = UART1TX – UART1 transmitter
00001011 = UART1RX – UART1 receiver
00001000 = TMR3 – Timer3
00000111 = TMR2 – Timer2
00000000 = INT0 – External Interrupt 0
Note 1: The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the
forced DMA transfer is complete or the channel is disabled (CHEN = 0).

REGISTER 8-3: DMAxSTAH: DMA CHANNEL x START ADDRESS REGISTER A (HIGH)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

STA<23:16>
bit 7 bit 0
Legend:

bit 7-0 STA<23:16>: DMA Primary Start Address bits (source or destination)
REGISTER 8-4: DMAxSTAL: DMA CHANNEL x START ADDRESS REGISTER A (LOW)

STA<15:8>
bit 15 bit 8

STA<7:0>
bit 7 bit 0
Legend:
bit 15-0 STA<15:0>: DMA Primary Start Address bits (source or destination)

REGISTER 8-5: DMAxSTBH: DMA CHANNEL x START ADDRESS REGISTER B (HIGH)
U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

STB<23:16>
bit 7 bit 0
Legend:

bit 7-0 STB<23:16>: DMA Secondary Start Address bits (source or destination)
REGISTER 8-6: DMAxSTBL: DMA CHANNEL x START ADDRESS REGISTER B (LOW)

STB<15:8>
bit 15 bit 8

STB<7:0>
bit 7 bit 0
Legend:
bit 15-0 STB<15:0>: DMA Secondary Start Address bits (source or destination)

REGISTER 8-7: DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1)
PAD<15:8>
bit 15 bit 8

PAD<7:0>
bit 7 bit 0
Legend:
bit 15-0 PAD<15:0>: DMA Peripheral Address Register bits
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
REGISTER 8-8: DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CNT<13:8>(2)
bit 15 bit 8

(2)
CNT<7:0>
bit 7 bit 0
Legend:

bit 13-0 CNT<13:0>: DMA Transfer Count Register bits(2)
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
2: The number of DMA transfers = CNT<13:0> + 1.

REGISTER 8-9: DSADRH: DMA MOST RECENT RAM HIGH ADDRESS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DSADR<23:16>
bit 7 bit 0
Legend:

bit 7-0 DSADR<23:16>: Most Recent DMA Address Accessed by DMA bits
REGISTER 8-10: DSADRL: DMA MOST RECENT RAM LOW ADDRESS REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
DSADR<15:8>
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DSADR<7:0>
bit 7 bit 0
Legend:
bit 15-0 DSADR<15:0>: Most Recent DMA Address Accessed by DMA bits

REGISTER 8-11: DMAPWC: DMA PERIPHERAL WRITE COLLISION STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — — PWCOL3 PWCOL2 PWCOL1 PWCOL0
bit 7 bit 0
Legend:

bit 3 PWCOL3: Channel 3 Peripheral Write Collision Flag bit
1 = Write collision is detected
0 = No write collision is detected

REGISTER 8-12: DMARQC: DMA REQUEST COLLISION STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — — RQCOL3 RQCOL2 RQCOL1 RQCOL0
bit 7 bit 0
Legend:

bit 3 RQCOL3: Channel 3 Transfer Request Collision Flag bit
1 = User FORCE and interrupt-based request collision are detected
0 = No request collision is detected

REGISTER 8-13: DMALCA: DMA LAST CHANNEL ACTIVE STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-1 R-1 R-1 R-1

— — — — LSTCH<3:0>
bit 7 bit 0
Legend:

bit 3-0 LSTCH<3:0>: Last DMA Controller Channel Active Status bits
1111 = No DMA transfer has occurred since system Reset
1110 = Reserved
•
•
•
0100 = Reserved
0011 = Last data transfer was handled by Channel 3

REGISTER 8-14: DMAPPS: DMA PING-PONG STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0

— — — — PPST3 PPST2 PPST1 PPST0
bit 7 bit 0
Legend:

bit 3 PPST3: Channel 3 Ping-Pong Mode Status Flag bit
1 = DMA3STB register is selected
0 = DMA3STA register is selected

NOTES:

9.0 OSCILLATOR CONFIGURATION The dsPIC33EPXXXGS70X/80X family oscillator
system provides:
• On-Chip Phase-Locked Loop (PLL) to Boost
Internal Operating Frequency on Select Internal
and External Oscillator Sources
comprehensive reference source. To
complement the information in this data • On-the-Fly Clock Switching between Various
sheet, refer to “Oscillator Module” Clock Sources
(DS70005131) in the “dsPIC33/PIC24 • Doze mode for System Power Savings
Family Reference Manual”, which is • Fail-Safe Clock Monitor (FSCM) that Detects
available from the Microchip website Clock Failure and Permits Safe Application
(www.microchip.com). Recovery or Shutdown
2: Some registers and associated bits • Configuration Bits for Clock Source Selection
described in this section may not be • Auxiliary PLL for ADC and PWM
A simplified diagram of the oscillator system is shown
in Figure 9-1.

FIGURE 9-1: OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator (POSC)

DOZE<2:0>
OSC1
POSCCLK XT, HS, EC
S2
XTPLL, HSPLL,
S3 FPLLO ECPLL, FRCPLL
S1/S3 FCY(2)
DOZE
S1 PLL (1)
OSC2 FVCO
POSCMD<1:0>
FP(2)
÷2
FRCDIV
FRC FRCCLK FRCDIVN FOSC
Oscillator S7
REFERENCE CLOCK OUTPUT

TUN<5:0> FRCDIV<2:0>
FRCDIV16 POSCCLK REFCLKO
÷ 16 S6
÷N
FRC FOSC RPn
S0
RODIV<3:0>
LPRC LPRC ROSEL
S5
Oscillator
Clock Fail Clock Switch Reset
S0 NOSC<2:0> FNOSC<2:0>
WDT, PWRT,
FSCM
AUXILIARY CLOCK GENERATOR CIRCUIT BLOCK DIAGRAM
FRCCLK FVCO(1)
1 0
ACLK PWM/ADC
POSCCLK 1 APLL x 16 1 ÷N
to LFSR
0 1
GND 0 0
ASRCSEL FRCSEL ENAPLL SELACLK APSTSCLR<2:0>(4)
Note 1: See Figure 9-2 for the source of the FVCO signal.
2: FP refers to the clock source for all the peripherals, while FCY (or MIPS) refers to the clock source for the CPU.
Throughout this document, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY
will be different when Doze mode is used in any ratio other than 1:1.
3: The auxiliary clock postscaler must be configured to divide-by-1 (APSTSCLR<2:0> = 111) for proper operation
of the PWM and ADC modules.

9.1 CPU Clocking System Instruction execution speed or device operating
frequency, FCY, is given by Equation 9-1.
The dsPIC33EPXXXGS70X/80X family of devices
provides six system clock options: EQUATION 9-1: DEVICE OPERATING
• Fast RC (FRC) Oscillator FREQUENCY
• FRC Oscillator with Phase-Locked Loop FCY = FOSC/2
(FRCPLL)
• FRC Oscillator with Postscaler Figure 9-2 is a block diagram of the PLL module.
• Primary (XT, HS or EC) Oscillator Equation 9-2 provides the relationship between Input
• Primary Oscillator with PLL (XTPLL, HSPLL, Frequency (FIN) and Output Frequency (FPLLO).
ECPLL) Equation 9-3 provides the relationship between Input
Frequency (FIN) and VCO Frequency (FVCO).
• Low-Power RC (LPRC) Oscillator
FIGURE 9-2: PLL BLOCK DIAGRAM
0.8 MHz < FPLLI(1) < 8.0 MHz FPLLO(1)  120 MHz @ +125ºC
120 MHZ < FVCO(1) < 340 MHZ FPLLO(1)  140 MHz @ +85ºC
FIN FPLLI
÷ N1 FVCO FOSC
PFD VCO ÷ N2
PLLPRE<4:0>
PLLPOST<1:0>
÷M
PLLDIV<8:0>
Note 1: This frequency range must be met at all times.
EQUATION 9-2: FPLLO CALCULATION
M PLLDIV<8:0> + 2
FPLLO = FIN  ( N1 ) (
= FIN  (PLLPRE<4:0> + 2) 2(PLLPOST<1:0> + 1) )
Where:
N1 = PLLPRE<4:0> + 2
N2 = 2 x (PLLPOST<1:0> + 1)
M = PLLDIV<8:0> + 2
EQUATION 9-3: FVCO CALCULATION
M PLLDIV<8:0> + 2
FVCO = FIN  ()
N1 (
= FIN  (PLLPRE<4:0> + 2) )

TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
See
Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0>
Notes
Fast RC Oscillator with Divide-by-n (FRCDIVN) Internal xx 111 1, 2
Fast RC Oscillator with Divide-by-16 Internal xx 110 1
Low-Power RC Oscillator (LPRC) Internal xx 101 1
Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011
Primary Oscillator (XT) with PLL (XTPLL) Primary 01 011
Primary Oscillator (EC) with PLL (ECPLL) Primary 00 011 1
Primary Oscillator (HS) Primary 10 010
Primary Oscillator (XT) Primary 01 010
Primary Oscillator (EC) Primary 00 010 1
Fast RC Oscillator (FRC) with Divide-by-N and Internal xx 001 1
PLL (FRCPLL)
Fast RC Oscillator (FRC) Internal xx 000 1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default Oscillator mode for an unprogrammed (erased) device.
9.2 Auxiliary Clock Generation 9.3 Reference Clock Generation

The auxiliary clock generation is used for peripherals The reference clock output logic provides the user with
that need to operate at a frequency unrelated to the the ability to output a clock signal based on the system
system clock, such as PWM or ADC. clock or the crystal oscillator on a device pin. The user
The primary oscillator and internal FRC oscillator application can specify a wide range of clock scaling
sources can be used with an Auxiliary PLL (APLL) to prior to outputting the reference clock.
obtain the auxiliary clock. The Auxiliary PLL has a fixed
16x multiplication factor. 9.4 Oscillator Resources
The auxiliary clock has the following configuration Many useful resources are provided on the main prod-
restrictions: uct page of the Microchip website for the devices listed
• For proper PWM operation, auxiliary clock in this data sheet. This product page contains the latest
generation must be configured for 120 MHz (see updates and additional information.
Parameter OS56 in Section 30.0 “Electrical Char-
acteristics”). If a slower frequency is desired, the 9.4.1 KEY RESOURCES
PWM Input Clock Prescaler (Divider) Select bits • “Oscillator Module” (DS70005131) in the
(PCLKDIV<2:0>) should be used. “dsPIC33/PIC24 Family Reference Manual”
• To achieve 1.04 ns PWM resolution, the auxiliary • Code Samples
clock must use the 16x Auxiliary PLL (APLL). All • Application Notes
other clock sources will have a minimum PWM • Software Libraries
resolution of 8 ns.
• Webinars
• If the primary PLL is used as a source for the
auxiliary clock, the primary PLL should be config-
Manual” Sections
ured up to a maximum operation of 30 MIPS or
less. • Development Tools

9.5 Oscillator Control Registers
REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1)
U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y
— COSC2 COSC1 COSC0 — NOSC2(2) NOSC1(2) NOSC0(2)
bit 15 bit 8
R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0

CLKLOCK IOLOCK LOCK — CF(3) — — OSWEN
bit 7 bit 0
Legend: y = Value set from Configuration bits on POR


bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Reserved
011 = Primary Oscillator (XT, HS, EC) with PLL
010 = Primary Oscillator (XT, HS, EC)
001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
000 = Fast RC Oscillator (FRC)
bit 10-8 NOSC<2:0>: New Oscillator Selection bits(2)
111 = Fast RC Oscillator (FRC) with Divide-by-n
110 = Fast RC Oscillator (FRC) with Divide-by-16
100 = Reserved
011 = Primary Oscillator (XT, HS, EC) with PLL
001 = Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
bit 7 CLKLOCK: Clock Lock Enable bit
1 = If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and
PLL configurations may be modified
0 = Clock and PLL selections are not locked, configurations may be modified
bit 6 IOLOCK: I/O Lock Enable bit
1 = I/O lock is active
0 = I/O lock is not active
bit 5 LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Note 1: Writes to this register require an unlock sequence.

2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not
permitted. This applies to clock switches in either direction. In these instances, the application must switch
to FRC mode as a transitional clock source between the two PLL modes.
3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and will trigger an oscillator failure trap.

REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
bit 3 CF: Clock Fail Detect bit(3)
1 = FSCM has detected a clock failure
0 = FSCM has not detected a clock failure
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Requests oscillator switch to the selection specified by the NOSC<2:0> bits
0 = Oscillator switch is complete
Note 1: Writes to this register require an unlock sequence.

2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not
permitted. This applies to clock switches in either direction. In these instances, the application must switch
to FRC mode as a transitional clock source between the two PLL modes.
3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and will trigger an oscillator failure trap.

REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER
ROI DOZE2(1) DOZE1(1) DOZE0(1) DOZEN(2,3) FRCDIV2 FRCDIV1 FRCDIV0
bit 15 bit 8
R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0
bit 7 bit 0
Legend:
bit 15 ROI: Recover on Interrupt bit

1 = Interrupts will clear the DOZEN bit and the processor clock, and the peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits(1)
111 = FCY divided by 128
011 = FCY divided by 8 (default)
bit 11 DOZEN: Doze Mode Enable bit(2,3)
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock and peripheral clock ratio is forced to 1:1
bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divided by 256
000 = FRC divided by 1 (default)
bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output divided by 8
10 = Reserved
01 = Output divided by 4 (default)
00 = Output divided by 2
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.

REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER (CONTINUED)
bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input divided by 33
•
•
•
00001 = Input divided by 3
00000 = Input divided by 2 (default)
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
REGISTER 9-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — PLLDIV8
bit 15 bit 8

PLLDIV<7:0>
bit 7 bit 0
Legend:

bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111 = 513
•
•
•
000110000 = 50 (default)
•
•
•
000000010 = 4
000000001 = 3
000000000 = 2

REGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — TUN<5:0>
bit 7 bit 0
Legend:

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits
011111 = Maximum frequency deviation of 1.457% (7.477 MHz)
011110 = Center frequency + 1.41% (7.474 MHz)
•
•
•
000001 = Center frequency + 0.047% (7.373 MHz)
000000 = Center frequency (7.37 MHz nominal)
111111 = Center frequency – 0.047% (7.367 MHz)
•
•
•
100001 = Center frequency – 1.457% (7.263 MHz)
100000 = Minimum frequency deviation of -1.5% (7.259 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is neither
characterized nor tested.

REGISTER 9-5: ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER
R/W-0 R-0 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1
ENAPLL APLLCK SELACLK — — APSTSCLR2 APSTSCLR1 APSTSCLR0
bit 15 bit 8
R/W-0 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0

ASRCSEL FRCSEL — — — — — —
bit 7 bit 0
Legend:
bit 15 ENAPLL: Auxiliary PLL Enable bit

1 = APLL is enabled
0 = APLL is disabled
bit 14 APLLCK: APLL Locked Status bit (read-only)
1 = Indicates that Auxiliary PLL is in lock
0 = Indicates that Auxiliary PLL is not in lock
bit 13 SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1 = Auxiliary oscillators provide the source clock for the auxiliary clock divider
0 = Primary PLL (FVCO) provides the source clock for the auxiliary clock divider
bit 10-8 APSTSCLR<2:0>: Auxiliary Clock Output Divider bits
111 = Divided by 1
110 = Divided by 2
101 = Divided by 4
100 = Divided by 8
011 = Divided by 16
010 = Divided by 32
001 = Divided by 64
000 = Divided by 256
bit 7 ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit
1 = Primary oscillator is the clock source
0 = No clock input is selected
bit 6 FRCSEL: Select Reference Clock Source for Auxiliary PLL bit
1 = Selects the FRC clock for Auxiliary PLL
0 = Input clock source is determined by the ASRCSEL bit setting

REGISTER 9-6: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ROON — ROSSLP ROSEL RODIV3(1) RODIV2(1) RODIV1(1) RODIV0(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15 ROON: Reference Oscillator Output Enable bit

1 = Reference oscillator output is enabled on the RPn pin(2)
0 = Reference oscillator output is disabled
bit 13 ROSSLP: Reference Oscillator Run in Sleep bit
1 = Reference oscillator output continues to run in Sleep
0 = Reference oscillator output is disabled in Sleep
bit 12 ROSEL: Reference Oscillator Source Select bit
1 = Oscillator crystal is used as the reference clock
0 = System clock is used as the reference clock
bit 11-8 RODIV<3:0>: Reference Oscillator Divider bits(1)
1111 = Reference clock divided by 32,768
1001 = Reference clock divided by 512
0000 = Reference clock
Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
2: This pin is remappable. See Section 11.6 “Peripheral Pin Select (PPS)” for more information.

REGISTER 9-7: LFSR: LINEAR FEEDBACK SHIFT REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— LFSR<14:8>
bit 15 bit 8

LFSR<7:0>
bit 7 bit 0
Legend:

bit 14-0 LFSR<14:0>: Pseudorandom Data bits

10.0 POWER-SAVING FEATURES 10.1 Clock Frequency and Clock
Switching
features of the dsPIC33EPXXXGS70X/ The dsPIC33EPXXXGS70X/80X family devices allow a
80X family of devices. It is not intended wide range of clock frequencies to be selected under
to be a comprehensive reference source. application control. If the system clock configuration is not
To complement the information in this data locked, users can choose low-power or high-precision
sheet, refer to “Watchdog Timer and oscillators by simply changing the NOSCx bits
Power-Saving Modes” (DS70615) in the (OSCCON<10:8>). The process of changing a system
“dsPIC33/PIC24 Family Reference Man- clock during operation, as well as limitations to the
ual”, which is available from the Microchip process, are discussed in more detail in Section 9.0
website (www.microchip.com). “Oscillator Configuration”.
described in this section may not be 10.2 Instruction-Based Power-Saving
available on all devices. Refer to Modes
The dsPIC33EPXXXGS70X/80X family devices have
two special power-saving modes that are entered
through the execution of a special PWRSAV instruc-
The dsPIC33EPXXXGS70X/80X family devices tion. Sleep mode stops clock operation and halts all
provide the ability to manage power consumption by code execution. Idle mode halts the CPU and code
selectively managing clocking to the CPU and the execution, but allows peripheral modules to continue
peripherals. In general, a lower clock frequency and operation. The assembler syntax of the PWRSAV
a reduction in the number of peripherals being instruction is shown in Example 10-1.
clocked constitutes lower consumed power. Note: SLEEP_MODE and IDLE_MODE are con-
dsPIC33EPXXXGS70X/80X family devices can stants defined in the assembler include
manage power consumption in four ways: file for the selected device.
• Clock Frequency Sleep and Idle modes can be exited as a result of an
• Instruction-Based Sleep and Idle modes enabled interrupt, WDT time-out or a device Reset. When
• Software-Controlled Doze mode the device exits these modes, it is said to “wake-up”.
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX

PWRSAV #SLEEP_MODE ; Put the device into Sleep mode
PWRSAV #IDLE_MODE ; Put the device into Idle mode

10.2.1 SLEEP MODE 10.2.2 IDLE MODE
The following occurs in Sleep mode: The following occurs in Idle mode:
• The system clock source is shut down. If an • The CPU stops executing instructions.
on-chip oscillator is used, it is turned off. • The WDT is automatically cleared.
• The device current consumption is reduced to a • The system clock source remains active. By
minimum, provided that no I/O pin is sourcing default, all peripheral modules continue to operate
current. normally from the system clock source, but can
• The Fail-Safe Clock Monitor does not operate, also be selectively disabled (see Section 10.4
since the system clock source is disabled. “Peripheral Module Disable”).
• The LPRC clock continues to run in Sleep mode if • If the WDT or FSCM is enabled, the LPRC also
the WDT is enabled. remains active.
• The WDT, if enabled, is automatically cleared The device wakes from Idle mode on any of these
prior to entering Sleep mode. events:
• Some device features or peripherals can continue • Any interrupt that is individually enabled
to operate. This includes items such as the Input • Any device Reset
Change Notification on the I/O ports or peripherals
• A WDT time-out
that use an external clock input.
• Any peripheral that requires the system clock On wake-up from Idle mode, the clock is reapplied to
source for its operation is disabled. the CPU and instruction execution will begin (two to
four clock cycles later), starting with the instruction
The device wakes up from Sleep mode on any of the following the PWRSAV instruction or the first instruction
these events: in the ISR.
• Any interrupt source that is individually enabled All peripherals also have the option to discontinue
• Any form of device Reset operation when Idle mode is entered to allow for
• A WDT time-out increased power savings. This option is selectable in
On wake-up from Sleep mode, the processor restarts the control register of each peripheral (for example, the
with the same clock source that was active when Sleep TSIDL bit in the Timer1 Control register (T1CON<13>).
mode was entered.
10.2.3 INTERRUPTS COINCIDENT WITH
For optimal power savings, the internal regulator and POWER SAVE INSTRUCTIONS
the Flash regulator can be configured to go into stand-
by when Sleep mode is entered by clearing the VREGS Any interrupt that coincides with the execution of a
(RCON<8>) and VREGSF (RCON<11>) bits (default PWRSAV instruction is held off until entry into Sleep or
configuration). Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
If the application requires a faster wake-up time, and
can accept higher current requirements, the VREGS
(RCON<8>) and VREGSF (RCON<11>) bits can be set
to keep the internal regulator and the Flash regulator
active during Sleep mode.

10.3 Doze Mode 10.4 Peripheral Module Disable
The preferred strategies for reducing power consump- The Peripheral Module Disable (PMD) registers
tion are changing clock speed and invoking one of the provide a method to disable a peripheral module by
power-saving modes. In some circumstances, this stopping all clock sources supplied to that module.
cannot be practical. For example, it may be necessary When a peripheral is disabled using the appropriate
for an application to maintain uninterrupted synchro- PMD control bit, the peripheral is in a minimum power
nous communication, even while it is doing nothing consumption state. The control and status registers
else. Reducing system clock speed can introduce associated with the peripheral are also disabled, so
communication errors, while using a power-saving writes to those registers do not have any effect and
mode can stop communications completely. read values are invalid.
Doze mode is a simple and effective alternative method A peripheral module is enabled only if both the associ-
to reduce power consumption while the device is still ated bit in the PMD register is cleared and the peripheral
executing code. In this mode, the system clock is supported by the specific dsPIC® DSC variant. If the
continues to operate from the same source and at the peripheral is present in the device, it is enabled in the
same speed. Peripheral modules continue to be PMD register by default.
clocked at the same speed, while the CPU clock speed
Note: If a PMD bit is set, the corresponding
is reduced. Synchronization between the two clock
module is disabled after a delay of one
domains is maintained, allowing the peripherals to
instruction cycle. Similarly, if a PMD bit is
access the SFRs while the CPU executes code at a
cleared, the corresponding module is
slower rate.
enabled after a delay of one instruction
Doze mode is enabled by setting the DOZEN bit cycle (assuming the module control regis-
(CLKDIV<11>). The ratio between peripheral and core ters are already configured to enable
clock speed is determined by the DOZE<2:0> bits module operation).
(CLKDIV<14:12>). There are eight possible configu-
rations, from 1:1 to 1:128, with 1:1 being the default
setting.
10.5 Power-Saving Resources
Programs can use Doze mode to selectively reduce Many useful resources are provided on the main prod-
power consumption in event-driven applications. This uct page of the Microchip website for the devices listed
allows clock-sensitive functions, such as synchronous in this data sheet. This product page contains the latest
communications, to continue without interruption while updates and additional information.
the CPU Idles, waiting for something to invoke an inter-
rupt routine. An automatic return to full-speed CPU 10.5.1 KEY RESOURCES
operation on interrupts can be enabled by setting the • “Watchdog Timer and Power-Saving Modes”
ROI bit (CLKDIV<15>). By default, interrupt events (DS70615) in the “dsPIC33/PIC24 Family
have no effect on Doze mode operation. Reference Manual”
• Code Samples
• Webinars
• All related “dsPIC33/PIC24 Family Reference
Manual” Sections

REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
T5MD T4MD T3MD T2MD T1MD — PWMMD —
bit 15 bit 8

I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD C1MD ADCMD
bit 7 bit 0
Legend:
bit 15 T5MD: Timer5 Module Disable bit

1 = Timer5 module is disabled
0 = Timer5 module is enabled
bit 9 PWMMD: PWM Module Disable bit
1 = PWM module is disabled
0 = PWM module is enabled
bit 7 I2C1MD: I2C1 Module Disable bit
1 = I2C1 module is disabled
0 = I2C1 module is enabled
bit 6 U2MD: UART2 Module Disable bit
1 = UART2 module is disabled
0 = UART2 module is enabled
bit 5 U1MD: UART1 Module Disable bit
1 = UART1 module is disabled
0 = UART1 module is enabled
bit 4 SPI2MD: SPI2 Module Disable bit
1 = SPI2 module is disabled
0 = SPI2 module is enabled
bit 2 C2MD: CAN2 Module Disable bit
1 = CAN2 module is disabled
0 = CAN2 module is enabled

REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED)
bit 1 C1MD: CAN1 Module Disable bit
1 = CAN1 module is disabled
0 = CAN1 module is enabled
bit 0 ADCMD: ADC Module Disable bit
1 = ADC module is disabled
0 = ADC module is enabled

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — IC4MD IC3MD IC2MD IC1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — OC4MD OC3MD OC2MD OC1MD
bit 7 bit 0
Legend:

bit 11 IC4MD: Input Capture 4 Module Disable bit
1 = Input Capture 4 module is disabled
0 = Input Capture 4 module is enabled
bit 3 OC4MD: Output Compare 4 Module Disable bit
1 = Output Compare 4 module is disabled
0 = Output Compare 4 module is enabled

U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0
— — — — — CMPMD — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

— — — — — — I2C2MD —
bit 7 bit 0
Legend:

bit 10 CMPMD: Comparator Module Disable bit
1 = Comparator module is disabled
0 = Comparator module is enabled
bit 1 I2C2MD: I2C2 Module Disable bit
1 = I2C2 module is disabled
0 = I2C2 module is enabled

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0

— — — — REFOMD — — —
bit 7 bit 0
Legend:

bit 3 REFOMD: Reference Clock Module Disable bit
1 = Reference clock module is disabled
0 = Reference clock module is enabled

PWM8MD PWM7MD PWM6MD PWM5MD PWM4MD PWM3MD PWM2MD PWM1MD
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — SPI3MD
bit 7 bit 0
Legend:
bit 15 PWM8MD: PWM8 Module Disable bit

1 = PWM8 module is disabled
0 = PWM8 module is enabled

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — CMP4MD CMP3MD CMP2MD CMP1MD
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0

— — — DMAMD PTGMD — PGA1MD —
bit 7 bit 0
Legend:

bit 11 CMP4MD: CMP4 Module Disable bit
1 = CMP4 module is disabled
0 = CMP4 module is enabled
bit 4 DMAMD: DMA Module Disable bit
1 = DMA module is disabled
0 = DMA module is enabled
bit 3 PTGMD: PTG Module Disable bit
1 = PTG module is disabled
0 = PTG module is enabled
bit 1 PGA1MD: PGA1 Module Disable bit
1 = PGA1 module is disabled
0 = PGA1 module is enabled

U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0
— — — — — PGA2MD — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

— — CLC4MD CLC3MD CLC2MD CLC1MD CCSMD —
bit 7 bit 0
Legend:

bit 10 PGA2MD: PGA2 Module Disable bit
1 = PGA2 module is disabled
0 = PGA2 module is enabled
bit 5 CLC4MD: CLC4 Module Disable bit
1 = CLC4 module is disabled
0 = CLC4 module is enabled
bit 1 CCSMD: Constant-Current Source Module Disable bit
1 = Constant-current source module is disabled
0 = Constant-current source module is enabled

11.0 I/O PORTS which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1 illus-
Note 1: This data sheet summarizes the features trates how ports are shared with other peripherals and
of the dsPIC33EPXXXGS70X/80X family the associated I/O pin to which they are connected.
of devices. It is not intended to be a When a peripheral is enabled and the peripheral is
comprehensive reference source. To com- actively driving an associated pin, the use of the pin as a
plement the information in this data sheet, general purpose output pin is disabled. The I/O pin can
refer to “I/O Ports” (DS70000598) in the be read, but the output driver for the parallel port bit is
“dsPIC33/PIC24 Family Reference Man- disabled. If a peripheral is enabled, but the peripheral is
ual”, which is available from the Microchip not actively driving a pin, that pin can be driven by a port.
website (www.microchip.com).
All port pins have eight registers directly associated with
2: Some registers and associated bits their operation as digital I/Os. The Data Direction register
described in this section may not be (TRISx) determines whether the pin is an input or an out-
available on all devices. Refer to put. If the data direction bit is a ‘1’, then the pin is an input.
Section 4.0 “Memory Organization” in All port pins are defined as inputs after a Reset. Reads
this data sheet for device-specific register from the latch (LATx), read the latch. Writes to the latch,
and bit information. write the latch. Reads from the port (PORTx), read the
Many of the device pins are shared among the periph- port pins, while writes to the port pins, write the latch.
erals and the Parallel I/O ports. All I/O input ports feature Any bit and its associated data and control registers
Schmitt Trigger inputs for improved noise immunity. that are not valid for a particular device are disabled.
This means the corresponding LATx and TRISx
11.1 Parallel I/O (PIO) Ports registers, and the port pin are read as zeros. Table 11-1
through Table 11-5 show ANSELx bits’ availability for
Generally, a Parallel I/O port that shares a pin with a device variants.
peripheral is subservient to the peripheral. The
When a pin is shared with another peripheral or func-
peripheral’s output buffer data and control signals are
tion that is defined as an input only, it is nevertheless
provided to a pair of multiplexers. The multiplexers
regarded as a dedicated port because there is no
select whether the peripheral or the associated port
other competing source of outputs.
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
I/O
Peripheral Output Enable
1 Output Enable
Peripheral Output Data
0
PIO Module 1 Output Data

Read TRISx 0
Data Bus
D Q
I/O Pin
WR TRISx
CK
TRISx Latch
D Q
WR LATx +
WR PORTx CK
Data Latch
Read LATx
Input Data
Read PORTx

TABLE 11-1: PORTA PIN AND ANSELA AVAILABILITY
PORTA I/O Pins
Device
RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
dsPIC33EPXXXGSX08 — — — — — — — — — — — X X X X X
dsPIC33EPXXXGS702 — — — — — — — — — — — X X X X X
ANSELA Bit Present — — — — — — — — — — — — — X X X
TABLE 11-2: PORTB PIN AND ANSELB AVAILABILITY

PORTB I/O Pins
Device
RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
dsPIC33EPXXXGSX08 X X X X X — X X X X X X X X X X
dsPIC33EPXXXGS702 X X X X X — X X X X X X X X X X
ANSELB Bit Present — — — — — — X — X X X — X X X X
TABLE 11-3: PORTC PIN AND ANSELC AVAILABILITY

PORTC I/O Pins
Device
RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
dsPIC33EPXXXGSX08 X X X X — X X X X X X X X X X X
dsPIC33EPXXXGSX06 X X X X — X X X X X X X X X X X
dsPIC33EPXXXGSX05 — — X X — X X X X X X X X X X X
dsPIC33EPXXXGSX04 — — X X — X X X X X X X X X X X
dsPIC33EPXXXGS702 — — — — — — — — — — — — — — — —
ANSELC Bit Present — — — X — X X — — X X X — X X —
TABLE 11-4: PORTD PIN AND ANSELD AVAILABILITY

PORTD I/O Pins
Device
RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
dsPIC33EPXXXGSX08 X X X X X X X X X X X X X X X X
dsPIC33EPXXXGSX05 — X — — — X — — — — — X — — — —
dsPIC33EPXXXGSX04 — X — — — X — — — — — X — — — —
dsPIC33EPXXXGS702 — — — — — — — — — — — — — — — —
ANSELD Bit Present — — X — — — — X X — X — — X — —
TABLE 11-5: PORTE PIN AND ANSELE AVAILABILITY

PORTE I/O Pins
Device
RE15 RE14 RE13 RE12 RE11 RE10 RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
dsPIC33EPXXXGSX06 — — — — — — — — — — — — — — — —
dsPIC33EPXXXGSX05 — — — — — — — — — — — — — — — —
dsPIC33EPXXXGSX04 — — — — — — — — — — — — — — — —
dsPIC33EPXXXGS702 — — — — — — — — — — — — — — — —
ANSELE Bit Present — — — — — — — — — — — — — — — —

11.2 I/O Port Control Register Maps
TABLE 11-6: PORTA REGISTER MAP(1)

File
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
TRISA — — — — — — — — — — — TRISA<4:0>
PORTA — — — — — — — — — — — RA<4:0>
LATA — — — — — — — — — — — LATA<4:0>
ODCA — — — — — — — — — — — ODCA<4:0>
CNENA — — — — — — — — — — — CNIEA<4:0>
CNPUA — — — — — — — — — — — CNPUA<4:0>
CNPDA — — — — — — — — — — — CNPDA<4:0>
ANSELA — — — — — — — — — — — — — ANSA<2:0>
Legend: — = unimplemented, read as ‘0’.
Note 1: Refer to Table 11-1 for bit availability on each pin count variant.
TABLE 11-7: PORTB REGISTER MAP(1)

File
Name
TRISB TRISB<15:11> — TRISB<9:0>

PORTB RB<15:11> — RB<9:0>
LATB LATB<15:11> — LATB<9:0>
ODCB ODCB<15:11> — ODCB<9:0>
CNENB CNIEB<15:11> — CNIEB<9:0>
CNPUB CNPUB<15:11> — CNPUB<9:0>
CNPDB CNPDB<15:11> — CNPDB<9:0>
ANSELB — — — — — — ANSB9 — ANSB<7:5> — ANSB<3:0>
DS70005258C-page 129
PORTC REGISTER MAP(1)
DS70005258C-page 130
TABLE 11-8:
File
Name
TRISC TRISC<15:12> — TRISC<10:0>

PORTC RC<15:12> — RC<10:0>
LATC LATC<15:12> — LATC<10:0>
ODCC ODCC<15:12> — ODCC<10:0>
CNENC CNIEC<15:12> — CNIEC<10:0>
CNPUC CNPUC<15:12> — CNPUC<10:0>
CNPDC CNPDC<15:12> — CNPDC<10:0>
ANSELC — — — ANSC12 — ANSC<10:9> — — ANSC<6:4> — ANSC<2:1> —
TABLE 11-9: PORTD REGISTER MAP(1)

File
Name
TRISD TRISD<15:0>
PORTD RD<15:0>
LATD LATD<15:0>
ODCD ODCD<15:0>
CNEND CNIED<15:0>
CNPUD CNPUD<15:0>
CNPDD CNPDD<15:0>
ANSELD — — ANSD13 — — — — ANSD<8:7> — ANSD5 — — ANSD2 — —

TABLE 11-10: PORTE REGISTER MAP(1)
File
Name
TRISE TRISE<15:0>
PORTE RE<15:0>
LATE LATE<15:0>
ODCE ODCE<15:0>
CNENE CNIEE<15:0>
CNPUE CNPUE<15:0>
CNPDE CNPDE<15:0>
ANSELE — — — — — — — — — — — — — — — —
DS70005258C-page 131
11.2.1 OPEN-DRAIN CONFIGURATION 11.3.1 I/O PORT WRITE/READ TIMING
In addition to the PORTx, LATx and TRISx registers One instruction cycle is required between a port
for data control, port pins can also be individually direction change or port write operation and a read
configured for either digital or open-drain output. This operation of the same port. Typically, this instruction
is controlled by the Open-Drain Control x register, would be a NOP, as shown in Example 11-1.
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an 11.4 Input Change Notification (ICN)
open-drain output.
The Input Change Notification function of the I/O ports
The open-drain feature allows the generation of out-
allows devices to generate interrupt requests to the
puts other than VDD by using external pull-up resistors.
processor in response to a Change-of-State (COS) on
The maximum open-drain voltage allowed on any pin
selected input pins. This feature can detect input
is the same as the maximum VIH specification for that
Change-of-States, even in Sleep mode, when the
particular pin. See the “Pin Diagrams” section for the
clocks are disabled. Every I/O port pin can be selected
available 5V tolerant pins and Table 30-11 for the
(enabled) for generating an interrupt request on a
maximum VIH specification for each pin.
Change-of-State.
11.3 Configuring Analog and Digital Three control registers are associated with the ICN
functionality of each I/O port. The CNENx registers
Port Pins contain the ICN interrupt enable control bits for each of
The ANSELx register controls the operation of the the input pins. Setting any of these bits enables an ICN
analog port pins. The port pins that are to function as interrupt for the corresponding pins.
analog inputs or outputs must have their corresponding Each I/O pin also has a weak pull-up and a weak
ANSELx and TRISx bits set. In order to use port pins for pull-down connected to it. The pull-ups and pull-
I/O functionality with digital modules, such as timers, downs act as a current source, or sink source,
UARTs, etc., the corresponding ANSELx bit must be connected to the pin, and eliminate the need for
cleared. external resistors when push button or keypad
The ANSELx register has a default value of 0xFFFF; devices are connected. The pull-ups and pull-downs
therefore, all pins that share analog functions are are enabled separately, using the CNPUx and the
analog (not digital) by default. CNPDx registers, which contain the control bits for
each of the pins. Setting any of the control bits
Pins with analog functions affected by the ANSELx
enables the weak pull-ups and/or pull-downs for the
registers are listed with a buffer type of analog in the
corresponding pins.
Pinout I/O Descriptions (see Table 1-1). Table 11-1
through Table 11-5 show ANSELx bits’ availability for Note: Pull-ups and pull-downs on Input Change
device variants. Notification pins should always be
If the TRISx bit is cleared (output) while the ANSELx bit disabled when the port pin is configured
is set, the digital output level (VOH or VOL) is converted as a digital output.
by an analog peripheral, such as the ADC module or
comparator module. EXAMPLE 11-1: PORT WRITE/READ
When the PORTx register is read, all pins configured as EXAMPLE
analog input channels are read as cleared (a low level). MOV 0xFF00, W0 ; Configure PORTB<15:8>
; as inputs
Pins configured as digital inputs do not convert an
MOV W0, TRISB ; and PORTB<7:0>
analog input. Analog levels on any pin, defined as a
; as outputs
digital input (including the ANx pins), can cause the NOP ; Delay 1 cycle
input buffer to consume current that exceeds the BTSS PORTB, #13 ; Next Instruction
device specifications.

11.5 I/O Port Control Registers
REGISTER 11-1: TRISx: PORTx DATA DIRECTION CONTROL REGISTER(1)

TRISx<15:8>
bit 15 bit 8

TRISx<7:0>
bit 7 bit 0
Legend:
bit 15-8 TRISx<15:0>: PORTx Data Direction Control bits

1 = The pin is an input
0 = The pin is an output
Note 1: See Table 11-1, Table 11-2, Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
REGISTER 11-2: PORTx: I/O PORTx REGISTER(1)

PORTx<15:8>
bit 15 bit 8

PORTx<7:0>
bit 7 bit 0
Legend:
bit 15-8 PORTx<15:0>: I/O PORTx bits

1 = The pin data is ‘1’
0 = The pin data is ‘0’

REGISTER 11-3: LATx: PORTx DATA LATCH REGISTER(1)
LATx<15:8>
bit 15 bit 8

LATx<7:0>
bit 7 bit 0
Legend:
bit 15-8 LATx<15:0>: PORTx Data Latch bits

1 = The latch content is ‘1’
0 = The latch content is ‘0’
REGISTER 11-4: ODCx: PORTx OPEN-DRAIN CONTROL REGISTER(1)

ODCx<15:8>
bit 15 bit 8

ODCx<7:0>
bit 7 bit 0
Legend:
bit 15-8 PORTx<15:0>: PORTx Open-Drain Control bits

1 = The pin acts as an open-drain output pin if TRISx is ‘0’
0 = The pin acts as a normal pin

REGISTER 11-5: CNENx: INPUT CHANGE NOTIFICATION INTERRUPT ENABLE x REGISTER(1)
CNIEx<15:8>
bit 15 bit 8

CNIEx<7:0>
bit 7 bit 0
Legend:
bit 15-8 CNIEx<15:0>: Input Change Notification Interrupt Enable x bits

1 = Enables interrupt on input change
0 = Disables interrupt on input change
REGISTER 11-6: CNPUx: INPUT CHANGE NOTIFICATION PULL-UP ENABLE x REGISTER(1)

CNPUx<15:8>
bit 15 bit 8

CNPUx<7:0>
bit 7 bit 0
Legend:
bit 15-8 CNPUx<15:0>: Input Change Notification Pull-up Enable bits

1 = Enables pull-up on PORTx pin
0 = Disables pull-up on PORTx pin

REGISTER 11-7: CNPDx: INPUT CHANGE NOTIFICATION PULL-DOWN ENABLE x REGISTER(1)

CNPDx<15:8>
bit 15 bit 8

CNPDx<7:0>
bit 7 bit 0
Legend:
bit 15-8 CNPDx<15:0>: Input Change Notification Pull-Down Enable x bits

1 = Enables pull-down on PORTx pin
0 = Disables pull-down on PORTx pin
REGISTER 11-8: ANSELx: ANALOG SELECT CONTROL x REGISTER(1)

ANSx<15:8>
bit 15 bit 8

ANSx<7:0>
bit 7 bit 0
Legend:
bit 15-8 ANSx<15:0>: Analog PORTx Enable bits

1 = Enables analog PORTx pin
0 = Enables digital PORTx pin

11.6 Peripheral Pin Select (PPS) In comparison, some digital only peripheral modules
are never included in the Peripheral Pin Select feature.
A major challenge in general purpose devices is This is because the peripheral’s function requires
providing the largest possible set of peripheral features, special I/O circuitry on a specific port and cannot be
while minimizing the conflict of features on I/O pins. easily connected to multiple pins. One example
The challenge is even greater on low pin count devices. includes I2C modules. A similar requirement excludes
In an application where more than one peripheral all modules with analog inputs, such as the ADC
needs to be assigned to a single pin, inconvenient Converter.
work arounds in application code, or a complete
redesign, may be the only option. A key difference between remappable and non-
remappable peripherals is that remappable peripherals
Peripheral Pin Select configuration provides an alter- are not associated with a default I/O pin. The peripheral
native to these choices by enabling peripheral set must always be assigned to a specific I/O pin before it
selection and placement on a wide range of I/O pins. can be used. In contrast, non-remappable peripherals
By increasing the pinout options available on a particu- are always available on a default pin, assuming that the
lar device, users can better tailor the device to their peripheral is active and not conflicting with another
entire application, rather than trimming the application peripheral.
to fit the device.
When a remappable peripheral is active on a given I/O
The Peripheral Pin Select configuration feature pin, it takes priority over all other digital I/Os and digital
operates over a fixed subset of digital I/O pins. Users communication peripherals associated with the pin.
may independently map the input and/or output of most Priority is given regardless of the type of peripheral that
digital peripherals to any one of these I/O pins. Hard- is mapped. Remappable peripherals never take priority
ware safeguards are included that prevent accidental over any analog functions associated with the pin.
or spurious changes to the peripheral mapping once it
has been established. 11.6.3 CONTROLLING PERIPHERAL PIN
SELECT
11.6.1 AVAILABLE PINS
Peripheral Pin Select features are controlled through
The number of available pins is dependent on the par- two sets of SFRs: one to map peripheral inputs and one
ticular device and its pin count. Pins that support the to map outputs. Because they are separately con-
Peripheral Pin Select feature include the label, “RPn”, trolled, a particular peripheral’s input and output (if the
in their full pin designation, where “n” is the remappable peripheral has both) can be placed on any selectable
pin number. “RP” is used to designate pins that support function pin without constraint.
both remappable input and output functions.
The association of a peripheral to a peripheral-
11.6.2 AVAILABLE PERIPHERALS selectable pin is handled in two different ways,
depending on whether an input or output is being
The peripherals managed by the Peripheral Pin Select
mapped.
are all digital only peripherals. These include general
serial communications (UART and SPI), general pur-
pose timer clock inputs, timer-related peripherals (input
capture and output compare) and interrupt-on-change
inputs.

11.6.4 INPUT MAPPING 11.6.4.1 Virtual Connections
The inputs of the Peripheral Pin Select options are The dsPIC33EPXXXGS70X/80X devices support six
mapped on the basis of the peripheral. That is, a control virtual RPn pins (RP176-RP181), which are identical in
register associated with a peripheral dictates the pin it functionality to all other RPn pins, with the exception of
will be mapped to. The RPINRx registers are used to pinouts. These six pins are internal to the devices and
configure peripheral input mapping (see Register 11-9 are not connected to a physical device pin.
through Register 11-32). Each register contains sets of These pins provide a simple way for inter-peripheral
8-bit fields, with each set associated with one of the connection without utilizing a physical pin. For
remappable peripherals. Programming a given periph- example, the output of the analog comparator can be
eral’s bit field with an appropriate 8-bit index value maps connected to RP176 and the PWM Fault input can be
the RPn pin with the corresponding value, or internal configured for RP176 as well. This configuration allows
signal, to that peripheral. See Table 11-11 for a list of the analog comparator to trigger PWM Faults without
available inputs. the use of an actual physical pin on the device.
For example, Figure 11-2 illustrates remappable pin
selection for the U1RX input. TABLE 11-11: REMAPPABLE SOURCES
Remap Index Output Function
FIGURE 11-2: REMAPPABLE INPUT FOR
U1RX 0 VSS
1 CMP1
U1RXR<7:0>
2 CMP2
VSS 0 3 CMP3
4 CMP4
5 PWM4H
PWM4L 15
U1RX Input 6 PTGO30
to Peripheral 7 PTGO31
8-11 Reserved
16
RP16 12 REFO
13 SYNCO1
14 SYNCO2
181
RP181 15 PWM4L
16-20 RP16-RP20
Note: For input only, Peripheral Pin Select func- 21-31 Reserved
tionality does not have priority over TRISx
settings. Therefore, when configuring an 32-41 RP32-RP41
RPn pin for input, the corresponding bit in 42 Reserved
the TRISx register must also be configured
43-58 RP43-RP58
for input (set to ‘1’).
59 Reserved
60-76 RP60-RP76
77-175 Reserved
176-181 RP176-RP181

TABLE 11-12: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)
Input Name(1) Function Name Register Configuration Bits
External Interrupt 1 INT1 RPINR0 INT1R<7:0>
External Interrupt 2 INT2 RPINR1 INT2R<7:0>
Timer1 External Clock T1CK RPINR2 T1CKR<7:0>
Input Capture 1 IC1 RPINR7 IC1R<7:0>
Output Compare Fault A OCFA RPINR11 OCFAR<7:0>
PWM Fault 1 FLT1 RPINR12 FLT1R<7:0>
UART1 Receive U1RX RPINR18 U1RXR<7:0>
UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<7:0>
UART2 Receive U2RX RPINR19 U2RXR<7:0>
UART2 Clear-to-Send U2CTS RPINR19 U2CTSR<7:0>
SPI1 Data Input SDI1 RPINR20 SDI1R<7:0>
SPI1 Clock Input SCK1 RPINR20 SCK1R<7:0>
SPI1 Slave Select SS1 RPINR21 SS1R<7:0>
CAN1 Receive C1RX PRINR26 C1RXR<7:0>
CAN2 Receive C2RX PRINR26 C2RXR<7:0>
PWM Synchronous Input 1 SYNCI1 RPINR37 SYNCI1R<7:0>
PWM Synchronous Input 2 SYNCI2 RPINR38 SYNCI2R<7:0>
CLC Input A CLCINA RPINR45 CLCINA<7:0>
CLC Input B CLCINB RPINR46 CLCINB<7:0>
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

11.6.5 OUTPUT MAPPING 11.6.5.1 Mapping Limitations
In contrast to inputs, the outputs of the Peripheral Pin The control schema of the peripheral select pins is not
Select options are mapped on the basis of the pin. In limited to a small range of fixed peripheral configura-
this case, a control register associated with a particular tions. There are no mutual or hardware-enforced
pin dictates the peripheral output to be mapped. The lockouts between any of the peripheral mapping SFRs.
RPORx registers are used to control output mapping. Literally any combination of peripheral mappings,
Each register contains sets of 6-bit fields, with each set across any or all of the RPn pins, is possible. This
associated with one RPn pin (see Register 11-33 includes both many-to-one and one-to-many mappings
through Register 11-56). The value of the bit field cor- of peripheral inputs, and outputs to pins. While such
responds to one of the peripherals and that peripheral’s mappings may be technically possible from a configu-
output is mapped to the pin (see Table 11-13 and ration point of view, they may not be supportable from
Figure 11-3). an electrical point of view.
A null output is associated with the output register
Reset value of ‘0’. This is done to ensure that remap-
pable outputs remain disconnected from all output pins
by default.
FIGURE 11-3: MULTIPLEXING REMAPPABLE

OUTPUTS FOR RPn
RPnR<6:0>
Default
0
U1TX Output
1
SDO2 Output
2
RPn
Output Data
CLC3OUT Output
65
CLC4OUT Output
66

TABLE 11-13: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)
Function RPnR<6:0> Output Name
Default PORT 0000000 RPn tied to Default Pin
U1TX 0000001 RPn tied to UART1 Transmit
U1RTS 0000010 RPn tied to UART1 Request-to-Send
U2TX 0000011 RPn tied to UART2 Transmit
U2RTS 0000100 RPn tied to UART2 Request-to-Send
SDO1 0000101 RPn tied to SPI1 Data Output
SCK1 0000110 RPn tied to SPI1 Clock Output
SS1 0000111 RPn tied to SPI1 Slave Select
C1TX 0001110 RPn tied to CAN1 Transmit
C2TX 0001111 RPn tied to CAN2 Transmit
OC1 0010000 RPn tied to Output Compare 1 Output
ACMP1 0011000 RPn tied to Analog Comparator 1 Output
SYNCO1 0101101 RPn tied to PWM Primary Master Time Base Sync Output
SYNCO2 0101110 RPn tied to PWM Secondary Master Time Base Sync Output
REFCLKO 0110001 RPn tied to Reference Clock Output
PWM4H 0110011 RPn tied to PWM Output Pins Associated with PWM Generator 4
PWM4L 0110100 RPn tied to PWM Output Pins Associated with PWM Generator 4
CLC1OUT 0111111 RPn tied to CLC1 Output
CLC2OUT 1000000 RPn tied to CLC2 Output
CLC3OUT(1) 1000001 RPn tied to CLC3 Output
CLC4OUT(1) 1000010 RPn tied to CLC4 Output
Note 1: PPS outputs are only available on dsPIC33EPXXXGS702 (28-pin) devices.

11.7 I/O Helpful Tips 3. Most I/O pins have multiple functions. Referring to
the device pin diagrams in this data sheet, the prior-
1. In some cases, certain pins, as defined in
ities of the functions allocated to any pins are
Table 30-11 under “Injection Current”, have internal
indicated by reading the pin name from left-to-right.
protection diodes to VDD and VSS. The term,
The left most function name takes precedence over
“Injection Current”, is also referred to as “Clamp
any function to its right in the naming convention.
Current”. On designated pins, with sufficient external
For example: AN16/T2CK/T7CK/RC1; this indi-
current-limiting precautions by the user, I/O pin
cates that AN16 is the highest priority in this
input voltages are allowed to be greater or less
example and will supersede all other functions to its
than the data sheet absolute maximum ratings,
right in the list. Those other functions to its right,
with respect to the VSS and VDD supplies. Note
even if enabled, would not work as long as any
that when the user application forward biases
other function to its left was enabled. This rule
either of the high or low-side internal input clamp
applies to all of the functions listed for a given pin.
diodes, that the resulting current being injected
into the device, that is clamped internally by the 4. Each pin has an internal weak pull-up resistor and
VDD and VSS power rails, may affect the ADC pull-down resistor that can be configured using the
accuracy by four to six counts. CNPUx and CNPDx registers, respectively. These
resistors eliminate the need for external resistors
2. I/O pins that are shared with any analog input pin
in certain applications. The internal pull-up is up to
(i.e., ANx) are always analog pins, by default, after
~(VDD – 0.8), not VDD. This value is still above the
any Reset. Consequently, configuring a pin as an
minimum VIH of CMOS and TTL devices.
analog input pin automatically disables the digital
input pin buffer and any attempt to read the digital 5. When driving LEDs directly, the I/O pin can source
input level by reading PORTx or LATx will always or sink more current than what is specified in the
return a ‘0’, regardless of the digital logic level on VOH/IOH and VOL/IOL DC characteristics specifica-
the pin. To use a pin as a digital I/O pin on a shared tion. The respective IOH and IOL current rating only
ANx pin, the user application needs to configure the applies to maintaining the corresponding output at
Analog Pin Configuration registers (i.e., ANSELx) in or above the VOH, and at or below the VOL levels.
the I/O ports module by setting the appropriate bit However, for LEDs, unlike digital inputs of an exter-
that corresponds to that I/O port pin to a ‘0’. nally connected device, they are not governed by
the same minimum VIH/VIL levels. An I/O pin output
Note: Although it is not possible to use a digital can safely sink or source any current less than that
input pin when its analog function is listed in the Absolute Maximum Ratings in
enabled, it is possible to use the digital I/O Section 30.0 “Electrical Characteristics”of this
output function, TRISx = 0x0, while the data sheet. For example:
analog function is also enabled. However, VOH = 2.4V @ IOH = -8 mA and VDD = 3.3V
this is not recommended, particularly if the
The maximum output current sourced by any 8 mA
analog input is connected to an external
I/O pin = 12 mA.
analog voltage source, which would
create signal contention between the LED source current < 12 mA is technically permitted.
analog signal and the output pin driver. Refer to the VOH/IOH graphs in Section 31.0 “DC
and AC Device Characteristics Graphs” for
additional information.

6. The Peripheral Pin Select (PPS) pin mapping rules 11.8 I/O Ports Resources
are as follows:
Many useful resources are provided on the main prod-
a) Only one “output” function can be active on a
uct page of the Microchip website for the devices listed
given pin at any time, regardless if it is a
in this data sheet. This product page contains the latest
dedicated or remappable function (one pin,
updates and additional information.
one output).
b) It is possible to assign a “remappable output” 11.8.1 KEY RESOURCES
function to multiple pins and externally short or
tie them together for increased current drive. • “I/O Ports” (DS70000598) in the “dsPIC33/PIC24
Family Reference Manual”
c) If any “dedicated output” function is enabled
on a pin, it will take precedence over any • Code Samples
remappable “output” function. • Application Notes
d) If any “dedicated digital” (input or output) func- • Software Libraries
tion is enabled on a pin, any number of “input” • Webinars
remappable functions can be mapped to the • All Related “dsPIC33/PIC24 Family Reference
same pin. Manual” Sections
e) If any “dedicated analog” function(s) are • Development Tools
enabled on a given pin, “digital input(s)” of any
kind will all be disabled, although a single “dig-
ital output”, at the user’s cautionary discretion,
can be enabled and active as long as there is
no signal contention with an external analog
input signal. For example, it is possible for the
ADC to convert the digital output logic level, or
to toggle a digital output on a comparator or
ADC input, provided there is no external
analog input, such as for a built-in self-test.
f) Any number of “input” remappable functions
can be mapped to the same pin(s) at the same
time, including to any pin with a single output
from either a dedicated or remappable “output”.
g) The TRISx registers control only the digital I/O
output buffer. Any other dedicated or remap-
pable active “output” will automatically override
the TRISx setting. The TRISx register does not
control the digital logic “input” buffer. Remap-
pable digital “inputs” do not automatically
override TRISx settings, which means that the
TRISx bit must be set to input for pins with only
remappable input function(s) assigned.
h) All analog pins are enabled by default after any
Reset and the corresponding digital input buffer
on the pin has been disabled. Only the Analog
Pin Select (ANSELx) registers control the digi-
tal input buffer, not the TRISx register. The user
must disable the analog function on a pin using
the Analog Pin Select registers in order to use
any “digital input(s)” on a corresponding pin, no
exceptions.

11.9 Peripheral Pin Select Registers
REGISTER 11-9: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0

INT1R7 INT1R6 INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 INT1R<7:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

INT2R7 INT2R6 INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0
bit 7 bit 0
Legend:

bit 7-0 INT2R<7:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits

T1CKR7 T1CKR6 T1CKR5 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 T1CKR<7:0>: Assign Timer1 External Clock (T1CK) to the Corresponding RPn Pin bits

bit 15 bit 8

bit 7 bit 0
Legend:

IC2R7 IC2R6 IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-8 IC2R<7:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits

bit 15 bit 8

bit 7 bit 0
Legend:

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

OCFAR7 OCFAR6 OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0
bit 7 bit 0
Legend:

bit 7-0 OCFAR<7:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits

FLT2R7 FLT2R6 FLT2R5 FLT2R4 FLT2R3 FLT2R2 FLT2R1 FLT2R0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-8 FLT2R<7:0>: Assign PWM Fault 2 (FLT2) to the Corresponding RPn Pin bits

bit 15 bit 8

bit 7 bit 0
Legend:

U1CTSR7 U1CTSR6 U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0
bit 15 bit 8

U1RXR7 U1RXR6 U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0
bit 7 bit 0
Legend:
bit 15-8 U1CTSR<7:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits
bit 7-0 U1RXR<7:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits

U2CTSR7 U2CTSR6 U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0
bit 15 bit 8

U2RXR7 U2RXR6 U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0
bit 7 bit 0
Legend:
bit 15-8 U2CTSR<7:0>: Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn Pin bits
bit 7-0 U2RXR<7:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits

SCK1INR7 SCK1INR6 SCK1INR5 SCK1INR4 SCK1INR3 SCK1INR2 SCK1INR1 SCK1INR0
bit 15 bit 8

SDI1R7 SDI1R6 SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0
bit 7 bit 0
Legend:
bit 15-8 SCK1INR<7:0>: Assign SPI1 Clock Input (SCK1) to the Corresponding RPn Pin bits
bit 7-0 SDI1R<7:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

SS1R7 SS1R6 SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0
bit 7 bit 0
Legend:

bit 7-0 SS1R<7:0>: Assign SPI1 Slave Select (SS1) to the Corresponding RPn Pin bits

SCK2INR7 SCK2INR6 SCK2INR5 SCK2INR4 SCK2INR3 SCK2INR2 SCK2INR1 SCK2INR0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-8 SCK2INR<7:0>: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

bit 7 bit 0
Legend:


C2RXR7 C2RXR6 C2RXR5 C2RXR4 C2RXR3 C2RXR2 C2RXR1 C2RXR0
bit 15 bit 8

C1RXR7 C1RXR6 C1RXR5 C1RXR4 C1RXR3 C1RXR2 C1RXR1 C1RXR0
bit 7 bit 0
Legend:
bit 15-8 C2RXR<7:0>: Assign CAN2 Receive (C2RX) to the Corresponding RPn Pin bits
bit 7-0 C1RXR<7:0>: Assign CAN1 Receive (C1RX) to the Corresponding RPn Pin bits


SCK3R7 SCK3R6 SCK3R5 SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-8 SCK3R<7:0>: Assign SPI3 Clock Input (SCK3) to the Corresponding RPn Pin bits

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

bit 7 bit 0
Legend:



SYNCI1R7 SYNCI1R6 SYNCI1R5 SYNCI1R4 SYNCI1R3 SYNCI1R2 SYNCI1R1 SYNCI1R0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 SYNCI1R<7:0>: Assign PWM Synchronization Input 1 (SYNCI1) to the Corresponding RPn Pin bits

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

SYNCI2R7 SYNCI2R6 SYNCI2R5 SYNCI2R4 SYNCI2R3 SYNCI2R2 SYNCI2R1 SYNCI2R0
bit 7 bit 0
Legend:

bit 7-0 SYNCI2R<7:0>: Assign PWM Synchronization Input 2 (SYNCI2) to the Corresponding RPn Pin bits

bit 15 bit 8

bit 7 bit 0
Legend:

bit 15 bit 8

bit 7 bit 0
Legend:

CLCINAR7 CLCINAR6 CLCINAR5 CLCINAR4 CLCINAR3 CLCINAR2 CLCINAR1 CLCINAR0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:
bit 15-8 CLCINAR<7:0>: Assign CLC Input A (CLCINA) to the Corresponding RPn Pin bits

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

CLCINBR7 CLCINBR6 CLCINBR5 CLCINBR4 CLCINBR3 CLCINBR2 CLCINBR1 CLCINBR0
bit 7 bit 0
Legend:

bit 7-0 CLCINBR<7:0>: Assign CLC Input B (CLCINB) to the Corresponding RPn Pin bits

REGISTER 11-33: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
— RP17R6 RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0
bit 15 bit 8

bit 7 bit 0
Legend:

bit 14-8 RP17R<6:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits
(see Table 11-13 for peripheral function numbers)

bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


bit 15 bit 8

bit 7 bit 0
Legend:


NOTES:

12.0 TIMER1 The Timer1 module can operate in one of the following
modes:
Note 1: This data sheet summarizes the • Timer mode
• Gated Timer mode
80X family of devices. It is not intended to
• Synchronous Counter mode
complement the information in this data • Asynchronous Counter mode
sheet, refer to “Timers” (DS70362) in the In Timer and Gated Timer modes, the input clock is
“dsPIC33/PIC24 Family Reference Man- derived from the internal instruction cycle clock (FCY).
ual”, which is available from the Microchip In Synchronous and Asynchronous Counter modes,
website (www.microchip.com). the input clock is derived from the external clock input
2: Some registers and associated bits at the T1CK pin.
described in this section may not be The Timer modes are determined by the following bits:
available on all devices. Refer to • Timer1 Clock Source Select bit (TCS): T1CON<1>
• Timer1 External Clock Input Synchronization Select
bit (TSYNC): T1CON<2>
• Timer1 Gated Time Accumulation Enable bit
The Timer1 module is a 16-bit timer that can operate as (TGATE): T1CON<6>
a free-running interval timer/counter. Timer control bit settings for different operating modes
The Timer1 module has the following unique features are provided in Table 12-1.
over other timers:
• Can be Operated in Asynchronous Counter mode TABLE 12-1: TIMER1 MODE SETTINGS
from an External Clock Source Mode TCS TGATE TSYNC
• The External Clock Input (T1CK) can Optionally be
Timer 0 0 x
Synchronized to the Internal Device Clock and the
Clock Synchronization is Performed after the Gated Timer 0 1 x
prescaler Synchronous 1 x 1
A block diagram of Timer1 is shown in Figure 12-1. Counter
Asynchronous 1 x 0
Counter
FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Gate Falling Edge

1
Sync Detect
Set T1IF Flag
0
(1)
FP Prescaler 10 T1CLK
(/n) TGATE
Reset Data
00 TMR1 Latch
TCKPS<1:0>
0 CLK ADC Trigger
T1CK x1
Prescaler Equal
Sync 1 Comparator
(/n)
TGATE
TSYNC
TCKPS<1:0> TCS
PR1
Note 1: FP is the peripheral clock.

12.1 Timer1 Resources 12.1.1 KEY RESOURCES
Many useful resources are provided on the main prod- • “Timers” (DS70362) in the “dsPIC33/PIC24
uct page of the Microchip website for the devices listed Family Reference Manual”
• Webinars
Manual” Sections

12.2 Timer1 Control Register
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(1) — TSIDL — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0

— TGATE TCKPS1 TCKPS0 — TSYNC(1) TCS(1) —
bit 7 bit 0
Legend:
bit 15 TON: Timer1 On bit(1)

1 = Starts 16-bit Timer1
0 = Stops 16-bit Timer1
bit 13 TSIDL: Timer1 Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit(1)
When TCS = 1:
1 = Synchronizes external clock input
0 = Does not synchronize external clock input
When TCS = 0:
bit 1 TCS: Timer1 Clock Source Select bit(1)
1 = External clock is from pin, T1CK (on the rising edge)
0 = Internal clock (FP)
Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any
attempts by user software to write to the TMR1 register are ignored.

NOTES:

13.0 TIMER2/3 AND TIMER4/5 Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
Note 1: This data sheet summarizes the features of features listed previously, except for the event trigger;
the dsPIC33EPXXXGS70X/80X family of this is implemented only with Timer2/3. The operating
devices. It is not intended to be a modes and enabled features are determined by setting
comprehensive reference source. To com- the appropriate bit(s) in the T2CON, T3CON, T4CON
plement the information in this data sheet, and T5CON registers. T2CON and T4CON are shown
refer to “Timers” (DS70362) in the in generic form in Register 13-1. T3CON and T5CON
“dsPIC33/PIC24 Family Reference Man- are shown in Register 13-2.
ual”, which is available from the Microchip For 32-bit timer/counter operation, Timer2 and Timer4
website (www.microchip.com). are the least significant word (lsw); Timer3 and Timer5
2: Some registers and associated bits are the most significant word (msw) of the 32-bit timers.
Note: For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
The Timer2/3 and Timer4/5 modules are 32-bit timers, modules, but an interrupt is generated
which can also be configured as four independent with the Timer3 and Timer5 interrupt flags.
16-bit timers with selectable operating modes. A block diagram for an example 32-bit timer pair
As 32-bit timers, Timer2/3 and Timer4/5 operate in (Timer2/3 and Timer4/5) is shown in Figure 13-2.
three modes:
• Two Independent 16-Bit Timers (e.g., Timer2 and 13.1 Timer Resources
Timer3) with all 16-Bit Operating modes (except
Many useful resources are provided on the main prod-
Asynchronous Counter mode)
• Single 32-Bit Timer in this data sheet. This product page contains the latest
• Single 32-Bit Synchronous Counter updates and additional information.
They also support these features:
13.1.1 KEY RESOURCES
• Timer Gate Operation
• “Timers” (DS70362) in the “dsPIC33/PIC24
• Selectable Prescaler Settings
Family Reference Manual”
• Timer Operation during Idle and Sleep modes
• Code Samples
• Interrupt on a 32-Bit Period Register Match
• Time Base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
• Webinars
Manual” Sections

FIGURE 13-1: TIMERx BLOCK DIAGRAM (x = 2 THROUGH 5)
Gate Falling Edge

1
Sync Detect
Set TxIF Flag
FP(1) Prescaler 10
TxCLK
(/n) TGATE
Reset Data
00 TMRx Latch
TCKPS<1:0>
CLK
TxCK
Prescaler ADC
Sync x1 Trigger(2)
(/n) Equal
Comparator
TCKPS<1:0> TGATE
TCS
PRx
Note 1: FP is the peripheral clock.

2: The ADC trigger is only available on TMR2.
FIGURE 13-2: TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)
Gate Falling Edge

1
Sync Detect
Set TyIF Flag
PRx PRy
0
TGATE
Equal
Comparator
Data
FP(1) Prescaler 10
(/n) CLK
lsw msw Latch
Reset
00 TMRx TMRy
TCKPS<1:0>
TxCK
Prescaler
Sync x1
(/n)
TMRyHLD
TCKPS<1:0> TGATE
TCS
Data Bus<15:0>
Note 1: Timerx is a Type B timer (x = 2 and 4).

2: Timery is a Type C timer (y = 3 and 5).

13.2 Timer2/3 and Timer4/5 Control Registers
REGISTER 13-1: TxCON: (TIMER2 AND TIMER4) CONTROL REGISTER

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON — TSIDL — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0

— TGATE TCKPS1 TCKPS0 T32 — TCS(1) —
bit 7 bit 0
Legend:
bit 15 TON: Timerx On bit

When T32 = 1:
1 = Starts 32-bit Timerx/y
0 = Stops 32-bit Timerx/y
When T32 = 0:
1 = Starts 16-bit Timerx
0 = Stops 16-bit Timerx
bit 13 TSIDL: Timerx Stop in Idle Mode bit
bit 6 TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
When TCS = 0:
bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3 T32: 32-Bit Timer Mode Select bit
1 = Timerx and Timery form a single 32-bit timer
0 = Timerx and Timery act as two 16-bit timers
bit 1 TCS: Timerx Clock Source Select bit(1)
1 = External clock is from pin, TxCK (on the rising edge)
Note 1: The TxCK pin is not available on all devices. Refer to the “Pin Diagrams” section for the available pins.

REGISTER 13-2: TyCON: (TIMER3 AND TIMER5) CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
TON(1) — TSIDL(2) — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0

— TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,3) —
bit 7 bit 0
Legend:
bit 15 TON: Timery On bit(1)

1 = Starts 16-bit Timery
0 = Stops 16-bit Timery
bit 13 TSIDL: Timery Stop in Idle Mode bit(2)
bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
When TCS = 0:
bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(1)
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 1 TCS: Timery Clock Source Select bit(1,3)
1 = External clock is from pin, TyCK (on the rising edge)
Note 1: When 32-bit operation is enabled (TxCON<3> = 1), these bits have no effect on Timery operation; all timer
functions are set through TxCON.
2: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
3: The TyCK pin is not available on all devices. See the “Pin Diagrams” section for the available pins.

14.0 INPUT CAPTURE Key features of the input capture module include:
• Hardware-Configurable for 32-Bit Operation in All
Note 1: This data sheet summarizes the modes by Cascading Two Adjacent modules
features of the dsPIC33EPXXXGS70X/ • Synchronous and Trigger modes of Output
80X family of devices. It is not intended Compare Operation, with up to 21 User-Selectable
to be a comprehensive reference Trigger/Sync Sources available
source. To complement the information • A 4-Level FIFO Buffer for Capturing and Holding
in this data sheet, refer to “Input Timer Values for Several Events
Capture with Dedicated Timer” • Configurable Interrupt Generation
(DS70000352) in the “dsPIC33/PIC24 • Up to Six Clock Sources available for each module,
Family Reference Manual”, which is Driving a Separate Internal 16-Bit Counter
available from the Microchip website
(www.microchip.com).
14.1 Input Capture Resources
described in this section may not be Many useful resources are provided on the main prod-
available on all devices. Refer to uct page of the Microchip website for the devices listed
Section 4.0 “Memory Organization” in in this data sheet. This product page contains the latest
this data sheet for device-specific register updates and additional information.
The input capture module is useful in applications • “Input Capture with Dedicated Timer”
requiring frequency (period) and pulse measurements. (DS70000352) in the “dsPIC33/PIC24 Family
The dsPIC33EPXXXGS70X/80X devices support four Reference Manual”
input capture channels.
• Code Samples
• Webinars
Manual” Sections
FIGURE 14-1: INPUT CAPTURE x MODULE BLOCK DIAGRAM
ICM<2:0>
ICI<1:0>
Prescaler Edge Detect Logic Event and Set ICxIF

Counter and Interrupt
1:1/4/16 Clock Synchronizer Logic
ICx Pin
ICTSEL<2:0>
Increment
16
ICx Clock Clock 4-Level FIFO Buffer
ICxTMR
Sources Select 16
Trigger and Trigger and Reset 16

Sync Sources Sync Logic ICxBUF
ICOV, ICBNE System Bus

SYNCSEL<4:0>(1)
Note 1: The trigger/sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for
proper ICx module operation or the trigger/sync source must be changed to another source option.

14.2 Input Capture Registers
REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
— — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — —
bit 15 bit 8
U-0 R/W-0 R/W-0 HC/HS/R-0 HC/HS/R-0 R/W-0 R/W-0 R/W-0

— ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit


bit 13 ICSIDL: Input Capture x Stop in Idle Control bit
1 = Input capture will halt in CPU Idle mode
0 = Input capture will continue to operate in CPU Idle mode
bit 12-10 ICTSEL<2:0>: Input Capture x Timer Select bits
111 = Peripheral clock (FP) is the clock source of the ICx
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of the ICx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the ICx
bit 6-5 ICI<1:0>: Number of Captures per Interrupt Select bits (this field is not used if ICM<2:0> = 001 or 111)
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only)
1 = Input capture buffer overflow has occurred
0 = No input capture buffer overflow has occurred
bit 3 ICBNE: Input Capture x Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty, at least one more capture value can be read
0 = Input capture buffer is empty
bit 2-0 ICM<2:0>: Input Capture x Mode Select bits
111 = Input Capture x functions as an interrupt pin only in CPU Sleep and Idle modes (rising edge
detect only, all other control bits are not applicable)
110 = Unused (module is disabled)
101 = Capture mode, every 16th rising edge (Prescaler Capture mode)
100 = Capture mode, every 4th rising edge (Prescaler Capture mode)
011 = Capture mode, every rising edge (Simple Capture mode)
010 = Capture mode, every falling edge (Simple Capture mode)
001 = Capture mode, every rising and falling edge (Edge Detect mode, ICI<1:0> is not used in this mode)
000 = Input Capture x is turned off

REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — IC32
bit 15 bit 8
R/W-0 HS/R/W-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1

ICTRIG(2) TRIGSTAT(3) — SYNCSEL4(4) SYNCSEL3(4) SYNCSEL2(4) SYNCSEL1(4) SYNCSEL0(4)
bit 7 bit 0
Legend: HS = Hardware Settable bit


bit 8 IC32: Input Capture x 32-Bit Timer Mode Select bit (Cascade mode)
1 = Odd ICx and even ICx form a single 32-bit input capture module(1)
0 = Cascade module operation is disabled
bit 7 ICTRIG: Input Capture x Trigger Operation Select bit(2)
1 = Input source is used to trigger the input capture timer (Trigger mode)
0 = Input source is used to synchronize the input capture timer to a timer of another module
(Synchronization mode)
bit 6 TRIGSTAT: Timer Trigger Status bit(3)
1 = ICxTMR has been triggered and is running
0 = ICxTMR has not been triggered and is being held clear
Note 1: The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits); it can be read, set and
cleared in software.
4: Do not use the ICx module as its own sync or trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.

REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0 SYNCSEL<4:0>: Input Source Select for Synchronization and Trigger Operation bits(4)
11111 = No sync or trigger source for ICx
11110 = Reserved
11101 = Reserved
11100 = Reserved
11011 = CMP4 module synchronizes or triggers ICx(5)
10111 = Reserved
10110 = Reserved
10101 = Reserved
10100 = Reserved
10011 = IC4 module interrupt synchronizes or triggers ICx
01111 = Timer5 synchronizes or triggers ICx
01101 = Timer3 synchronizes or triggers ICx (default)
01010 = Reserved
01001 = Reserved
01000 = IC4 module synchronizes or triggers ICx
00100 = OC4 module synchronizes or triggers ICx
00000 = No sync or trigger source for ICx
Note 1: The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits); it can be read, set and
cleared in software.
4: Do not use the ICx module as its own sync or trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.

15.0 OUTPUT COMPARE single output pulse, or a sequence of output pulses, by
changing the state of the output pin on the compare
Note 1: This data sheet summarizes the features match events. The output compare module can also
of the dsPIC33EPXXXGS70X/80X family generate interrupts on compare match events.
comprehensive reference source. To 15.1 Output Compare Resources
sheet, refer to “Output Compare with Many useful resources are provided on the main prod-
Dedicated Timer” (DS70005159) in uct page of the Microchip website for the devices listed
the “dsPIC33/PIC24 Family Reference in this data sheet. This product page contains the latest
Manual”, which is available from the updates and additional information.
described in this section may not be • “Output Compare with Dedicated Timer”
available on all devices. Refer to (DS70005159) in the “dsPIC33/PIC24 Family
Section 4.0 “Memory Organization” in Reference Manual”
this data sheet for device-specific register • Code Samples
and bit information. • Application Notes
The output compare module can select one of six • Software Libraries
available clock sources for its time base. The module • Webinars
compares the value of the timer with the value of one or • All Related “dsPIC33/PIC24 Family Reference
two Compare registers, depending on the operating Manual” Sections
mode selected. The state of the output pin changes • Development Tools
when the timer value matches the Compare register
value. The output compare module generates either a
FIGURE 15-1: OUTPUT COMPARE x MODULE BLOCK DIAGRAM
OCxCON1
OCxCON2
OCxR
Rollover/Reset
OCxR Buffer
OCx Pin
Comparator
Increment Match
OCx Clock Clock Event
Sources Select
OCx Output and
OCxTMR
Rollover Fault Logic
Reset
OCFA
Comparator
Match Event Match
Trigger and Event
Trigger and
Sync Sources Sync Logic
OCxRS Buffer
SYNCSEL<4:0> Rollover/Reset
Trigger(1)
OCx Synchronization/Trigger Event
OCxRS
OCx Interrupt
Reset
Note 1: The trigger/sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for
proper OCx module operation or the trigger/sync source must be changed to another source option.

15.2 Output Compare Control Registers
REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
— — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 — —
bit 15 bit 8
R/W-0 U-0 U-0 HSC/R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ENFLTA — — OCFLTA TRIGMODE OCM2 OCM1 OCM0
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit


bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit
1 = Output Compare x halts in CPU Idle mode
0 = Output Compare x continues to operate in CPU Idle mode
bit 12-10 OCTSEL<2:0>: Output Compare x Clock Select bits
111 = Peripheral clock (FP)
110 = Reserved
101 = Reserved
100 = T1CLK is the clock source of the OCx (only the synchronous clock is supported)
011 = T5CLK is the clock source of the OCx
bit 7 ENFLTA: Fault A Input Enable bit
1 = Output Compare Fault A input (OCFA) is enabled
0 = Output Compare Fault A input (OCFA) is disabled
bit 4 OCFLTA: PWM Fault A Condition Status bit
1 = PWM Fault A condition on the OCFA pin has occurred
0 = No PWM Fault A condition on the OCFA pin has occurred
bit 3 TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is cleared only by software
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.

REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
bit 2-0 OCM<2:0>: Output Compare x Mode Select bits
111 = Center-Aligned PWM mode: Output is set high when OCxTMR = OCxR and set low when
OCxTMR = OCxRS(1)
110 = Edge-Aligned PWM mode: Output is set high when OCxTMR = 0 and set low when OCxTMR = OCxR(1)
101 = Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously
on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of
OCxR and OCxRS for one cycle
011 = Single Compare mode: Compare event with OCxR, continuously toggles OCx pin
010 = Single Compare Single-Shot mode: Initializes OCx pin high, compare event with OCxR, forces OCx
pin low
001 = Single Compare Single-Shot mode: Initializes OCx pin low, compare event with OCxR, forces OCx
pin high
000 = Output compare channel is disabled
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.

REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
FLTMD FLTOUT FLTTRIEN OCINV — — — OC32
bit 15 bit 8
R/W-0 HS/R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0

OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 7 bit 0

bit 15 FLTMD: Fault Mode Select bit

1 = Fault mode is maintained until the Fault source is removed; the corresponding OCFLTA bit is
cleared in software and a new PWMx period starts
0 = Fault mode is maintained until the Fault source is removed and a new PWMx period starts
bit 14 FLTOUT: Fault Out bit
1 = PWMx output is driven high on a Fault
0 = PWMx output is driven low on a Fault
bit 13 FLTTRIEN: Fault Output State Select bit
1 = OCx pin is tri-stated on a Fault condition
0 = OCx pin I/O state is defined by the FLTOUT bit on a Fault condition
bit 12 OCINV: Output Compare x Invert bit
1 = OCx output is inverted
0 = OCx output is not inverted
bit 8 OC32: Cascade Two OCx Modules Enable bit (32-bit operation)
1 = Cascade module operation is enabled
0 = Cascade module operation is disabled
bit 7 OCTRIG: Output Compare x Trigger/Sync Select bit
1 = Triggers OCx from the source designated by the SYNCSELx bits
0 = Synchronizes OCx with the source designated by the SYNCSELx bits
bit 6 TRIGSTAT: Timer Trigger Status bit
1 = Timer source has been triggered and is running
0 = Timer source has not been triggered and is being held clear
bit 5 OCTRIS: Output Compare x Output Pin Direction Select bit
1 = OCx is tri-stated
0 = OCx module drives the OCx pin
Note 1: Do not use the OCx module as its own synchronization or trigger source.
2: When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.
3: For each OCMPx instance, a different PTG trigger out is used:
OCMP1 – PTG trigger out [0]

REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits
11111 = OCxRS compare event is used for synchronization
11110 = INT2 pin synchronizes or triggers OCx
11101 = INT1 pin synchronizes or triggers OCx
11100 = Reserved
11011 = CMP4 module synchronizes or triggers OCx
10111 = Reserved
10110 = Reserved
10101 = Reserved
10100 = Reserved
10011 = IC4 input capture interrupt event synchronizes or triggers OCx
01111 = Timer5 synchronizes or triggers OCx
01100 = Timer2 synchronizes or triggers OCx (default)
01010 = PTG Trigger Output x(3)
01001 = Reserved
01000 = IC4 input capture event synchronizes or triggers OCx
00100 = OC4 module synchronizes or triggers OCx(1,2)
00000 = No sync or trigger source for OCx
Note 1: Do not use the OCx module as its own synchronization or trigger source.
2: When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.
3: For each OCMPx instance, a different PTG trigger out is used:

NOTES:

16.0 HIGH-SPEED PWM Figure 16-1 conceptualizes the PWM module in a
simplified block diagram. Figure 16-2 illustrates how
Note: This data sheet summarizes the features the module hardware is partitioned for each PWMx
of the dsPIC33EPXXXGS70X/80X family output pair for the Complementary PWM mode.
of devices. It is not intended to be a The PWM module contains eight PWM generators. The
comprehensive reference source. To module has up to 16 PWMx output pins: PWM1H/
complement the information in this data PWM1L through PWM8H/PWM8L. For complementary
sheet, refer to “High-Speed PWM outputs, these 16 I/O pins are grouped into high/low
Module” (DS70000323) in the “dsPIC33/ pairs. PWM1 through PWM6 can be used to trigger an
PIC24 Family Reference Manual”, which ADC conversion.
is available from the Microchip website
(www.microchip.com).
16.2 Feature Description
The high-speed PWM on dsPIC33EPXXXGS70X/80X
The PWM module is designed for applications that
devices supports a wide variety of PWM modes and
require:
output formats. This PWM module is ideal for power
conversion applications, such as: • High resolution at high PWM frequencies
• AC/DC Converters • The ability to drive Standard Edge-Aligned,
Center-Aligned, Complementary mode and
• DC/DC Converters
Push-Pull mode outputs
• Power Factor Correction
• The ability to create multiphase PWM outputs
• Uninterruptible Power Supply (UPS)
Two common, medium power converter topologies are
• Inverters
push-pull and half-bridge. These designs require the
• Battery Chargers PWM output signal to be switched between alternate
• Digital Lighting pins, as provided by the Push-Pull PWM mode.
Phase-shifted PWM describes the situation where
16.1 Features Overview each PWM generator provides outputs, but the phase
The high-speed PWM module incorporates the relationship between the generator outputs is
following features: specifiable and changeable.
• Eight PWMx Generators with Two Outputs per Multiphase PWM is often used to improve DC/DC
Generator Converter load transient response, and reduce the size
of output filter capacitors and inductors. Multiple DC/DC
• Two Master Time Base modules
Converters are often operated in parallel, but phase
• Individual Time Base and Duty Cycle for each shifted in time. A single PWM output, operating at
PWM Output 250 kHz, has a period of 4 s but an array of four PWM
• Duty Cycle, Dead Time, Phase Shift and a channels, staggered by 1 s each, yields an effective
Frequency Resolution of 1.04 ns switching frequency of 1 MHz. Multiphase PWM
• Independent Fault and Current-Limit Inputs applications typically use a fixed-phase relationship.
• Redundant Output Variable phase PWM is useful in Zero Voltage
• True Independent Output Transition (ZVT) power converters. Here, the PWM
• Center-Aligned PWM mode duty cycle is always 50% and the power flow is
controlled by varying the relative phase shift between
• Output Override Control
the two PWM generators.
• Chop mode (also known as Gated mode)
• Special Event Trigger
• Dual Trigger from PWMx to Analog-to-Digital
Converter (ADC)
• PWMxL and PWMxH Output Pin Swapping
• Independent PWMx Frequency, Duty Cycle and
Phase-Shift Changes
• Enhanced Leading-Edge Blanking (LEB) Functionality
• PWM Capture Functionality
Note: Duty cycle, dead time, phase shift and
frequency resolution is 8.32 ns in
Center-Aligned PWM mode.

16.2.1 WRITE-PROTECTED REGISTERS To gain write access to these locked registers, the user
application must write two consecutive values (0xABCD
On dsPIC33EPXXXGS70X/80X family devices, write
and 0x4321) to the PWMKEY register to perform the
protection is implemented for the IOCONx and FCLCONx
unlock operation. The write access to the IOCONx or
registers. The write protection feature prevents any inad-
FCLCONx registers must be the next SFR access
vertent writes to these registers. This protection feature
following the unlock process. There can be no other SFR
can be controlled by the PWMLOCK Configuration bit
accesses during the unlock process and subsequent
(FDEVOPT<0>). The default state of the write protection
write access. To write to both the IOCONx and
feature is enabled (PWMLOCK = 1). The write protection
FCLCONx registers requires two unlock operations.
feature can be disabled by configuring PWMLOCK = 0.
The correct unlocking sequence is described in
Example 16-1.
EXAMPLE 16-1: PWM WRITE-PROTECTED REGISTER UNLOCK SEQUENCE

; Writing to FCLCON1 register requires unlock sequence
mov #0xabcd, w10 ; Load first unlock key to w10 register

mov #0x4321, w11 ; Load second unlock key to w11 register
mov #0x0000, w0 ; Load desired value of FCLCON1 register in w0
mov w10, PWMKEY ; Write first unlock key to PWMKEY register
mov w11, PWMKEY ; Write second unlock key to PWMKEY register
mov w0, FCLCON1 ; Write desired value to FCLCON1 register
; Set PWM ownership and polarity using the IOCON1 register

; Writing to IOCON1 register requires unlock sequence
mov #0xabcd, w10 ; Load first unlock key to w10 register

mov #0x4321, w11 ; Load second unlock key to w11 register
mov #0xF000, w0 ; Load desired value of IOCON1 register in w0
mov w10, PWMKEY ; Write first unlock key to PWMKEY register
mov w11, PWMKEY ; Write second unlock key to PWMKEY register
mov w0, IOCON1 ; Write desired value to IOCON1 register
16.3 PWM Resources 16.3.1 KEY RESOURCES

Many useful resources are provided on the main prod- • “High-Speed PWM Module” (DS70000323) in
uct page of the Microchip website for the devices listed the “dsPIC33/PIC24 Family Reference Manual”
• Webinars
Manual” Sections

FIGURE 16-1: HIGH-SPEED PWM MODULE ARCHITECTURAL DIAGRAM
SYNCI1/SYNCI2
Data Bus
Primary and Secondary

Master Time Base
SYNCO1/SYNCO2
Synchronization Signal
PWM1 Interrupt
PWM1H
PWM
Generator 1
PWM1L
Fault, Current Limit
PWM2 Interrupt
PWM2H
PWM
Generator 2
CPU PWM2L
Fault, Current Limit
PWM3 through PWM7
PWM8 Interrupt PWM8H

PWM
Generator 8
PWM8L
Primary Trigger
Secondary Trigger
ADC Module Fault and
Current Limit
Special Event Trigger

FIGURE 16-2: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF THE HIGH-SPEED PWM
PTCON, PTCON2 Module Control and Timing

STCON, STCON2 SYNCI1 SYNCI2
PWMKEY
PTPER SEVTCMP Special Event Compare Trigger SYNCO1
Comparator Special Event

Comparator Postscaler Special Event Trigger
Master Time Base Counter
Clock
PMTMR Prescaler Primary Master Time Base
SYNCO2
STPER SEVTCMP Special Event Compare Trigger
Special Event
Comparator Comparator
Postscaler Special Event Trigger
Master Time Base Counter

Clock
SMTMR Prescaler Secondary Master Time Base
MDC Master Duty Cycle Register

Synchronization
Master Duty Cycle
16-Bit Data Bus
PDCx PWM Generator 1
MUX
Master Period
Comparator PWMx Output Mode

PWMCAPx Control Logic
ADC Trigger User Override Logic

Dead-Time Pin
PTMRx Control PWM1H
Current-Limit Logic
Comparator Logic
Override Logic PWM1L
PHASEx
TRIGx Fault Override Logic
SDCx
Secondary PWMx
MUX
Interrupt Fault and

Comparator Current-Limit
Logic FLTx
Logic
ADC Trigger
STMRx
Comparator
Synchronization
SPHASEx
STRIGx FCLCONx IOCONx ALTDTRx
Master Duty Cycle
PWMCONx
Master Period
AUXCONx TRGCONx LEBCONx DTRx
PWMxH
PWM Generator 1 – PWM Generator 8 PWMxL
FLTx

REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER
R/W-0 U-0 R/W-0 HSC/R-0 R/W-0 R/W-0 R/W-0 R/W-0
(1) (1)
PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN(1)
bit 15 bit 8

(1) (1) (1) (1) (1) (1) (1)
SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0(1)
bit 7 bit 0

bit 15 PTEN: PWM Module Enable bit

1 = PWM module is enabled
0 = PWM module is disabled
bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Special event interrupt is pending
0 = Special event interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Special event interrupt is enabled
0 = Special event interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit(1)
1 = SYNCIx/SYNCO1 polarity is inverted (active-low)
0 = SYNCIx/SYNCO1 is active-high
bit 8 SYNCOEN: Primary Time Base Synchronization Enable bit(1)
1 = SYNCO1 output is enabled
0 = SYNCO1 output is disabled
bit 7 SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1)
111 = Reserved
101 = Reserved
100 = Reserved
011 = PTG Trigger Output 17
001 = SYNCI2
000 = SYNCI1
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.

REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED)
bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1)
1111 = 1:16 postscaler generates a Special Event Trigger on every sixteenth compare match event
•
•
•
0001 = 1:2 postscaler generates a Special Event Trigger on every second compare match event
0000 = 1:1 postscaler generates a Special Event Trigger on every compare match event
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
REGISTER 16-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>(1)
bit 7 bit 0
Legend:

bit 2-0 PCLKDIV<2:0>: PWMx Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
110 = Divide-by-64, maximum PWM timing resolution
000 = Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.

REGISTER 16-3: PTPER: PWM PRIMARY MASTER TIME BASE PERIOD REGISTER(1,2)
PTPER<15:8>
bit 15 bit 8

PTPER<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits
Note 1: The PWMx time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.
2: Any period value that is less than 0x0028 must have the Least Significant three bits set to ‘0’, thus yielding
a period resolution at 8.32 ns (at fastest auxiliary clock rate).
REGISTER 16-4: SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER(1)

SEVTCMP<12:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

SEVTCMP<4:0> — — —
bit 7 bit 0
Legend:
bit 15-3 SEVTCMP<12:0>: Special Event Compare Count Value bits

Note 1: One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SEVTCMP resolution is 8.32 ns.

REGISTER 16-5: STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER
U-0 U-0 U-0 HSC/R-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — SESTAT SEIEN EIPU(1) SYNCPOL SYNCOEN
bit 15 bit 8

SYNCEN SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3 SEVTPS2 SEVTPS1 SEVTPS0
bit 7 bit 0


bit 12 SESTAT: Special Event Interrupt Status bit
1 = Secondary special event interrupt is pending
0 = Secondary special event interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Secondary special event interrupt is enabled
0 = Secondary special event interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(1)
1 = Active Secondary Period register is updated immediately
0 = Active Secondary Period register updates occur on PWMx cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCIx/SYNCO2 polarity is inverted (active-low)
0 = SYNCIx/SYNCO2 polarity is active-high
bit 8 SYNCOEN: Secondary Master Time Base Synchronization Enable bit
1 = SYNCO2 output is enabled
0 = SYNCO2 output is disabled
bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit
1 = External synchronization of secondary time base is enabled
0 = External synchronization of secondary time base is disabled
bit 6-4 SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits
111 = Reserved
101 = Reserved
100 = Reserved
001 = SYNCI2
000 = SYNCI1
bit 3-0 SEVTPS<3:0>: PWMx Secondary Special Event Trigger Output Postscaler Select bits
1111 = 1:16 postcaler
0001 = 1:2 postcaler
•
•
•
0000 = 1:1 postscaler
Note 1: This bit only applies to the secondary master time base period.

REGISTER 16-6: STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>(1)
bit 7 bit 0
Legend:

bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)
111 = Reserved
000 = Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
REGISTER 16-7: STPER: PWM SECONDARY MASTER TIME BASE PERIOD REGISTER(1,2)
STPER<15:8>
bit 15 bit 8

STPER<7:0>
bit 7 bit 0
Legend:
bit 15-0 STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits
Note 1: The PWMx time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.
2: Any period value that is less than 0x0028 must have the Least Significant 3 bits set to ‘0’, thus yielding a
period resolution at 8.32 ns (at fastest auxiliary clock rate).

REGISTER 16-8: SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER(1)
SSEVTCMP<12:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

SSEVTCMP<4:0> — — —
bit 7 bit 0
Legend:
bit 15-3 SSEVTCMP<12:0>: Special Event Compare Count Value bits

Note 1: One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SSEVTCMP resolution is 8.32 ns.
REGISTER 16-9: CHOP: PWM CHOP CLOCK GENERATOR REGISTER(1)

R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
CHPCLKEN — — — — — CHOPCLK6 CHOPCLK5
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0 — — —
bit 7 bit 0
Legend:
bit 15 CHPCLKEN: Enable Chop Clock Generator bit

1 = Chop clock generator is enabled
0 = Chop clock generator is disabled
bit 9-3 CHOPCLK<6:0>: Chop Clock Divider bits
Value is in 8.32 ns increments. The frequency of the chop clock signal is given by:
Chop Frequency = 1/(16.64 * (CHOP<7:3> + 1) * Primary Master PWM Input Clock Period).
Note 1: The chop clock generator operates with the primary PWM clock prescaler (PCLKDIV<2:0>) in the
PTCON2 register (Register 16-2).

REGISTER 16-10: MDC: PWM MASTER DUTY CYCLE REGISTER(1,2)
MDC<15:8>
bit 15 bit 8

MDC<7:0>
bit 7 bit 0
Legend:
bit 15-0 MDC<15:0>: PWM Master Duty Cycle Value bits
Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of
operation), PWM duty cycle resolution will increase from one to three LSBs.
REGISTER 16-11: PWMKEY: PWM PROTECTION LOCK/UNLOCK KEY REGISTER

PWMKEY<15:8>
bit 15 bit 8

PWMKEY<7:0>
bit 7 bit 0
Legend:
bit 15-0 PWMKEY<15:0>: PWM Protection Lock/Unlock Key Value bits

REGISTER 16-12: PWMCONx: PWMx CONTROL REGISTER (x = 1 to 8)
HSC/R-0 HSC/R-0 HSC/R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSTAT(1) CLSTAT(1) TRGSTAT FLTIEN CLIEN TRGIEN ITB(3) MDCS(3)
bit 15 bit 8
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

DTC1 DTC0 — — MTBS CAM(2,3,4) XPRES(5) IUE
bit 7 bit 0

bit 15 FLTSTAT: Fault Interrupt Status bit(1)

1 = Fault interrupt is pending
0 = No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
bit 14 CLSTAT: Current-Limit Interrupt Status bit(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
bit 13 TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
bit 12 FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11 CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt is enabled
0 = Current-limit interrupt is disabled and the CLSTAT bit is cleared
bit 10 TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9 ITB: Independent Time Base Mode bit(3)
1 = PHASEx/SPHASEx registers provide the time base period for this PWMx generator
0 = PTPER register provides timing for this PWMx generator
bit 8 MDCS: Master Duty Cycle Register Select bit(3)
1 = MDC register provides duty cycle information for this PWMx generator
0 = PDCx and SDCx registers provide duty cycle information for this PWMx generator
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should not be changed after the PWMx is enabled by setting PTEN (PTCON<15>) = 1.
4: Center-Aligned mode ignores the Least Significant three bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
5: Configure CLMOD (FCLCONx<8>) = 0 and ITB (PWMCONx<9>) = 1 to operate in External Period Reset mode.

REGISTER 16-12: PWMCONx: PWMx CONTROL REGISTER (x = 1 to 8) (CONTINUED)
bit 7-6 DTC<1:0>: Dead-Time Control bits
11 = Reserved
10 = Dead-time function is disabled
01 = Negative dead time is actively applied for Complementary Output mode
00 = Positive dead time is actively applied for all Output modes
bit 3 MTBS: Master Time Base Select bit
1 = PWMx generator uses the secondary master time base for synchronization and the clock source for
the PWMx generation logic (if secondary time base is available)
0 = PWMx generator uses the primary master time base for synchronization and the clock source for the
PWMx generation logic
bit 2 CAM: Center-Aligned Mode Enable bit(2,3,4)
1 = Center-Aligned mode is enabled
0 = Edge-Aligned mode is enabled
bit 1 XPRES: External PWMx Reset Control bit(5)
1 = Current-limit source resets the time base for this PWMx generator if it is in Independent Time Base mode
0 = External pins do not affect the PWMx time base
bit 0 IUE: Immediate Update Enable bit
1 = Updates to the active Duty Cycle, Phase Offset, Dead-Time and local Time Base Period registers are
immediate
0 = Updates to the active Duty Cycle, Phase Offset, Dead-Time and local Time Base Period registers are
synchronized to the local PWMx time base
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should not be changed after the PWMx is enabled by setting PTEN (PTCON<15>) = 1.
4: Center-Aligned mode ignores the Least Significant three bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
5: Configure CLMOD (FCLCONx<8>) = 0 and ITB (PWMCONx<9>) = 1 to operate in External Period Reset mode.

REGISTER 16-13: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER (x = 1 to 8)(1,2,3)
PDCx<15:8>
bit 15 bit 8

PDCx<7:0>
bit 7 bit 0
Legend:
bit 15-0 PDCx<15:0>: PWMx Generator Duty Cycle Value bits
Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In the
Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both
the PWMxH and PWMxL.
2: The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,
operation), PWMx duty cycle resolution will increase from one to three LSBs.
REGISTER 16-14: SDCx: PWMx SECONDARY DUTY CYCLE REGISTER (x = 1 to 8)(1,2,3)

SDCx<15:8>
bit 15 bit 8

SDCx<7:0>
bit 7 bit 0
Legend:
bit 15-0 SDCx<15:0>: PWMx Secondary Duty Cycle for PWMxL Output Pin bits
Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the
SDCx register controls the PWMxL duty cycle.
2: The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,
operation), PWMx duty cycle resolution will increase from one to three LSBs.

REGISTER 16-15: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER (x = 1 to 8)(1,2)
PHASEx<15:8>
bit 15 bit 8

PHASEx<7:0>
bit 7 bit 0
Legend:
bit 15-0 PHASEx<15:0>: PWMx Phase-Shift Value or Independent Time Base Period for the PWMx Generator bits
Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation:

• Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01 or 10);
PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs
• True Independent Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Phase-shift value for
PWMxH only
• When the PHASEx/SPHASEx registers provide the phase shift with respect to the master time base;
therefore, the valid range is 0x0000 through period
2: If PWMCONx<9> = 1, the following applies based on the mode of operation:
PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL
• True Independent Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Independent time base
period value for PWMxH only
• When the PHASEx/SPHASEx registers provide the local period, the valid range is 0x0000-0xFFF8

REGISTER 16-16: SPHASEx: PWMx SECONDARY PHASE-SHIFT REGISTER (x = 1 to 8)(1,2)
SPHASEx<15:8>
bit 15 bit 8

SPHASEx<7:0>
bit 7 bit 0
Legend:
bit 15-0 SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits
(used in Independent PWM mode only)
Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation:

SPHASEx<15:0> = Not used
• True Independent Output mode (IOCONx<11:10> = 11), SPHASEx<15:0> = Phase-shift value for
PWMxL only
2: If PWMCONx<9> = 1, the following applies based on the mode of operation:
SPHASEx<15:0> = Not used
• True Independent Output mode (IOCONx<11:10> = 11); SPHASEx<15:0> = Independent time base
period value for PWMxL only
• When the PHASEx/SPHASEx registers provide the local period, the valid range of values is
0x0010-0xFFF8

REGISTER 16-17: DTRx: PWMx DEAD-TIME REGISTER (x = 1 to 8)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DTRx<13:8>
bit 15 bit 8

DTRx<7:0>
bit 7 bit 0
Legend:

bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
REGISTER 16-18: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER (x = 1 to 8)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — ALTDTRx<13:8>
bit 15 bit 8

ALTDTRx<7:0>
bit 7 bit 0
Legend:

bit 13-0 ALTDTRx<13:0>: Unsigned 14-Bit Alternate Dead-Time Value for PWMx Dead-Time Unit bits

REGISTER 16-19: TRGCONx: PWMx TRIGGER CONTROL REGISTER (x = 1 to 8)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — —
bit 15 bit 8

DTM(1) — TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
bit 7 bit 0
Legend:
bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits

1111 = Trigger output for every 16th trigger event
0010 = Trigger output for every 3rd trigger event
0001 = Trigger output for every 2nd trigger event
0000 = Trigger output for every trigger event
bit 7 DTM: Dual Trigger Mode bit(1)
1 = Secondary trigger event is combined with the primary trigger event to create a PWM trigger
0 = Secondary trigger event is not combined with the primary trigger event to create a PWM trigger;
two separate PWM triggers are generated
bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits
111111 = Wait 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000001 = Wait 1 PWM cycle before generating the first trigger event after the module is enabled
Note 1: The secondary PWMx generator cannot generate PWM trigger interrupts.

REGISTER 16-20: IOCONx: PWMx I/O CONTROL REGISTER (x = 1 to 8)
(1) (1)
PENH PENL POLH POLL PMOD1 PMOD0 OVRENH OVRENL
bit 15 bit 8

(2) (2) (2) (2)
OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC
bit 7 bit 0
Legend:
bit 15 PENH: PWMxH Output Pin Ownership bit

1 = PWMx module controls the PWMxH pin
0 = GPIO module controls the PWMxH pin
bit 14 PENL: PWMxL Output Pin Ownership bit
1 = PWMx module controls the PWMxL pin
0 = GPIO module controls the PWMxL pin
bit 13 POLH: PWMxH Output Pin Polarity bit
1 = PWMxH pin is active-low
0 = PWMxH pin is active-high
bit 12 POLL: PWMxL Output Pin Polarity bit
1 = PWMxL pin is active-low
0 = PWMxL pin is active-high
bit 11-10 PMOD<1:0>: PWMx I/O Pin Mode bits(1)
11 = PWMx I/O pin pair is in the True Independent Output mode
10 = PWMx I/O pin pair is in the Push-Pull Output mode
01 = PWMx I/O pin pair is in the Redundant Output mode
00 = PWMx I/O pin pair is in the Complementary Output mode
bit 9 OVRENH: Override Enable for PWMxH Pin bit
1 = OVRDAT1 provides data for output on the PWMxH pin
0 = PWMx generator provides data for the PWMxH pin
bit 8 OVRENL: Override Enable for PWMxL Pin bit
1 = OVRDAT0 provides data for output on the PWMxL pin
0 = PWMx generator provides data for the PWMxL pin
bit 7-6 OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits
If OVRENH = 1, OVRDAT1 provides data for the PWMxH pin.
If OVRENL = 1, OVRDAT0 provides data for the PWMxL pin.
bit 5-4 FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD<1:0> are Enabled bits(2)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If Fault is active, then FLTDAT1 provides the state for the PWMxH pin.
If Fault is active, then FLTDAT0 provides the state for the PWMxL pin.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
If current limit is active, then FLTDAT1 provides the state for the PWMxH pin.
If Fault is active, then FLTDAT0 provides the state for the PWMxL pin.
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.

REGISTER 16-20: IOCONx: PWMx I/O CONTROL REGISTER (x = 1 to 8) (CONTINUED)
bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits(2)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If current limit is active, then CLDAT1 provides the state for the PWMxH pin.
If current limit is active, then CLDAT0 provides the state for the PWMxL pin.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
CLDAT<1:0> bits are ignored.
bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit
1 = PWMxH output signal is connected to the PWMxL pins; PWMxL output signal is connected to the
PWMxH pins
0 = PWMxH and PWMxL pins are mapped to their respective pins
bit 0 OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWMx time base
0 = Output overrides via the OVRDAT<1:0> bits occur on the next CPU clock boundary
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.
REGISTER 16-21: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER (x = 1 to 8)

TRGCMP<12:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

TRGCMP<4:0> — — —
bit 7 bit 0
Legend:
bit 15-3 TRGCMP<12:0>: Trigger Compare Value bits

When the primary PWMx functions in the local time base, this register contains the compare values
that can trigger the ADC module.

REGISTER 16-22: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
(x = 1 to 8)
IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL(1) CLMOD
bit 15 bit 8

FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL(1) FLTMOD1 FLTMOD0
bit 7 bit 0
Legend:
bit 15 IFLTMOD: Independent Fault Mode Enable bit

1 = Independent Fault mode: Current-limit input maps FLTDAT1 to the PWMxH output and the Fault
input maps FLTDAT0 to the PWMxL output; the CLDAT<1:0> bits are not used for override functions
0 = Normal Fault mode: Current-Limit mode maps CLDAT<1:0> bits to the PWMxH and PWMxL
outputs; the PWM Fault mode maps FLTDAT<1:0> to the PWMxH and PWMxL outputs
bit 14-10 CLSRC<4:0>: Current-Limit Control Signal Source Select for PWMx Generator bits
11111 = FLT31
10001 = Reserved
10000 = Analog Comparator 4
01100 = Fault 12
01011 = Fault 11
01010 = Fault 10
01001 = Fault 9
01000 = Fault 8
00111 = Fault 7
00110 = Fault 6
00101 = Fault 5
00100 = Fault 4
00011 = Fault 3
00010 = Fault 2
00001 = Fault 1
00000 = Reserved
bit 9 CLPOL: Current-Limit Polarity for PWMx Generator bit(1)
1 = The selected current-limit source is active-low
0 = The selected current-limit source is active-high
bit 8 CLMOD: Current-Limit Mode Enable for PWMx Generator bit
1 = Current-Limit mode is enabled
0 = Current-Limit mode is disabled
Note 1: These bits should be changed only when PTEN = 0 (PTCON<15>).

REGISTER 16-22: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
(x = 1 to 8) (CONTINUED)
bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWMx Generator bits
11111 = Fault 31 (Default)
11110-10111 = Reserved
10110 = Fault 22
10101 = Fault 21
10100 = Fault 20
10011 = Fault 19
10010 = Fault 18
10001 = Fault 17
01100 = Fault 12
01011 = Fault 11
01010 = Fault 10
01001 = Fault 9
01000 = Fault 8
00111 = Fault 7
00110 = Fault 6
00101 = Fault 5
00100 = Fault 4
00011 = Fault 3
00010 = Fault 2
00001 = Fault 1
00000 = Reserved
bit 2 FLTPOL: Fault Polarity for PWMx Generator bit(1)
1 = The selected Fault source is active-low
0 = The selected Fault source is active-high
bit 1-0 FLTMOD<1:0>: Fault Mode for PWMx Generator bits
11 = Fault input is disabled
10 = Reserved
01 = The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (cycle)
00 = The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (latched condition)
Note 1: These bits should be changed only when PTEN = 0 (PTCON<15>).

REGISTER 16-23: STRIGx: PWMx SECONDARY TRIGGER COMPARE VALUE REGISTER (x = 1 to 8)(1)
STRGCMP<12:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

STRGCMP<4:0> — — —
bit 7 bit 0
Legend:
bit 15-3 STRGCMP<12:0>: Secondary Trigger Compare Value bits

When the secondary PWMx functions in the local time base, this register contains the compare values
that can trigger the ADC module.
Note 1: STRIGx cannot generate the PWM trigger interrupts.

REGISTER 16-24: LEBCONx: PWMx LEADING-EDGE BLANKING (LEB) CONTROL REGISTER
(x = 1 to 8)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
PHR PHF PLR PLF FLTLEBEN CLLEBEN — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1) (1)
— — BCH BCL BPHH BPHL BPLH BPLL
bit 7 bit 0
Legend:
bit 15 PHR: PWMxH Rising Edge Trigger Enable bit

1 = Rising edge of PWMxH will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the rising edge of PWMxH
bit 14 PHF: PWMxH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the falling edge of PWMxH
bit 13 PLR: PWMxL Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the rising edge of PWMxL
bit 12 PLF: PWMxL Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger the Leading-Edge Blanking counter
0 = Leading-Edge Blanking ignores the falling edge of PWMxL
bit 11 FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to the selected Fault input
0 = Leading-Edge Blanking is not applied to the selected Fault input
bit 10 CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1 = Leading-Edge Blanking is applied to the selected current-limit input
0 = Leading-Edge Blanking is not applied to the selected current-limit input
bit 5 BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when the selected blanking signal is high
0 = No blanking when the selected blanking signal is high
bit 4 BCL: Blanking in Selected Blanking Signal Low Enable bit(1)
1 = State blanking (of current-limit and/or Fault input signals) when the selected blanking signal is low
0 = No blanking when the selected blanking signal is low
bit 3 BPHH: Blanking in PWMxH High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxH output is high
0 = No blanking when the PWMxH output is high
bit 2 BPHL: Blanking in PWMxH Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxH output is low
0 = No blanking when the PWMxH output is low
Note 1: The blanking signal is selected via the BLANKSEL<3:0> bits in the AUXCONx register.

REGISTER 16-24: LEBCONx: PWMx LEADING-EDGE BLANKING (LEB) CONTROL REGISTER
bit 1 BPLH: Blanking in PWMxL High Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxL output is high
0 = No blanking when the PWMxL output is high
bit 0 BPLL: Blanking in PWMxL Low Enable bit
1 = State blanking (of current-limit and/or Fault input signals) when the PWMxL output is low
0 = No blanking when the PWMxL output is low
Note 1: The blanking signal is selected via the BLANKSEL<3:0> bits in the AUXCONx register.
REGISTER 16-25: LEBDLYx: PWMx LEADING-EDGE BLANKING DELAY REGISTER (x = 1 to 8)

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — LEB<8:5>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0

LEB<4:0> — — —
bit 7 bit 0
Legend:

bit 11-3 LEB<8:0>: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits
The value is in 8.32 ns increments.

REGISTER 16-26: AUXCONx: PWMx AUXILIARY CONTROL REGISTER (x = 1 to 8)
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
HRPDIS HRDDIS — — BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN CHOPLEN
bit 7 bit 0
Legend:
bit 15 HRPDIS: High-Resolution PWMx Period Disable bit

1 = High-resolution PWMx period is disabled to reduce power consumption
0 = High-resolution PWMx period is enabled
bit 14 HRDDIS: High-Resolution PWMx Duty Cycle Disable bit
1 = High-resolution PWMx duty cycle is disabled to reduce power consumption
0 = High-resolution PWMx duty cycle is enabled
bit 11-8 BLANKSEL<3:0>: PWMx State Blank Source Select bits
The selected state blank signal will block the current-limit and/or Fault input signals
(if enabled via the BCH and BCL bits in the LEBCONx register).
1001 = Reserved
1000 = PWM8H is selected as the state blank source
0000 = No state blanking
bit 5-2 CHOPSEL<3:0>: PWMx Chop Clock Source Select bits
The selected signal will enable and disable (chop) the selected PWMx outputs.
1001 = Reserved
1000 = PWM8H is selected as the chop clock source
0000 = Chop clock generator is selected as the chop clock source
bit 1 CHOPHEN: PWMxH Output Chopping Enable bit
1 = PWMxH chopping function is enabled
0 = PWMxH chopping function is disabled
bit 0 CHOPLEN: PWMxL Output Chopping Enable bit
1 = PWMxL chopping function is enabled
0 = PWMxL chopping function is disabled

REGISTER 16-27: PWMCAPx: PWMx PRIMARY TIME BASE CAPTURE REGISTER (x = 1 to 8)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
PWMCAP<12:5>(1,2,3,4)
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 U-0 U-0 U-0

PWMCAP<4:0>(1,2,3,4) — — —
bit 7 bit 0
Legend:
bit 15-3 PWMCAP<12:0>: PWMx Primary Time Base Capture Value bits(1,2,3,4)
The value in this register represents the captured PWMx time base value when a leading edge is
detected on the current-limit input.
Note 1: The capture feature is only available on a primary output (PWMxH).

2: This feature is active only after LEB processing on the current-limit input signal is complete.
3: The minimum capture resolution is 8.32 ns.
4: This feature can be used when the XPRES bit (PWMCONx<1>) is set to ‘0’.

NOTES:

17.0 PERIPHERAL TRIGGER The PTG module has the following major features:
GENERATOR (PTG) MODULE • Multiple Clock Sources
• Two 16-Bit General Purpose Timers
• Two 16-Bit General Limit Counters
of devices. It is not intended to be a • Configurable for Rising or Falling Edge Triggering
comprehensive reference source. To • Generates Processor Interrupts to include:
complement the information in this data - Four configurable processor interrupts
sheet, refer to “Peripheral Trigger - Interrupt on a Step event in Single-Step mode
Generator (PTG)” (DS70000669) in - Interrupt on a PTG Watchdog Timer time-out
the “dsPIC33/PIC24 Family Reference
• Able to Receive Trigger Signals from these
Manual”, which is available from the
Peripherals:
- ADC
- PWM
available on all devices. Refer to - Output Compare
Section 4.0 “Memory Organization” in - Input Capture
this data sheet for device-specific register - Comparator
and bit information. - INT2
• Able to Trigger or Synchronize to these
17.1 Module Introduction Peripherals:
The Peripheral Trigger Generator (PTG) provides a - Watchdog Timer
means to schedule complex, high-speed peripheral - Output Compare
operations that would be difficult to achieve using soft- - Input Capture
ware. The PTG module uses 8-bit commands, called - ADC
“Steps”, that the user writes to the PTG Queue register - PWM
(PTGQUE0-PTQUE15) which performs operations,
- Comparator
such as wait for input signal, generate output trigger
and wait for timer.

FIGURE 17-1: PTG BLOCK DIAGRAM
PTGHOLD
PTGL0<15:0> PTGTxLIM<15:0> PTGCxLIM<15:0> PTGSDLIM<15:0>
PTGADJ
PTG General PTG Step
PTG Loop
Purpose
Counter x Delay Timer
Step Command Timerx
PTGBTE<15:0>
PTGCST<15:0>
Step Command
PTGCON<15:0>
PTGDIV<4:0>
Trigger Outputs
PTGO0
PTGCLK<2:0> •
•
•
PTGO31
16-Bit Data Bus
FP
Clock Inputs
TAD
T1CLK
T2CLK  PTG Control Logic
T3CLK Step Command
FOSC
Step Command
PTG Interrupts
PTG0IF
•
PWM •
Trigger Inputs
OC1 •
OC2 PTG3IF
IC1
CMPx
ADC
INT2
CNVCHSEL<5:0>
PTGQPTR<4:0>
PTG Watchdog
Timer(1) PTGWDTIF
PTGQUE0
PTGQUE1
Command
Decoder
PTGQUE14
PTGQUE15
PTGSTEPIF
Note 1: This is a dedicated Watchdog Timer for the PTG module and is independent of the device Watchdog Timer.

17.2 PTG Control Registers
REGISTER 17-1: PTGCST: PTG CONTROL/STATUS REGISTER

R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
(2)
PTGEN — PTGSIDL PTGTOGL — PTGSWT PTGSSEN PTGIVIS
bit 15 bit 8
R/W-0 HS-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

(1)
PTGSTRT PTGWDTO — — — — PTGITM1 PTGITM0(1)
bit 7 bit 0

bit 15 PTGEN: PTG Module Enable bit

1 = PTG module is enabled
0 = PTG module is disabled
bit 13 PTGSIDL: PTG Stop in Idle Mode bit
bit 12 PTGTOGL: PTG TRIG Output Toggle Mode bit
1 = Toggles the state of the PTGOx for each execution of the PTGTRIG command
0 = Each execution of the PTGTRIG command will generate a single PTGOx pulse determined by the
value in the PTGPWDx bits
bit 10 PTGSWT: PTG Software Trigger bit(2)
1 = Triggers the PTG module
0 = No action (clearing this bit will have no effect)
bit 9 PTGSSEN: PTG Enable Single-Step bit
1 = Enables Single-Step mode
0 = Disables Single-Step mode
bit 8 PTGIVIS: PTG Counter/Timer Visibility Control bit
1 = Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the current values of their
corresponding Counter/Timer registers (PTGSD, PTGCx, PTGTx)
0 = Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the value previously written to
those PTG Limit registers
bit 7 PTGSTRT: Start PTG Sequencer bit
1 = Starts to sequentially execute commands (Continuous mode)
0 = Stops executing commands
bit 6 PTGWDTO: PTG Watchdog Timer Time-out Status bit
1 = PTG Watchdog Timer has timed out
0 = PTG Watchdog Timer has not timed out.
Note 1: These bits apply to the PTGWHI and PTGWLO commands only.
2: This bit is only used with the PTGCTRL Step command software trigger option.

REGISTER 17-1: PTGCST: PTG CONTROL/STATUS REGISTER (CONTINUED)
bit 1-0 PTGITM<1:0>: PTG Input Trigger Command Operating Mode bits(1)
11 = Single level detect with Step delay is not executed on exit of command (regardless of PTGCTRL
command)
10 = Single level detect with Step delay is executed on exit of command
01 = Continuous edge detect with Step delay is not executed on exit of command (regardless of
PTGCTRL command)
00 = Continuous edge detect with Step delay is executed on exit of command
Note 1: These bits apply to the PTGWHI and PTGWLO commands only.
2: This bit is only used with the PTGCTRL Step command software trigger option.

REGISTER 17-2: PTGCON: PTG CONTROL REGISTER
PTGCLK2 PTGCLK1 PTGCLK0 PTGDIV4 PTGDIV3 PTGDIV2 PTGDIV1 PTGDIV0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

PTGPWD3 PTGPWD2 PTGPWD1 PTGPWD0 — PTGWDT2 PTGWDT1 PTGWDT0
bit 7 bit 0
Legend:
bit 15-13 PTGCLK<2:0>: Select PTG Module Clock Source bits

111 = CLC2
110 = CLC1
101 = PTG module clock source will be T3CLK
010 = PTG module clock source will be TAD
001 = PTG module clock source will be FOSC
000 = PTG module clock source will be FP
bit 12-8 PTGDIV<4:0>: PTG Module Clock Prescaler (divider) bits
11111 = Divide-by-32
11110 = Divide-by-31
•
•
•
00001 = Divide-by-2
00000 = Divide-by-1
bit 7-4 PTGPWD<3:0>: PTG Trigger Output Pulse-Width bits
1111 = All trigger outputs are 16 PTG clock cycles wide
•
•
•
0000 = All trigger outputs are 1 PTG clock cycle wide
bit 2-0 PTGWDT<2:0>: Select PTG Watchdog Timer Time-out Count Value bits
111 = Watchdog Timer will time-out after 512 PTG clocks
000 = Watchdog Timer is disabled

REGISTER 17-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — ADCTS1 IC4TSS IC3TSS IC2TSS IC1TSS
bit 15 bit 8

OC4CS OC3CS OC2CS OC1CS OC4TSS OC3TSS OC2TSS OC1TSS
bit 7 bit 0
Legend:

bit 12 ADCTS1: Sample Trigger PTGO12 for ADCx bit
1 = Generates trigger when the broadcast command is executed
0 = Does not generate trigger when the broadcast command is executed
bit 11 IC4TSS: Trigger/Synchronization Source for IC4 bit
1 = Generates trigger/synchronization when the broadcast command is executed
0 = Does not generate trigger/synchronization when the broadcast command is executed
bit 7 OC4CS: Clock Source for OC4 bit
1 = Generates clock pulse when the broadcast command is executed
0 = Does not generate clock pulse when the broadcast command is executed
bit 3 OC4TSS: Trigger/Synchronization Source for OC4 bit
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
2: This register is only used with the PTGCTRL OPTION = 1111 Step command.

REGISTER 17-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2) (CONTINUED)
PTGSTRT = 1).
2: This register is only used with the PTGCTRL OPTION = 1111 Step command.

REGISTER 17-4: PTGT0LIM: PTG TIMER0 LIMIT REGISTER(1)
PTGT0LIM<15:8>
bit 15 bit 8

PTGT0LIM<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTGT0LIM<15:0>: PTG Timer0 Limit Register bits

General purpose Timer0 Limit register (effective only with a PTGT0 Step command).
PTGSTRT = 1).
REGISTER 17-5: PTGT1LIM: PTG TIMER1 LIMIT REGISTER(1)

PTGT1LIM<15:8>
bit 15 bit 8

PTGT1LIM<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTGT1LIM<15:0>: PTG Timer1 Limit Register bits

General purpose Timer1 Limit register (effective only with a PTGT1 Step command).
PTGSTRT = 1).

REGISTER 17-6: PTGSDLIM: PTG STEP DELAY LIMIT REGISTER(1,2)
PTGSDLIM<15:8>
bit 15 bit 8

PTGSDLIM<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTGSDLIM<15:0>: PTG Step Delay Limit Register bits

Holds a PTG Step delay value, representing the number of additional PTG clocks, between the start
of a Step command and the completion of a Step command.
Note 1: A base Step delay of one PTG clock is added to any value written to the PTGSDLIM register
(Step Delay = (PTGSDLIM) + 1).
2: This register is read-only when the PTG module is executing Step commands (PTGEN = 1 and
PTGSTRT = 1).
REGISTER 17-7: PTGC0LIM: PTG COUNTER 0 LIMIT REGISTER(1)

PTGC0LIM<15:8>
bit 15 bit 8

PTGC0LIM<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTGC0LIM<15:0>: PTG Counter 0 Limit Register bits

May be used to specify the loop count for the PTGJMPC0 Step command or as a limit register for the
General Purpose Counter 0.
PTGSTRT = 1).

REGISTER 17-8: PTGC1LIM: PTG COUNTER 1 LIMIT REGISTER(1)
PTGC1LIM<15:8>
bit 15 bit 8

PTGC1LIM<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTGC1LIM<15:0>: PTG Counter 1 Limit Register bits

May be used to specify the loop count for the PTGJMPC1 Step command or as a limit register for the
General Purpose Counter 1.
PTGSTRT = 1).
REGISTER 17-9: PTGHOLD: PTG HOLD REGISTER(1)

PTGHOLD<15:8>
bit 15 bit 8

PTGHOLD<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTGHOLD<15:0>: PTG General Purpose Hold Register bits

Holds user-supplied data to be copied to the PTGTxLIM, PTGCxLIM, PTGSDLIM or PTGL0 register
with the PTGCOPY command.
PTGSTRT = 1).

REGISTER 17-10: PTGADJ: PTG ADJUST REGISTER(1)
PTGADJ<15:8>
bit 15 bit 8

PTGADJ<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTGADJ<15:0>: PTG Adjust Register bits

This register holds user-supplied data to be added to the PTGTxLIM, PTGCxLIM, PTGSDLIM or
PTGL0 register with the PTGADD command.
PTGSTRT = 1).
REGISTER 17-11: PTGL0: PTG LITERAL 0 REGISTER(1)

PTGL0<15:8>
bit 15 bit 8

PTGL0<7:0>
bit 7 bit 0
Legend:
bit 15-0 PTGL0<15:0>: PTG Literal 0 Register bits

This register holds the 6-bit value to be written to the CNVCHSEL<5:0> bits (ADCON3L<5:0>) with
the PTGCTRL Step command.
PTGSTRT = 1).

REGISTER 17-12: PTGQPTR: PTG STEP QUEUE POINTER REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — PTGQPTR<4:0>
bit 7 bit 0
Legend:

bit 4-0 PTGQPTR<4:0>: PTG Step Queue Pointer Register bits
This register points to the currently active Step command in the Step queue.
PTGSTRT = 1).
REGISTER 17-13: PTGQUEx: PTG STEP QUEUE REGISTER x (x = 0-15)(1,3)

STEP(2x + 1)<7:0>(2)
bit 15 bit 8

STEP(2x)<7:0>(2)
bit 7 bit 0
Legend:
bit 15-8 STEP(2x + 1)<7:0>: PTG Step Queue Pointer Register bits(2)
A queue location for storage of the STEP(2x +1) command byte.
bit 7-0 STEP(2x)<7:0>: PTG Step Queue Pointer Register bits(2)
A queue location for storage of the STEP(2x) command byte.
PTGSTRT = 1).
2: Refer to Table 17-1 for the Step command encoding.
3: The Step registers maintain their values on any type of Reset.

17.3 Step Commands and Format
TABLE 17-1: PTG STEP COMMAND FORMAT

Step Command Byte:
STEPx<7:0>
CMD<3:0> OPTION<3:0>
bit 7 bit 4 bit 3 bit 0
bit 7-4 Step

CMD<3:0> Command Description
Command
0000 PTGCTRL Execute control command as described by OPTION<3:0>
0001 PTGADD Add contents of PTGADJ register to target register as described by
OPTION<3:0>
PTGCOPY Copy contents of PTGHOLD register to target register as described by
OPTION<3:0>
001x PTGSTRB Copy the value contained in CMD0:OPTION<3:0> to the CNVCHSEL<5:0> bits
(ADCON3L<5:0>)
0100 PTGWHI Wait for a low-to-high edge input from selected PTG trigger input as described
by OPTION<3:0>
0101 PTGWLO Wait for a high-to-low edge input from selected PTG trigger input as described
by OPTION<3:0>
0110 Reserved Reserved
0111 PTGIRQ Generate individual interrupt request as described by OPTION<3:0>
100x PTGTRIG Generate individual trigger output as described by <<CMD0>:OPTION<3:0>>
101x PTGJMP Copy the value indicated in <<CMD0>:OPTION<3:0>> to the PTG Queue
Pointer (PTGQPTR) and jump to that Step queue
110x PTGJMPC0 PTGC0 = PTGC0LIM: Increment the PTG Queue Pointer (PTGQPTR)
PTGC0  PTGC0LIM: Increment PTG Counter 0 (PTGC0) and copy the value
indicated in <<CMD0>:OPTION<3:0>> to the PTG Queue Pointer (PTGQPTR)
and jump to that Step queue
111x PTGJMPC1 PTGC1 = PTGC1LIM: Increment the PTG Queue Pointer (PTGQPTR)
PTGC1  PTGC1LIM: Increment PTG Counter 1 (PTGC1) and copy the value
indicated in <<CMD0>:OPTION<3:0>> to the PTG Queue Pointer (PTGQPTR)
and jump to that Step queue
Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOP instruction).
2: Refer to Table 17-2 for the trigger output descriptions.

TABLE 17-1: PTG STEP COMMAND FORMAT (CONTINUED)
bit 3-0 Step
OPTION<3:0> Option Description
Command
PTGCTRL(1) 0000 Reserved
0001 Reserved
0010 Disable PTG Step Delay Timer (PTGSD)
0011 Reserved
0100 Reserved
0101 Reserved
0110 Enable PTG Step Delay Timer (PTGSD)
0111 Reserved
1000 Start and wait for the PTG Timer0 to match the PTG Timer0 Limit register
1001 Start and wait for the PTG Timer1 to match the PTG Timer1 Limit register
1010 Reserved
1011 Wait for software trigger bit transition from low-to-high before continuing
(PTGSWT = 0 to 1)
1100 Copy contents of the PTG Counter 0 register to the CNVCHSEL<5:0> bits
(ADCON3L<5:0>)
1101 Copy contents of the PTG Counter 1 register to the CNVCHSEL<5:0> bits
(ADCON3L<5:0>)
1110 Copy contents of the PTG Literal 0 register to the CNVCHSEL<5:0> bits
(ADCON3L<5:0>)
1111 Generate the triggers indicated in the PTG Broadcast Trigger Enable register
(PTGBTE)
PTGADD(1) 0000 Add contents of PTGADJ register to the PTG Counter 0 Limit register (PTGC0LIM)
0001 Add contents of PTGADJ register to the PTG Counter 1 Limit register (PTGC1LIM)
0010 Add contents of PTGADJ register to the PTG Timer0 Limit register (PTGT0LIM)
0011 Add contents of PTGADJ register to the PTG Timer1 Limit register (PTGT1LIM)
0100 Add contents of PTGADJ register to the PTG Step Delay Limit register
(PTGSDLIM)
0101 Add contents of PTGADJ register to the PTG Literal 0 register (PTGL0)
0110 Reserved
0111 Reserved
(1)
PTGCOPY 1000 Copy contents of PTGHOLD register to the PTG Counter 0 Limit register
(PTGC0LIM)
1001 Copy contents of PTGHOLD register to the PTG Counter 1 Limit register
(PTGC1LIM)
1010 Copy contents of PTGHOLD register to the PTG Timer0 Limit register (PTGT0LIM)
1011 Copy contents of PTGHOLD register to the PTG Timer1 Limit register (PTGT1LIM)
1100 Copy contents of PTGHOLD register to the PTG Step Delay Limit register
(PTGSDLIM)
1101 Copy contents of PTGHOLD register to the PTG Literal 0 register (PTGL0)
1110 Reserved
1111 Reserved

TABLE 17-1: PTG STEP COMMAND FORMAT (CONTINUED)
bit 3-0 Step
OPTION<3:0> Option Description
Command
PTGWHI(1) or 0000 PWM Special Event Trigger
PTGWLO(1) 0001 PWM master time base synchronization output
0010 PWM1 interrupt
0011 PWM2 interrupt
0100 PWM3 interrupt
0101 PWM4 interrupt
0110 PWM5 interrupt
0111 OC1 trigger event
1000 OC2 trigger event
1001 IC1 trigger event
1010 CMP1 trigger event
1110 ADC conversion done interrupt
1111 INT2 external interrupt
PTGIRQ(1) 0000 Generate PTG Interrupt 0
0001 Generate PTG Interrupt 1
0100 Reserved
• •
• •
• •
1111 Reserved
PTGTRIG(2) 00000 PTGO0
00001 PTGO1
• •
• •
• •
11110 PTGO30
11111 PTGO31

TABLE 17-2: PTG OUTPUT DESCRIPTIONS
PTG Output
PTG Output Description
Number
PTGO0 Trigger/synchronization source for OC1
PTGO4 Clock source for OC1
PTGO8 Trigger/synchronization source for IC1
PTGO12 Sample trigger for ADC
PTGO13 Reserved
PTGO14 Reserved
PTGO15 Reserved
PTGO16 PWM time base synchronous source for PWM3
PTGO17 PWM time base synchronous source for PWM4
PTGO18 Reserved
PTGO19 Reserved
PTGO20 Reserved
PTGO21 Reserved
PTGO22 Reserved
PTGO23 Reserved
PTGO24 Reserved
PTGO25 Reserved
PTGO26 CLC1 input
PTGO27 CLC2 input
PTGO28 CLC3 input
PTGO29 CLC4 input
PTGO30 PTG output to PPS input selection, RPI6
PTGO31 PTG output to PPS input selection, RPI7

18.0 SERIAL PERIPHERAL The SPI serial interface consists of four pins:
INTERFACE (SPI) • SDIx: Serial Data Input
• SDOx: Serial Data Output
Note: This data sheet summarizes the features of
• SCKx: Shift Clock Input or Output
the dsPIC33EPXXXGS70X/80X family of
devices. It is not intended to be a compre- • SSx: Active-Low Slave Select or Frame
hensive reference source. To complement Synchronization I/O Pulse
the information in this data sheet, refer to The SPI module can be configured to operate using
“Serial Peripheral Interface (SPI) with two, three or four pins. In the 3-pin mode, SSx is not
Audio Codec Support” (DS70005136) in used. In the 2-pin mode, both SDOx and SSx are not
the “dsPIC33/PIC24 Family Reference used.
Manual”, which is available from the The SPI module has the ability to generate three inter-
Microchip website (www.microchip.com). rupts, reflecting the events that occur during the data
The Serial Peripheral Interface (SPI) module is a communication. The following types of interrupts can
synchronous serial interface useful for communicating be generated:
with other peripheral or microcontroller devices. These 1. Receive interrupts are signalled by SPIxRXIF.
peripheral devices may be serial EEPROMs, shift This event occurs when:
registers, display drivers, A/D Converters, etc. The SPI - RX watermark interrupt
module is compatible with the Motorola® SPI and SIOP - SPIROV = 1
interfaces. All devices in the dsPIC33EPXXXGS70X/80X
- SPIRBF = 1
family include three SPI modules.
- SPIRBE = 1
The module supports operation in two buffer modes. In
Standard mode, data is shifted through a single serial provided the respective mask bits are enabled in
buffer. In Enhanced Buffer mode, data is shifted SPIxIMSKL/H.
through a FIFO buffer. The FIFO level depends on the 2. Transmit interrupts are signalled by SPIxTXIF.
configured mode. This event occurs when:
Variable length data can be transmitted and received, - TX watermark interrupt
from 2 to 32 bits. - SPITUR = 1
Note: Do not perform Read-Modify-Write opera- - SPITBF = 1
tions (such as bit-oriented instructions) on - SPITBE = 1
the SPIxBUF register in either Standard or provided the respective mask bits are enabled in
Enhanced Buffer mode. SPIxIMSKL/H.
The module also supports a basic framed SPI protocol 3. General interrupts are signalled by SPIxIF. This
while operating in either Master or Slave mode. A total event occurs when
of four framed SPI configurations are supported. - FRMERR = 1
SPI3 also supports Audio modes. Four different Audio - SPIBUSY = 1
modes are available. - SRMT = 1
• I2S provided the respective mask bits are enabled in
• Left Justified SPIxIMSKL/H.
• Right Justified Block diagrams of the module in Standard and Enhanced
• PCM/DSP modes are shown in Figure 18-1 and Figure 18-2.
In each of these modes, the serial clock is free-running Note: In this section, the SPI modules are
and audio data is always transferred. referred to together as SPIx, or separately
If an audio protocol data transfer takes place between as SPI1, SPI2 or SPI3. Special Function
two devices, then usually one device is the master and Registers will follow a similar notation. For
the other is the slave. However, audio data can be example, SPIxCON1 and SPIxCON2
transferred between two slaves. Because the audio refer to the control registers for any of the
protocols require free-running clocks, the master can three SPI modules.
be a third party controller. In either case, the master
generates two free-running clocks: SCKx and LRC
(Left, Right Channel Clock/SSx/FSYNC).

To set up the SPIx module for the Standard Master To set up the SPIx module for the Standard Slave mode
mode of operation: of operation:
1. If using interrupts: 1. Clear the SPIxBUF registers.
a) Clear the interrupt flag bits in the respective 2. If using interrupts:
IFSx register. a) Clear the SPIxBUFL and SPIxBUFH
b) Set the interrupt enable bits in the registers.
respective IECx register. b) Set the interrupt enable bits in the
c) Write the SPIxIP bits in the respective IPCx respective IECx register.
register to set the interrupt priority. c) Write the SPIxIP bits in the respective IPCx
2. Write the desired settings to the SPIxCON1L register to set the interrupt priority.
and SPIxCON1H registers with the MSTEN bit 3. Write the desired settings to the SPIxCON1L,
(SPIxCON1L<5>) = 1. SPIxCON1H and SPIxCON2L registers with
3. Clear the SPIROV bit (SPIxSTATL<6>). the MSTEN bit (SPIxCON1L<5>) = 0.
4. Enable SPIx operation by setting the SPIEN bit 4. Clear the SMP bit.
(SPIxCON1L<15>). 5. If the CKE bit (SPIxCON1L<8>) is set, then the
5. Write the data to be transmitted to the SPIxBUFL SSEN bit (SPIxCON1L<7>) must be set to
and SPIxBUFH registers. Transmission (and enable the SSx pin.
reception) will start as soon as data is written to 6. Clear the SPIROV bit (SPIxSTATL<6>).
the SPIxBUFL and SPIxBUFH registers. 7. Enable SPIx operation by setting the SPIEN bit
(SPIxCON1L<15>).
FIGURE 18-1: SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
Internal
Data Bus
Read Write
SPIxRXB SPIxTXB SPIxURDT

MSb
Receive
Transmit
SPIxRXSR SPIxTXSR
SDIx MSb
0
Shift 1
SDOx
Control TXELM<5:0> = 6’b0
URDTEN
SSx & FSYNC Clock Edge
Control Control Select MCLKEN
SSx/FSYNC
REFO
Baud Rate
Generator
SCKx Peripheral Clock
Edge Clock
Select Control Enable Master Clock

To set up the SPIx module for the Enhanced Buffer To set up the SPIx module for the Enhanced Buffer
Master mode of operation: Slave mode of operation:
1. If using interrupts: 1. Clear the SPIxBUFL and SPIxBUFH registers.
a) Clear the interrupt flag bits in the respective 2. If using interrupts:
IFSx register. a) Clear the interrupt flag bits in the respective
b) Set the interrupt enable bits in the IFSx register.
respective IECx register. b) Set the interrupt enable bits in the
c) Write the SPIxIP bits in the respective IPCx respective IECx register.
register. c) Write the SPIxIP bits in the respective IPCx
2. Write the desired settings to the SPIxCON1L, register to set the interrupt priority.
SPIxCON1H and SPIxCON2L registers with 3. Write the desired settings to the SPIxCON1L,
MSTEN (SPIxCON1L<5>) = 1. SPIxCON1H and SPIxCON2L registers with the
3. Clear the SPIROV bit (SPIxSTATL<6>). MSTEN bit (SPIxCON1L<5>) = 0.
4. Select Enhanced Buffer mode by setting the 4. Clear the SMP bit.
ENHBUF bit (SPIxCON1L<0>). 5. If the CKE bit is set, then the SSEN bit must be
5. Enable SPIx operation by setting the SPIEN bit set, thus enabling the SSx pin.
(SPIxCON1L<15>). 6. Clear the SPIROV bit (SPIxSTATL<6>).
6. Write the data to be transmitted to the 7. Select Enhanced Buffer mode by setting the
SPIxBUFL and SPIxBUFH registers. Transmis- ENHBUF bit (SPIxCON1L<0>).
sion (and reception) will start as soon as data is 8. Enable SPIx operation by setting the SPIEN bit
written to the SPIxBUFL and SPIxBUFH (SPIxCON1L<15>).
registers.
FIGURE 18-2: SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Internal
Data Bus
Read Write
SPIxRXB SPIxTXB SPIxURDT

MSb
Transmit
Receive
SPIxRXSR SPIxTXSR
SDIx MSb
0
Shift 1
SDOx
Control TXELM<5:0> = 6’b0
URDTEN
SSx & FSYNC Clock Edge
Control Control Select MCLKEN
SSx/FSYNC
REFO
Baud Rate
Generator
Peripheral Clock
SCKx
Edge Clock
Select Control Enable Master Clock

To set up the SPIx module for Audio mode: 3. Write the desired settings to the SPIxCON1L,
1. Clear the SPIxBUFL and SPIxBUFH registers. SPIxCON1H and SPIxCON2L registers with
AUDEN (SPIxCON1H<15>) = 1.
2. If using interrupts:
4. Clear the SPIROV bit (SPIxSTATL<6>).
a) Clear the interrupt flag bits in the respective
IFSx register. 5. Enable SPIx operation by setting the SPIEN bit
(SPIxCON1L<15>).
b) Set the interrupt enable bits in the
respective IECx register. 6. Write the data to be transmitted to the SPIxBUFL
and SPIxBUFH registers. Transmission (and
a) Write the SPIxIP bits in the respective IPCx
reception) will start as soon as data is written to
register to set the interrupt priority.
the SPIxBUFL and SPIxBUFH registers.
REGISTER 18-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW

(1,4) (1,4)
SPIEN — SPISIDL DISSDO MODE32 MODE16 SMP CKE(1)
bit 15 bit 8

SSEN(2) CKP MSTEN DISSDI DISSCK MCLKEN(3) SPIFE ENHBUF
bit 7 bit 0
Legend:
bit 15 SPIEN: SPIx On bit

1 = Enables module
0 = Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR
modifications
bit 13 SPISIDL: SPIx Stop in Idle Mode bit
1 = Halts in CPU Idle mode
0 = Continues to operate in CPU Idle mode
bit 12 DISSDO: Disable SDOx Output Port bit
1 = SDOx pin is not used by the module; pin is controlled by port function
0 = SDOx pin is controlled by the module
bit 11-10 MODE32 and MODE16: Serial Word Length Select bits(1,4)
MODE32 MODE16 AUDEN Communication

1 x 32-Bit
0 1 0 16-Bit
0 0 8-Bit
1 1 24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
1
0 0 16-Bit FIFO, 16-Bit Channel/32-Bit Frame
Note 1: When AUDEN (SPIxCON1H<15>) = 1, this module functions as if CKE = 0, regardless of its actual value.
2: When FRMEN = 1, SSEN is not used.
3: MCLKEN can only be written when the SPIEN bit = 0.
4: This channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW.

REGISTER 18-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW (CONTINUED)
bit 9 SMP: SPIx Data Input Sample Phase bit
Master Mode:
1 = Input data is sampled at the end of data output time
0 = Input data is sampled at the middle of data output time
Slave Mode:
Input data is always sampled at the middle of data output time, regardless of the SMP setting.
bit 8 CKE: SPIx Clock Edge Select bit(1)
1 = Transmit happens on transition from active clock state to Idle clock state
0 = Transmit happens on transition from Idle clock state to active clock state
bit 7 SSEN: Slave Select Enable bit (Slave mode)(2)
1 = SSx pin is used by the macro in Slave mode; SSx pin is used as the slave select input
0 = SSx pin is not used by the macro (SSx pin will be controlled by the port I/O)
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
bit 4 DISSDI: Disable SDIx Input Port bit
1 = SDIx pin is not used by the module; pin is controlled by port function
0 = SDIx pin is controlled by the module
bit 3 DISSCK: Disable SCKx Output Port bit
1 = SCKx pin is not used by the module; pin is controlled by port function
0 = SCKx pin is controlled by the module
bit 2 MCLKEN: Master Clock Enable bit(3)
1 = REFO is used by the Baud Rate Generator (BRG)
0 = Peripheral clock is used by the BRG
bit 1 SPIFE: Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock
0 = Frame Sync pulse (Idle-to-active edge) precedes the first bit clock
bit 0 ENHBUF: Enhanced Buffer Enable bit
1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
Note 1: When AUDEN (SPIxCON1H<15>) = 1, this module functions as if CKE = 0, regardless of its actual value.
2: When FRMEN = 1, SSEN is not used.
3: MCLKEN can only be written when the SPIEN bit = 0.
4: This channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW.

REGISTER 18-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH
(1) (2) (3) (4)
AUDEN SPISGNEXT IGNROV IGNTUR AUDMONO URDTEN AUDMOD1 AUDMOD0(4)
bit 15 bit 8

FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT2 FRMCNT1 FRMCNT0
bit 7 bit 0
Legend:
bit 15 AUDEN: Audio Codec Support Enable bit(1)

1 = Audio protocol is enabled; MSTEN controls the direction of both SCKx and frame (a.k.a. LRC), and
this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT<2:0> = 001 and SMP = 0,
regardless of their actual values
0 = Audio protocol is disabled
bit 14 SPISGNEXT: SPIx Sign-Extend RX FIFO Read Data Enable bit
1 = Data from RX FIFO is sign-extended
0 = Data from RX FIFO is not sign-extended
bit 13 IGNROV: Ignore Receive Overflow bit
1 = A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO is not overwritten
by the receive data
0 = A ROV is a critical error that stops SPI operation
bit 12 IGNTUR: Ignore Transmit Underrun bit
1 = A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN is transmitted
until the SPIxTXB is not empty
0 = A TUR is a critical error that stops SPI operation
bit 11 AUDMONO: Audio Data Format Transmit bit(2)
1 = Audio data is mono (i.e., each data word is transmitted on both left and right channels)
0 = Audio data is stereo
bit 10 URDTEN: Transmit Underrun Data Enable bit(3)
1 = Transmits data out of SPIxURDT register during Transmit Underrun conditions
0 = Transmits the last received data during Transmit Underrun conditions
bit 9-8 AUDMOD<1:0>: Audio Protocol Mode Selection bits(4)
11 = PCM/DSP mode
10 = Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01 = Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
00 = I2S mode: This module functions as if SPIFE = 0, regardless of its actual value
bit 7 FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled (SSx pin is used as the FSYNC input/output)
0 = Framed SPIx support is disabled
Note 1: AUDEN can only be written when the SPIEN bit = 0.

2: AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.
3: URDTEN is only valid when IGNTUR = 1.
4: The AUDMOD<1:0> bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1.
When NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.

REGISTER 18-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH (CONTINUED)
bit 6 FRMSYNC: Frame Sync Pulse Direction Control bit
1 = Frame Sync pulse input (slave)
0 = Frame Sync pulse output (master)
bit 5 FRMPOL: Frame Sync/Slave Select Polarity bit
1 = Frame Sync pulse/slave select is active-high
0 = Frame Sync pulse/slave select is active-low
bit 4 MSSEN: Master Mode Slave Select Enable bit
1 = SPIx slave select support is enabled with polarity determined by FRMPOL (SSx pin is automatically
driven during transmission in Master mode)
0 = Slave select SPIx support is disabled (SSx pin will be controlled by port I/O)
bit 3 FRMSYPW: Frame Sync Pulse-Width bit
1 = Frame Sync pulse is one serial word length wide (as defined by MODE<32,16>/WLENGTH<4:0>)
0 = Frame Sync pulse is one clock (SCK) wide
bit 2-0 FRMCNT<2:0>: Frame Sync Pulse Counter bits
Controls the number of serial words transmitted per Sync pulse.
111 = Reserved
110 = Reserved
101 = Generates a Frame Sync pulse on every 32 serial words
001 = Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols)
000 = Generates a Frame Sync pulse on each serial word
Note 1: AUDEN can only be written when the SPIEN bit = 0.

2: AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN = 1.
3: URDTEN is only valid when IGNTUR = 1.
4: The AUDMOD<1:0> bits can only be written when the SPIEN bit = 0 and are only valid when AUDEN = 1.
When NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.

REGISTER 18-3: SPIxCON2L: SPIx CONTROL REGISTER 2 LOW
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

(1,2)
— — — WLENGTH<4:0>
bit 7 bit 0
Legend:

bit 4-0 WLENGTH<4:0>: Variable Word Length bits(1,2)
11111 = 32-bit data
11110 = 31-bit data
11101 = 30-bit data
11100 = 29-bit data
11011 = 28-bit data
11010 = 27-bit data
11001 = 26-bit data
11000 = 25-bit data
10111 = 24-bit data
10110 = 23-bit data
10101 = 22-bit data
10100 = 21-bit data
10011 = 20-bit data
10010 = 19-bit data
10001 = 18-bit data
10000 = 17-bit data
01111 = 16-bit data
01110 = 15-bit data
01101 = 14-bit data
01100 = 13-bit data
01011 = 12-bit data
01010 = 11-bit data
01001 = 10-bit data
01000 = 9-bit data
00111 = 8-bit data
00110 = 7-bit data
00101 = 6-bit data
00100 = 5-bit data
00011 = 4-bit data
00010 = 3-bit data
00001 = 2-bit data
00000 = See MODE<32,16> bits in SPIxCON1L<11:10>
Note 1: These bits are effective when AUDEN = 0 only.

2: Varying the length by changing these bits does not affect the depth of the TX/RX FIFO.

REGISTER 18-4: SPIxSTATL: SPIx STATUS REGISTER LOW
U-0 U-0 U-0 HS/R/C-0 HSC/R-0 U-0 U-0 HSC/R-0
— — — FRMERR SPIBUSY — — SPITUR(1)
bit 15 bit 8
HSC/R-0 HS/R/C-0 HSC/R-1 U-0 HSC/R-1 U-0 HSC/R-0 HSC/R-0

SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF
bit 7 bit 0
Legend: C = Clearable bit U = Unimplemented, read as ‘0’

R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware Settable bit

bit 12 FRMERR: SPIx Frame Error Status bit
1 = Frame error is detected
0 = No frame error is detected
bit 11 SPIBUSY: SPIx Activity Status bit
1 = Module is currently busy with some transactions
0 = No ongoing transactions (at time of read)
bit 8 SPITUR: SPIx Transmit Underrun Status bit(1)
1 = Transmit buffer has encountered a Transmit Underrun condition
0 = Transmit buffer does not have a Transmit Underrun condition
bit 7 SRMT: Shift Register Empty Status bit
1 = No current or pending transactions (i.e., neither SPIxTXB or SPIxTXSR contains data to transmit)
0 = Current or pending transactions
bit 6 SPIROV: SPIx Receive Overflow Status bit
1 = A new byte/half-word/word has been completely received when the SPIxRXB was full
0 = No overflow
bit 5 SPIRBE: SPIx RX Buffer Empty Status bit
1 = RX buffer is empty
0 = RX buffer is not empty
Standard Buffer mode:
Automatically set in hardware when SPIxBUF is read from, reading SPIxRXB. Automatically cleared in
hardware when SPIx transfers data from SPIxRXSR to SPIxRXB.
Enhanced Buffer mode:
Indicates RXELM<5:0> = 000000.
Note 1: SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the
Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by
software.

REGISTER 18-4: SPIxSTATL: SPIx STATUS REGISTER LOW (CONTINUED)
bit 3 SPITBE: SPIx Transmit Buffer Empty Status bit
1 = SPIxTXB is empty
0 = SPIxTXB is not empty
Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Automatically
cleared in hardware when SPIxBUF is written, loading SPIxTXB.
Indicates TXELM<5:0> = 000000.
bit 1 SPITBF: SPIx Transmit Buffer Full Status bit
1 = SPIxTXB is full
0 = SPIxTXB not full
Automatically set in hardware when SPIxBUF is written, loading SPIxTXB. Automatically cleared in
hardware when SPIx transfers data from SPIxTXB to SPIxTXSR.
Indicates TXELM<5:0> = 111111.
bit 0 SPIRBF: SPIx Receive Buffer Full Status bit
1 = SPIxRXB is full
0 = SPIxRXB is not full
Automatically set in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB. Automatically
cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Indicates RXELM<5:0> = 111111.
Note 1: SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the
Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by
software.

REGISTER 18-5: SPIxSTATH: SPIx STATUS REGISTER HIGH
U-0 U-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0
(3) (2) (1)
— — RXELM5 RXELM4 RXELM3 RXELM2 RXELM1 RXELM0
bit 15 bit 8

(3) (2) (1)
— — TXELM5 TXELM4 TXELM3 TXELM2 TXELM1 TXELM0
bit 7 bit 0


bit 13-8 RXELM<5:0>: Receive Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3)
bit 5-0 TXELM<5:0>: Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3)
Note 1: RXELM3 and TXELM3 bits are only present when FIFODEPTH = 8 or higher.
2: RXELM4 and TXELM4 bits are only present when FIFODEPTH = 16 or higher.
3: RXELM5 and TXELM5 bits are only present when FIFODEPTH = 32.

REGISTER 18-6: SPIxIMSKL: SPIx INTERRUPT MASK REGISTER LOW
U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0
— — — FRMERREN BUSYEN — — SPITUREN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0

SRMTEN SPIROVEN SPIRBEN — SPITBEN — SPITBFEN SPIRBFEN
bit 7 bit 0
Legend:

bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit
1 = Frame error generates an interrupt event
0 = Frame error does not generate an interrupt event
bit 11 BUSYEN: Enable Interrupt Events via SPIBUSY bit
1 = SPIBUSY generates an interrupt event
0 = SPIBUSY does not generate an interrupt event
bit 8 SPITUREN: Enable Interrupt Events via SPITUR bit
1 = Transmit Underrun (TUR) generates an interrupt event
0 = Transmit Underrun does not generate an interrupt event
bit 7 SRMTEN: Enable Interrupt Events via SRMT bit
1 = Shift Register Empty (SRMT) generates interrupt events
0 = Shift Register Empty does not generate interrupt events
bit 6 SPIROVEN: Enable Interrupt Events via SPIROV bit
1 = SPIx Receive Overflow (ROV) generates an interrupt event
0 = SPIx Receive Overflow does not generate an interrupt event
bit 5 SPIRBEN: Enable Interrupt Events via SPIRBE bit
1 = SPIx RX buffer empty generates an interrupt event
0 = SPIx RX buffer empty does not generate an interrupt event
bit 3 SPITBEN: Enable Interrupt Events via SPITBE bit
1 = SPIx transmit buffer empty generates an interrupt event
0 = SPIx transmit buffer empty does not generate an interrupt event
bit 1 SPITBFEN: Enable Interrupt Events via SPITBF bit
1 = SPIx transmit buffer full generates an interrupt event
0 = SPIx transmit buffer full does not generate an interrupt event
bit 0 SPIRBFEN: Enable Interrupt Events via SPIRBF bit
1 = SPIx receive buffer full generates an interrupt event
0 = SPIx receive buffer full does not generate an interrupt event

REGISTER 18-7: SPIxIMSKH: SPIx INTERRUPT MASK REGISTER HIGH
RXWIEN — RXMSK5(1) RXMSK4(1,4) RXMSK3(1,3) RXMSK2(1,2) RXMSK1(1) RXMSK0(1)
bit 15 bit 8

TXWIEN — TXMSK5(1) TXMSK4(1,4) TXMSK3(1,3) TXMSK2(1,2) TXMSK1(1) TXMSK0(1)
bit 7 bit 0
Legend:
bit 15 RXWIEN: Receive Watermark Interrupt Enable bit

1 = Triggers receive buffer element watermark interrupt when RXMSK<5:0>  RXELM<5:0>
0 = Disables receive buffer element watermark interrupt
bit 13-8 RXMSK<5:0>: RX Buffer Mask bits(1,2,3,4)
RX mask bits; used in conjunction with the RXWIEN bit.
bit 7 TXWIEN: Transmit Watermark Interrupt Enable bit
1 = Triggers transmit buffer element watermark interrupt when TXMSK<5:0> = TXELM<5:0>
0 = Disables transmit buffer element watermark interrupt
bit 5-0 TXMSK<5:0>: TX Buffer Mask bits(1,2,3,4)
TX mask bits; used in conjunction with the TXWIEN bit.
Note 1: Mask values higher than FIFODEPTH are not valid. The module will not trigger a match for any value in
this case.
2: RXMSK2 and TXMSK2 bits are only present when FIFODEPTH = 8 or higher.
3: RXMSK3 and TXMSK3 bits are only present when FIFODEPTH = 16 or higher.
4: RXMSK4 and TXMSK4 bits are only present when FIFODEPTH = 32.

FIGURE 18-3: SPIx MASTER/SLAVE CONNECTION (STANDARD MODE)
Processor 1 (SPIx Master) Processor 2 (SPIx Slave)
SDOx SDIx
Serial Receive Buffer Serial Transmit Buffer

(SPIxRXB)(2) (SPIxTXB)(2)
Shift Register SDIx SDOx Shift Register

(SPIxRXSR) (SPIxTXSR)
MSb LSb SDOx SDIx MSb LSb
Shift Register Shift Register

(SPIxTXSR) (SPIxRXSR)
MSb LSb MSb LSb
Serial Clock
Serial Transmit Buffer SCKx SCKx Serial Receive Buffer
(SPIxTXB)(2) (SPIxRXB)(2)
SSx(1)
SPIx Buffer SPIx Buffer

(SPIxBUF)(2) (SPIxBUF)(2)
MSTEN (SPIxCON1L<5>) = 1) MSSEN (SPIxCON1H<4>) = 1 and MSTEN (SPIxCON1L<5>) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory-mapped to SPIxBUF.

FIGURE 18-4: SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
Processor 1 (SPIx Master) Processor 2 (SPIx Slave)
SDOx SDIx
Serial Receive FIFO Serial Transmit FIFO

(SPIxRXB)(2) (SPIxTXB)(2)
Shift Register SDIx SDOx Shift Register

(SPIxRXSR) (SPIxTXSR)
MSb LSb SDOx SDIx MSb LSb
Shift Register Shift Register

(SPIxTXSR) (SPIxRXSR)
MSb LSb MSb LSb
Serial Clock
Serial Transmit FIFO SCKx SCKx Serial Receive FIFO
(SPIxTXB)(2) (SPIxRXB)(2)
SSx(1)
SPIx Buffer SPIx Buffer

(SPIxBUF)(2) (SPIxBUF)(2)
MSTEN (SPIxCON1L<5>) = 1) MSSEN (SPIxCON1H<4>) = 1 and MSTEN (SPIxCON1L<5>) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory-mapped to SPIxBUF.
FIGURE 18-5: SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24F Processor 2
(SPIx Master, Frame Master)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse

FIGURE 18-6: SPIx MASTER, FRAME SLAVE CONNECTION DIAGRAM
PIC24F Processor 2
SPIx Master, Frame Slave)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
FIGURE 18-7: SPIx SLAVE, FRAME MASTER CONNECTION DIAGRAM
PIC24F Processor 2
(SPIx Slave, Frame Master)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
FIGURE 18-8: SPIx SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC24F Processor 2
(SPIx Slave, Frame Slave)
SDOx SDIx
SDIx SDOx
Serial Clock
SCKx SCKx
SSx SSx
Frame Sync
Pulse
EQUATION 18-1: RELATIONSHIP BETWEEN DEVICE AND SPIx CLOCK SPEED

FPB
Baud Rate =
(2 * (SPIxBRG + 1))
Where:
FPB is the Peripheral Bus Clock Frequency.

19.0 INTER-INTEGRATED CIRCUIT The I2C module offers the following key features:
(I2C) • I2C Interface supporting both Master and Slave
modes of Operation
Note 1: This data sheet summarizes the • I2C Slave mode Supports 7 and 10-Bit Addressing
• I2C Master mode Supports 7 and 10-Bit Addressing
80X family of devices. It is not intended
to be a comprehensive reference source. • I2C Port allows Bidirectional Transfers between
To complement the information in this Master and Slaves
data sheet, refer to “Inter-Integrated • Serial Clock Synchronization for I2C Port can be
Circuit (I2C)” (DS70000195) in the used as a Handshake Mechanism to Suspend
“dsPIC33/PIC24 Family Reference Man- and Resume Serial Transfer (SCLREL control)
ual”, which is available from the Microchip • I2C Supports Multi-Master Operation, Detects Bus
website (www.microchip.com). Collision and Arbitrates Accordingly
2: Some registers and associated bits • System Management Bus (SMBus) Support
described in this section may not be • Alternate I2C Pin Mapping (ASCLx/ASDAx)
Section 4.0 “Memory Organization” in 19.1 I2C Resources
and bit information. Many useful resources are provided on the main prod-
The dsPIC33EPXXXGS70X/80X family of devices in this data sheet. This product page contains the latest
contains two Inter-Integrated Circuit (I2C) modules: updates and additional information.
I2C1 and I2C2.
The I2C module provides complete hardware support 19.1.1 KEY RESOURCES
for both Slave and Multi-Master modes of the I2C serial • “Inter-Integrated Circuit (I2C)” (DS70000195) in
communication standard, with a 16-bit interface. the “dsPIC33/PIC24 Family Reference Manual”
The I2C module has a 2-pin interface: • Code Samples
• The SCLx/ASCLx pin is clock • Application Notes
• The SDAx/ASDAx pin is data • Software Libraries
• Webinars
Manual” Sections

FIGURE 19-1: I2Cx BLOCK DIAGRAM (x = 1 OR 2)
Internal
Data Bus
I2CxRCV
Read
Shift
SCLx/ASCLx Clock
I2CxRSR
LSb
SDAx/ASDAx Address Match

Match Detect Write
I2CxMSK
Write Read
I2CxADD
Read
Start and Stop

Bit Detect
Write
Start and Stop

Bit Generation I2CxSTAT
Control Logic
Read
Collision Write
Detect
I2CxCONH
Acknowledge
Generation Read
Write
Clock
Stretching I2CxCONL
Read
Write
I2CxTRN
LSb
Shift Clock Read
Reload
Control
Write
BRG Down Counter I2CxBRG
Read
FP/2

19.2 I2C Control Registers
REGISTER 19-1: I2CxCONL: I2Cx CONTROL REGISTER LOW

R/W-0 U-0 R/W-0 HC/R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
I2CEN — I2CSIDL SCLREL STRICT A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 HC/R/W-0 HC/R/W-0 HC/R/W-0 HC/R/W-0 HC/R/W-0

GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bit

bit 15 I2CEN: I2Cx Enable bit

1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module; all I2C pins are controlled by port functions
bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Releases SCLx clock
0 = Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). It is cleared by hard-
ware at the beginning of every slave data byte transmission. It is cleared by hardware at the end of every
slave address byte reception. It is cleared by hardware at the end of every slave data byte reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). It is cleared by hardware at the beginning
of every slave data byte transmission. It is cleared by hardware at the end of every slave address byte
reception.
bit 11 STRICT: Strict I2Cx Reserved Address Enable bit
1 = Strict Reserved Addressing is Enabled:
In Slave mode, the device will NACK any reserved address. In Master mode, the device is allowed
to generate addresses within the reserved address space.
0 = Reserved Addressing is Acknowledged:
In Slave mode, the device will ACK any reserved address. In Master mode, the device should not
address a slave device with a reserved address.
bit 10 A10M: 10-Bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enables I/O pin thresholds compliant with SMBus specification
0 = Disables SMBus input thresholds

REGISTER 19-1: I2CxCONL: I2Cx CONTROL REGISTER LOW (CONTINUED)
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enables interrupt when a general call address is received in I2CxRSR (module is enabled for reception)
0 = General call address is disabled
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1 = Enables software controlled clock stretching
0 = Disables software controlled clock stretching
bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; it is
cleared by hardware at the end of the master Acknowledge sequence
0 = Acknowledge sequence is not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C; it is cleared by hardware at the end of the eighth bit of the master
receive data byte
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiates Stop condition on SDAx and SCLx pins; it is cleared by hardware at the end of the master
Stop sequence
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiates Repeated Start condition on SDAx and SCLx pins; it is cleared by hardware at the end of
the master Repeated Start sequence
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiates Start condition on SDAx and SCLx pins; it is cleared by hardware at the end of the master
Start sequence
0 = Start condition is not in progress

REGISTER 19-2: I2CxCONH: I2Cx CONTROL REGISTER HIGH
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

— PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:

bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enables interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1 = Enables interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
bit 4 BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)
1 = I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of
the I2COV only if the RBF bit = 0
0 = I2CxRCV is only updated when I2COV is clear
bit 3 SDAHT: SDAx Hold Time Selection bit
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
1 = Enables slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
If the rising edge of SCLx and SDAx is sampled low when the module is in a high state, the BCL bit is
set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences.
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte, the SCLREL
(I2CxCONL<12>) bit will be cleared and SCLx will be held low
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte, the slave hardware clears the
SCLREL (I2CxCONL<12>) bit and SCLx is held low
0 = Data holding is disabled

REGISTER 19-3: I2CxSTAT: I2Cx STATUS REGISTER
HSC/R-0 HSC/R-0 HSC/R-0 U-0 U-0 HS/R/C-0 HSC/R-0 HSC/R-0
ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10
bit 15 bit 8
HS/R/C-0 HS/R/C-0 HSC/R-0 HSC/R/C-0 HSC/R/C-0 HSC/R-0 HSC/R-0 HSC/R-0

IWCOL I2COV D_A P S R_W RBF TBF
bit 7 bit 0
Legend: C = Clearable bit ‘0’ = Bit is cleared HS = Hardware Settable bit

-n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’
bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation)
1 = NACK was received from slave
0 = ACK was received from slave
It is set or cleared by hardware at the end of a slave Acknowledge.
bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
It is set by hardware at the beginning of master transmission. It is cleared by hardware at the end of slave
Acknowledge.
bit 13 ACKTIM: Acknowledge Time Status bit (I2C Slave mode only)
1 = I2C bus is an Acknowledge sequence, set on the 8th falling edge of SCLx
0 = Not an Acknowledge sequence, cleared on the 9th rising edge of SCLx
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No bus collision detected
It is set by hardware at detection of a bus collision.
bit 9 GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
It is set by hardware when address matches the general call address. It is cleared by hardware at Stop
detection.
bit 8 ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
It is set by hardware at the match of the 2nd byte of the matched 10-bit address. It is cleared by hardware
at Stop detection.
bit 7 IWCOL: I2Cx Write Collision Detect bit
1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy
0 = No collision
It is set by hardware at the occurrence of a write to I2CxTRN while busy (cleared by software).
bit 6 I2COV: I2Cx Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register was still holding the previous byte
0 = No overflow
It is set by hardware at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

REGISTER 19-3: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 5 D_A: Data/Address bit (I2C Slave mode only)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was a device address
It is cleared by hardware at a device address match. It is set by hardware by reception of a slave byte.
bit 4 P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
It is set or cleared by hardware when a Start, Repeated Start or Stop is detected.
bit 3 S: Start bit
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
It is set or cleared by hardware when a Start, Repeated Start or Stop is detected.
bit 2 R_W: Read/Write Information bit (I2C Slave mode only)
1 = Read – Indicates data transfer is output from the slave
0 = Write – Indicates data transfer is input to the slave
It is set or cleared by hardware after reception of an I 2C device address byte.
bit 1 RBF: Receive Buffer Full Status bit
1 = Receive is complete, I2CxRCV is full
0 = Receive is not complete, I2CxRCV is empty
It is set by hardware when I2CxRCV is written with a received byte. It is cleared by hardware when
software reads I2CxRCV.
bit 0 TBF: Transmit Buffer Full Status bit
1 = Transmit is in progress, I2CxTRN is full
0 = Transmit is complete, I2CxTRN is empty
It is set by hardware when software writes to I2CxTRN. It is cleared by hardware at completion of a data
transmission.

REGISTER 19-4: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — AMSK<9:8>
bit 15 bit 8

AMSK<7:0>
bit 7 bit 0
Legend:

bit 9-0 AMSK<9:0>: Address Mask Select bits
For 10-Bit Address:
1 = Enables masking for bit Ax of incoming message address; bit match is not required in this position
0 = Disables masking for bit Ax; bit match is required in this position
For 7-Bit Address (I2CxMSK<6:0> only):
1 = Enables masking for bit Ax + 1 of incoming message address; bit match is not required in this position
0 = Disables masking for bit Ax + 1; bit match is required in this position

20.0 UNIVERSAL ASYNCHRONOUS The primary features of the UARTx module are:
RECEIVER TRANSMITTER • Full-Duplex, 8 or 9-Bit Data Transmission through
(UART) the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
Note 1: This data sheet summarizes the • One or Two Stop bits
features of the dsPIC33EPXXXGS70X/ • Hardware Flow Control Option with UxCTS and
80X family of devices. It is not intended UxRTS Pins
to be a comprehensive reference
• Fully Integrated Baud Rate Generator with
source. To complement the information
16-Bit Prescaler
in this data sheet, refer to “Universal
Asynchronous Receiver Transmitter • Baud Rates Ranging from 4.375 Mbps to 67 bps in
(UART)” (DS70000582) in the “dsPIC33/ 16x mode at 70 MIPS
PIC24 Family Reference Manual”, which • Baud Rates Ranging from 17.5 Mbps to 267 bps in
is available from the Microchip website 4x mode at 70 MIPS
(www.microchip.com). • 4-Deep First-In First-Out (FIFO) Transmit Data
2: Some registers and associated bits Buffer
described in this section may not be • 4-Deep FIFO Receive Data Buffer
available on all devices. Refer to • Parity, Framing and Buffer Overrun Error Detection
Section 4.0 “Memory Organization” in • Support for 9-Bit mode with Address Detect
this data sheet for device-specific register (9th bit = 1)
• Transmit and Receive Interrupts
The dsPIC33EPXXXGS70X/80X family of devices • A Separate Interrupt for all UARTx Error Conditions
contains two UART modules. • Loopback mode for Diagnostic Support
The Universal Asynchronous Receiver Transmitter • Support for Sync and Break Characters
(UART) module is one of the serial I/O modules avail- • Support for Automatic Baud Rate Detection
able in the dsPIC33EPXXXGS70X/80X device family. • IrDA® Encoder and Decoder Logic
The UART is a full-duplex, asynchronous system that
• 16x Baud Clock Output for IrDA Support
can communicate with peripheral devices, such as
personal computers, LIN/J2602, RS-232 and RS-485 A simplified block diagram of the UARTx module is
interfaces. The module also supports a hardware flow shown in Figure 20-1. The UARTx module consists of
control option with the UxCTS and UxRTS pins, and these key hardware elements:
also includes an IrDA® encoder and decoder. • Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 20-1: UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control UxRTS/BCLKx

UxCTS
UARTx Receiver UxRX
UARTx Transmitter UxTX

20.1 UART Helpful Tips 20.2 UART Resources
1. In multi-node, direct connect UART networks, Many useful resources are provided on the main prod-
UART receive inputs react to the complemen- uct page of the Microchip website for the devices listed
tary logic level defined by the URXINV bit in this data sheet. This product page contains the latest
(UxMODE<4>), which defines the Idle state, the updates and additional information.
default of which is logic high (i.e., URXINV = 0).
Because remote devices do not initialize at the 20.2.1 KEY RESOURCES
same time, it is likely that one of the devices, • “Universal Asynchronous Receiver
because the RX line is floating, will trigger a Start Transmitter (UART)” (DS70000582) in the
bit detection and will cause the first byte received, “dsPIC33/PIC24 Family Reference Manual”
after the device has been initialized, to be invalid.
• Code Samples
To avoid this situation, the user should use a pull-
up or pull-down resistor on the RX pin depending • Application Notes
on the value of the URXINV bit. • Software Libraries
a) If URXINV = 0, use a pull-up resistor on the • Webinars
UxRX pin. • All Related “dsPIC33/PIC24 Family Reference
b) If URXINV = 1, use a pull-down resistor on Manual” Sections
the UxRX pin. • Development Tools
2. The first character received on a wake-up from
Sleep mode, caused by activity on the UxRX pin
of the UARTx module, will be invalid. In Sleep
mode, peripheral clocks are disabled. By the
time the oscillator system has restarted and
stabilized from Sleep mode, the baud rate bit
sampling clock, relative to the incoming UxRX
bit timing, is no longer synchronized, resulting in
the first character being invalid; this is to be
expected.

20.3 UART Control Registers
REGISTER 20-1: UxMODE: UARTx MODE REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0
bit 15 bit 8
HC/R/W-0 R/W-0 HC/R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL
bit 7 bit 0
Legend: HC = Hardware Clearable bit

bit 15 UARTEN: UARTx Enable bit(1)

1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is
minimal
bit 13 USIDL: UARTx Stop in Idle Mode bit
bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder are enabled
0 = IrDA encoder and decoder are disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 9-8 UEN<1:0>: UARTx Pin Enable bits
11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by PORT latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by PORT latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
PORT latches
bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1 = UARTx continues to sample the UxRX pin, interrupt is generated on the falling edge; bit is cleared
in hardware on the following rising edge
0 = No wake-up is enabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Enables Loopback mode
0 = Loopback mode is disabled
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the

“dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for receive or
transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).

REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement is disabled or completed
bit 4 URXINV: UARTx Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the

“dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for receive or
transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).

REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 HC/R/W-0 R/W-0 R-0 R-1
(1)
UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0

URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA
bit 7 bit 0
Legend: C = Clearable bit HC = Hardware Clearable bit

bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits

11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14 UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA® encoded, UxTX Idle state is ‘1’
0 = IrDA encoded, UxTX Idle state is ‘0’
bit 11 UTXBRK: UARTx Transmit Break bit
1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10 UTXEN: UARTx Transmit Enable bit(1)
1 = Transmit is enabled, UxTX pin is controlled by UARTx
0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; UxTX pin is controlled
by the PORT
bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has four data characters)
10 = Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)
0x = Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.

REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive FIFO)
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed; clearing a previously set OERR bit (1  0 transition) resets the
receiver buffer and the UxRSR to the empty state
bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.

21.0 CONFIGURABLE LOGIC CELL The Configurable Logic Cell (CLC) module allows the
user to specify combinations of signals as inputs to a
(CLC)
logic function and to use the logic output to control
Note: This data sheet summarizes the features other peripherals or I/O pins. This provides greater flex-
of the dsPIC33EPXXXGS70X/80X family ibility and potential in embedded designs, since the
devices. It is not intended to be a CLC module can operate outside the limitations of
comprehensive reference source. To com- software execution and supports a vast amount of
plement the information in this data sheet, output designs.
refer to “Configurable Logic Cell (CLC)” There are four input gates to the selected logic func-
(DS70005298) in the “dsPIC33/PIC24 tion. These four input gates select from a pool of up to
Family Reference Manual”, which is 32 signals that are selected using four data source
available from the Microchip website selection multiplexers. Figure 21-1 shows an overview
(www.microchip.com). of the module. Figure 21-3 shows the details of the data
source multiplexers and logic input gate connections.
FIGURE 21-1: CLCx MODULE
DS1<2:0> G1POL
DS2<2:0> G2POL
DS3<2:0> G3POL
DS4<2:0> G4POL
D Q LCOUT
FCY CLK
MODE<2:0>
LCOE
CLC LCEN
Gate 1
Inputs TRISx Control
(32) Input Gate 2 CLCx
Logic Output
Data
Gate 3 Function Logic CLCx
Selection
Gate 4 Output
Gates
LCPOL Interrupt
See Figure 21-2
det
Set
See Figure 21-3 INTP CLCxIF
INTN
Interrupt
det

FIGURE 21-2: CLCx LOGIC FUNCTION COMBINATORIAL OPTIONS
AND – OR OR – XOR
Gate 1 Gate 1
Gate 2 Gate 2
Logic Output Logic Output
Gate 3 Gate 3
Gate 4 Gate 4
MODE<2:0> = 000 MODE<2:0> = 001
4-Input AND S-R Latch
Gate 1 Gate 1
S Q Logic Output
Gate 2 Gate 2
Logic Output
Gate 3 Gate 3
R
Gate 4 Gate 4
MODE<2:0> = 010 MODE<2:0> = 011
1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R
Gate 4
Gate 4
S D Q Logic Output
Gate 2 D Q Logic Output Gate 2
Gate 1
Gate 1 R
R
Gate 3
Gate 3
MODE<2:0> = 100 MODE<2:0> = 101
J-K Flip-Flop with R 1-Input Transparent Latch with S and R
Gate 4
Gate 2 J Q Logic Output
S
Gate 1 Gate 2 D Q Logic Output
Gate 4 K
R Gate 1 LE
Gate 3 R
Gate 3
MODE<2:0> = 110 MODE<2:0> = 111

FIGURE 21-3: CLCx INPUT SOURCE SELECTION DIAGRAM
Data Selection
Input 0 000
Input 1 Data Gate 1
Input 2
Input 3 Data 1 Non-Inverted G1D1T
Input 4
Data 1
Input 5 Inverted G1D1N
Input 6
Input 7 111
G1D2T
DS1x (CLCxSEL<2:0>)
G1D2N Gate 1
Input 8 000
Input 9 G1D3T
Input 10 G1POL
Input 11 Data 2 Non-Inverted (CLCxCONH<0>)
G1D3N
Input 12 Data 2
Input 13 Inverted
Input 14 G1D4T
Input 15 111
DS2x (CLCxSEL<6:4>) G1D4N
Input 16 000
Input 17 Data Gate 2
Input 18 Gate 2
Input 19 Data 3 Non-Inverted
(Same as Data Gate 1)
Input 20 Data 3
Input 21 Inverted
Input 22 Data Gate 3
Input 23 111
Gate 3
DS3x (CLCxSEL<10:8>)
(Same as Data Gate 1)
Input 24 000 Data Gate 4

Input 25 Gate 4
Input 26
Input 27 Data 4 Non-Inverted (Same as Data Gate 1)
Input 28 Data 4
Input 29 Inverted
Input 30
Input 31 111
DS4x (CLCxSEL<14:12>)
Note: All controls are undefined at power-up.

21.1 Control Registers The CLCx Input MUX Select register (CLCxSEL)
allows the user to select up to four data input sources
The CLCx module is controlled by the following registers: using the four data input selection multiplexers. Each
• CLCxCONL multiplexer has a list of eight data sources available.
• CLCxCONH The CLCx Gate Logic Input Select registers
• CLCxSEL (CLCxGLSL and CLCxGLSH) allow the user to select
• CLCxGLSL which outputs from each of the selection MUXes are
used as inputs to the input gates of the logic cell. Each
• CLCxGLSH
data source MUX outputs both a true and a negated
The CLCx Control registers (CLCxCONL and version of its output. All of these eight signals are
CLCxCONH) are used to enable the module and inter- enabled, ORed together by the logic cell input gates.
rupts, control the output enable bit, select output polarity
and select the logic function. The CLCx Control registers
also allow the user to control the logic polarity of not only
the cell output, but also some intermediate variables.
REGISTER 21-1: CLCxCONL: CLCx CONTROL REGISTER (LOW)

R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0
LCEN — — — INTP INTN — —
bit 15 bit 8
R-0 R-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0

LCOE LCOUT LCPOL — — MODE2 MODE1 MODE0
bit 7 bit 0
Legend:
bit 15 LCEN: CLCx Enable bit

1 = CLCx is enabled and mixing input signals
0 = CLCx is disabled and has logic zero outputs
bit 11 INTP: CLCx Positive Edge Interrupt Enable bit
1 = Interrupt will be generated when a rising edge occurs on LCOUT
0 = Interrupt will not be generated
bit 10 INTN: CLCx Negative Edge Interrupt Enable bit
1 = Interrupt will be generated when a falling edge occurs on LCOUT
0 = Interrupt will not be generated
bit 7 LCOE: CLCx Port Enable bit
1 = CLCx port pin output is enabled
0 = CLCx port pin output is disabled
bit 6 LCOUT: CLCx Data Output Status bit
1 = CLCx output high
0 = CLCx output low
bit 5 LCPOL: CLCx Output Polarity Control bit
1 = The output of the module is inverted
0 = The output of the module is not inverted

REGISTER 21-1: CLCxCONL: CLCx CONTROL REGISTER (LOW) (CONTINUED)
bit 2-0 MODE<2:0>: CLCx Mode bits
111 = Single Input Transparent Latch with S and R
110 = JK Flip-Flop with R
101 = Two-Input D Flip-Flop with R
100 = Single Input D Flip-Flop with S and R
011 = SR Latch
010 = Four-Input AND
001 = Four-Input OR-XOR
000 = Four-Input AND-OR
REGISTER 21-2: CLCxCONH: CLCx CONTROL REGISTER (HIGH)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — G4POL G3POL G2POL G1POL
bit 7 bit 0
Legend:

bit 3 G4POL: Gate 4 Polarity Control bit
1 = Channel 4 logic output is inverted when applied to the logic cell
0 = Channel 4 logic output is not inverted

REGISTER 21-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
— DS4<2:0> — DS3<2:0>
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

— DS2<2:0> — DS1<2:0>
bit 7 bit 0
Legend:

bit 14-12 DS4<2:0>: Data Selection MUX 4 Signal Selection bits
See Table 21-1 for input selections.

TABLE 21-1: CLC1 MULTIPLEXER INPUT SOURCES
DSx<2:0> Signal Source
000 CLCINA
001 System Clock
010 Timer1 Match
DS1<2:0>
011 PWM1H
100 PWM5L
101 High-Speed PWM Clock
110 Timer2 Match
111 Timer3 Match
000 CLCINB
001 CLC2 Out
010 CMP1 Out
DS2<2:0>
011 UART1 TX Out

100 ADC End-of-Conversion
101 DMA Channel 0 Interrupt
110 PWM1L
111 PWM5H
000 CLCINA
001 CLC1 Out
010 CMP2 Out
DS3<2:0>
011 SPI1 SDO Out

100 UART1 RX
101 PWM2H
110 PWM6L
111 OCMP2 Sync Output
000 CLCINB
001 CLC2 Out
010 CMP3 Out
DS4<2:0>
011 SDI1
100 PTGO26
101 ECAN1
110 PWM2L
111 PWM6H

000 CLCINA
001 System Clock
010 Timer1 Match
DS1<2:0>
011 PWM3H
100 PWM7L
110 Timer2 Match
111 Timer3 Match
000 CLCINB
001 CLC1 Out
010 CMP1 Out
DS2<2:0>
011 UART2 TX Out

110 PWM3L
111 PWM7H
000 CLCINA
001 CLC2 Out
010 CMP2 Out
DS3<2:0>
011 SPI2 SDO Out

100 UART2 RX
101 PWM4H
110 PWM8L
000 CLCINB
001 CLC1 Out
010 CMP3 Out
DS4<2:0>
011 SDI2
100 PTGO27
101 ECAN1
110 PWM4L
111 PWM8H

000 CLCINA
001 System Clock
010 Timer1 Match
DS1<2:0>
011 PWM5H
100 REFO1 Clock Output
110 Timer2 Match
111 PWM3L
000 CLCINB
001 CLC4 Out
010 CMP1 Out
DS2<2:0>
011 PWM5L
101 PWM3H
110 ICAP1 Sync Output
000 CLCINA
001 CLC3 Out
010 CMP2 Out
DS3<2:0>
011 PWM6H
100 UART1 RX
111 PWM4L
000 CLCINB
001 CLC4 Out
010 CMP3 Out
DS4<2:0>
011 PWM6L
100 PTGO28
101 PWM4H
110 PC_PWM

000 CLCINA
001 PWM7H
010 Timer1 Match
DS1<2:0>
011 INTOSC/LPRC Clock

100 REFO1 Clock Output
110 Timer2 Match
111 PWM1L
000 CLCINB
001 CLC3 Out
010 CMP1 Out
DS2<2:0>
011 PWM7L
101 PWM1H
000 CLCINA
001 CLC4 Out
010 CMP2 Out
DS3<2:0>
011 PWM8H
100 UART2 RX
111 PWM2L
000 CLCINB
001 CLC3 Out
010 CMP3 Out
DS4<2:0>
011 PWM8L
100 PTGO29
101 PWM2H
110 PWM Sync Output

REGISTER 21-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER
G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15 G2D4T: Gate 2 Data Source 4 True Enable bit

1 = Data Source 4 non-inverted signal is enabled for Gate 2
0 = Data Source 4 non-inverted signal is disabled for Gate 2
bit 14 G2D4N: Gate 2 Data Source 4 Negated Enable bit
1 = Data Source 4 inverted signal is enabled for Gate 2
0 = Data Source 4 inverted signal is disabled for Gate 2

REGISTER 21-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER (CONTINUED)

REGISTER 21-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER
bit 15 bit 8

bit 7 bit 0
Legend:


REGISTER 21-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER (CONTINUED)

22.0 HIGH-SPEED, 12-BIT • Simultaneous Sampling of up to Five Analog Inputs
ANALOG-TO-DIGITAL • Channel Scan Capability
CONVERTER (ADC) • Multiple Conversion Trigger Options for each
Core, including:
Note 1: This data sheet summarizes the features of - PWM1 through PWM6 (primary and
the dsPIC33EPXXXGS70X/80X family of secondary triggers, and current-limit event
devices. It is not intended to be a compre- trigger)
hensive reference source. To complement - PWM Special Event Trigger
the information in this data sheet, refer to - Timer1/Timer2 period match
“12-Bit High-Speed, Multiple SARs A/D
- Output Compare 1 and event trigger
Converter (ADC)” (DS70005213) in the
“dsPIC33/PIC24 Family Reference Man- - External pin trigger event (ADTRG31)
ual”, which is available from the Microchip - Software trigger
website (www.microchip.com). • Two Integrated Digital Comparators with
2: Some registers and associated bits Dedicated Interrupts:
described in this section may not be - Multiple comparison options
available on all devices. Refer to - Assignable to specific analog inputs
Section 4.0 “Memory Organization” in • Two Oversampling Filters with Dedicated
this data sheet for device-specific register Interrupts:
- Provide increased resolution
dsPIC33EPXXXGS70X/80X devices have a high-speed, - Assignable to a specific analog input
12-bit Analog-to-Digital Converter (ADC) that features The module consists of five independent SAR ADC
a low conversion latency, high resolution and over- cores. Simplified block diagrams of the multiple SARs
sampling capabilities to improve performance in 12-bit ADC are shown in Figure 22-1, Figure 22-2 and
AC/DC, DC/DC power converters. Figure 22-3.
The analog inputs (channels) are connected through
22.1 Features Overview multiplexers and switches to the Sample-and-Hold
The high-speed, 12-bit multiple SARs Analog-to-Digital (S&H) circuit of each ADC core. The core uses the
Converter (ADC) includes the following features: channel information (the output format, the Measure-
ment mode and the input number) to process the analog
• Five ADC Cores: Four Dedicated Cores and
sample. When conversion is complete, the result is
One Shared (common) Core
stored in the result buffer for the specific analog input,
• User-Configurable Resolution of up to 12 Bits for and passed to the digital filter and digital comparator if
each Core they were configured to use data from this particular
• Up to 3.25 Msps Conversion Rate per Channel at channel.
12-Bit Resolution
The ADC module can sample up to five inputs at a time
• Low Latency Conversion (four inputs from the dedicated SAR cores and one
• Up to 22 Analog Input Channels, with a Separate from the shared SAR core). If multiple ADC inputs
16-Bit Conversion Result Register for each Input request conversion on the shared core, the module will
• Conversion Result can be Formatted as Unsigned convert them in a sequential manner, starting with the
or Signed Data, on a per Channel Basis, for All lowest order input.
Channels The ADC provides each analog input the ability to
• Single-Ended and Pseudodifferential specify its own trigger source. This capability allows the
Conversions are available on All ADC Cores ADC to sample and convert analog inputs that are
associated with PWM generators operating on
independent time bases.

FIGURE 22-1: ADC MODULE BLOCK DIAGRAM
AVDD AVSS
Voltage Reference
(REFSEL<2:0>)
AN0 Reference
AN7 Dedicated Output Data
PGA1(1) ADC Core 0(2) Digital Comparator 0
Clock ADCMP0 Interrupt
AN0ALT
Digital Comparator 1 ADCMP1 Interrupt
AN1 Reference
AN18 Dedicated Output Data
PGA2(1) ADC Core 1(2)
Clock
AN1ALT
Digital Filter 0 ADFL0DAT
ADFLTR0 Interrupt
Reference
AN2 Digital Filter 1 ADFL1DAT
ADFLTR1 Interrupt
Dedicated Output Data
VBG Reference(1) ADC Core 2(2)
Clock
AN11
Reference
ADCBUF0
AN3 Dedicated ADCAN0 Interrupt
Output Data ADCBUF1
ADC Core 3(2) ADCAN1 Interrupt
AN15 Clock
ADCBUF21
ADCAN21 Interrupt
Reference
AN4
Shared Output Data
ADC Core
Clock
AN21
Divider
(CLKDIV<5:0>)
Clock Selection
(CLKSEL<1:0>)
Instruction FRC AUX

Clock Clock
Note 1: PGA1, PGA2 and the Band Gap Reference (VBG) are internal analog inputs and are not available on device pins.
2: If the dedicated core uses an alternate channel, then shared core function cannot be used.

FIGURE 22-2: DEDICATED ADC CORES 0 TO 3 BLOCK DIAGRAM
Positive Input Positive Input

Selection +
PGAx
Alternate (CxCHS<1:0>) Reference
Positive Input Sample- 12-Bit SAR
and-Hold ADC
Output Data
Negative Input Negative Input
–
Selection
(1)
(DIFFx)
ADC Core Clock

Clock Divider
Trigger Stops
Sampling (ADCS<6:0> bits)
AVSS
Note 1: The DIFFx bit for the corresponding positive input channel must be set in order to use the negative differential input.
FIGURE 22-3: SHARED ADC CORE BLOCK DIAGRAM
AN4
+
Reference
12-Bit
AN21 SAR
Shared ADC Output Data
Sample-
Analog Channel Number and-Hold
from Current Trigger
ADC Core Clock
AN9(1) Negative Input – Clock Divider
Selection
(SHRADC<6:0> bits)
(DIFFx)(1)
SHRSAMC<9:0>
Sampling Time
AVSS
Note 1: Differential-mode conversion is not available for the shared ADC core in dsPIC33EPXXGS70X/80X
devices. For all other devices, the DIFFx bit for the corresponding positive input channel must be set to use
AN9 as the negative differential input.

22.2 Analog-to-Digital Converter 22.2.1 KEY RESOURCES
Resources • “12-Bit High-Speed, Multiple SARs A/D
Converter (ADC)” (DS70005213) in the
Many useful resources are provided on the main
“dsPIC33/PIC24 Family Reference Manual”
product page of the Microchip website for the devices
listed in this data sheet. This product page contains the • Code Samples
latest updates and additional information. • Application Notes
• Webinars
Manual” Sections
REGISTER 22-1: ADCON1L: ADC CONTROL REGISTER 1 LOW

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
ADON(1) — ADSIDL — — — — —
bit 15 bit 8
R/W-0 r-0 r-0 r-0 r-0 U-0 U-0 U-0

(2)
NRE — — — — — — —
bit 7 bit 0
Legend: r = Reserved bit

bit 15 ADON: ADC Enable bit(1)

1 = ADC module is enabled
0 = ADC module is off
bit 13 ADSIDL: ADC Stop in Idle Mode bit
bit 7 NRE: Noise Reduction Enable bit(2)
1 = Holds conversion process for one TADCORE when another core completes conversion to reduce
noise between cores
0 = Noise reduction feature is disabled
bit 6-3 Reserved: Maintain as ‘0’
Note 1: Set the ADON bit only after the ADC module has been configured. Changing ADC Configuration bits when
ADON = 1 will result in unpredictable behavior.
2: If the NRE bit in the ADCON1L register is set, the end of conversion time is adjusted to reduce the noise
between ADC cores. Depending on the number of cores converting and the priority of the input, a few
additional TADs may be inserted, making the conversion time slightly less deterministic.

REGISTER 22-2: ADCON1H: ADC CONTROL REGISTER 1 HIGH
r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-1 R/W-1 r-0 r-0 r-0 r-0 r-0

FORM SHRRES1 SHRRES0 — — — — —
bit 7 bit 0


bit 7 FORM: Fractional Data Output Format bit
1 = Fractional
0 = Integer
bit 6-5 SHRRES<1:0>: Shared ADC Core Resolution Selection bits
11 = 12-bit resolution

R/W-0 R/W-0 r-0 R/W-0 r-0 R/W-0 R/W-0 R/W-0
REFCIE REFERCIE — EIEN — SHREISEL2(1) SHREISEL1(1) SHREISEL0(1)
bit 15 bit 8

— SHRADCS<6:0>
bit 7 bit 0

bit 15 REFCIE: Band Gap and Reference Voltage Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when the band gap will become ready
0 = Common interrupt is disabled for the band gap ready event
bit 14 REFERCIE: Band Gap or Reference Voltage Error Common Interrupt Enable bit
1 = Common interrupt will be generated when a band gap or reference voltage error is detected
0 = Common interrupt is disabled for the band gap and reference voltage error event
bit 13 Reserved: Maintain as ‘0’
bit 12 EIEN: Early Interrupts Enable bit
1 = The early interrupt feature is enabled for the input channel interrupts (when the EISTATx flag is set)
0 = The individual interrupts are generated when conversion is done (when the ANxRDY flag is set)
bit 10-8 SHREISEL<2:0>: Shared Core Early Interrupt Time Selection bits(1)
111 = Early interrupt is set and interrupt is generated eight TADCORE clocks prior to when the data is ready
110 = Early interrupt is set and interrupt is generated seven TADCORE clocks prior to when the data is ready
101 = Early interrupt is set and interrupt is generated six TADCORE clocks prior to when the data is ready
100 = Early interrupt is set and interrupt is generated five TADCORE clocks prior to when the data is ready
011 = Early interrupt is set and interrupt is generated four TADCORE clocks prior to when the data is ready
010 = Early interrupt is set and interrupt is generated three TADCORE clocks prior to when the data is ready
001 = Early interrupt is set and interrupt is generated two TADCORE clocks prior to when the data is ready
000 = Early interrupt is set and interrupt is generated one TADCORE clock prior to when the data is ready
bit 6-0 SHRADCS<6:0>: Shared ADC Core Input Clock Divider bits
These bits determine the number of TCORESRC (Source Clock Periods) for one shared TADCORE (Core
Clock Period).
1111111 = 254 Source Clock Periods
•
•
•
Note 1: For the 6-bit shared ADC core resolution (SHRRES<1:0> = 00), the SHREISEL<2:0> settings,
from ‘100’ to ‘111’, are not valid and should not be used. For the 8-bit shared ADC core resolution
(SHRRES<1:0> = 01), the SHREISEL<2:0> settings, ‘110’ and ‘111’, are not valid and should not be used.

HSC/R-0 HSC/R-0 r-0 r-0 r-0 r-0 R/W-0 R/W-0
REFRDY REFERR — — — — SHRSAMC<9:8>
bit 15 bit 8

SHRSAMC<7:0>
bit 7 bit 0
Legend: r = Reserved bit U = Unimplemented bit, read as ‘0’

bit 15 REFRDY: Band Gap and Reference Voltage Ready Flag bit
1 = Band gap is ready
0 = Band gap is not ready
bit 14 REFERR: Band Gap or Reference Voltage Error Flag bit
1 = Band gap was removed after the ADC module was enabled (ADON = 1)
0 = No band gap error was detected
bit 9-0 SHRSAMC<9:0>: Shared ADC Core Sample Time Selection bits
These bits specify the number of shared ADC Core Clock Periods (TADCORE) for the shared ADC core
sample time.
1111111111 = 1025 TADCORE
•
•
•
0000000001 = 3 TADCORE
0000000000 = 2 TADCORE

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HSC/R-0 R/W-0 HSC/R-0
REFSEL2 REFSEL1 REFSEL0 SUSPEND SUSPCIE SUSPRDY SHRSAMP CNVRTCH
bit 15 bit 8
R/W-0 HSC/R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SWLCTRG SWCTRG CNVCHSEL5 CNVCHSEL4 CNVCHSEL3 CNVCHSEL2 CNVCHSEL1 CNVCHSEL0
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’

bit 15-13 REFSEL<2:0>: ADC Reference Voltage Selection bits
Value VREFH VREFL

000 AVDD AVSS
001-111 = Unimplemented: Do not use
bit 12 SUSPEND: All ADC Cores Triggers Disable bit
1 = All new trigger events for all ADC cores are disabled
0 = All ADC cores can be triggered
bit 11 SUSPCIE: Suspend All ADC Cores Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC core triggers are suspended (SUSPEND bit = 1)
and all previous conversions are finished (SUSPRDY bit becomes set)
0 = Common interrupt is not generated for suspend ADC cores event
bit 10 SUSPRDY: All ADC Cores Suspended Flag bit
1 = All ADC cores are suspended (SUSPEND bit = 1) and have no conversions in progress
0 = ADC cores have previous conversions in progress
bit 9 SHRSAMP: Shared ADC Core Sampling Direct Control bit
This bit should be used with the individual channel conversion trigger controlled by the CNVRTCH bit.
It connects an analog input, specified by the CNVCHSEL<5:0> bits, to the shared ADC core and allows
extending the sampling time. This bit is not controlled by hardware and must be cleared before the
conversion starts (setting CNVRTCH to ‘1’).
1 = Shared ADC core samples an analog input specified by the CNVCHSEL<5:0> bits
0 = Sampling is controlled by the shared ADC core hardware
bit 8 CNVRTCH: Software Individual Channel Conversion Trigger bit
1 = Single trigger is generated for an analog input specified by the CNVCHSEL<5:0> bits; when the bit
is set, it is automatically cleared by hardware on the next instruction cycle
0 = Next individual channel conversion trigger can be generated
bit 7 SWLCTRG: Software Level-Sensitive Common Trigger bit
1 = Triggers are continuously generated for all channels with the software, level-sensitive common
trigger selected as a source in the ADTRIGxL and ADTRIGxH registers
0 = No software, level-sensitive common triggers are generated
bit 6 SWCTRG: Software Common Trigger bit
1 = Single trigger is generated for all channels with the software, common trigger selected as a source
in the ADTRIGxL and ADTRIGxH registers; when the bit is set, it is automatically cleared by
hardware on the next instruction cycle
0 = Ready to generate the next software common trigger
bit 5-0 CNVCHSEL <5:0>: Channel Number Selection for Software Individual Channel Conversion Trigger bits
These bits define a channel to be converted when the CNVRTCH bit is set.

CLKSEL1 CLKSEL0 CLKDIV5 CLKDIV4 CLKDIV3 CLKDIV2 CLKDIV1 CLKDIV0
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

SHREN — — — C3EN C2EN C1EN C0EN
bit 7 bit 0
Legend:
bit 15-14 CLKSEL<1:0>: ADC Module Clock Source Selection bits

11 = APLL
10 = FRC
01 = FOSC (System Clock x 2)
00 = FSYS (System Clock)
bit 13-8 CLKDIV<5:0>: ADC Module Clock Source Divider bits
The divider forms a TCORESRC clock used by all ADC cores (shared and dedicated) from the TSRC ADC
module clock source selected by the CLKSEL<1:0> bits. Then, each ADC core individually divides the
TCORESRC clock to get a core-specific TADCORE clock using the ADCS<6:0> bits in the ADCORExH
register or the SHRADCS<6:0> bits in the ADCON2L register.
•
•
•
000000 = 1 Source Clock Period
bit 7 SHREN: Shared ADC Core Enable bit
1 = Shared ADC core is enabled
0 = Shared ADC core is disabled
bit 3 C3EN: Dedicated ADC Core 3 Enable bits
1 = Dedicated ADC Core 3 is enabled
0 = Dedicated ADC Core 3 is disabled

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — SAMC3EN SAMC2EN SAMC1EN SAMC0EN
bit 7 bit 0
Legend:

bit 3 SAMC3EN: Dedicated ADC Core 3 Conversion Delay Enable bit
1 = After trigger, the conversion will be delayed and the ADC core will continue sampling during the
time specified by the SAMC<9:0> bits in the ADCORE3L register
0 = After trigger, the sampling will be stopped immediately and the conversion will be started on the
next core clock cycle

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

C3CHS1 C3CHS0 C2CHS1 C2CHS0 C1CHS1 C1CHS0 C0CHS1 C0CHS0
bit 7 bit 0
Legend:

bit 7-6 C3CHS<1:0>: Dedicated ADC Core 3 Input Channel Selection bits
1x = Reserved
01 = AN15 (differential negative input when DIFF3 (ADMOD0L<7>) = 1)
00 = AN3
11 = Reserved
10 = VREF band gap
00 = AN2
11 = AN1ALT
10 = PGA2
00 = AN1
11 = AN0ALT
10 = PGA1
00 = AN0

HSC/R-0 U-0 U-0 U-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0
SHRRDY — — — C3RDY C2RDY C1RDY C0RDY
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

SHRPWR — — — C3PWR C2PWR C1PWR C0PWR
bit 7 bit 0

bit 15 SHRRDY: Shared ADC Core Ready Flag bit

1 = ADC core is powered and ready for operation
0 = ADC core is not ready for operation
bit 11 C3RDY: Dedicated ADC Core 3 Ready Flag bit
bit 7 SHRPWR: Shared ADC Core x Power Enable bit
1 = ADC Core x is powered
0 = ADC Core x is off
bit 3 C3PWR: Dedicated ADC Core 3 Power Enable bit
1 = ADC core is powered
0 = ADC core is off
0 = ADC core is off
0 = ADC core is off
0 = ADC core is off

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — WARMTIME<3:0>
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

SHRCIE — — — C3CIE C2CIE C1CIE C0CIE
bit 7 bit 0
Legend:

bit 11-8 WARMTIME<3:0>: ADC Dedicated Core x Power-up Delay bits
These bits determine the power-up delay in the number of the Core Source Clock Periods (TCORESRC)
for all ADC cores.
00xx = 16 Source Clock Periods
bit 7 SHRCIE: Shared ADC Core Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC core is powered and ready for operation
0 = Common interrupt is disabled for an ADC core ready event
bit 3 C3CIE: Dedicated ADC Core 3 Ready Common Interrupt Enable bit
1 = Common interrupt will be generated when ADC Core 3 is powered and ready for operation
0 = Common interrupt is disabled for an ADC Core 3 ready event

REGISTER 22-11: ADCORExL: DEDICATED ADC CORE x CONTROL REGISTER LOW (x = 0 to 3)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SAMC<9:8>
bit 15 bit 8

SAMC<7:0>
bit 7 bit 0
Legend:

bit 9-0 SAMC<9:0>: Dedicated ADC Core x Conversion Delay Selection bits
These bits determine the time between the trigger event and the start of conversion in the number of
the Core Clock Periods (TADCORE). During this time, the ADC Core x still continues sampling. This
feature is enabled by the SAMCxEN bits in the ADCON4L register.
1111111111 = 1025 TADCORE
•
•
•
0000000001 = 3 TADCORE
0000000000 = 2 TADCORE

REGISTER 22-12: ADCORExH: DEDICATED ADC CORE x CONTROL REGISTER HIGH (x = 0 to 3)(1)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
— — — EISEL2 EISEL1 EISEL0 RES1 RES0
bit 15 bit 8

— ADCS<6:0>
bit 7 bit 0
Legend:

bit 12-10 EISEL<2:0>: ADC Core x Early Interrupt Time Selection bits
111 = Early interrupt is set and an interrupt is generated eight TADCORE clocks prior to when the data is ready
110 = Early interrupt is set and an interrupt is generated seven TADCORE clocks prior to when the data is ready
101 = Early interrupt is set and an interrupt is generated six TADCORE clocks prior to when the data is ready
100 = Early interrupt is set and an interrupt is generated five TADCORE clocks prior to when the data is ready
011 = Early interrupt is set and an interrupt is generated four TADCORE clocks prior to when the data is ready
010 = Early interrupt is set and an interrupt is generated three TADCORE clocks prior to when the data is ready
001 = Early interrupt is set and an interrupt is generated two TADCORE clocks prior to when the data is ready
000 = Early interrupt is set and an interrupt is generated one TADCORE clock prior to when the data is ready
bit 9-8 RES<1:0>: ADC Core x Resolution Selection bits
bit 6-0 ADCS<6:0>: ADC Core x Input Clock Divider bits
These bits determine the number of Source Clock Periods (TCORESRC) for one Core Clock Period
(TADCORE).
•
•
•
Note 1: For the 6-bit ADC core resolution (RES<1:0> = 00), the EISEL<2:0> bits settings, from ‘100’ to ‘111’, are
not valid and should not be used. For the 8-bit ADC core resolution (RES<1:0> = 01), the EISEL<2:0> bits
settings, ‘110’ and ‘111’, are not valid and should not be used.

REGISTER 22-13: ADLVLTRGL: ADC LEVEL-SENSITIVE TRIGGER CONTROL REGISTER LOW
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
LVLEN<15:8>
bit 15 bit 8

LVLEN<7:0>
bit 7 bit 0
Legend:
bit 15-0 LVLEN<15:0>: Level Trigger for Corresponding Analog Input Enable bits
1 = Input trigger is level-sensitive
0 = Input trigger is edge-sensitive
REGISTER 22-14: ADLVLTRGH: ADC LEVEL-SENSITIVE TRIGGER CONTROL REGISTER HIGH

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — LVLEN<21:16>
bit 7 bit 0
Legend:

bit 5-0 LVLEN<21:16>: Level Trigger for Corresponding Analog Input Enable bits
1 = Input trigger is level-sensitive
0 = Input trigger is edge-sensitive

REGISTER 22-15: ADEIEL: ADC EARLY INTERRUPT ENABLE REGISTER LOW
EIEN<15:8>
bit 15 bit 8

EIEN<7:0>
bit 7 bit 0
Legend:
bit 15-0 EIEN<15:0>: Early Interrupt Enable for Corresponding Analog Inputs bits
1 = Early interrupt is enabled for the channel
0 = Early interrupt is disabled for the channel
REGISTER 22-16: ADEIEH: ADC EARLY INTERRUPT ENABLE REGISTER HIGH

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — EIEN<21:16>
bit 7 bit 0
Legend:

bit 5-0 EIEN<21:16>: Early Interrupt Enable for Corresponding Analog Inputs bits
1 = Early interrupt is enabled for the channel
0 = Early interrupt is disabled for the channel

REGISTER 22-17: ADEISTATL: ADC EARLY INTERRUPT STATUS REGISTER LOW
EISTAT<15:8>
bit 15 bit 8

EISTAT<7:0>
bit 7 bit 0
Legend:
bit 15-0 EISTAT<15:0>: Early Interrupt Status for Corresponding Analog Inputs bits
1 = Early interrupt was generated
0 = Early interrupt was not generated since the last ADCBUFx read
REGISTER 22-18: ADEISTATH: ADC EARLY INTERRUPT STATUS REGISTER HIGH

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — EISTAT<21:16>
bit 7 bit 0
Legend:

bit 5-0 EISTAT<21:16>: Early Interrupt Status for Corresponding Analog Inputs bits
1 = Early interrupt was generated
0 = Early interrupt was not generated since the last ADCBUFx read

REGISTER 22-19: ADMOD0L: ADC INPUT MODE CONTROL REGISTER 0 LOW
DIFF7 SIGN7 DIFF6 SIGN6 DIFF5 SIGN5 DIFF4 SIGN4
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-1(odd) DIFF<7:0>: Differential-Mode for Corresponding Analog Inputs bits

1 = Channel is differential
0 = Channel is single-ended
bit 14-0 (even) SIGN<7:0>: Output Data Sign for Corresponding Analog Inputs bits
1 = Channel output data is signed
0 = Channel output data is unsigned
REGISTER 22-20: ADMOD0H: ADC INPUT MODE CONTROL REGISTER 0 HIGH

bit 15 bit 8

bit 7 bit 0
Legend:


REGISTER 22-21: ADMOD1L: ADC INPUT MODE CONTROL REGISTER 1 LOW
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — DIFF21 SIGN21 DIFF20 SIGN20
bit 15 bit 8

bit 7 bit 0
Legend:


REGISTER 22-22: ADIEL: ADC INTERRUPT ENABLE REGISTER LOW
IE<15:8>
bit 15 bit 8

IE<7:0>
bit 7 bit 0
Legend:
bit 15-0 IE<15:0>: Common Interrupt Enable bits

1 = Common and individual interrupts are enabled for the corresponding channel
0 = Common and individual interrupts are disabled for the corresponding channel
REGISTER 22-23: ADIEH: ADC INTERRUPT ENABLE REGISTER HIGH

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — IE<21:16>
bit 7 bit 0
Legend:

bit 5-0 IE<21:16>: Common Interrupt Enable bits
1 = Common and individual interrupts are enabled for the corresponding channel
0 = Common and individual interrupts are disabled for the corresponding channel

REGISTER 22-24: ADSTATL: ADC DATA READY STATUS REGISTER LOW
HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0
AN<15:8>RDY
bit 15 bit 8
HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0

AN<7:0>RDY
bit 7 bit 0

bit 15-0 AN<15:0>RDY: Common Interrupt Enable for Corresponding Analog Inputs bits
1 = Channel conversion result is ready in the corresponding ADCBUFx register
0 = Channel conversion result is not ready
REGISTER 22-25: ADSTATH: ADC DATA READY STATUS REGISTER HIGH

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

— — AN<21:16>RDY
bit 7 bit 0


bit 5-0 AN<21:16>RDY: Common Interrupt Enable for Corresponding Analog Inputs bits
1 = Channel conversion result is ready in the corresponding ADCBUFx register
0 = Channel conversion result is not ready

REGISTER 22-26: ADTRIGxL: ADC CHANNEL TRIGGER x SELECTION REGISTER LOW
(x = 0 to 5)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC(4x+1)<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TRGSRC(4x)<4:0>
bit 7 bit 0
Legend:

bit 12-8 TRGSRC(4x+1)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits
11111 = ADTRG31
11101 = PWM Generator 6 current-limit trigger
10111 = Output Compare 2 trigger
10101 = CLC2 output
10100 = PWM Generator 6 secondary trigger
01110 = PWM secondary Special Event Trigger
01101 = Timer2 period match
01011 = CLC1 output
01010 = PWM Generator 6 primary trigger
00100 = PWM Special Event Trigger
00011 = Reserved
00010 = Level software trigger
00001 = Common software trigger
00000 = No trigger is enabled

REGISTER 22-26: ADTRIGxL: ADC CHANNEL TRIGGER x SELECTION REGISTER LOW
bit 4-0 TRGSRC(4x)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits
11111 = ADTRG31
10101 = CLC2 output
01011 = CLC1 output
00011 = Reserved

REGISTER 22-27: ADTRIGxH: ADC CHANNEL TRIGGER x SELECTION REGISTER HIGH
(x = 0 to 5)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TRGSRC(4x+3)<4:0>
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TRGSRC(4x+2)<4:0>
bit 7 bit 0
Legend:

11111 = ADTRG31
10101 = CLC2 output
01011 = CLC1 output
00011 = Reserved

REGISTER 22-27: ADTRIGxH: ADC CHANNEL TRIGGER x SELECTION REGISTER HIGH
11111 = ADTRG31
10101 = CLC2 output
01011 = CLC1 output
00011 = Reserved

REGISTER 22-28: ADCAL0L: ADC CALIBRATION REGISTER 0 LOW
HSC/R-0 U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0
CAL1RDY — — — — CAL1DIFF CAL1EN CAL1RUN
bit 15 bit 8
HSC/R-0 U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0

bit 15 CAL1RDY: Dedicated ADC Core 1 Calibration Status Flag bit

1 = Dedicated ADC Core 1 calibration is finished
0 = Dedicated ADC Core 1 calibration is in progress
bit 10 CAL1DIFF: Dedicated ADC Core 1 Differential-Mode Calibration bit
1 = Dedicated ADC Core 1 will be calibrated in Differential Input mode
0 = Dedicated ADC Core 1 will be calibrated in Single-Ended Input mode
bit 9 CAL1EN: Dedicated ADC Core 1 Calibration Enable bit
1 = Dedicated ADC Core 1 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by
software
0 = Dedicated ADC Core 1 calibration bits are disabled
bit 8 CAL1RUN: Dedicated ADC Core 1 Calibration Start bit
1 = If this bit is set by software, the dedicated ADC Core 1 calibration cycle is started; this bit is
automatically cleared by hardware
0 = Software can start the next calibration cycle
software

REGISTER 22-29: ADCAL0H: ADC CALIBRATION REGISTER 0 HIGH
HSC/R-0 U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0
bit 15 bit 8
HSC/R-0 U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0

bit 7 bit 0


software
software

REGISTER 22-30: ADCAL1H: ADC CALIBRATION REGISTER 1 HIGH
HS/R/W-0 U-0 U-0 U-0 r-0 R/W-0 R/W-0 R/W-0
CSHRRDY — — — — CSHRDIFF CSHREN CSHRRUN
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0

R = Readable bit W = Writable bit HS = Hardware Settable bit
bit 15 CSHRRDY: Shared ADC Core Calibration Status Flag bit

1 = Shared ADC core calibration is finished
0 = Shared ADC core calibration is in progress
bit 10 CSHRDIFF: Shared ADC Core Differential-Mode Calibration bit
1 = Shared ADC core will be calibrated in Differential Input mode
0 = Shared ADC core will be calibrated in Single-Ended Input mode
bit 9 CSHREN: Shared ADC Core Calibration Enable bit
1 = Shared ADC core calibration bits (CSHRRDY, CSHRDIFF and CSHRRUN) can be accessed by
software
0 = Shared ADC core calibration bits are disabled
bit 8 CSHRRUN: Shared ADC Core Calibration Start bit
1 = If this bit is set by software, the shared ADC core calibration cycle is started; this bit is cleared
automatically by hardware

REGISTER 22-31: ADCMPxCON: ADC DIGITAL COMPARATOR x CONTROL REGISTER (x = 0 or 1)
U-0 U-0 U-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0 HSC/R-0
— — — CHNL<4:0>
bit 15 bit 8
R/W-0 R/W-0 HC/HS/R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CMPEN IE STAT BTWN HIHI HILO LOHI LOLO
bit 7 bit 0
Legend: HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware Settable bit

bit 12-8 CHNL<4:0>: Input Channel Number bits
If the comparator has detected an event for a channel, this channel number is written to these bits.
11111 = Reserved
•
•
10110 = Reserved
10101 = AN21
10100 = AN20
•
•
00001 = AN1
00000 = AN0
bit 7 CMPEN: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled and the STAT status bit is cleared
bit 6 IE: Comparator Common ADC Interrupt Enable bit
1 = Common ADC interrupt will be generated if the comparator detects a comparison event
0 = Common ADC interrupt will not be generated for the comparator
bit 5 STAT: Comparator Event Status bit
This bit is cleared by hardware when the channel number is read from the CHNL<4:0> bits.
1 = A comparison event has been detected since the last read of the CHNL<4:0> bits
0 = A comparison event has not been detected since the last read of the CHNL<4:0> bits
bit 4 BTWN: Between Low/High Comparator Event bit
1 = Generates a comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI
0 = Does not generate a digital comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI
bit 3 HIHI: High/High Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx ≥ ADCMPxHI
0 = Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxHI
bit 2 HILO: High/Low Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx < ADCMPxHI
0 = Does not generate a digital comparator event when ADCBUFx < ADCMPxHI
bit 1 LOHI: Low/High Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx ≥ ADCMPxLO
0 = Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxLO
bit 0 LOLO: Low/Low Comparator Event bit
1 = Generates a digital comparator event when ADCBUFx < ADCMPxLO
0 = Does not generate a digital comparator event when ADCBUFx < ADCMPxLO

REGISTER 22-32: ADCMPxENL: ADC DIGITAL COMPARATOR x CHANNEL ENABLE REGISTER
LOW (x = 0 or 1)
CMPEN<15:8>
bit 15 bit 8
R/W/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CMPEN<7:0>
bit 7 bit 0
Legend:
bit 15-0 CMPEN<15:0>: Comparator Enable for Corresponding Input Channels bits
1 = Conversion result for corresponding channel is used by the comparator
0 = Conversion result for corresponding channel is not used by the comparator
REGISTER 22-33: ADCMPxENH: ADC DIGITAL COMPARATOR x CHANNEL ENABLE REGISTER

HIGH (x = 0 or 1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CMPEN<21:16>
bit 7 bit 0
Legend:

bit 5-0 CMPEN<21:16>: Comparator Enable for Corresponding Input Channels bits
1 = Conversion result for corresponding channel is used by the comparator
0 = Conversion result for corresponding channel is not used by the comparator

REGISTER 22-34: ADFLxCON: ADC DIGITAL FILTER x CONTROL REGISTER
(x = 0 or 1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HSC/R-0
FLEN MODE1 MODE0 OVRSAM2 OVRSAM1 OVRSAM0 IE RDY
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — FLCHSEL<4:0>
bit 7 bit 0

bit 15 FLEN: Filter Enable bit

1 = Filter is enabled
0 = Filter is disabled and the RDY bit is cleared
bit 14-13 MODE<1:0>: Filter Mode bits
11 = Averaging mode
10 = Reserved
01 = Reserved
00 = Oversampling mode
bit 12-10 OVRSAM<2:0>: Filter Averaging/Oversampling Ratio bits
If MODE<1:0> = 00:
111 = 128x (16-bit result in the ADFLxDAT register is in 12.4 format)
If MODE<1:0> = 11 (12-bit result in the ADFLxDAT register in all instances):
111 = 256x
110 = 128x
101 = 64x
100 = 32x
011 = 16x
010 = 8x
001 = 4x
000 = 2x
bit 9 IE: Filter Common ADC Interrupt Enable bit
1 = Common ADC interrupt will be generated when the filter result will be ready
0 = Common ADC interrupt will not be generated for the filter
bit 8 RDY: Oversampling Filter Data Ready Flag bit
This bit is cleared by hardware when the result is read from the ADFLxDAT register.
1 = Data in the ADFLxDAT register is ready
0 = The ADFLxDAT register has been read and new data in the ADFLxDAT register is not ready

REGISTER 22-34: ADFLxCON: ADC DIGITAL FILTER x CONTROL REGISTER
(x = 0 or 1) (CONTINUED)
bit 4-0 FLCHSEL<4:0>: Oversampling Filter Input Channel Selection bits
11111 = Reserved
•
•
•
10110 = Reserved
10101 = AN21
10100 = AN20
•
•
•
00001 = AN1
00000 = AN0

NOTES:

23.0 CONTROLLER AREA The CAN module features are as follows:
NETWORK (CAN) MODULE • Implementation of the CAN Protocol, CAN 1.2,
(dsPIC33EPXXXGS80X CAN 2.0A and CAN 2.0B
• Standard and Extended Data Frames
DEVICES ONLY)
• 0-8 Bytes of Data Length
Note 1: This data sheet summarizes the features • Programmable Bit Rate, up to 1 Mbit/sec
of the dsPIC33EPXXXGS70X/80X family • Automatic Response to Remote Transmission
of devices. It is not intended to be a Requests
comprehensive reference source. To com-
• Up to Eight Transmit Buffers with Application
plement the information in this data sheet,
Specified Prioritization and Abort Capability (each
refer to “Enhanced Controller Area
buffer can contain up to 8 bytes of data)
Network (ECAN™)” (DS70353) in the
“dsPIC33/PIC24 Family Reference Man- • Up to 32 Receive Buffers (each buffer can contain
ual”, which is available from the Microchip up to 8 bytes of data)
website (www.microchip.com). • Up to 16 Full (Standard/Extended Identifier)
Acceptance Filters
described in this section may not be • Three Full Acceptance Filter Masks
available on all devices. Refer to • DeviceNet™ Addressing Support
Section 4.0 “Memory Organization” in • Programmable Wake-up Functionality with
this data sheet for device-specific register Integrated Low-Pass Filter
and bit information. • Programmable Loopback mode supports
Self-Test Operation
23.1 Overview • Signaling via Interrupt Capabilities for All CAN
Receiver and Transmitter Error States
The Controller Area Network (CAN) module is a serial
• Programmable Clock Source
interface, useful for communicating with other CAN
modules or microcontroller devices. This interface/ • Programmable Link to Input Capture 2 (IC2)
protocol was designed to allow communications within module for Timestamping and Network
noisy environments. The dsPIC33EPXXXGS80X Synchronization
devices contain two CAN modules. • Low-Power Sleep and Idle modes
The CAN module is a communication controller, imple- The CAN bus module consists of a protocol engine and
menting the CAN 2.0 A/B protocol, as defined in the message buffering/control. The CAN protocol engine
BOSCH CAN specification. The module supports handles all functions for receiving and transmitting
CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B messages on the CAN bus. Messages are transmitted
Active versions of the protocol. The module implemen- by first loading the appropriate data registers. Status
tation is a full CAN system. The CAN specification is and errors can be checked by reading the appropriate
not covered within this data sheet. The reader can refer registers. Any message detected on the CAN bus is
to the BOSCH CAN specification for further details. checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.

FIGURE 23-1: CANx MODULE BLOCK DIAGRAM
RxF15 Filter
RxF14 Filter
RxF13 Filter
RxF12 Filter
DMA Controller RxF11 Filter

RxF10 Filter
RxF9 Filter
RxF8 Filter
TRB7 TX/RX Buffer Control Register RxF7 Filter
TRB2 TX/RX Buffer Control Register RxF2 Filter RxM2 Mask

Transmit Byte Message Assembly

Sequencer Buffer
Control
CPU
Configuration Bus
Logic
CAN Protocol
Engine
Interrupts
CxTX CxRX
23.2 Modes of Operation Modes are requested by setting the REQOP<2:0> bits
(CxCTRL1<10:8>). Entry into a mode is Acknowledged
The CANx module can operate in one of several by monitoring the OPMODE<2:0> bits (CxCTRL1<7:5>).
operation modes selected by the user. These modes The module does not change the mode and the
include: OPMODEx bits until a change in mode is acceptable,
• Initialization mode generally during bus Idle time, which is defined as at least
• Disable mode eleven consecutive recessive bits.
• Normal Operation mode
• Listen Only mode
• Listen All Messages mode
• Loopback mode

23.3 CAN Control Registers
REGISTER 23-1: CxCTRL1: CANx CONTROL REGISTER 1

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
— — CSIDL ABAT CANCKS REQOP2 REQOP1 REQOP0
bit 15 bit 8
R-1 R-0 R-0 U-0 R/W-0 U-0 U-0 R/W-0

OPMODE2 OPMODE1 OPMODE0 — CANCAP — — WIN
bit 7 bit 0
Legend:

bit 13 CSIDL: CANx Stop in Idle Mode bit
bit 12 ABAT: Abort All Pending Transmissions bit
1 = Signals all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions are aborted
bit 11 CANCKS: CANx Module Clock (FCAN) Source Select bit
1 = FCAN is equal to 2 * FP
0 = FCAN is equal to FP
bit 10-8 REQOP<2:0>: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Set Configuration mode
011 = Set Listen Only mode
010 = Set Loopback mode
001 = Set Disable mode
000 = Set Normal Operation mode
bit 7-5 OPMODE<2:0>: Operation Mode bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 3 CANCAP: CANx Message Receive Timer Capture Event Enable bit
1 = Enables input capture based on CAN message receive
0 = Disables CAN capture
bit 0 WIN: SFR Map Window Select bit
1 = Uses filter window
0 = Uses buffer window

REGISTER 23-2: CxCTRL2: CANx CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0

— — — DNCNT<4:0>
bit 7 bit 0
Legend:

bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits
10010-11111 = Invalid selection
10001 = Compare up to Data Byte 3, bit 6 with EID<17>
•
•
•
00001 = Compare up to Data Byte 1, bit 7 with EID<0>
00000 = Do not compare data bytes

REGISTER 23-3: CxVEC: CANx INTERRUPT CODE REGISTER
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
— — — FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0
bit 15 bit 8
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0

— ICODE6 ICODE5 ICODE4 ICODE3 ICODE2 ICODE1 ICODE0
bit 7 bit 0
Legend:

bit 12-8 FILHIT<4:0>: Filter Hit Number bits
10000-11111 = Reserved
01111 = Filter 15
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 6-0 ICODE<6:0>: Interrupt Flag Code bits
1000101-1111111 = Reserved
1000100 = FIFO almost full interrupt
1000011 = Receiver overflow interrupt
1000010 = Wake-up interrupt
1000001 = Error interrupt
1000000 = No interrupt
•
•
•
0010000-0111111 = Reserved
0001111 = RB15 buffer interrupt
•
•
•
0000111 = TRB7 buffer interrupt

REGISTER 23-4: CxFCTRL: CANx FIFO CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
DMABS2 DMABS1 DMABS0 — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — FSA4 FSA3 FSA2 FSA1 FSA0
bit 7 bit 0
Legend:
bit 15-13 DMABS<2:0>: DMA Buffer Size bits

111 = Reserved
110 = 32 buffers in RAM
bit 4-0 FSA<4:0>: FIFO Area Starts with Buffer bits
11111 = Receive Buffer RB31
11110 = Receive Buffer RB30
•
•
•
00001 = Transmit/Receive Buffer TRB1
00000 = Transmit/Receive Buffer TRB0

REGISTER 23-5: CxFIFO: CANx FIFO STATUS REGISTER
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
— — FBP5 FBP4 FBP3 FBP2 FBP1 FBP0
bit 15 bit 8
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— — FNRB5 FNRB4 FNRB3 FNRB2 FNRB1 FNRB0
bit 7 bit 0
Legend:

bit 13-8 FBP<5:0>: FIFO Buffer Pointer bits
011111 = RB31 buffer
•
•
•
000001 = TRB1 buffer
bit 5-0 FNRB<5:0>: FIFO Next Read Buffer Pointer bits
•
•
•

REGISTER 23-6: CxINTF: CANx INTERRUPT FLAG REGISTER
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
— — TXBO TXBP RXBP TXWAR RXWAR EWARN
bit 15 bit 8
R/C-0 R/C-0 R/C-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0

IVRIF WAKIF ERRIF — FIFOIF RBOVIF RBIF TBIF
bit 7 bit 0
Legend: C = Writable bit, but only ‘0’ can be Written to Clear bit

bit 13 TXBO: Transmitter in Error State Bus Off bit
1 = Transmitter is in Bus Off state
0 = Transmitter is not in Bus Off state
bit 12 TXBP: Transmitter in Error State Bus Passive bit
1 = Transmitter is in Bus Passive state
0 = Transmitter is not in Bus Passive state
bit 11 RXBP: Receiver in Error State Bus Passive bit
1 = Receiver is in Bus Passive state
0 = Receiver is not in Bus Passive state
bit 10 TXWAR: Transmitter in Error State Warning bit
1 = Transmitter is in Error Warning state
0 = Transmitter is not in Error Warning state
bit 9 RXWAR: Receiver in Error State Warning bit
1 = Receiver is in Error Warning state
0 = Receiver is not in Error Warning state
bit 8 EWARN: Transmitter or Receiver in Error State Warning bit
1 = Transmitter or receiver is in Error Warning state
0 = Transmitter or receiver is not in Error Warning state
bit 7 IVRIF: Invalid Message Interrupt Flag bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6 WAKIF: Bus Wake-up Activity Interrupt Flag bit
bit 5 ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF<13:8> register)
bit 3 FIFOIF: FIFO Almost Full Interrupt Flag bit
bit 2 RBOVIF: RX Buffer Overflow Interrupt Flag bit

REGISTER 23-6: CxINTF: CANx INTERRUPT FLAG REGISTER (CONTINUED)
bit 1 RBIF: RX Buffer Interrupt Flag bit
bit 0 TBIF: TX Buffer Interrupt Flag bit
REGISTER 23-7: CxINTE: CANx INTERRUPT ENABLE REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

IVRIE WAKIE ERRIE — FIFOIE RBOVIE RBIE TBIE
bit 7 bit 0
Legend:

bit 7 IVRIE: Invalid Message Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6 WAKIE: Bus Wake-up Activity Interrupt Enable bit
bit 5 ERRIE: Error Interrupt Enable bit
bit 3 FIFOIE: FIFO Almost Full Interrupt Enable bit
bit 2 RBOVIE: RX Buffer Overflow Interrupt Enable bit
bit 1 RBIE: RX Buffer Interrupt Enable bit
bit 0 TBIE: TX Buffer Interrupt Enable bit

REGISTER 23-8: CxEC: CANx TRANSMIT/RECEIVE ERROR COUNT REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1 RERRCNT0
bit 7 bit 0
Legend:
bit 15-8 TERRCNT<7:0>: Transmit Error Count bits

bit 7-0 RERRCNT<7:0>: Receive Error Count bits
REGISTER 23-9: CxCFG1: CANx BAUD RATE CONFIGURATION REGISTER 1

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8

SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
bit 7 bit 0
Legend:

bit 7-6 SJW<1:0>: Synchronization Jump Width bits
11 = Length is 4 x TQ
bit 5-0 BRP<5:0>: Baud Rate Prescaler bits
11 1111 = TQ = 2 x 64 x 1/FCAN
•
•
•
00 0010 = TQ = 2 x 3 x 1/FCAN
00 0001 = TQ = 2 x 2 x 1/FCAN
00 0000 = TQ = 2 x 1 x 1/FCAN

REGISTER 23-10: CxCFG2: CANx BAUD RATE CONFIGURATION REGISTER 2
U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x
— WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0
bit 15 bit 8

SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0
bit 7 bit 0
Legend:

bit 14 WAKFIL: Select CAN Bus Line Filter for Wake-up bit
1 = Uses CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 10-8 SEG2PH<2:0>: Phase Segment 2 bits
•
•
•
bit 7 SEG2PHTS: Phase Segment 2 Time Select bit
1 = Freely programmable
0 = Maximum of SEG1PHx bits or Information Processing Time (IPT), whichever is greater
bit 6 SAM: Sample of the CAN Bus Line bit
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 5-3 SEG1PH<2:0>: Phase Segment 1 bits
•
•
•
bit 2-0 PRSEG<2:0>: Propagation Time Segment bits
•
•
•

REGISTER 23-11: CxFEN1: CANx ACCEPTANCE FILTER ENABLE REGISTER 1
FLTEN<15:8>
bit 15 bit 8

FLTEN<7:0>
bit 7 bit 0
Legend:
bit 15-0 FLTEN<15:0>: Enable Filter n to Accept Messages bits

1 = Enables Filter n
0 = Disables Filter n
REGISTER 23-12: CxBUFPNT1: CANx FILTERS 0-3 BUFFER POINTER REGISTER 1

F3BP3 F3BP2 F3BP1 F3BP0 F2BP3 F2BP2 F2BP1 F2BP0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-12 F3BP<3:0>: RX Buffer Mask for Filter 3 bits

1111 = Filter hits received in RX FIFO buffer
1110 = Filter hits received in RX Buffer 14
•
•
•
bit 11-8 F2BP<3:0>: RX Buffer Mask for Filter 2 bits (same values as bits 15-12)

bit 15 bit 8

bit 7 bit 0
Legend:

•
•
•

bit 15 bit 8

bit 7 bit 0
Legend:

•
•
•

bit 15 bit 8

bit 7 bit 0
Legend:

•
•
•

REGISTER 23-16: CxRXFnSID: CANx ACCEPTANCE FILTER n STANDARD IDENTIFIER
REGISTER (n = 0-15)
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 15 bit 8
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 — EXIDE — EID17 EID16
bit 7 bit 0
Legend:
bit 15-5 SID<10:0>: Standard Identifier bits

1 = Message address bit, SIDx, must be ‘1’ to match filter
0 = Message address bit, SIDx, must be ‘0’ to match filter
bit 3 EXIDE: Extended Identifier Enable bit
If MIDE = 1:
1 = Matches only messages with Extended Identifier addresses
0 = Matches only messages with Standard Identifier addresses
If MIDE = 0:
Ignores EXIDE bit.
bit 1-0 EID<17:16>: Extended Identifier bits
1 = Message address bit, EIDx, must be ‘1’ to match filter
REGISTER 23-17: CxRXFnEID: CANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER

REGISTER (n = 0-15)
EID<15:8>
bit 15 bit 8

EID<7:0>
bit 7 bit 0
Legend:


REGISTER 23-18: CxFMSKSEL1: CANx FILTERS 7-0 MASK SELECTION REGISTER 1
F7MSK1 F7MSK0 F6MSK1 F6MSK0 F5MSK1 F5MSK0 F4MSK1 F4MSK0
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-14 F7MSK<1:0>: Mask Source for Filter 7 bits

11 = Reserved
10 = Acceptance Mask 2 registers contain mask
bit 13-12 F6MSK<1:0>: Mask Source for Filter 6 bits (same values as bits 15-14)

REGISTER 23-19: CxFMSKSEL2: CANx FILTERS 15-8 MASK SELECTION REGISTER 2
bit 15 bit 8

bit 7 bit 0
Legend:
bit 15-14 F15MSK<1:0>: Mask Source for Filter 15 bits

11 = Reserved

REGISTER 23-20: CxRXMnSID: CANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER
REGISTER (n = 0-2)
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 15 bit 8
R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x

SID2 SID1 SID0 — MIDE — EID17 EID16
bit 7 bit 0
Legend:

1 = Includes bit, SIDx, in filter comparison
0 = Bit, SIDx, is a don’t care in filter comparison
bit 3 MIDE: Identifier Receive Mode bit
1 = Matches only message types (standard or extended address) that correspond to the EXIDE bit in
the filter
0 = Matches either standard or extended address message if filters match
(i.e., if (Filter SIDx) = (Message SIDx) or if (Filter SIDx/EIDx) = (Message SIDx/EIDx))
1 = Includes bit, EIDx, in filter comparison
0 = Bit, EIDx, is a don’t care in filter comparison
REGISTER 23-21: CxRXMnEID: CANx ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER

REGISTER (n = 0-2)
EID<15:8>
bit 15 bit 8

EID<7:0>
bit 7 bit 0
Legend:

1 = Includes bit, EIDx, in filter comparison
0 = Bit, EIDx, is a don’t care in filter comparison

REGISTER 23-22: CxRXFUL1: CANx RECEIVE BUFFER FULL REGISTER 1
R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
RXFUL<15:8>
bit 15 bit 8

RXFUL<7:0>
bit 7 bit 0
bit 15-0 RXFUL<15:0>: Receive Buffer n Full bits

1 = Buffer is full (set by module)
0 = Buffer is empty (cleared by user software)
REGISTER 23-23: CxRXFUL2: CANx RECEIVE BUFFER FULL REGISTER 2

RXFUL<31:24>
bit 15 bit 8

RXFUL<23:16>
bit 7 bit 0
bit 15-0 RXFUL<31:16>: Receive Buffer n Full bits

1 = Buffer is full (set by module)
0 = Buffer is empty (cleared by user software)

REGISTER 23-24: CxRXOVF1: CANx RECEIVE BUFFER OVERFLOW REGISTER 1
RXOVF<15:8>
bit 15 bit 8

RXOVF<7:0>
bit 7 bit 0
bit 15-0 RXOVF<15:0>: Receive Buffer n Overflow bits

1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition (cleared by user software)
REGISTER 23-25: CxRXOVF2: CANx RECEIVE BUFFER OVERFLOW REGISTER 2

RXOVF<31:24>
bit 15 bit 8

RXOVF<23:16>
bit 7 bit 0
bit 15-0 RXOVF<31:16>: Receive Buffer n Overflow bits

1 = Module attempted to write to a full buffer (set by module)
0 = No overflow condition (cleared by user software)

REGISTER 23-26: CxTRmnCON: CANx TX/RX BUFFER mn CONTROL REGISTER
(m = 0,2,4,6; n = 1,3,5,7)
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI1 TXnPRI0
bit 15 bit 8
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

TXENm TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm RTRENm TXmPRI1 TXmPRI0
bit 7 bit 0
Legend:
bit 15-8 See Definition for bits 7-0, controls Buffer n.

bit 7 TXENm: TX/RX Buffer m Selection bit
1 = Buffer, TRBm, is a transmit buffer
0 = Buffer, TRBm, is a receive buffer
bit 6 TXABTm: Message Aborted bit(1)
1 = Message was aborted
0 = Message completed transmission successfully
bit 5 TXLARBm: Message Lost Arbitration bit(1)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4 TXERRm: Error Detected During Transmission bit(1)
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3 TXREQm: Message Send Request bit
1 = Requests that a message be sent; the bit automatically clears when the message is successfully sent
0 = Clearing the bit to ‘0’ while set requests a message abort
bit 2 RTRENm: Auto-Remote Transmit Enable bit
1 = When a remote transmit is received, TXREQx will be set
0 = When a remote transmit is received, TXREQx will be unaffected
bit 1-0 TXmPRI<1:0>: Message Transmission Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority
Note 1: This bit is cleared when TXREQmn is set.
Note: The buffers, SIDx, EIDx, DLCx, Data Field and Receive Status registers, are located in DMA RAM.

23.4 CAN Message Buffers
CAN Message Buffers are part of RAM memory. They
are not CAN Special Function Registers. The user
application must directly write into the RAM area that is
configured for CAN Message Buffers. The location and
size of the buffer area is defined by the user
application.
BUFFER 21-1: CANx MESSAGE BUFFER WORD 0

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — SID10 SID9 SID8 SID7 SID6
bit 15 bit 8

SID5 SID4 SID3 SID2 SID1 SID0 SRR IDE
bit 7 bit 0
Legend:

bit 1 SRR: Substitute Remote Request bit
When IDE = 0:
1 = Message will request remote transmission
0 = Normal message
When IDE = 1:
The SRR bit must be set to ‘1’.
bit 0 IDE: Extended Identifier bit
1 = Message will transmit an Extended Identifier
0 = Message will transmit a Standard Identifier

U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
— — — — EID<17:14>
bit 15 bit 8

EID<13:6>
bit 7 bit 0
Legend:


(

EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1
bit 15 bit 8
U-x U-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — — RB0 DLC3 DLC2 DLC1 DLC0
bit 7 bit 0
Legend:

bit 9 RTR: Remote Transmission Request bit
When IDE = 1:
1 = Message will request remote transmission
0 = Normal message
When IDE = 0:
The RTR bit is ignored.
bit 8 RB1: Reserved Bit 1
User must set this bit to ‘0’ per CAN protocol.
bit 4 RB0: Reserved Bit 0
User must set this bit to ‘0’ per CAN protocol.
bit 3-0 DLC<3:0>: Data Length Code bits

Byte 1<15:8>
bit 15 bit 8

Byte 0<7:0>
bit 7 bit 0
Legend:
bit 15-8 Byte 1<15:8>: CANx Message Byte 1 bits


Byte 3<15:8>
bit 15 bit 8

Byte 2<7:0>
bit 7 bit 0
Legend:


Byte 5<15:8>
bit 15 bit 8

Byte 4<7:0>
bit 7 bit 0
Legend:


Byte 7<15:8>
bit 15 bit 8

Byte 6<7:0>
bit 7 bit 0
Legend:


U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — FILHIT<4:0>(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —
bit 7 bit 0
Legend:

bit 12-8 FILHIT<4:0>: Filter Hit Code bits(1)
Encodes number of filter that resulted in writing this buffer.
Note 1: Only written by module for receive buffers, unused for transmit buffers.

NOTES:

24.0 HIGH-SPEED ANALOG 24.1 Features Overview
COMPARATOR The Switch Mode Power Supply (SMPS) comparator
Note 1: This data sheet summarizes the module offers the following major features:
features of the dsPIC33EPXXXGS70X/ • Four Rail-to-Rail Analog Comparators
80X family of devices. It is not intended • Dedicated 12-Bit DAC for each Analog
to be a comprehensive reference source. Comparator
To complement the information in this data • Up to Six Selectable Input Sources per
sheet, refer to “High-Speed Analog Comparator:
Comparator Module” (DS70005128) in
- Four external inputs
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the - Two internal inputs from the PGAx module
Microchip website (www.microchip.com). • Programmable Comparator Hysteresis
2: Some registers and associated bits • Programmable Output Polarity
described in this section may not be • Up to Two DAC Outputs to Device Pins
available on all devices. Refer to • Multiple Voltage References for the DAC:
Section 4.0 “Memory Organization” in - External References (EXTREF1 or
this data sheet for device-specific register EXTREF2)
- AVDD
The high-speed analog comparator module monitors • Interrupt Generation Capability
current and/or voltage transients that may be too fast • Functional Support for PWMx:
for the CPU and ADC to capture. - PWM duty cycle control
- PWM period control
- PWM Fault detected

24.2 Module Description The analog comparator input pins are typically shared
with pins used by the Analog-to-Digital Converter (ADC)
Figure 24-1 shows a functional block diagram of one module. Both the comparator and the ADC can use the
analog comparator from the high-speed analog same pins at the same time. This capability enables a
comparator module. The analog comparator provides user to measure an input voltage with the ADC and
high-speed operation with a typical delay of 15 ns. The detect voltage transients with the comparator.
negative input of the comparator is always connected
to the DACx circuit. The positive input of the compara-
tor is connected to an analog multiplexer that selects
the desired source pin.
FIGURE 24-1: HIGH-SPEED ANALOG COMPARATOR x MODULE BLOCK DIAGRAM
INSELx
PWM Trigger
ALTINP
PGA1OUT (remappable I/O)
PGA2OUT
CMPxA(1)
MUX
CMPxB(1) Status
CMPx(1) 0 Pulse Stretcher
CMPxC(1) and
CMPxD(1) 1 Digital Filter Interrupt
Request
EXTREF
RANGE CMPPOL
AVDD
MUX
EXTREF1(2) DACx(1) DACOE
EXTREF2(2,3)
12 DAC1/
DAC3 Output
CMREFx Buffer
DACOUT1
PGA1OUT
DBCC bit
FDEVOPT<6>
PGAOEN
DACOE
DAC2/
DAC4 Output
Buffer
DACOUT2(3)
PGA2OUT
PGAOEN
Note 1: x = 1-4
2: EXTREF1 is connected to DAC1/DAC3. EXTREF2 is connected to DAC2/DAC4.
3: Not available on all devices.

24.3 Module Applications Each DACx has an output enable bit, DACOE, in the
CMPxCON register that enables the DACx reference
This module provides a means for the SMPS dsPIC® voltage to be routed to an external output pin
DSC devices to monitor voltage and currents in a (DACOUTx). Refer to Figure 24-1 for connecting the
power conversion application. The ability to detect DACx output voltage to the DACOUTx pins.
transient conditions and stimulate the dsPIC DSC
processor and/or peripherals, without requiring the Note 1: Ensure that multiple DACOE bits are not
processor and ADC to constantly monitor voltages or set in software. The output on the
currents, frees the dsPIC DSC to perform other tasks. DACOUTx pin will be indeterminate if
multiple comparators enable the DACx
The comparator module has a high-speed comparator output.
and an associated 12-bit DAC that provides a
programmable reference voltage to the inverting input 2: DACOUT2 is not available on all devices.
of the comparator. The polarity of the comparator out-
put is user-programmable. The output of the module 24.5 Pulse Stretcher and Digital Logic
can be used in the following modes:
The analog comparator can respond to very fast tran-
• Generate an Interrupt sient signals. After the comparator output is given the
• Trigger an ADC Sample and Convert Process desired polarity, the signal is passed to a pulse
• Truncate the PWM Signal (current limit) stretching circuit. The pulse stretching circuit has an
• Truncate the PWM Period (current minimum) asynchronous set function and a delay circuit that
ensures the minimum pulse width is three system clock
• Disable the PWM Outputs (Fault latch)
cycles wide to allow the attached circuitry to properly
The output of the comparator module may be used in respond to a narrow pulse event.
multiple modes at the same time, such as: 1) generate
The pulse stretcher circuit is followed by a digital filter.
an interrupt, 2) have the ADC take a sample and con-
The digital filter is enabled via the FLTREN bit in the
vert it, and 3) truncate the PWM output in response to
CMPxCON register. The digital filter operates with the
a voltage being detected beyond its expected value.
clock specified via the FCLKSEL bit in the CMPxCON
The comparator module can also be used to wake-up the register. The comparator signal must be stable in a high
system from Sleep or Idle mode when the analog input or low state, for at least three of the selected clock
voltage exceeds the programmed threshold voltage. cycles, for it to pass through the digital filter.
24.4 Digital-to-Analog Comparator (DAC)

Each analog comparator has a dedicated 12-bit DAC
that is used to program the comparator threshold voltage
via the CMPxDAC register. The DAC voltage reference
source is selected using the EXTREF and RANGE bits
in the CMPxCON register.
The EXTREF bit selects either the external voltage ref-
erence, EXTREFx, or an internal source as the voltage
reference source. The EXTREFx input enables users to
connect to a voltage reference that better suits their
application. The RANGE bit enables AVDD as the
voltage reference source for the DAC when an internal
voltage reference is selected.
Note: EXTREF2 is not available on all devices.

24.6 Hysteresis 24.7 Analog Comparator Resources
An additional feature of the module is hysteresis con- Many useful resources are provided on the main prod-
trol. Hysteresis can be enabled or disabled and its uct page of the Microchip website for the devices listed
amplitude can be controlled by the HYSSEL<1:0> bits in this data sheet. This product page contains the latest
in the CMPxCON register. Three different values are updates and additional information.
available: 15 mV, 30 mV and 45 mV. It is also possible
to select the edge (rising or falling) to which hysteresis 24.7.1 KEY RESOURCES
is to be applied.
• “High-Speed Analog Comparator Module”
Hysteresis control prevents the comparator output from (DS70005128) in the “dsPIC33/PIC24 Family
continuously changing state because of small Reference Manual”
perturbations (noise) at the input (see Figure 24-2). • Code Samples
FIGURE 24-2: HYSTERESIS CONTROL
• Webinars
Output
Manual” Sections
Hysteresis Range
(15 mV/30 mV/45 mV)
Input

REGISTER 24-1: CMPxCON: COMPARATOR x CONTROL REGISTER
CMPON — CMPSIDL HYSSEL1 HYSSEL0 FLTREN FCLKSEL DACOE
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0

INSEL1 INSEL0 EXTREF HYSPOL CMPSTAT ALTINP CMPPOL RANGE
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit

bit 15 CMPON: Comparator Operating Mode bit

1 = Comparator module is enabled
0 = Comparator module is disabled (reduces power consumption)
bit 13 CMPSIDL: Comparator Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode.
If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables all comparators while in Idle mode.
bit 12-11 HYSSEL<1:0>: Comparator Hysteresis Select bits
11 = 45 mV hysteresis
00 = No hysteresis is selected
bit 10 FLTREN: Digital Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 9 FCLKSEL: Digital Filter and Pulse Stretcher Clock Select bit
1 = Digital filter and pulse stretcher operate with the PWM clock
0 = Digital filter and pulse stretcher operate with the system clock
bit 8 DACOE: DACx Output Enable bit
1 = DACx analog voltage is connected to the DACOUTx pin(1)
0 = DACx analog voltage is not connected to the DACOUTx pin
bit 7-6 INSEL<1:0>: Input Source Select for Comparator bits
If ALTINP = 0, Select from Comparator Inputs:
11 = Selects CMPxD input pin
10 = Selects CMPxC input pin
01 = Selects CMPxB input pin
00 = Selects CMPxA input pin
If ALTINP = 1, Select from Alternate Inputs:
11 = Reserved
10 = Reserved
01 = Selects PGA2 output
00 = Selects PGA1 output
Note 1: DACOUTx can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DACx output by setting their respective DACOE bit.

REGISTER 24-1: CMPxCON: COMPARATOR x CONTROL REGISTER (CONTINUED)
bit 5 EXTREF: Enable External Reference bit
1 = External source provides reference to DACx (maximum DAC voltage is determined by the external
voltage source)
0 = AVDD provides reference to DACx (maximum DAC voltage is AVDD)
bit 4 HYSPOL: Comparator Hysteresis Polarity Select bit
1 = Hysteresis is applied to the falling edge of the comparator output
0 = Hysteresis is applied to the rising edge of the comparator output
bit 3 CMPSTAT: Comparator Current State bit
Reflects the current output state of Comparator x, including the setting of the CMPPOL bit.
bit 2 ALTINP: Alternate Input Select bit
1 = INSEL<1:0> bits select alternate inputs
0 = INSEL<1:0> bits select comparator inputs
bit 1 CMPPOL: Comparator Output Polarity Control bit
1 = Output is inverted
0 = Output is non-inverted
bit 0 RANGE: DACx Output Voltage Range Select bit
1 = AVDD is the maximum DACx output voltage
0 = Unimplemented, do not use
Note 1: DACOUTx can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DACx output by setting their respective DACOE bit.

REGISTER 24-2: CMPxDAC: COMPARATOR x DAC CONTROL REGISTER
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — CMREF<11:8>
bit 15 bit 8

CMREF<7:0>
bit 7 bit 0
Legend:

bit 11-0 CMREF<11:0>: Comparator Reference Voltage Select bits
111111111111
•
•
• = ([CMREF<11:0>] * (AVDD)/4096) volts (EXTREF = 0)
• or ([CMREF<11:0>] * (EXTREF)/4096) volts (EXTREF = 1)
•
•
000000000000

NOTES:

25.0 PROGRAMMABLE GAIN The dsPIC33EPXXXGS70X/80X family devices have
two Programmable Gain Amplifiers (PGA1, PGA2).
AMPLIFIER (PGA)
The PGA is an op amp-based, non-inverting amplifier
Note 1: This data sheet summarizes the with user-programmable gains. The output of the PGA
features of the dsPIC33EPXXXGS70X/ can be connected to a number of dedicated Sample-
80X family of devices. It is not intended and-Hold inputs of the Analog-to-Digital Converter and/
to be a comprehensive reference source. or to the high-speed analog comparator module. The
To complement the information in this data PGA has five selectable gains and may be used as a
sheet, refer to “Programmable Gain ground referenced amplifier (single-ended) or used
Amplifier (PGA)” (DS70005146) in the with an independent ground reference point.
“dsPIC33/PIC24 Family Reference Man- Key features of the PGA module include:
ual”, which is available from the Microchip
• Single-Ended or Independent Ground Reference
website (www.microchip.com).
• Selectable Gains: 4x, 8x, 16x, 32x and 64x
• High Gain Bandwidth
available on all devices. Refer to • Rail-to-Rail Output Voltage
Section 4.0 “Memory Organization” in • Wide Input Voltage Range
FIGURE 25-1: PGAx MODULE BLOCK DIAGRAM
GAIN<2:0> = 6
Gain of 64x
GAIN<2:0> = 5
Gain of 32x
GAIN<2:0> = 4
Gain of 16x
GAIN<2:0> = 3
Gain of 8x
GAIN<2:0> = 2
Gain of 4x
PGAx Negative Input – PGAxOUT

AMPx
PGAx Positive Input +
PGACAL<5:0>
Note 1: x = 1 and 2.

25.1 Module Description input source. To provide an independent ground
reference, the PGAxN2 and PGAxN3 pins are available
The Programmable Gain Amplifiers are used to amplify as the negative input source to the PGAx module.
small voltages (i.e., voltages across burden/shunt
resistors) to improve the signal-to-noise ratio of the Note 1: Not all PGA positive/negative inputs are
measured signal. The PGAx output voltage can be available on all devices. Refer to the
read by any of the four dedicated Sample-and-Hold specific device pinout for available input
circuits on the ADC module. The output voltage can source pins.
also be fed to the comparator module for overcurrent/ The output voltage of the PGAx module can be
voltage protection. Figure 25-2 shows a functional connected to the DACOUTx pin by setting the
block diagram of the PGAx module. Refer to PGAOEN bit in the PGAxCON register. When the
Section 22.0 “High-Speed, 12-Bit Analog-to-Digital PGAOEN bit is enabled, the output voltage of PGA1 is
Converter (ADC)” and Section 24.0 “High-Speed connected to DACOUT1 and PGA2 is connected to
Analog Comparator” for more interconnection details. DACOUT2. For devices with a single DACOUTx pin,
The gain of the PGAx module is selectable via the the output voltage of PGA2 can be connected to
GAIN<2:0> bits in the PGAxCON register. There are DACOUT1 by configuring the DBCC Configuration bit
five selectable gains, ranging from 4x to 64x. The in the FDEVOPT register (FDEVOPT<6>).
SELPI<2:0> and SELNI<2:0> bits in the PGAxCON If both the DACx output voltage and PGAx output volt-
register select one of four positive/negative inputs to age are connected to the DACOUTx pin, the resulting
the PGAx module. For single-ended applications, the output voltage would be a combination of signals.
SELNI<2:0> bits will select the ground as the negative There is no assigned priority between the PGAx
module and the DACx module.
FIGURE 25-2: PGAx FUNCTIONAL BLOCK DIAGRAM
INSEL<1:0>
(CMPCONx)
SELPI<2:0>
PGAxCON(1) PGAxCAL(1)
+
PGAEN GAIN<2:0> –
PGAxP1(1)
DACx
PGAxP2(1) PGACAL<5:0>
PGAxP3(1)
CxCHS<1:0>
PGAxP4(1) (ADCON4H)
ADC
+
PGAx(1) S&H
GND
–
PGAxN2(1)
PGAxN3(1,3)
GND
PGAOEN
SELNI<2:0> To DACOUTx Pin(2)
Note 1: x = 1 and 2.
2: The DACOUT2 device pin is only available on 64-pin devices.
3: The PGAxN3 input is not available on 28-pin devices.

25.2 PGA Resources 25.2.1 KEY RESOURCES
Many useful resources are provided on the main prod- • “Programmable Gain Amplifier (PGA)”
uct page of the Microchip website for the devices listed (DS70005146) in the “dsPIC33/PIC24 Family
in this data sheet. This product page contains the latest Reference Manual”
updates and additional information. • Code Samples
• Webinars
Manual” Sections
REGISTER 25-1: PGAxCON: PGAx CONTROL REGISTER

PGAEN PGAOEN SELPI2 SELPI1 SELPI0 SELNI2 SELNI1 SELNI0
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — GAIN2 GAIN1 GAIN0
bit 7 bit 0
Legend:
bit 15 PGAEN: PGAx Enable bit

1 = PGAx module is enabled
0 = PGAx module is disabled (reduces power consumption)
bit 14 PGAOEN: PGAx Output Enable bit
1 = PGAx output is connected to the DACOUTx pin
0 = PGAx output is not connected to the DACOUTx pin
bit 13-11 SELPI<2:0>: PGAx Positive Input Selection bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = PGAxP4
010 = PGAxP3
001 = PGAxP2
000 = PGAxP1
bit 10-8 SELNI<2:0>: PGAx Negative Input Selection bits
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = Ground (Single-Ended mode)
010 = PGAxN3
001 = PGAxN2
000 = Ground (Single-Ended mode)

REGISTER 25-1: PGAxCON: PGAx CONTROL REGISTER (CONTINUED)
bit 2-0 GAIN<2:0>: PGAx Gain Selection bits
111 = Reserved
110 = Gain of 64x
101 = Gain of 32x
100 = Gain of 16x
011 = Gain of 8x
010 = Gain of 4x
001 = Reserved
000 = Reserved
REGISTER 25-2: PGAxCAL: PGAx CALIBRATION REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — PGACAL<5:0>
bit 7 bit 0
Legend:

bit 5-0 PGACAL<5:0>: PGAx Offset Calibration bits
The calibration values for PGA1 and PGA2 must be copied from Flash addresses, 0x800E48 and
0x800E4C, respectively, into these bits before the module is enabled. Refer to the calibration data
address table (Table 27-3) in Section 27.0 “Special Features” for more information.

26.0 CONSTANT-CURRENT 26.1 Features Overview
SOURCE The constant-current source module offers the following
major features:
features of the dsPIC33EPXXXGS70X/ • Constant-Current Generator (10 µA nominal)
80X family of devices. It is not intended • Internal Selectable Connection to One of Four Pins
to be a comprehensive reference source. • Enable/Disable bit
To complement the information in this data
sheet, refer to the related section of the 26.2 Module Description
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip Figure 26-1 shows a functional block diagram of the
website (www.microchip.com). constant-current source module. It consists of a
2: Some registers and associated bits precision current generator with a nominal value of
described in this section may not be 10 µA. The module can be enabled and disabled using
available on all devices. Refer to the ISRCEN bit in the ISRCCON register. The output
Section 4.0 “Memory Organization” in of the current generator is internally connected to a
this data sheet for device-specific register device pin. The dsPIC33EPXXXGS70X/80X family
and bit information. can have up to four selectable current source pins.
The OUTSEL<2:0> bits in the ISRCCON register allow
The constant-current source module is a precision selection of the target pin.
current generator and is used in conjunction with the The current source is calibrated during testing.
ADC module to measure the resistance of external
resistors connected to device pins.
FIGURE 26-1: CONSTANT-CURRENT SOURCE MODULE BLOCK DIAGRAM
Constant-Current Source
ISRC1
M ISRC2
U
X ISRC3
ISRC4
ISRCEN
OUTSEL<2:0>

26.3 Current Source Control Register
REGISTER 26-1: ISRCCON: CONSTANT-CURRENT SOURCE CONTROL REGISTER
R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
ISRCEN — — — — OUTSEL2(1) OUTSEL1(1) OUTSEL0(1)
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — ISRCCAL5 ISRCCAL4 ISRCCAL3 ISRCCAL2 ISRCCAL1 ISRCCAL0
bit 7 bit 0
Legend:
bit 15 ISRCEN: Constant-Current Source Enable bit

1 = Current source is enabled
0 = Current source is disabled
bit 10-8 OUTSEL<2:0>: Output Constant-Current Select bits(1)
111 = Reserved
110 = Reserved
101 = Reserved
100 = Reserved
011 = Input pin, ISRC4 (AN4)
bit 5-0 ISRCCAL<5:0>: Constant-Current Source Calibration bits
The calibration value must be copied from Flash address, 0x800E78, into these bits before the
module is enabled. Refer to the calibration data address table (Table 27-3) in Section 27.0 “Special
Features” for more information.
Note 1: ISRC1 and ISCR3 are not available on 28, 44 and 48-pin packages. Refer to the “Pin Diagrams” section
for availability.

27.0 SPECIAL FEATURES 27.1 Configuration Bits
Note: This data sheet summarizes the features of In dsPIC33EPXXXGS70X/80X family devices, the
the dsPIC33EPXXXGS70X/80X family of Configuration Words are implemented as volatile
devices. It is not intended to be a compre- memory. This means that configuration data must be
hensive reference source. To complement programmed each time the device is powered up.
the information in this data sheet, refer to Configuration data is stored at the end of the on-chip
“Device Configuration” (DS70000618), program memory space, known as the Flash Configura-
“Watchdog Timer and Power-Saving tion Words. Their specific locations are shown in
Modes” (DS70615) and “CodeGuard™ Table 27-1 with detailed descriptions in Table 27-2. The
Intermediate Security” (DS70005182) in configuration data is automatically loaded from the Flash
the “dsPIC33/PIC24 Family Reference Configuration Words to the proper Configuration
Manual”, which is available from the Shadow registers during device Resets.
Microchip website (www.microchip.com). For devices operating in Dual Partition Flash modes, the
BSEQx bits (FBTSEQ<11:0>) determine which panel is
The dsPIC33EPXXXGS70X/80X family devices the Active Partition at start-up and the Configuration
include several features intended to maximize Words from that panel are loaded into the Configuration
application flexibility and reliability, and minimize cost Shadow registers.
through elimination of external components. These are:
Note: Configuration data is reloaded on all types
• Flexible Configuration
of device Resets.
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security When creating applications for these devices, users
• JTAG Boundary Scan Interface should always specifically allocate the location of the
Flash Configuration Words for configuration data in
• In-Circuit Serial Programming™ (ICSP™)
their code for the compiler. This is to make certain that
• In-Circuit Emulation program code is not stored in this address when the
• Brown-out Reset (BOR) code is compiled. Program code executing out of
configuration space will cause a device Reset.
Note: Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words.

TABLE 27-1: CONFIGURATION REGISTER MAP(3)
DS70005258C-page 352
Device
Memory
Name Address Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Size
(Kbytes)
00AF80 64
FSEC — AIVTDIS — — — CSS<2:0> CWRP GSS<1:0> GWRP — BSEN BSS<1:0> BWRP
015780 128
00AF90 64
FBSLIM — — — — BSLIM<12:0>
015790 128
00AF90 64
FSIGN — Reserved(2) — — — — — — — — — — — — — — —
015794 128
00AF98 64
FOSCSEL — — — — — — — — — IESO — — — — FNOSC<2:0>
015798 128
00AF9C 64
FOSC — — — — — — — — PLLKEN FCKSM<1:0> IOL1WAY — — OSCIOFNC POSCMD<1:0>
01579C 128
00AFA0 64
FWDT — — — — — — — WDTWIN<1:0> WINDIS WDTEN<1:0> WDTPRE WDTPOST<3:0>
0157A0 128
00AFA4 64
FPOR — — — — — — — — — — — — — — — — Reserved(1)
0157A4 128
00AFA8 64
FICD — BTSWP — — — — — — — Reserved(1) — JTAGEN — — — ICS<1:0>
0157A8 128
FDEVOPT 00AFAC 64
— — — — — — — — — — DBCC — ALTI2C2 ALTI2C1 Reserved(1) — PWMLOCK
0157AC 128
FALTREG 00AFB0 64 — —
CTXT4<2:0> — CTXT3<3:0> — CTXT2 <2:0> — CTXT1 <2:0>
0157B0 128
FBTSEQ 00AFFC 64
IBSEQ<11:0> BSEQ<11:0>
0157FC 128
FBOOT(4) 801000 — — — — — — — — — — — — — — — — BTMODE<1:0>
Note 1: These bits are reserved and must be programmed as ‘1’.

2: This bit is reserved and must be programmed as ‘0’.
3: When operating in Dual Partition Flash mode, each partition will have dedicated Configuration registers. On a device Reset, the configuration values of the Active Partition are read at start-up, but during a soft
swap condition, the configuration settings of the newly Active Partition are ignored.
4: FBOOT resides in configuration memory space.
TABLE 27-2: CONFIGURATION BITS DESCRIPTION
Bit Field Description
BSS<1:0> Boot Segment Code-Protect Level bits
11 = Boot Segment is not code-protected other than BWRP
10 = Standard security
0x = High security
BSEN Boot Segment Control bit
1 = No Boot Segment is enabled
0 = Boot Segment size is determined by the BSLIM<12:0> bits
BWRP Boot Segment Write-Protect bit
1 = Boot Segment can be written
0 = Boot Segment is write-protected
BSLIM<12:0> Boot Segment Flash Page Address Limit bits
Contains the last active Boot Segment page. The value to be programmed is the inverted
page address, such that programming additional ‘0’s can only increase the Boot Segment
size (i.e., 0x1FFD = 2 Pages or 1024 IW).
GSS<1:0> General Segment Code-Protect Level bits
11 = User program memory is not code-protected
0x = High security
GWRP General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
CWRP Configuration Segment Write-Protect bit
1 = Configuration data is not write-protected
0 = Configuration data is write-protected
CSS<2:0> Configuration Segment Code-Protect Level bits
111 = Configuration data is not code-protected
10x = Enhanced security
0xx = High security
BTSWP BOOTSWP Instruction Enable/Disable bit
1 = BOOTSWP instruction is disabled
0 = BOOTSWP instruction is enabled
BSEQ<11:0> Boot Sequence Number bits (Dual Partition modes only)
Relative value defining which partition will be active after device Reset; the partition
containing a lower boot number will be active.
IBSEQ<11:0> Inverse Boot Sequence Number bits (Dual Partition modes only)
The one’s complement of BSEQ<11:0>; must be calculated by the user and written for
device programming. If BSEQx and IBSEQx are not complements of each other, the Boot
Sequence Number is considered to be invalid.
AIVTDIS(1) Alternate Interrupt Vector Table bit
1 = Alternate Interrupt Vector Table is disabled
0 = Alternate Interrupt Vector Table is enabled if INTCON2<8> = 1
IESO Two-Speed Oscillator Start-up Enable bit
1 = Starts up device with FRC, then automatically switches to the user-selected oscillator
source when ready
0 = Starts up device with the user-selected oscillator source
PWMLOCK PWMx Lock Enable bit
1 = Certain PWMx registers may only be written after a key sequence
0 = PWMx registers may be written without a key sequence
Note 1: The Boot Segment must be present to use the Alternate Interrupt Vector Table.

TABLE 27-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)
FNOSC<2:0> Oscillator Selection bits
111 = Fast RC Oscillator with Divide-by-N (FRCDIVN)
110 = Fast RC Oscillator with Divide-by-16
100 = Reserved; do not use
011 = Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL)
001 = Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL)
FCKSM<1:0> Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY Peripheral Pin Select Configuration bit
1 = Allows only one reconfiguration
0 = Allows multiple reconfigurations
OSCIOFNC OSC2 Pin Function bit (except in XT and HS modes)
1 = OSC2 is the clock output
0 = OSC2 is a general purpose digital I/O pin
POSCMD<1:0> Primary Oscillator Mode Select bits
11 = Primary Oscillator is disabled
10 = HS Crystal Oscillator mode
01 = XT Crystal Oscillator mode
00 = EC (External Clock) mode
WDTEN<1:0> Watchdog Timer Enable bits
11 = Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the
SWDTEN bit in the RCON register will have no effect)
10 = Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by
clearing the SWDTEN bit in the RCON register)
01 = Watchdog Timer is enabled only while device is active and is disabled while in Sleep
mode; software control is disabled in this mode
00 = Watchdog Timer and SWDTEN bit are disabled
WINDIS Watchdog Timer Window Enable bit
1 = Watchdog Timer is in Non-Window mode
0 = Watchdog Timer is in Window mode
PLLKEN PLL Lock Enable bit
1 = PLL lock is enabled
0 = PLL lock is disabled
WDTPRE Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
WDTPOST<3:0> Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
0001 = 1:2
0000 = 1:1

WDTWIN<1:0> Watchdog Timer Window Select bits
11 = WDT window is 25% of the WDT period
10 = WDT window is 37.5% of the WDT period
ALTI2C1 Alternate I2C1 Pin bit
1 = I2C1 is mapped to the SDA1/SCL1 pins
0 = I2C1 is mapped to the ASDA1/ASCL1 pins
ALTI2C2 Alternate I2C2 Pin bit
1 = I2C2 is mapped to the SDA2/SCL2 pins
0 = I2C2 is mapped to the ASDA2/ASCL2 pins
JTAGEN JTAG Enable bit
1 = JTAG is enabled
0 = JTAG is disabled
ICS<1:0> ICD Communication Channel Select bits
11 = Communicates on PGEC1 and PGED1
00 = Reserved, do not use
DBCC DACx Output Cross Connection Select bit
1 = No cross connection between DAC outputs
0 = Interconnects DACOUT1 and DACOUT2
CTXT1<2:0> Alternate Working Register Set 1 Interrupt Priority Level (IPL) Select bits
111 = Reserved
110 = Assigned to IPL of 7
111 = Reserved
111 = Reserved

111 = Reserved
BTMODE<1:0> Boot Mode Configuration bits
11 = Single Partition mode
10 = Dual Partition mode
01 = Protected Dual Partition mode
00 = Privileged Dual Partition mode

27.2 Device Calibration and The dsPIC33EPXXXGS70X/80X devices have two
Identification Identification registers near the end of configuration
memory space that store the Device ID (DEVID) and
The PGAx and current source modules on the Device Revision (DEVREV). These registers are used
dsPIC33EPXXXGS70X/80X family devices require to determine the mask, variant and manufacturing
Calibration Data registers to improve performance of information about the device. These registers are
the module over a wide operating range. These read-only and are shown in Register 27-1 and
Calibration registers are read-only and are stored in Register 27-2.
configuration memory space. Prior to enabling the
module, the calibration data must be read (TBLPAG
and Table Read instruction) and loaded into its respec-
tive SFR registers. The device calibration addresses
are shown in Table 27-3.
TABLE 27-3: DEVICE CALIBRATION ADDRESSES(1)

Calibration
Address Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
PGA1CAL 800E48 — — — — — — — — — — — PGA1 Calibration Data

PGA2CAL 800E4C — — — — — — — — — — — PGA2 Calibration Data
ISRCCAL 800E78 — — — — — — — — — — — Current Source Calibration Data
Note 1: The calibration data must be copied into its respective SFR registers prior to enabling the module.

REGISTER 27-1: DEVID: DEVICE ID REGISTER
R R R R R R R R
DEVID<23:16>
bit 23 bit 16
R R R R R R R R
DEVID<15:8>
bit 15 bit 8
R R R R R R R R
DEVID<7:0>
bit 7 bit 0
Legend: R = Read-Only bit U = Unimplemented bit
bit 23-0 DEVID<23:0>: Device Identifier bits
REGISTER 27-2: DEVREV: DEVICE REVISION REGISTER

R R R R R R R R
DEVREV<23:16>
bit 23 bit 16
R R R R R R R R
DEVREV<15:8>
bit 15 bit 8
R R R R R R R R
DEVREV<7:0>
bit 7 bit 0
Legend: R = Read-only bit U = Unimplemented bit
bit 23-0 DEVREV<23:0>: Device Revision bits

27.3 User OTP Memory 27.5 Brown-out Reset (BOR)
The dsPIC33EPXXXGS70X/80X family devices contain The Brown-out Reset (BOR) module is based on an
64 words of user One-Time-Programmable (OTP) mem- internal voltage reference circuit that monitors the reg-
ory, located at addresses, 0x800F80 through 0x800FFC. ulated supply voltage, VCAP. The main purpose of the
The user OTP Words can be used for storing checksum, BOR module is to generate a device Reset when a
code revisions, product information, such as serial brown-out condition occurs. Brown-out conditions are
numbers, system manufacturing dates, manufacturing lot generally caused by glitches on the AC mains (for
numbers and other application-specific information. example, missing portions of the AC cycle waveform
These words can only be written once at program time due to bad power transmission lines or voltage sags
and not at run time; they can be read at run time. due to excessive current draw when a large inductive
load is turned on).
27.4 On-Chip Voltage Regulator A BOR generates a Reset pulse which resets the
device. The BOR selects the clock source based on the
All the dsPIC33EPXXXGS70X/80X family devices power
device Configuration bit values (FNOSC<2:0> and
their core digital logic at a nominal 1.8V. This can create
POSCMD<1:0>).
a conflict for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system If an Oscillator mode is selected, the BOR activates the
design, all devices in the dsPIC33EPXXXGS70X/80X Oscillator Start-up Timer (OST). The system clock is
family incorporate an on-chip regulator that allows the held until OST expires. If the PLL is used, the clock is
device to run its core logic from VDD. held until the LOCK bit (OSCCON<5>) is ‘1’.
The regulator provides power to the core from the other Concurrently, the Power-up Timer (PWRT) Time-out
VDD pins. A low-ESR (less than 1 Ohm) capacitor (such (TPWRT) is applied before the internal Reset is released.
as tantalum or ceramic) must be connected to the VCAP If TPWRT = 0 and a crystal oscillator is being used, then a
pin (Figure 27-1). This helps to maintain the stability of nominal delay of TFSCM is applied. The total delay in this
the regulator. The recommended value for the filter case is TFSCM. Refer to Parameter SY35 in Table 30-23
capacitor is provided in Table 30-5, located in of Section 30.0 “Electrical Characteristics” for specific
Section 30.0 “Electrical Characteristics”. TFSCM values.
Note: It is important for the low-ESR capacitor to The BOR status bit (RCON<1>) is set to indicate that a
be placed as close as possible to the VCAP BOR has occurred. The BOR circuit continues to oper-
pin. ate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
FIGURE 27-1: CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1,2,3)
3.3V
dsPIC33EP
VDD
VCAP
CEFC
VSS
Note 1: These are typical operating voltages. Refer

to Table 30-5 located in Section 30.0
“Electrical Characteristics” for the full
operating ranges of VDD and VCAP.
2: It is important for the low-ESR capacitor
to be placed as close as possible to the
VCAP pin.
3: Typical VCAP pin voltage = 1.8V when
VDD ≥ VDDMIN.

27.6 Watchdog Timer (WDT) 27.6.2 SLEEP AND IDLE MODES
For dsPIC33EPXXXGS70X/80X family devices, the If the WDT is enabled, it continues to run during Sleep or
WDT is driven by the LPRC oscillator. When the WDT Idle modes. When the WDT time-out occurs, the device
is enabled, the clock source is also enabled. wakes and code execution continues from where the
PWRSAV instruction was executed. The corresponding
27.6.1 PRESCALER/POSTSCALER SLEEP or IDLE bit (RCON<3:2>) needs to be cleared in
software after the device wakes up.
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either 27.6.3 ENABLING WDT
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration The WDT is enabled or disabled by the WDTEN<1:0>
bit. With a 32 kHz input, the prescaler yields a WDT Configuration bits in the FWDT Configuration register.
Time-out Period (TWDT), as shown in Parameter SY12 When the WDTEN<1:0> Configuration bits have been
in Table 30-23. programmed to ‘0b11’, the WDT is always enabled.
A variable postscaler divides down the WDT prescaler The WDT can be optionally controlled in software
output and allows for a wide range of time-out periods. when the WDTEN<1:0> Configuration bits have been
The postscaler is controlled by the WDTPOST<3:0> programmed to ‘0b10’. The WDT is enabled in soft-
Configuration bits (FWDT<3:0>), which allow the ware by setting the SWDTEN control bit (RCON<5>).
selection of 16 settings, from 1:1 to 1:32,768. Using the The SWDTEN control bit is cleared on any device
prescaler and postscaler time-out periods, ranges from Reset. The software WDT option allows the user appli-
1 ms to 131 seconds can be achieved. cation to enable the WDT for critical code segments
and disables the WDT during non-critical segments for
The WDT, prescaler and postscaler are reset: maximum power savings.
• On any device Reset The WDT Time-out flag bit, WDTO (RCON<4>), is not
• On the completion of a clock switch, whether automatically cleared following a WDT time-out. To
invoked by software (i.e., setting the OSWEN bit detect subsequent WDT events, the flag must be
after changing the NOSCx bits) or by hardware cleared in software.
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed 27.6.4 WDT WINDOW
(i.e., Sleep or Idle mode is entered) The Watchdog Timer has an optional Windowed mode,
• When the device exits Sleep or Idle mode to enabled by programming the WINDIS bit in the WDT
resume normal operation Configuration register (FWDT<7>). In the Windowed
• By a CLRWDT instruction during normal execution mode (WINDIS = 0), the WDT should be cleared based
on the settings in the programmable Watchdog Timer
Note: The CLRWDT and PWRSAV instructions
Window select bits (WDTWIN<1:0>).
clear the prescaler and postscaler counts
when executed.
FIGURE 27-2: WDT BLOCK DIAGRAM
All Device Resets

Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
Watchdog Timer
Sleep/Idle
WDTPRE WDTPOST<3:0>
SWDTEN WDT
WDTEN<1:0> Wake-up
1
RS RS
Prescaler Postscaler
LPRC Clock (Divide-by-N1) (Divide-by-N2) WDT
0 Reset
WINDIS
WDT Window Select
WDTWIN<1:0>
CLRWDT Instruction

27.7 JTAG Interface 27.10 Code Protection and
The dsPIC33EPXXXGS70X/80X family devices imple-
CodeGuard™ Security
ment a JTAG interface, which supports boundary scan dsPIC33EPXXXGS70X/80X devices offer multiple levels
device testing. Detailed information on this interface is of security for protecting individual intellectual property.
provided in future revisions of the document. The program Flash protection can be broken up into
Note: Refer to “Programming and Diagnostics” three segments: Boot Segment (BS), General Segment
(DS70608) in the “dsPIC33/PIC24 Family (GS) and Configuration Segment (CS). Boot Segment
Reference Manual” for further information on has the highest security privilege and can be thought to
usage, configuration and operation of the have limited restrictions when accessing other segments.
JTAG interface. General Segment has the least security and is intended
for the end user system code. Configuration Segment
contains only the device user configuration data which is
27.8 In-Circuit Serial Programming™ located at the end of the program memory space.
(ICSP™) The code protection features are controlled by the
The dsPIC33EPXXXGS70X/80X family devices can be Configuration registers, FSEC and FBSLIM. The FSEC
serially programmed while in the end application circuit. register controls the code-protect level for each
This is done with two lines for clock and data, and three segment and if that segment is write-protected. The
other lines for power, ground and the programming size of BS and GS will depend on the BSLIM<12:0> bits
sequence. Serial programming allows customers to setting and if the Alternate Interrupt Vector Table (AIVT)
manufacture boards with unprogrammed devices and is enabled. The BSLIM<12:0> bits define the number of
then program the device just before shipping the pages for BS with each page containing 512 IW. The
product. Serial programming also allows the most recent smallest BS size is one page, which will consist of the
firmware or a custom firmware to be programmed. Interrupt Vector Table (IVT) and 256 IW of code
Refer to the “dsPIC33E/PIC24E Flash Programming protection.
Specification for Devices with Volatile Configuration If the AIVT is enabled, the last page of BS will contain
Bits” (DS70663) for details about In-Circuit Serial the AIVT and will not contain any BS code. With AIVT
Programming™ (ICSP™). enabled, the smallest BS size is now two pages
Any of the three pairs of programming clock/data pins (1024 IW), with one page for the IVT and BS code, and
can be used: the other page for the AIVT. Write protection of the BS
does not cover the AIVT. The last page of BS can
• PGEC1 and PGED1
always be programmed or erased by BS code. The
• PGEC2 and PGED2 General Segment will start at the next page and will
• PGEC3 and PGED3 consume the rest of program Flash except for the Flash
Configuration Words. The IVT will assume GS security
27.9 In-Circuit Debugger only if BS is not enabled. The IVT is protected from
being programmed or page erased when either
When MPLAB® ICD 3 or REAL ICE™ emulator is security segment has enabled write protection.
selected as a debugger, the in-circuit debugging function-
ality is enabled. This function allows simple debugging Note: Refer to “CodeGuard™ Intermediate
functions when used with MPLAB IDE. Debugging func- Security” (DS70005182) in the “dsPIC33/
tionality is controlled through the PGECx (Emulation/ PIC24 Family Reference Manual” for further
Debug Clock) and PGEDx (Emulation/Debug Data) pin information on usage, configuration and
functions. operation of CodeGuard Security.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins (PGECx and PGEDx).

The different device security segments are shown in Privileged Dual Partition mode performs the same
Figure 27-3. Here, all three segments are shown but function as Protected Dual Partition mode, except
are not required. If only basic code protection is additional constraints are applied in an effort to prevent
required, then GS can be enabled independently or code in the Boot Segment and General Segment from
combined with CS, if desired. being used against each other.
FIGURE 27-3: SECURITY SEGMENTS FIGURE 27-4: SECURITY SEGMENTS

EXAMPLE FOR EXAMPLE FOR
dsPIC33EPXXXGS70X/80X dsPIC33EP64GS70X/80X
DEVICES DEVICES (DUAL
PARTITION MODES)
0x000000
IVT 0x000000
0x000200 IVT
IVT and AIVT 0x000200
Assume BS IVT and AIVT
BS Protection Assume BS
BS Protection
AIVT + 256 IW(2)
BSLIM<12:0> AIVT + 256IW(2)
BSLIM<12:0>
GS
GS
CS(1) 0x0XXX00
CS(1)
0x005800
Unimplemented
Note 1: If CS is write-protected, the last page (read ‘0’s)
(GS + CS) of program memory will be 0x400000
protected from an erase condition. IVT
2: The last half (256 IW) of the last page of 0x400200
BS is unusable program memory.
IVT and AIVT
Assume BS
BS Protection
dsPIC33EPXXXGS70X/80X family devices can be
operated in Dual Partition mode, where security is
AIVT + 256 IW(2)
required for each partition. When operating in Dual Par-
BSLIM<12:0>
tition mode, the Active and Inactive Partitions both
contain unique copies of the Reset vector, Interrupt
Vector Tables (IVT and AIVT, if enabled) and the Flash
GS
Configuration Words. Both partitions have the three
security segments described previously. Code may not
be executed from the Inactive Partition, but it may be
programmed by, and read from, the Active Partition, CS(1)
0x405800
subject to defined code protection. Figure 27-4 and
Figure 27-5 show the different security segments for
devices operating in Dual Partition mode. Note 1: If CS is write-protected, the last page
(GS + CS) of program memory will be
The device may also operate in a Protected Dual protected from an erase condition.
Partition mode or in Privileged Dual Partition mode. In 2: The last half (256 IW) of the last page of
Protected Dual Partition mode, Partition 1 is perma- BS is unusable program memory.
nently erase/write-protected. This implementation
allows for a “Factory Default” mode, which provides a
fail-safe backup image to be stored in Partition 1. For
example, a fail-safe bootloader can be placed in
Partition 1, along with a fail-safe backup code image,
which can be used or rewritten into Partition 2 in the
event of a failed Flash update to Partition 2.

FIGURE 27-5: SECURITY SEGMENTS
EXAMPLE FOR
dsPIC33EP128GS70X/80X
DEVICES (DUAL
PARTITION MODES)
0x000000
IVT
0x000200
IVT and AIVT
Assume BS
BS Protection
AIVT + 256IW(2)
BSLIM<12:0>
GS
CS(1)
0x00AC00
Unimplemented
(read ‘0’s)
0x400000
IVT
0x400200
IVT and AIVT
Assume BS
BS Protection
AIVT + 256 IW(2)

BSLIM<12:0>
GS
CS(1)
0x40AC00
Note 1: If CS is write-protected, the last page

(GS + CS) of program memory will be
protected from an erase condition.
2: The last half (256 IW) of the last page of
BS is unusable program memory.

NOTES:

28.0 INSTRUCTION SET SUMMARY Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
Note: This data sheet summarizes the • The W register (with or without an address
features of the dsPIC33EPXXXGS70X/ modifier) or file register (specified by the value of
80X family of devices. It is not intended to ‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
sheet, refer to the related section of the
register ‘Wb’)
“dsPIC33/PIC24 Family Reference Manual”,
which is available from the Microchip The literal instructions that involve data movement can
web site (www.microchip.com). use some of the following operands:
• A literal value to be loaded into a W register or file
The dsPIC33EP instruction set is almost identical to
register (specified by ‘k’)
that of the dsPIC30F and dsPIC33F.
• The W register or file register where the literal
Most instructions are a single program memory word value is to be loaded (specified by ‘Wb’ or ‘f’)
(24 bits). Only three instructions require two program
memory locations. However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction • The first source operand, which is a register ‘Wb’
type and one or more operands, which further specify without any address modifier
the operation of the instruction. • The second source operand, which is a literal
value
The instruction set is highly orthogonal and is grouped
into five basic categories: • The destination of the result (only if not the same
as the first source operand), which is typically a
• Word or byte-oriented operations register ‘Wd’ with or without an address modifier
• Bit-oriented operations
The MAC class of DSP instructions can use some of the
• Literal operations following operands:
• DSP operations
• The accumulator (A or B) to be used (required
• Control operations operand)
Table 28-1 lists the general symbols used in describing • The W registers to be used as the two operands
the instructions. • The X and Y address space prefetch operations
The dsPIC33E instruction set summary in Table 28-2 • The X and Y address space prefetch destinations
lists all the instructions, along with the status flags • The accumulator write back destination
affected by each instruction.
The other DSP instructions do not involve any
Most word or byte-oriented W register instructions multiplication and can include:
(including barrel shift instructions) have three
operands: • The accumulator to be used (required)
• The source or destination operand (designated as
• The first source operand, which is typically a
Wso or Wdo, respectively) with or without an
register ‘Wb’ without any address modifier
address modifier
• The second source operand, which is typically a
• The amount of shift specified by a W register ‘Wn’
register ‘Ws’ with or without an address modifier
or a literal value
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier The control instructions can use some of the following
operands:
However, word or byte-oriented file register instructions
have two operands: • A program memory address
• The mode of the Table Read and Table Write
• The file register specified by the value ‘f’
instructions
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’

Most instructions are a single word. Certain double-word these cases, the execution takes multiple instruction
instructions are designed to provide all the required cycles, with the additional instruction cycle(s) executed
information in these 48 bits. In the second word, the as a NOP. Certain instructions that involve skipping over
eight MSbs are ‘0’s. If this second word is executed as the subsequent instruction require either two or three
an instruction (by itself), it executes as a NOP. cycles if the skip is performed, depending on whether
The double-word instructions execute in two instruction the instruction being skipped is a single-word or two-
cycles. word instruction. Moreover, double-word moves require
two cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the Note: For more details on the instruction set, refer
Program Counter is changed as a result of the to the “16-Bit MCU and DSC Programmer’s
instruction, or a PSV or Table Read is performed. In Reference Manual” (DS70000157).
TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field Description
#text Means literal defined by “text”

(text) Means “content of text”
[text] Means “the location addressed by text”
{} Optional field or operation
a  {b, c, d} a is selected from the set of values b, c, d
<n:m> Register bit field
.b Byte mode selection
.d Double-Word mode selection
.S Shadow register select
.w Word mode selection (default)
Acc One of two accumulators {A, B}
AWB Accumulator Write-Back Destination Address register {W13, [W13]+ = 2}
bit4 4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr Absolute address, label or expression (resolved by the linker)
f File register address {0x0000...0x1FFF}
lit1 1-bit unsigned literal {0,1}
lit4 4-bit unsigned literal {0...15}
lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit23 23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None Field does not require an entry, can be blank
OA, OB, SA, SB DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC Program Counter
Slit10 10-bit signed literal {-512...511}
Wb Base W register {W0...W15}
Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo Destination W register 
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn Dividend, Divisor Working register pair (Direct Addressing)

TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field Description
Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions 
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions 
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn One of 16 Working registers {W0...W15}
Wnd One of 16 Destination Working registers {W0...W15}
Wns One of 16 Source Working registers {W0...W15}
WREG W0 (Working register used in file register instructions)
Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso Source W register 
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx X Data Space Prefetch Address register for DSP instructions
 {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Wy Y Data Space Prefetch Address register for DSP instructions
 {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd Y Data Space Prefetch Destination register for DSP instructions {W4...W7}

TABLE 28-2: INSTRUCTION SET OVERVIEW
Base
Assembly # of # of Status Flags
Instr Assembly Syntax Description
Mnemonic Words Cycles(1) Affected
#
1 ADD ADD Acc Add Accumulators 1 1 OA,OB,SA,SB

ADD f f = f + WREG 1 1 C,DC,N,OV,Z
ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z
ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z
ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z
ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
ADD Wso,#Slit4,Acc 16-bit Signed Add to Accumulator 1 1 OA,OB,SA,SB
2 ADDC ADDC f f = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC f,WREG WREG = f + WREG + (C) 1 1 C,DC,N,OV,Z
ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C,DC,N,OV,Z
ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C,DC,N,OV,Z
3 AND AND f f = f .AND. WREG 1 1 N,Z
AND f,WREG WREG = f .AND. WREG 1 1 N,Z
AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N,Z
AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N,Z
AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N,Z
4 ASR ASR f f = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C,N,OV,Z
ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C,N,OV,Z
ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N,Z
ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N,Z
5 BCLR BCLR f,#bit4 Bit Clear f 1 1 None
BCLR Ws,#bit4 Bit Clear Ws 1 1 None
6 BOOTSWP BOOTSWP Swap the Active and Inactive Program 1 2 None
Flash Space
7 BRA BRA C,Expr Branch if Carry 1 1 (4) None
BRA GE,Expr Branch if Greater Than or Equal 1 1 (4) None
BRA GEU,Expr Branch if Unsigned Greater Than or Equal 1 1 (4) None
BRA GT,Expr Branch if Greater Than 1 1 (4) None
BRA GTU,Expr Branch if Unsigned Greater Than 1 1 (4) None
BRA LE,Expr Branch if Less Than or Equal 1 1 (4) None
BRA LEU,Expr Branch if Unsigned Less Than or Equal 1 1 (4) None
BRA LT,Expr Branch if Less Than 1 1 (4) None
BRA LTU,Expr Branch if Unsigned Less Than 1 1 (4) None
BRA N,Expr Branch if Negative 1 1 (4) None
BRA NC,Expr Branch if Not Carry 1 1 (4) None
BRA NN,Expr Branch if Not Negative 1 1 (4) None
BRA NOV,Expr Branch if Not Overflow 1 1 (4) None
BRA NZ,Expr Branch if Not Zero 1 1 (4) None
BRA OA,Expr Branch if Accumulator A Overflow 1 1 (4) None
BRA OB,Expr Branch if Accumulator B Overflow 1 1 (4) None
BRA OV,Expr Branch if Overflow 1 1 (4) None
BRA SA,Expr Branch if Accumulator A Saturated 1 1 (4) None
BRA SB,Expr Branch if Accumulator B Saturated 1 1 (4) None
BRA Expr Branch Unconditionally 1 4 None
BRA Z,Expr Branch if Zero 1 1 (4) None
BRA Wn Computed Branch 1 4 None
8 BSET BSET f,#bit4 Bit Set f 1 1 None
BSET Ws,#bit4 Bit Set Ws 1 1 None
Note 1: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.

TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
#
9 BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None

BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None
10 BTG BTG f,#bit4 Bit Toggle f 1 1 None
BTG Ws,#bit4 Bit Toggle Ws 1 1 None
11 BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None
(2 or 3)
BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None
(2 or 3)
12 BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None
(2 or 3)
BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None
(2 or 3)
13 BTST BTST f,#bit4 Bit Test f 1 1 Z
BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C
BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z
BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C
BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z
14 BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z
BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C
BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z
15 CALL CALL lit23 Call Subroutine 2 4 SFA
CALL Wn Call Indirect Subroutine 1 4 SFA
CALL.L Wn Call Indirect Subroutine (long address) 1 4 SFA
16 CLR CLR f f = 0x0000 1 1 None
CLR WREG WREG = 0x0000 1 1 None
CLR Ws Ws = 0x0000 1 1 None
CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Accumulator 1 1 OA,OB,SA,SB
17 CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO,Sleep
18 COM COM f f=f 1 1 N,Z
COM f,WREG WREG = f 1 1 N,Z
COM Ws,Wd Wd = Ws 1 1 N,Z
19 CP CP f Compare f with WREG 1 1 C,DC,N,OV,Z
CP Wb,#lit8 Compare Wb with lit8 1 1 C,DC,N,OV,Z
CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C,DC,N,OV,Z
20 CP0 CP0 f Compare f with 0x0000 1 1 C,DC,N,OV,Z
CP0 Ws Compare Ws with 0x0000 1 1 C,DC,N,OV,Z
21 CPB CPB f Compare f with WREG, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,#lit8 Compare Wb with lit8, with Borrow 1 1 C,DC,N,OV,Z
CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C,DC,N,OV,Z
(Wb – Ws – C)
22 CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None
(2 or 3)
CPBEQ CPBEQ Wb,Wn,Expr Compare Wb with Wn, Branch if = 1 1 (5) None
23 CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None
(2 or 3)
CPBGT CPBGT Wb,Wn,Expr Compare Wb with Wn, Branch if > 1 1 (5) None
24 CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None
(2 or 3)
CPBLT CPBLT Wb,Wn,Expr Compare Wb with Wn, Branch if < 1 1 (5) None
25 CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None
(2 or 3)
CPBNE CPBNE Wb,Wn,Expr Compare Wb with Wn, Branch if  1 1 (5) None

Base
#
26 CTXTSWP CTXTSWP #1it3 Switch CPU Register Context to Context 1 2 None

Defined by lit3
CTXTSWP Wn Switch CPU Register Context to Context 1 2 None
Defined by Wn
27 DAW DAW Wn Wn = Decimal Adjust Wn 1 1 C
28 DEC DEC f f=f–1 1 1 C,DC,N,OV,Z
DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z
DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z
29 DEC2 DEC2 f f=f–2 1 1 C,DC,N,OV,Z
DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z
DEC2 Ws,Wd Wd = Ws – 2 1 1 C,DC,N,OV,Z
30 DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None
31 DIV DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV
DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N,Z,C,OV
32 DIVF DIVF Wm,Wn Signed 16/16-bit Fractional Divide 1 18 N,Z,C,OV
33 DO DO #lit15,Expr Do Code to PC + Expr, lit15 + 1 Times 2 2 None
DO Wn,Expr Do Code to PC + Expr, (Wn) + 1 Times 2 2 None
34 ED ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance (no accumulate) 1 1 OA,OB,OAB,
SA,SB,SAB
35 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean Distance 1 1 OA,OB,OAB,
SA,SB,SAB
36 EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None
37 FBCL FBCL Ws,Wnd Find Bit Change from Left (MSb) Side 1 1 C
38 FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C
39 FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C
40 GOTO GOTO Expr Go to Address 2 4 None
GOTO Wn Go to Indirect 1 4 None
GOTO.L Wn Go to Indirect (long address) 1 4 None
41 INC INC f f=f+1 1 1 C,DC,N,OV,Z
INC f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
INC Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
42 INC2 INC2 f f=f+2 1 1 C,DC,N,OV,Z
INC2 f,WREG WREG = f + 2 1 1 C,DC,N,OV,Z
INC2 Ws,Wd Wd = Ws + 2 1 1 C,DC,N,OV,Z
43 IOR IOR f f = f .IOR. WREG 1 1 N,Z
IOR f,WREG WREG = f .IOR. WREG 1 1 N,Z
IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N,Z
IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N,Z
IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N,Z
44 LAC LAC Wso,#Slit4,Acc Load Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
45 LNK LNK #lit14 Link Frame Pointer 1 1 SFA
46 LSR LSR f f = Logical Right Shift f 1 1 C,N,OV,Z
LSR f,WREG WREG = Logical Right Shift f 1 1 C,N,OV,Z
LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C,N,OV,Z
LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N,Z
LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N,Z
47 MAC MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB Multiply and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB
MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate 1 1 OA,OB,OAB,
SA,SB,SAB

Base
#
48 MOV MOV f,Wn Move f to Wn 1 1 None

MOV f Move f to f 1 1 None
MOV f,WREG Move f to WREG 1 1 None
MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None
MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None
MOV Wn,f Move Wn to f 1 1 None
MOV Wso,Wdo Move Ws to Wd 1 1 None
MOV WREG,f Move WREG to f 1 1 None
MOV.D Wns,Wd Move Double from W(ns):W(ns + 1) to Wd 1 2 None
MOV.D Ws,Wnd Move Double from Ws to W(nd + 1):W(nd) 1 2 None
49 MOVPAG MOVPAG #lit10,DSRPAG Move 10-bit Literal to DSRPAG 1 1 None
MOVPAG #lit8,TBLPAG Move 8-bit Literal to TBLPAG 1 1 None
MOVPAGW Ws, DSRPAG Move Ws<9:0> to DSRPAG 1 1 None
MOVPAGW Ws, TBLPAG Move Ws<7:0> to TBLPAG 1 1 None
50 MOVSAC MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Prefetch and Store Accumulator 1 1 None
51 MPY MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
52 MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator 1 1 None
53 MSC MSC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB Multiply and Subtract from Accumulator 1 1 OA,OB,OAB,
SA,SB,SAB
54 MUL MUL.SS Wb,Ws,Wnd {Wnd + 1, Wnd} = Signed(Wb) * 1 1 None
Signed(Ws)
MUL.SS Wb,Ws,Acc Accumulator = Signed(Wb) * Signed(Ws) 1 1 None
MUL.SU Wb,Ws,Wnd {Wnd + 1, Wnd} = Signed(Wb) * 1 1 None
Unsigned(Ws)
MUL.SU Wb,Ws,Acc Accumulator = Signed(Wb) * 1 1 None
Unsigned(Ws)
MUL.SU Wb,#lit5,Acc Accumulator = Signed(Wb) * Unsigned(lit5) 1 1 None
MUL.US Wb,Ws,Wnd {Wnd + 1, Wnd} = Unsigned(Wb) * 1 1 None
Signed(Ws)
MUL.US Wb,Ws,Acc Accumulator = Unsigned(Wb) * 1 1 None
Signed(Ws)
MUL.UU Wb,Ws,Wnd {Wnd + 1, Wnd} = Unsigned(Wb) * 1 1 None
Unsigned(Ws)
MUL.UU Wb,#lit5,Acc Accumulator = Unsigned(Wb) * 1 1 None
Unsigned(lit5)
MUL.UU Wb,Ws,Acc Accumulator = Unsigned(Wb) * 1 1 None
Unsigned(Ws)
MULW.SS Wb,Ws,Wnd Wnd = Signed(Wb) * Signed(Ws) 1 1 None
MULW.SU Wb,Ws,Wnd Wnd = Signed(Wb) * Unsigned(Ws) 1 1 None
MULW.US Wb,Ws,Wnd Wnd = Unsigned(Wb) * Signed(Ws) 1 1 None
MULW.UU Wb,Ws,Wnd Wnd = Unsigned(Wb) * Unsigned(Ws) 1 1 None
MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = Signed(Wb) * 1 1 None
Unsigned(lit5)
MUL.SU Wb,#lit5,Wnd Wnd = Signed(Wb) * Unsigned(lit5) 1 1 None
MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = Unsigned(Wb) * 1 1 None
Unsigned(lit5)
MUL.UU Wb,#lit5,Wnd Wnd = Unsigned(Wb) * Unsigned(lit5) 1 1 None
MUL f W3:W2 = f * WREG 1 1 None

Base
#
55 NEG NEG Acc Negate Accumulator 1 1 OA,OB,OAB,

SA,SB,SAB
NEG f f=f+1 1 1 C,DC,N,OV,Z
NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z
NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z
56 NOP NOP No Operation 1 1 None
NOPR No Operation 1 1 None
57 POP POP f Pop f from Top-of-Stack (TOS) 1 1 None
POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None
POP.D Wnd Pop from Top-of-Stack (TOS) to 1 2 None
W(nd):W(nd + 1)
POP.S Pop Shadow Registers 1 1 All
58 PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None
PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None
PUSH.D Wns Push W(ns):W(ns + 1) to Top-of-Stack 1 2 None
(TOS)
PUSH.S Push Shadow Registers 1 1 None
59 PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO,Sleep
60 RCALL RCALL Expr Relative Call 1 4 SFA
RCALL Wn Computed Call 1 4 SFA
61 REPEAT REPEAT #lit15 Repeat Next Instruction lit15 + 1 Times 1 1 None
REPEAT Wn Repeat Next Instruction (Wn) + 1 Times 1 1 None
62 RESET RESET Software Device Reset 1 1 None
63 RETFIE RETFIE Return from Interrupt 1 6 (5) SFA
64 RETLW RETLW #lit10,Wn Return with Literal in Wn 1 6 (5) SFA
65 RETURN RETURN Return from Subroutine 1 6 (5) SFA
66 RLC RLC f f = Rotate Left through Carry f 1 1 C,N,Z
RLC f,WREG WREG = Rotate Left through Carry f 1 1 C,N,Z
RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C,N,Z
67 RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N,Z
RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N,Z
RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N,Z
68 RRC RRC f f = Rotate Right through Carry f 1 1 C,N,Z
RRC f,WREG WREG = Rotate Right through Carry f 1 1 C,N,Z
RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C,N,Z
69 RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N,Z
RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z
RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z
70 SAC SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None
SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator 1 1 None
71 SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C,N,Z
72 SETM SETM f f = 0xFFFF 1 1 None
SETM WREG WREG = 0xFFFF 1 1 None
SETM Ws Ws = 0xFFFF 1 1 None
73 SFTAC SFTAC Acc,Wn Arithmetic Shift Accumulator by (Wn) 1 1 OA,OB,OAB,
SA,SB,SAB
SFTAC Acc,#Slit6 Arithmetic Shift Accumulator by Slit6 1 1 OA,OB,OAB,
SA,SB,SAB

Base
#
74 SL SL f f = Left Shift f 1 1 C,N,OV,Z

SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z
SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z
SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z
SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z
75 SUB SUB Acc Subtract Accumulators 1 1 OA,OB,OAB,
SA,SB,SAB
SUB f f = f – WREG 1 1 C,DC,N,OV,Z
SUB f,WREG WREG = f – WREG 1 1 C,DC,N,OV,Z
SUB #lit10,Wn Wn = Wn – lit10 1 1 C,DC,N,OV,Z
SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C,DC,N,OV,Z
SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C,DC,N,OV,Z
76 SUBB SUBB f f = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB f,WREG WREG = f – WREG – (C) 1 1 C,DC,N,OV,Z
SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C,DC,N,OV,Z
SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C,DC,N,OV,Z
77 SUBR SUBR f f = WREG – f 1 1 C,DC,N,OV,Z
SUBR f,WREG WREG = WREG – f 1 1 C,DC,N,OV,Z
SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C,DC,N,OV,Z
SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C,DC,N,OV,Z
78 SUBBR SUBBR f f = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR f,WREG WREG = WREG – f – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C,DC,N,OV,Z
SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C,DC,N,OV,Z
79 SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None
SWAP Wn Wn = Byte Swap Wn 1 1 None
80 TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 5 None
81 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 5 None
82 TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None
83 TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None
84 ULNK ULNK Unlink Frame Pointer 1 1 SFA
85 XOR XOR f f = f .XOR. WREG 1 1 N,Z
XOR f,WREG WREG = f .XOR. WREG 1 1 N,Z
XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N,Z
XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N,Z
XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N,Z
86 ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C,Z,N

NOTES:

29.0 DEVELOPMENT SUPPORT 29.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

29.2 MPLAB XC Compilers 29.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16 and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
• Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
29.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
29.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

29.6 MPLAB X SIM Software Simulator 29.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the
buffer and logic analyzer display extend the power of MPLAB IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 29.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
29.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the
programs all 8, 16 and 32-bit MCU, and DSC devices target via a Microchip debug (RJ-11) connector (com-
with the easy-to-use, powerful graphical user interface of patible with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 29.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display
downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod-
significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

29.11 Demonstration/Development 29.12 Third-Party Development Tools
Boards, Evaluation Kits and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and • Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

30.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the dsPIC33EPXXXGS70X/80X family electrical characteristics. Additional
information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33EPXXXGS70X/80X family are listed below. Exposure to these maximum
rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any
other conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(1)

Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(3)..................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V(3) ................................................... -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(3) ................................................... -0.3V to +3.6V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2) ...........................................................................................................................300 mA
Maximum current sunk/sourced by any 4x I/O pin..................................................................................................15 mA
Maximum current sunk/sourced by any 8x I/O pin ..................................................................................................25 mA
Maximum current sunk by all ports(2) ....................................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those, or any other conditions
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.

30.1 DC Characteristics
TABLE 30-1: OPERATING MIPS vs. VOLTAGE

VDD Range Temperature Range Maximum MIPS
Characteristic
(in Volts) (in °C) dsPIC33EPXXXGS70X/80X Family
— 3.0V to 3.6V(1) -40°C to +85°C 70
— 3.0V to 3.6V(1) -40°C to +125°C 60
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators)
may have degraded performance. Device functionality is tested but not characterized. Refer to
Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
TABLE 30-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min. Typ. Max. Unit
Industrial Temperature Devices
Operating Junction Temperature Range TJ -40 — +125 °C
Operating Ambient Temperature Range TA -40 — +85 °C
Extended Temperature Devices
Operating Junction Temperature Range TJ -40 — +140 °C
Operating Ambient Temperature Range TA -40 — +125 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD –  IOH) PD PINT + PI/O W
I/O Pin Power Dissipation:
I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic Symbol Typ. Max. Unit Notes
Package Thermal Resistance, 80-Pin TQFP 12x12x1 mm JA 53.0 — °C/W 1
Package Thermal Resistance, 44-Pin QFN 8x8 mm JA 29.0 — °C/W 1
Package Thermal Resistance, 28-Pin QFN-S 6x6x0.9 mm JA 30.0 — °C/W 1
Package Thermal Resistance, 28-Pin UQFN 6x6x0.55 mm JA 26.0 — °C/W 1
Package Thermal Resistance, 28-Pin SOIC 7.50 mm JA 70.0 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.

TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
Operating Voltage
DC10 VDD Supply Voltage 3.0 — 3.6 V
(2)
DC12 VDR RAM Retention Voltage — — 1.95 V +25°C, +85°C, +125°C
— — 2.0 V -40°C
DC16 VPOR VDD Start Voltage — — VSS V
to Ensure Internal
Power-on Reset Signal
DC17 SVDD VDD Rise Rate 1.0 — — V/ms 0V-3V in 3 ms
to Ensure Internal
Power-on Reset Signal
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators) may
have degraded performance. Device functionality is tested but not characterized. Refer to
Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
2: This is the limit to which VDD may be lowered and the RAM contents will always be retained.
TABLE 30-5: FILTER CAPACITOR (CEFC) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated):
Param
Symbol Characteristics Min. Typ. Max. Units Comments
No.
CEFC External Filter Capacitor 4.7 — 10 F Capacitor must have a low
Value(1) series resistance (<1 Ohm)
Note 1: Typical VCAP Voltage = 1.8 volts when VDD  VDDMIN.

TABLE 30-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
(unless otherwise stated)
DC CHARACTERISTICS
Parameter
Typ. Max. Units Conditions
No.
Operating Current (IDD)(1)
DC20d 8 13 mA -40°C
DC20a 8 13 mA +25°C
3.3V 10 MIPS
DC20b 8 13 mA +85°C
DC20c 8 13 mA +125°C
DC22d 12 20 mA -40°C
DC22a 12 20 mA +25°C
3.3V 20 MIPS
DC22b 12 20 mA +85°C
DC22c 12 20 mA +125°C
DC24d 19 30 mA -40°C
DC24a 19 30 mA +25°C
3.3V 40 MIPS
DC24b 19 30 mA +85°C
DC24c 19 30 mA +125°C
DC25d 27 42 mA -40°C
DC25a 27 42 mA +25°C
3.3V 60 MIPS
DC25b 27 42 mA +85°C
DC25c 27 42 mA +125°C
DC26d 30 46 mA -40°C
DC26a 30 46 mA +25°C 3.3V 70 MIPS
DC26b 30 46 mA +85°C
DC27d 57 75 mA -40°C
70 MIPS
DC27a 57 75 mA +25°C 3.3V
(Note 2)
DC27b 57 75 mA +85°C
Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from
rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating or being clocked (all defined PMDx bits are set)
• CPU is executing while(1) statement
• JTAG is disabled
2: For this specification, the following test conditions apply:
• APLL clock is enabled
• All 8 PWMs enabled and operating at maximum speed (PTCON2<2:0> = 000), PTPER = 1000h,
50% duty cycle
• All other peripherals are disabled (corresponding PMDx bits are set)

TABLE 30-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS
Parameter
No.
Idle Current (IIDLE)(1)
DC40d 2 4 mA -40°C
DC40a 2 4 mA +25°C
3.3V 10 MIPS
DC40b 2 4 mA +85°C
DC40c 2 4 mA +125°C
DC42d 3 6 mA -40°C
DC42a 3 6 mA +25°C
3.3V 20 MIPS
DC42b 4 7 mA +85°C
DC42c 4 7 mA +125°C
DC44d 6 12 mA -40°C
DC44a 6 12 mA +25°C
3.3V 40 MIPS
DC44b 6 12 mA +85°C
DC44c 6 12 mA +125°C
DC45d 9 17 mA -40°C
DC45a 9 17 mA +25°C
3.3V 60 MIPS
DC45b 9 17 mA +85°C
DC45c 9 17 mA +125°C
DC46d 10 20 mA -40°C
DC46a 10 20 mA +25°C 3.3V 70 MIPS
DC46b 10 20 mA +85°C
Note 1: Base Idle current (IIDLE) is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• The NVMSIDL bit (NVMCON<12>) = 1 (i.e., Flash regulator is set to standby while the device is in Idle
mode)
• The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep mode)

TABLE 30-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Parameter
No.
Power-Down Current (IPD)(1)
DC60d 15 110 A -40°C
DC60a 20 150 A +25°C
3.3V
DC60b 150 500 A +85°C
DC60c 500 1200 A +125°C
Note 1: IPD (Sleep) current is measured as follows:
• CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• All peripheral modules are disabled (PMDx bits are all set)
• The VREGS bit (RCON<8>) = 0 (i.e., core regulator is set to standby while the device is in Sleep mode)
• The VREGSF bit (RCON<11>) = 0 (i.e., Flash regulator is set to standby while the device is in Sleep mode)
TABLE 30-9: DC CHARACTERISTICS: WATCHDOG TIMER DELTA CURRENT (IWDT)(1)

DC CHARACTERISTICS
Parameter No. Typ. Max. Units Conditions
DC61d 1 10 A -40°C
DC61a 1 10 A +25°C
3.3V
DC61b 2 17 A +85°C
DC61c 2 20 A +125°C
Note 1: The IWDT current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current. All parameters are characterized but not tested during manufacturing.

TABLE 30-10: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
DC CHARACTERISTICS
Doze
Parameter No. Typ. Max. Units Conditions
Ratio
Doze Current (IDOZE)(1)
DC73a(2) 20 40 1:2 mA
-40°C 3.3V FOSC = 140 MHz
DC73g 10 22 1:128 mA
DC70a(2) 20 40 1:2 mA
+25°C 3.3V FOSC = 140 MHz
DC70g 10 22 1:128 mA
DC71a(2) 20 40 1:2 mA
+85°C 3.3V FOSC = 140 MHz
DC71g 10 22 1:128 mA
DC72a(2) 20 40 1:2 mA
+125°C 3.3V FOSC = 120 MHz
DC72g 10 22 1:128 mA
Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
• Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CPU, SRAM, program memory and data memory are operational
• CPU is executing while(1) statement
2: These parameter are characterized but not tested in manufacturing.

TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Param
Symbol Characteristic Min. Typ.(1) Max. Units Conditions
No.
VIL Input Low Voltage
DI10 Any I/O Pin and MCLR VSS — 0.2 VDD V
DI18 I/O Pins with SDAx, SCLx VSS — 0.3 VDD V SMBus disabled
DI19 I/O Pins with SDAx, SCLx VSS — 0.8 V SMBus enabled
VIH Input High Voltage
DI20 I/O Pins Not 5V Tolerant(4) 0.8 VDD — VDD V
I/O Pins 5V Tolerant and 0.8 VDD — 5.5 V
MCLR(4)
5V Tolerant I/O Pins with 0.8 VDD — 5.5 V SMBus disabled
SDAx, SCLx(4)
5V Tolerant I/O Pins with 2.1 — 5.5 V SMBus enabled
SDAx, SCLx(4)
I/O Pins with SDAx, SCLx Not 0.8 VDD — VDD V SMBus disabled
5V Tolerant(4)
I/O Pins with SDAx, SCLx Not 2.1 — VDD V SMBus enabled
5V Tolerant(4)
DI30 ICNPU Input Change Notification 100 230 550 A VDD = 3.3V, VPIN = VSS
Pull-up Current
DI31 ICNPD Input Change Notification 100 230 400 A VDD = 3.3V, VPIN = VDD
Pull-Down Current(5)
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See the “Pin Diagrams” section for the 5V tolerant I/O pins.
5: VIL Source < (VSS – 0.3). Characterized but not tested.
6: VIH Source > (VDD + 0.3) for pins that are not 5V tolerant only.
7: Digital 5V tolerant pins do not have internal high-side diodes to VDD and cannot tolerate any “positive”
input injection current.
8: | Injection Currents | > 0 can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.

TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Param
No.
IIL Input Leakage Current(2,3)
DI50 I/O Pins 5V Tolerant(4) -1 — +1 A VSS  VPIN  VDD,
pin at high-impedance
DI51 I/O Pins Not 5V Tolerant(4) -1 — +1 A VSS  VPIN  VDD,
pin at high-impedance,
-40°C  TA  +85°C
DI51a I/O Pins Not 5V Tolerant(4) -1 — +1 A Analog pins shared with
external reference pins,
-40°C  TA  +85°C
DI51b I/O Pins Not 5V Tolerant(4) -1 — +1 A VSS  VPIN  VDD,
pin at high-impedance,
-40°C  TA  +125°C
DI51c I/O Pins Not 5V Tolerant(4) -1 — +1 A Analog pins shared with
external reference pins,
-40°C  TA  +125°C
DI55 MCLR -5 — +5 A VSS VPIN VDD
DI56 OSC1 -5 — +5 A VSS VPIN VDD,
XT and HS modes
voltages.

TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Param
No.
DI60a IICL Input Low Injection Current 0 — -5(5,8) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP
and RB7
DI60b IICH Input High Injection Current 0 — +5(6,7,8) mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB7 and all 5V tolerant
pins(7)
DI60c IICT Total Input Injection Current -20(9) — +20(9) mA Absolute instantaneous
(sum of all I/O and control sum of all ± input injection
pins) currents from all I/O pins
( | IICL | + | IICH | )  IICT
voltages.

TABLE 30-12: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
DC CHARACTERISTICS
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
DO10 VOL Output Low Voltage — — 0.4 V VDD = 3.3V,
4x Sink Driver Pins(2) IOL  6 mA, -40°C  TA  +85°C,
IOL  5 mA, +85°C  TA  +125°C
Output Low Voltage — — 0.4 V VDD = 3.3V,
8x Sink Driver Pins(3) IOL  12 mA, -40°C  TA  +85°C,
IOL  8 mA, +85°C  TA  +125°C
DO20 VOH Output High Voltage 2.4 — — V IOH  -10 mA, VDD = 3.3V
4x Source Driver Pins(2)
Output High Voltage 2.4 — — V IOH  -15 mA, VDD = 3.3V
8x Source Driver Pins(3)
DO20A VOH1 Output High Voltage 1.5(1) — — V IOH  -14 mA, VDD = 3.3V
4x Source Driver Pins(2) 2.0 (1) — — IOH  -12 mA, VDD = 3.3V
3.0(1) — — IOH  -7 mA, VDD = 3.3V
Output High Voltage 1.5(1) — — V IOH  -22 mA, VDD = 3.3V
8x Source Driver Pins(3) 2.0(1) — — IOH  -18 mA, VDD = 3.3V
3.0(1) — — IOH  -10 mA, VDD = 3.3V
Note 1: Parameters are characterized but not tested.
2: Includes RA0-RA2, RB0-RB1, RB9, RC1-RC2, RC9-RC10, RC12, RD7, RD8, RE4-RE5, RE8-RE9 and
RE12-RE13 pins.
3: Includes all I/O pins that are not 4x driver pins (see Note 2).
TABLE 30-13: ELECTRICAL CHARACTERISTICS: BOR

DC CHARACTERISTICS
Param
Symbol Characteristic Min.(2) Typ. Max. Units Conditions
No.
BO10 VBOR BOR Event on VDD Transition 2.65 — 2.95 V VDD (Notes 2 and 3)
High-to-Low
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, PGAs and comparators) may have degraded
performance.
2: Parameters are for design guidance only and are not tested in manufacturing.
3: The VBOR specification is relative to VDD.

TABLE 30-14: DC CHARACTERISTICS: PROGRAM MEMORY

DC CHARACTERISTICS
Param
No.
Program Flash Memory
D130 EP Cell Endurance 10,000 — — E/W -40C to +125C
D131 VPR VDD for Read 3.0 — 3.6 V
D132b VPEW VDD for Self-Timed Write 3.0 — 3.6 V
D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications
are violated, -40C to +125C
D135 IDDP Supply Current during — 10 — mA
Programming(2)
D136 IPEAK Instantaneous Peak Current — — 150 mA
During Start-up
D137a TPE Page Erase Time 19.7 — 20.1 ms TPE = 146893 FRC cycles,
TA = +85°C (Note 3)
D137b TPE Page Erase Time 19.5 — 20.3 ms TPE = 146893 FRC cycles,
TA = +125°C (Note 3)
D138a TWW Word Write Cycle Time 46.5 — 47.3 µs TWW = 346 FRC cycles,
TA = +85°C (Note 3)
D138b TWW Word Write Cycle Time 46.0 — 47.9 µs TWW = 346 FRC cycles,
TA = +125°C (Note 3)
D139a TRW Row Write Time 667 — 679 µs TRW = 4965 FRC cycles,
TA = +85°C (Note 3)
D139b TRW Row Write Time 660 — 687 µs TRW = 4965 FRC cycles,
TA = +125°C (Note 3)
2: Parameter characterized but not tested in manufacturing.
3: Other conditions: FRC = 7.37 MHz, TUN<5:0> = 011111 (for Minimum), TUN<5:0> = 100000 (for
Maximum). This parameter depends on the FRC accuracy (see Table 30-20) and the value of the FRC
Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and
Maximum time, see Section 5.3 “Programming Operations”.

30.2 AC Characteristics and Timing
Parameters
This section defines the dsPIC33EPXXXGS70X/80X
family AC characteristics and timing parameters.
TABLE 30-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial
Operating voltage VDD range as described in Section 30.1 “DC Characteristics”.
FIGURE 30-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2
VDD/2
RL Pin CL
VSS
CL
Pin RL = 464
CL = 50 pF for all pins except OSC2
VSS 15 pF for OSC2 output
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param
No.
DO50 COSCO OSC2 Pin — — 15 pF In XT and HS modes, when
external clock is used to drive
OSC1
DO56 CIO All I/O Pins and OSC2 — — 50 pF EC mode
DO58 CB SCLx, SDAx — — 400 pF In I2C mode

FIGURE 30-2: EXTERNAL CLOCK TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
OS20
OS30 OS30 OS31 OS31
OS25
CLKO
OS41 OS40
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
Sym Characteristic Min. Typ.(1) Max. Units Conditions
No.
OS10 FIN External CLKI Frequency DC — 60 MHz EC
(External clocks allowed only
in EC and ECPLL modes)
Oscillator Crystal Frequency 3.5 — 10 MHz XT
10 — 40 MHz HS
OS20 TOSC TOSC = 1/FOSC 8.33 — DC ns +125°C
TOSC = 1/FOSC 7.14 — DC ns +85°C
OS25 TCY Instruction Cycle Time(2) 16.67 — DC ns +125°C
Instruction Cycle Time(2) 14.28 — DC ns +85°C
OS30 TosL, External Clock in (OSC1) 0.45 x TOSC — 0.55 x TOSC ns EC
TosH High or Low Time
OS31 TosR, External Clock in (OSC1) — — 20 ns EC
TosF Rise or Fall Time
OS40 TckR CLKO Rise Time(3,4) — 5.2 — ns
(3,4)
OS41 TckF CLKO Fall Time — 5.2 — ns
OS42 GM External Oscillator — 12 — mA/V HS, VDD = 3.3V,
Transconductance(4) TA = +25°C
— 6 — mA/V XT, VDD = 3.3V,
TA = +25°C
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at
“Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used,
the “Maximum” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: This parameter is characterized but not tested in manufacturing.

TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Param
No.
OS50 FPLLI PLL Voltage Controlled Oscillator 0.8 — 8.0 MHz ECPLL, XTPLL modes
(VCO) Input Frequency Range
OS51 FVCO On-Chip VCO System Frequency 120 — 340 MHz
OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 ms
(2)
OS53 DCLK CLKO Stability (Jitter) -3 0.5 3 %
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases, or communication clocks used by the application, use the following formula:
D CLK
Effective Jitter = -------------------------------------------------------------------------------------------
F OSC
---------------------------------------------------------------------------------------
Time Base or Communication Clock
For example, if FOSC = 120 MHz and the SPIx bit rate = 10 MHz, the effective jitter is as follows:
D CLK D CLK D CLK
Effective Jitter = -------------- = -------------- = --------------
120 12 3.464
---------
10
TABLE 30-19: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS

AC CHARACTERISTICS
Param
Symbol Characteristic Min Typ(1) Max Units Conditions
No.
OS56 FHPOUT On-Chip 16x PLL CCO 112 118 120 MHz
Frequency
OS57 FHPIN On-Chip 16x PLL Phase 7.0 7.37 7.5 MHz
Detector Input Frequency
OS58 TSU Frequency Generator Lock — — 10 µs
Time
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.

TABLE 30-20: INTERNAL FRC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Param
Characteristic Min. Typ. Max. Units Conditions
No.
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a FRC -2 0.5 +2 % -40°C  TA -10°C VDD = 3.0-3.6V
-0.9 0.5 +0.9 % -10°C  TA +85°C VDD = 3.0-3.6V
F20b FRC -2 1 +2 % +85°C  TA  +125°C VDD = 3.0-3.6V
Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
TABLE 30-21: INTERNAL LPRC ACCURACY

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Param
Characteristic Min. Typ. Max. Units Conditions
No.
LPRC @ 32.768 kHz(1)
F21a LPRC -30 — +30 % -40°C  TA  -10°C VDD = 3.0-3.6V
-20 — +20 % -10°C  TA  +85°C VDD = 3.0-3.6V
F21b LPRC -30 — +30 % +85°C  TA  +125°C VDD = 3.0-3.6V
Note 1: This is the change of the LPRC frequency as VDD changes.

FIGURE 30-3: I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
Old Value New Value
(Output)
DO31
DO32
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-22: I/O TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
DO31 TIOR Port Output Rise Time — 5 10 ns
DO32 TIOF Port Output Fall Time — 5 10 ns
DI35 TINP INTx Pin High or Low Time (input) 20 — — ns
DI40 TRBP CNx High or Low Time (input) 2 — — TCY
FIGURE 30-4: BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS
MCLR
TMCLR
(SY20)
BOR
TBOR Various Delays (depending on configuration)

(SY30)
Reset Sequence
CPU Starts Fetching Code

TABLE 30-23: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions
No.
SY00 TPU Power-up Period — 400 600 µs
SY10 TOST Oscillator Start-up Time — 1024 TOSC — — TOSC = OSC1 period
SY12 TWDT Watchdog Timer 0.81 — 1.22 ms WDTPRE = 0,
Time-out Period WDTPOST<3:0> = 0000,
using LPRC tolerances indicated in
F21 (see Table 30-21) at +85°C
3.25 — 4.88 ms WDTPRE = 1,
WDTPOST<3:0> = 0000,
using LPRC tolerances indicated in
F21 (see Table 30-21) at +85°C
SY13 TIOZ I/O High-Impedance from 0.68 0.72 1.2 µs
MCLR Low or Watchdog
Timer Reset
SY20 TMCLR MCLR Pulse Width (low) 2 — — µs
SY30 TBOR BOR Pulse Width (low) 1 — — µs
SY35 TFSCM Fail-Safe Clock Monitor — 500 900 µs -40°C to +85°C
Delay
SY36 TVREG Voltage Regulator — — 30 µs
Standby-to-Active mode
Transition Time
SY37 TOSCDFRC FRC Oscillator Start-up — 48 — µs
Delay
SY38 TOSCDLPRC LPRC Oscillator Start-up — — 70 µs
Delay
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

FIGURE 30-5: TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10 Tx11
Tx15 Tx20
OS60
TMRx
TABLE 30-24: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

AC CHARACTERISTICS
Param
Symbol Characteristic(2) Min. Typ. Max. Units Conditions
No.
TA10 TTXH T1CK High Synchronous mode Greater of: — — ns Must also meet
Time 20 or Parameter TA15,
(TCY + 20)/N N = Prescale Value
(1, 8, 64, 256)
Asynchronous mode 35 — — ns
TA11 TTXL T1CK Low Synchronous mode Greater of: — — ns Must also meet
Time 20 or Parameter TA15,
(1, 8, 64, 256)
Asynchronous mode 10 — — ns
TA15 TTXP T1CK Input Synchronous mode Greater of: — — ns N = Prescale Value
Period 40 or (1, 8, 64, 256)
(2 TCY + 40)/N
OS60 Ft1 T1CK Oscillator Input Frequency DC — 50 kHz
Range (oscillator enabled by
setting bit, TCS (T1CON<1>))
TA20 TCKEXTMRL Delay from External T1CK Clock 0.75 TCY + 40 — 1.75 TCY + 40 ns
Edge to Timer Increment
Note 1: Timer1 is a Type A timer.
2: These parameters are characterized but not tested in manufacturing.

TABLE 30-25: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
TB10 TtxH TxCK High Synchronous mode Greater of: — — ns Must also meet
Time 20 or Parameter TB15,
(1, 8, 64, 256)
TB11 TtxL TxCK Low Synchronous mode Greater of: — — ns Must also meet
Time 20 or Parameter TB15,
(1, 8, 64, 256)
TB15 TtxP TxCK Input Synchronous mode Greater of: — — ns N = Prescale Value
Period 40 or (1, 8, 64, 256)
(2 TCY + 40)/N
TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns
Clock Edge to Timer Increment
TABLE 30-26: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
No.
TC10 TtxH TxCK High Synchronous TCY + 20 — — ns Must also meet
Time Parameter TC15
TC11 TtxL TxCK Low Synchronous TCY + 20 — — ns Must also meet
Time Parameter TC15
TC15 TtxP TxCK Input Synchronous 2 TCY + 40 — — ns N = Prescale Value
Period with Prescaler (1, 8, 64, 256)
TC20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40 — 1.75 TCY + 40 ns
Clock Edge to Timer Increment

FIGURE 30-6: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10 IC11
IC15
TABLE 30-27: INPUT CAPTURE x MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param.
Symbol Characteristics(1) Min. Max. Units Conditions
No.
IC10 TCCL ICx Input Low Time Greater of: — ns Must also meet
12.5 + 25 or Parameter IC15
(0.5 TCY/N) + 25
IC11 TCCH ICx Input High Time Greater of: — ns Must also meet
N = Prescale Value
12.5 + 25 or Parameter IC15
(1, 4, 16)
(0.5 TCY/N) + 25
IC15 TCCP ICx Input Period Greater of: — ns
25 + 50 or
(1 TCY/N) + 50

FIGURE 30-7: OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11 OC10
TABLE 30-28: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32
OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31
FIGURE 30-8: OCx/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
TABLE 30-29: OCx/PWMx MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
OC15 TFD Fault Input to PWMx I/O Change — — TCY + 20 ns
OC20 TFLT Fault Input Pulse Width TCY + 20 — — ns

FIGURE 30-9: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
Fault Input
(active-low)
MP20
PWMx
FIGURE 30-10: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
TABLE 30-30: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
MP10 TFPWM PWMx Output Fall Time — — — ns See Parameter DO32
MP11 TRPWM PWMx Output Rise Time — — — ns See Parameter DO31
MP20 TFD Fault Input  to PWMx — — 15 ns
I/O Change
MP30 TFH Fault Input Pulse Width 15 — — ns

TABLE 30-31: SPI1, SPI2 AND SPI3 MAXIMUM DATA/CLOCK RATE SUMMARY(1)
AC CHARACTERISTICS
Master Master Slave
Maximum
Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP
Data Rate
(Half-Duplex) (Full-Duplex) (Full-Duplex)
15 MHz Table 30-32 — — 0,1 0,1 0,1
9 MHz — Table 30-33 — 1 0,1 1
9 MHz — Table 30-34 — 0 0,1 1
15 MHz — — Table 30-35 1 0 0
11 MHz — — Table 30-36 1 1 0
15 MHz — — Table 30-37 0 1 0
11 MHz — — Table 30-38 0 0 0
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
FIGURE 30-11: SPI1, SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY,
CKE = 0) TIMING CHARACTERISTICS(1,2)
SCKx
(CKP = 0)
SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP20 SP21
SDOx MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP30, SP31
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices with

a remappable SCK3 pin.
2: Refer to Figure 30-1 for load conditions.

FIGURE 30-12: SPI1, SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY,
CKE = 1) TIMING CHARACTERISTICS(1,2)
SP36
SCKx
(CKP = 0)
SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP20 SP21
SP30, SP31

TABLE 30-32: SPI1, SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY)
TIMING REQUIREMENTS(5)
AC CHARACTERISTICS
Param. Symbol Characteristic(1) Min. Typ.(2) Max. Units Conditions
SP10 FscP Maximum SCKx Frequency — — 15 MHz (Note 3)
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDOx Data Output Valid after — 6 20 ns
TscL2doV SCKx Edge
SP36 TdiV2scH, SDOx Data Output Setup to 30 — — ns
TdiV2scL First SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
5: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices

FIGURE 30-13: SPI1, SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x,
SMP = 1) TIMING CHARACTERISTICS(1,2)
SP36
SCKx
(CKP = 0)
SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP20 SP21
SP40 SP30, SP31
SDIx MSb In Bit 14 - - - -1 LSb In

SP41
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05

devices with a remappable SCK3 pin.
TABLE 30-33: SPI1, SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
AC CHARACTERISTICS
SP10 FscP Maximum SCKx Frequency — — 9 MHz (Note 3)
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 (Note 4)
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 (Note 4)
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 (Note 4)
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 (Note 4)
TscL2doV SCKx Edge
SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns
TdoV2scL First SCKx Edge
SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns
TdiV2scL Input to SCKx Edge
SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns
TscL2diL to SCKx Edge
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.

FIGURE 30-14: SPI1, SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x,
SMP = 1) TIMING CHARACTERISTICS(1,2)
SCKx
(CKP = 0)
SP10 SP21 SP20
SCKx
(CKP = 1)
SP35 SP36 SP20 SP21
SP30, SP31 SP30, SP31
SP40 SP41

TABLE 30-34: SPI1, SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
AC CHARACTERISTICS
SP10 FscP Maximum SCKx Frequency — — 9 MHz -40ºC to +125ºC (Note 3)
SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 (Note 4)
SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 (Note 4)
SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 (Note 4)
SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 (Note 4)
TscL2doV SCKx Edge
SP36 TdoV2scH, SDOx Data Output Setup to 30 — — ns
SP40 TdiV2scH, Setup Time of SDIx Data 30 — — ns
TdiV2scL Input to SCKx Edge
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.

FIGURE 30-15: SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS(1,2)
SP60
SSx
SP50 SP52
SCKx
(CKP = 0)
SP70 SP73 SP72
SCKx
(CKP = 1) SP36
SP35 SP72 SP73
SP30, SP31 SP51
SDIx
MSb In Bit 14 - - - -1 LSb In
SP41
SP40


TABLE 30-35: SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
AC CHARACTERISTICS
SP70 FscP Maximum SCKx Input Frequency — — 15 MHz (Note 3)
SP72 TscF SCKx Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCKx Input Rise Time — — — ns See Parameter DO31
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCKx Edge
SP40 TdiV2scH, Setup Time of SDIx Data Input 30 — — ns
TdiV2scL to SCKx Edge
SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns
TssL2scL Input
SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns (Note 4)
High-Impedance
SP52 TscH2ssH SSx after SCKx Edge 1.5 TCY + 40 — — ns (Note 4)
TscL2ssH
SP60 TssL2doV SDOx Data Output Valid after — — 50 ns
SSx Edge
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.

SP60
SSx
SP50 SP52
SCKx
(CKP = 0)
SP70 SP73 SP72
SCKx
(CKP = 1) SP36
SP35
SP72 SP73
SP30, SP31 SP51
SDIx
SP41
SP40


AC CHARACTERISTICS
(Note 4)
(Note 4
(Note 4)
(Note 4)
TscL2doV SCKx Edge
TssL2scL Input
High-Impedance
TscL2ssH
SP60 TssL2doV SDOx Data Output Valid after — — 50 ns
SSx Edge
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not

SSx
SP50 SP52
SCKx
(CKP = 0)
SP70 SP73 SP72
SCKx
(CKP = 1)
SP72 SP73
SP35 SP36
SDOx
MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SP41
SP40


AC CHARACTERISTICS
(Note 4)
(Note 4
(Note 4)
(Note 4)
TscL2doV SCKx Edge
TssL2scL Input
High-Impedance
TscL2ssH
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must

SSx
SP50 SP52
SCKx
(CKP = 0)
SP70 SP73 SP72
SCKx
(CKP = 1)
SP72 SP73
SP35 SP36
SP30, SP31 SP51

SP41
SP40


AC CHARACTERISTICS
(Note 4)
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCKx Edge
TssL2scL Input
High-Impedance
TscL2ssH
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not

TABLE 30-39: SPI3 MAXIMUM DATA/CLOCK RATE SUMMARY(1)
AC CHARACTERISTICS
Master Master Slave
Maximum
Transmit Only Transmit/Receive Transmit/Receive CKE CKP SMP
Data Rate
(Half-Duplex) (Full-Duplex) (Full-Duplex)
25 MHz Table 30-40 — — 0,1 0,1 0,1
25 MHz — Table 30-41 — 1 0,1 1
25 MHz — Table 30-42 — 0 0,1 1
25 MHz — — Table 30-43 1 0 0
25 MHz — — Table 30-44 1 1 0
25 MHz — — Table 30-45 0 1 0
25 MHz — — Table 30-46 0 0 0
Note 1: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
FIGURE 30-19: SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)

SCK3
(CKP = 0)
SP10 SP21 SP20
SCK3
(CKP = 1)
SP35 SP20 SP21
SDO3 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP30, SP31

FIGURE 30-20: SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
SP36
SCK3
(CKP = 0)
SP10 SP21 SP20
SCK3
(CKP = 1)
SP35 SP20 SP21
SDO3 MSb Bit 14 - - - - - -1 LSb
SP30, SP31
TABLE 30-40: SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS(5)
AC CHARACTERISTICS
SP10 FscP Maximum SCK3 Frequency — — 25 MHz (Note 3)
SP20 TscF SCK3 Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP21 TscR SCK3 Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP30 TdoF SDO3 Data Output Fall Time — — — ns See Parameter DO32
(Note 4)
SP31 TdoR SDO3 Data Output Rise Time — — — ns See Parameter DO31
(Note 4)
SP35 TscH2doV, SDO3 Data Output Valid after — 6 20 ns
TscL2doV SCK3 Edge
SP36 TdiV2scH, SDO3 Data Output Setup to 20 — — ns
TdiV2scL First SCK3 Edge
3: The minimum clock period for SCK3 is 66.7 ns. Therefore, the clock generated in Master mode must not
4: Assumes 50 pF load on all SPI3 pins.
5: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.

FIGURE 30-21: SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
SP36
SCK3
(CKP = 0)
SP10 SP21 SP20
SCK3
(CKP = 1)
SP35 SP20 SP21
SDO3 MSb Bit 14 - - - - - -1 LSb
SP30, SP31
SP40
SDI3 MSb In Bit 14 - - - -1 LSb In

SP41
TABLE 30-41: SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)

AC CHARACTERISTICS
SP10 FscP Maximum SCK3 Frequency — — 25 MHz (Note 3)
SP20 TscF SCK3 Output Fall Time — — — ns See Parameter DO32 (Note 4)
SP21 TscR SCK3 Output Rise Time — — — ns See Parameter DO31 (Note 4)
SP30 TdoF SDO3 Data Output Fall Time — — — ns See Parameter DO32 (Note 4)
SP31 TdoR SDO3 Data Output Rise Time — — — ns See Parameter DO31 (Note 4)
TscL2doV SCK3 Edge
SP36 TdoV2sc, SDO3 Data Output Setup to 20 — — ns
TdoV2scL First SCK3 Edge
SP40 TdiV2scH, Setup Time of SDI3 Data 20 — — ns
TdiV2scL Input to SCK3 Edge
SP41 TscH2diL, Hold Time of SDI3 Data Input 15 — — ns
TscL2diL to SCK3 Edge
3: The minimum clock period for SCK3 is 100 ns. The clock generated in Master mode must not violate this
specification.

FIGURE 30-22: SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
SCK3
(CKP = 0)
SP10 SP21 SP20
SCK3
(CKP = 1)
SP35 SP36 SP20 SP21
SDO3 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP30, SP31
SD3 MSb In Bit 14 - - - -1 LSb In
SP40 SP41
TABLE 30-42: SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)

AC CHARACTERISTICS
SP10 FscP Maximum SCK3 Frequency — — 25 MHz -40ºC to +125ºC (Note 3)
SP20 TscF SCK3 Output Fall Time — — — ns See Parameter DO32 (Note 4)
SP21 TscR SCK3 Output Rise Time — — — ns See Parameter DO31 (Note 4)
SP30 TdoF SDO3 Data Output Fall Time — — — ns See Parameter DO32 (Note 4)
SP31 TdoR SDO3 Data Output Rise Time — — — ns See Parameter DO31 (Note 4)
TscL2doV SCK3 Edge
SP36 TdoV2scH, SDO3 Data Output Setup to 20 — — ns
SP40 TdiV2scH, Setup Time of SDI3 Data 20 — — ns
TdiV2scL Input to SCK3 Edge
TscL2diL to SCK3Edge
3: The minimum clock period for SCK3 is 100 ns. The clock generated in Master mode must not violate this
specification.

FIGURE 30-23: SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
SP60
SS3
SP50 SP52
SCK3
(CKP = 0)
SP70 SP73 SP72
SCK3
(CKP = 1) SP36
SP35
SP72 SP73
SDO3 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SDI3
SP41
SP40

TABLE 30-43: SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
AC CHARACTERISTICS
SP70 FscP Maximum SCK3 Input Frequency — — 25 MHz (Note 3)
SP72 TscF SCK3 Input Fall Time — — — ns See Parameter DO32
(Note 4)
SP73 TscR SCK3 Input Rise Time — — — ns See Parameter DO31
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCK3 Edge
SP40 TdiV2scH, Setup Time of SDI3 Data Input 20 — — ns
TdiV2scL to SCK3 Edge
SP50 TssL2scH, SS3  to SCK3  or SCK3  120 — — ns
TssL2scL Input
SP51 TssH2doZ SS3  to SDO3 Output 10 — 50 ns (Note 4)
High-Impedance
SP52 TscH2ssH SS3 after SCK3 Edge 1.5 TCY + 40 — — ns (Note 4)
TscL2ssH
SP60 TssL2doV SDO3 Data Output Valid after — — 50 ns
SS3 Edge
3: The minimum clock period for SCK3 is 66.7 ns. Therefore, the SCK3 clock generated by the master must

SP60
SS3
SP50 SP52
SCK3
(CKP = 0)
SP70 SP73 SP72
SCK3
(CKP = 1) SP36
SP35
SP72 SP73
SDO3 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SP41
SP40

AC CHARACTERISTICS
(Note 4)
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCK3 Edge
TssL2scL Input
High-Impedance
SP52 TscH2ssH, SS3 after SCK3 Edge 1.5 TCY + 40 — — ns (Note 4)
TscL2ssH
SP60 TssL2doV SDO3 Data Output Valid after — — 50 ns
SS3 Edge
3: The minimum clock period for SCK3 is 91 ns. Therefore, the SCK3 clock generated by the master must

SS3
SP50 SP52
SCK3
(CKP = 0)
SP70 SP73 SP72
SCK3
(CKP = 1)
SP72 SP73
SP35 SP36
SDO3 MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SP41
SP40

AC CHARACTERISTICS
(Note 4)
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCK3 Edge
TssL2scL Input
High-Impedance
TscL2ssH
3: The minimum clock period for SCK3 is 66.7 ns. Therefore, the SCK3 clock generated by the master must

SS3
SP50 SP52
SCK3
(CKP = 0)
SP70 SP73 SP72
SCK3
(CKP = 1)
SP72 SP73
SP35 SP36
SDO3
MSb Bit 14 - - - - - -1 LSb
SP30, SP31 SP51

SP41
SP40

AC CHARACTERISTICS
(Note 4)
(Note 4)
(Note 4)
(Note 4)
TscL2doV SCK3 Edge
TssL2scL Input
High-Impedance
TscL2ssH
3: The minimum clock period for SCK3 is 91 ns. Therefore, the SCK3 clock generated by the master must

FIGURE 30-27: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31 IM34
IM30 IM33
SDAx
Start Stop
Condition Condition
FIGURE 30-28: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20 IM11 IM21

IM10
SCLx
IM26
IM11
IM25
IM10 IM33
SDAx
In
IM40 IM40 IM45
SDAx
Out

TABLE 30-47: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
AC CHARACTERISTICS
Param
Symbol Characteristic(4) Min.(1) Max. Units Conditions
No.
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2) — µs
400 kHz mode TCY/2 (BRG + 2) — µs
(2)
1 MHz mode TCY/2 (BRG + 2) — µs
IM11 THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2) — µs
400 kHz mode TCY/2 (BRG + 2) — µs
1 MHz mode(2) TCY/2 (BRG + 2) — µs
IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode(2) — 100 ns
IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
IM25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
(2)
1 MHz mode 40 — ns
IM26 THD:DAT Data Input 100 kHz mode 0 — µs
Hold Time 400 kHz mode 0 0.9 µs
1 MHz mode(2) 0.2 — µs
IM30 TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) — µs Only relevant for
Setup Time 400 kHz mode TCY/2 (BRG + 2) — µs Repeated Start
1 MHz mode(2) TCY/2 (BRG + 2) — µs condition
IM31 THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 2) — µs After this period, the
Hold Time 400 kHz mode TCY/2 (BRG +2) — µs first clock pulse is
1 MHz mode(2) TCY/2 (BRG + 2) — µs generated
IM33 TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — µs
Setup Time 400 kHz mode TCY/2 (BRG + 2) — µs
1 MHz mode (2)
TCY/2 (BRG + 2) — µs
IM34 THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2) — µs
Hold Time 400 kHz mode TCY/2 (BRG + 2) — µs
1 MHz mode(2) TCY/2 (BRG + 2) — µs
IM40 TAA:SCL Output Valid 100 kHz mode — 3500 ns
from Clock 400 kHz mode — 1000 ns
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — µs Time the bus must be
400 kHz mode 1.3 — µs free before a new
1 MHz mode(2) 0.5 — µs transmission can start
IM50 CB Bus Capacitive Loading — 400 pF
IM51 TPGD Pulse Gobbler Delay 65 390 ns (Note 3)
Note 1: 2
BRG is the value of the I C Baud Rate Generator.
2: Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.

FIGURE 30-29: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31 IS34
IS30 IS33
SDAx
Start Stop
Condition Condition
FIGURE 30-30: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20 IS11 IS21

IS10
SCLx
IS30 IS26
IS31 IS25 IS33
SDAx
In
IS40 IS40 IS45
SDAx
Out

TABLE 30-48: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
AC CHARACTERISTICS
Param
Symbol Characteristic(3) Min. Max. Units Conditions
No.
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — µs
400 kHz mode 1.3 — µs
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — µs Device must operate at a
minimum of 10 MHz
IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode (1)
— 100 ns
IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
IS25 TSU:DAT Data Input 100 kHz mode 250 — ns
Setup Time 400 kHz mode 100 — ns
1 MHz mode(1) 100 — ns
IS26 THD:DAT Data Input 100 kHz mode 0 — µs
Hold Time 400 kHz mode 0 0.9 µs
1 MHz mode(1) 0 0.3 µs
IS30 TSU:STA Start Condition 100 kHz mode 4.7 — µs Only relevant for Repeated
Setup Time 400 kHz mode 0.6 — µs Start condition
(1)
1 MHz mode 0.25 — µs
IS31 THD:STA Start Condition 100 kHz mode 4.0 — µs After this period, the first
Hold Time 400 kHz mode 0.6 — µs clock pulse is generated
1 MHz mode(1) 0.25 — µs
IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — µs
Setup Time 400 kHz mode 0.6 — µs
IS34 THD:STO Stop Condition 100 kHz mode 4 — µs
Hold Time 400 kHz mode 0.6 — µs
1 MHz mode(1) 0.25 µs
IS40 TAA:SCL Output Valid from 100 kHz mode 0 3500 ns
Clock 400 kHz mode 0 1000 ns
1 MHz mode (1)
0 350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — µs Time the bus must be free
400 kHz mode 1.3 — µs before a new transmission
1 MHz mode(1) 0.5 — µs can start
IS50 CB Bus Capacitive Loading — 400 pF
IS51 TPGD Pulse Gobbler Delay 65 390 ns (Note 2)
Note 1: Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: Typical value for this parameter is 130 ns.

FIGURE 30-31: CANx MODULE I/O TIMING CHARACTERISTICS
CxTX Pin Old Value New Value

(output)
CA10 CA11
CxRX Pin
(input)
CA20
TABLE 30-49: CANx MODULE I/O TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
No.
CA10 TIOF Port Output Fall Time — — — ns See Parameter DO32
CA11 TIOR Port Output Rise Time — — — ns See Parameter DO31
CA20 TCWF Pulse Width to Trigger 120 — — ns
CAN Wake-up Filter
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.

FIGURE 30-32: UARTx MODULE I/O TIMING CHARACTERISTICS
UA20
UxRX MSb In Bits 6-1 LSb In

UXTX
UA10
TABLE 30-50: UARTx MODULE I/O TIMING REQUIREMENTS

AC CHARACTERISTICS (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
No.
UA10 TUABAUD UARTx Baud Time 66.67 — — ns
UA11 FBAUD UARTx Baud Frequency — — 15 Mbps
UA20 TCWF Start Bit Pulse Width to Trigger 500 — — ns
UARTx Wake-up
2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 30-51: ANALOG CURRENT SPECIFICATIONS

AC CHARACTERISTICS (unless otherwise stated)
Operating temperature -40°C  TA  +125°C
Param
No.
AVD01 IDD Analog Modules Current — 9 — mA Characterized data with the
Consumption following modules enabled:
APLL, 5 ADC Cores, 2 PGAs
and 4 Analog Comparators
2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.

TABLE 30-52: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
Symbol Characteristics Min. Typical Max. Units Conditions
No.
Device Supply
AD01 AVDD Module VDD Supply Greater of: — Lesser of: V Within 300 mV of VDD at
VDD – 0.3 VDD + 0.3 all times, including device
or 3.0 or 3.6 power-up
AD02 AVSS Module VSS Supply VSS — VSS + 0.3 V
Reference Inputs
AD06 VREFL Reference Voltage Low — AVSS — V (Note 1)
AD07 VREF Absolute Reference 2.7 — AVDD V (Note 3)
Voltage (VREFH – VREFL)
AD08 IREF Reference Input Current — 5 10 µA ADC operating or in standby
Analog Input
AD12 VINH-VINL Full-Scale Input Span AVSS — AVDD V
AD14 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V
AD17 RIN Recommended — 100 —  For minimum sampling
Impedance of Analog time (Note 1)
Voltage Source
AD66 VBG Internal Voltage — 1.2 — V
Reference Source
ADC Accuracy: Pseudodifferential Input
AD20a Nr Resolution 12 bits
AD21a INL Integral Nonlinearity > -3 — <3 LSb AVSS = 0V, AVDD = 3.3V
AD22a DNL Differential Nonlinearity > -1 — <1 LSb AVSS = 0V, AVDD = 3.3V
(Note 2)
AD23a GERR Gain Error >0 8 < 15 LSb AVSS = 0V, AVDD = 3.3V
(Dedicated Core)
Gain Error >5 15 < 22 LSb
(Shared Core)
AD24a EOFF Offset Error >0 5 < 10 LSb AVSS = 0V, AVDD = 3.3V
(Dedicated Core)
Offset Error >2 8 < 13 LSb
(Shared Core)
AD25a — Monotonicity — — — — Guaranteed
Note 1: These parameters are not characterized or tested in manufacturing.
2: No missing codes, limits based on characterization results.
4: Characterized with a 15 kHz sine wave.
5: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is ensured, but not characterized.

TABLE 30-52: ADC MODULE SPECIFICATIONS (CONTINUED)
AC CHARACTERISTICS
Param
Symbol Characteristics Min. Typical Max. Units Conditions
No.
ADC Accuracy: Single-Ended Input
AD20b Nr Resolution 12 bits
AD21b INL Integral Nonlinearity >5 — <5 LSb AVSS = 0V, AVDD = 3.3V
AD22b DNL Differential Nonlinearity > -1 — <1 LSb AVSS = 0V, AVDD = 3.3V
(Note 2)
AD23b GERR Gain Error >0 8 < 15 LSb AVSS = 0V, AVDD = 3.3V
(Dedicated Core)
Gain Error >5 15 < 22 LSb
(Shared Core)
AD24b EOFF Offset Error >2 9 < 15 LSb AVSS = 0V, AVDD = 3.3V
(Dedicated Core)
Offset Error >5 17 < 22 LSb
(Shared Core)
AD25b — Monotonicity — — — — Guaranteed
Dynamic Performance
AD31b SINAD Signal-to-Noise and 63 — > 65 dB (Notes 3, 4)
Distortion
AD34b ENOB Effective Number of Bits 10.3 — — bits (Notes 3, 4)
Note 1: These parameters are not characterized or tested in manufacturing.
2: No missing codes, limits based on characterization results.
4: Characterized with a 15 kHz sine wave.

TABLE 30-53: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
AC CHARACTERISTICS
Param
Symbol Characteristics Min. Typ.(1) Max. Units Conditions
No.
Clock Parameters
AD50 TAD ADC Clock Period 14.28 — — ns
Throughput Rate
AD51 FTP SH0-SH3 — — 3.25 Msps 70 MHz ADC clock, 12 bits, no pending
SH4 — — 3.25 Msps conversion at time of trigger
TABLE 30-54: HIGH-SPEED ANALOG COMPARATOR MODULE SPECIFICATIONS

AC/DC CHARACTERISTICS
Param
Symbol Characteristic Min. Typ. Max. Units Comments
No.
CM10 VIOFF Input Offset Voltage -35 ±5 35 mV
CM11 VICM Input Common-Mode 0 — AVDD V
Voltage Range(1)
CM13 CMRR Common-Mode 60 — — dB
Rejection Ratio
CM14 TRESP Large Signal Response — 15 — ns V+ input step of 100 mV while
V- input is held at AVDD/2. Delay
measured from analog input pin to
PWMx output pin.
CM15 VHYST Input Hysteresis 5 10 20 mV Depends on HYSSEL<1:0>
CM16 TON Comparator Enabled to — — 1 µs
Valid Output
Note 1: These parameters are for design guidance only and are not tested in manufacturing.
2: The comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.

TABLE 30-55: DACx MODULE SPECIFICATIONS
Param
No.
DA01 EXTREF External Voltage Reference(1) 1 — AVDD V
DA02 CVRES Resolution 12 bits
DA03 INL Integral Nonlinearity Error -16 -12 0 LSB
DA04 DNL Differential Nonlinearity Error -1.8 ±1 1.8 LSB
DA05 EOFF Offset Error -8 3 15 LSB
DA06 EG Gain Error -1.2 -0.5 0 %
DA07 TSET Settling Time(1) — 700 — ns Output with 2% of desired
output voltage with a
10-90% or 90-10% step
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
TABLE 30-56: DACx OUTPUT (DACOUTx PIN) SPECIFICATIONS

DC CHARACTERISTICS
Param
No.
DA11 RLOAD Resistive Output Load 10k — — Ohm
Impedance
DA11a CLOAD Output Load — — 35 pF Including output pin
Capacitance capacitance
DA12 IOUT Output Current Drive — 300 — µA Sink and source
Strength
DA13 VRANGE Output Drive Voltage AVSS + 250 mV — AVDD – 900 mV V
Range at Current
Drive of 300 µA
DA14 VLRANGE Output Drive Voltage AVSS + 50 mV — AVDD – 500 mV V
Range at Reduced
Current Drive of 50 µA
DA15 IDD Current Consumed — — 1.3 x IOUT µA Module will always
when Module is consume this current,
Enabled even if no load is
connected to the output
DA30 VOFFSET Input Offset Voltage — 5 — mV
Note 1: The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless

TABLE 30-57: PGAx MODULE SPECIFICATIONS
Param
No.
PA01 VIN Input Voltage Range AVSS – 0.3 — AVDD + 0.3 V
PA02 VCM Common-Mode Input AVSS — AVDD – 1.6 V
Voltage Range
PA03 VOS Input Offset Voltage -10 — 10 mV
PA04 VOS Input Offset Voltage Drift — 15 — µV/C
with Temperature
PA05 RIN+ Input Impedance of — >1M || 7 pF — || pF
Positive Input
PA06 RIN- Input Impedance of — 10k || 7 pF — || pF
Negative Input
PA07 GERR Gain Error -2 — 2 % Gain = 4x, 8x
-3 — 3 % Gain = 16x
-4 — 4 % Gain = 32x, 64x
PA08 LERR Gain Nonlinearity Error — — 0.5 % % of full scale,
Gain = 16x
PA09 IDD Current Consumption — 2.0 — mA Module is enabled with
a 2-volt P-P output
voltage swing
PA10a BW Small Signal G = 4x — 10 — MHz
PA10b Bandwidth (-3 dB) G = 8x — 5 — MHz
PA10c G = 16x — 2.5 — MHz
PA10d G = 32x — 1.25 — MHz
PA10e G = 64x — 0.625 — MHz
PA11 OST Output Settling Time to 1% — 0.4 — µs Gain = 16x, 100 mV
of Final Value input step change
PA12 SR Output Slew Rate — 40 — V/µs Gain = 16x
PA13 TGSEL Gain Selection Time — 1 — µs
PA14 TON Module Turn On/Setting Time — — 10 µs
Note 1: The PGAx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless

TABLE 30-58: CONSTANT-CURRENT SOURCE SPECIFICATIONS
DC CHARACTERISTICS
Param
No.
CC01 IDD Current Consumption — 30 — µA
CC02 IREG Regulation of Current with — ±3 — %
Voltage On
CC03 IOUT Current Output at Terminal — 10 — µA
Note 1: The constant-current source module is functional at VBORMIN < VDD < VDDMIN, but with degraded
performance. Unless otherwise stated, module functionality is tested, but not characterized.
TABLE 30-59: DMA MODULE TIMING REQUIREMENTS

AC CHARACTERISTICS
Param
Characteristic Min. Typ.(1) Max. Units Conditions
No.
DM1 DMA Byte/Word Transfer Latency 1 TCY(2) — — ns
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Because DMA transfers use the CPU data bus, this time is dependent on other functions on the bus.

NOTES:

31.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS
Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 31-1: VOH – 4x DRIVER PINS FIGURE 31-3: VOL – 4x DRIVER PINS
VOH (V)
-0.050 VOL(V)
0.050
-0.045 3.6V
0.045 3.6V
-0.040 3.3V 0.040 3.3V
-0.035
0.035 3V
-0.030 3V
0.030
IOH(A)
IOL(A)
IOH(A)
-0.025 0.025
-0.020 0.020
-0.015 Absolute Maximum 0.015 Absolute Maximum
-0.010 0.010
-0.005 0.005
0.000 0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FIGURE 31-2: VOH – 8x DRIVER PINS FIGURE 31-4: VOL – 8x DRIVER PINS
8X
VOH(V) VOL(V)
-0.080 0.080 3.6V
3.6V
-0.070 0.070 3.3V
3.3V
-0.060 0.060 3V
-0.050 3V 0.050
IOH(A)
IOH(A)
IOL(A)
-0.040 0.040
DS70005258C-page 439
0 030
-0.030 0.030
Absolute Maximum Absolute Maximum
-0.020 0 020
0.020
-0.010 0.010
0.000 0.000
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
FIGURE 31-5: TYPICAL IPD CURRENT @ VDD = 3.3V FIGURE 31-7: TYPICAL IDOZE CURRENT @ VDD = 3.3V, +25°C
DS70005258C-page 440
300 30.0
250 25.0
200 20.0
IDOZE (mA)
IPD (µA)
150 15.0
100 10.0
50 5.0
0 0.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 1:1 1:2 1:64 1:128
Temperature (°C) Doze Ratio
FIGURE 31-6: TYPICAL IDD CURRENT @ VDD = 3.3V, +25°C FIGURE 31-8: TYPICAL IIDLE CURRENT @ VDD = 3.3V, +25°C
30 12.0
10.0
25
8.0
IIDLE (mA)
20
IDD (mA)
6.0
15
4.0
10
2.0
5 0.0
10 20 30 40 50 60 70 10 20 30 40 50 60 70
MIPS MIPS
FIGURE 31-9: TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 31-10: TYPICAL LPRC FREQUENCY @ VDD = 3.3V
7400 34.4
34.2
7350
34
Frequency (kHz)
Frequency (kHz)
7300
33.8
33.6
7250
33.4
7200
33.2
7150 33
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature (°C) Temperature (°C)
DS70005258C-page 441
NOTES:

32.0 PACKAGING INFORMATION
32.1 Package Marking Information
28-Lead SOIC (7.50 mm) Example
XXXXXXXXXXXXXXXXXXXX dsPIC33EP128GS702
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN 1810017
28-Lead UQFN (6x6x0.55 mm) Example
XXXXXXXX 33EP128
XXXXXXXX GS702
YYWWNNN 1810017
28-Lead QFN-S (6x6x0.9 mm) Example
XXXXXXXX 33EP128
XXXXXXXX GS702
YYWWNNN 1810017
44-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX dsPIC33EP
XXXXXXXXXX 64GS804
XXXXXXXXXX
YYWWNNN 1810017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

32.1 Package Marking Information (Continued)
44-Lead QFN (8x8 mm) Example
XXXXXXXXXXX dsPIC33EP
XXXXXXXXXXX 64GS804
XXXXXXXXXXX
YYWWNNN 1810017
48-Lead TQFP (7x7x1.0 mm) Example
1
XXXXXXX 1
EP64GS
XXXYYWW 8051810
NNN 017
XXXXXXXXXX dsPIC33EP
XXXXXXXXXX 64GS806
XXXXXXXXXX
YYWWNNN 1810017
XXXXXXXXXXXX dsPIC33EP64
XXXXXXXXXXXX GS808
YYWWNNN 1810017

32.2 Package Details
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging



28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (2N) - 6x6x0.55 mm Body [UQFN]
With 4.65x4.65 mm Exposed Pad and Corner Anchors
D A B
NOTE 1 N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.10 C
TOP VIEW
A
C A1
0.10 C
SEATING
PLANE
(A3) 28X
SIDE VIEW 0.08 C
8X b1
0.10 C A B
D2
0.10 C A B
8X b2
E2
2 28X K
1
2X P
N
NOTE 1 e
L 28X b
0.10 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-385 Rev C Sheet 1 of 2

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Terminals N 28
Pitch e 0.65 BSC
Overall Height A 0.45 0.50 0.55
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.127 REF
Overall Width E 6.00 BSC
Exposed Pad Width E2 4.55 4.65 4.75
Overall Length D 6.00 BSC
Exposed Pad Length D2 4.55 4.65 4.75
Exposed Pad Corner Chamfer P - 0.35 -
Terminal Width b 0.25 0.30 0.35
Corner Anchor Pad b1 0.35 0.40 0.43
Corner Pad, Metal Free Zone b2 0.15 0.20 0.25
Terminal Length L 0.30 0.40 0.50
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-385 Rev C Sheet 2 of 2

C2
Y2
EV
28
Y3
1
X1
2 ØV
Y4
C1 G1
EV G2
X4 Y1
X3 E SILK SCREEN
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Contact Pitch E 0.65 BSC
Optional Center Pad Width X2 4.75
Optional Center Pad Length Y2 4.75
Contact Pad Spacing C1 6.00
Contact Pad Width (X28) X1 0.35
Contact Pad Length (X28) Y1 0.80
Corner Anchor (X4) X3 1.00
Corner Anchor (X4) Y3 1.00
Corner Anchor Chamfer (X4) X4 0.35
Corner Anchor Chamfer (X4) Y4 0.35
Contact Pad to Pad (X28) G1 0.20
Contact Pad to Center Pad (X28) G2 0.20
Thermal Via Diameter V 0.33
Thermal Via Pitch EV 1.20
Notes:
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2385B
Note: Corner anchor pads are not connected internally and are designed as mechanical features when the
package is soldered to the PCB.



/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH 00 ±[[PP%RG\>4)16@
ZLWKPP&RQWDFW/HQJWK
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ

44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
D A
D1 B
NOTE 2
(DATUM A)
(DATUM B)
E1 E
NOTE 1 A A
2X
N
0.20 H A B
2X 1 2 3
0.20 H A B 4X 11 TIPS
TOP VIEW
0.20 C A B
A A2
C
SEATING PLANE
0.10 C A1
SIDE VIEW
1 2 3
NOTE 1
44 X b
e 0.20 C A B
BOTTOM VIEW
Microchip Technology Drawing C04-076C Sheet 1 of 2

44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
L θ
(L1)
SECTION A-A
Units MILLIMETERS
Number of Leads N 44
Lead Pitch e 0.80 BSC
Overall Height A - - 1.20
Standoff A1 0.05 - 0.15
Molded Package Thickness A2 0.95 1.00 1.05
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Width b 0.30 0.37 0.45
Lead Thickness c 0.09 - 0.20
Lead Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle θ 0° 3.5° 7°
Notes:
2. Exact shape of each corner is optional.


44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
D A B
N
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
0.20 C TOP VIEW
0.10 C A1
C
SEATING A
PLANE 44X
A3 0.08 C
SIDE VIEW
L
0.10 C A B
D2
0.10 C A B
E2
K
2
1
NOTE 1 N
44X b
e 0.07 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-103D Sheet 1 of 2

Units MILLIMETERS
Number of Pins N 44
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.20 REF
Exposed Pad Width E2 6.25 6.45 6.60
Exposed Pad Length D2 6.25 6.45 6.60
Terminal Width b 0.20 0.30 0.35
Terminal Length L 0.30 0.40 0.50
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
2. Package is saw singulated
Microchip Technology Drawing C04-103D Sheet 2 of 2

C1
X2
EV
44
G2
1
2
ØV
EV
C2 Y2
G1
Y1
E SILK SCREEN
X1

Units MILLIMETERS
Optional Center Pad Width X2 6.60
Optional Center Pad Length Y2 6.60
Contact Pad to Contact Pad (X40) G1 0.30
Contact Pad to Center Pad (X44) G2 0.28
Thermal Via Diameter V 0.33
Thermal Via Pitch EV 1.20
Notes:
reflow process
Microchip Technology Drawing No. C04-2103C

48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
48X TIPS
0.20 C A-B D
D
D1
D1
2
A B
E1 E
E1
A A 2
E1
4 N
NOTE 1 1 2 4X
D1 0.20 H A-B D
4
48x b
e 0.08 C A-B D
TOP VIEW
0.10 C H
C A2
A
SEATING
PLANE 0.08 C
A1 SIDE VIEW
Microchip Technology Drawing C04-300-PT Rev A Sheet 1 of 2

E T
L
(L1)
SECTION A-A
Units MILLIMETERS
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Foot Angle I 0° 3.5° 7°
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top D 11° 12° 13°
Mold Draft Angle Bottom E 11° 12° 13°
Notes:
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
5. Datums A-B and D to be determined at center line between leads where leads exit
plastic body at datum plane H
Microchip Technology Drawing C04-300-PT Rev A Sheet 2 of 2

C1
C2 G
SILK SCREEN
48
Y1
1 2
X1
E
Units MILLIMETERS
Distance Between Pads G 0.20
Notes:
reflow process
Microchip Technology Drawing C04-2300-PT Rev A

64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
D
D1
D1/2
D
NOTE 2
E1/2
A B
E1 E
A A
SEE DETAIL 1
N
4X N/4 TIPS
0.20 C A-B D 1 3
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
C 0.05
SEATING
PLANE
A1
64 X b
0.08 C 0.08 C A-B D
e
SIDE VIEW

64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
E
L T
(L1) X=A—B OR D
SECTION A-A X
e/2
DETAIL 1
Units MILLIMETERS
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Foot Angle I 0° 3.5° 7°
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top D 11° 12° 13°
Notes: Mold Draft Angle Bottom E 11° 12° 13°
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.


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NOTES:

APPENDIX A: REVISION HISTORY Revision C (October 2018)
• Sections:
Revision A (May 2016) - Adds Note 1 to all “Pin Diagrams”.
This is the initial version of the document. - Updates Section 2.5 “ICSP Pins”,
Section 4.5.2 “Extended X Data Space”,
Revision B (January 2017) Section 8.0 “Direct Memory Access
(DMA)”, Section 11.7 “I/O Helpful Tips”,
• Sections: Section 16.2 “Feature Description”,
- Updates Note 1 in Section 5.0 “Flash Section 24.1 “Features Overview” and
Program Memory”. Section 24.3 “Module Applications”.
• Tables: • Tables:
- Updates the device description table on - Updates Table 1-1, Table 4-9, Table 4-15,
page 2. Table 8-1, Table 21-1, Table 21-2, Table 21-3,
- Updates Table 1-1, Table 4-2, Table 4-11, Table 21-4, Table 30-11, Table 30-56 and
Table 7-1, Table 8-1, Table 11-11, Table 30-57.
Table 11-13, Table 17-1, Table 30-3, • Registers:
Table 30-4, Table 30-6, Table 30-7, - Updates Register 3-2, Register 5-1,
Table 30-8, Table 30-9, Table 30-10, Register 9-4, Register 9-5, Register 10-1,
Table 30-11, Table 30-52, Table 30-54 and Register 11-8, Register 14-1, Register 16-1,
Table 30-55. Register 16-2, Register 16-3, Register 16-4,
- Adds Table 11-6, Table 11-7, Table 11-8, Register 16-5, Register 16-6, Register 16-7,
Table 11-9 and Table 11-10. Register 16-8, Register 16-9, Register 16-10,
• Figures: Register 16-11, Register 16-13,
- Updates the Pin Function tables in the Pin Register 16-14, Register 16-16,
Diagram figures on pages 5 through 8. Register 16-22, Register 19-1, Register 19-3,
Register 21-3, Register 22-1, Register 22-28,
- Updates Figure 4-1, Figure 17-1, Figure 18-1
Register 22-29, Register 22-30 and
and Figure 18-2.
Register 26-1.
• Registers:
• Figures:
- Updates Register 3-3, Register 16-5,
- Updates Figure 16-2, Figure 18-1,
Figure 18-2 and Figure 30-30.
Register 19-2.
- Adds Register 11-1, Register 11-2,
Register 11-3, Register 11-4, Register 11-5,
Register 11-8.

NOTES:

INDEX
A Assembler
MPASM Assembler .................................................. 376
Absolute Maximum Ratings .............................................. 379
AC Characteristics ............................................................ 391 MPLAB Assembler, Linker, Librarian........................ 376
ADC Specifications ................................................... 432 B
Analog Current Specifications................................... 431
Bit-Reversed Addressing .................................................... 58
Analog-to-Digital Conversion Requirements............. 434
Example...................................................................... 59
Auxiliary PLL Clock ................................................... 393
Implementation ........................................................... 58
CANx I/O Requirements ........................................... 430
Sequence Table (16-Entry) ........................................ 59
Capacitive Loading Requirements on
Block Diagrams
Output Pins ....................................................... 391
16-Bit Timer1 Module ............................................... 171
DMA Module Requirements...................................... 437
ADC Module ............................................................. 278
External Clock Requirements ................................... 392
Addressing for Table Registers .................................. 63
High-Speed PWMx Requirements ............................ 401
CALL Stack Frame ..................................................... 54
I/O Requirements...................................................... 395
CANx Module ........................................................... 312
I2Cx Bus Data Requirements (Master Mode) ........... 427
CLCx Input Source Selection ................................... 265
I2Cx Bus Data Requirements (Slave Mode) ............. 429
CLCx Logic Function Combinatorial Options............ 264
Input Capture x Requirements .................................. 399
CLCx Module............................................................ 263
Internal FRC Accuracy.............................................. 394
Connections for On-Chip Voltage Regulator ............ 359
Internal LPRC Accuracy............................................ 394
Constant-Current Source.......................................... 349
Load Conditions ........................................................ 391
CPU Core ................................................................... 24
OCx/PWMx Module Requirements ........................... 400
Data Access from Program Space
Output Compare x Requirements ............................. 400
Address Generation............................................ 60
PLL Clock.................................................................. 393
Dedicated ADC Cores 0-3 ........................................ 279
Reset, WDT, OST, PWRT Requirements ................. 396
DMA Controller ........................................................... 93
SPI1, SPI2 and SPI3 Master Mode (Full-Duplex,
dsPIC33EPXXGS70X/80X Family.............................. 13
CKE = 0, CKP = x, SMP = 1) Requirements ........ 405
High-Speed Analog Comparator x............................ 338
SPI1, SPI2 and SPI3 Master Mode (Full-Duplex,
High-Speed PWM Architecture................................. 191
CKE = 1, CKP = x, SMP = 1) Requirements ........ 404
Hysteresis Control .................................................... 340
SPI1, SPI2 and SPI3 Master Mode (Half-Duplex,
I2Cx Module ............................................................. 250
Transmit Only) Requirements ............................... 403
Input Capture x ......................................................... 179
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
Interleaved PFC.......................................................... 20
CKE = 0, CKP = 0, SMP = 0) Requirements ........ 413
MCLR Pin Connections .............................................. 18
Multiplexing Remappable Outputs for RPn .............. 140
Off-Line UPS .............................................................. 22
Oscillator System...................................................... 106
Output Compare x Module ....................................... 183
Peripheral to DMA Controller...................................... 91
PGAx Functions........................................................ 346
SPI3 Master Mode (Full-Duplex, CKE = 0,
PGAx Module ........................................................... 345
CKP = x, SMP = 1) Requirements .................... 417
Phase-Shifted Full-Bridge Converter.......................... 21
PLL Module .............................................................. 107
CKP = x, SMP = 1) Requirements .................... 416
Programmer’s Model .................................................. 26
SPI3 Master Mode (Half-Duplex, Transmit Only)
PSV Read Address Generation.................................. 51
Requirements ................................................... 415
PTG Module ............................................................. 218
SPI3 Slave Mode (Full-Duplex, CKE = 0,
Recommended Minimum Connection ........................ 18
CKP = 0, SMP = 0) Requirements .................... 425
Remappable Input for U1RX .................................... 138
Reset System ............................................................. 71
Security Segments for dsPIC33EP128GS70X/80X
(Dual Partition Modes)...................................... 363
Security Segments for dsPIC33EP64GS70X/80X
(Dual Partition Modes)...................................... 362
Security Segments for
Temperature and Voltage Specifications .................. 391
dsPIC33EPXXXGS70X/80X............................. 362
Timer1 External Clock Requirements ....................... 397
Shared ADC Core..................................................... 279
Timer2/Timer4 External Clock Requirements ........... 398
Shared Port Structure............................................... 127
Timer3/Timer5 External Clock Requirements ........... 398
Simplified Conceptual of High-Speed PWM ............. 192
UARTx I/O Requirements ......................................... 431
SPIx Master, Frame Master Connection .................. 247
AC/DC Characteristics
SPIx Master, Frame Slave Connection .................... 248
DACx Specifications ................................................. 435
SPIx Master/Slave Connection
High-Speed Analog Comparator Specifications........ 434
(Enhanced Buffer Modes)................................. 247
PGAx Specifications ................................................. 436
SPIx Master/Slave Connection (Standard Mode)..... 246
Analog-to-Digital Converter. See ADC.
SPIx Module (Enhanced Mode)................................ 235
Arithmetic Logic Unit (ALU)................................................. 32

SPIx Module (Standard Mode).................................. 234 D
SPIx Slave, Frame Master Connection ..................... 248
Data Address Space........................................................... 39
SPIx Slave, Frame Slave Connection ....................... 248
Memory Map for dsPIC33EP64GS70X/80X
Suggested Oscillator Circuit Placement...................... 19
Devices............................................................... 40
Timerx (x = 2 through 5)............................................ 176
Near Data Space ........................................................ 39
Type B/Type C Timer Pair (32-Bit Timer).................. 176
Organization, Alignment ............................................. 39
UARTx Module.......................................................... 257
SFR Space ................................................................. 39
Watchdog Timer (WDT) ............................................ 360
Width .......................................................................... 39
Brown-out Reset (BOR) ............................................ 351, 359
Data Space
C Extended X ................................................................. 54
Paged Data Memory Space (figure) ........................... 52
C Compilers
Paged Memory Scheme ............................................. 51
MPLAB XC ................................................................ 376
DC Characteristics
CAN Module
Brown-out Reset (BOR)............................................ 389
Control Registers ...................................................... 313
Constant-Current Source Specifications................... 437
Message Buffers ....................................................... 332
DACx Output (DACOUTx Pin) Specifications........... 435
Word 0 .............................................................. 332
Doze Current (IDOZE) ................................................ 385
Word 1 .............................................................. 332
I/O Pin Input Specifications....................................... 386
Word 2 .............................................................. 333
I/O Pin Output Specifications.................................... 389
Word 3 .............................................................. 333
Idle Current (IIDLE) .................................................... 383
Word 4 .............................................................. 334
Operating Current (IDD) ............................................ 382
Word 5 .............................................................. 334
Operating MIPS vs. Voltage ..................................... 380
Word 6 .............................................................. 335
Power-Down Current (IPD)........................................ 384
Word 7 .............................................................. 335
Program Memory ...................................................... 390
Modes of Operation .................................................. 312
Temperature and Voltage Specifications.................. 381
Overview ................................................................... 311
Watchdog Timer Delta Current (IWDT).................... 384
CAN Module (CAN)........................................................... 311
DC/AC Characteristics
CLC
Graphs and Tables ................................................... 439
Demo/Development Boards, Evaluation and
Code Examples
Starter Kits ................................................................ 378
Port Write/Read ........................................................ 132
Development Support ....................................................... 375
PWM Write-Protected Register
Device Calibration............................................................. 357
Unlock Sequence.............................................. 190
Addresses................................................................. 357
PWRSAV Instruction Syntax........................................ 117
and Identification ...................................................... 357
Code Protection ........................................................ 351, 361
Device Programmer
CodeGuard Security.................................................. 351, 361
MPLAB PM3 ............................................................. 377
Configurable Logic Cell (CLC) .......................................... 263
Direct Memory Access. See DMA.
Configurable Logic Cell. See CLC.
DMA Controller
Configuration Bits.............................................................. 351
Channel to Peripheral Associations............................ 92
Description ................................................................ 353
Control Registers ........................................................ 94
Configuration Register Map .............................................. 352
DMAxCNT .......................................................... 94
Constant-Current Source .................................................. 349
DMAxCON.......................................................... 94
Control Register ........................................................ 350
DMAxPAD .......................................................... 94
Description ................................................................ 349
DMAxREQ .......................................................... 94
Features Overview .................................................... 349
DMAxSTAL/H ..................................................... 94
Controller Area Network. See CAN.
DMAxSTBL/H ..................................................... 94
CPU
Supported Peripherals ................................................ 91
Addressing Modes ...................................................... 23
Doze Mode ....................................................................... 119
Clocking System Options .......................................... 107
DSP Engine ........................................................................ 32
Fast RC (FRC) Oscillator .................................. 107
FRC Oscillator with PLL (FRCPLL)................... 107 E
FRC Oscillator with Postscaler ......................... 107 Electrical Characteristics .................................................. 379
Low-Power RC (LPRC) Oscillator..................... 107
AC............................................................................. 391
Primary (XT, HS, EC) Oscillator........................ 107 Equations
Primary Oscillator with PLL
Device Operating Frequency .................................... 107
(XTPLL, HSPLL, ECPLL).......................... 107 FPLLO Calculation ..................................................... 107
Control Registers ........................................................ 28 FVCO Calculation ...................................................... 107
Data Space Addressing .............................................. 23
Relationship Between Device and
Instruction Set ............................................................. 23 SPIx Clock Speed............................................. 248
Registers ..................................................................... 23 Errata .................................................................................. 10
Resources ................................................................... 27
Customer Change Notification Service ............................. 478
Customer Notification Service........................................... 478
Customer Support ............................................................. 478

F Input Change Notification (ICN)........................................ 132
Filter Capacitor (CEFC) Specifications............................... 381 Instruction Addressing Modes ............................................ 55
Flash Program Memory ...................................................... 63 File Register Instructions ............................................ 55
Fundamental Modes Supported ................................. 55
and Table Instructions................................................. 63
Control Registers ........................................................ 66 MAC Instructions ........................................................ 56
Dual Partition Flash Configuration .............................. 65 MCU Instructions ........................................................ 55
Move and Accumulator Instructions ........................... 56
Operations .................................................................. 64
Resources................................................................... 65 Other Instructions ....................................................... 56
RTSP Operation.......................................................... 64 Instruction Set Summary .................................................. 365
Overview................................................................... 368
Flexible Configuration ....................................................... 351
Symbols Used in Opcode Descriptions .................... 366
G Instruction-Based Power-Saving Modes........................... 117
Getting Started Guidelines .................................................. 17 Idle............................................................................ 118
Connection Requirements .......................................... 17 Sleep ........................................................................ 118
CPU Logic Filter Capacitor Connection (VCAP) .......... 18 Inter-Integrated Circuit (I2C) ............................................. 249
Decoupling Capacitors................................................ 17 Control Registers...................................................... 251
External Oscillator Pins............................................... 19 Resources ................................................................ 249
ICSP Pins.................................................................... 19 Inter-Integrated Circuit. See I2C.
Master Clear (MCLR) Pin............................................ 18 Internet Address ............................................................... 478
Oscillator Value Conditions on Start-up ...................... 20 Interrupt Controller
Targeted Applications ................................................. 20 Alternate Interrupt Vector Table (AIVT) ...................... 75
Unused I/Os ................................................................ 20 Control and Status Registers...................................... 83
INTCON1............................................................ 83
H INTCON2............................................................ 83
High-Speed Analog Comparator INTCON3............................................................ 83
Applications............................................................... 339 INTCON4............................................................ 83
Description ................................................................ 338 INTTREG............................................................ 83
Digital-to-Analog Comparator (DAC) ........................ 339 Interrupt Vector Details............................................... 78
Features Overview.................................................... 337 Interrupt Vector Table (IVT)........................................ 75
Hysteresis ................................................................. 340 Reset Sequence ......................................................... 75
Pulse Stretcher and Digital Logic.............................. 339 Resources .................................................................. 83
Resources................................................................. 340 Interrupts Coincident with Power Save Instructions ......... 118
High-Speed PWM
J
Features.................................................................... 189
Resources................................................................. 190 JTAG Boundary Scan Interface ........................................ 351
Write-Protected Registers......................................... 190 JTAG Interface ................................................................. 361
High-Speed, 12-Bit Analog-to-Digital L
Converter (ADC) ....................................................... 277
Leading-Edge Blanking (LEB) .......................................... 189
LPRC Oscillator
Features Overview.................................................... 277
Use with WDT........................................................... 360
Resources................................................................. 280
I M
I/O Ports ............................................................................ 127 Memory Organization ......................................................... 33
Configuring Analog/Digital Port Pins......................... 132 Resources .................................................................. 41
Special Function Register Maps................................. 42
Helpful Tips ............................................................... 142 Microchip Internet Web Site.............................................. 478
Open-Drain Configuration ......................................... 132 Modulo Addressing ............................................................. 57
Applicability................................................................. 58
Parallel I/O (PIO)....................................................... 127
Register Maps........................................................... 129 Operation Example..................................................... 57
PORTA ............................................................. 129 Start and End Address ............................................... 57
W Address Register Selection.................................... 57
PORTB ............................................................. 129
PORTC ............................................................. 130 MPLAB REAL ICE In-Circuit Emulator System ................ 377
PORTD ............................................................. 130 MPLAB X Integrated Development
PORTE ............................................................. 131 Environment Software .............................................. 375
Resources................................................................. 143 MPLINK Object Linker/MPLIB Object Librarian ................ 376
Multiplexer Input Sources
Write/Read Timing .................................................... 132
In-Circuit Debugger ........................................................... 361 CLC1 ........................................................................ 269
MPLAB ICD 3............................................................ 377 CLC2 ........................................................................ 270
CLC3 ........................................................................ 271
PICkit 3 Programmer ................................................ 377
In-Circuit Emulation........................................................... 351 CLC4 ........................................................................ 272
In-Circuit Serial Programming (ICSP) ....................... 351, 361
Input Capture .................................................................... 179
Resources................................................................. 179

O ADCAL0L (ADC Calibration 0 Low) .......................... 303
Oscillator ADCAL1H (ADC Calibration 1 High)......................... 305
Control Registers ...................................................... 109 ADCMPxCON (ADC Digital Comparator x
Control)............................................................. 306
Resources ................................................................. 108
Oscillator Configuration..................................................... 105 ADCMPxENH (ADC Digital Comparator x
Output Compare................................................................ 183 Channel Enable High) ...................................... 307
ADCMPxENL (ADC Digital Comparator x
Resources ................................................................. 183 Channel Enable Low) ....................................... 307
ADCON1H (ADC Control 1 High) ............................. 281
P ADCON1L (ADC Control 1 Low)............................... 280
Packaging ......................................................................... 443 ADCON2H (ADC Control 2 High) ............................. 283
Details ....................................................................... 445 ADCON2L (ADC Control 2 Low)............................... 282
Marking ..................................................................... 443 ADCON3H (ADC Control 3 High) ............................. 285
Peripheral Module Disable (PMD)..................................... 119 ADCON3L (ADC Control 3 Low)............................... 284
Peripheral Pin Select (PPS) .............................................. 137 ADCON4H (ADC Control 4 High) ............................. 287
Available Peripherals ................................................ 137 ADCON4L (ADC Control 4 Low)............................... 286
Available Pins ........................................................... 137 ADCON5H (ADC Control 5 High) ............................. 289
Control ...................................................................... 137 ADCON5L (ADC Control 5 Low)............................... 288
Control Registers ...................................................... 144 ADCORExH (Dedicated ADC Core x
Input Mapping ........................................................... 138 Control High) .................................................... 291
Output Mapping ........................................................ 140 ADCORExL (Dedicated ADC Core x
Output Selection for Remappable Pins ..................... 141 Control Low) ..................................................... 290
Selectable Input Sources .......................................... 139 ADEIEH (ADC Early Interrupt Enable High) ............. 293
Peripheral Trigger Generator (PTG) Module..................... 217 ADEIEL (ADC Early Interrupt Enable Low)............... 293
Peripheral Trigger Generator. See PTG. ADEISTATH (ADC Early Interrupt Status High) ....... 294
Pinout I/O Descriptions (table) ............................................ 14 ADEISTATL (ADC Early Interrupt Status Low)......... 294
Power-Saving Features..................................................... 117 ADFLxCON (ADC Digital Filter x Control) ................ 308
Clock Frequency and Switching................................ 117 ADIEH (ADC Interrupt Enable High)......................... 297
Resources ................................................................. 119 ADIEL (ADC Interrupt Enable Low) .......................... 297
Program Address Space ..................................................... 33 ADLVLTRGH (ADC Level-Sensitive Trigger
Construction ................................................................ 60 Control High) .................................................... 292
Data Access from Program Memory Using ADLVLTRGL (ADC Level-Sensitive Trigger
Table Instructions................................................ 61 Control Low) ..................................................... 292
Memory Map (dsPIC33EP128GS70X/80X Devices, ADMOD0H (ADC Input Mode Control 0 High).......... 295
Dual Partition) ..................................................... 37 ADMOD0L (ADC Input Mode Control 0 Low) ........... 295
Memory Map (dsPIC33EP128GS70X/80X ADMOD1L (ADC Input Mode Control 1 Low) ........... 296
Devices) .............................................................. 35 ADSTATH (ADC Data Ready Status High) .............. 298
Memory Map (dsPIC33EP64GS70X/80X Devices, ADSTATL (ADC Data Ready Status Low)................ 298
Dual Partition) ..................................................... 36 ADTRIGxH (ADC Channel Trigger x
Memory Map Selection High) ................................................. 301
(dsPIC33EP64GS70X/80X Devices) .................. 34 ADTRIGxL (ADC Channel Trigger x
Table Read High Instructions (TBLRDH) ..................... 61 Selection Low) .................................................. 299
Table Read Low Instructions (TBLRDL) ...................... 61 ALTDTRx (PWMx Alternate Dead-Time).................. 205
Program Memory ANSELx (Analog Select Control x) ........................... 136
Interfacing with Data Memory Spaces ........................ 60 AUXCONx (PWMx Auxiliary Control) ....................... 214
Organization................................................................ 38 CHOP (PWM Chop Clock Generator) ...................... 198
Reset Vector ............................................................... 38 CLCxCONH (CLCx Control High)............................. 267
Programmable Gain Amplifier (PGA) ................................ 345 CLCxCONL (CLCx Control Low) .............................. 266
Description ................................................................ 346 CLCxGLSH (CLCx Gate Logic
Resources ................................................................. 347 Input Select High) ............................................. 275
Programmable Gain Amplifier. See PGA. CLCxGLSL (CLCx Gate Logic Input Select Low) ..... 273
Programmer’s Model........................................................... 25 CLCxSEL (CLCx Input MUX Select)......................... 268
Register Descriptions .................................................. 25 CLKDIV (Clock Divisor) ............................................ 111
PTG CMPxCON (Comparator x Control) .......................... 341
Control Registers ...................................................... 219 CMPxDAC (Comparator x DAC Control) .................. 343
Introduction ............................................................... 217 CNENx (Input Change Notification
Output Descriptions .................................................. 232 Interrupt Enable x) ............................................ 135
Step Commands and Format .................................... 229 CNPDx (Input Change Notification
Pulse-Width Modulator. See PWM. Pull-Down Enable x) ......................................... 136
CNPUx (Input Change Notification
R Pull-up Enable x) .............................................. 135
Referenced Sources ........................................................... 11 CORCON (Core Control) ...................................... 30, 85
Registers CTXTSTAT (CPU W Register Context Status)........... 31
ACLKCON (Auxiliary Clock Divisor Control) ............. 114 CxBUFPNT1 (CANx Filters 0-3 Buffer Pointer 1) ..... 322
ADCAL0L (ADC Calibration 0 High) ......................... 304 CxBUFPNT2 (CANx Filters 4-7 Buffer Pointer 2) ..... 323

CxBUFPNT3 (CANx Filters 8-11 INTTREG (Interrupt Control and Status) .................... 90
Buffer Pointer 3)................................................ 323 IOCONx (PWMx I/O Control).................................... 207
CxBUFPNT4 (CANx Filters 12-15 ISRCCON (Constant-Current Source Control) ......... 350
Buffer Pointer 4)................................................ 324 LATx (PORTx Data Latch)........................................ 134
CxCFG1 (CANx Baud Rate Configuration 1)............ 320 LEBCONx (PWMx Leading-Edge
CxCFG2 (CANx Baud Rate Configuration 2)............ 321 Blanking Control) .............................................. 212
CxCTRL1 (CANx Control 1)...................................... 313 LEBDLYx (PWMx Leading-Edge
CxCTRL2 (CANx Control 2)...................................... 314 Blanking Delay) ................................................ 213
CxEC (CANx Transmit/Receive Error Count) ........... 320 LFSR (Linear Feedback Shift) .................................. 116
CxFCTRL (CANx FIFO Control) ............................... 316 MDC (PWM Master Duty Cycle)............................... 199
CxFEN1 (CANx Acceptance Filter Enable 1)............ 322 NVMADR (Nonvolatile Memory Lower Address)........ 69
CxFIFO (CANx FIFO Status) .................................... 317 NVMADRU (Nonvolatile Memory Upper Address) ..... 69
CxFMSKSEL1 (CANx Filters 7-0 NVMCON (Nonvolatile Memory (NVM) Control) ........ 67
Mask Selection 1) ............................................. 326 NVMKEY (Nonvolatile Memory Key) .......................... 70
CxFMSKSEL2 (CANx Filters 15-8 NVMSRCADR (NVM Source Data Address).............. 70
Mask Selection 2) ............................................. 327 OCxCON1 (Output Compare x Control 1) ................ 184
CxINTE (CANx Interrupt Enable) .............................. 319 OCxCON2 (Output Compare x Control 2) ................ 186
CxINTF (CANx Interrupt Flag) .................................. 318 ODCx (PORTx Open-Drain Control) ........................ 134
CxRXFnEID (CANx Acceptance Filter n OSCCON (Oscillator Control)................................... 109
Extended Identifier)........................................... 325 OSCTUN (FRC Oscillator Tuning)............................ 113
CxRXFnSID (CANx Acceptance Filter n PDCx (PWMx Generator Duty Cycle)....................... 202
Standard Identifier) ........................................... 325 PGAxCAL (PGAx Calibration) .................................. 348
CxRXFUL1 (CANx Receive Buffer Full 1)................. 329 PGAxCON (PGAx Control)....................................... 347
CxRXFUL2 (CANx Receive Buffer Full 2)................. 329 PHASEx (PWMx Primary Phase-Shift)..................... 203
CxRXMnEID (CANx Acceptance Filter Mask n PLLFBD (PLL Feedback Divisor) ............................. 112
Extended Identifier)........................................... 328 PMD1 (Peripheral Module Disable Control 1) .......... 120
CxRXMnSID (CANx Acceptance Filter Mask n PMD2 (Peripheral Module Disable Control 2) .......... 122
Standard Identifier) ........................................... 328 PMD3 (Peripheral Module Disable Control 3) .......... 123
CxRXOVF1 (CANx Receive Buffer Overflow 1)........ 330 PMD4 (Peripheral Module Disable Control 4) .......... 123
CxRXOVF2 (CANx Receive Buffer Overflow 2)........ 330 PMD6 (Peripheral Module Disable Control 6) .......... 124
CxTRmnCON (CANx TX/RX Buffer mn Control) ...... 331 PMD7 (Peripheral Module Disable Control 7) .......... 125
CxVEC (CANx Interrupt Code) ................................. 315 PMD8 (Peripheral Module Disable Control 8) .......... 126
DEVID (Device ID) .................................................... 358 PORTx (I/O PORTx)................................................. 133
DEVREV (Device Revision) ...................................... 358 PTCON (PWM Time Base Control) .......................... 193
DMALCA (DMA Last Channel Active Status) ........... 102 PTCON2 (PWM Clock Divider Select)...................... 194
DMAPPS (DMA Ping-Pong Status) .......................... 103 PTGADJ (PTG Adjust).............................................. 227
DMAPWC (DMA Peripheral Write PTGBTE (PTG Broadcast Trigger Enable)............... 222
Collision Status) ................................................ 100 PTGC0LIM (PTG Counter 0 Limit) ........................... 225
DMARQC (DMA Request Collision Status) .............. 101 PTGC1LIM (PTG Counter 1 Limit) ........................... 226
DMAxCNT (DMA Channel x Transfer Count) ............. 98 PTGCON (PTG Control)........................................... 221
DMAxCON (DMA Channel x Control) ......................... 94 PTGCST (PTG Control/Status) ................................ 219
DMAxPAD (DMA Channel x Peripheral Address)....... 98 PTGHOLD (PTG Hold) ............................................. 226
DMAxREQ (DMA Channel x IRQ Select) ................... 95 PTGL0 (PTG Literal 0).............................................. 227
DMAxSTAH (DMA Channel x PTGQPTR (PTG Step Queue Pointer) ..................... 228
Start Address A, High) ........................................ 96 PTGQUEx (PTG Step Queue x)............................... 228
DMAxSTAL (DMA Channel x PTGSDLIM (PTG Step Delay Limit) ......................... 225
Start Address A, Low) ......................................... 96 PTGT0LIM (PTG Timer0 Limit) ................................ 224
DMAxSTBH (DMA Channel x PTGT1LIM (PTG Timer1 Limit) ................................ 224
Start Address B, High) ........................................ 97 PTPER (PWM Primary Master
DMAxSTBL (DMA Channel x Time Base Period)............................................ 195
Start Address B, Low) ......................................... 97 PWMCAPx (PWMx Primary
DSADRH (DMA Most Recent RAM High Address)..... 99 Time Base Capture) ......................................... 215
DSADRL (DMA Most Recent RAM Low Address) ...... 99 PWMCONx (PWMx Control) .................................... 200
DTRx (PWMx Dead-Time) ........................................ 205 PWMKEY (PWM Protection Lock/Unlock Key) ........ 199
FCLCONx (PWMx Fault Current-Limit Control) ........ 209 RCON (Reset Control)................................................ 73
I2CxCONH (I2Cx Control High) ................................ 253 REFOCON (Reference Oscillator Control) ............... 115
I2CxCONL (I2Cx Control Low).................................. 251 RPINR0 (Peripheral Pin Select Input 0) ................... 144
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 256 RPINR1 (Peripheral Pin Select Input 1) ................... 144
I2CxSTAT (I2Cx Status) ........................................... 254 RPINR11 (Peripheral Pin Select Input 11) ............... 147
ICxCON1 (Input Capture x Control 1) ....................... 180 RPINR12 (Peripheral Pin Select Input 12) ............... 147
ICxCON2 (Input Capture x Control 2) ....................... 181 RPINR13 (Peripheral Pin Select Input 13) ............... 148
INTCON1 (Interrupt Control 1).................................... 86 RPINR18 (Peripheral Pin Select Input 18) ............... 148
INTCON3 (Interrupt Control 3).................................... 89 RPINR2 (Peripheral Pin Select Input 2) ................... 145

RPINR21 (Peripheral Pin Select Input 21) ................ 150 STRIGx (PWMx Secondary Trigger
RPINR22 (Peripheral Pin Select Input 22) ................ 150 Compare Value) ............................................... 211
RPINR23 (Peripheral Pin Select Input 23) ................ 151 T1CON (Timer1 Control) .......................................... 173
RPINR26 (Peripheral Pin Select Input 26) ................ 151 TRGCONx (PWMx Trigger Control) ......................... 206
RPINR29 (Peripheral Pin Select Input 29) ................ 152 TRIGx (PWMx Primary Trigger Compare Value)...... 208
RPINR3 (Peripheral Pin Select Input 3) .................... 145 TRISx (PORTx Data Direction Control) .................... 133
RPINR30 (Peripheral Pin Select Input 30) ................ 152 TxCON (Timer2/4 Control)........................................ 177
RPINR37 (Peripheral Pin Select Input 37) ................ 153 TyCON (Timer3/5 Control)........................................ 178
RPINR38 (Peripheral Pin Select Input 38) ................ 153 UxMODE (UARTx Mode).......................................... 259
RPINR42 (Peripheral Pin Select Input 42) ................ 154 UxSTA (UARTx Status and Control)......................... 261
RPINR43 (Peripheral Pin Select Input 43) ................ 154 Resets................................................................................. 71
RPINR45 (Peripheral Pin Select Input 45) ................ 155 Brown-out Reset (BOR).............................................. 71
RPINR46 (Peripheral Pin Select Input 46) ................ 155 Configuration Mismatch Reset (CM)........................... 71
RPINR7 (Peripheral Pin Select Input 7) .................... 146 Illegal Condition Reset (IOPUWR).............................. 71
RPINR8 (Peripheral Pin Select Input 8) .................... 146 Illegal Opcode..................................................... 71
RPOR0 (Peripheral Pin Select Output 0) .................. 156 Security............................................................... 71
RPOR1 (Peripheral Pin Select Output 1) .................. 156 Uninitialized W Register ..................................... 71
RPOR10 (Peripheral Pin Select Output 10) .............. 161 Master Clear (MCLR) Pin Reset ................................. 71
RPOR11 (Peripheral Pin Select Output 11) .............. 161 Power-on Reset (POR)............................................... 71
RPOR12 (Peripheral Pin Select Output 12) .............. 162 RESET Instruction (SWR)............................................ 71
RPOR13 (Peripheral Pin Select Output 13) .............. 162 Resources .................................................................. 72
RPOR14 (Peripheral Pin Select Output 14) .............. 163 Trap Conflict Reset (TRAPR) ..................................... 71
RPOR15 (Peripheral Pin Select Output 15) .............. 163 Watchdog Timer Time-out Reset (WDTO) ................. 71
RPOR16 (Peripheral Pin Select Output 16) .............. 164 Revision History................................................................ 469
RPOR17 (Peripheral Pin Select Output 17) .............. 164
RPOR18 (Peripheral Pin Select Output 18) .............. 165 S
RPOR19 (Peripheral Pin Select Output 19) .............. 165 Serial Peripheral Interface (SPI) ....................................... 233
RPOR2 (Peripheral Pin Select Output 2) .................. 157 Serial Peripheral Interface. See SPI.
RPOR20 (Peripheral Pin Select Output 20) .............. 166 SFR Blocks
RPOR21 (Peripheral Pin Select Output 21) .............. 166 000h............................................................................ 42
RPOR3 (Peripheral Pin Select Output 3) .................. 157 600h............................................................................ 45
RPOR7 (Peripheral Pin Select Output 7) .................. 159 A00h ........................................................................... 48
RPOR8 (Peripheral Pin Select Output 8) .................. 160 B00h ........................................................................... 48
RPOR9 (Peripheral Pin Select Output 9) .................. 160 C00h-D00h ................................................................. 49
SDCx (PWMx Secondary Duty Cycle) ...................... 202 E00h-F00h .................................................................. 50
SEVTCMP (PWM Special Event Compare).............. 195 Software Simulator
SPHASEx (PWMx Secondary Phase-Shift) .............. 204 MPLAB X SIM........................................................... 377
SPIxCON1H (SPIx Control 1 High) ........................... 238 Special Features of the CPU ............................................ 351
SPIxCON1L (SPIx Control 1 Low) ............................ 236
SPIxCON2L (SPIx Control 2 Low) ............................ 240
T
SPIxIMSKH (SPIx Interrupt Mask High).................... 245 Thermal Operating Conditions.......................................... 380
SPIxIMSKL (SPIx Interrupt Mask Low) ..................... 244 Thermal Packaging Characteristics .................................. 380
SPIxSTATH (SPIx Status High) ................................ 243 Third-Party Development Tools ........................................ 378
SPIxSTATL (SPIx Status Low) ................................. 241 Timer1............................................................................... 171
SR (CPU STATUS) ............................................... 28, 84 Control Register........................................................ 173
SSEVTCMP (PWM Secondary Mode Settings........................................................... 171
Special Event Compare) ................................... 198 Resources ................................................................ 172
STCON (PWM Secondary Master Timer2/3 and Timer4/5 ..................................................... 175
Time Base Control) ........................................... 196 Control Registers ...................................................... 177
STCON2 (PWM Secondary Resources ................................................................ 175
Clock Divider Select)......................................... 197
STPER (PWM Secondary Master
Time Base Period) ............................................ 197

Timing Diagrams U
BOR and Master Clear Reset Characteristics .......... 395
UART
CANx I/O................................................................... 430
Unique Device Identifier (UDID) ......................................... 34
External Clock........................................................... 392
Universal Asynchronous Receiver
High-Speed PWMx Fault Characteristics.................. 401
Transmitter (UART) .................................................. 257
High-Speed PWMx Module Characteristics.............. 401
Control Registers...................................................... 259
I/O Characteristics .................................................... 395
Helpful Tips............................................................... 258
I2Cx Bus Data (Master Mode) .................................. 426
Resources ................................................................ 258
I2Cx Bus Data (Slave Mode) .................................... 428
Universal Asynchronous Receiver Transmitter. See UART.
I2Cx Bus Start/Stop Bits (Master Mode) ................... 426
User OTP Memory............................................................ 359
I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 428
Input Capture x (ICx) Characteristics........................ 399 V
OCx/PWMx Characteristics ...................................... 400 Voltage Regulator (On-Chip) ............................................ 359
Output Compare x (OCx) Characteristics ................. 400
SPI1, SPI2 and SPI3 Master Mode (Full-Duplex, W
CKE = 0, CKP = x, SMP = 1) ............................ 405 Watchdog Timer (WDT)............................................ 351, 360
SPI1, SPI2 and SPI3 Master Mode (Full-Duplex, Programming Considerations ................................... 360
CKE = 1, CKP = x, SMP = 1) ............................ 404 WWW Address ................................................................. 478
SPI1, SPI2 and SPI3 Master Mode (Half-Duplex, WWW, On-Line Support ..................................................... 10
Transmit Only, CKE = 0)................................... 402
SPI1, SPI2 and SPI3 Master Mode (Half-Duplex,
CKE = 0, CKP = 0, SMP = 0)............................ 412
CKE = 0, CKP = 1, SMP = 0)............................ 410
CKE = 1, CKP = 0, SMP = 0)............................ 406
CKE = 1, CKP = 1, SMP = 0)............................ 408
CKP = x, SMP = 1) ........................................... 417
CKP = x, SMP = 1) ........................................... 416
SPI3 Master Mode (Half-Duplex,
SPI3 Master Mode (Half-Duplex,
CKP = 0, SMP = 0) ........................................... 424
CKP = 1, SMP = 0) ........................................... 422
CKP = 0, SMP = 0) ........................................... 418
CKP = 1, SMP = 0) ........................................... 420
Timer1-Timer5 External Clock Characteristics ......... 397
UARTx I/O Characteristics........................................ 431

NOTES:

THE MICROCHIP WEBSITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This website is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
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browser, the website contains the following information:
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Questions (FAQ), technical support requests, included in the back of this document.
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To register, access the Microchip website at
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registration instructions.

NOTES:

PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC 33 EP 64 GS8 04 T - I / PT XXX Examples:
dsPIC33EP64GS804-I/PT:
Microchip Trademark dsPIC33, Enhanced Performance,
64-Kbyte Program Memory, SMPS,
Architecture
44-Pin, Industrial Temperature,
Flash Memory Family TQFP Package.
Program Memory Size (Kbyte)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture: 33 = 16-Bit Digital Signal Controller
Flash Memory Family: EP = Enhanced Performance
Product Group: GS = SMPS Family
Pin Count: 02 = 28-pin

04 = 44-pin
05 = 48-pin
06 = 64-pin
08 = 80-pin
Temperature Range: I = -40C to +85C (Industrial)

E = -40C to +125C (Extended)
Package: ML = Plastic Quad, No Lead Package – (44-pin) 8x8 mm body (QFN)

MM = Plastic Quad, No Lead Package – (28-pin) 6x6 mm body (QFN-S)
2N = Plastic Quad Flat, No Lead Package – (28-pin) 6x6 mm body (UQFN)
PT = Plastic Thin Quad Flatpack – (44-pin) 10x10 mm body (TQFP)
SO = Plastic Small Outline, Wide – (28-pin) 7.50 mm body (SOIC)

NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate, AVR,
and may be superseded by updates. It is your responsibility to AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
ensure that your application meets with your specifications. CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
MICROCHIP MAKES NO REPRESENTATIONS OR JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
OTHERWISE, RELATED TO THE INFORMATION, Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
QUALITY, PERFORMANCE, MERCHANTABILITY OR trademarks of Microchip Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability and other countries.
arising from this information and its use. Use of Microchip ClockWorks, The Embedded Control Solutions Company,
devices in life support and/or safety applications is entirely at EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
the buyer’s risk, and the buyer agrees to defend, indemnify and mTouch, Precision Edge, and Quiet-Wire are registered
hold harmless Microchip from any and all damages, claims, trademarks of Microchip Technology Incorporated in the U.S.A.
suits, or expenses resulting from such use. No licenses are Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
conveyed, implicitly or otherwise, under any Microchip Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
intellectual property rights unless otherwise stated. CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
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QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
Microchip received ISO/TS-16949:2009 certification for its worldwide SQTP is a service mark of Microchip Technology Incorporated in
headquarters, design and wafer fabrication facilities in Chandler and the U.S.A.
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures Silicon Storage Technology is a registered trademark of Microchip
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping Technology Inc. in other countries.
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
GestIC is a registered trademark of Microchip Technology
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and manufacture of development systems is ISO 9001:2000 certified. Germany II GmbH & Co. KG, a subsidiary of Microchip
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All other trademarks mentioned herein are property of their
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© 2018, Microchip Technology Incorporated, All Rights Reserved.
CERTIFIED BY DNV ISBN: 978-1-5224-3795-6
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08/15/18

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dsPIC33EPXXXGS70X/80X FAMILY

16-Bit Digital Signal Controllers for Digital Power Applications with

Operating Conditions Advanced Analog Features

High-Speed PWM Timers/Output Compare/Input Capture

 2016-2018 Microchip Technology Inc. DS70005258C-page 1

dsPIC33EP128GS702 28 128K 8K 20 5 4 4 2 3 8x2 4 0 1 2 4 1 11 5 2 0 4 1 1 SOIC,

DS70005258C-page 2  2016-2018 Microchip Technology Inc.

Pin Pin Function Pin Pin Function

Legend: Shaded pins are up to 5 VDC tolerant.

 2016-2018 Microchip Technology Inc. DS70005258C-page 3

28-Pin QFN-S, UQFN

Pin Pin Function Pin Pin Function

Legend: Shaded pins are up to 5 VDC tolerant.

DS70005258C-page 4  2016-2018 Microchip Technology Inc.

44-Pin QFN, TQFP

Pin Pin Function Pin Pin Function

Legend: Shaded pins are up to 5 VDC tolerant.

 2016-2018 Microchip Technology Inc. DS70005258C-page 5

Pin Pin Function Pin Pin Function

Legend: Shaded pins are up to 5 VDC tolerant.

DS70005258C-page 6  2016-2018 Microchip Technology Inc.

 2016-2018 Microchip Technology Inc. DS70005258C-page 7

DS70005258C-page 8  2016-2018 Microchip Technology Inc.

 2016-2018 Microchip Technology Inc. DS70005258C-page 9

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS70005258C-page 10  2016-2018 Microchip Technology Inc.

• “dsPIC33E Enhanced CPU” (DS70005158)

 2016-2018 Microchip Technology Inc. DS70005258C-page 11

DS70005258C-page 12  2016-2018 Microchip Technology Inc.

FIGURE 1-1: dsPIC33EPXXXGS70X/80X FAMILY BLOCK DIAGRAM

Constant Analog Ports

 2016-2018 Microchip Technology Inc. DS70005258C-page 13

DS70005258C-page 14  2016-2018 Microchip Technology Inc.

U2CTS I ST Yes UART2 Clear-to-Send.

 2016-2018 Microchip Technology Inc. DS70005258C-page 15

DS70005258C-page 16  2016-2018 Microchip Technology Inc.

 2016-2018 Microchip Technology Inc. DS70005258C-page 17

DS70005258C-page 18  2016-2018 Microchip Technology Inc.

 2016-2018 Microchip Technology Inc. DS70005258C-page 19

2.8 Unused I/Os

FIGURE 2-4: INTERLEAVED PFC

PGA/ADC Channel PWM PGA/ADC PWM PGA/ADC ADC

DS70005258C-page 20  2016-2018 Microchip Technology Inc.

FET PWM PGA/ADC PWM ADC

 2016-2018 Microchip Technology Inc. DS70005258C-page 21

FET FET FET FET FET FET

PWM PWM PGA/ADC ADC PWM PWM PWM PWM

DS70005258C-page 22  2016-2018 Microchip Technology Inc.

 2016-2018 Microchip Technology Inc. DS70005258C-page 23

Interrupt Data Latch Data Latch

Control Signals Instruction

Power, Reset Ports

DS70005258C-page 24  2016-2018 Microchip Technology Inc.

TABLE 3-1: PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

 2016-2018 Microchip Technology Inc. DS70005258C-page 25

PUSH.S and POP.S Shadows

AD39 AD31 AD15 AD0