PIC16 (L) F1526/7: 64-Pin Flash Microcontrollers With XLP Technology

PIC16(L)F1526/7
64-Pin Flash Microcontrollers with XLP Technology

High-Performance RISC CPU Extreme Low-Power Management
• C Compiler Optimized Architecture PIC16LF1526/7 with XLP
• Only 49 Instructions • Sleep mode: 20 nA @ 1.8V, typical
• Operating Speed: • Watchdog Timer: 300 nA @ 1.8V, typical
- DC – 20 MHz clock input @ 2.5V • Secondary Oscillator: 600 nA @ 32 kHz, 1.8V,
- DC – 16 MHz clock input @ 1.8V typical
- DC – 200 ns instruction cycle Analog Features
• Interrupt Capability with Automatic Context
• Analog-to-Digital Converter (ADC):
Saving
- 10-bit resolution
• 16-Level Deep Hardware Stack with Optional
- 30 external channels
Overflow/Underflow Reset
- Two internal channels
• Direct, Indirect and Relative Addressing modes:
- Fixed Voltage Reference (FVR) channel
- Two full 16-bit File Select Registers (FSRs)
- Temperature Indicator channel
- FSRs can read program and data memory
- Auto acquisition capability
Memory - Conversion available during Sleep
- Dedicated ADC RC oscillator
• Up to 28 Kbytes Linear Program Memory
- Fixed Voltage Reference (FVR) as ADC
Addressing
positive reference
• Up to 1536 Bytes Linear Data Memory
• Voltage Reference module:
Addressing
- Fixed Voltage Reference (FVR) with 1.024V,
• High-Endurance Flash Data Memory (HEF)
2.048V and 4.096V output levels
- 128B of nonvolatile data storage
- Low-Power Sleep mode
- 100K erase/write cycles
- Low-Power BOR (LPBOR)
Flexible Oscillator Structure Peripheral Features
• 16 MHz Internal Oscillator Block: • 53 I/O Pins and One Input-only Pin:
- Software selectable frequency range from - High current sink/source 25 mA/25 mA
16 MHz to 31 kHz - Individually programmable weak pull-ups
• 31 kHz Low-Power Internal Oscillator - Individually programmable
• External Oscillator Block with: interrupt-on-change (IOC) pins
- Four crystal/resonator modes up to 20 MHz • Timer0: 8-Bit Timer/Counter with 8-Bit
- Three external clock modes up to 20 MHz Programmable Prescaler
• Fail-Safe Clock Monitor • Enhanced Timer1, 3, 5:
- Allows safe shutdown if peripheral clock stops - 16-bit timer/counter with prescaler
• Two-Speed Oscillator Start-up - External Gate Input mode
• Oscillator Start-up Timer (OST) - Low-power 32 kHz secondary oscillator driver
• Timer2, 4, 6, 8, 10: 8-Bit Timer/Counter with 8-Bit
Special Microcontroller Features
Period Register, Prescaler and Postscaler
• Operating Voltage Range:
• Ten Capture/Compare/PWM (CCP) modules:
- 1.8V to 3.6V (PIC16LF1526/7)
- 16-bit Capture, 200 ns (max. resolution)
- 2.3V to 5.5V (PIC16F1526/7)
- 16-bit Compare, 200 ns (max. resolution)
• Self-Programmable under Software Control
- 10-bit PWM, 20 kHz @ 10 bits
• Power-on Reset (POR)
(max. frequency)
• Power-up Timer (PWRT)
• Two Master Synchronous Serial Ports (MSSPs)
• Programmable Low-Power Brown-Out Reset
with SPI and I2 CTM with:
(LPBOR)
- 7-bit address masking
• Extended Watch-Dog Timer (WDT):
- SMBus/PMBusTM compatibility
- Programmable period from 1 ms to 256s
- Auto-wake-up on start
• Programmable Code Protection
• Two Enhanced Universal Synchronous
• In-Circuit Serial Programming™ (ICSP™) via two
Asynchronous Receiver Transmitters (EUSART):
pins
- RS-232, RS-485 and LIN compatible
• In-Circuit Debug (ICD) via Two Pins
- Auto-Baud Detect
• Enhanced Low-Voltage Programming (LVP)
• Power-Saving Sleep mode
 2011-2015 Microchip Technology Inc. DS40001458D-page 1

PIC16(L)F1526/7
PIC16(L)F151X/152X Family Types
High-Endurance Flash (bytes)

ADC
Program Memory
Data Sheet Index
MSSP (I2C/SPI)
Advanced Control
Flash (words)
Data SRAM
(8/16-bit)
EUSART
Debug(1)
(bytes)
Timers
I/O’s(2)
10-bit (ch)
CCP
XLP
Device
PIC16(L)F1512 (1) 2048 128 128 25 17 Y 2/1 1 1 2 I Y

PIC16(L)F1513 (1) 4096 256 128 25 17 Y 2/1 1 1 2 I Y
PIC16(L)F1516 (2) 8192 512 128 25 17 N 2/1 1 1 2 I Y
PIC16(L)F1517 (2) 8192 512 128 36 28 N 2/1 1 1 2 I Y
PIC16(L)F1518 (2) 16384 1024 128 25 17 N 2/1 1 1 2 I Y
PIC16(L)F1519 (2) 16384 1024 128 36 28 N 2/1 1 1 2 I Y
PIC16(L)F1526 (3) 8192 768 128 54 30 N 6/3 2 2 10 I Y
PIC16(L)F1527 (3) 16384 1536 128 54 30 N 6/3 2 2 10 I Y
Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS41624 PIC16(L)F1512/13 Data Sheet, 28-Pin Flash, 8-bit Microcontrollers.
2: DS41452 PIC16(L)F1516/7/8/9 Data Sheet, 28/40/44-Pin Flash, 8-bit MCUs.
3: DS41458 PIC16(L)F1526/7 Data Sheet, 64-Pin Flash, 8-bit MCUs.
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
DS40001458D-page 2  2011-2015 Microchip Technology Inc.

PIC16(L)F1526/7
FIGURE 1: 64-PIN TQFP (10MM X 10MM) PACKAGE DIAGRAM FOR PIC16(L)F1526/7
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE2
RE3
RE4
RE5
RE6
RE7
VDD
VSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1 1 48 RB0
RE0 2 47 RB1
RG0 3 46 RB2
RG1 4 45 RB3
RG2 5 44 RB4
RG3 6 43 RB5
VPP/MCLR/RG5 7 42 RB6
RG4 8 PIC16(L)F1526 41 VSS
VSS 9 PIC16(L)F1527 40 RA6
VDD 10 39 RA7
RF7 11 38 VDD
RF6 12 37 RB7
RF5 13 36 RC5
RF4 14 35 RC4
RF3 15 34 RC3
RF2 16 33 RC2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RF1
RF0
RA3
RA2
RA5
RC1
RC0
RC6
RC7
RA1
RA0
RA4
AVSS
VSS
AVDD
VDD
Note 1: See Table 1 for list of pin peripheral function.

PIC16(L)F1526/7
FIGURE 2: 64-PIN QFN (9MM X 9MM) PACKAGE DIAGRAM FOR PIC16(L)F1526/7
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE2
RE3
RE4
RE5
RE6
RE7
VDD
VSS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RE1 1 48 RB0
RE0 2 47 RB1
RG0 3 46 RB2
RG1 4 45 RB3
RG2 5 44 RB4
RG3 6 43 RB5
VPP/MCLR/RG5 7 42 RB6
RG4 8 PIC16(L)F1526 41 VSS
VSS 9 PIC16(L)F1527 40 RA6
VDD 10 39 RA7
RF7 11 38 VDD
RF6 12 37 RB7
RF5 13 36 RC5
RF4 14 35 RC4
RF3 15 34 RC3
RF2 16 33 RC2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RF1
RF0
RA3
RA2
RA5
RC1
RC0
RC6
RC7
RA1
RA0
RA4
AVSS
VSS
AVDD
VDD
Note 1: See Table 1 for list of pin peripheral function.

PIC16(L)F1526/7
TABLE 1: 64-PIN DEVICE ALLOCATION TABLE (PIC16(L)F1526/7)
64-Pin TQFP, QFN
Interrupt
USART
Pull-up
Timers
Basic
ADC
CCP
SSP
I/O
RA0 24 AN0 — — — — — — —
RA1 23 AN1 — — — — — — —
RA2 22 AN2 — — — — — — —
RA3 21 AN3 — — — — — — VREF+
RA4 28 — T0CKI — — — — — —
RA5 27 AN4 T3G — — — — — —
RA6 40 — — — — — — — OSC2/CLKOUT
RA7 39 — — — — — — — OSC1/CLKIN
RB0 48 AN17 — — — — INT/ Y —
IOC
RB1 47 AN18 — — — — IOC Y —
RB2 46 AN19 — — — — IOC Y —
RB3 45 AN20 — — — — IOC Y —
RB4 44 AN21 T3CKI(1) — — — IOC Y —
RB5 43 AN22 T1G/T3CKI — — — IOC Y —
RB6 42 — — — — — IOC Y ICSPCLK/ICDCLK
RB7 37 — — — — — IOC Y ICSPDAT/ICDDAT
RC0 30 — SOSCO/T1CKI — — — — — —
RC1 29 — SOSCI CCP2 — — — — —
RC2 33 — — CCP1 — — — — —
RC3 34 — — — — SCK1/SCL1 — — —
RC4 35 — — — — SDI1/SDA1 — — —
RC5 36 — — — — SDO1 — — —
RC6 31 — — — TX1/CK1 — — — —
RC7 32 — — — RX1/DT1 — — — —
RD0 58 AN23 — — — — — Y —
RD1 55 AN24 T5CKI — — — — Y —
RD2 54 AN25 — — — — — Y —
RD3 53 AN26 — — — — — Y —
RD4 52 — — — — SDO2 — Y —
RD5 51 — — — — SDI2, SDA2 — Y —
RD6 50 — — — — SCK2, SCL2 — Y —
RD7 49 — — — — SS2 — Y —
RE0 2 AN27 — — — — Y —
RE1 1 AN28 — — — — — Y —
RE2 64 AN29 — CCP10 — — — Y —
RE3 63 — — CCP9 — — — Y —
RE4 62 — — CCP8 — — — Y —
RE5 61 — — CCP7 — — — Y —
RE6 60 — — CCP6 — — — Y —
Note 1: Alternate pin function selected with the APFCON (Register 12-1) register.
2: Weak pull-up is always enabled when MCLR is enabled, otherwise the pull-up is under user control.

PIC16(L)F1526/7
TABLE 1: 64-PIN DEVICE ALLOCATION TABLE (PIC16(L)F1526/7) (CONTINUED)
64-Pin TQFP, QFN
Interrupt
USART
Pull-up
Timers
Basic
ADC
CCP
SSP
I/O
RE7 59 — — CCP2(1) — — — Y —
RF0 18 AN16 — — — — — — VCAP
RF1 17 AN6 — — — — — — —
RF2 16 AN7 — — — — — — —
RF3 15 AN8 — — — — — — —
RF4 14 AN9 — — — — — — —
RF5 13 AN10 — — — — — — —
RF6 12 AN11 — — — — — — —
RF7 11 AN5 — — — SS1 — — —
RG0 3 — — CCP3 — — — — —
RG1 4 AN15 — — TX2/CK2 — — — —
RG2 5 AN14 — — RX2/DT2 — — — —
RG3 6 AN13 — CCP4 — — — — —
RG4 8 AN12 T5G CCP5 — — — — —
RG5 7 — — — — — — Y(2) MCLR/VPP
VDD 10, 26, — — — — — — — VDD
38, 57
VSS 9, 25, — — — — — — — VSS
41, 56
AVDD 19 — — — — — — — AVDD
AVSS 20 — — — — — — — AVSS
2: Weak pull-up is always enabled when MCLR is enabled, otherwise the pull-up is under user control.

PIC16(L)F1526/7
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15
3.0 Memory Organization ................................................................................................................................................................. 17
4.0 Device Configuration .................................................................................................................................................................. 42
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 48
6.0 Resets ........................................................................................................................................................................................ 63
7.0 Interrupts .................................................................................................................................................................................... 71
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 86
9.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 90
10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 91
11.0 Flash Program Memory Control ................................................................................................................................................. 95
12.0 I/O Ports ................................................................................................................................................................................... 111
13.0 Interrupt-on-Change ................................................................................................................................................................. 135
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 139
15.0 Temperature Indicator Module ................................................................................................................................................. 141
16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 143
17.0 Timer0 Module ......................................................................................................................................................................... 156
18.0 Timer1/3/5 Modules.................................................................................................................................................................. 159
19.0 Timer2/4/6/8/10 Modules.......................................................................................................................................................... 171
20.0 Capture/Compare/PWM Module .............................................................................................................................................. 175
21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 193
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 248
23.0 In-Circuit Serial Programming™ (ICSP™) ................................................................................................................................ 278
24.0 Instruction Set Summary .......................................................................................................................................................... 280
25.0 Electrical Specifications............................................................................................................................................................ 294
26.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 324
27.0 Development Support............................................................................................................................................................... 358
28.0 Packaging Information.............................................................................................................................................................. 362
Appendix A: Revision History............................................................................................................................................................. 369
The Microchip Web Site ..................................................................................................................................................................... 371
Customer Change Notification Service .............................................................................................................................................. 371
Customer Support .............................................................................................................................................................................. 371
Product Identification System ............................................................................................................................................................ 370

PIC16(L)F1526/7
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PIC16(L)F1526/7
1.0 DEVICE OVERVIEW
The PIC16(L)F1526/7 are described within this data
sheet. They are available in 64-pin packages. Figure 1-1
shows a block diagram of the PIC16(L)F1526/7 devices.
Table 1-2 shows the pinout descriptions.
Reference Table 1-1 for peripherals available per
device.
TABLE 1-1: DEVICE PERIPHERAL

SUMMARY
PIC16LF1527
PIC16LF1526
PIC16F1526
PIC16F1527
Peripheral
ADC ● ●
EUSART ● ●
Fixed Voltage Reference (FVR) ● ●
Temperature Indicator ● ●
Capture/Compare/PWM Modules
CCP1 ● ●
CCP2 ● ●
CCP3 ● ●
CCP4 ● ●
CCP5 ● ●
CCP6 ● ●
CCP7 ● ●
CCP8 ● ●
CCP9 ● ●
CCP10 ● ●
EUSARTs
EUSART1 ● ●
EUSART2 ● ●
Master Synchronous Serial Ports
MSSP1 ● ●
MSSP2 ● ●
Timers
Timer0 ● ●
Timer1/3/5 ● ●
Timer2/4/6 ● ●
/8/10

PIC16(L)F1526/7
FIGURE 1-1: PIC16(L)F1526/7 BLOCK DIAGRAM
PORTA
Program
Flash Memory
RAM
PORTB
OSC2/CLKOUT Timing
Generation PORTC
OSC1/CLKIN INTRC
CPU
Oscillator
(Figure 2-1) PORTD
MCLR
PORTE
PORTF
Timer0 Timer1/3/5 Timer2/4/6/8/10 EUSARTs
PORTG
Temp. ADC
CCP1-10 MSSPs Indicator FVR
10-Bit
Note 1: See applicable chapters for more information on peripherals.

2: See Table 1-1 for peripherals available on specific devices.

PIC16(L)F1526/7
TABLE 1-2: PIC16(L)F1526/7 PINOUT DESCRIPTION

Input Output
Name Function Description
Type Type
RA0/AN0 RA0 TTL CMOS General purpose I/O.

AN0 AN — ADC Channel 0 input.
RA3/AN3/VREF+ RA3 TTL CMOS General purpose I/O.
VREF+ AN — ADC Positive Voltage Reference input.
RA4/T0CKI RA4 TTL CMOS General purpose I/O.
T0CKI ST — Timer0 clock input.
RA5/AN4/T3G RA5 TTL CMOS General purpose I/O.
T3G ST — Timer3 gate input.
RA6/OSC2/CLKOUT RA6 TTL CMOS General purpose I/O.
OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).
CLKOUT — CMOS FOSC/4 output.
RA7/OSC1/CLKIN RA7 TTL CMOS General purpose I/O.
OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).
CLKIN ST — External clock input (EC mode).
RB0/AN17/INT RB0 TTL CMOS General purpose I/O with IOC and WPU.
INT ST — External interrupt.
RB1/AN18 RB1 TTL CMOS General purpose I/O with IOC and WPU.
RB4/AN21/T3CKI(1) RB4 TTL CMOS General purpose I/O with IOC and WPU.
RB5/AN22/T1G/T3CKI RB5 TTL CMOS General purpose I/O with IOC and WPU.
RB6/ICSPCLK/ICDCLK RB6 TTL CMOS General purpose I/O with IOC and WPU.
ICSPCLK ST — Serial Programming Clock.
ICDCLK ST — In-Circuit Debug Clock.
RB7/ICSPDAT/ICDDAT RB7 TTL CMOS General purpose I/O with IOC and WPU.
ICSPDAT ST CMOS ICSP™ Data I/O.
ICDDAT ST CMOS In-Circuit Data I/O.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
2: RC3, RC4, RD5 and RD6 read the I2C ST input when I2C mode is enabled.

PIC16(L)F1526/7
TABLE 1-2: PIC16(L)F1526/7 PINOUT DESCRIPTION (CONTINUED)
Input Output
Type Type
RC0/SOSCO/T1CKI RC0 ST CMOS General purpose I/O.
SOSCO XTAL XTAL Timer1/3/5 oscillator connection.
T1CKI ST — Timer1/3/5 clock input.
RC1/SOSCI/CCP2 RC1 ST CMOS General purpose I/O.
SOSCI XTAL XTAL Timer1/3/5 oscillator connection.
CCP2 ST CMOS Capture/Compare/PWM2.
RC2/CCP1 RC2 ST CMOS General purpose I/O.
RC3/SCK1/SCL1(2) RC3 ST CMOS General purpose I/O.
SCK1 ST CMOS SPI clock.
SCL1 I2C OD I2C clock.
(2)
RC4/SDI1/SDA1 RC4 ST CMOS General purpose I/O.
SDI1 ST — SPI data input.
2
SDA1 I C OD I2C data input/output.
RC5/SDO1 RC5 ST CMOS General purpose I/O.
SDO1 — CMOS SPI data output.
RC6/TX1/CK1 RC6 ST CMOS General purpose I/O.
TX1 — CMOS USART1 asynchronous transmit.
CK1 ST CMOS USART1 synchronous clock.
RC7/RX1/DT1 RC7 ST CMOS General purpose I/O.
RX1 ST — USART1 asynchronous input.
DT1 ST CMOS USART1 synchronous data.
RDO/AN23 RD0 ST CMOS General purpose I/O with WPU.
RD1/AN24/T5CKI RD1 ST CMOS General purpose I/O with WPU.
RD2/AN25 RD2 ST CMOS General purpose I/O with WPU.
RD3/AN26 RD3 ST CMOS General purpose I/O with WPU.
RD4/SDO2 RD4 ST CMOS General purpose I/O with WPU.
SDO2 — CMOS SPI data output.
RD5/SDI2/SDA2(2) RD5 ST CMOS General purpose I/O with WPU.
SDI2 ST — SPI data input.
SDA2 I2C OD I2C data input/output.
RD6/SCK2/SCL2(2) RD6 ST CMOS General purpose I/O with WPU.
SCK2 ST CMOS SPI clock.
SCL2 I2C OD I2C clock.
RD7/SS2 RD7 ST CMOS General purpose I/O with WPU.
SS2 ST — Slave Select input.
RE0/AN27 RE0 ST CMOS General purpose I/O with WPU.

PIC16(L)F1526/7
Input Output
Type Type
RE1/AN28 RE1 ST CMOS General purpose I/O with WPU.
RE2/AN29/CCP10 RE2 ST CMOS General purpose I/O with WPU.
RE3/CCP9 RE3 ST CMOS General purpose I/O with WPU.
RE7/CCP2(1) RE7 ST CMOS General purpose I/O with WPU.
RF0/AN16/VCAP RF0 ST CMOS General purpose I/O.
VCAP Power Power Filter capacitor for Voltage Regulator.
RF1/AN6 RF1 ST CMOS General purpose I/O.
RF7/AN5/SS1 RF7 ST CMOS General purpose I/O.
SS1 ST — Slave Select input.
RG0/CCP3 RG0 ST CMOS General purpose I/O.
RG1/AN15/TX2/CK2 RG1 ST CMOS General purpose I/O.
TX2 — CMOS USART2 asynchronous transmit.
CK2 ST CMOS USART2 synchronous clock.
RG2/AN14/RX2/DT2 RG2 ST CMOS General purpose I/O.
RX2 ST — USART2 asynchronous input.
DT2 ST CMOS USART2 synchronous data.

PIC16(L)F1526/7
Input Output
Type Type
RG3/AN13/CCP4 RG3 ST CMOS General purpose I/O.
RG4/AN12/T5G/CCP5 RG4 ST — General purpose input.
RG5/MCLR/VPP RG5 ST — General purpose input with WPU.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Programming voltage.
AVDD AVDD Power — Analog positive supply.
AVSS AVSS Power — Analog ground reference.
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.

PIC16(L)F1526/7
2.0 ENHANCED MID-RANGE CPU Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
This family of devices contain an enhanced mid-range program and data memory.
8-bit CPU core. The CPU has 49 instructions. Interrupt
• Automatic Interrupt Context Saving
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and • 16-level Stack with Overflow and Underflow
Underflow Reset capability. Direct, Indirect, and • File Select Registers
• Instruction Set
FIGURE 2-1: CORE BLOCK DIAGRAM
15
Configuration
Configuration 8
15 Data Bus
Program Counter
Flash
MUX
Program
Memory 16-Level
8 Level Stack
Stack
RAM
(13-bit)
(15-bit)
Program
14 Program Memory 12 RAM Addr
Bus
Read (PMR)
Addr MUX
Instruction
Instruction Reg
reg Indirect
Direct Addr 7 Addr
5 12 12
15 BSR
FSR Reg
reg
FSR0reg
FSR Reg
FSR1 Reg
FSR reg
15 STATUS Reg
STATUS reg
8
3 MUX
Power-up
Timer
Instruction Oscillator
Decodeand
Decode & Start-up Timer
ALU
Control
CLKIN Power-on
Reset 8
Timing Watchdog
CLKOUT Generation Timer W Reg
Brown-out
Reset
Internal
Oscillator
Block
VDD VSS

PIC16(L)F1526/7
2.1 Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2 16-level Stack with Overflow and

Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under-
flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a soft-
ware Reset. See Section 3.7 “Stack” for more details.
2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.8 “Indirect Addressing” for more details.
2.4 Instruction Set

There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 24.0 “Instruction Set Summary” for more
details.

PIC16(L)F1526/7
3.0 MEMORY ORGANIZATION wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is
These devices contain the following types of memory: at 0004h (see Figure 3-1 and Figure 3-2).
• Program Memory
- Configuration Words 3.2 High Endurance Flash
- Device ID This device has a 128-byte section of high-endurance
- User ID Program Flash Memory (PFM) in lieu of data EEPROM.
- Flash Program Memory This area is especially well suited for nonvolatile data
• Data Memory storage that is expected to be updated frequently over
the life of the end product. See Section 11.2 “Flash
- Core Registers
Program Memory Overview” for more information on
- Special Function Registers writing data to PFM. Refer to section Section 3.2.1.2
- General Purpose RAM “Indirect Read with FSR” for more information about
- Common RAM using the FSR registers to read byte data stored in
The following features are associated with access and PFM.
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for the PIC16(L)F1526/7 family. Accessing
a location above these boundaries will cause a
TABLE 3-1: DEVICE SIZES AND ADDRESSES

Program Memory Last Program Memory High-Endurance Flash
Device
Space (Words) Address Memory Address Range (1)
PIC16F1526
8,192 1FFFh 1F80h-1FFFh
PIC16LF1526
PIC16F1527
16,384 3FFFh 3F80h-3FFFh
PIC16LF1527
Note 1: High-endurance Flash applies to the low byte of each address in the range.

PIC16(L)F1526/7
FIGURE 3-1: PROGRAM MEMORY MAP FIGURE 3-2: PROGRAM MEMORY MAP
AND STACK FOR AND STACK FOR
PIC16(L)F1526 PIC16(L)F1527
PC<14:0> PC<14:0>
CALL, CALLW 15
RETURN, RETLW
CALL, CALLW 15
RETURN, RETLW
Interrupt, RETFIE Interrupt, RETFIE
Stack Level 0 Stack Level 0
Reset Vector 0000h Reset Vector 0000h
Interrupt Vector 0004h Interrupt Vector 0004h

0005h 0005h
Page 0 Page 0
07FFh 07FFh
0800h 0800h
Page 1 Page 1
On-chip 0FFFh
Program 0FFFh
Memory 1000h 1000h
Page 2 On-chip Page 2
17FFh Program 17FFh
1800h Memory 1800h
Page 3 Page 3
1FFFh 1FFFh
Rollover to Page 0 2000h Page 4 2000h
Page 7
3FFFh
Rollover to Page 0 4000h
Rollover to Page 3 Rollover to Page 7

7FFFh 7FFFh

PIC16(L)F1526/7
3.2.1 READING PROGRAM MEMORY AS EXAMPLE 3-2: ACCESSING PROGRAM
DATA MEMORY VIA FSR
There are two methods of accessing constants in pro- constants
DW DATA0 ;First constant
gram memory. The first method is to use tables of
DW DATA1 ;Second constant
RETLW instructions. The second method is to set an
DW DATA2
FSR to point to the program memory. DW DATA3
my_function
3.2.1.1 RETLW Instruction ;… LOTS OF CODE…
The RETLW instruction can be used to provide access MOVLW DATA_INDEX
to tables of constants. The recommended way to create ADDLW LOW constants
MOVWF FSR1L
such a table is shown in Example 3-1.
MOVLW HIGH constants ;Msb is set
automatically
EXAMPLE 3-1: RETLW INSTRUCTION MOVWF FSR1H
constants BTFSC STATUS,C ;carry from
BRW ;Add Index in W to ADDLW?
;program counter to INCF FSR1H,f ;yes
;select data MOVIW 0[FSR1]
RETLW DATA0 ;Index0 data ;THE PROGRAM MEMORY IS IN W
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
CALL constants
;… THE CONSTANT IS IN W
The BRW instruction makes this type of table very sim-

ple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
3.2.1.2 Indirect Read with FSR

The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access-
ing the program memory via an FSR.
The high directive will set bit<7> if a label points to a
location in program memory.

PIC16(L)F1526/7
3.3 Data Memory Organization 3.3.1 CORE REGISTERS
The data memory is partitioned in 32 memory banks The core registers contain the registers that directly
with 128 bytes in a bank. Each bank consists of affect the basic operation. The core registers occupy
(Figure 3-3): the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
• 12 core registers registers are listed below in Table 3-2. For detailed
• 20 Special Function Registers (SFR) information, see Table 3-4.
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM TABLE 3-2: CORE REGISTERS
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be Addresses BANKx
accessed either directly (via instructions that use the x00h or x80h INDF0
file registers) or indirectly via the two File Select x01h or x81h INDF1
Registers (FSR). See Section 3.8 “Indirect x02h or x82h PCL
Addressing” for more information. x03h or x83h STATUS
Data memory uses a 12-bit address. The upper seven x04h or x84h FSR0L
bits of the address define the Bank address and the x05h or x85h FSR0H
lower five bits select the registers/RAM in that bank. x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON

PIC16(L)F1526/7
3.3.1.1 STATUS Register For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 3-1, contains:
as ‘000u u1uu’ (where u = unchanged).
• the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
• the Reset status SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any STATUS register, because these instructions do not
instruction, like any other register. If the STATUS affect any Status bits. For other instructions not
register is the destination for an instruction that affects affecting any Status bits (Refer to Section 24.0
the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”).
disabled. These bits are set or cleared according to the
Note 1: The C and DC bits operate as Borrow and
device logic. Furthermore, the TO and PD bits are not
Digit Borrow out bits, respectively, in
writable. Therefore, the result of an instruction with the
subtraction.
STATUS register as destination may be different than
intended.
3.4 Register Definitions: Status
REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — — TO PD Z DC(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.

PIC16(L)F1526/7
3.5 Special Function Register FIGURE 3-3: BANKED MEMORY
PARTITIONING
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function 7-bit Bank Offset Memory Region
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
00h
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the Core Registers
appropriate peripheral chapter of this data sheet. (12 bytes)
0Bh
3.5.1 GENERAL PURPOSE RAM 0Ch
Special Function Registers
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20 (20 bytes maximum)
bytes after the core registers of every data memory 1Fh
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 20h
3.5.1.1 Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.8.2
“Linear Data Memory” for more information. General Purpose RAM
(80 bytes maximum)
3.5.2 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.5.3 DEVICE MEMORY MAPS

The memory maps for PIC16(L)F1526/7 are shown in
Table 3-3.

TABLE 3-3: PIC16(L)F1526/7 MEMORY MAP
 2011-2015 Microchip Technology Inc.
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch — 28Ch PORTF 30Ch TRISF 38Ch LATF
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh PORTG 30Dh TRISG 38Dh LATG
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh — 20Eh — 28Eh — 30Eh — 38Eh —
00Fh PORTD 08Fh TRISD 10Fh LATD 18Fh ANSELD 20Fh WPUD 28Fh — 30Fh — 38Fh —
010h PORTE 090h TRISE 110h LATE 190h ANSELE 210h WPUE 290h — 310h — 390h —
011h PIR1 091h PIE1 111h — 191h PMADRL 211h SSP1BUF 291h CCPR1L 311h CCPR3L 391h —
012h PIR2 092h PIE2 112h — 192h PMADRH 212h SSP1ADD 292h CCPR1H 312h CCPR3H 392h —
013h PIR3 093h PIE3 113h — 193h PMDATL 213h SSP1MSK 293h CCP1CON 313h CCP3CON 393h —
014h PIR4 094h PIE4 114h — 194h PMDATH 214h SSP1STAT 294h — 314h — 394h IOCBP
015h TMR0 095h OPTION_REG 115h — 195h PMCON1 215h SSP1CON1 295h — 315h — 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h — 316h — 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSP1CON3 297h — 317h — 397h —
018h T1CON 098h — 118h — 198h — 218h — 298h CCPR2L 318h CCPR4L 398h —
019h T1GCON 099h OSCCON 119h — 199h RC1REG 219h SSP2BUF 299h CCPR2H 319h CCPR4H 399h —
01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TX1REG 21Ah SSP2ADD 29Ah CCP2CON 31Ah CCP4CON 39Ah —
01Bh PR2 09Bh ADRESL 11Bh — 19Bh SP1BRG 21Bh SSP2MSK 29Bh — 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SP1BRGH 21Ch SSP2STAT 29Ch — 31Ch CCPR5L 39Ch —
01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RC1STA 21Dh SSP2CON1 29Dh CCPTMRS0 31Dh CCPR5H 39Dh —
01Eh — 09Eh ADCON1 11Eh — 19Eh TX1STA 21Eh SSP2CON2 29Eh CCPTMRS1 31Eh CCP5CON 39Eh —
01Fh — 09Fh — 11Fh — 19Fh BAUD1CON 21Fh SSP2CON3 29Fh CCPTMRS2 31Fh — 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h
General General General General General General General General
Purpose Purpose Purpose Purpose Purpose Purpose Purpose Purpose
Register Register Register Register Register Register Register Register
80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes
PIC16(L)F1526/7
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
Common RAM (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh)
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: PIC16F1526/7 only.

DS40001458D-page 23
TABLE 3-3: PIC16(L)F1526/7 MEMORY MAP (CONTINUED)
DS40001458D-page 24
PIC16(L)F1526/7
400h 480h 500h 580h 600h 680h 700h 780h
40Bh 48Bh 50Bh 58Bh 60Bh 68Bh 70Bh 78Bh
40Ch ANSELF 48Ch — 50Ch 58Ch — 60Ch — 68Ch 70Ch 78Ch
40Dh ANSELG 48Dh WPUG 58Dh — 60Dh —
40Eh — 48Eh — 58Eh — 60Eh —
40Fh — 48Fh — 58Fh — 60Fh —
410h — 490h — 590h — 610h —
411h TMR3L 491h RC2REG 591h — 611h CCPR6L
412h TMR3H 492h TX2REG 592h — 612h CCPR6H
413h T3CON 493h SP2BRG 593h — 613h CCP6CON
414h T3GCON 494h SP2BRGH 594h — 614h CCPR7L
TMR4 RC2STA Unimplemented TMR8 CCPR7H Unimplemented Unimplemented Unimplemented
415h 495h 595h 615h
416h PR4 496h TX2STA Read as ‘0’ 596h PR8 616h CCP7CON Read as ‘0’ Read as ‘0’ Read as ‘0’
417h T4CON 497h BAUD2CON 597h T8CON 617h CCPR8L
418h TMR5L 498h — 598h — 618h CCPR8H
419h TMR5H 499h — 599h — 619h CCP8CON
41Ah T5CON 49Ah — 59Ah — 61Ah CCPR9L
41Bh T5GCON 49Bh — 59Bh — 61Bh CCPR9H
41Ch TMR6 49Ch — 59Ch TMR10 61Ch CCP9CON
41Dh PR6 49Dh — 59Dh PR10 61Dh CCPR10L
41Eh T6CON 49Eh — 59Eh T10CON 61Eh CCPR10H
41Fh — 49Fh — 51Fh 59Fh — 61Fh CCP10CON 69Fh 71Fh 79Fh
420h 4A0h General Purpose 520h 5A0h 620h 6A0h 720h 7A0h
General Register General General General General General General

Purpose 4BFh 32 Bytes Purpose Purpose Purpose Purpose Purpose Purpose
Register 4C0h General Purpose Register Register Register Register Register Register
80 Bytes 80 Bytes(1) 80 Bytes(1) 80 Bytes(1) 80 Bytes(1) 80 Bytes(1) 80 Bytes(1)
Register
46Fh 4EFh 48 Bytes(1) 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h 4F0h 570h 5F0h 670h 6F0h 770h 7F0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh)
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
Note 1: PIC16(L)F1527 only.
TABLE 3-3: PIC16(L)F1526/7 MEMORY MAP (CONTINUED)

800h 880h 900h 980h A00h A80h B00h B80h
80Bh 88Bh 90Bh 98Bh A0Bh A8Bh B0Bh B8Bh
80Ch 88Ch 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch
Unimplemented Unimplemented Unimplemented
Read as ‘0’ Read as ‘0’ Read as ‘0’
81Fh 89Fh 91Fh Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
820h 8A0h 920h Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
General General General
Purpose Purpose Purpose
Register Register Register
80 Bytes(1) 80 Bytes(1) 80 Bytes(1) 9EFh AEFh BEFh
86Fh 8EFh 96Fh A6Fh B6Fh
870h 8F0h 970h 9F0h A70h AF0h B70h BF0h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh)
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30

C00h C80h D00h D80h E00h E80h F00h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
C0Bh C8Bh D0Bh D8Bh E0Bh E8Bh F0Bh
C0Ch C8Ch D0Ch D8Ch E0Ch E8Ch F0Ch
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’ Read as ‘0’
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh
C70h CF0h D70h DF0h E70h EF0h F70h
Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM Common RAM
(Accesses (Accesses (Accesses (Accesses (Accesses (Accesses (Accesses
70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh) 70h – 7Fh)
PIC16(L)F1526/7
C7Fh CFFh D7Fh DFFh E7Fh EFFh F7Fh

DS40001458D-page 25
TABLE 3-3: PIC16(L)F1526 MEMORY MAP (CONTINUED)
DS40001458D-page 26
PIC16(L)F1526/7
Bank 31
F80h
Core Registers
(Table 3-2)
F8Bh
F8Ch
Unimplemented
Read as ‘0’
FE3h
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
FE7h PCLATH_SHAD
FE8h FSR0L_SHAD
FE9h FSR0H_SHAD
FEAh FSR1L_SHAD
FEBh FSR1H_SHAD
FECh —
FEDh STKPTR
FEEh TOSL
FEFh TOSH
FF0h
Common RAM
(Accesses
70h – 7Fh)
FFFh

PIC16(L)F1526/7
3.5.4 CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3-4 can be
addressed from any Bank.
TABLE 3-4: CORE FUNCTION REGISTERS SUMMARY

Value on Value on all
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
Bank 0-31
x00h or Addressing this location uses contents of FSR0H/FSR0L to address data memory
INDF0 xxxx xxxx uuuu uuuu
x80h (not a physical register)
x01h or Addressing this location uses contents of FSR1H/FSR1L to address data memory
INDF1 xxxx xxxx uuuu uuuu
x81h (not a physical register)
x02h or
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x82h
x03h or
STATUS — — — TO PD Z DC C ---1 1000 ---q quuu
x83h
x04h or
FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x84h
x05h or
FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x85h
x06h or
FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x86h
x07h or
FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x87h
x08h or
BSR — — — BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000
x88h
x09h or
WREG Working Register 0000 0000 uuuu uuuu
x89h
x0Ah or
PCLATH — Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000
x8Ah
x0Bh or
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
x8Bh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.

PIC16(L)F1526/7
TABLE 3-2: SPECIAL FUNCTION REGISTER SUMMARY

Value on
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
Bank 0
00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu
00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
00Fh PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
010h PORTE PORTE Data Latch when written: PORTE pins when read xxxx xxxx uuuu uuuu
011h PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
012h PIR2 OSFIF TMR5GIF TMR3GIF — BCL1IF TMR10IF TMR8IF CCP2IF 000- 0000 000- 0000
013h PIR3 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF 0000 0000 0000 0000
014h PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 0000 0000 0000 0000
015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC — TMR1ON 0000 00-0 uuuu uu-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
DONE
01Ah TMR2 Timer 2 Module Register 0000 0000 0000 0000
01Bh PR2 Timer 2 Period Register 1111 1111 1111 1111
01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
01Dh — Unimplemented — —
01Eh — Unimplemented — —
01Fh — Unimplemented — —
Bank 1
08Ch TRISA PORTA Data Direction Register 1111 1111 1111 1111
08Dh TRISB PORTB Data Direction Register 1111 1111 1111 1111
08Eh TRISC PORTC Data Direction Register 1111 1111 1111 1111
08Fh TRISD PORTD Data Direction Register 1111 1111 1111 1111
090h TRISE PORTE Data Direction Register 1111 1111 1111 1111
091h PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
092h PIE2 OSFIE TMR5GIE TMR3GIE — BCL1IE TMR10IE TMR8IE CCP2IE 000- 0000 000- 0000
093h PIE3 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE 0000 0000 0000 0000
094h PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 0000 0000 0000 0000
095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 1111 1111 1111 1111
096h PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 00-1 11qq qq-q qquu
097h WDTCON — — WDTPS<4:0> SWDTEN --01 0110 --01 0110
098h — Unimplemented — —
099h OSCCON — IRCF<3:0> — SCS<1:0> -011 1-00 -011 1-00
09Ah OSCSTAT SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS 0-q0 --00 q-qq --0q
09Bh ADRESL ADC Result Register Low xxxx xxxx uuuu uuuu
09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu
09Dh ADCON0 — CHS<4:0> GO/DONE ADON -000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 0000 --00 0000 --00
2: Unimplemented, read as ‘1’.

PIC16(L)F1526/7
TABLE 3-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on
Value on
POR, BOR
Resets
Bank 2
10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu
10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu
10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu
10Fh LATD PORTD Data Latch xxxx xxxx uuuu uuuu
110h LATE PORTE Data Latch xxxx xxxx uuuu uuuu
111h
to — Unimplemented — —
115h
116h BORCON SBOREN BORFS — — — — — BORRDY 10-- ---q uu-- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR<1:0> 0q00 0000 0q00 0000
118h
11Ch
11Dh APFCON — — — — — — T3CKISEL CCP2SEL ---- --00 ---- --00
Bank 3
18Ch ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 --1- 1111
18Dh ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111
18Eh ANSELC Unimplemented — —
18Fh ANSELD — — — — ANSD3 ANSD2 ANSD1 ANSD0 ---- 1111 ---- 1111
190h ANSELE — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111
191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000
192h PMADRH —(2) Program Memory Address Register High Byte 1000 0000 1000 0000
193h PMDATL Program Memory Data Register Low Byte xxxx xxxx uuuu uuuu
194h PMDATH — — Program Memory Data Register High Byte --xx xxxx --uu uuuu
195h PMCON1 —(2) CFGS LWLO FREE WRERR WREN WR RD 1000 x000 1000 q000
196h PMCON2 Program Memory control register 2 0000 0000 0000 0000
197h VREGCON(1) — — — — — — VREGPM Reserved ---- --01 ---- --01
199h RC1REG USART Receive Data Register 0000 0000 0000 0000
19Ah TX1REG USART Transmit Data Register 0000 0000 0000 0000
19Bh SP1BRG BRG<7:0> 0000 0000 0000 0000
19Ch SP1BRGH BRG<15:8> 0000 0000 0000 0000
19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
19Fh BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00

PIC16(L)F1526/7
Value on
Value on
POR, BOR
Resets
Bank 4
20Ch — Unimplemented — —
20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
20Fh WPUD WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 1111 1111 1111 1111
210h WPUE WPUE7 WPUE6 WPUE5 WPUE4 WPUE3 WPUE2 WPUE1 WPUE0 1111 1111 1111 1111
211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
212h SSP1ADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
213h SSP1MSK Synchronous Serial Port (I2C mode) Address Mask Register 1111 1111 1111 1111
214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
219h SSP2BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
21Ah SSP2ADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
21Bh SSP2MSK Synchronous Serial Port (I2C mode) Address Mask Register 1111 1111 1111 1111
21Ch SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
21Dh SSP2CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000
21Eh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
21Fh SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000
Bank 5
28Ch PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx xxxx uuuu uuuu
28Dh PORTG — — RG5 RG4 RG3 RG2 RG1 RG0 --xx xxxx --uu uuuu
291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu
292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu
293h CCP1CON — — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000
29Ah CCP2CON — — DC2B<1:0> CCP2M<3:0> --00 0000 --00 0000
29Bh — Unimplemented — —
29Dh CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 0000 0000 0000 0000
29Eh CCPTMRS1 C8TSEL<1:0> C7TSEL<1:0> C6TSEL<1:0> C5TSEL<1:0> 0000 0000 0000 0000
29Fh CCPTMRS2 — — — — C10TSEL<1:0> C9TSEL<1:0> ---- 0000 ---- 0000

PIC16(L)F1526/7
Value on
Value on
POR, BOR
Resets
Bank 6
30Ch TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111
30Dh TRISG — — —(2) TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 --11 1111 --11 1111
313h CCP3CON — — DC3B<1:0> CCP3M<3:0> --00 0000 --00 0000
31Ah CCP4CON — — DC4B<1:0> CCP4M<3:0> --00 0000 --00 0000
31Bh — Unimplemented — —
31Ch CCPR5L Capture/Compare/PWM Register 5 (LSB) xxxx xxxx uuuu uuuu
31Dh CCPR5H Capture/Compare/PWM Register 5 (MSB) xxxx xxxx uuuu uuuu
31Eh CCP5CON — — DC5B<1:0> CCP5M<3:0> --00 0000 --00 0000
Bank 7
38Ch LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx xxxx uuuu uuuu
38Dh LATG — — — LATG4 LATG3 LATG2 LATG1 LATG0 ---x xxxx ---u uuuu
38Eh
393h
394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000
395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000
396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000
397h
39Fh

PIC16(L)F1526/7
Value on
Value on
POR, BOR
Resets
Bank 8
40Ch ANSELF ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0 1111 1111 1111 1111
40Dh ANSELG — — — ANSG4 ANSG3 ANSG2 ANSG1 — ---1 111- ---1 111-
413h T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC — TMR3ON 0000 00-0 uuuu uu-u
414h T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/ T3GVAL T3GSS<1:0> 0000 0x00 uuuu uxuu
DONE
415h TMR4 Timer 4 Module Register 0000 0000 0000 0000
416h PR4 Timer 4 Period Register 1111 1111 1111 1111
417h T4CON — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> -000 0000 -000 0000
41Ah T5CON TMR5CS<1:0> T5CKPS<1:0> SOSCEN T5SYNC — TMR5ON 0000 00-0 uuuu uu-u
41Bh T5GCON TMR5GE T5GPOL T5GTM T5GSPM T5GGO/ T5GVAL T5GSS<1:0> 0000 0x00 uuuu uxuu
DONE
41Ch TMR6 Timer 6 Module Register 0000 0000 0000 0000
41Dh PR6 Timer 6 Period Register 1111 1111 1111 1111
41Eh T6CON — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> -000 0000 -000 0000
Bank 9
48Dh WPUG — — WPUG5 — — — — — --1- ---- --1- ----
48Dh
490h
491h RC2REG USART Receive Data Register 0000 0000 0000 0000
492h TX2REG USART Transmit Data Register 0000 0000 0000 0000
493h SP2BRG BRG<7:0> 0000 0000 0000 0000
494h SP2BRGH BRG<15:8> 0000 0000 0000 0000
495h RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
496h TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
497h BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
498h
49Fh

PIC16(L)F1526/7
Value on
Value on
POR, BOR
Resets
Bank 10
50Ch
— — Unimplemented — —
51Fh
Bank 11
58Ch
594h
595h TMR8 Timer 8 Module Register 0000 0000 0000 0000
596h PR8 Timer 8 Period Register 1111 1111 1111 1111
597h T8CON — T8OUTPS<3:0> TMR8ON T8CKPS<1:0> -000 0000 -000 0000
598h
59Bh
59Ch TMR10 Timer 10 Module Register 0000 0000 0000 0000
59Dh PR10 Timer 10 Period Register 1111 1111 1111 1111
59Eh T10CON — T10OUTPS<3:0> TMR10ON T10CKPS<1:0> -000 0000 -000 0000
Bank 12
60Ch
610h
613h CCP6CON — — DC6B<1:0> CCP6M<3:0> --00 0000 --00 0000
616h CCP7CON — — DC7B<1:0> CCP7M<3:0> --00 0000 --00 0000
619h CCP8CON — — DC8B<1:0> CCP8M<3:0> --00 0000 --00 0000
61Ah CCPR9L Capture/Compare/PWM Register 9 (LSB) xxxx xxxx uuuu uuuu
61Bh CCPR9H Capture/Compare/PWM Register 9 (MSB) xxxx xxxx uuuu uuuu
61Ch CCP9CON — — DC9B<1:0> CCP9M<3:0> --00 0000 --00 0000
61Dh CCPR10L Capture/Compare/PWM Register 10 (LSB) xxxx xxxx uuuu uuuu
61Eh CCPR10H Capture/Compare/PWM Register 10 (MSB) xxxx xxxx uuuu uuuu
61Fh CCP10CON — — DC10B<1:0> CCP10M<3:0> --00 0000 --00 0000
Bank 13-30
x0Ch
or
x8Ch
x1Fh
or
x9Fh

PIC16(L)F1526/7
Value on
Value on
POR, BOR
Resets
Bank 31
F8Ch
FE3h
FE4h STATUS_SHAD — — — — — Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu
FE5h WREG_SHAD Working Register Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
FE6h BSR_SHAD — — — Bank Select Register Normal (Non-ICD) Shadow ---x xxxx ---u uuuu
FE7h PCLATH_SHAD — Program Counter Latch High Register Normal (Non-ICD) Shadow -xxx xxxx uuuu uuuu
FE8h FSR0L_SHAD Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
FE9h FSR0H_SHAD Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
FEAh FSR1L_SHAD Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
FEBh FSR1H_SHAD Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow xxxx xxxx uuuu uuuu
FECh — Unimplemented — —
FEDh STKPTR — — — Current Stack Pointer ---1 1111 ---1 1111
FEEh TOSL Top of Stack Low byte xxxx xxxx uuuu uuuu
FEFh TOSH — Top of Stack High byte -xxx xxxx -uuu uuuu

PIC16(L)F1526/7
3.6 PCL and PCLATH 3.6.2 COMPUTED GOTO
The Program Counter (PC) is 15 bits wide. The low byte A computed GOTO is accomplished by adding an offset to
comes from the PCL register, which is a readable and the program counter (ADDWF PCL). When performing a
writable register. The high byte (PC<14:8>) is not directly table read using a computed GOTO method, care should
readable or writable and comes from PCLATH. On any be exercised if the table location crosses a PCL memory
Reset, the PC is cleared. Figure 3-4 shows the five boundary (each 256-byte block). Refer to Application
situations for the loading of the PC. Note AN556, “Implementing a Table Read” (DS00556).
3.6.3 COMPUTED FUNCTION CALLS

FIGURE 3-4: LOADING OF PC IN
DIFFERENT SITUATIONS A computed function CALL allows programs to maintain
tables of functions and provide another way to execute
14 PCH PCL 0 Instruction with state machines or look-up tables. When performing a
PC PCL as
Destination table read using a computed function CALL, care
8
should be exercised if the table location crosses a PCL
6 7 0
ALU Result
memory boundary (each 256-byte block).
PCLATH
If using the CALL instruction, the PCH<2:0> and PCL
14
registers are loaded with the operand of the CALL
PCH PCL 0
PC GOTO, CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>.
The CALLW instruction enables computed calls by com-
6 4 0 11
bining PCLATH and W to form the destination address.
PCLATH OPCODE <10:0>
A computed CALLW is accomplished by loading the W
14 PCH PCL 0 register with the desired address and executing CALLW.
PC CALLW The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
6 7 0 8
PCLATH W
3.6.4 BRANCHING
14 PCH PCL 0 The branching instructions add an offset to the PC.
PC BRW This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
15 BRW and BRA. The PC will have incremented to fetch
PC + W the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
14 PCH PCL 0
PC BRA crossed.
If using BRW, load the W register with the desired
15 unsigned address and execute BRW. The entire PC will
PC + OPCODE <8:0>
be loaded with the address PC + 1 + W.
If using BRA, the entire PC will be loaded with PC + 1 +,
3.6.1 MODIFYING PCL
the signed value of the operand of the BRA instruction.
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by writ-
ing the desired upper 7 bits to the PCLATH register.
When the lower 8 bits are written to the PCL register, all
15 bits of the program counter will change to the values
contained in the PCLATH register and those being writ-
ten to the PCL register.

PIC16(L)F1526/7
3.7 Stack 3.7.1 ACCESSING THE STACK
All devices have a 16-level x 15-bit wide hardware The stack is available through the TOSH, TOSL and
stack (refer to Figures 3-5 through 3-8). The stack STKPTR registers. STKPTR is the current value of the
space is not part of either program or data space. The Stack Pointer. TOSH:TOSL register pair points to the
PC is PUSHed onto the stack when CALL or CALLW TOP of the stack. Both registers are read/writable. TOS
instructions are executed or an interrupt causes a is split into TOSH and TOSL due to the 15-bit size of the
branch. The stack is POPed in the event of a RETURN, PC. To access the stack, adjust the value of STKPTR,
RETLW or a RETFIE instruction execution. PCLATH is which will position TOSH:TOSL, then read/write to
not affected by a PUSH or POP operation. TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0’ (Configuration Words). This Note: Care should be taken when modifying the
means that after the stack has been PUSHed sixteen STKPTR while interrupts are enabled.
times, the seventeenth PUSH overwrites the value that
During normal program operation, CALL, CALLW and
was stored from the first PUSH. The eighteenth PUSH
Interrupts will increment STKPTR while RETLW,
overwrites the second PUSH (and so on). The
RETURN, and RETFIE will decrement STKPTR. At any
STKOVF and STKUNF flag bits will be set on an Over-
time STKPTR can be inspected to see how much stack
flow/Underflow, regardless of whether the Reset is
is left. The STKPTR always points at the currently used
enabled.
place on the stack. Therefore, a CALL or CALLW will
Note 1: There are no instructions/mnemonics increment the STKPTR and then write the PC, and a
called PUSH or POP. These are actions return will unload the PC and then decrement the
that occur from the execution of the STKPTR.
CALL, CALLW, RETURN, RETLW and Reference Figures 3-5 through 3-8 for examples of
RETFIE instructions or the vectoring to accessing the stack.
an interrupt address.
FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1
Stack Reset Disabled

TOSH:TOSL 0x0F STKPTR = 0x1F
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
0x0A
Initial Stack Configuration:
0x09
After Reset, the stack is empty. The
0x08 empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
0x07
Overflow/Underflow Reset is enabled, the
0x06 TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
0x05 disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x04
0x03
0x02
0x01
0x00
Stack Reset Enabled
TOSH:TOSL 0x1F 0x0000 STKPTR = 0x1F
(STVREN = 1)

PIC16(L)F1526/7
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09 This figure shows the stack configuration
after the first CALL or a single interrupt.
0x08 If a RETURN instruction is executed, the
0x07 return address will be placed in the
Program Counter and the Stack Pointer
0x06 decremented to the empty state (0x1F).
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL 0x00 Return Address STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an
0x0B interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
0x0A will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x09
0x08
0x07
0x05 Return Address

0x04 Return Address
0x03 Return Address
0x02 Return Address
0x01 Return Address
0x00 Return Address

PIC16(L)F1526/7
0x0F Return Address

0x0E Return Address
0x0D Return Address
0x0C Return Address
0x0B Return Address
0x0A Return Address
When the stack is full, the next CALL or
0x09 Return Address an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
0x08 Return Address so the stack will wrap and overwrite the
return address at 0x00. If the Stack
0x07 Return Address Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
0x06 Return Address not be overwritten.
0x05 Return Address
0x04 Return Address
0x03 Return Address
0x02 Return Address
0x01 Return Address
3.7.2 OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.8 Indirect Addressing

The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory

PIC16(L)F1526/7
FIGURE 3-9: INDIRECT ADDRESSING
0x0000 0x0000
Traditional
Data Memory
0x0FFF 0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR Reserved
0x7FFF
Address
Range 0x8000 0x0000
Program
Flash Memory
0xFFFF 0x7FFF
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.

PIC16(L)F1526/7
3.8.1 TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-10: TRADITIONAL DATA MEMORY MAP
Direct Addressing Indirect Addressing
4 BSR 0 6 From Opcode 0 7 FSRxH 0 7 FSRxL 0

0 0 0 0
Bank Select Location Select Bank Select Location Select

00000 00001 00010 11111
0x00
0x7F
Bank 0 Bank 1 Bank 2 Bank 31

PIC16(L)F1526/7
3.8.2 LINEAR DATA MEMORY 3.8.3 PROGRAM FLASH MEMORY
The linear data memory is the region from FSR To make constant data access easier, the entire
address 0x2000 to FSR address 0x29AF. This region is Program Flash Memory is mapped to the upper half of
a virtual region that points back to the 80-byte blocks of the FSR address space. When the MSB of FSRnH is
GPR memory in all the banks. set, the lower 15 bits are the address in program
Unimplemented memory reads as 0x00. Use of the memory which will be accessed through INDF. Only the
linear data memory region allows buffers to be larger lower 8 bits of each memory location is accessible via
than 80 bytes because incrementing the FSR beyond INDF. Writing to the Program Flash Memory cannot be
one bank will go directly to the GPR memory of the next accomplished via the FSR/INDF interface. All
bank. instructions that access Program Flash Memory via the
FSR/INDF interface will require one additional
The 16 bytes of common memory are not included in instruction cycle to complete.
the linear data memory region.
FIGURE 3-12: PROGRAM FLASH
FIGURE 3-11: LINEAR DATA MEMORY MEMORY MAP
MAP
7 FSRnH 0 7 FSRnL 0
7 FSRnH 0 7 FSRnL 0 1
0 0 1
Location Select 0x8000 0x0000
Location Select 0x2000 0x020
Bank 0
0x06F
0x0A0
Bank 1
Program
0x0EF Flash
0x120 Memory
Bank 2 (low 8
bits)
0x16F
0xF20
Bank 30 0x7FFF
0xFFFF
0x29AF 0xF6F

PIC16(L)F1526/7
4.0 DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
Code Protection and Device ID.
4.1 Configuration Words

There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note: The DEBUG bit in Configuration Word 2 is
managed automatically by device
development tools including debuggers and
programmers. For normal device operation,
this bit should be maintained as a '1'.

PIC16(L)F1526/7
4.2 Register Definitions: Configuration Words
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
FCMEN IESO CLKOUTEN BOREN<1:0> —
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 12 IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 11 CLKOUTEN: Clock Out Enable bit
If FOSC configuration bits are set to LP, XT, HS modes:
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
All other FOSC modes:
1 = CLKOUT function is disabled. I/O function on the CLKOUT pin.
0 = CLKOUT function is enabled on the CLKOUT pin
bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
bit 8 Unimplemented: Read as ‘1’
bit 7 CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6 MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUG5 bit.
bit 5 PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled

PIC16(L)F1526/7
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED)
bit 2-0 FOSC<2:0>: Oscillator Selection bits
111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin
110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin
101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin
100 = INTOSC oscillator: I/O function on CLKIN pin
011 = EXTRC oscillator: External RC circuit connected to CLKIN pin
010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins
001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins
000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins

PIC16(L)F1526/7
REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1
LVP DEBUG LPBOR BORV STVREN —
bit 13 bit 8
U-1 U-1 U-1 R/P-1 U-1 U-1 R/P-1 R/P-1

(1)
— — — VCAPEN — — WRT<1:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 LVP: Low-Voltage Programming Enable bit

1 = Low-voltage programming enabled
0 = High-voltage on MCLR must be used for programming
bit 12 DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11 LPBOR: Low-Power BOR bit
1 = Low-Power BOR is disabled
0 = Low-Power BOR is enabled
bit 10 BORV: Brown-out Reset Voltage Selection bit(2)
1 = Brown-out Reset voltage (Vbor), low trip point selected.
0 = Brown-out Reset voltage (Vbor), high trip point selected.
bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 4 VCAPEN: Voltage Regulator Capacitor Enable bits(1)
If PIC16LF1526/7 (regulator disabled):
These bits are ignored. All VCAP pin functions are disabled.
If PIC16F1526/7 (regulator enabled):
0 = VCAP functionality is enabled on RF0.
1 = All VCAP pin functions are disabled
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
8 kW Flash memory (PIC16(L)F1526 only):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 1FFFh may be modified by PMCON control
01 = 000h to FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control
00 = 000h to 1FFFh write-protected, no addresses may be modified by PMCON control
16 kW Flash memory (PIC16(L)F1527 only):
11 = Write protection off
10 = 000h to 1FFh write-protected, 200h to 3FFFh may be modified by PMCON control
01 = 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by PMCON control
00 = 000h to 3FFFh write-protected, no addresses may be modified by PMCON control
2: See Vbor parameter for specific trip point voltages.

PIC16(L)F1526/7
4.3 Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection is
controlled independently. Internal access to the
program memory is unaffected by any code protection
setting.
4.3.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection setting. See Section 4.4 “Write
Protection” for more information.
4.4 Write Protection

Write protection allows the device to be protected from
unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
4.5 User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 11.5 “User ID, Device ID and Configuration
Word Access” for more information on accessing these
memory locations. For more information on checksum
calculation, see the “PIC16F/LF151X/152X Memory
Programming Specification” (DS41422).

PIC16(L)F1526/7
4.6 Device ID and Revision ID
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 11.5 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
REGISTER 4-3: DEVID: DEVICE ID REGISTER

R R R R R R
DEV<8:3>
bit 13 bit 8
R R R R R R R R
DEV<2:0> REV<4:0>
bit 7 bit 0
Legend:
R = Readable bit U = Unimplemented bit, read as ‘1’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 13-5 DEV<8:0>: Device ID bits
DEVID<13:0> Values
Device
DEV<8:0> REV<4:0>
PIC16F1526 01 0101 100 x xxxx
PIC16F1527 01 0101 101 x xxxx
PIC16LF1526 01 0101 110 x xxxx
PIC16LF1527 01 0101 111 x xxxx
bit 4-0 REV<4:0>: Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

PIC16(L)F1526/7
5.0 OSCILLATOR MODULE (WITH The oscillator module can be configured in one of eight
clock modes.
FAIL-SAFE CLOCK MONITOR)
1. ECL – External Clock Low-Power mode
5.1 Overview (0 MHz to 0.5 MHz)
2. ECM – External Clock Medium-Power mode
The oscillator module has a wide variety of clock (0.5 MHz to 4 MHz)
sources and selection features that allow it to be used 3. ECH – External Clock High-Power mode
in a wide range of applications while maximizing perfor- (4 MHz to 20 MHz)
mance and minimizing power consumption. Figure 5-1
4. LP – 32 kHz Low-Power Crystal mode.
illustrates a block diagram of the oscillator module.
5. XT – Medium Gain Crystal or Ceramic Resonator
Clock sources can be supplied from external oscillators, Oscillator mode (up to 4 MHz)
quartz crystal resonators, ceramic resonators and
6. HS – High Gain Crystal or Ceramic Resonator
Resistor-Capacitor (RC) circuits. In addition, the system
mode (4 MHz to 20 MHz)
clock source can be supplied from one of two internal
oscillators, with a choice of speeds selectable via 7. RC – External Resistor-Capacitor (RC).
software. Additional clock features include: 8. INTOSC – Internal oscillator (31 kHz to 16 MHz).
• Selectable system clock source between external Clock Source modes are selected by the FOSC<2:0>
or internal sources via software. bits in the Configuration Words. The FOSC bits
• Two-Speed Start-up mode, which minimizes determine the type of oscillator that will be used when
latency between external oscillator start-up and the device is first powered.
code execution. The EC clock mode relies on an external logic level
• Fail-Safe Clock Monitor (FSCM) designed to signal as the device clock source. The LP, XT and HS
detect a failure of the external clock source (LP, clock modes require an external crystal or resonator to
XT, HS, EC or RC modes) and switch be connected to the device. Each mode is optimized for
automatically to the internal oscillator. a different frequency range. The RC clock mode
• Oscillator Start-up Timer (OST) ensures stability requires an external resistor and capacitor to set the
of crystal oscillator sources oscillator frequency.
• Fast start-up oscillator allows internal circuits to The INTOSC internal oscillator block produces a low
power up and stabilize before switching to the 16 and high-frequency clock source, designated
MHz HFINTOSC LFINTOSC and HFINTOSC. (see Internal Oscillator
Block, Figure 5-1). A wide selection of device clock
frequencies may be derived from these two clock
sources.

PIC16(L)F1526/7
FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
Low Power Mode

Primary Oscillator Event Switch
(SCS<1:0>)
OSC2 Primary
Oscillator
(OSC) 2
OSC1
Primary Clock
00
Clock Switch MUX

Secondary Oscillator
SOSCO/
Secondary 01
T1CKI Secondary Clock
Oscillator
(SOSC)
SOSCI
INTOSC
1x
Internal Oscillator
IRCF<3:0>
4 4
Start-up HF-16 MHz

Control
/1 1111
Internal Oscillator MUX
HF-8 MHz
Logic /2 1110
HF-4 MHz
/4 1101
HF-2 MHz
/8 1100
HF-1 MHz
Divide Circuit
16 MHz /16 1011

INTOSC
Primary Osc HF-500 kHz 1010/

/32 0111
HF-250 kHz 1001/
Start-Up Osc /64 0110
HF-125 kHz 1000/
/128 0101
HF-62.5 kHz
/256 0100
HF-31.25 kHz 0011

/512 0010
LF-INTOSC LF-31 kHz 0001
(31.25 kHz) 0000

PIC16(L)F1526/7
5.2 Clock Source Types The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
Clock sources can be classified as external or internal. operation after a Power-on Reset (POR) or wake-up
External clock sources rely on external circuitry for the from Sleep. Because the PIC® MCU design is fully
clock source to function. Examples are: oscillator static, stopping the external clock input will have the
modules (EC mode), quartz crystal resonators or effect of halting the device while leaving all data intact.
ceramic resonators (LP, XT and HS modes) and Upon restarting the external clock, the device will
Resistor-Capacitor (RC) mode circuits. resume operation as if no time had elapsed.
Internal clock sources are contained within the oscillator
module. The internal oscillator block has two internal FIGURE 5-2: EXTERNAL CLOCK (EC)
oscillators that are used to generate the internal system MODE OPERATION
clock sources: the 16 MHz High-Frequency Internal
Oscillator and the 31 kHz Low-Frequency Internal OSC1/CLKIN
Clock from
Oscillator (LFINTOSC). Ext. System
The system clock can be selected between external or PIC® MCU
internal clock sources via the System Clock Select
OSC2/CLKOUT
(SCS) bits in the OSCCON register. See Section 5.3 FOSC/4 or I/O(1)
“Clock Switching” for additional information.
Note 1: Output depends upon CLKOUTEN bit of the
5.2.1 EXTERNAL CLOCK SOURCES
Configuration Words.
An external clock source can be used as the device
system clock by performing one of the following
actions: 5.2.1.2 LP, XT, HS Modes
• Program the FOSC<2:0> bits in the Configuration The LP, XT and HS modes support the use of quartz
Words to select an external clock source that will crystal resonators or ceramic resonators connected to
be used as the default system clock upon a OSC1 and OSC2 (Figure 5-3). The three modes select
device Reset. a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
• Write the SCS<1:0> bits in the OSCCON register
and speed.
to switch the system clock source to:
- Secondary oscillator during run-time, or LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
- An external clock source determined by the
is the least of the three modes. This mode is designed to
value of the FOSC bits.
drive only 32.768 kHz tuning-fork type crystals (watch
See Section 5.3 “Clock Switching”for more informa- crystals).
tion.
XT Oscillator mode selects the intermediate gain
5.2.1.1 EC Mode setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
The External Clock (EC) mode allows an externally This mode is best suited to drive resonators with a
generated logic level signal to be the system clock medium drive level specification.
source. When operating in this mode, an external clock
source is connected to the OSC1 input. HS Oscillator mode selects the highest gain setting of the
OSC2/CLKOUT is available for general purpose I/O or internal inverter-amplifier. HS mode current consumption
CLKOUT. Figure 5-2 shows the pin connections for EC is the highest of the three modes. This mode is best
mode. suited for resonators that require a high drive setting.
EC mode has three power modes to select from through Figure 5-3 and Figure 5-4 show typical circuits for
Configuration Words: quartz crystal and ceramic resonators, respectively.
• High power, 4-20 MHz (FOSC = 111)

• Medium power, 0.5-4 MHz (FOSC = 110)
• Low power, 0-0.5 MHz (FOSC = 101)

PIC16(L)F1526/7
FIGURE 5-3: QUARTZ CRYSTAL FIGURE 5-4: CERAMIC RESONATOR
OPERATION (LP, XT OR OPERATION
HS MODE) (XT OR HS MODE)
PIC® MCU PIC® MCU
OSC1/CLKIN OSC1/CLKIN
C1 To Internal C1 To Internal
Logic Logic
Quartz
RF(2) Sleep RP(3)
Crystal RF(2) Sleep
C2 OSC2/CLKOUT
RS(1) OSC2/CLKOUT
C2 Ceramic RS(1)
Resonator
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level. Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M. 2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
Note 1: Quartz crystal characteristics vary may be required for proper ceramic resonator
according to type, package and operation.
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application. 5.2.1.3 Oscillator Start-up Timer (OST)
2: Always verify oscillator performance over If the oscillator module is configured for LP, XT or HS
the VDD and temperature range that is modes, the Oscillator Start-up Timer (OST) counts
expected for the application. 1024 oscillations from OSC1. This occurs following a
3: For oscillator design assistance, reference Power-on Reset (POR) and when the Power-up Timer
the following Microchip Applications Notes: (PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
• AN826, “Crystal Oscillator Basics and increment and program execution is suspended,
Crystal Selection for rfPIC® and PIC® unless either FSCM or Two-Speed Start-Up are
Devices” (DS00826) enabled. The OST ensures that the oscillator circuit,
• AN849, “Basic PIC® Oscillator Design” using a quartz crystal resonator or ceramic resonator,
(DS00849) has started and is providing a stable system clock to
• AN943, “Practical PIC® Oscillator the oscillator module.
Analysis and Design” (DS00943) In order to minimize latency between external oscillator
• AN949, “Making Your Oscillator Work” start-up and code execution, the Two-Speed Clock
(DS00949) Start-up mode can be selected (see Section 5.4
“Two-Speed Clock Start-up Mode”).

PIC16(L)F1526/7
5.2.1.4 Secondary Oscillator 5.2.1.5 External RC Mode
The secondary oscillator is a separate crystal oscillator The external Resistor-Capacitor (RC) modes support
that is associated with the Timer1 peripheral. It is opti- the use of an external RC circuit. This allows the
mized for timekeeping operations with a 32.768 kHz designer maximum flexibility in frequency choice while
crystal connected between the SOSCO and SOSCI keeping costs to a minimum when clock accuracy is not
device pins. required.
The secondary oscillator can be used as an alternate The RC circuit connects to OSC1. OSC2/CLKOUT is
system clock source and can be selected during available for general purpose I/O or CLKOUT. The
run-time using clock switching. Refer to Section 5.3 function of the OSC2/CLKOUT pin is determined the
“Clock Switching” for more information. CLKOUTEN bit in Configuration Words.
Figure 5-6 shows the external RC mode connections.
FIGURE 5-5: QUARTZ CRYSTAL
OPERATION FIGURE 5-6: EXTERNAL RC MODES
(SECONDARY
OSCILLATOR)
VDD
PIC® MCU
REXT
PIC® MCU
OSC1/CLKIN Internal
SOSCI Clock
CEXT
C1 To Internal
Logic VSS
32.768 kHz
Quartz
OSC2/CLKOUT
Crystal FOSC/4 or I/O(1)
SOSCO
C2 Recommended values: 10 k  REXT  100 k, <3V
3 k  REXT  100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1: Output depends upon CLKOUTEN bit of the

Note 1: Quartz crystal characteristics vary Configuration Words.
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications The RC oscillator frequency is a function of the supply
and recommended application. voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
2: Always verify oscillator performance over the oscillator frequency are:
the VDD and temperature range that is
expected for the application. • threshold voltage variation
• component tolerances
3: For oscillator design assistance, reference • packaging variations in capacitance
the following Microchip Applications Notes:
The user also needs to take into account variation due
• AN826, “Crystal Oscillator Basics and to tolerance of the external RC components used.
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
• TB097, “Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)
• AN1288, “Design Practices for
Low-Power External Oscillators”
(DS01288)

PIC16(L)F1526/7
5.2.2 INTERNAL CLOCK SOURCES 5.2.2.2 LFINTOSC
The device may be configured to use the internal oscil- The Low-Frequency Internal Oscillator (LFINTOSC) is
lator block as the system clock by performing one of the an uncalibrated 31 kHz internal clock source.
following actions: The output of the LFINTOSC connects to a multiplexer
• Program the FOSC<2:0> bits in Configuration (see Figure 5-1). Select 31 kHz, via software, using the
Words to select the INTOSC clock source, which IRCF<3:0> bits of the OSCCON register. See
will be used as the default system clock upon a Section 5.2.2.4 “Internal Oscillator Clock Switch
device Reset. Timing” for more information. The LFINTOSC is also
• Write the SCS<1:0> bits in the OSCCON register the frequency for the Power-up Timer (PWRT),
to switch the system clock source to the internal Watchdog Timer (WDT) and Fail-Safe Clock Monitor
oscillator during run-time. See Section 5.3 (FSCM).
“Clock Switching”for more information. The LFINTOSC is enabled by selecting 31 kHz
In INTOSC mode, OSC1/CLKIN is available for general (IRCF<3:0> bits of the OSCCON register = 000) as the
purpose I/O. OSC2/CLKOUT is available for general system clock source (SCS bits of the OSCCON
purpose I/O or CLKOUT. register = 1x), or when any of the following are
enabled:
The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN bit in Configuration Words. • Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
The internal oscillator block has two independent
oscillators that provides the internal system clock • FOSC<2:0> = 100, or
source. • Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at Peripherals that use the LFINTOSC are:
16 MHz. • Power-up Timer (PWRT)
2. The LFINTOSC (Low-Frequency Internal • Watchdog Timer (WDT)
Oscillator) is uncalibrated and operates at • Fail-Safe Clock Monitor (FSCM)
31 kHz.
The Low-Frequency Internal Oscillator Ready bit
5.2.2.1 HFINTOSC (LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source.
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). The frequency derived
from the HFINTOSC can be selected via software using
the IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.4 “Internal Oscillator Clock Switch
Timing” for more information.
The HFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
A fast start-up oscillator allows internal circuits to
power-up and stabilize before switching to HFINTOSC.
The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.
The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.

PIC16(L)F1526/7
5.2.2.3 Internal Oscillator Frequency 5.2.2.4 Internal Oscillator Clock Switch
Selection Timing
The system clock speed can be selected via software When switching between the HFINTOSC and the
using the Internal Oscillator Frequency Select bits LFINTOSC, the new oscillator may already be shut
IRCF<3:0> of the OSCCON register. down to save power (see Figure 5-7). If this is the case,
The outputs of the 16 MHz HFINTOSC and LFINTOSC there is a delay after the IRCF<3:0> bits of the
connects to a postscaler and multiplexer (see OSCCON register are modified before the frequency
Figure 5-1). The Internal Oscillator Frequency Select selection takes place. The OSCSTAT register will
bits IRCF<3:0> of the OSCCON register select the reflect the current active status of the HFINTOSC and
frequency output of the internal oscillators. One of the LFINTOSC oscillators. The sequence of a frequency
following frequencies can be selected via software: selection is as follows:
• 16 MHz 1. IRCF<3:0> bits of the OSCCON register are

modified.
• 8 MHz
2. If the new clock is shut down, a clock start-up
• 4 MHz
delay is started.
• 2 MHz
3. Clock switch circuitry waits for a falling edge of
• 1 MHz the current clock.
• 500 kHz (default after Reset) 4. The current clock is held low and the clock
• 250 kHz switch circuitry waits for a rising edge in the new
• 125 kHz clock.
• 62.5 kHz 5. The new clock is now active.
• 31.25 kHz 6. The OSCSTAT register is updated as required.
• 31 kHz (LFINTOSC) 7. Clock switch is complete.
Note: Following any Reset, the IRCF<3:0> bits See Figure 5-7 for more details.
of the OSCCON register are set to ‘0111’ If the internal oscillator speed is switched between two
and the frequency selection is set to clocks of the same source, there is no start-up delay
500 kHz. The user can modify the IRCF before the new frequency is selected. Clock switching
bits to select a different frequency. time delays are shown in Table 5-1.
The IRCF<3:0> bits of the OSCCON register allow Start-up delay specifications are located in the
duplicate selections for some frequencies. These dupli- oscillator tables of Section 25.0 “Electrical
cate choices can offer system design trade-offs. Lower Specifications”
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transi-
tion times can be obtained between frequency changes
that use the same oscillator source.

PIC16(L)F1526/7
FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC LFINTOSC (FSCM and WDT disabled)
HFINTOSC
Oscillator Delay(1) 2-cycle Sync Running
LFINTOSC
IRCF <3:0> 0 0
System Clock
HFINTOSC LFINTOSC (Either FSCM or WDT enabled)
HFINTOSC
2-cycle Sync Running
LFINTOSC
IRCF <3:0> 0 0
System Clock
LFINTOSC HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Oscillator Delay(1) 2-cycle Sync Running
HFINTOSC
IRCF <3:0> =0 0
System Clock
Note: See Table 5-1, “Oscillator Switching Delays” for more information.

PIC16(L)F1526/7
5.3 Clock Switching 5.3.3 SECONDARY OSCILLATOR
The system clock source can be switched between The secondary oscillator is a separate crystal oscillator
external and internal clock sources via software using associated with the Timer1 peripheral. It is optimized
the System Clock Select (SCS) bits of the OSCCON for timekeeping operations with a 32.768 kHz crystal
register. The following clock sources can be selected connected between the SOSCO and SOSCI device
using the SCS bits: pins.
• Default system oscillator determined by FOSC The secondary oscillator is enabled using the SOSCEN
bits in Configuration Words control bit in the TxCON register. See Section 18.0
“Timer1/3/5 Module with Gate Control” for more
• Secondary oscillator 32 kHz crystal
information about the Timer1 peripheral.
• Internal Oscillator Block (INTOSC)
5.3.4 SECONDARY OSCILLATOR READY
5.3.1 SYSTEM CLOCK SELECT (SCS)
(SOSCR) BIT
BITS
The user must ensure that the secondary oscillator is
The System Clock Select (SCS) bits of the OSCCON
ready to be used before it is selected as a system clock
register selects the system clock source that is used for
source. The Secondary Oscillator Ready (SOSCR) bit
the CPU and peripherals.
of the OSCSTAT register indicates whether the
• When the SCS bits of the OSCCON register = 00, secondary oscillator is ready to be used. After the
the system clock source is determined by value of SOSCR bit is set, the SCS bits can be configured to
the FOSC<2:0> bits in the Configuration Words. select the secondary oscillator.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the secondary 5.3.5 CLOCK SWITCHING BEFORE
oscillator. SLEEP
• When the SCS bits of the OSCCON register = 1x, When clock switching from an old clock to a new clock,
the system clock source is chosen by the internal prior to entering Sleep mode, it is necessary to confirm
oscillator frequency selected by the IRCF<3:0> that the switch is complete before the Sleep instruction
bits of the OSCCON register. After a Reset, the is executed. Failure to do so may result in an
SCS bits of the OSCCON register are always incomplete switch and consequential loss of the
cleared. system clock altogether. Clock switching is confirmed
Note: Any automatic clock switch, which may by monitoring the clock status bits in the OSCSTAT
occur from Two-Speed Start-up or register. Switch confirmation can be accomplished by
Fail-Safe Clock Monitor, does not update sensing that the ready bit for the new clock is set or the
the SCS bits of the OSCCON register. The ready bit for the old clock is cleared. For example,
user can monitor the OSTS bit of the when switching between the internal oscillator with the
OSCSTAT register to determine the current PLL and the internal oscillator without the PLL, monitor
system clock source. the PLLR bit. When PLLR is set, the switch to 32 MHz
operation is complete. Conversely, when PLLR is
When switching between clock sources, a delay is cleared the switch from the 32 MHz operation to the
required to allow the new clock to stabilize. These oscil- selected internal clock is complete.
lator delays are shown in Table 5-1.
5.3.2 OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT
The Oscillator Start-up Timer Status (OSTS) bit of the
OSCSTAT register indicates whether the system clock
is running from the external clock source, as defined by
the FOSC<2:0> bits in the Configuration Words, or
from the internal clock source. In particular, OSTS
indicates that the Oscillator Start-up Timer (OST) has
timed out for LP, XT or HS modes. The OST does not
reflect the status of the secondary oscillator.

PIC16(L)F1526/7
5.4 Two-Speed Clock Start-up Mode 5.4.1 TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external Two-Speed Start-up mode is configured by the
oscillator start-up and code execution. In applications following settings:
that make heavy use of the Sleep mode, Two-Speed • IESO (of the Configuration Words) = 1;
Start-up will remove the external oscillator start-up Internal/External Switchover bit (Two-Speed
time from the time spent awake and can reduce the Start-up mode enabled).
overall power consumption of the device. This mode • SCS (of the OSCCON register) = 00.
allows the application to wake-up from Sleep, perform
• FOSC<2:0> bits in the Configuration Words
a few instructions using the INTOSC internal oscillator
configured for LP, XT or HS mode.
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable. Two-Speed Start-up mode is entered after:
Two-Speed Start-up provides benefits when the • Power-on Reset (POR) and, if enabled, after
oscillator module is configured for LP, XT or HS Power-up Timer (PWRT) has expired, or
modes. The Oscillator Start-up Timer (OST) is enabled • Wake-up from Sleep.
for these modes and must count 1024 oscillations
before the oscillator can be used as the system clock
source.
If the oscillator module is configured for any mode
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT reg-
ister is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
TABLE 5-1: OSCILLATOR SWITCHING DELAYS

Switch From Switch To Oscillator Delay
LFINTOSC One cycle of each clock source
HFINTOSC 2 s (approx.)
Any clock source ECH, ECM, ECL, EXTRC 2 cycles
LP, XT, HS 1024 Clock Cycles (OST)
Secondary Oscillator 1024 Secondary Oscillator Cycles

PIC16(L)F1526/7
5.4.2 TWO-SPEED START-UP 5.4.3 CHECKING TWO-SPEED CLOCK
SEQUENCE STATUS
1. Wake-up from Power-on Reset or Sleep. Checking the state of the OSTS bit of the OSCSTAT
2. Instructions begin execution by the internal register will confirm if the microcontroller is running
oscillator at the frequency set in the IRCF<3:0> from the external clock source, as defined by the
bits of the OSCCON register. FOSC<2:0> bits in the Configuration Words, or the
3. OST enabled to count 1024 clock cycles. internal oscillator.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
FIGURE 5-8: TWO-SPEED START-UP
INTOSC
TOST
OSC1 0 1 1022 1023
OSC2
Program Counter PC - N PC PC + 1
System Clock

PIC16(L)F1526/7
5.5 Fail-Safe Clock Monitor 5.5.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset,
to continue operating should the external oscillator fail. executing a SLEEP instruction or changing the SCS bits
The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bits are
the Oscillator Start-up Timer (OST) has expired. The changed, the OST is restarted. While the OST is
FSCM is enabled by setting the FCMEN bit in the running, the device continues to operate from the
Configuration Words. The FSCM is applicable to all INTOSC selected in OSCCON. When the OST times
external Oscillator modes (LP, XT, HS, EC, RC and out, the Fail-Safe condition is cleared after successfully
secondary oscillator). switching to the external clock source. The OSFIF bit
should be cleared prior to switching to the external
clock source. If the Fail-Safe condition still exists, the
FIGURE 5-9: FSCM BLOCK DIAGRAM
OSFIF flag will again become set by hardware.
Clock Monitor
Latch 5.5.4 RESET OR WAKE-UP FROM SLEEP
External
S Q The FSCM is designed to detect an oscillator failure
Clock
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
LFINTOSC any type of Reset. The OST is not used with the EC or
÷ 64 R Q
Oscillator RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
31 kHz 488 Hz the FSCM is enabled, the Two-Speed Start-up is also
(~32 s) (~2 ms)
enabled. Therefore, the device will always be executing
Sample Clock code while the OST is operating.
Clock
Failure Note: Due to the wide range of oscillator start-up
Detected times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
5.5.1 FAIL-SAFE DETECTION amount of time, the user should check the
The FSCM module detects a failed oscillator by Status bits in the OSCSTAT register to
comparing the external oscillator to the FSCM sample verify the oscillator start-up and that the
clock. The sample clock is generated by dividing the system clock switchover has successfully
LFINTOSC by 64. See Figure 5-9. Inside the fail completed.
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
5.5.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.

PIC16(L)F1526/7
FIGURE 5-10: FSCM TIMING DIAGRAM
Sample Clock
System Oscillator
Clock Failure
Output
Clock Monitor Output

(Q)
Failure
Detected
OSCFIF
Test Test Test
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.

PIC16(L)F1526/7
5.6 Register Definitions: Oscillator Control
REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0
— IRCF<3:0> — SCS<1:0>
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 = 16 MHz
1110 = 8 MHz
1101 = 4 MHz
1100 = 2 MHz
1011 = 1 MHz
1010 = 500 kHz(1)
1001 = 250 kHz(1)
1000 = 125 kHz(1)
0111 = 500 kHz (default upon Reset)
0110 = 250 kHz
0101 = 125 kHz
0100 = 62.5 kHz
001x = 31.25 kHz
000x = 31 kHz LF
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Secondary oscillator
00 = Clock determined by FOSC<2:0> in Configuration Words.
Note 1: Duplicate frequency derived from HFINTOSC.

PIC16(L)F1526/7
REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER

R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/0 R-0/q
SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional
bit 7 SOSCR: Secondary Oscillator Ready bit

If SOSCEN = 1:
1 = Secondary oscillator is ready
0 = Secondary oscillator is not ready
If SOSCEN = 0:
1 = Timer1 clock source is always ready
bit 5 OSTS: Oscillator Start-up Timer Status bit
1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words
0 = Running from an internal oscillator (FOSC<2:0> = 100)
bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit
1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit
1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit
1 = HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC
0 = HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
OSCCON — IRCF<3:0> — SCS<1:0> 61

OSCSTAT SOSCR — OSTS HFIOFR — — LFIOFR HFIOFS 62
PIE2 OSFIE TMR5GIE TMR3GIE — BCL1IE TMR10IE TMR8IE CCP2IE 78
PIR2 OSFIF TMR5GIF TMR3GIF — BCL1IF TMR10IF TMR8IF CCP2IF 82
T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC — TMR1ON 168
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page
13:8 — FCMEN IESO CLKOUTEN BOREN<1:0> —

CONFIG1 43
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

PIC16(L)F1526/7
6.0 RESETS A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.
There are multiple ways to reset this device:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
• Low-Power Brown-Out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• RESET instruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional power-up timer
can be enabled to extend the Reset time after a BOR
or POR event.
FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
ICSP Programming Mode Exit

RESET Instruction
Stack
Pointer
MCLRE
Sleep
WDT
Time-out Device
Reset
Power-on
Reset
VDD
Brown-out PWRT
R
Reset Done
LPBOR
Reset PWRTE
LFINTOSC
BOR
Active(1)
Note 1: See Table for BOR active conditions.

PIC16(L)F1526/7
6.1 Power-On Reset (POR) 6.2 Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has The BOR circuit holds the device in Reset when VDD
reached an acceptable level for minimum operation. reaches a selectable minimum level. Between the
Slow rising VDD, fast operating speeds or analog POR and BOR, complete voltage range coverage for
performance may require greater than minimum VDD. execution protection can be implemented.
The PWRT, BOR or MCLR features can be used to The Brown-out Reset module has four operating
extend the start-up period until all device operation modes controlled by the BOREN<1:0> bits in
conditions have been met. Configuration Words. The four operating modes are:
6.1.1 POWER-UP TIMER (PWRT) • BOR is always on
The Power-up Timer provides a nominal 64 ms • BOR is off when in Sleep
time-out on POR or Brown-out Reset. • BOR is controlled by software
The device is held in Reset as long as PWRT is active. • BOR is always off
The PWRT delay allows additional time for the VDD to Refer to Table for more information.
rise to an acceptable level. The Power-up Timer is The Brown-out Reset voltage level is selectable by
enabled by clearing the PWRTE bit in Configuration configuring the BORV bit in Configuration Words.
Words.
A VDD noise rejection filter prevents the BOR from
The Power-up Timer starts after the release of the POR triggering on small events. If VDD falls below VBOR for
and BOR. a duration greater than parameter TBORDC, the device
For additional information, refer to Application Note will reset. See Figure 6-2 for more information.
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 6-1: BOR OPERATING MODES

Instruction Execution upon:
BOREN<1:0> SBOREN Device Mode BOR Mode
Release of POR or Wake-up from Sleep
11 X X Active Waits for BOR ready(1) (BORRDY = 1)
Awake Active
10 X Waits for BOR ready (BORRDY = 1)
Sleep Disabled
1 X Active Waits for BOR ready(1) (BORRDY = 1)
01
0 X Disabled
Begins immediately (BORRDY = x)
00 X X Disabled
Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The
BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the
BOR circuit is forced on by the BOREN<1:0> bits.
6.2.1 BOR IS ALWAYS ON 6.2.3 BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Words are When the BOREN bits of Configuration Words are
programmed to ‘11’, the BOR is always on. The device programmed to ‘01’, the BOR is controlled by the
start-up will be delayed until the BOR is ready and VDD SBOREN bit of the BORCON register. The device
is higher than the BOR threshold. start-up is not delayed by the BOR ready condition or
BOR protection is active during Sleep. The BOR does the VDD level.
not delay wake-up from Sleep. BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
6.2.2 BOR IS OFF IN SLEEP BORRDY bit of the BORCON register.
When the BOREN bits of Configuration Words are BOR protection is unchanged by Sleep.
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.

PIC16(L)F1526/7
FIGURE 6-2: BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
VBOR
Internal < TPWRT

Reset TPWRT(1)
VDD
VBOR
Internal
Reset TPWRT(1)
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.
6.3 Register Definitions: BOR Control
REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u
SBOREN BORFS — — — — — BORRDY
bit 7 bit 0
Legend:
bit 7 SBOREN: Software Brown-out Reset Enable bit(1)

If BOREN <1:0>  01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> = 01:
1 = BOR Enabled
0 = BOR Disabled
bit 6 BORFS: Brown-out Reset Fast Start bit(1)
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in Configuration Words.

PIC16(L)F1526/7
6.4 Low-Power Brown-Out Reset 6.6 Watchdog Timer (WDT) Reset
(LPBOR) The Watchdog Timer generates a Reset if the firmware
The Low-Power Brown-Out Reset (LPBOR) is an does not issue a CLRWDT instruction within the time-out
essential part of the Reset subsystem. Refer to period. The TO and PD bits in the STATUS register are
Figure 6-1 to see how the BOR interacts with other changed to indicate the WDT Reset. See Section 10.0
modules. “Watchdog Timer (WDT)” for more information.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is 6.7 RESET Instruction
held in Reset. When this occurs, a register bit (BOR) is A RESET instruction will cause a device Reset. The RI
changed to indicate that a BOR Reset has occurred. bit in the PCON register will be set to ‘0’. See Table 6-4
The same bit is set for both the BOR and the LPBOR. for default conditions after a RESET instruction has
Refer to Register 6-2. occurred.
6.4.1 ENABLING LPBOR
6.8 Stack Overflow/Underflow Reset
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the The device can reset when the Stack Overflows or
LPBOR module defaults to disabled. Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
6.4.1.1 LPBOR Module Output enabled by setting the STVREN bit in Configuration
Words. See Section 3.7.2 “Overflow/Underflow
The output of the LPBOR module is a signal indicating
Reset” for more information.
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR
module to provide the generic BOR signal, which goes 6.9 Programming Mode Exit
to the PCON register and to the power control block. Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.5 MCLR
The MCLR is an optional external input that can reset 6.10 Power-up Timer
the device. The MCLR function is controlled by the The Power-up Timer optionally delays device execution
MCLRE bit of Configuration Words and the LVP bit of after a BOR or POR event. This timer is typically used to
Configuration Words (Table 6-2). allow VDD to stabilize before allowing the device to start
running.
TABLE 6-2: MCLR CONFIGURATION The Power-up Timer is controlled by the PWRTE bit of
MCLRE LVP MCLR Configuration Words.
0 0 Disabled 6.11 Start-up Sequence

1 0 Enabled
Upon the release of a POR or BOR, the following must
x 1 Enabled
occur before the device will begin executing:
6.5.1 MCLR ENABLED 1. Power-up Timer runs to completion (if enabled).
When MCLR is enabled and the pin is held low, the 2. Oscillator start-up timer runs to completion (if
device is held in Reset. The MCLR pin is connected to required for oscillator source).
VDD through an internal weak pull-up. 3. MCLR must be released (if enabled).
The device has a noise filter in the MCLR Reset path. The total time-out will vary based on oscillator configu-
The filter will detect and ignore small pulses. ration and Power-up Timer configuration. See
Section 5.0 “Oscillator Module (with Fail-Safe
Note: A Reset does not drive the MCLR pin low. Clock Monitor)” for more information.
The Power-up Timer and oscillator start-up timer run
6.5.2 MCLR DISABLED
independently of MCLR Reset. If MCLR is kept low long
When MCLR is disabled, the pin functions as a general enough, the Power-up Timer and oscillator start-up
purpose input and the internal weak pull-up is under timer will expire. Upon bringing MCLR high, the device
software control. See Section Register 12-19: will begin execution immediately (see Figure 6-3). This
“PORTE: PORTE Register” for more information. is useful for testing purposes or to synchronize more
than one device operating in parallel.

PIC16(L)F1526/7
FIGURE 6-3: RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-Up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC

PIC16(L)F1526/7
6.12 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 6-3 and Table 6-4 show the Reset
conditions of these registers.
TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition
0 0 1 1 1 0 x 1 1 Power-on Reset
0 0 1 1 1 0 x 0 x Illegal, TO is set on POR
0 0 1 1 1 0 x x 0 Illegal, PD is set on POR
0 0 u 1 1 u 0 1 1 Brown-out Reset
u u 0 u u u u 0 u WDT Reset
u u u u u u u 0 0 WDT Wake-up from Sleep
u u u u u u u 1 0 Interrupt Wake-up from Sleep
u u u 0 u u u u u MCLR Reset during normal operation
u u u 0 u u u 1 0 MCLR Reset during Sleep
u u u u 0 u u u u RESET Instruction Executed
1 u u u u u u u u Stack Overflow Reset (STVREN = 1)
u 1 u u u u u u u Stack Underflow Reset (STVREN = 1)
TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS

Program STATUS PCON
Condition
Counter Register Register
Power-on Reset 0000h ---1 1000 00-1 110x
MCLR Reset during normal operation 0000h ---u uuuu uu-u 0uuu
MCLR Reset during Sleep 0000h ---1 0uuu uu-u 0uuu
WDT Reset 0000h ---0 uuuu uu-0 uuuu
WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-u uuuu
Brown-out Reset 0000h ---1 1uuu 00-1 11u0
(1)
Interrupt Wake-up from Sleep PC + 1 ---1 0uuu uu-u uuuu
RESET Instruction Executed 0000h ---u uuuu uu-u u0uu
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-u uuuu
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-u uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

PIC16(L)F1526/7
6.13 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 6-2.
6.14 Register Definitions: Power Control
REGISTER 6-2: PCON: POWER CONTROL REGISTER

R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF STKUNF — RWDT RMCLR RI POR BOR
bit 7 bit 0
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
bit 7 STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6 STKUNF: Stack Underflow Flag bit
1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 4 RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3 RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or set to ‘1’ by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2 RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set to ‘1’ by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)

PIC16(L)F1526/7
TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Register
on Page
BORCON SBOREN BORFS — — — — — BORRDY 65
PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 69
STATUS — — — TO PD Z DC C 21
WDTCON — — WDTPS<4:0> SWDTEN 93
Legend: — = unimplemented bit, read as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

PIC16(L)F1526/7
7.0 INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.
FIGURE 7-1: INTERRUPT LOGIC
TMR0IF Wake-up
TMR0IE (If in Sleep mode)
INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF
(TMR1IE) PIE1<0> Interrupt
IOCIE to CPU
PEIE
PIRn<7>
PIEn<7>
GIE

PIC16(L)F1526/7
7.1 Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIEx register)
The INTCON and PIRx registers record individual
interrupts via interrupt flag bits. Interrupt flag bits will be
set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See Section 7.5 “Automatic
Context Saving”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
7.2 Interrupt Latency

Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
asynchronous interrupts, the latency is three to five
instruction cycles, depending on when the interrupt
occurs. See Figure 7-2 and Figure 7-3 for more details.

PIC16(L)F1526/7
FIGURE 7-2: INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR Interrupt Sampled

during Q1
Interrupt
GIE
PC PC-1 PC PC+1 0004h 0005h
Execute 1 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)
Interrupt
GIE
PC+1/FSR New PC/

PC PC-1 PC 0004h 0005h
ADDR PC+1
Execute 2 Cycle Instruction at PC Inst(PC) NOP NOP Inst(0004h)
Interrupt
GIE
PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h
Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h)
Interrupt
GIE
PC PC-1 PC FSR ADDR PC+1 PC+2 0004h 0005h
Execute 3 Cycle Instruction at PC INST(PC) NOP NOP NOP NOP Inst(0004h)

PIC16(L)F1526/7
FIGURE 7-3: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF (5) Interrupt Latency (2)
GIE
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Instruction Forced NOP Forced NOP Inst (0004h)

Inst (PC – 1) Inst (PC)
Executed
Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT not available in all oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 25.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.

PIC16(L)F1526/7
7.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 8.0
“Power-Down Mode (Sleep)” for more details.
7.4 INT Pin

The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these
registers are automatically restored. Any modifications
to these registers during the ISR will be lost. If
modifications to any of these registers are desired, the
corresponding shadow register should be modified and
the value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.

PIC16(L)F1526/7
7.6 Register Definitions: Interrupt Control
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0
GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF
bit 7 bit 0
Legend:
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all active interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 IOCIE: Interrupt-on-Change Interrupt Enable bit
1 = Enables the interrupt-on-change interrupt
0 = Disables the interrupt-on-change interrupt
bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
Note 1: The IOCIF flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register
have been cleared by software.
Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.

PIC16(L)F1526/7
REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR1GIE ADIE RC1IE TX1IE SSP1IE SSP2IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 Gate Acquisition interrupt
0 = Disables the Timer1 Gate Acquisition interrupt
bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RC1IE: USART1 Receive Interrupt Enable bit
1 = Enables the USART1 receive interrupt
0 = Disables the USART1 receive interrupt
bit 4 TX1IE: USART1 Transmit Interrupt Enable bit
1 = Enables the USART1 transmit interrupt
0 = Disables the USART1 transmit interrupt
bit 3 SSP1IE: Synchronous Serial Port (MSSP1) Interrupt Enable bit
1 = Enables the MSSP1 interrupt
0 = Disables the MSSP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIC16(L)F1526/7

U-0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0
AD2IE BCL1IE BCL2IE TMR4IE
bit 7 bit 0
Legend:

bit 6 AD2IE: Analog-to-Digital Converter (ADC2) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 3 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit
1 = Enables the MSSP1 Bus Collision Interrupt
0 = Disables the MSSP1 Bus Collision Interrupt
1 = Enables the Timer8 to PR4 match interrupt
0 = Disables the Timer8 to PR4 match interrupt


PIC16(L)F1526/7

CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE
bit 7 bit 0
Legend:
bit 7 CCP6IE: CCP6 Interrupt Enable bit

1 = Enables the CCP6 interrupt
0 = Disables the CCP6 interrupt
1 = Enables the TMR6 to PR6 Match interrupt
0 = Disables the TMR6 to PR6 Match interrupt
1 = Enables the TMR4 to PR4 Match interrupt
0 = Disables the TMR4 to PR4 Match interrupt


PIC16(L)F1526/7

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE
bit 7 bit 0
Legend:

bit 5 RC2IE: USART2 Receive Interrupt Enable bit
1 = Enables the USART2 receive interrupt
0 = Disables the USART2 receive interrupt
bit 4 TX2IE: USART2 Transmit Interrupt Enable bit
1 = Enables the USART2 transmit interrupt
0 = Disables the USART2 transmit interrupt


PIC16(L)F1526/7
REGISTER 7-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 ADIF: ADC Converter Interrupt Flag bit
bit 5 RC1IF: USART1 Receive Interrupt Flag bit
bit 4 TX1IF: USART1 Transmit Interrupt Flag bit
bit 3 SSP1IF: Synchronous Serial Port (MSSP1) Interrupt Flag bit
bit 2 CCP1IF: CCP1 Interrupt Flag bit
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

PIC16(L)F1526/7

U-0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0
— AD2IF — — BCL1IF BCL2IF TMR4IF —
bit 7 bit 0
Legend:

bit 6 AD2IF: Timer5 Gate Interrupt Flag bit
bit 3 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit
bit 1 TMR4IF: Timer4 to PR4 Interrupt Flag bit


PIC16(L)F1526/7

CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF
bit 7 bit 0
Legend:

bit 3 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit
bit 1 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit


PIC16(L)F1526/7

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF
bit 7 bit 0
Legend:

bit 5 RC2IF: USART2 Receive Interrupt Flag bit
bit 4 TX2IF: USART2 Transmit Interrupt Flag bit
bit 0 SSP2IF: Synchronous Serial Port (MSSP2) Interrupt Flag bit


PIC16(L)F1526/7
TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 76

IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 137
IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 137
IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 137
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 158
PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE SSP2IE TMR2IE TMR1IE 77
PIE2 — AD2IE — — BCL1IE BCL2IE TMR4IE — 78
PIE3 CCP6IE CCP5IE CCP4IE CCP3IE TMR6IE TMR5IE TMR4IE TMR3IE 79
PIE4 CCP10IE CCP9IE RC2IE TX2IE CCP8IE CCP7IE BCL2IE SSP2IE 80
PIR1 TMR1GIF AD1IF RCIF TXIF SSP1IF SSP2IF TMR2IF TMR1IF 81
PIR2 — AD2IF — — BCL1IF BCL2IF TMR4IF — 82
PIR3 CCP6IF CCP5IF CCP4IF CCP3IF TMR6IF TMR5IF TMR4IF TMR3IF 83
PIR4 CCP10IF CCP9IF RC2IF TX2IF CCP8IF CCP7IF BCL2IF SSP2IF 84
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.

PIC16(L)F1526/7
8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep
The Power-down mode is entered by executing a The device can wake-up from Sleep through one of the
SLEEP instruction. following events:
Upon entering Sleep mode, the following conditions 1. External Reset input on MCLR pin, if enabled
exist: 2. BOR Reset, if enabled
1. WDT will be cleared but keeps running, if 3. POR Reset
enabled for operation during Sleep. 4. Watchdog Timer, if enabled
2. PD bit of the STATUS register is cleared. 5. Any external interrupt
3. TO bit of the STATUS register is set. 6. Interrupts by peripherals capable of running
4. CPU clock is disabled. during Sleep (see individual peripheral for more
5. 31 kHz LFINTOSC is unaffected and peripherals information)
that operate from it may continue operation in The first three events will cause a device Reset. The
Sleep. last three events are considered a continuation of
6. Timer1 and peripherals that operate from Tim- program execution. To determine whether a device
er1 continue operation in Sleep when the Tim- Reset or wake-up event occurred, refer to
er1 clock source selected is: Section 6.12 “Determining the Cause of a Reset”.
• LFINTOSC When the SLEEP instruction is being executed, the next
• T1CKI instruction (PC + 1) is prefetched. For the device to
• Secondary oscillator wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
7. ADC is unaffected, if the dedicated FRC oscillator
occur regardless of the state of the GIE bit. If the GIE
is selected.
bit is disabled, the device continues execution at the
8. I/O ports maintain the status they had before instruction after the SLEEP instruction. If the GIE bit is
SLEEP was executed (driving high, low or enabled, the device executes the instruction after the
high-impedance). SLEEP instruction, the device will then call the Interrupt
9. Resets other than WDT are not affected by Service Routine. In cases where the execution of the
Sleep mode. instruction following SLEEP is not desirable, the user
Refer to individual chapters for more details on periph- should have a NOP after the SLEEP instruction.
eral operation during Sleep. The WDT is cleared when the device wakes up from
To minimize current consumption, the following condi- Sleep, regardless of the source of wake-up.
tions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• Modules using Secondary oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include modules such as the FVR modules.
See Section 14.0 “Fixed Voltage Reference (FVR)”
for more information on these modules.

PIC16(L)F1526/7
8.1.1 WAKE-UP USING INTERRUPTS - SLEEP instruction will be completely exe-
cuted
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit - Device will immediately wake-up from Sleep
and interrupt flag bit set, one of the following will occur: - WDT and WDT prescaler will be cleared
• If the interrupt occurs before the execution of a - TO bit of the STATUS register will be set
SLEEP instruction - PD bit of the STATUS register will be cleared.
- SLEEP instruction will execute as a NOP. Even if the flag bits were checked before executing a
- WDT and WDT prescaler will not be cleared SLEEP instruction, it may be possible for flag bits to
- TO bit of the STATUS register will not be set become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
- PD bit of the STATUS register will not be
the PD bit. If the PD bit is set, the SLEEP instruction
cleared.
was executed as a NOP.
• If the interrupt occurs during or after the execu-
tion of a SLEEP instruction
FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
CLKOUT(2) TOST(3)
Interrupt flag Interrupt Latency (4)
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.

2: CLKOUT is shown here for timing reference.
3: TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-Up (if available).
4: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

PIC16(L)F1526/7
8.2 Low-Power Sleep Mode 8.2.2 PERIPHERAL USAGE IN SLEEP
The PIC16F1526 device contains an internal Low Some peripherals that can operate in Sleep mode will
Dropout (LDO) voltage regulator, which allows the not operate properly with the Low-Power Sleep mode
device I/O pins to operate at voltages up to 5.5V while selected. The LDO will remain in the normal power
the internal device logic operates at a lower voltage. mode when those peripherals are enabled. The
The LDO and its associated reference circuitry must Low-Power Sleep mode is intended for use with these
remain active when the device is in Sleep mode. The peripherals:
PIC16F1526 allows the user to optimize the operating • Brown-Out Reset (BOR)
current in Sleep, depending on the application • Watchdog Timer (WDT)
requirements.
• External interrupt pin/Interrupt-on-change pins
A Low-Power Sleep mode can be selected by setting • Timer1 (with external clock source)
the VREGPM bit of the VREGCON register. With this
• CCP (Capture mode)
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
Note: The PIC16LF1526/7 does not have a
8.2.1 SLEEP CURRENT VS. WAKE-UP
configurable Low-Power Sleep mode.
TIME PIC16LF1526/7 is an unregulated device
In the default operating mode, the LDO and reference and is always in the lowest power state
circuitry remain in the normal configuration while in when in Sleep, with no wake-up time
Sleep. The device is able to exit Sleep mode quickly penalty. This device has a lower maximum
since all circuits remain active. In Low-Power Sleep VDD and I/O voltage than the
mode, when waking up from Sleep, an extra delay time PIC16LF1526/7. See Section 25.0
is required for these circuits to return to the normal “Electrical Specifications” for more
configuration and stabilize. information.
The Low-Power Sleep mode is beneficial for
applications that stay in Sleep mode for long periods of
time. The normal mode is beneficial for applications
that need to wake from Sleep quickly and frequently.

PIC16(L)F1526/7
8.3 Register Definitions: Voltage Regulator Control
REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1
— — — — — — VREGPM Reserved
bit 7 bit 0
Legend:

bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0 Reserved: Read as ‘1’. Maintain this bit set.
2: See Section 25.0 “Electrical Specifications”.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register on
Page
PIE1 TMR1GIE ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 77
PIE2 OSFIE TMR5GIE TMR3GIE — BCLIE TMR10IE TMR8IE CCP2IE 78
PIR1 TMR1GIF ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 81
VREGCON(1) — — — — — — VREGPM Reserved 89
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.

PIC16(L)F1526/7
9.0 LOW DROPOUT (LDO) On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
VOLTAGE REGULATOR
device is held in Reset while a constant current source
The PIC16F1526/7 has an internal Low Dropout charges the external capacitor. After the cap is fully
Regulator (LDO) which provides operation above 3.6V. charged, the device is released from Reset. For more
The LDO regulates a voltage for the internal device information on the constant current rate, refer to the
logic while permitting the VDD and I/O pins to operate LDO Regulator Characteristics Table in Section 25.0,
at a higher voltage. There is no user enable/disable Electrical Specifications.
control available for the LDO, it is always active. The
PIC16LF1526/7 operates at a maximum VDD of 3.6V
and does not incorporate an LDO.
A device I/O pin may be configured as the LDO voltage
output, identified as the VCAP pin. Although not
required, an external low-ESR capacitor may be con-
nected to the VCAP pin for additional regulator stability.
The VCAPEN bit of Configuration Words determines
which pin is assigned as the VCAP pin. Refer to Table 9-1.
TABLE 9-1: VCAPEN SELECT BIT

VCAPEN Pin
0 RF0
1 No Vcap
TABLE 9-2: SUMMARY OF CONFIGURATION WORD WITH LDO

Register
on Page
13:8 — LVP DEBUG LPBOR BORV STVREN —

CONFIG2 45
7:0 — — — VCAPEN(1) — — WRT<1:0>
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.

PIC16(L)F1526/7
10.0 WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11 23-bit Programmable

LFINTOSC WDT Time-out
Prescaler WDT
WDTE<1:0> = 10
Sleep
WDTPS<4:0>

PIC16(L)F1526/7
10.1 Independent Clock Source 10.3 Time-out Period
The WDT derives its time base from the 31 kHz The WDTPS bits of the WDTCON register set the
LFINTOSC internal oscillator. Time intervals in this time-out period from 1 ms to 256 seconds (nominal).
chapter are based on a nominal interval of 1 ms. See After a Reset, the default time-out period is 2 seconds.
Section 25.0 “Electrical Specifications” for the
LFINTOSC tolerances. 10.4 Clearing the WDT
10.2 WDT Operating Modes The WDT is cleared when any of the following condi-
tions occur:
The Watchdog Timer module has four operating modes • Any Reset
controlled by the WDTE<1:0> bits in Configuration
• CLRWDT instruction is executed
Words. See Table 10-1.
• Device enters Sleep
10.2.1 WDT IS ALWAYS ON • Device wakes up from Sleep
When the WDTE bits of Configuration Words are set to • Oscillator fail
‘11’, the WDT is always on. • WDT is disabled
WDT protection is active during Sleep. • Oscillator Start-up Timer (OST) is running
See Table 10-2 for more information.
10.2.2 WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Words are set to 10.5 Operation During Sleep
‘10’, the WDT is on, except in Sleep.
When the device enters Sleep, the WDT is cleared. If
WDT protection is not active during Sleep. the WDT is enabled during Sleep, the WDT resumes
counting.
10.2.3 WDT CONTROLLED BY SOFTWARE
When the device exits Sleep, the WDT is cleared
When the WDTE bits of Configuration Words are set to
again. The WDT remains clear until the OST, if
‘01’, the WDT is controlled by the SWDTEN bit of the
enabled, completes. See Section 5.0 “Oscillator
WDTCON register.
Module (with Fail-Safe Clock Monitor)” for more
WDT protection is unchanged by Sleep. See information on the OST.
Table 10-1 for more details.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
TABLE 10-1: WDT OPERATING MODES wakes up and resumes operation. The TO and PD bits
Device WDT in the STATUS register are changed to indicate the
WDTE<1:0> SWDTEN
Mode Mode event. The RWDT bit in the PCON register can also be
used. See Section 3.0 “Memory Organization” and
11 X X Active The STATUS register (Register 3-1) for more
information.
Awake Active
10 X
Sleep Disabled
1 X Active
01
0 X Disabled
00 X X Disabled
TABLE 10-2: WDT CLEARING CONDITIONS
Conditions WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF bits) Unaffected

PIC16(L)F1526/7
10.6 Register Definitions: Watchdog Control
REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0
— — WDTPS<4:0> SWDTEN
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets

bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)

01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 00:
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 1x:
Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

PIC16(L)F1526/7
TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
on Page
OSCCON — IRCF<3:0> — SCS<1:0> 61
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register
on Page

CONFIG1 43
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

PIC16(L)F1526/7
11.0 FLASH PROGRAM MEMORY 11.1.1 PMCON1 AND PMCON2
CONTROL REGISTERS
PMCON1 is the control register for Flash program
The Flash program memory is readable and writable
memory accesses.
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special Control bits RD and WR initiate read and write,
Function Registers (SFRs). The SFRs used to access respectively. These bits cannot be cleared, only set, in
program memory are: software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
• PMCON1
WR bit in software prevents the accidental, premature
• PMCON2 termination of a write operation.
• PMDATL
The WREN bit, when set, will allow a write operation to
• PMDATH occur. On power-up, the WREN bit is clear. The
• PMADRL WRERR bit is set when a write operation is interrupted
• PMADRH by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
When accessing the program memory, the
and execute the appropriate error handling routine.
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the The PMCON2 register is a write-only register. Attempting
PMADRH:PMADRL register pair forms a 2-byte word to read the PMCON2 register will return all ‘0’s.
that holds the 15-bit address of the program memory To enable writes to the program memory, a specific
location being read. pattern (the unlock sequence), must be written to the
The write time is controlled by an on-chip timer. The PMCON2 register. The required unlock sequence
write/erase voltages are generated by an on-chip charge prevents inadvertent writes to the program memory
pump rated to operate over the operating voltage range write latches and Flash program memory.
of the device.
The Flash program memory can be protected in two 11.2 Flash Program Memory Overview
ways; by code protection (CP bit in Configuration Words) It is important to understand the Flash program memory
and write protection (WRT<1:0> bits in Configuration structure for erase and programming operations. Flash
Words). program memory is arranged in rows. A row consists of
Code protection (CP = 0)(1), disables access, reading a fixed number of 14-bit program memory words. A row
and writing, to the Flash program memory via external is the minimum size that can be erased by user software.
device programmers. Code protection does not affect After a row has been erased, the user can reprogram
the self-write and erase functionality. Code protection all or a portion of this row. Data to be written into the
can only be reset by a device programmer performing program memory row is written to 14-bit wide data write
a Bulk Erase to the device, clearing all Flash program latches. These write latches are not directly accessible
memory, Configuration bits and User IDs. to the user, but may be loaded via sequential writes to
Write protection prohibits self-write and erase to a the PMDATH:PMDATL register pair.
portion or all of the Flash program memory as defined
Note: If the user wants to modify only a portion
by the bits WRT<1:0>. Write protection does not affect
of a previously programmed row, then the
a device programmers ability to read, write or erase the
contents of the entire row must be read
device.
and saved in RAM prior to the erase.
Note 1: Code protection of the entire Flash Then, new data and retained data can be
program memory array is enabled by written into the write latches to reprogram
clearing the CP bit of Configuration Words. the row of Flash program memory. How-
ever, any unprogrammed locations can be
11.1 PMADRL and PMADRH Registers written without first erasing the row. In this
case, it is not necessary to save and
The PMADRH:PMADRL register pair can address up rewrite the other previously programmed
to a maximum of 32K words of program memory. When locations.
selecting a program address value, the MSB of the
See Table 11-1 for Erase Row size and the number of
address is written to the PMADRH register and the LSB
write latches for Flash program memory.
is written to the PMADRL register.

PIC16(L)F1526/7
FIGURE 11-1: FLASH PROGRAM
TABLE 11-1: FLASH MEMORY MEMORY READ
ORGANIZATION BY DEVICE FLOWCHART
Write
Row Erase
Device Latches
(words)
(words) Start
Read Operation
PIC16(L)F1526
32 32
PIC16(L)F1527
Select
Program or Configuration Memory
11.2.1 READING THE FLASH PROGRAM (CFGS)
MEMORY
To read a program memory location, the user must:
Select
1. Write the desired address to the Word Address
PMADRH:PMADRL register pair. (PMADRH:PMADRL)
2. Clear the CFGS bit of the PMCON1 register.
3. Then, set control bit RD of the PMCON1 register.
Once the read control bit is set, the program memory Initiate Read Operation
(RD = 1)
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle, Instruction Fetched ignored
NOP execution forced
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
PMDATH:PMDATL register pair will hold this value until
Instruction Fetched ignored
another read or until it is written to by the user. NOP execution forced
Note: The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a Data read now in
two-cycle instruction on the next PMDATH:PMDATL
instruction after the RD bit is set.
End
Read Operation

PIC16(L)F1526/7
FIGURE 11-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR PC PC + 1 PMADRH,PMADRL PC +3

PC+3 PC + 4 PC + 5
Flash Data INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4)
INSTR(PC + 1) INSTR(PC + 2)
INSTR(PC - 1) BSF PMCON1,RD instruction ignored instruction ignored INSTR(PC + 3) INSTR(PC + 4)
executed here executed here Forced NOP Forced NOP executed here executed here
executed here executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 11-1: FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program

* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL ; Select Bank for PMCON registers

MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
MOVLW PROG_ADDR_HI ;
MOVWL PMADRH ; Store MSB of address
BCF PMCON1,CFGS ; Do not select Configuration Space

BSF PMCON1,RD ; Initiate read
NOP ; Ignored (Figure 11-2)
NOP ; Ignored (Figure 11-2)
MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

PIC16(L)F1526/7
11.2.2 FLASH MEMORY UNLOCK FIGURE 11-3: FLASH PROGRAM
SEQUENCE MEMORY UNLOCK
The unlock sequence is a mechanism that protects the SEQUENCE FLOWCHART
Flash program memory from unintended self-write
programming or erasing. The sequence must be
Start
executed and completed without interruption to
Unlock Sequence
successfully complete any of the following operations:
• Row Erase
• Load program memory write latches Write 055h to
• Write of program memory write latches to pro- PMCON2
gram memory
• Write of program memory write latches to User
IDs Write 0AAh to
PMCON2
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2
Initiate
2. Write AAh to PMCON2
Write or Erase Operation
3. Set the WR bit in PMCON1 (WR = 1)
4. NOP instruction
5. NOP instruction Instruction Fetched ignored
Once the WR bit is set, the processor will always force NOP execution forced
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is Instruction Fetched ignored
complete and then resume with the next instruction. NOP execution forced
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next End
instruction. Unlock Sequence
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.

PIC16(L)F1526/7
11.2.3 ERASING FLASH PROGRAM FIGURE 11-4: FLASH PROGRAM
MEMORY MEMORY ERASE
While executing code, program memory can only be FLOWCHART
erased by rows. To erase a row:
1. Load the PMADRH:PMADRL register pair with Start
any address within the row to be erased. Erase Operation
2. Clear the CFGS bit of the PMCON1 register.
3. Set the FREE and WREN bits of the PMCON1
register. Disable Interrupts
4. Write 55h, then AAh, to PMCON2 (Flash (GIE = 0)
programming unlock sequence).
5. Set control bit WR of the PMCON1 register to Select
begin the erase operation. Program or Configuration Memory
See Example 11-2. (CFGS)
After the “BSF PMCON1,WR” instruction, the processor

requires two cycles to set up the erase operation. The Select Row Address
user must place two NOP instructions immediately (PMADRH:PMADRL)
following the WR bit set instruction. The processor will
halt internal operations for the typical 2 ms erase time.
This is not Sleep mode as the clocks and peripherals Select Erase Operation
will continue to run. After the erase cycle, the processor (FREE = 1)
will resume operation with the third instruction after the
PMCON1 WRITE instruction.
Enable Write/Erase Operation
(WREN = 1)
Unlock Sequence
Figure 11-3
(FIGURE x-x)
CPU stalls while

Erase operation completes
(2ms typical)
Disable Write/Erase Operation

(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation

PIC16(L)F1526/7
EXAMPLE 11-2: ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF INTCON,GIE ; Disable ints so required sequences will execute properly

BANKSEL PMADRL
MOVF ADDRL,W ; Load lower 8 bits of erase address boundary
MOVWF PMADRL
MOVF ADDRH,W ; Load upper 6 bits of erase address boundary
MOVWF PMADRH
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,FREE ; Specify an erase operation
BSF PMCON1,WREN ; Enable writes
MOVLW 55h ; Start of required sequence to initiate erase

MOVWF PMCON2 ; Write 55h
Sequence
Required
MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin erase
NOP ; NOP instructions are forced as processor starts
NOP ; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction
BCF PMCON1,WREN ; Disable writes

BSF INTCON,GIE ; Enable interrupts

PIC16(L)F1526/7
11.2.4 WRITING TO FLASH PROGRAM The following steps should be completed to load the
MEMORY write latches and program a row of program memory.
These steps are divided into two parts. First, each write
Program memory is programmed using the following
latch is loaded with data from the PMDATH:PMDATL
steps:
using the unlock sequence with LWLO = 1. When the
1. Load the address in PMADRH:PMADRL of the last word to be loaded into the write latch is ready, the
row to be programmed. LWLO bit is cleared and the unlock sequence
2. Load each write latch with data. executed. This initiates the programming operation,
3. Initiate a programming operation. writing all the latches into Flash program memory.
4. Repeat steps 1 through 3 until all data is written. Note: The special unlock sequence is required
Before writing to program memory, the word(s) to be to load a write latch with data or initiate a
written must be erased or previously unwritten. Pro- Flash programming operation. If the
gram memory can only be erased one row at a time. No unlock sequence is interrupted, writing to
automatic erase occurs upon the initiation of the write. the latches or program memory will not be
initiated.
Program memory can be written one or more words at
a time. The maximum number of words written at one 1. Set the WREN bit of the PMCON1 register.
time is equal to the number of write latches. See 2. Clear the CFGS bit of the PMCON1 register.
Figure 11-5 (row writes to program memory with 32 3. Set the LWLO bit of the PMCON1 register.
write latches) for more details. When the LWLO bit of the PMCON1 register is
The write latches are aligned to the Flash row address ‘1’, the write sequence will only load the write
boundary defined by the upper 10-bits of latches and will not initiate the write to Flash
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) program memory.
with the lower 5-bits of PMADRL, (PMADRL<4:0>) 4. Load the PMADRH:PMADRL register pair with
determining the write latch being loaded. Write opera- the address of the location to be written.
tions do not cross these boundaries. At the completion 5. Load the PMDATH:PMDATL register pair with
of a program memory write operation, the data in the the program memory data to be written.
write latches is reset to contain 0x3FFF.
6. Execute the unlock sequence (Section 11.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 11.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
Note: The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 11-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.

FIGURE 11-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
DS40001458D-page 102
PIC16(L)F1526/7
7 6 0 7 5 4 0 7 5 0 7 0
PMADRH PMADRL - - PMDATH PMDATL
- r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 6 8
14
Program Memory Write Latches
10 5
14 14 14 14
Write Latch #0 Write Latch #1 Write Latch #30 Write Latch #31
PMADRL<4:0> 00h 01h 1Eh 1Fh
14 14 14 14
Row Addr Addr Addr Addr
000h 0000h 0001h 001Eh 001Fh
001h 0020h 0021h 003Eh 003Fh
002h 0040h 0041h 005Eh 005Fh

CFGS = 0
3FEh 7FC0h 7FC1h 7FDEh 7FDFh

Row 3FFh 7FE0h 7FE1h 7FFEh 7FFFh

PMADRH<6:0> Address
:PMADRL<7:5> Decode Flash Program Memory
400h 8000h - 8003h 8004h - 8005h 8006h 8007h – 8008h 8009h - 801Fh
DEVID Configuration
USER ID 0 - 3 reserved reserved
REVID Words
CFGS = 1
Configuration Memory
PIC16(L)F1526/7
FIGURE 11-6: FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
Write Operation
Determine number of words Enable Write/Erase

to be written into Program or Operation (WREN = 1)
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
(word_cnt) Load the value to write
(PMDATH:PMDATL)
Update the word counter Write Latches to Flash

Disable Interrupts
(word_cnt--) (LWLO = 0)
(GIE = 0)
Unlock Sequence
Select
Last word to Yes (Figure11-3
Figure x-x)
Program or Config. Memory
(CFGS) write ?
No CPU stalls while Write

Select Row Address operation completes
(PMADRH:PMADRL) (2ms typical)
Unlock Sequence
(Figure11-3
Figure x-x)
Select Write Operation

(FREE = 0)
Disable
No delay when writing to Write/Erase Operation
Program Memory Latches (WREN = 0)
Load Write Latches Only
(LWLO = 1)
Re-enable Interrupts
(GIE = 1)
Increment Address
(PMADRH:PMADRL++)
End
Erase Operation

PIC16(L)F1526/7
EXAMPLE 11-3: WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;
BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL PMADRH ; Bank 3
MOVF ADDRH,W ; Load initial address
MOVWF PMADRH ;
MOVF ADDRL,W ;
MOVWF PMADRL ;
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L ;
MOVLW HIGH DATA_ADDR ; Load initial data address
MOVWF FSR0H ;
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,WREN ; Enable writes
BSF PMCON1,LWLO ; Only Load Write Latches
LOOP
MOVIW FSR0++ ; Load first data byte into lower
MOVWF PMDATL ;
MOVIW FSR0++ ; Load second data byte into upper
MOVWF PMDATH ;
MOVF PMADRL,W ; Check if lower bits of address are '00000'

XORLW 0x1F ; Check if we're on the last of 32 addresses
ANDLW 0x1F ;
BTFSC STATUS,Z ; Exit if last of 32 words,
GOTO START_WRITE ;
MOVLW 55h ; Start of required write sequence:

MOVLW 0AAh ;
Sequence
Required

BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor
; loads program memory write latches
NOP ;
INCF PMADRL,F ; Still loading latches Increment address

GOTO LOOP ; Write next latches
START_WRITE
BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
MOVLW 55h ; Start of required write sequence:

Sequence
MOVLW 0AAh ;
Required

BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor writes
; all the program memory write latches simultaneously
NOP ; to program memory.
; After NOPs, the processor
; stalls until the self-write process in complete
; after write processor continues with 3rd instruction
BCF PMCON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts

PIC16(L)F1526/7
11.3 Modifying Flash Program Memory FIGURE 11-7: FLASH PROGRAM
MEMORY MODIFY
When modifying existing data in a program memory
FLOWCHART
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
Start
1. Load the starting address of the row to be Modify Operation
modified.
2. Read the existing data from the row into a RAM
image.
Read Operation
3. Modify the RAM image to contain the new data (Figure11-2
Figure x.x)
to be written into program memory.
4. Load the starting address of the row to be
rewritten. An image of the entire row read
5. Erase the program memory row. must be stored in RAM
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(Figure11-4
Figure x.x)
Write Operation
use RAM image
(Figure11-5
Figure x.x)
End
Modify Operation

PIC16(L)F1526/7
11.4 User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 11-2.
When read access is initiated on an address outside
the parameters listed in Table 11-2, the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.
TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8006h Device ID/Revision ID Yes No
8007h-8008h Configuration Words 1 and 2 Yes No
EXAMPLE 11-4: CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:
* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL ; Select correct Bank

MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
CLRF PMADRH ; Clear MSB of address
BSF PMCON1,CFGS ; Select Configuration Space

BCF INTCON,GIE ; Disable interrupts
BSF PMCON1,RD ; Initiate read
NOP ; Executed (See Figure 11-2)
NOP ; Ignored (See Figure 11-2)
BSF INTCON,GIE ; Restore interrupts
MOVF PMDATL,W ; Get LSB of word

MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location

PIC16(L)F1526/7
11.5 Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 11-8: FLASH PROGRAM

MEMORY VERIFY
FLOWCHART
Start
Verify Operation
This routine assumes that the last row

of data written was from an image
saved in RAM. This image will be used
to verify the data currently stored in
Flash Program Memory.
Read Operation
(Figure
Figure x.x)
11-2
PMDAT = No
RAM image
?
Yes Fail
Verify Operation
No Last
Word ?
Yes
End
Verify Operation

PIC16(L)F1526/7
11.6 Register Definitions: Flash Program Memory Control
REGISTER 11-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PMDAT<7:0>
bit 7 bit 0
Legend:
bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory
REGISTER 11-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — PMDAT<13:8>
bit 7 bit 0
Legend:

bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 11-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

PMADR<7:0>
bit 7 bit 0
Legend:
bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address
REGISTER 11-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—(1) PMADR<14:8>
bit 7 bit 0
Legend:

bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address
Note 1: Unimplemented, read as ‘1’.

PIC16(L)F1526/7
REGISTER 11-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
—(1) CFGS LWLO FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 6 CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash program memory
bit 5 LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches
will be initiated on the next WR command
bit 4 FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs an write operation on the next WR command
bit 3 WRERR: Program/Erase Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
on any set attempt (write ‘1’) of the WR bit).
0 = The program or erase operation completed normally.
bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1 WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive.
bit 0 RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0 = Does not initiate a program Flash read.
Note 1: Unimplemented bit, read as ‘1’.
2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1).
3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).

PIC16(L)F1526/7
REGISTER 11-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
Program Memory Control Register 2
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Register on
Page
PMCON1 —(1) CFGS LWLO FREE WRERR WREN WR RD 109
PMCON2 Program Memory Control Register 2 110
PMADRL PMADRL<7:0> 108
PMADRH —(1) PMADRH<6:0> 108
PMDATL PMDATL<7:0> 108
PMDATH — — PMDATH<5:0> 108
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Register
on Page
13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —

CONFIG1 43
CONFIG2 45
7:0 — — VCAPEN(1) — — WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.

PIC16(L)F1526/7
12.0 I/O PORTS FIGURE 12-1: GENERIC I/O PORT
OPERATION
In general, when a peripheral is enabled on a port pin,
that pin cannot be used as a general purpose output.
However, the pin can still be read.
Each port has three standard registers for its operation. Read LATx
TRISx
These registers are:
• TRISx registers (data direction) D Q
• PORTx registers (reads the levels on the pins of Write LATx

the device) Write PORTx
CK VDD
• LATx registers (output latch)
Data Register
Some ports may have one or more of the following
additional registers. These registers are: Data Bus
• ANSELx (analog select) I/O pin

Read PORTx
• WPUx (weak pull-up)
To digital peripherals
VSS
ANSELx
TABLE 12-1: PORT AVAILABILITY PER To analog peripherals
DEVICE
PORTB
PORTA
PORTG
PORTC
PORTD
PORTE
PORTF
Device
PIC16(L)F1526 ● ● ● ● ● ● ●
PIC16(L)F1527 ● ● ● ● ● ● ●
The Data Latch (LATA register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATA register has the same
effect as a write to the corresponding PORTA register.
A read of the LATA register reads of the values held in
the I/O PORT latches, while a read of the PORTA
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 12-1.

PIC16(L)F1526/7
12.1 Alternate Pin Function
The Alternate Pin Function Control (APFCON)
registers are used to steer specific peripheral input and
output functions between different pins. The APFCON
registers are shown in Register 12-1. For this device
family, the following functions can be moved between
different pins.
• Timer3
• CCP2
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
12.2 Register Definitions: Alternate Pin Function Control
REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
— — — — — — T3CKISEL CCP2SEL
bit 7 bit 0
Legend:

bit 1 T3CKISEL: Timer3 Input Selection bit
1 = T3CKI function is on RB4
0 = T3CKI function is on RB5
bit 0 CCP2SEL: Pin Selection bit
1 = CCP2 function is on RE7
0 = CCP2 function is on RC1

PIC16(L)F1526/7
12.3 PORTA Registers EXAMPLE 12-1: INITIALIZING PORTA
; This code example illustrates
12.3.1 DATA REGISTER ; initializing the PORTA register. The
PORTA is an 8-bit wide, bidirectional port. The ; other ports are initialized in the same
; manner.
corresponding data direction register is TRISA
(Register 12-3). Setting a TRISA bit (= 1) will make the BANKSEL PORTA ;
corresponding PORTA pin an input (i.e., disable the CLRF PORTA ;Init PORTA
output driver). Clearing a TRISA bit (= 0) will make the BANKSEL LATA ;Data Latch
corresponding PORTA pin an output (i.e., enables CLRF LATA ;
output driver and puts the contents of the output latch BANKSEL ANSELA ;
on the selected pin). Example 12-1 shows how to CLRF ANSELA ;digital I/O
initialize an I/O port. BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
Reading the PORTA register (Register 12-2) reads the MOVWF TRISA ;and set RA<2:0> as
status of the pins, whereas writing to it will write to the ;outputs
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then 12.3.4 PORTA FUNCTIONS AND OUTPUT
written to the PORT data latch (LATA). PRIORITIES
Each PORTA pin is multiplexed with other functions. The
12.3.2 DIRECTION CONTROL pins, their combined functions and their output priorities
The TRISA register (Register 12-3) controls the are shown in Table 12-2.
PORTA pin output drivers, even when they are being When multiple outputs are enabled, the actual pin
used as analog inputs. The user should ensure the bits control goes to the peripheral with the highest priority.
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog Analog input functions, such as ADC, are not shown in
input always read ‘0’. the priority lists. These inputs are active when the I/O
pin is set for Analog mode using the ANSELx registers.
12.3.3 ANALOG CONTROL Digital output functions may control the pin when it is in
Analog mode with the priority shown in the priority list
The ANSELA register (Register 12-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all TABLE 12-2: PORTA OUTPUT PRIORITY
digital reads on the pin to be read as ‘0’ and allow
Pin Name Function Priority(1)
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital RA0 RA0
output functions. A pin with TRIS clear and ANSEL set RA1 RA1
will still operate as a digital output, but the Input mode RA2 RA2
will be analog. This can cause unexpected behavior
RA3 RA3
when executing read-modify-write instructions on the
affected port. RA4 RA4
RA5 RA5
Note: The ANSELA bits default to the Analog
mode after Reset. To use any pins as RA6 CLKOUT
digital general purpose or peripheral OSC2
inputs, the corresponding ANSEL bits RA6
must be initialized to ‘0’ by user software. RA7 RA7
Note 1: Priority listed from highest to lowest.

PIC16(L)F1526/7
12.4 Register Definitions: PORTA
REGISTER 12-2: PORTA: PORTA REGISTER

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
bit 7-0 RA<7:0>: PORTA I/O Value bits(1)

1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O
pin values.
REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:
bit 7-0 TRISA<7:0>: PORTA Tri-State Control bits

1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER

LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0
bit 7 bit 0
Legend:
bit 7-0 LATA<7:0>: PORTA Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O
pin values.

PIC16(L)F1526/7
REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER

U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0
bit 7 bit 0
Legend:

bit 5 ANSA5: Analog Select between Analog or Digital Function on pins RA5, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 3-0 ANSA<3:0>: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Register
on Page
ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 115
APFCON — — — — — — T3CKISEL CCP2SEL 112
LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 114
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 114
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 114
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH PORTA

Register
on Page

CONFIG1 45
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.

PIC16(L)F1526/7
12.5 PORTB Registers 12.5.4 PORTB FUNCTIONS AND OUTPUT
PRIORITIES
12.5.1 DATA REGISTER Each PORTB pin is multiplexed with other functions. The
PORTB is an 8-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISB are shown in Table 12-5.
(Register 12-7). Setting a TRISB bit (= 1) will make the When multiple outputs are enabled, the actual pin
corresponding PORTB pin an input (i.e., put the control goes to the peripheral with the highest priority.
corresponding output driver in a High-Impedance mode). Analog input and some digital input functions are not
Clearing a TRISB bit (= 0) will make the corresponding included in the list below. These input functions can
PORTB pin an output (i.e., enable the output driver and remain active when the pin is configured as an output.
put the contents of the output latch on the selected pin). Certain digital input functions override other port
Example 12-1 shows how to initialize an I/O port. functions and are included in Table 12-5.
Reading the PORTB register (Register 12-6) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write TABLE 12-5: PORTB OUTPUT PRIORITY
operations. Therefore, a write to a port implies that the Pin Name Function Priority(1)
port pins are read, this value is modified and then written
RB0 RB0
to the PORT data latch (LATB).
RB1 RB1
12.5.2 DIRECTION CONTROL RB2 RB2
The TRISB register (Register 12-7) controls the PORTB RB3 CCP2
pin output drivers, even when they are being used as RB3
analog inputs. The user should ensure the bits in the RB4 RB4
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always RB5 RB5
read ‘0’. RB6 ICDCLK
RB6
12.5.3 ANALOG CONTROL RB7 ICDDAT
The ANSELB register (Register 12-9) is used to RB7
configure the Input mode of an I/O pin to analog. Note 1: Priority listed from highest to lowest.
Setting the appropriate ANSELB bit high will cause all
The state of the ANSELB bits has no effect on digital
output functions. A pin with TRIS clear and ANSELB set
will still operate as a digital output, but the Input mode
affected port.
Note: The ANSELB bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.

PIC16(L)F1526/7
12.6 Register Definitions: PORTB
REGISTER 12-6: PORTB: PORTB REGISTER

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
bit 7 bit 0
Legend:
bit 7-0 RB<7:0>: PORTB I/O Pin bits(1)

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
REGISTER 12-7: TRISB: PORTB TRI-STATE REGISTER

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
bit 7 bit 0
Legend:
bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
REGISTER 12-8: LATB: PORTB DATA LATCH REGISTER

LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
bit 7 bit 0
Legend:
bit 7-0 LATB<7:0>: PORTB Output Latch Value bits(1)
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is

PIC16(L)F1526/7
REGISTER 12-9: ANSELB: PORTB ANALOG SELECT REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0
bit 7 bit 0
Legend:

bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively
REGISTER 12-10: WPUB: WEAK PULL-UP PORTB REGISTER

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0
Legend:
bit 7-0 WPUB<7:0>: Weak Pull-up Register bits

1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register
on Page

ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 118
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 117
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 117
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 117
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 118
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTB.

PIC16(L)F1526/7
12.7 PORTC Registers 12.7.3 PORTC FUNCTIONS AND OUTPUT
PRIORITIES
12.7.1 DATA REGISTER Each PORTC pin is multiplexed with other functions. The
PORTC is an 8-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISC are shown in Table 12-7.
(Register 12-12). Setting a TRISC bit (= 1) will make the When multiple outputs are enabled, the actual pin
corresponding PORTC pin an input (i.e., put the control goes to the peripheral with the highest priority.
Clearing a TRISC bit (= 0) will make the corresponding included in the list below. These input functions can
PORTC pin an output (i.e., enable the output driver and remain active when the pin is configured as an output.
Example 12-1 shows how to initialize an I/O port. functions and are included in the priority list.
Reading the PORTC register (Register 12-11) reads the
PORT latch. All write operations are read-modify-write TABLE 12-7: PORTC OUTPUT PRIORITY
RC0 SOSCO
to the PORT data latch (LATC).
RC0
12.7.2 DIRECTION CONTROL RC1 SOSCI
CCP2
The TRISC register (Register 12-12) controls the
RC1
PORTC pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in RC2 CCP1
the TRISC register are maintained set when using them RC2
as analog inputs. I/O pins configured as analog input RC3 SCL1
always read ‘0’. SCK1
RC3(2)
RC4 SDA1
RC4(2)
RC5 SDO1
RC5
RC6 CK1
TX1
RC6
RC7 DT1
RC7
2: RC3 and RC4 read the I2C ST input when
I2C mode is enabled.

PIC16(L)F1526/7
12.8 Register Definitions: PORTC
REGISTER 12-11: PORTC: PORTC REGISTER

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits(1)

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
REGISTER 12-12: TRISC: PORTC TRI-STATE REGISTER

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0
Legend:
bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
REGISTER 12-13: LATC: PORTC DATA LATCH REGISTER

LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0
bit 7 bit 0
Legend:
bit 7-0 LATC<7:0>: PORTC Output Latch Value bits(1)
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is

PIC16(L)F1526/7
TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Register
on Page

LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 117
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 117
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 120
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

PIC16(L)F1526/7
12.9 PORTD Registers 12.9.4 PORTD FUNCTIONS AND OUTPUT
PRIORITIES
12.9.1 DATA REGISTER Each PORTD pin is multiplexed with other functions. The
PORTD is an 8-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISD are shown in Table 12-9.
(Register 12-15). Setting a TRISD bit (= 1) will make the When multiple outputs are enabled, the actual pin
corresponding PORTD pin an input (i.e., put the control goes to the peripheral with the highest priority.
Clearing a TRISD bit (= 0) will make the corresponding included in the list below. These input functions can
PORTD pin an output (i.e., enable the output driver and remain active when the pin is configured as an output.
Reading the PORTD register (Register 12-14) reads the
PORT latch. All write operations are read-modify-write TABLE 12-9: PORTD OUTPUT PRIORITY
RD0 RD0
to the PORT data latch (LATD).
RD1 RD1
12.9.2 DIRECTION CONTROL RD2 RD2
The TRISD register (Register 12-15) controls the RD3 RD3
PORTD pin output drivers, even when they are being RD4 SDO2
used as analog inputs. The user should ensure the bits in RD4
the TRISD register are maintained set when using them
as analog inputs. I/O pins configured as analog input RD5 SDA2
always read ‘0’. RD5(2)
RD6 SCL2
12.9.3 ANALOG CONTROL SCK2
The ANSELD register (Register 12-17) is used to RD6(2)
configure the Input mode of an I/O pin to analog. RD7 RD7
Setting the appropriate ANSELD bit high will cause all Note 1: Priority listed from highest to lowest.
digital reads on the pin to be read as ‘0’ and allow 2: RD5 and RD6 read the I2C ST input when
analog functions on the pin to operate correctly. I2C mode is enabled.
The state of the ANSELD bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSEL set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when exe-
cuting read-modify-write instructions on the affected
port.
Note: The ANSELD bits default to the Analog

PIC16(L)F1526/7
12.10 Register Definitions: PORTD
REGISTER 12-14: PORTD: PORTD REGISTER

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
bit 7 bit 0
Legend:
bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bits(1)

Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is
REGISTER 12-15: TRISD: PORTD TRI-STATE REGISTER

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
bit 7 bit 0
Legend:
bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits

1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output
REGISTER 12-16: LATD: PORTD DATA LATCH REGISTER

LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0
bit 7 bit 0
Legend:
bit 7-0 LATD<7:0>: PORTD Output Latch Value bits(1)
Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is

PIC16(L)F1526/7
REGISTER 12-17: ANSELD: PORTD ANALOG SELECT REGISTER

U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— — — — ANSD3 ANSD2 ANSD1 ANSD0
bit 7 bit 0
Legend:

bit 3-0 ANSD<3:0>: Analog Select between Analog or Digital Function on pins RD<3:0>, respectively
REGISTER 12-18: WPUD: WEAK PULL-UP PORTD REGISTER

WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0
bit 7 bit 0
Legend:
bit 7-0 WPUD<7:0>: Weak Pull-up Register bits

1 = Pull-up enabled
TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Register
on Page
ANSELD — — — — ANSD3 ANSD2 ANSD1 ANSD0 118

LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 117
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 117
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 123
WPUD WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 124
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.

PIC16(L)F1526/7
12.11 PORTE Registers 12.11.4 PORTE FUNCTIONS AND OUTPUT
PRIORITIES
12.11.1 DATA REGISTER Each PORTE pin is multiplexed with other functions. The
PORTE is an 8-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISE are shown in Table 12-11.
(Register 12-20). Setting a TRISE bit (= 1) will make the When multiple outputs are enabled, the actual pin
corresponding PORTE pin an input (i.e., put the control goes to the peripheral with the highest priority.
Clearing a TRISE bit (= 0) will make the corresponding included in the list below. These input functions can
PORTE pin an output (i.e., enable the output driver and remain active when the pin is configured as an output.
Reading the PORTE register (Register 12-19) reads the
PORT latch. All write operations are read-modify-write TABLE 12-11: PORTE OUTPUT PRIORITY
RE0 RE0
to the PORT data latch (LATE).
RE1 RE1
12.11.2 DIRECTION CONTROL RE2 CCP10
The TRISE register (Register 12-20) controls the PORTE RE2
pin output drivers, even when they are being used as RE3 CCP9
analog inputs. The user should ensure the bits in the RE3
TRISE register are maintained set when using them as RE4 CCP8
analog inputs. I/O pins configured as analog input always RE4
read ‘0’.
RE5 CCP7
12.11.3 ANALOG CONTROL RE5
The ANSELE register (Register 12-22) is used to RE6 CCP6
configure the Input mode of an I/O pin to analog. RE6
Setting the appropriate ANSELE bit high will cause all RE7 CCP2
digital reads on the pin to be read as ‘0’ and allow RE7
analog functions on the pin to operate correctly. Note 1: Priority listed from highest to lowest.
The state of the ANSELE bits has no effect on digital
output functions. A pin with TRIS clear and ANSELE set
affected port.
Note: The ANSELE bits default to the Analog

PIC16(L)F1526/7
12.12 Register Definitions: PORTE
REGISTER 12-19: PORTE: PORTE REGISTER

RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
bit 7 bit 0
Legend:
bit 7-0 RE<7:0>: PORTE General Purpose I/O Pin bits(1)

Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is
REGISTER 12-20: TRISE: PORTE TRI-STATE REGISTER

TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0
bit 7 bit 0
Legend:
bit 7-0 TRISE<7:0>: PORTE Tri-State Control bits

1 = PORTE pin configured as an input (tri-stated)
0 = PORTE pin configured as an output
REGISTER 12-21: LATE: PORTE DATA LATCH REGISTER

LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0
bit 7 bit 0
Legend:
bit 7-0 LATE<7:0>: PORTE Output Latch Value bits(1)
Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is

PIC16(L)F1526/7
REGISTER 12-22: ANSELE: PORTE ANALOG SELECT REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1
— — — — — ANSE2 ANSE1 ANSE0
bit 7 bit 0
Legend:

bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on pins RE<2:0>, respectively
REGISTER 12-23: WPUE: WEAK PULL-UP PORTE REGISTER

WPUE7 WPUE6 WPUE5 WPUE4 WPUE3 WPUE2 WPUE1 WPUE0
bit 7 bit 0
Legend:
bit 7-0 WPUE<7:0>: Weak Pull-up Register bits

1 = Pull-up enabled
TABLE 12-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Register
on Page

ANSELE — — — — — ANSE2 ANSE1 ANSE0 127
LATE LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 126
PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 126
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 126
WPUE WPUE7 WPUE6 WPUE5 WPUE4 WPUE3 WPUE2 WPUE1 WPUE0 127
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.

PIC16(L)F1526/7
12.13 PORTF Registers 12.13.4 PORTE FUNCTIONS AND OUTPUT
PRIORITIES
12.13.1 DATA REGISTER Each PORTF pin is multiplexed with other functions. The
PORTF is an 8-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISF are shown in Table 12-13.
(Register 12-25). Setting a TRISF bit (= 1) will make the When multiple outputs are enabled, the actual pin
corresponding PORTF pin an input (i.e., put the control goes to the peripheral with the highest priority.
Clearing a TRISF bit (= 0) will make the corresponding included in the list below. These input functions can
PORTF pin an output (i.e., enable the output driver and remain active when the pin is configured as an output.
Reading the PORTF register (Register 12-24) reads the
PORT latch. All write operations are read-modify-write TABLE 12-13: PORTF OUTPUT PRIORITY
RF0 VCAP(2)
to the PORT data latch (LATF).
RF0
12.13.2 DIRECTION CONTROL RF1 RF1
The TRISF register (Register 12-25) controls the PORTF RF2 RF2
pin output drivers, even when they are being used as RF3 RF3
analog inputs. The user should ensure the bits in the RF4 RF4
TRISF register are maintained set when using them as
analog inputs. I/O pins configured as analog input always RF5 RF5
read ‘0’. RF6 RF6
RF7 RF7
12.13.3 ANALOG CONTROL
The ANSELF register (Register 12-27) is used to 2: PIC16F1526/7 only
Setting the appropriate ANSELF bit high will cause all
The state of the ANSELF bits has no effect on digital
output functions. A pin with TRIS clear and ANSELF set
affected port.
Note: The ANSELF bits default to the Analog

PIC16(L)F1526/7
12.14 Register Definitions: PORTF
REGISTER 12-24: PORTF: PORTF REGISTER

RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0
bit 7 bit 0
Legend:
bit 7-0 RF<7:0>: PORTF General Purpose I/O Pin bits(1)

Note 1: Writes to PORTF are actually written to corresponding LATF register. Reads from PORTF register is return
of actual I/O pin values.
REGISTER 12-25: TRISF: PORTF TRI-STATE REGISTER

TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0
bit 7 bit 0
Legend:
bit 7-0 TRISF<7:0>: PORTF Tri-State Control bits

1 = PORTF pin configured as an input (tri-stated)
0 = PORTF pin configured as an output
REGISTER 12-26: LATF: PORTF DATA LATCH REGISTER

LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0
bit 7 bit 0
Legend:
bit 7-0 LATF<7:0>: PORTF Output Latch Value bits(1)
Note 1: Writes to PORTF are actually written to corresponding LATF register. Reads from PORTF register is return
of actual I/O pin values.

PIC16(L)F1526/7
REGISTER 12-27: ANSELF: PORTF ANALOG SELECT REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0
bit 7 bit 0
Legend:
bit 7-0 ANSF<7:0>: Analog Select between Analog or Digital Function on pins RF<7:0>, respectively
TABLE 12-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF

Register
on Page
ANSELF ANSF7 ANSF6 ANSF5 ANSF4 ANSF3 ANSF2 ANSF1 ANSF0 130
LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 129
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 129
TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 129
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTF.
TABLE 12-15: SUMMARY OF CONFIGURATION WORD WITH PORTF

Register
on Page

CONFIG2 45
7:0 — — — VCAPEN(1) — — WRT<1:0>
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTF.

PIC16(L)F1526/7
12.15 PORTG Registers 12.15.4 PORTG FUNCTIONS AND OUTPUT
PRIORITIES
12.15.1 DATA REGISTER
Each PORTG pin is multiplexed with other functions. The
PORTG is a 6-bit wide, bidirectional port. The pins, their combined functions and their output priorities
corresponding data direction register is TRISG are shown in Table 12-16.
(Register 12-29). Setting a TRISG bit (= 1) will make the
When multiple outputs are enabled, the actual pin
corresponding PORTG pin an input (i.e., disable the
control goes to the peripheral with the highest priority.
output driver). Clearing a TRISG bit (= 0) will make the
corresponding PORTG pin an output (i.e., enables Analog input functions, such as ADC, are not shown in
output driver and puts the contents of the output latch the priority lists. These inputs are active when the I/O
on the selected pin). The exception is RG5, which is pin is set for Analog mode using the ANSELx registers.
input only and its TRIS bit will always read as ‘1’. Digital output functions may control the pin when it is in
Example 12-1 shows how to initialize an I/O port. Analog mode with the priority list.
Reading the PORTG register (Register 12-28) reads
the status of the pins, whereas writing to it will write to TABLE 12-16: PORTG OUTPUT PRIORITY
the PORT latch. All write operations are
Pin Name Function Priority(1)
read-modify-write operations. Therefore, a write to a
port implies that the port pins are read, this value is RG0 CCP3
modified and then written to the PORT data latch RG0
(LATG). RG1 CK2
TX2
12.15.2 DIRECTION CONTROL RG1
The TRISG register (Register 12-29) controls the RG2 DT2
PORTG pin output drivers, even when they are being RG2
used as analog inputs. The user should ensure the bits
RG3 CCP4
in the TRISG register are maintained set when using
RG3
them as analog inputs. I/O pins configured as analog
input always read ‘0’. RG4 CCP5
RG4
12.15.3 ANALOG CONTROL RG5 Input only pin
The ANSELG register (Register 12-31) is used to Note 1: Priority listed from highest to lowest.
Setting the appropriate ANSELG bit high will cause all
The state of the ANSELG bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
affected port.
Note: The ANSELG bits default to the Analog

PIC16(L)F1526/7
12.16 Register Definitions: PORTG
REGISTER 12-28: PORTG: PORTG REGISTER
U-0 U-0 R-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — RG5 RG4 RG3 RG2 RG1 RG0
bit 7 bit 0
Legend:

bit 5-0 RG<5:0>: PORTG I/O Pin bits(1)
Note 1: Writes to PORTG are actually written to corresponding LATG register. Reads from PORTG register is
REGISTER 12-29: TRISG: PORTG TRI-STATE REGISTER

U-0 U-0 U-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — —(1) TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
bit 7 bit 0
Legend:
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

bit 4-0 TRISG<4:0>: RG<4:0> Tri-State Control bits(1)
1 = PORTG pin configured as an input (tri-stated)
0 = PORTG pin configured as an output

PIC16(L)F1526/7
REGISTER 12-30: LATG: PORTG DATA LATCH REGISTER

U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — LATG4 LATG3 LATG2 LATG1 LATG0
bit 7 bit 0
Legend:

bit 4-0 LATG<4:0>: PORTG Output Latch Value bits(1)
Note 1: Writes to PORTG are actually written to corresponding LATG register. Reads from PORTG register is
REGISTER 12-31: ANSELG: PORTG ANALOG SELECT REGISTER

U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 U-0
— — — ANSG4 ANSG3 ANSG2 ANSG1 —
bit 7 bit 0
Legend:
u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

bit 4-1 ANSG<4:1>: Analog Select between Analog or Digital Function on Pins RG<4:1>, respectively

PIC16(L)F1526/7
REGISTER 12-32: WPUG: WEAK PULL-UP PORTG REGISTER

U-0 U-0 R/W-1/1 U-0 U-0 U-0 U-0 U-0
— — WPUG5 — — — — —
bit 7 bit 0
Legend:

bit 5 WPUG5: Weak Pull-up Register bit
1 = Pull-up enabled
TABLE 12-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG

Register
on Page
ANSELG — — — ANSG4 ANSG3 ANSG2 ANSG1 — 133
LATG — — — LATG4 LATG3 LATG2 LATG1 LATG0 133
PORTG — — RG5 RG4 RG3 RG2 RG1 RG0 132
TRISG — — —(1) TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 132
WPUG — — WPUG5 — — — — — 134
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTG.
TABLE 12-18: SUMMARY OF CONFIGURATION WORD WITH PORTG

Register
on Page

CONFIG1 45
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTG.

PIC16(L)F1526/7
13.0 INTERRUPT-ON-CHANGE 13.3 Interrupt Flags
The PORTB pins can be configured to operate as The IOCBFx bits located in the IOCBF register are
Interrupt-On-Change (IOC) pins. An interrupt can be status flags that correspond to the Interrupt-on-change
generated by detecting a signal that has either a rising pins of PORTB. If an expected edge is detected on an
edge or a falling edge. Any individual PORTB pin, or appropriately enabled pin, then the status flag for that pin
combination of PORTB pins, can be configured to will be set, and an interrupt will be generated if the IOCIE
generate an interrupt. The interrupt-on-change module bit is set. The IOCIF bit of the INTCON register reflects
has the following features: the status of all IOCBFx bits.
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
13.4 Clearing Interrupt Flags
• Rising and falling edge detection The individual status flags, (IOCBFx bits), can be
• Individual pin interrupt flags cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
Figure 13-1 is a block diagram of the IOC module.
status flag will be set at the end of the sequence,
regardless of the value actually being written.
13.1 Enabling the Module
In order to ensure that no detected edge is lost while
To allow individual PORTB pins to generate an interrupt, clearing flags, only AND operations masking out known
the IOCIE bit of the INTCON register must be set. If the changed bits should be performed. The following
IOCIE bit is disabled, the edge detection on the pin will sequence is an example of what should be performed.
still occur, but an interrupt will not be generated.
EXAMPLE 13-1: CLEARING INTERRUPT
13.2 Individual Pin Configuration FLAGS
(PORTA EXAMPLE)
For each PORTB pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a MOVLW 0xff
rising edge, the associated IOCBPx bit of the IOCBP XORWF IOCAF, W
register is set. To enable a pin to detect a falling edge, ANDWF IOCAF, F
the associated IOCBNx bit of the IOCBN register is set.
A pin can be configured to detect rising and falling 13.5 Operation in Sleep
edges simultaneously by setting both the IOCBPx bit
and the IOCBNx bit of the IOCBP and IOCBN registers, The interrupt-on-change interrupt sequence will wake
respectively. the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCBF
register will be updated prior to the first instruction
executed out of Sleep.

PIC16(L)F1526/7
FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM
IOCBNx D Q4Q1
Q
CK edge
detect
R
RBx
data bus = S to data bus

IOCBPx D Q 0 or 1 D Q IOCBFx
CK write IOCBFx CK
IOCIE
R
Q2
from all other
IOCBFx individual IOC interrupt
pin detectors to CPU core
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4 Q4
Q4Q1 Q4Q1 Q4Q1 Q4Q1

PIC16(L)F1526/7
13.6 Register Definitions: Interrupt-on-change Control
REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER

IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
bit 7 bit 0
Legend:
bit 7-0 IOCBP<7:0>: Interrupt-on-Change PORTB Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be
set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin
REGISTER 13-2: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER

IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0
bit 7 bit 0
Legend:
bit 7-0 IOCBN<7:0>: Interrupt-on-Change PORTB Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be
set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin
REGISTER 13-3: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
bit 7-0 IOCBF<7:0>: Interrupt-on-Change PORTB Flag bits

1 = An enabled change was detected on the associated pin.
Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge
was detected on RBx.
0 = No change was detected, or the user cleared the detected change.

PIC16(L)F1526/7
TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
on Page
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change.

PIC16(L)F1526/7
14.0 FIXED VOLTAGE REFERENCE 14.1 Independent Gain Amplifiers
(FVR) The output of the FVR supplied to the ADC module is
The Fixed Voltage Reference, or FVR, is a stable routed through two independent programmable gain
voltage reference, independent of VDD, with 1.024V, amplifiers. Each amplifier can be configured to amplify
2.048V or 4.096V selectable output levels. The output the reference voltage by 1x, 2x or 4x, to produce the
of the FVR can be configured to supply a reference three possible voltage levels.
voltage to the following: The ADFVR<1:0> bits of the FVRCON register are
• ADC input channel used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Refer-
• ADC positive reference
ence Section 16.0 “Analog-to-Digital Converter
The FVR can be enabled by setting the FVREN bit of (ADC) Module” for additional information.
the FVRCON register.
14.2 FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 25.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
x1
FVR_buffer1
x2
(To ADC Module)
x4
1.024V Fixed
Reference
FVREN +
FVRRDY
-
Any peripheral requiring
the Fixed Reference
(See Table 14-1)
TABLE 14-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)

Peripheral Conditions Description
HFINTOSC FOSC<2:0> = 100 and INTOSC is active and device is not in Sleep.
IRCF<3:0> = 000x
BOREN<1:0> = 11 BOR always enabled.
BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled.
BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled.
LDO All PIC16F1526/7 devices, when The device runs off of the low-power regulator when in Sleep
VREGPM = 1 and not in Sleep mode.

PIC16(L)F1526/7
14.3 Register Definitions: FVR Control
REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0 R-q/q R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
FVREN FVRRDY(1) TSEN TSRNG — — ADFVR<1:0>
bit 7 bit 0
Legend:
bit 7 FVREN: Fixed Voltage Reference Enable bit

1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5 TSEN: Temperature Indicator Enable bit
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4 TSRNG: Temperature Indicator Range Selection bit
1 = VOUT = VDD - 4VT (High Range)
0 = VOUT = VDD - 2VT (Low Range)
bit 1-0 ADFVR<1:0>: ADC Fixed Voltage Reference Selection bits
11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
00 = ADC Fixed Voltage Reference Peripheral output is off
Note 1: FVRRDY is always ‘1’ on PIC16F1526/7 only.

2: Fixed Voltage Reference output cannot exceed VDD.
TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR<1:0> 140
Legend: Shaded cells are unused by the Fixed Voltage Reference.

PIC16(L)F1526/7
15.0 TEMPERATURE INDICATOR FIGURE 15-1: TEMPERATURE CIRCUIT
MODULE DIAGRAM
This family of devices is equipped with a temperature

circuit designed to measure the operating temperature VDD
of the silicon die. The circuit’s range of operating
TSEN
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC. TSRNG
The circuit may be used as a temperature threshold

detector or a more accurate temperature indicator,
depending on the level of calibration performed. A
one-point calibration allows the circuit to indicate a
VOUT
temperature closely surrounding that point. A two-point To ADC
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, Use and Calibration of the Internal
Temperature Indicator (DS01333) for more details
regarding the calibration process.
15.1 Circuit Operation 15.2 Minimum Operating VDD

Figure 15-1 shows a simplified block diagram of the When the temperature circuit is operated in low range,
temperature circuit. The proportional voltage output is the device may be operated at any operating voltage
achieved by measuring the forward voltage drop across that is within specifications.
multiple silicon junctions.
When the temperature circuit is operated in high range,
Equation 15-1 describes the output characteristics of the device operating voltage, VDD, must be high
the temperature indicator. enough to ensure that the temperature circuit is cor-
rectly biased.
EQUATION 15-1: VOUT RANGES Table 15-1 shows the recommended minimum VDD vs.
range setting.
High Range: VOUT = VDD - 4VT
TABLE 15-1: RECOMMENDED VDD VS.
Low Range: VOUT = VDD - 2VT RANGE
Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0
The temperature sense circuit is integrated with the 3.6V 1.8V
Fixed Voltage Reference (FVR) module. See
Section 14.0 “Fixed Voltage Reference (FVR)” for 15.3 Temperature Output
more information.
The circuit is enabled by setting the TSEN bit of the The output of the circuit is measured using the internal
FVRCON register. When disabled, the circuit draws no Analog-to-Digital Converter. A channel is reserved for
current. the temperature circuit output. Refer to Section 16.0
“Analog-to-Digital Converter (ADC) Module” for
The circuit operates in either high or low range. The high detailed information.
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This Note: Every time the ADC MUX is changed to
provides more resolution over the temperature range, the temperature indicator output selection
but may be less consistent from part to part. This range (CHS bit in the ADCCON0 register), wait
requires a higher bias voltage to operate and thus, a 500 sec for the sampling capacitor to fully
higher VDD is needed. charge before sampling the temperature
indicator output.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.

PIC16(L)F1526/7
15.4 ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR

Register
on page
FVRCON FVREN FVRRDY TSEN TSRNG — — ADFVR<1:0> 140
Legend: Shaded cells are unused by the temperature indicator module.

PIC16(L)F1526/7
16.0 ANALOG-TO-DIGITAL The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
CONVERTER (ADC) MODULE
device from Sleep.
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 16-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
FIGURE 16-1: ADC BLOCK DIAGRAM
AVDD
ADPREF = 00
ADPREF = 11
VREF ADPREF = 10
AN0 00000
AN1 00001
AN2 00010
VREF+/AN3 00011 Ref+
AN4 00100
ADC
AN5 00101
GO/DONE 10
AN6 00110
0 = Left Justify
ADFM
1 = Right Justify
ADON(1) 16
AN29 11101
Temp Indicator 11110 AVSS ADRESH ADRESL
FVR Buffer1 11111
CHS<4:0>(2)
Note 1: When ADON = 0, all multiplexer inputs are disconnected.

2: See ADCON0 register (Example 16-1) for detailed analog channel selection per device.

PIC16(L)F1526/7
16.1 ADC Configuration 16.1.4 CONVERSION CLOCK
When configuring and using the ADC the following The source of the conversion clock is software
functions must be considered: selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
• Port configuration
• FOSC/2
• Channel selection
• FOSC/4
• ADC voltage reference selection
• FOSC/8
• ADC conversion clock source
• FOSC/16
• Interrupt control
• FOSC/32
• Result formatting
• FOSC/64
16.1.1 PORT CONFIGURATION • FRC (dedicated internal FRC oscillator)
The ADC can be used to convert both analog and The time to complete one bit conversion is defined as
digital signals. When converting analog signals, the I/O TAD. One full 10-bit conversion requires 11.5 TAD
pin should be configured for analog by setting the periods as shown in Figure 16-2.
associated TRIS and ANSEL bits. Refer to For correct conversion, the appropriate TAD
Section 12.0 “I/O Ports” for more information. specification must be met. Refer to the ADC conversion
Note: Analog voltages on any pin that is defined requirements in Section 25.0 “Electrical
as a digital input may cause the input buf- Specifications” for more information. Table 16-1 gives
fer to conduct excess current. examples of appropriate ADC clock selections.
Note: Unless using the FRC, any changes in the
16.1.2 CHANNEL SELECTION system clock frequency will change the
There are 32 channel selections available: ADC clock frequency, which may
adversely affect the ADC result.
• AN<29:0> pins
• Temperature Indicator
• FVR (Fixed Voltage Reference) Output
Refer to Section 14.0 “Fixed Voltage Reference
(FVR)” and Section 15.0 “Temperature Indicator
Module” for more information on these channel
selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 16.2
“ADC Operation” for more information.
16.1.3 ADC VOLTAGE REFERENCE

The ADPREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be:
• VREF+ pin
• VDD
• FVR 2.048V
• FVR 4.096V (Not available on LF devices)
See Section 14.0 “Fixed Voltage Reference (FVR)”
for more details on the Fixed Voltage Reference.

PIC16(L)F1526/7
TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC
ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source
FOSC/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
FOSC/4 100 200 ns (2)
250 ns (2)
500 ns (2)
1.0 s 4.0 s
FOSC/8 001 400 ns(2) 0.5 s(2) 1.0 s 2.0 s 8.0 s(3)
FOSC/16 101 800 ns 1.0 s 2.0 s 4.0 s 16.0 s(3)
FOSC/32 010 1.6 s 2.0 s 4.0 s 8.0 s(3)
32.0 s(3)
FOSC/64 110 3.2 s 4.0 s 8.0 s (3)
16.0 s (3)
64.0 s(3)
FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.

PIC16(L)F1526/7
16.1.5 INTERRUPTS 16.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an The 10-bit ADC conversion result can be supplied in
interrupt upon completion of an Analog-to-Digital two formats, left justified or right justified. The ADFM bit
conversion. The ADC Interrupt Flag is the ADIF bit in of the ADCON1 register controls the output format.
the PIR1 register. The ADC Interrupt Enable is the Figure 16-3 shows the two output formats.
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
FIGURE 16-3: 10-BIT ADC CONVERSION RESULT FORMAT
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit ADC Result Unimplemented: Read as ‘0’
(ADFM = 1) MSB LSB

bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit ADC Result

PIC16(L)F1526/7
16.2 ADC Operation 16.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
16.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC
To enable the ADC module, the ADON bit of the option. When the FRC oscillator source is selected, the
ADCON0 register must be set to a ‘1’. Setting the ADC waits one additional instruction before starting the
GO/DONE bit of the ADCON0 register to a ‘1’ will start conversion. This allows the SLEEP instruction to be
the Analog-to-Digital conversion. executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
Note: The GO/DONE bit should not be set in the
will wake-up from Sleep when the conversion
same instruction that turns on the ADC.
completes. If the ADC interrupt is disabled, the ADC
Refer to Section 16.2.6 “ADC Conver-
module is turned off after the conversion completes,
sion Procedure”.
although the ADON bit remains set.
16.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
When the conversion is complete, the ADC module will: sion to be aborted and the ADC module is turned off,
• Clear the GO/DONE bit although the ADON bit remains set.
• Set the ADIF Interrupt Flag bit
16.2.5 SPECIAL EVENT TRIGGER
• Update the ADRESH and ADRESL registers with
new conversion result The Special Event Trigger of the CCPx module allows
periodic ADC measurements without software
16.2.3 TERMINATING A CONVERSION intervention. When this trigger occurs, the GO/DONE
If a conversion must be terminated before completion, bit is set by hardware and the Timer1 counter resets to
the GO/DONE bit can be cleared in software. The zero.
ADRESH and ADRESL registers will be updated with TABLE 16-2: SPECIAL EVENT TRIGGER
the partially complete Analog-to-Digital conversion Device CCP
sample. Incomplete bits will match the last bit
converted. PIC16(L)F1526/7 CCP10
Note: A device Reset forces all registers to their Using the Special Event Trigger does not assure proper
Reset state. Thus, the ADC module is ADC timing. It is the user’s responsibility to ensure that
turned off and any pending conversion is the ADC timing requirements are met.
terminated. Refer to Section 20.0 “Capture/Compare/PWM
Modules” for more information.

PIC16(L)F1526/7
16.2.6 ADC CONVERSION PROCEDURE EXAMPLE 16-1: ADC CONVERSION
This is an example procedure for using the ADC to ;This code block configures the ADC
perform an Analog-to-Digital conversion: ;for polling, VDD and VSS references, Frc
;clock and AN0 input.
1. Configure Port:
;
• Disable pin output driver (Refer to the TRIS ;Conversion start & polling for completion
register) ; are included.
• Configure pin as analog (Refer to the ANSEL ;
register) BANKSEL ADCON1 ;
MOVLW B’11110000’ ;Right justify, Frc
• Disable weak pull-ups either globally (Refer ;clock
to the OPTION_REG register) or individually MOVWF ADCON1 ;Vdd and Vss Vref
(Refer to the appropriate WPUx register) BANKSEL TRISA ;
2. Configure the ADC module: BSF TRISA,0 ;Set RA0 to input
• Select ADC conversion clock BANKSEL ANSEL ;
BSF ANSEL,0 ;Set RA0 to analog
• Configure voltage reference BANKSEL WPUA
• Select ADC input channel BCF WPUA,0 ;Disable weak
• Turn on ADC module pull-up on RA0
BANKSEL ADCON0 ;
3. Configure ADC interrupt (optional): MOVLW B’00000001’ ;Select channel AN0
• Clear ADC interrupt flag MOVWF ADCON0 ;Turn ADC On
• Enable ADC interrupt CALL SampleTime ;Acquisiton delay
BSF ADCON0,ADGO ;Start conversion
• Enable peripheral interrupt
BTFSC ADCON0,ADGO ;Is conversion done?
• Enable global interrupt(1) GOTO $-1 ;No, test again
4. Wait the required acquisition time(2). BANKSEL ADRESH ;
5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
6. Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 16.4 “ADC
Acquisition Requirements”.

PIC16(L)F1526/7
16.3 Register Definitions: ADC Control
REGISTER 16-1: ADCON0: ADC CONTROL REGISTER 0

— CHS<4:0> GO/DONE ADON
bit 7 bit 0
Legend:

bit 6-2 CHS<4:0>: Analog Channel Select bits
11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(1)
11110 = Temperature Indicator(2).
11101 = AN29
•
•
•
00110 = AN6
00101 = AN5
00100 = AN4
00011 = AN3
00010 = AN2
00001 = AN1
00000 = AN0
bit 1 GO/DONE: ADC Conversion Status bit
1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.
This bit is automatically cleared by hardware when the ADC conversion has completed.
0 = ADC conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
2: See Section 15.0 “Temperature Indicator Module” for more information.

PIC16(L)F1526/7
REGISTER 16-2: ADCON1: ADC CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
ADFM ADCS<2:0> — — ADPREF<1:0>
bit 7 bit 0
Legend:
bit 7 ADFM: ADC Result Format Select bit

1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits
111 = FRC (clock supplied from a dedicated FRC oscillator)
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC (clock supplied from a dedicated FRC oscillator)
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module(1)
10 = VREF+ is connected to external VREF+ pin(1)
01 = Reserved
00 = VREF+ is connected to VDD
Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a
minimum voltage specification exists. See Section 25.0 “Electrical Specifications” for details.

PIC16(L)F1526/7
REGISTER 16-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

ADRES<9:2>
bit 7 bit 0
Legend:
bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result
REGISTER 16-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

ADRES<1:0> — — — — — —
bit 7 bit 0
Legend:

Lower 2 bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.

PIC16(L)F1526/7
REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

— — — — — — ADRES<9:8>
bit 7 bit 0
Legend:
bit 7-2 Reserved: Do not use.

Upper 2 bits of 10-bit conversion result
REGISTER 16-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

ADRES<7:0>
bit 7 bit 0
Legend:

Lower 8 bits of 10-bit conversion result

PIC16(L)F1526/7
16.4 ADC Acquisition Requirements source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
For the ADC to meet its specified accuracy, the charge selected (or changed), an ADC acquisition must be
holding capacitor (CHOLD) must be allowed to fully done before the conversion can be started. To calculate
charge to the input channel voltage level. The Analog the minimum acquisition time, Equation 16-1 may be
Input model is shown in Figure 16-4. The source used. This equation assumes that 1/2 LSb error is used
impedance (RS) and the internal sampling switch (RSS) (1,024 steps for the ADC). The 1/2 LSb error is the
impedance directly affect the time required to charge maximum error allowed for the ADC to meet its
the capacitor CHOLD. The sampling switch (RSS) specified resolution.
impedance varies over the device voltage (VDD), refer
to Figure 16-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 16-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
V AP P LI ED  1 – -------------------------- = V CHOLD
1
;[1] VCHOLD charged to within 1/2 lsb
 n+1 
2 –1
–TC
 ----------
RC
V AP P LI ED  1 – e  = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
 
– Tc
 ---------
V AP P LI ED  1 – e  = V A PP LIE D  1 – -------------------------- ;combining [1] and [2]
RC 1
  n+1 
2 –1
Note: Where n = number of bits of the ADC.
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 10pF  1k  + 7k  + 10k   ln(0.000488)
= 1.37 µs
Therefore:
T A CQ = 2µs + 1.37µs +   50°C- 25°C   0.05 µs/°C  
= 4.62µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

PIC16(L)F1526/7
FIGURE 16-4: ANALOG INPUT MODEL
VDD
Analog Sampling
Input Switch
VT  0.6V
Rs pin RIC  1k SS Rss
VA CPIN I LEAKAGE(1)
VT  0.6V CHOLD = 10 pF
5 pF
VSS/VREF-
6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage
Note 1: Refer to Section 25.0 “Electrical Specifications”.
FIGURE 16-5: ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
VREF- Zero-Scale
Transition Full-Scale
Transition VREF+

PIC16(L)F1526/7
TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
on Page
ADCON0 — CHS<4:0> GO/DONE ADON 149

ADCON1 ADFM ADCS<2:0> — — ADPREF<1:0> 150
ADRESH ADC Result Register High 151, 152
ADRESL ADC Result Register Low 151, 152
ANSELD — — — — ANSD3 ANSD2 ANSD1 ANSD0 124
ANSELE — — — — — ANSE2 ANSE1 ANSE0 127
ANSELG — — — ANSG4 ANSG3 ANSG2 ANSG1 — 133
CCP1CON — — DC1B<1:0> CCP1M<3:0> 189
CCP2CON — — DC2B<1:0> CCP2M<3:0> 189
CCP3CON — — DC3B<1:0> CCP3M<3:0> 189
CCP4CON — — DC4B<1:0> CCP4M<3:0> 189
CCP5CON — — DC5B<1:0> CCP5M<3:0> 189
CCP6CON — — DC6B<1:0> CCP6M<3:0> 189
CCP7CON — — DC7B<1:0> CCP7M<3:0> 189
CCP8CON — — DC8B<1:0> CCP8M<3:0> 189
CCP9CON — — DC9B<1:0> CCP9M<3:0> 189
CCP10CON — — DC10B<1:0> CCP10M<3:0> 189
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 140
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 126
TRISG — — —(1) TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 132
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.

PIC16(L)F1526/7
17.0 TIMER0 MODULE 17.1.2 8-BIT COUNTER MODE
The Timer0 module is an 8-bit timer/counter with the In 8-Bit Counter mode, the Timer0 module will
following features: increment on either the rising or falling edge of the
T0CKI pin.
• 8-bit timer/counter register (TMR0)
The 8-bit Counter mode using the T0CKI pin is selected
• 8-bit prescaler (independent of Watchdog Timer)
by setting the TMR0CS bit in the OPTION_REG register
• Programmable internal or external clock source to ‘1’.
• Programmable external clock edge selection
The rising or falling transition of the incrementing edge
• Interrupt on overflow for either input source is determined by the TMR0SE bit
• TMR0 can be used to gate Timer1/3/5 in the OPTION_REG register.
Figure 17-1 is a block diagram of the Timer0 module.
17.1 Timer0 Operation

The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
17.1.1 8-BIT TIMER MODE

The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
FIGURE 17-1: BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
8
T0CKI 1
Sync
1 2 TCY TMR0
0
TMR0SE TMR0CS Set Flag bit TMR0IF
8-bit on Overflow
Prescaler PSA
Overflow to Timer1/3/5
PS<2:0>

PIC16(L)F1526/7
17.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note: The Watchdog Timer (WDT) uses its own
independent prescaler.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by
setting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
17.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
17.1.5 8-BIT COUNTER MODE

SYNCHRONIZATION
When in 8-bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 25.0 “Electrical
Specifications”.
17.1.6 OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.

PIC16(L)F1526/7
17.2 Register Definitions: Option Register
REGISTER 17-1: OPTION_REG: OPTION REGISTER

WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
bit 7 bit 0
Legend:
bit 7 WPUEN: Weak Pull-Up Enable bit

1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUA latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate
000 1:2
001 1:4
010 1:8
011 1 : 16
100 1 : 32
101 1 : 64
110 1 : 128
111 1 : 256
TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register
on Page
TMR0 Timer0 Module Register 156*
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.

PIC16(L)F1526/7
18.0 TIMER1/3/5 MODULE WITH • Gate Toggle mode
GATE CONTROL • Gate Single-pulse mode
• Gate Value Status
The Timer1/3/5 module is a 16-bit timer/counter with
• Gate Event Interrupt
the following features:
Figure 18-1 is a block diagram of the Timer1/3/5 module.
• 16-bit timer/counter register pair (TMRxH:TMRxL)
• Programmable internal or external clock source .
• 2-bit prescaler Note: The ‘x’ variable used in this section is
• Dedicated 32 kHz oscillator circuit used to designate Timer1, Timer3 or
• Optionally synchronized comparator out Timer5. For example, TxCON references
T1CON, T3CON or T5CON. PRx
• Multiple Timer1/3/5 gate (count enable) sources
references PR1, PR3 or PR5.
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Auto-conversion Trigger (with CCP)
• Selectable Gate Source Polarity
FIGURE 18-1: TIMER1/3/5 BLOCK DIAGRAM
TxGSS<1:0>
TxG 00 TxGSPM
From Timer0 01 TxG_IN 0

Overflow TxGVAL Data Bus
0 D Q
Timer2/4/6 10 Single Pulse RD
Overflow(4) 1 T1GCON
Acq. Control Q1 EN
D Q 1
Timer10 11 Interrupt
TxGGO/DONE Set
Overflow
TMRxON CK Q
det TMRxGIF
R
TxGPOL TxGTM
TMRxGE
Set flag bit TMRxON
TMRxIF on To Comparator Module
Overflow TMRx(2)
EN Synchronized
0 clock input
TMRxH TMRxL TxCLK
Q D
1
TMRxCS<1:0>
TxSYNC
LFINTOSC 11
Prescaler Synchronize(3)
Secondary Oscillator 1, 2, 4, 8 det
SOSC/TxCKI
10
(See Figure 18-2) 2
FOSC TxCKPS<1:0>
Internal 01
Clock FOSC/2
Internal Sleep input
FOSC/4 Clock
Internal 00
Clock
Note 1: ST Buffer is high-speed type when using TxCKI.

2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: See Table 18-4 for Timer selection.

PIC16(L)F1526/7
FIGURE 18-2: TIMER1/3/5 CLOCK SOURCE DIAGRAM
To Clock Switching (SOSC users)

(1)
TMR1CS<1:0>
0
10
SOSCO/T1CKI OUT 1 LFINTOSC 11
Timer1
Secondary FOSC/4 00
Oscillator
FOSC 01
SOSCI Timer 1
EN
T1CON[SOSCEN]
T3CON[SOSCEN]
T5CON[SOSCEN]
TMR3CS<1:0>
1
(1) 10
T3CKI 0 LFINTOSC 11
Timer3
FOSC/4 00
FOSC 01
Timer 3
TMR5CS<1:0>
1
(1) 10
T5CKI 0 LFINTOSC 11
Timer5
FOSC/4 00
FOSC 01
Timer 5
Note 1: ST Buffer is high-speed type when using TxCKI.

PIC16(L)F1526/7
18.1 Timer1/3/5 Operation 18.2 Clock Source Selection
The Timer1/3/5 module is a 16-bit incrementing counter The TMRxCS<1:0> and SOSCEN bits of the TxCON
which is accessed through the TMRxH:TMRxL register register are used to select the clock source for
pair. Writes to TMRxH or TMRxL directly update the Timer1/3/5. Table 18-2 displays the clock source
counter. selections.
When used with an internal clock source, the module is
18.2.1 INTERNAL CLOCK SOURCE
a timer and increments on every instruction cycle.
When used with an external clock source, the module When the internal clock source is selected, the
can be used as either a timer or counter and incre- TMRxH:TMRxL register pair will increment on multiples
ments on every selected edge of the external source. of FOSC as determined by the Timer1/3/5 prescaler.
Timer1/3/5 is enabled by configuring the TMRxON and When the FOSC internal clock source is selected, the
TMRxGE bits in the TxCON and TxGCON registers, Timer1/3/5 register value will increment by four counts
respectively. Table 18-1 displays the Timer1/3/5 enable every instruction clock cycle. Due to this condition, a
selections. 2 LSB error in resolution will occur when reading the
Timer1/3/5 value. To utilize the full resolution of
Timer1/3/5, an asynchronous input signal must be used
TABLE 18-1: TIMER1/3/5 ENABLE to gate the Timer1/3/5 clock input.
SELECTIONS
The following asynchronous sources may be used:
Timer1/3/5
TMRxON TMRxGE • Asynchronous event on the TxG pin to Timer1/3/5
Operation
gate
0 0 Off
0 1 Off 18.2.2 EXTERNAL CLOCK SOURCE
1 0 Always On When the external clock source is selected, the Tim-
er1/3/5 module may work as a timer or a counter.
1 1 Count Enabled
When enabled to count, Timer1/3/5 is incremented on
the rising edge of the external clock input TxCKI. These
external clock inputs (TxCKI) can be synchronized to the
microcontroller system clock or they can run
asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
•Timer1/3/5 enabled after POR
•Write to TMRxH or TMRxL
•Timer1/3/5 is disabled
•Timer1/3/5 is disabled (TMRxON = 0)
when TxCKI is high then Timer1/3/5
is enabled (TMRxON = 1) when
TxCKI is low.
TABLE 18-2: CLOCK SOURCE SELECTIONS

TMRxCS<1:0> SOSCEN Clock Source
00 x Instruction Clock (FOSC/4)
01 x System Clock (FOSC)
0 External Clocking on TxCKI Pin
10
1 Secondary Oscillator Circuit on SOSCI/SOSCO Pins
11 x LFINTOSC

PIC16(L)F1526/7
18.3 Timer1/3/5 Prescaler 18.5.1 READING AND WRITING
TIMER1/3/5 IN ASYNCHRONOUS
Timer1/3/5 has four prescaler options allowing 1, 2, 4 or
COUNTER MODE
8 divisions of the clock input. The TxCKPS bits of the
TxCON register control the prescale counter. The Reading TMRxH or TMRxL while the timer is running
prescale counter is not directly readable or writable; from an external asynchronous clock will ensure a valid
however, the prescaler counter is cleared upon a write to read (taken care of in hardware). However, the user
TMRxH or TMRxL. should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
18.4 Timer1/3/5 Oscillator timer may overflow between the reads.
For writes, it is recommended that the user simply stop
A dedicated low-power 32.768 kHz oscillator circuit is
the timer and write the desired values. A write
built-in between pins SOSCI (input) and SOSCO
contention may occur by writing to the timer registers,
(amplifier output). This internal circuit is to be used in
while the register is incrementing. This may produce an
conjunction with an external 32.768 kHz crystal.
unpredictable value in the TMRxH:TMRxL register pair.
The oscillator circuit is enabled by setting the SOSCEN
bit of the TxCON register. The oscillator will continue to 18.6 Timer1/3/5 Gate
run during Sleep.
Timer1/3/5 can be configured to count freely or the
Note: The oscillator requires a start-up and count can be enabled and disabled using Timer1/3/5
stabilization time before use. Thus, gate circuitry. This is also referred to as Timer1/3/5
SOSCEN should be set and a suitable Gate Enable.
delay observed prior to enabling
Timer1/3/5. Timer1/3/5 gate can also be driven by multiple select-
able sources.
18.5 Timer1/3/5 Operation in 18.6.1 TIMER1/3/5 GATE ENABLE

Asynchronous Counter Mode The Timer1/3/5 Gate Enable mode is enabled by set-
If control bit TxSYNC of the TxCON register is set, the ting the TMRxGE bit of the TxGCON register. The
external clock input is not synchronized. The timer polarity of the Timer1/3/5 Gate Enable mode is config-
increments asynchronously to the internal phase ured using the TxGPOL bit of the TxGCON register.
clocks. If the external clock source is selected then the When Timer1/3/5 Gate Enable mode is enabled,
timer will continue to run during Sleep and can Timer1/3/5 will increment on the rising edge of the
generate an interrupt on overflow, which will wake-up Timer1/3/5 clock source. When Timer1/3/5 Gate
the processor. However, special precautions in Enable mode is disabled, no incrementing will occur
software are needed to read/write the timer (see and Timer1/3/5 will hold the current count. See
Section 18.5.1 “Reading and Writing Timer1/3/5 in Figure 18-4 for timing details.
Asynchronous Counter Mode”).
Note: When switching from synchronous to TABLE 18-3: TIMER1/3/5 GATE ENABLE
asynchronous operation, it is possible to SELECTIONS
skip an increment. When switching from
asynchronous to synchronous operation, Timer1/3/5
TxCLK TxGPOL TxG
it is possible to produce an additional Operation
increment.  0 0 Counts
 0 1 Holds Count
 1 0 Holds Count
 1 1 Counts

PIC16(L)F1526/7
18.6.2 TIMER1/3/5 GATE SOURCE
SELECTION
The Timer1/3/5 gate source can be selected from one
of four different sources. Source selection is controlled
by the TxGSS bits of the TxGCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the TxGPOL bit of the
TxGCON register.
TABLE 18-4: TIMER1/3/5 GATE SOURCES

T1GSS Timer1 Gate Source Timer3 Gate Source Timer5 Gate Source
00 T1G Pin T3G Pin T5G Pin
01 Overflow of Timer0
(TMR0 increments from FFh to 00h)
10 Timer2 match PR2 Timer4 match PR4 Timer6 match PR6
(TMR2 increments to match PR2)
11 Timer10 match PR10
18.6.2.1 TxG Pin Gate Operation 18.6.4 TIMER1/3/5 GATE SINGLE-PULSE

The TxG pin is one source for Timer1/3/5 gate control. MODE
It can be used to supply an external source to the Tim- When Timer1/3/5 Gate Single-Pulse mode is enabled, it
er1/3/5 gate circuitry. is possible to capture a single-pulse gate event.
Timer1/3/5 Gate Single-Pulse mode is first enabled by
18.6.2.2 Timer0 Overflow Gate Operation setting the TxGSPM bit in the TxGCON register. Next,
When Timer0 increments from FFh to 00h, a the TxGGO/DONE bit in the TxGCON register must be
low-to-high pulse will automatically be generated and set. The Timer1/3/5 will be fully enabled on the next
internally supplied to the Timer1/3/5 gate circuitry. incrementing edge. On the next trailing edge of the pulse,
the TxGGO/DONE bit will automatically be cleared. No
18.6.3 TIMER1/3/5 GATE TOGGLE MODE other gate events will be allowed to increment Timer1/3/5
until the TxGGO/DONE bit is once again set in software.
When Timer1/3/5 Gate Toggle mode is enabled, it is
See Figure 18-6 for timing details.
possible to measure the full-cycle length of a Tim-
er1/3/5 gate signal, as opposed to the duration of a sin- If the Single-Pulse Gate mode is disabled by clearing the
gle level pulse. TxGSPM bit in the TxGCON register, the TxGGO/DONE
bit should also be cleared.
The Timer1/3/5 gate source is routed through a flip-flop
that changes state on every incrementing edge of the Enabling the Toggle mode and the Single-Pulse mode
signal. See Figure 18-5 for timing details. simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1/3/5
Timer1/3/5 Gate Toggle mode is enabled by setting the
gate source to be measured. See Figure 18-7 for timing
TxGTM bit of the TxGCON register. When the TxGTM
details.
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
18.6.5 TIMER1/3/5 GATE VALUE STATUS
measured.
When Timer1/3/5 Gate Value Status is utilized, it is pos-
Note: Enabling Toggle mode at the same time sible to read the most current level of the gate control
as changing the gate polarity may result in value. The value is stored in the TxGVAL bit in the
indeterminate operation. TxGCON register. The TxGVAL bit is valid even when
the Timer1/3/5 gate is not enabled (TMRxGE bit is
cleared).

PIC16(L)F1526/7
18.6.6 TIMER1/3/5 GATE EVENT 18.9 ECCP/CCP Capture/Compare Time
INTERRUPT Base
When Timer1/3/5 Gate Event Interrupt is enabled, it is The CCP module uses the TMRxH:TMRxL register pair
possible to generate an interrupt upon the completion as the time base when operating in Capture or Com-
of a gate event. When the falling edge of TxGVAL pare mode.
occurs, the TMRxGIF flag bit in the PIR1 register will be
set. If the TMRxGIE bit in the PIE1 register is set, then In Capture mode, the value in the TMRxH:TMRxL
an interrupt will be recognized. register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
The TMRxGIF flag bit operates even when the Tim-
er1/3/5 gate is not enabled (TMRxGE bit is cleared). In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMRxH:TMRxL register pair. This event can be a
18.7 Timer1/3/5 Interrupt
Special Event Trigger.
The Timer1/3/5 register pair (TMRxH:TMRxL) For more information, see Section 20.0
increments to FFFFh and rolls over to 0000h. When “Capture/Compare/PWM Modules”.
Timer1/3/5 rolls over, the Timer1/3/5 interrupt flag bit of
the PIR1 register is set. To enable the interrupt on
18.10 ECCP/CCP Special Event Trigger
rollover, you must set these bits:
• TMRxON bit of the TxCON register When the CCP is configured to trigger a special event,
the trigger will clear the TMRxH:TMRxL register pair.
• TMRxIE bit of the PIE1 register
This special event does not cause a Timer1/3/5 inter-
• PEIE bit of the INTCON register rupt. The CCP module may still be configured to gener-
• GIE bit of the INTCON register ate a CCP interrupt.
The interrupt is cleared by clearing the TMRxIF bit in In this mode of operation, the CCPR1H:CCPR1L
the Interrupt Service Routine. register pair becomes the period register for
Note: The TMRxH:TMRxL register pair and the Timer1/3/5.
TMRxIF bit should be cleared before Timer1/3/5 should be synchronized and FOSC/4 should
enabling interrupts. be selected as the clock source in order to utilize the
Special Event Trigger. Asynchronous operation of Tim-
18.8 Timer1/3/5 Operation During Sleep er1/3/5 can cause a Special Event Trigger to be
missed.
Timer1/3/5 can only operate during Sleep when setup In the event that a write to TMRxH or TMRxL coincides
in Asynchronous Counter mode. In this mode, an exter- with a Special Event Trigger from the CCP, the write will
nal crystal or clock source can be used to increment the take precedence.
counter. To set up the timer to wake the device:
For more information, see Section 16.2.5 “Special
• TMRxON bit of the TxCON register must be set Event Trigger”.
• TMRxIE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• TxSYNC bit of the TxCON register must be set
• TMRxCS bits of the TxCON register must be
configured
• SOSCEN bit of the TxCON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Timer1/3/5 oscillator will continue to operate in Sleep
regardless of the TxSYNC bit setting.

PIC16(L)F1526/7
FIGURE 18-3: TIMER1/3/5 INCREMENTING EDGE
TXCKI = 1
when TMR1
Enabled
TXCKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
FIGURE 18-4: TIMER1/3/5 GATE ENABLE MODE
TMRxGE
TxGPOL
txg_in
TxCKI
TxGVAL
Timer1/3/5 N N+1 N+2 N+3 N+4

PIC16(L)F1526/7
FIGURE 18-5: TIMER1/3/5 GATE TOGGLE MODE
TMRxGE
TxGPOL
TxGTM
txg_in
TxCKI
TxGVAL
Timer1/3/5 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8
FIGURE 18-6: TIMER1/3/5 GATE SINGLE-PULSE MODE
TMRxGE
TxGPOL
TxGSPM
Cleared by hardware on
TxGGO/ Set by software falling edge of TxGVAL
DONE
Counting enabled on
rising edge of TxG
txg_in
TxCKI
TxGVAL
Timer1/3/5 N N+1 N+2
Cleared by
TMRxGIF Cleared by software Set by hardware on software
falling edge of TxGVAL

PIC16(L)F1526/7
FIGURE 18-7: TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMRxGE
TxGPOL
TxGSPM
TxGTM
Cleared by hardware on
TxGGO/ Set by software falling edge of TxGVAL
DONE Counting enabled on
rising edge of TxG
txg_in
TxCKI
TxGVAL
Timer1/3/5 N N+1 N+2 N+3 N+4
Set by hardware on Cleared by

TMRxGIF Cleared by software falling edge of TxGVAL software

PIC16(L)F1526/7
18.11 Register Definitions: Timer1/3/5 Control
REGISTER 18-1: TxCON: TIMER1/3/5 CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u
TMRxCS<1:0> TxCKPS<1:0> SOSCEN TxSYNC — TMRxON
bit 7 bit 0
Legend:
bit 7-6 TMRxCS<1:0>: Timer1/3/5 Clock Source Select bits

11 = Timer1/3/5 clock source is LFINTOSC
10 = Timer1/3/5 clock source is pin or oscillator:
If SOSCEN = 0:
External clock from TxCKI pin (on the rising edge)
If SOSCEN = 1:
Crystal oscillator on SOSCI/SOSCO pins
01 = Timer1/3/5 clock source is system clock (FOSC)
00 = Timer1/3/5 clock source is instruction clock (FOSC/4)
bit 5-4 TxCKPS<1:0>: Timer1/3/5 Input Clock Prescale Select bits
11 = 1:8 Prescale value
bit 3 SOSCEN: LP Oscillator Enable Control bit
1 = Dedicated secondary oscillator circuit enabled
0 = Dedicated secondary oscillator circuit disabled
bit 2 TxSYNC: Timer1/3/5 External Clock Input Synchronization Control bit
TMRxCS<1:0> = 1X:
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock (FOSC)
TMRxCS<1:0> = 0X:
bit 0 TMRxON: Timer1/3/5 On bit
1 = Enables Timer1/3/5
0 = Stops Timer1/3/5
Clears Timer1/3/5 gate flip-flop

PIC16(L)F1526/7
18.12 Register Definitions: Timer1/3/5 Gate Control
REGISTER 18-2: TxGCON: TIMER1/3/5 GATE CONTROL REGISTER

R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u
TMRxGE TxGPOL TxGTM TxGSPM TxGGO/ TxGVAL TxGSS<1:0>
DONE
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware
bit 7 TMRxGE: Timer1/3/5 Gate Enable bit

If TMRxON = 0:
This bit is ignored
If TMRxON = 1:
1 = Timer1/3/5 counting is controlled by the Timer1/3/5 gate function
0 = Timer1/3/5 counts regardless of Timer1/3/5 gate function
bit 6 TxGPOL: Timer1/3/5 Gate Polarity bit
1 = Timer1/3/5 gate is active-high (Timer1/3/5 counts when gate is high)
0 = Timer1/3/5 gate is active-low (Timer1/3/5 counts when gate is low)
bit 5 TxGTM: Timer1/3/5 Gate Toggle Mode bit
1 = Timer1/3/5 Gate Toggle mode is enabled
0 = Timer1/3/5 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1/3/5 gate flip-flop toggles on every rising edge.
bit 4 TxGSPM: Timer1/3/5 Gate Single-Pulse Mode bit
1 = Timer1/3/5 Gate Single-Pulse mode is enabled and is controlling Timer1/3/5 gate
0 = Timer1/3/5 Gate Single-Pulse mode is disabled
bit 3 TxGGO/DONE: Timer1/3/5 Gate Single-Pulse Acquisition Status bit
1 = Timer1/3/5 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1/3/5 gate single-pulse acquisition has completed or has not been started
bit 2 TxGVAL: Timer1/3/5 Gate Current State bit
Indicates the current state of the Timer1/3/5 gate that could be provided to TMRxH:TMRxL.
Unaffected by Timer1/3/5 Gate Enable (TMRxGE).
bit 1-0 TxGSS<1:0>: Timer1/3/5 Gate Source Select bits
11 = Timer10 match PR10
10 = Timer2/4/6/8 match PR2/PR4/PR6/PR8(1)
01 = Timer0 overflow output
00 = Timer1/3/5 gate pin
Note 1: See Table 18-4 for Timer selection.

PIC16(L)F1526/7
18.12.1 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function” for
more information.
TABLE 18-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1/3/5

Register
on Page
CCP1CON — — DC1B<1:0> CCP1M<3:0> 189
CCP2CON — — DC2B<1:0> CCP2M<3:0> 189
CCP3CON — — DC3B<1:0> CCP3M<3:0> 189
CCP4CON — — DC4B<1:0> CCP4M<3:0> 189
CCP5CON — — DC5B<1:0> CCP5M<3:0> 189
CCP6CON — — DC6B<1:0> CCP6M<3:0> 189
CCP7CON — — DC7B<1:0> CCP7M<3:0> 189
CCP8CON — — DC8B<1:0> CCP8M<3:0> 189
CCP9CON — — DC9B<1:0> CCP9M<3:0> 189
CCP10CON — — DC10B<1:0> CCP10M<3:0> 189
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 164*
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 164*
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 169
DONE
DONE
DONE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1/3/5 module.

PIC16(L)F1526/7
19.0 TIMER2/4/6/8/10 MODULES
There are up to five identical Timer2-type modules
available. To maintain pre-existing naming conventions,
the Timers are called Timer2, Timer4, Timer6, Timer8
and Timer10 (also Timer2/4/6/8/10).
Note: The ‘x’ variable used in this section is
used to designate Timer2, Timer4,
Timer6, Timer8 or Timer10. For example,
TxCON references T2CON, T4CON,
T6CON, T8CON or T10CON. PRx
references PR2, PR4, PR6, PR8 or PR10.
The Timer2/4/6/8/10 modules incorporate the following
features:
• 8-bit Timer and Period registers (TMR2/4/6/8/10
and PR2/4/6/8/10, respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2/4/6/8/10 match with
PR2/4/6/8/10, respectively
• Optional use as the shift clock for the MSSPx
modules (Timer2 only)
See Figure 19-1 for a block diagram of Tim-
er2/4/6/8/10.
FIGURE 19-1: TIMER2/4/6/8/10 BLOCK DIAGRAM
Prescaler Reset
FOSC/4 TMRx TMRx Output
1:1, 1:4, 1:16, 1:64
2 Postscaler
Comparator Sets Flag bit TMRxIF
EQ 1:1 to 1:16
TxCKPS<1:0>
PRx 4
TxOUTPS<3:0>

PIC16(L)F1526/7
19.1 Timer2/4/6/8/10 Operation 19.3 Timer2/4/6/8/10 Output
The clock input to the Timer2/4/6/8/10 modules is the The unscaled output of TMR2/4/6/8/10 is available pri-
system instruction clock (FOSC/4). marily to the CCP modules, where it is used as a time
TMR2/4/6/8/10 increments from 00h on each clock base for operations in PWM mode.
edge. Timer2 can be optionally used as the shift clock source
A 4-bit counter/prescaler on the clock input allows direct for the MSSPx modules operating in SPI mode.
input, divide-by-4 and divide-by-16 prescale options. Additional information is provided in Section 21.1
These options are selected by the prescaler control bits, “Master SSPx (MSSPx) Module Overview”
TxCKPS<1:0> of the TxCON register. The value of
TMR2/4/6/8/10 is compared to that of the Period 19.4 Timer2/4/6/8/10 Operation During
register, PR2/4/6/8/10, on each clock cycle. When the Sleep
two values match, the comparator generates a match
signal as the timer output. This signal also resets the The Timer2/4/6/8/10 timers cannot be operated while
value of TMR2/4/6/8/10 to 00h on the next cycle and the processor is in Sleep mode. The contents of the
drives the output counter/postscaler (see Section 19.2 TMR2/4/6/8/10 and PR2/4/6/8/10 registers will remain
“Timer2/4/6/8/10 Interrupt”). unchanged while the processor is in Sleep mode.
The TMR2/4/6/8/10 and PR2/4/6/8/10 registers are

both directly readable and writable. The TMR2/4/6/8/10
register is cleared on any device Reset, whereas the
PR2/4/6/8/10 register initializes to FFh. Both the
prescaler and postscaler counters are cleared on the
following events:
• a write to the TMR2/4/6/8/10 register
• a write to the TxCON register
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
Note: TMR2/4/6/8/10 is not cleared when TxCON
is written.
19.2 Timer2/4/6/8/10 Interrupt

Timer2/4/6/8/10 can also generate an optional device
interrupt. The Timer2/4/6/8/10 output signal
(TMRx-to-PRx match) provides the input for the 4-bit
counter/postscaler. This counter generates the TMRx
match interrupt flag which is latched in TMRxIF of the
PIRx register. The interrupt is enabled by setting the
TMR2/4/6/8/10 Match Interrupt Enable bit, TMRxIE of
the PIEx register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, TxOUTPS<3:0>, of the TxCON register.

PIC16(L)F1526/7
19.5 Register Definitions: Timer2/4/6/8/10 Control
REGISTER 19-1: TxCON: TIMER2/TIMER4/TIMER6/TIMER8/TIMER10 CONTROL REGISTER

— TxOUTPS<3:0> TMRxON TxCKPS<1:0>
bit 7 bit 0
Legend:

bit 6-3 TxOUTPS<3:0>: Timerx Output Postscaler Select bits
1111 = 1:16 Postscaler
bit 2 TMRxON: Timerx On bit
1 = Timer2/4/6 is on
0 = Timer2/4/6 is off
bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits
11 = Prescaler is 64
10 = Prescaler is 16
01 = Prescaler is 4
00 = Prescaler is 1

PIC16(L)F1526/7
TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6/8/10
Register
on Page
CCP1CON — — DC1B<1:0> CCP1M<3:0> 189
CCP2CON — — DC2B<1:0> CCP2M<3:0> 189
CCP3CON — — DC3B<1:0> CCP3M<3:0> 189
CCP4CON — — DC4B<1:0> CCP4M<3:0> 189
CCP5CON — — DC5B<1:0> CCP5M<3:0> 189
CCP6CON — — DC6B<1:0> CCP6M<3:0> 189
CCP7CON — — DC7B<1:0> CCP7M<3:0> 189
CCP8CON — — DC8B<1:0> CCP8M<3:0> 189
CCP9CON — — DC9B<1:0> CCP9M<3:0> 189
CCP10CON — — DC10B<1:0> CCP10M<3:0> 189
PR2 Timer2 Module Period Register 213*
T2CON — T2OUTPS<3:0> TMR2ON T2CKPS1 T2CKPS0 215
TMR2 Holding Register for the 8-bit TMR2 Register 213*
TMR4 Holding Register for the 8-bit TMR4 Register(1) 213*
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2/4/6/8/10 module.

PIC16(L)F1526/7
20.0 CAPTURE/COMPARE/PWM
MODULES
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events, and to generate Pulse-Width Modulation
(PWM) signals. In Capture mode, the peripheral allows
the timing of the duration of an event. The Compare
mode allows the user to trigger an external event when
a predetermined amount of time has expired. The
PWM mode can generate Pulse-Width Modulated
signals of varying frequency and duty cycle.
This device contains ten standard
Capture/Compare/PWM modules (CCP1 through
CCP10).
The capture and compare functions are identical for all
CCP modules.
Note 1: In devices with more than one CCP

module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
2: Throughout this section, generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to any CCPx
module. Register names, module
signals, I/O pins, and bit names may use
the generic designator 'x' to indicate the
use of a numeral to distinguish a
particular module, when required.

PIC16(L)F1526/7
20.1 Capture Mode 20.1.2 TIMER1/3/5 MODE RESOURCE
The Capture mode function described in this section is Timer1/3/5 must be running in Timer mode or
available and identical for CCP modules. Synchronized Counter mode for the CCP module to use
the capture feature. In Asynchronous Counter mode, the
Capture mode makes use of the 16-bit Timer1/3/5 capture operation may not work.
resource. When an event occurs on the CCPx pin, the
16-bit CCPRxH:CCPRxL register pair captures and See Section 18.0 “Timer1/3/5 Module with Gate
stores the 16-bit value of the TMRxH:TMRxL register Control” for more information on configuring
pair, respectively. An event is defined as one of the Timer1/3/5.
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register: TABLE 20-1: CCPx CAPTURE TIMER1/3/5
• Every falling edge RESOURCES
• Every rising edge CCP TMR1 TMR3 TMR5
• Every 4th rising edge
CCP1 ● ●
• Every 16th rising edge
CCP2 ● ●
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag CCP3 ● ●
must be cleared in software. If another capture occurs CCP4 ● ●
before the value in the CCPRxH, CCPRxL register pair CCP5 ● ●
is read, the old captured value is overwritten by the new
CCP6 ● ●
captured value.
CCP7 ● ●
Figure 20-1 shows a simplified diagram of the Capture
operation. CCP8 ● ●
CCP9 ● ●
20.1.1 CCP PIN CONFIGURATION CCP10 ● ●
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit. 20.1.3 SOFTWARE INTERRUPT MODE
Also, the CCP2x pin function can be moved to When the Capture mode is changed, a false capture
alternative pins using the APFCON register. Refer to interrupt may be generated. The user should keep the
Section 12.1 “Alternate Pin Function” for more CCPxIE interrupt enable bit of the PIEx register clear to
details. avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
Note: If the CCPx pin is configured as an output, following any change in Operating mode.
a write to the port can cause a capture
condition.
FIGURE 20-1: CAPTURE MODE

OPERATION BLOCK
DIAGRAM
Set Flag bit CCPxIF
(PIRx register)
Prescaler
 1, 4, 16
CCPx CCPRxH CCPRxL
Pin
and Capture
Edge Detect Enable
TMRxH TMRxL
CCPxM<3:0>
System Clock (FOSC)

PIC16(L)F1526/7
20.1.4 CCP PRESCALER 20.1.6 ALTERNATE PIN LOCATIONS
There are four prescaler settings specified by the This module incorporates I/O pins that can be moved to
CCPxM<3:0> bits of the CCPxCON register. Whenever other locations with the use of the alternate pin function
the CCP module is turned off, or the CCP module is not register, APFCON. To determine which pins can be
in Capture mode, the prescaler counter is cleared. Any moved and what their default locations are upon a
Reset will clear the prescaler counter. reset, see Section 12.1 “Alternate Pin Function” for
Switching from one capture prescaler to another does not more information.
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler. Equation 20-1 demonstrates the code to
perform this function.
EXAMPLE 20-1: CHANGING BETWEEN

CAPTURE PRESCALERS
BANKSEL CCPxCON ;Set Bank bits to point
;to CCPxCON
CLRF CCPxCON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;move value and CCP ON
MOVWF CCPxCON ;Load CCPxCON with this
;value
20.1.5 CAPTURE DURING SLEEP

Capture mode depends upon the Timer1/3/5 module for
proper operation. There are two options for driving the
Timer1/3/5 module in Capture mode. It can be driven by
the instruction clock (FOSC/4), or by an external clock
source.
When Timer1/3/5 is clocked by FOSC/4, Timer1/3/5 will
not increment during Sleep. When the device wakes from
Sleep, Timer1/3/5 will continue from its previous state.
Capture mode will operate during Sleep when Tim-
er1/3/5 is clocked by an external clock source.

PIC16(L)F1526/7
TABLE 20-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Register on
Page

CCP1CON — — DC1B<1:0> CCP1M<3:0> 189
CCP2CON — — DC2B<1:0> CCP2M<3:0> 189
CCP3CON — — DC3B<1:0> CCP3M<3:0> 189
CCP4CON — — DC4B<1:0> CCP4M<3:0> 189
CCP5CON — — DC5B<1:0> CCP5M<3:0> 189
CCP6CON — — DC6B<1:0> CCP6M<3:0> 189
CCP7CON — — DC7B<1:0> CCP7M<3:0> 189
CCP8CON — — DC8B<1:0> CCP8M<3:0> 189
CCP9CON — — DC9B<1:0> CCP9M<3:0> 189
CCP10CON — — DC10B<1:0> CCP10M<3:0> 189
CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) 176*
CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) 176*
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 169
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.

PIC16(L)F1526/7
TABLE 20-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE (CONTINUED)
Register on
Page

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.

PIC16(L)F1526/7
20.2 Compare Mode 20.2.1 CCP PIN CONFIGURATION
The Compare mode function described in this section The user must configure the CCPx pin as an output by
is available and identical for CCP modules. clearing the associated TRIS bit.
Compare mode makes use of the 16-bit Timer1/3/5 Also, the CCPx pin function can be moved to
resource. The 16-bit value of the CCPRxH:CCPRxL alternative pins using the APFCON register. Refer to
register pair is constantly compared against the 16-bit Section 12.1 “Alternate Pin Function” for more
value of the TMRxH:TMRxL register pair. When a details.
match occurs, one of the following events can occur: Note: Clearing the CCPxCON register will force
• Toggle the CCPx output the CCPx compare output latch to the
• Set the CCPx output default low level. This is not the PORT I/O
data latch.
• Clear the CCPx output
• Generate a Special Event Trigger 20.2.2 TIMER1/3/5 MODE RESOURCE
• Generate a Software Interrupt
In Compare mode, Timer1/3/5 must be running in either
The action on the pin is based on the value of the Timer mode or Synchronized Counter mode. The
CCPxM<3:0> control bits of the CCPxCON register. At compare operation may not work in Asynchronous
the same time, the interrupt flag CCPxIF bit is set. Counter mode.
All Compare modes can generate an interrupt.
Figure 20-2 shows a simplified diagram of the TABLE 20-3: CCPx COMPARE TIMER1/3/5
Compare operation. RESOURCES
CCP TMR1 TMR3 TMR5
FIGURE 20-2: COMPARE MODE
OPERATION BLOCK CCP1 ● ●
DIAGRAM CCP2 ● ●
CCPxM<3:0>
CCP3 ● ●
Mode Select CCP4 ● ●
CCP5 ● ●
Set CCPxIF Interrupt Flag
4
(PIRx) CCP6 ● ●
CCPx
Pin CCPRxH CCPRxL CCP7 ● ●
Q S
Output CCP8 ● ●
Comparator
Logic Match
R CCP9 ● ●
TMRxH TMRxL CCP10 ● ●
TRIS
Output Enable See Section 18.0 “Timer1/3/5 Module with Gate
Special Event Trigger Control” for more information on configuring
Timer1/3/5.
Note: Clocking Timer1/3/5 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, Timer1/3/5 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.

PIC16(L)F1526/7
20.2.3 SOFTWARE INTERRUPT MODE 20.2.5 COMPARE DURING SLEEP
When Generate Software Interrupt mode is chosen The Compare mode is dependent upon the system
(CCPxM<3:0> = 1010), the CCPx module does not clock (FOSC) for proper operation. Since FOSC is shut
assert control of the CCPx pin (see the CCPxCON down during Sleep mode, the Compare mode will not
register). function properly during Sleep.
20.2.4 SPECIAL EVENT TRIGGER 20.2.6 ALTERNATE PIN LOCATIONS

When Special Event Trigger mode is chosen This module incorporates I/O pins that can be moved to
(CCPxM<3:0> = 1011), the CCPx module does the other locations with the use of the alternate pin function
following: register, APFCON. To determine which pins can be
• Resets Timer1/3/5 moved and what their default locations are upon a
reset, see Section 12.1 “Alternate Pin Function” for
• Starts an ADC conversion if ADC is enabled
more information.
The CCPx module does not assert control of the CCPx
pin in this mode.
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMRxH,
TMRxL register pair and the CCPRxH, CCPRxL regis-
ter pair. The TMRxH, TMRxL register pair is not reset
until the next rising edge of the Timer1/3/5 clock. The
Special Event Trigger output starts an ADC conversion
(if the ADC module is enabled). This allows the
CCPRxH, CCPRxL register pair to effectively provide a
16-bit programmable period register for Timer1/3/5.
TABLE 20-4: SPECIAL EVENT TRIGGER
Device CCPx
PIC16(L)F1526/7 CCP10
Refer to Section 16.2.5 “Special Event Trigger” for
more information.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMRxIF of the PIRx register.
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1/3/5 Reset, will
preclude the Reset from occurring.

PIC16(L)F1526/7
TABLE 20-5: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Register on
Page

CCP1CON — — DC1B<1:0> CCP1M<3:0> 189
CCP2CON — — DC2B<1:0> CCP2M<3:0> 189
CCP3CON — — DC3B<1:0> CCP3M<3:0> 189
CCP4CON — — DC4B<1:0> CCP4M<3:0> 189
CCP5CON — — DC5B<1:0> CCP5M<3:0> 189
CCP6CON — — DC6B<1:0> CCP6M<3:0> 189
CCP7CON — — DC7B<1:0> CCP7M<3:0> 189
CCP8CON — — DC8B<1:0> CCP8M<3:0> 189
CCP9CON — — DC9B<1:0> CCP9M<3:0> 189
CCP10CON — — DC10B<1:0> CCP10M<3:0> 189
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.

PIC16(L)F1526/7
TABLE 20-5: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE (CONTINUED)
Register on
Page

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.

PIC16(L)F1526/7
20.3 PWM Overview FIGURE 20-3: CCP PWM OUTPUT SIGNAL
Pulse-Width Modulation (PWM) is a scheme that Period
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles Pulse Width
TMRx = PRx
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal TMRx = CCPRxH:CCPxCON<5:4>
is considered the off state. The high portion, also known
TMRx = 0
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
FIGURE 20-4: SIMPLIFIED PWM BLOCK
shortens the pulse width, supplies less power. The DIAGRAM
PWM period is defined as the duration of one complete CCPxCON<5:4>
cycle or the total amount of on and off time combined. Duty Cycle Registers
PWM resolution defines the maximum number of steps CCPRxL

that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load. CCPRxH(2) (Slave)
CCPx
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages, Comparator R Q
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher (1) S
TMRx
duty cycle corresponds to more power applied. TRIS
Figure 20-3 shows a typical waveform of the PWM
signal. Comparator
Clear Timer,
toggle CCPx pin and
20.3.1 STANDARD PWM OPERATION PRx
latch duty cycle
The standard PWM function described in this section is

Note 1: The 8-bit timer TMRx register is concatenated
available and identical for CCP modules.
with the 2-bit internal system clock (FOSC), or
The standard PWM mode generates a Pulse-Width 2 bits of the prescaler, to create the 10-bit time
Modulation (PWM) signal on the CCPx pin with up to 10 base.
bits of resolution. The period, duty cycle, and resolution 2: In PWM mode, CCPRxH is a read-only register.
are controlled by the following registers:
• PRx registers
• TxCON registers TABLE 20-6: CCPx PWM TIMER2/4/6/8/10
• CCPRxL registers RESOURCES
• CCPxCON registers CCP TMR2 TMR4 TMR6 TMR8 TMR10
Figure 20-4 shows a simplified block diagram of PWM CCP1 ● ● ●
operation.
CCP2 ● ● ●
CCP3 ● ● ●
Note 1: The corresponding TRIS bit must be CCP4 ● ● ●
cleared to enable the PWM output on the
CCP5 ● ● ●
CCPx pin.
CCP6 ● ● ●
2: Clearing the CCPxCON register will
relinquish control of the CCPx pin. CCP7 ● ● ●
CCP8 ● ● ●
CCP9 ● ● ●
CCP10 ● ● ●

PIC16(L)F1526/7
20.3.2 SETUP FOR PWM OPERATION 20.3.4 PWM PERIOD
The following steps should be taken when configuring The PWM period is specified by the PRx register of
the CCP module for standard PWM operation: Timer2/4/6/8/10. The PWM period can be calculated
1. Disable the CCPx pin output driver by setting the using the formula of Equation 20-1.
associated TRIS bit.
2. Load the PRx register with the PWM period EQUATION 20-1: PWM PERIOD
value.
PWM Period =   PRx  + 1   4  T OSC 
3. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the (TMRx Prescale Value)
appropriate values.
Note 1: TOSC = 1/FOSC
4. Load the CCPRxL register and the DCxBx bits
of the CCPxCON register, with the PWM duty
When TMRx is equal to PRx, the following three events
cycle value.
occur on the next increment cycle:
5. Configure and start Timer2/4/6/8/10:
• TMRx is cleared
• Select the Timer2/4/6/8/10 resource to be
used for PWM generation by setting the • The CCPx pin is set. (Exception: If the PWM duty
CxTSEL<1:0> bits in the CCPTMRSx cycle = 0%, the pin will not be set.)
register. • The PWM duty cycle is latched from CCPRxL into
• Clear the TMRxIF interrupt flag bit of the CCPRxH.
PIRx register. See Note below.
• Configure the TxCKPS bits of the TxCON Note: The Timer postscaler (see Section 19.1
register with the Timer prescale value. “Timer2/4/6/8/10 Operation” is not used
in the determination of the PWM
• Enable the Timer by setting the TMRxON
frequency.
bit of the TxCON register.
6. Enable PWM output pin:
• Wait until the Timer overflows and the
TMRxIF bit of the PIRx register is set. See
Note below.
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.
Note: In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
20.3.3 TIMER2/4/6/8/10 TIMER RESOURCE

The PWM standard mode makes use of one of the 8-bit
Timer2/4/6/8/10 timer resources to specify the PWM
period.
Configuring the CxTSEL<1:0> bits in the CCPTMRSx
register selects which Timer2/4/6/8/10 timer is used.
See Table 20-6 for CCPx PWM Timer2/4/6/8/10
resources.

PIC16(L)F1526/7
20.3.5 PWM DUTY CYCLE The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
The PWM duty cycle is specified by writing a 10-bit
buffering is essential for glitchless PWM operation.
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The The 8-bit timer TMRx register is concatenated with either
CCPRxL contains the eight MSbs and the DCxB<1:0> the 2-bit internal system clock (FOSC), or 2 bits of the
bits of the CCPxCON register contain the two LSbs. prescaler, to create the 10-bit time base. The system
CCPRxL and DCxB<1:0> bits of the CCPxCON clock is used if the Timer2/4/6/8/10 prescaler is set to
register can be written to at any time. The duty cycle 1:1.
value is not latched into CCPRxH until after the period When the 10-bit time base matches the CCPRxH and
completes (i.e., a match between PRx and TMRx 2-bit latch, then the CCPx pin is cleared (see
registers occurs). While using the PWM, the CCPRxH Figure 20-4).
register is read-only.
Equation 20-2 is used to calculate the PWM pulse 20.3.6 PWM RESOLUTION
width. The resolution determines the number of available duty
Equation 20-3 is used to calculate the PWM duty cycle cycles for a given period. For example, a 10-bit resolution
ratio. will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
EQUATION 20-2: PULSE WIDTH The maximum PWM resolution is 10 bits when PRx is
255. The resolution is a function of the PRx register
Pulse Width =  CCPRxL:CCPxCON<5:4>   value as shown by Equation 20-4.
T OSC  (TMRx Prescale Value)

EQUATION 20-4: PWM RESOLUTION
log  4  PRx + 1  
EQUATION 20-3: DUTY CYCLE RATIO Resolution = ------------------------------------------ bits
log  2 
 CCPRxL:CCPxCON<5:4> 
Duty Cycle Ratio = -----------------------------------------------------------------------
4  PRx + 1 
Note: If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 20-7: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PRx Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6
TABLE 20-8: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PRx Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5

PIC16(L)F1526/7
20.3.7 OPERATION IN SLEEP MODE 20.3.9 EFFECTS OF RESET
In Sleep mode, the TMRx register will not increment Any Reset will force all ports to Input mode and the
and the state of the module will not change. If the CCPx CCP registers to their Reset states.
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its 20.3.10 ALTERNATE PIN LOCATIONS
previous state. This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
20.3.8 CHANGES IN SYSTEM CLOCK register, APFCON. To determine which pins can be
FREQUENCY moved and what their default locations are upon a
The PWM frequency is derived from the system clock reset, see Section 12.1 “Alternate Pin Function” for
frequency. Any changes in the system clock frequency more information.
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (with Fail-Safe
Clock Monitor)” for additional details.
TABLE 20-9: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM

Register
on Page
CCP1CON — — DC1B<1:0> CCP1M<3:0> 189
CCP2CON — — DC2B<1:0> CCP2M<3:0> 189
CCP3CON — — DC3B<1:0> CCP3M<3:0> 189
CCP4CON — — DC4B<1:0> CCP4M<3:0> 189
CCP5CON — — DC5B<1:0> CCP5M<3:0> 189
CCP6CON — — DC6B<1:0> CCP6M<3:0> 189
CCP7CON — — DC7B<1:0> CCP7M<3:0> 189
CCP8CON — — DC8B<1:0> CCP8M<3:0> 189
CCP9CON — — DC9B<1:0> CCP9M<3:0> 189
CCP10CON — — DC10B<1:0> CCP10M<3:0> 189
PR2 Timer2 Period Register 171*
T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<:0>1 168
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.

PIC16(L)F1526/7
TABLE 20-10: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM (CONTINUED)
Register
on Page
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.

PIC16(L)F1526/7
20.4 Register Definitions: ECCP Control
REGISTER 20-1: CCPxCON: CCPx CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — DCxB<1:0> CCPxM<3:0>
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM<3:0>: CCPx Mode Select bits
11xx = PWM mode
1011 = Compare mode: Special Event Trigger (sets CCP10IF bit (CCP10), starts ADC conversion if ADC module
is enabled)(1)
1010 = Compare mode: generate software interrupt only
1001 = Compare mode: clear output on compare match (set CCPxIF)
1000 = Compare mode: set output on compare match (set CCPxIF)
0111 = Capture mode: every 16th rising edge

0110 = Capture mode: every 4th rising edge
0101 = Capture mode: every rising edge
0100 = Capture mode: every falling edge
0011 = Reserved
0010 = Compare mode: toggle output on match
0001 = Reserved
0000 = Capture/Compare/PWM off (resets CCPx module)

PIC16(L)F1526/7
REGISTER 20-2: CCPTMRS0: CCP TIMER SELECTION CONTROL REGISTER 0

C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0>
bit 7 bit 0
Legend:
bit 7-6 C4TSEL<1:0>: CCP4 Timer Selection bits

When in Capture/Compare mode:
x1 = CCP4 is based off Timer3 in Capture/Compare mode
When in PWM mode:
11 = Reserved
10 = CCP4 is based off Timer6 in PWM mode
When in PWM mode:
11 = Reserved
When in PWM mode:
11 = Reserved
When in PWM mode:
11 = Reserved

PIC16(L)F1526/7

C8TSEL<1:0> C7TSEL<1:0> C6TSEL<1:0> C5TSEL<1:0>
bit 7 bit 0
Legend:

When in PWM mode:
11 = Reserved
When in PWM mode:
11 = Reserved
When in PWM mode:
11 = Reserved
When in PWM mode:
11 = Reserved

PIC16(L)F1526/7

U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — C10TSEL<1:0> C9TSEL<1:0>
bit 7 bit 0
Legend:

When in PWM mode:
11 = Reserved
When in PWM mode:
11 = Reserved

PIC16(L)F1526/7
21.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP1 AND
MSSP2) MODULE
21.1 Master SSPx (MSSPx) Module
Overview
The Master Synchronous Serial Port (MSSPx) module
is a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSPx
module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy-chain connection of slave devices
Figure 21-1 is a block diagram of the SPI interface
module.
FIGURE 21-1: MSSPX BLOCK DIAGRAM (SPI MODE)
Data Bus
Read Write
SSPxBUF Reg
SDIx
SDO_out
SSPxSR Reg
SDOx bit 0 Shift
Clock
SSx SSx Control 2 (CKP, CKE)

Enable Clock Select
Edge
Select SCK_out
SSPM<3:0>
4
( TMR22Output )
SCKx
Edge Prescaler TOSC
Select 4, 16, 64
Baud Rate
Generator
TRIS bit (SSPxADD)

PIC16(L)F1526/7
The I2C interface supports the following modes and The PIC16F1527 has two MSSP modules, MSSP1 and
features: MSSP2, each module operating independently from
• Master mode the other.
• Slave mode
• Byte NACKing (Slave mode) Note 1: In devices with more than one MSSP
• Limited Multi-master support module, it is very important to pay close
• 7-bit and 10-bit addressing attention to SSPxCONx register names.
• Start and Stop interrupts SSP1CON1 and SSP1CON2 registers
control different operational aspects of
• Interrupt masking
the same module, while SSP1CON1 and
• Clock stretching SSP2CON1 control the same features for
• Bus collision detection two different modules.
• General call address matching 2: Throughout this section, generic refer-
• Address masking ences to an MSSP module in any of its
• Address Hold and Data Hold modes operating modes may be interpreted as
• Selectable SDAx hold times being equally applicable to MSSP1 or
MSSP2. Register names, module I/O sig-
Figure 21-2 is a block diagram of the I2C Interface nals, and bit names may use the generic
module in Master mode. Figure 21-3 is a diagram of the designator ‘x’ to indicate the use of a
I2C interface module in Slave mode. numeral to distinguish a particular module
when required.
FIGURE 21-2: MSSPX BLOCK DIAGRAM (I2C MASTER MODE)
Internal
data bus [SSPM 3:0]
Read Write
SSPxBUF Baud rate

generator
(SSPxADD)
SDAx Shift
SDAx in Clock
Clock arbitrate/BCOL detect
SSPxSR
Clock Cntl
(Hold off clock source)
MSb LSb
Receive Enable (RCEN)
Start bit, Stop bit,

Acknowledge
Generate (SSPxCON2)
SCLx
Start bit detect,

Stop bit detect
SCLx in Write collision detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV
Clock arbitration Reset SEN, PEN (SSPxCON2)
Bus Collision State counter for Set SSPxIF, BCLxIF
end of XMIT/RCV
Address Match detect

PIC16(L)F1526/7
FIGURE 21-3: MSSPX BLOCK DIAGRAM (I2C SLAVE MODE)
Internal
Data Bus
Read Write
SCLx SSPxBUF Reg
Shift
Clock
SSPxSR Reg
SDAx MSb LSb
SSPxMSK Reg
Match Detect Addr Match
SSPxADD Reg
Start and Set, Reset

Stop bit Detect S, P bits
(SSPxSTAT Reg)

PIC16(L)F1526/7
21.2 SPI Mode Overview its SDOx pin) and the slave device is reading this bit
and saving it as the LSb of its shift register, that the
The Serial Peripheral Interface (SPI) bus is a slave device is also sending out the MSb from its shift
synchronous serial data communication bus that register (on its SDOx pin) and the master device is
operates in Full-Duplex mode. Devices communicate reading this bit and saving it as the LSb of its shift
in a master/slave environment where the master device register.
initiates the communication. A slave device is
controlled through a chip select known as Slave Select. After 8 bits have been shifted out, the master and slave
have exchanged register values.
The SPI bus specifies four signal connections:
If there is more data to exchange, the shift registers are
• Serial Clock (SCKx) loaded with new data and the process repeats itself.
• Serial Data Out (SDOx)
Whether the data is meaningful or not (dummy data),
• Serial Data In (SDIx) depends on the application software. This leads to
• Slave Select (SSx) three scenarios for data transmission:
Figure 21-1 shows the block diagram of the MSSPx • Master sends useful data and slave sends dummy
module when operating in SPI mode. data.
The SPI bus operates with a single master device and • Master sends useful data and slave sends useful
one or more slave devices. When multiple slave data.
devices are used, an independent Slave Select con- • Master sends dummy data and slave sends useful
nection is required from the master device to each data.
slave device.
Transmissions may involve any number of clock
Figure 21-4 shows a typical connection between a cycles. When there is no more data to be transmitted,
master device and multiple slave devices. the master stops sending the clock signal and it
The master selects only one slave at a time. Most slave deselects the slave.
devices have tri-state outputs so their output signal Every slave device connected to the bus that has not
appears disconnected from the bus when they are not been selected through its slave select line must disre-
selected. gard the clock and transmission signals and must not
Transmissions involve two shift registers, eight bits in transmit out any data of its own.
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 21-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the
programmed clock edge and latched on the opposite
edge of the clock.
The master device transmits information out on its
SDOx output pin which is connected to, and received
by, the slave’s SDIx input pin. The slave device
transmits information out on its SDOx output pin, which
is connected to, and received by, the master’s SDIx
input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock
polarity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on

PIC16(L)F1526/7
FIGURE 21-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION
SCKx SCKx
SPI Master
SDOx SDIx SPI Slave
SDIx SDOx #1
General I/O SSx
General I/O
General I/O SCKx
SDIx SPI Slave
SDOx #2
SSx
SCKx
SDIx SPI Slave
SDOx #3
SSx
21.2.1 SPI MODE REGISTERS

The MSSPx module has five registers for SPI mode
operation. These are:
• MSSPx STATUS register (SSPxSTAT)
• MSSPx Control Register 1 (SSPxCON1)
• MSSPx Control Register 3 (SSPxCON3)
• MSSPx Data Buffer register (SSPxBUF)
• MSSPx Address register (SSPxADD)
• MSSPx Shift register (SSPxSR)
(Not directly accessible)
SSPxCON1 and SSPxSTAT are the control and
STATUS registers in SPI mode operation. The SSPx-
CON1 register is readable and writable. The lower 6
bits of the SSPxSTAT are read-only. The upper two
bits of the SSPxSTAT are read/write.
In one SPI master mode, SSPxADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 21.7 “Baud Rate Generator”.
SSPxSR is the shift register used for shifting data in
and out. SSPxBUF provides indirect access to the
SSPxSR register. SSPxBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSPxSR and SSPxBUF
together create a buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPxSR.

PIC16(L)F1526/7
21.2.2 SPI MODE OPERATION Any serial port function that is not desired may be
overridden by programming the corresponding data
When initializing the SPI, several options need to be direction (TRIS) register to the opposite value.
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). The MSSPx consists of a transmit/receive shift register
These control bits allow the following to be specified: (SSPxSR) and a buffer register (SSPxBUF). The
SSPxSR shifts the data in and out of the device, MSb
• Master mode (SCKx is the clock output) first. The SSPxBUF holds the data that was written to
• Slave mode (SCKx is the clock input) the SSPxSR until the received data is ready. Once the
• Clock Polarity (Idle state of SCKx) 8 bits of data have been received, that byte is moved to
• Data Input Sample Phase (middle or end of data the SSPxBUF register. Then, the Buffer Full Detect bit,
output time) BF of the SSPxSTAT register, and the interrupt flag bit,
• Clock Edge (output data on rising/falling edge of SSPxIF, are set. This double-buffering of the received
SCKx) data (SSPxBUF) allows the next byte to start reception
before reading the data that was just received. Any
• Clock Rate (Master mode only)
write to the SSPxBUF register during
• Slave Select mode (Slave mode only) transmission/reception of data will be ignored and the
To enable the serial port, SSPx Enable bit, SSPEN of write collision detect bit WCOL of the SSPxCON1
the SSPxCON1 register, must be set. To reset or recon- register, will be set. User software must clear the
figure SPI mode, clear the SSPEN bit, re-initialize the WCOL bit to allow the following write(s) to the
SSPxCONx registers and then set the SSPEN bit. This SSPxBUF register to complete successfully.
configures the SDIx, SDOx, SCKx and SSx pins as When the application software is expecting to receive
serial port pins. For the pins to behave as the serial port valid data, the SSPxBUF should be read before the
function, some must have their data direction bits (in next byte of data to transfer is written to the SSPxBUF.
the TRIS register) appropriately programmed as The Buffer Full bit, BF of the SSPxSTAT register,
follows: indicates when SSPxBUF has been loaded with the
• SDIx must have corresponding TRIS bit set received data (transmission is complete). When the
• SDOx must have corresponding TRIS bit cleared SSPxBUF is read, the BF bit is cleared. This data may
be irrelevant if the SPI is only a transmitter. Generally,
• SCKx (Master mode) must have corresponding
the MSSPx interrupt is used to determine when the
TRIS bit cleared
transmission/reception has completed. If the interrupt
• SCKx (Slave mode) must have corresponding method is not going to be used, then software polling
TRIS bit set can be done to ensure that a write collision does not
• SSx must have corresponding TRIS bit set occur.
FIGURE 21-5: SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx SPI Slave SSPM<3:0> = 010x

= 1010
SDOx SDIx
Serial Input Buffer Serial Input Buffer

(BUF) (SSPxBUF)
Shift Register SDIx SDOx Shift Register

(SSPxSR) (SSPxSR)
MSb LSb MSb LSb
Serial Clock
SCKx SCKx
Slave Select
General I/O SSx
Processor 1 (optional) Processor 2

PIC16(L)F1526/7
21.2.3 SPI MASTER MODE The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
The master can initiate the data transfer at any time
and the CKE bit of the SSPxSTAT register. This then,
because it controls the SCKx line. The master
would give waveforms for SPI communication as
determines when the slave (Processor 2, Figure 21-5)
shown in Figure 21-6, Figure 21-8, Figure 21-9 and
is to broadcast data by the software protocol.
Figure 21-10, where the MSb is transmitted first. In
In Master mode, the data is transmitted/received as Master mode, the SPI clock rate (bit rate) is user
soon as the SSPxBUF register is written to. If the SPI programmable to be one of the following:
is only going to receive, the SDOx output could be dis-
• FOSC/4 (or TCY)
abled (programmed as an input). The SSPxSR register
will continue to shift in the signal present on the SDIx • FOSC/16 (or 4 * TCY)
pin at the programmed clock rate. As each byte is • FOSC/64 (or 16 * TCY)
received, it will be loaded into the SSPxBUF register as • Timer2 output/2
if a normal received byte (interrupts and Status bits • Fosc/(4 * (SSPxADD + 1))
appropriately set).
Figure 21-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDOx data is valid before
there is a clock edge on SCKx. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
FIGURE 21-6: SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPxBUF
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
4 Clock
SCKx Modes
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)
SDIx
(SMP = 0) bit 7 bit 0
Input
Sample
(SMP = 0)
SDIx
(SMP = 1) bit 0
bit 7
Input
Sample
(SMP = 1)
SSPxIF
SSPxSR to
SSPxBUF

PIC16(L)F1526/7
21.2.4 SPI SLAVE MODE 21.2.5 SLAVE SELECT
In Slave mode, the data is transmitted and received as SYNCHRONIZATION
external clock pulses appear on SCKx. When the last The Slave Select can also be used to synchronize
bit is latched, the SSPxIF interrupt flag bit is set. communication. The Slave Select line is held high until
Before enabling the module in SPI Slave mode, the clock the master device is ready to communicate. When the
line must match the proper Idle state. The clock line can Slave Select line is pulled low, the slave knows that a
be observed by reading the SCKx pin. The Idle state is new transmission is starting.
determined by the CKP bit of the SSPxCON1 register. If the slave fails to receive the communication properly,
While in Slave mode, the external clock is supplied by it will be reset at the end of the transmission, when the
the external clock source on the SCKx pin. This exter- Slave Select line returns to a high state. The slave is
nal clock must meet the minimum high and low times then ready to receive a new transmission when the
as specified in the electrical specifications. Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will
While in Sleep mode, the slave can transmit/receive
eventually become out of sync with the master. If the
data. The shift register is clocked from the SCKx pin
slave misses a bit, it will always be one bit off in future
input and when a byte is received, the device will
transmissions. Use of the Slave Select line allows the
generate an interrupt. If enabled, the device will
slave and master to align themselves at the beginning
wake-up from Sleep.
of each transmission.
21.2.4.1 Daisy-Chain Configuration The SSx pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SSx pin control
The SPI bus can sometimes be connected in a
enabled (SSPxCON1<3:0> = 0100).
daisy-chain configuration. The first slave output is con-
nected to the second slave input, the second slave When the SSx pin is low, transmission and reception
output is connected to the third slave input, and so on. are enabled and the SDOx pin is driven.
The final slave output is connected to the master input. When the SSx pin goes high, the SDOx pin is no longer
Each slave sends out, during a second group of clock driven, even if in the middle of a transmitted byte and
pulses, an exact copy of what was received during the becomes a floating output. External pull-up/pull-down
first group of clock pulses. The whole chain acts as resistors may be desirable depending on the applica-
one large communication shift register. The tion.
daisy-chain feature only requires a single Slave Select
line from the master device. Note 1: When the SPI is in Slave mode with SSx
pin control enabled (SSPxCON1<3:0> =
Figure 21-7 shows the block diagram of a typical
0100), the SPI module will reset if the SSx
daisy-chain connection when operating in SPI mode.
pin is set to VDD.
In a daisy-chain configuration, only the most recent
2: When the SPI is used in Slave mode with
byte on the bus is required by the slave. Setting the
CKE set; the user must enable SSx pin
BOEN bit of the SSPxCON3 register will enable writes
control.
to the SSPxBUF register, even if the previous byte has
not been read. This allows the software to ignore data 3: While operated in SPI Slave mode the
that may not apply to it. SMP bit of the SSPxSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SSx pin to
a high level or clearing the SSPEN bit.

PIC16(L)F1526/7
FIGURE 21-7: SPI DAISY-CHAIN CONNECTION
SCK SCK
SPI Master
SDOx SDIx SPI Slave
SDIx SDOx #1
General I/O SSx
SCK
SDIx SPI Slave
SDOx #2
SSx
SCK
SDIx SPI Slave
SDOx #3
SSx
FIGURE 21-8: SLAVE SELECT SYNCHRONOUS WAVEFORM
SSx
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPxSR
and bit count are reset
SSPxBUF to
SSPxSR
SDOx bit 7 bit 6 bit 7 bit 6 bit 0
SDIx bit 0
bit 7 bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF

PIC16(L)F1526/7
FIGURE 21-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SSx
Optional
SCKx
(CKP = 0
CKE = 0)
SCKx
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDIx
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active
FIGURE 21-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SSx
Not Optional
SCKx
(CKP = 0
CKE = 1)
SCKx
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDIx
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPxSR to
SSPxBUF
Write Collision
detection active

PIC16(L)F1526/7
21.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the
In SPI Master mode, module clocks may be operating transmission/reception will remain in that state until the
at a different speed than when in Full-Power mode; in device wakes. After the device returns to Run mode,
the case of the Sleep mode, all clocks are halted. the module will resume transmitting and receiving data.
Special care must be taken by the user when the In SPI Slave mode, the SPI Transmit/Receive Shift
MSSPx clock is much faster than the system clock. register operates asynchronously to the device. This
In Slave mode, when MSSPx interrupts are enabled, allows the device to be placed in Sleep mode and data
after the master completes sending data, an MSSPx to be shifted into the SPI Transmit/Receive Shift
interrupt will wake the controller from Sleep. register. When all 8 bits have been received, the
If an exit from Sleep mode is not desired, MSSPx MSSPx interrupt flag bit will be set and if enabled, will
interrupts should be disabled. wake the device.
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Register
on Page
SSP1BUF MSSPx Receive Buffer/Transmit Register 197*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 244
SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 246
SSP1STAT SMP CKE D/A P S R/W UA BF 242
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.

PIC16(L)F1526/7
21.3 I2C MODE OVERVIEW FIGURE 21-11: I2C MASTER/
SLAVE CONNECTION
The Inter-Integrated Circuit Bus (I2C) is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master VDD
devices initiate the communication. A slave device is
controlled through addressing. SCLx SCLx
The I2C bus specifies two signal connections:
VDD
• Serial Clock (SCLx) Master Slave
• Serial Data (SDAx)
SDAx SDAx
Figure 21-2 and Figure 21-3 shows the block diagram
of the MSSPx module when operating in I2C mode.
Both the SCLx and SDAx connections are bidirectional
open-drain lines, each requiring pull-up resistors for the The Acknowledge bit (ACK) is an active-low signal,
supply voltage. Pulling the line to ground is considered which holds the SDAx line low to indicate to the trans-
a logical zero and letting the line float is considered a mitter that the slave device has received the transmit-
logical one. ted data and is ready to receive more.
Figure 21-11 shows a typical connection between two The transition of a data bit is always performed while
processors configured as master and slave devices. the SCLx line is held low. Transitions that occur while
The I2C bus can operate with one or more master the SCLx line is held high are used to indicate Start and
devices and one or more slave devices. Stop bits.
There are four potential modes of operation for a given If the master intends to write to the slave, then it repeat-
device: edly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
• Master Transmit mode
master device is in Master Transmit mode and the
(master is transmitting data to a slave)
slave is in Slave Receive mode.
• Master Receive mode
(master is receiving data from a slave) If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
• Slave Transmit mode
responds after each byte with an ACK bit. In this exam-
(slave is transmitting data to a master)
ple, the master device is in Master Receive mode and
• Slave Receive mode the slave is Slave Transmit mode.
(slave is receiving data from the master)
On the last byte of data communicated, the master
To begin communication, a master device starts out in device may end the transmission by sending a Stop bit.
Master Transmit mode. The master device sends out a If the master device is in Receive mode, it sends the
Start bit followed by the address byte of the slave it Stop bit in place of the last ACK bit. A Stop bit is indi-
intends to communicate with. This is followed by a sin- cated by a low-to-high transition of the SDAx line while
gle Read/Write bit, which determines whether the mas- the SCLx line is held high.
ter intends to transmit to or receive data from the slave
device. In some cases, the master may want to maintain con-
trol of the bus and re-initiate another transmission. If
If the requested slave exists on the bus, it will respond so, the master device may send another Start bit in
with an Acknowledge bit, otherwise known as an ACK. place of the Stop bit or last ACK bit when it is in receive
The master then continues in either Transmit mode or mode.
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode, The I2C bus specifies three message protocols;
respectively. • Single message where a master writes data to a
A Start bit is indicated by a high-to-low transition of the slave.
SDAx line while the SCLx line is held high. Address and • Single message where a master reads data from
data bytes are sent out, Most Significant bit (MSb) first. a slave.
The Read/Write bit is sent out as a logical one when the • Combined message where a master initiates a
master intends to read data from the slave, and is sent minimum of two writes, or two reads, or a
out as a logical zero when it intends to write data to the combination of writes and reads, to one or more
slave. slaves.

PIC16(L)F1526/7
When one device is transmitting a logical one, or letting 21.3.2 ARBITRATION
the line float, and a second device is transmitting a
Each master device must monitor the bus for Start and
logical zero, or holding the line low, the first device can
Stop bits. If the device detects that the bus is busy, it
detect that the line is not a logical one. This detection,
cannot begin a new message until the bus returns to an
when used on the SCLx line, is called clock stretching.
Idle state.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on However, two master devices may try to initiate a
the SDAx line, it is called arbitration. Arbitration transmission on or about the same time. When this
ensures that there is only one master device occurs, the process of arbitration begins. Each
communicating at any single time. transmitter checks the level of the SDAx data line and
compares it to the level that it expects to find. The first
21.3.1 CLOCK STRETCHING transmitter to observe that the two levels do not match,
loses arbitration, and must stop transmitting on the
When a slave device has not completed processing
SDAx line.
data, it can delay the transfer of more data through the
process of clock stretching. An addressed slave device For example, if one transmitter holds the SDAx line to
may hold the SCLx clock line low after receiving or a logical one (lets it float) and a second transmitter
sending a bit, indicating that it is not yet ready to holds it to a logical zero (pulls it low), the result is that
continue. The master that is communicating with the the SDAx line will be low. The first transmitter then
slave will attempt to raise the SCLx line in order to observes that the level of the line is different than
transfer the next bit, but will detect that the clock line expected and concludes that another transmitter is
has not yet been released. Because the SCLx connec- communicating.
tion is open-drain, the slave has the ability to hold that The first transmitter to notice this difference is the one
line low until it is ready to continue communicating. that loses arbitration and must stop driving the SDAx
Clock stretching allows receivers that cannot keep up line. If this transmitter is also a master device, it also
with a transmitter to control the flow of incoming data. must stop driving the SCLx line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDAx line continues with its
original transmission. It can do so without any compli-
cations, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less
common.
If two master devices are sending a message to two
different slave devices at the address stage, the master
sending the lower slave address always wins arbitra-
tion. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a
necessary process for proper multi-master support.

PIC16(L)F1526/7
21.4 I2C MODE OPERATION TABLE 21-2: I2C BUS TERMS
TERM Description
All MSSPx I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and 2 interrupt Transmitter The device which shifts data out
flags interface the module with the PIC® microcontrol- onto the bus.
ler and user software. Two pins, SDAx and SCLx, are Receiver The device which shifts data in
exercised by the module to communicate with other from the bus.
external I2C devices. Master The device that initiates a transfer,
21.4.1 BYTE FORMAT generates clock signals and
terminates a transfer.
All communication in I2C is done in 9-bit segments. A Slave The device addressed by the
byte is sent from a master to a slave or vice-versa, fol- master.
lowed by an Acknowledge bit sent back. After the 8th Multi-master A bus with more than one device
falling edge of the SCLx line, the device outputting that can initiate data transfers.
data on the SDAx changes that pin to an input and
Arbitration Procedure to ensure that only one
reads in an acknowledge value on the next clock
master at a time controls the bus.
pulse.
Winning arbitration ensures that
The clock signal, SCLx, is provided by the master. the message is not corrupted.
Data is valid to change while the SCLx signal is low, Synchronization Procedure to synchronize the
and sampled on the rising edge of the clock. Changes clocks of two or more devices on
on the SDAx line while the SCLx line is high define the bus.
special conditions on the bus, explained below.
Idle No master is controlling the bus,
21.4.2 DEFINITION OF I2C TERMINOLOGY and both SDAx and SCLx lines are
high.
There is language and terminology in the description
Active Any time one or more master
of I2C communication that have definitions specific to
devices are controlling the bus.
I2C. That word usage is defined below and may be
used in the rest of this document without explanation. Addressed Slave device that has received a
This table was adapted from the Philips I2C Slave matching address and is actively
specification. being clocked by a master.
Matching Address byte that is clocked into a
21.4.3 SDAX AND SCLX PINS Address slave that matches the value
stored in SSPxADD.
Selection of any I2C mode with the SSPEN bit set,
forces the SCLx and SDAx pins to be open-drain. Write Request Slave receives a matching
These pins should be set by the user to inputs by set- address with R/W bit clear, and is
ting the appropriate TRIS bits. ready to clock in data.
Read Request Master sends an address byte with
Note: Data is tied to output zero when an I2C the R/W bit set, indicating that it
mode is enabled. wishes to clock data out of the
Slave. This data is the next and all
21.4.4 SDAX HOLD TIME
following bytes until a Restart or
The hold time of the SDAx pin is selected by the Stop.
SDAHT bit of the SSPxCON3 register. Hold time is the Clock Stretching When a device on the bus hold
time SDAx is held valid after the falling edge of SCLx. SCLx low to stall communication.
Setting the SDAHT bit selects a longer 300 ns mini- Bus Collision Any time the SDAx line is sampled
mum hold time and may help on buses with large low by the module while it is out-
capacitance. putting and expected high state.

PIC16(L)F1526/7
21.4.5 START CONDITION 21.4.7 RESTART CONDITION
The I2C specification defines a Start condition as a A Restart is valid any time that a Stop would be valid.
transition of SDAx from a high to a low state while A master can issue a Restart if it wishes to hold the
SCLx line is high. A Start condition is always gener- bus after terminating the current transfer. A Restart
ated by the master and signifies the transition of the has the same effect on the slave that a Start would,
bus from an Idle to an Active state. Figure 21-12 resetting all slave logic and preparing it to clock in an
shows wave forms for Start and Stop conditions. address. The master may want to address the same or
A bus collision can occur on a Start condition if the another slave. Figure 21-13 shows the wave form for a
module samples the SDAx line low before asserting it Restart condition.
low. This does not conform to the I2C Specification that In 10-bit Addressing Slave mode a Restart is required
states no bus collision can occur on a Start. for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
21.4.6 STOP CONDITION ing both high and low address bytes, the master can
A Stop condition is a transition of the SDAx line from issue a Restart and the high address byte with the
low-to-high state while the SCLx line is high. R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
Note: At least one SCLx low time must appear
After a full match with R/W clear in 10-bit mode, a prior
before a Stop is valid, therefore, if the SDAx
match flag is set and maintained. Until a Stop condi-
line goes low then high again while the SCLx
tion, a high address with R/W clear, or high address
line stays high, only the Start condition is
match fails.
detected.
21.4.8 START/STOP CONDITION INTERRUPT
MASKING
The SCIE and PCIE bits of the SSPxCON3 register
can enable the generation of an interrupt in Slave
modes that do not typically support this function. Slave
modes where interrupt on Start and Stop detect are
already enabled, these bits will have no effect.
FIGURE 21-12: I2C START AND STOP CONDITIONS
SDAx
SCLx
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition

PIC16(L)F1526/7
FIGURE 21-13: I2C RESTART CONDITION
Sr
Change of Change of
Data Allowed Data Allowed
Restart
Condition

PIC16(L)F1526/7
21.4.9 ACKNOWLEDGE SEQUENCE 21.5 I2C SLAVE MODE OPERATION
The 9th SCLx pulse for any transferred byte in I2C is The MSSPx Slave mode operates in one of four
dedicated as an Acknowledge. It allows receiving modes selected in the SSPM bits of SSPxCON1 regis-
devices to respond back to the transmitter by pulling ter. The modes can be divided into 7-bit and 10-bit
the SDAx line low. The transmitter must release con- Addressing mode. 10-bit Addressing modes operate
trol of the line during this time to shift in the response. the same as 7-bit with some additional overhead for
The Acknowledge (ACK) is an active-low signal, pull- handling the larger addresses.
ing the SDAx line low indicated to the transmitter that
the device has received the transmitted data and is Modes with Start and Stop bit interrupts operated the
ready to receive more. same as the other modes with SSPxIF additionally
getting set upon detection of a Start, Restart, or Stop
The result of an ACK is placed in the ACKSTAT bit of condition.
the SSPxCON2 register.
21.5.1 SLAVE MODE ADDRESSES
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to The SSPxADD register (Register 21-6) contains the
the transmitter. The ACKDT bit of the SSPxCON2 reg- Slave mode address. The first byte received after a
ister is set/cleared to determine the response. Start or Restart condition is compared against the
Slave hardware will generate an ACK response if the value stored in this register. If the byte matches, the
AHEN and DHEN bits of the SSPxCON3 register are value is loaded into the SSPxBUF register and an
clear. interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the soft-
There are certain conditions where an ACK will not be
ware that anything happened.
sent by the slave. If the BF bit of the SSPxSTAT regis-
ter or the SSPOV bit of the SSPxCON1 register are The SSPx Mask register (Register 21-5) affects the
set when a byte is received. address matching process. See Section 21.5.9
“SSPx Mask Register” for more information.
When the module is addressed, after the 8th falling
edge of SCLx on the bus, the ACKTIM bit of the SSPx- 21.5.1.1 I2C Slave 7-bit Addressing Mode
CON3 register is set. The ACKTIM bit indicates the
acknowledge time of the active bus. The ACKTIM Sta- In 7-bit Addressing mode, the LSb of the received data
tus bit is only active when the AHEN bit or DHEN bit is byte is ignored when determining if there is an address
enabled. match.
21.5.1.2 I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb’s of the 10-bit address and
stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte the UA bit is set
and SCLx is held low until the user updates SSPxADD
with the low address. The low address byte is clocked
in and all 8 bits are compared to the low address value
in SSPxADD. Even if there is not an address match;
SSPxIF and UA are set, and SCLx is held low until
SSPxADD is updated to receive a high byte again.
When SSPxADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave hard-
ware will then acknowledge the read request and pre-
pare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.

PIC16(L)F1526/7
21.5.2 SLAVE RECEPTION 21.5.2.2 7-bit Reception with AHEN and DHEN
When the R/W bit of a matching received address byte Slave device reception with AHEN and DHEN set
is clear, the R/W bit of the SSPxSTAT register is operate the same as without these options with extra
cleared. The received address is loaded into the interrupts and clock stretching added after the 8th fall-
SSPxBUF register and acknowledged. ing edge of SCLx. These additional interrupts allow the
When the overflow condition exists for a received slave software to decide whether it wants to ACK the
address, then not Acknowledge is given. An overflow receive address or data byte, rather than the hard-
condition is defined as either bit BF of the SSPxSTAT ware. This functionality adds support for PMBus™ that
register is set, or bit SSPOV of the SSPxCON1 register was not present on previous versions of this module.
is set. The BOEN bit of the SSPxCON3 register This list describes the steps that need to be taken by
modifies this operation. For more information see slave software to use these options for I2C communi-
Register 21-4. cation. Figure 21-16 displays a module using both
An MSSPx interrupt is generated for each transferred address and data holding. Figure 21-17 includes the
data byte. Flag bit, SSPxIF, must be cleared by operation with the SEN bit of the SSPxCON2 register
software. set.
When the SEN bit of the SSPxCON2 register is set, 1. S bit of SSPxSTAT is set; SSPxIF is set if
SCLx will be held low (clock stretch) following each interrupt on Start detect is enabled.
received byte. The clock must be released by setting 2. Matching address with R/W bit clear is clocked
the CKP bit of the SSPxCON1 register, except in. SSPxIF is set and CKP cleared after the 8th
sometimes in 10-bit mode. See Section 21.2.3 “SPI falling edge of SCLx.
Master Mode” for more detail. 3. Slave clears the SSPxIF.
4. Slave can look at the ACKTIM bit of the SSPx-
21.5.2.1 7-bit Addressing Reception
CON3 register to determine if the SSPxIF was
This section describes a standard sequence of events after or before the ACK.
for the MSSPx module configured as an I2C slave in 5. Slave reads the address value from SSPxBUF,
7-bit Addressing mode. Figure 21-14 and Figure 21-15 clearing the BF flag.
is used as a visual reference for this description. 6. Slave sets ACK value clocked out to the master
This is a step by step process of what typically must by setting ACKDT.
be done to accomplish I2C communication. 7. Slave releases the clock by setting CKP.
1. Start bit detected. 8. SSPxIF is set after an ACK, not after a NACK.
2. S bit of SSPxSTAT is set; SSPxIF is set if 9. If SEN = 1 the slave hardware will stretch the
interrupt on Start detect is enabled. clock after the ACK.
3. Matching address with R/W bit clear is received. 10. Slave clears SSPxIF.
4. The slave pulls SDAx low sending an ACK to the Note: SSPxIF is still set after the 9th falling edge of
master, and sets SSPxIF bit. SCLx even if there is no clock stretching and
5. Software clears the SSPxIF bit. BF has been cleared. Only if NACK is sent
6. Software reads received address from to master is SSPxIF not set
SSPxBUF clearing the BF flag. 11. SSPxIF set and CKP cleared after 8th falling
7. If SEN = 1; Slave software sets CKP bit to edge of SCLx for a received data byte.
release the SCLx line. 12. Slave looks at ACKTIM bit of SSPxCON3 to
8. The master clocks out a data byte. determine the source of the interrupt.
9. Slave drives SDAx low sending an ACK to the 13. Slave reads the received data from SSPxBUF
master, and sets SSPxIF bit. clearing BF.
10. Software clears SSPxIF. 14. Steps 7-14 are the same for each received data
11. Software reads the received byte from byte.
SSPxBUF clearing BF. 15. Communication is ended by either the slave
12. Steps 8-12 are repeated for all received bytes sending an ACK = 1, or the master sending a
from the master. Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
13. Master sends Stop condition, setting P bit of
by polling the P bit of the SSTSTAT register.
SSPxSTAT, and the bus goes idle.

FIGURE 21-14:
Bus Master sends

Stop condition
From Slave to Master

Receiving Address Receiving Data Receiving Data ACK = 1
SDAx
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF
SSPxIF set on 9th
Cleared by software Cleared by software falling edge of
SCLx
BF
First byte
SSPxBUF is read of data is
available
in SSPxBUF
SSPOV
SSPOV set because

SSPxBUF is still full.
ACK is not sent.
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
DS40001458D-page 211
PIC16(L)F1526/7
FIGURE 21-15:
Bus Master sends

Stop condition
DS40001458D-page 212
Receive Address Receive Data Receive Data ACK
SDAx A7 A6 A5 A4 A3 A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCLx S 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 SEN 1 2 3 4 5 6 7 8 9 P

PIC16(L)F1526/7
Clock is held low until CKP is set to ‘1’
SSPxIF
SSPxIF set on 9th

Cleared by software Cleared by software falling edge of SCLx
BF
First byte
of data is
SSPxBUF is read available
in SSPxBUF
SSPOV
SSPOV set because

SSPxBUF is still full.
ACK is not sent.
CKP
SCLx is not held

CKP is written to ‘1’ in software, CKP is written to ‘1’ in software,
low because
releasing SCLx releasing SCLx
ACK= 1

Master Releases SDAx Master sends
to slave for ACK sequence Stop condition
FIGURE 21-16:
SDAx Receiving Address Receiving Data ACK Received Data ACK=1

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCLx
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P

SSPxIF
If AHEN = 1: SSPxIF is set on
SSPxIF is set 9th falling edge of Cleared by software No interrupt
SCLx, after ACK after not ACK
BF from Slave
Address is
read from Data is read from SSPxBUF
ACKDT SSBUF
Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
CKP byte not ACK
When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCLx is released
and SCLx is stretched hardware on 8th falling
edge of SCLx
ACKTIM
ACKTIM set by hardware ACKTIM cleared by ACKTIM set by hardware

on 8th falling edge of SCLx hardware in 9th on 8th falling edge of SCLx
rising edge of SCLx
P
DS40001458D-page 213
PIC16(L)F1526/7
Master sends
FIGURE 21-17:
Stop condition
Master releases
R/W = 0 SDAx to slave for ACK sequence
DS40001458D-page 214
Receiving Address Receive Data Receive Data ACK
SDAx ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
PIC16(L)F1526/7
SSPxIF
Cleared by software No interrupt after
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSPxBUF can be
SSPxBUF available on SSPxBUF read any time before
next byte is loaded
ACKDT
Slave software clears

Slave sends
ACKDT to ACK not ACK
the received byte
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCLx of an address of SCLx of a received release SCLx
byte, CKP is cleared data byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware ACKTIM is cleared by hardware

on 8th falling edge of SCLx on 9th rising edge of SCLx
P

PIC16(L)F1526/7
21.5.3 SLAVE TRANSMISSION 21.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A master device can transmit a read request to a
and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list
SSPxSTAT register is set. The received address is below outlines what software for a slave will need to
loaded into the SSPxBUF register, and an ACK pulse is do to accomplish a standard transmission.
sent by the slave on the ninth bit. Figure 21-18 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDAx and
and the SCLx pin is held low (see Section 21.5.6 SCLx.
“Clock Stretching” for more detail). By stretching the 2. S bit of SSPxSTAT is set; SSPxIF is set if
clock, the master will be unable to assert another clock interrupt on Start detect is enabled.
pulse until the slave is done preparing the transmit 3. Matching address with R/W bit set is received by
data. the slave setting SSPxIF bit.
The transmit data must be loaded into the SSPxBUF 4. Slave hardware generates an ACK and sets
register which also loads the SSPxSR register. Then SSPxIF.
the SCLx pin should be released by setting the CKP bit 5. SSPxIF bit is cleared by user.
of the SSPxCON1 register. The eight data bits are
6. Software reads the received address from
shifted out on the falling edge of the SCLx input. This
SSPxBUF, clearing BF.
ensures that the SDAx signal is valid during the SCLx
high time. 7. R/W is set so CKP was automatically cleared
after the ACK.
The ACK pulse from the master-receiver is latched on
8. The slave software loads the transmit data into
the rising edge of the ninth SCLx input pulse. This ACK
SSPxBUF.
value is copied to the ACKSTAT bit of the SSPxCON2
register. If ACKSTAT is set (not ACK), then the data 9. CKP bit is set releasing SCLx, allowing the
transfer is complete. In this case, when the not ACK is master to clock the data out of the slave.
latched by the slave, the slave goes idle and waits for 10. SSPxIF is set after the ACK response from the
another occurrence of the Start bit. If the SDAx line was master is loaded into the ACKSTAT register.
low (ACK), the next transmit data must be loaded into 11. SSPxIF bit is cleared.
the SSPxBUF register. Again, the SCLx pin must be 12. The slave software checks the ACKSTAT bit to
released by setting bit CKP. see if the master wants to clock out more data.
An MSSPx interrupt is generated for each data transfer Note 1: If the master ACKs the clock will be
byte. The SSPxIF bit must be cleared by software and stretched.
the SSPxSTAT register is used to determine the status
of the byte. The SSPxIF bit is set on the falling edge of 2: ACKSTAT is the only bit updated on the
the ninth clock pulse. rising edge of SCLx (9th) rather than the
falling.
21.5.3.1 Slave Mode Bus Collision 13. Steps 9-13 are repeated for each transmitted
A slave receives a Read request and begins shifting byte.
data out on the SDAx line. If a bus collision is detected 14. If the master sends a not ACK; the clock is not
and the SBCDE bit of the SSPxCON3 register is set, held, but SSPxIF is still set.
the BCLxIF bit of the PIRx register is set. Once a bus 15. The master sends a Restart condition or a Stop.
collision is detected, the slave goes Idle and waits to be 16. The slave is no longer addressed.
addressed again. User software can use the BCLxIF bit
to handle a slave bus collision.

Master sends
Stop condition
FIGURE 21-18:
Receiving Address Transmitting Data Automatic Transmitting Data ACK

R/W = 1 Automatic
SDAx A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
DS40001458D-page 216
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF
Cleared by software
PIC16(L)F1526/7
BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCLx
CKP
When R/W is set CKP is not
SCLx is always held for not
held low after 9th SCLx Set by software ACK
falling edge
ACKSTAT
Masters not ACK

is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Indicates an address
has been received

PIC16(L)F1526/7
21.5.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt gen-
eration after the 8th falling edge of a received match-
ing address. Once a matching address has been
clocked in, CKP is cleared and the SSPxIF interrupt is
set.
Figure 21-19 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the 8th falling edge of the SCLx line the
CKP bit is cleared and SSPxIF interrupt is gen-
erated.
4. Slave software clears SSPxIF.
5. Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
8. Slave sets the CKP bit releasing SCLx.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCLx pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCLx
line to receive a Stop.

Master sends
Master releases SDAx Stop condition
FIGURE 21-19:
to slave for ACK sequence

Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK
DS40001458D-page 218
SDAx ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCLx
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P
SSPxIF
Cleared by software
PIC16(L)F1526/7
BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCLx
ACKDT
Slave clears
ACKDT to ACK
address
ACKSTAT
Master’s ACK
response is copied
to SSPxSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCLx
address. cleared after ACK
ACKTIM
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
ACKTIM is set on 8th falling ACKTIM is cleared

edge of SCLx on 9th rising edge of SCLx
R/W
D/A

PIC16(L)F1526/7
21.5.4 SLAVE MODE 10-BIT ADDRESS 21.5.5 10-BIT ADDRESSING WITH ADDRESS OR
RECEPTION DATA HOLD
This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSPx module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSPxADD register
Figure 21-20 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCLx line is held low are the
same. Figure 21-21 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 21-22 shows a standard waveform for a slave
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Slave loads low address into SSPxADD,
releasing SCLx.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
9. Slave sends ACK and SSPxIF is set.

Note: If the low address does not match, SSPxIF
and UA are still set so that the slave soft-
ware can set SSPxADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSPxIF.
11. Slave reads the received matching address
from SSPxBUF clearing BF.
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCLx
pulse; SSPxIF is set.
14. If SEN bit of SSPxCON2 is set, CKP is cleared
by hardware and the clock is stretched.
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCLx.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.

FIGURE 21-20:
Master sends
Stop condition
DS40001458D-page 220
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDAx
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
PIC16(L)F1526/7
SCLx is held low

while CKP = 0
SSPxIF
Set by hardware Cleared by software
on 9th falling edge
BF
If address matches Receive address is Data is read
SSPxADD it is loaded into read from SSPxBUF from SSPxBUF
SSPxBUF
UA
When UA = 1; Software updates SSPxADD
SCLx is held low and releases SCLx
CKP
When SEN = 1; Set by software,

CKP is cleared after releasing SCLx
9th falling edge of received byte

Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
FIGURE 21-21:
SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5
SCLx S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2

SSPxIF
Set by hardware Cleared by software Cleared by software
on 9th falling edge
BF
SSPxBUF can be Received data

read anytime before is read from
the next received byte SSPxBUF
ACKDT
Slave software clears
ACKDT to ACK
the received byte
UA
Update to SSPxADD is Update of SSPxADD,

not allowed until 9th
falling edge of SCLx clears UA and releases
SCLx
CKP If when AHEN = 1;

on the 8th falling edge Set CKP with software
of SCLx of an address releases SCLx
byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCLx
DS40001458D-page 221
PIC16(L)F1526/7
FIGURE 21-22:
Master sends
DS40001458D-page 222
Master sends Stop condition
Restart event Master sends
not ACK
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDAx 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCLx 1 2 3 4 5 6 7 8 9 1 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
PIC16(L)F1526/7
S 2 3 4 5 P
Sr
SSPxIF
Set by hardware Cleared by software Set by hardware
BF
SSPxBUF loaded Received address is Data to transmit is

with received address read from SSPxBUF loaded into SSPxBUF
UA
High address is loaded
UA indicates SSPxADD After SSPxADD is back into SSPxADD
must be updated updated, UA is cleared
CKP and SCLx is released
When R/W = 1; Set by software

ACKSTAT CKP is cleared on releases SCLx
9th falling edge of SCLx
Masters not ACK

is copied
R/W
R/W is copied from the
matching address byte
D/A
Indicates an address
has been received
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)

PIC16(L)F1526/7
21.5.6 CLOCK STRETCHING 21.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the
holds the SCLx line low effectively pausing communi- clock is always stretched. This is the only time the
cation. The slave may stretch the clock to allow more SCLx is stretched without CKP being cleared. SCLx is
time to handle data or prepare a response for the mas- released immediately after a write to SSPxADD.
ter device. A master device is not concerned with
Note: Previous versions of the module did not
stretching as anytime it is active on the bus and not
stretch the clock if the second address byte
transferring data it is stretching. Any stretching done
did not match.
by a slave is invisible to the master software and han-
dled by the hardware that generates SCLx. 21.5.6.3 Byte NACKing
The CKP bit of the SSPxCON1 register is used to con-
trol stretching in software. Any time the CKP bit is When AHEN bit of SSPxCON3 is set; CKP is cleared
cleared, the module will wait for the SCLx line to go by hardware after the 8th falling edge of SCLx for a
low and then hold it. Setting CKP will release SCLx received matching address byte. When DHEN bit of
and allow more communication. SSPxCON3 is set; CKP is cleared after the 8th falling
edge of SCLx for received data.
21.5.6.1 Normal Clock Stretching Stretching after the 8th falling edge of SCLx allows the
Following an ACK if the R/W bit of SSPxSTAT is set, a slave to look at the received address or data and
read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data.
allows the slave time to update SSPxBUF with data to 21.5.7 CLOCK SYNCHRONIZATION AND
transfer to the master. If the SEN bit of SSPxCON2 is THE CKP BIT
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait
is set by software and communication resumes. for the SCLx line to go low and then hold it. However,
clearing the CKP bit will not assert the SCLx output
Note 1: The BF bit has no effect on if the clock will
low until the SCLx output is already sampled low.
be stretched or not. This is different than
Therefore, the CKP bit will not assert the SCLx line
previous versions of the module that
until an external I2C master device has already
would not stretch the clock, clear CKP, if
asserted the SCLx line. The SCLx output will remain
SSPxBUF was read before the 9th falling
low until the CKP bit is set and all other devices on the
edge of SCLx.
I2C bus have released SCLx. This ensures that a write
2: Previous versions of the module did not to the CKP bit will not violate the minimum high time
stretch the clock for a transmission if requirement for SCLx (see Figure 21-23).
SSPxBUF was loaded before the 9th fall-
ing edge of SCLx. It is now always cleared
for read requests.
FIGURE 21-23: CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDAx DX DX ‚ – 1
SCLx
Master device
CKP asserts clock
Master device
releases clock
WR
SSPxCON1

PIC16(L)F1526/7
21.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
The addressing procedure for the I2C bus is such that will prepare to receive the second byte as data, just as
the first byte after the Start condition usually deter- it would in 7-bit mode.
mines which device will be the slave addressed by the
master device. The exception is the general call If the AHEN bit of the SSPxCON3 register is set, just
address which can address all devices. When this as with any other address reception, the slave hard-
address is used, all devices should, in theory, respond ware will stretch the clock after the 8th falling edge of
with an acknowledge. SCLx. The slave must then set its ACKDT value and
release the clock with communication progressing as it
The general call address is a reserved address in the would normally.
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPxCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPxADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPxBUF and respond.
Figure 21-24 shows a general call reception
sequence.
FIGURE 21-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address
after ACK, set interrupt
R/W = 0 Receiving Data ACK

SDAx General Call Address ACK D7 D6 D5 D4 D3 D2 D1 D0
SCLx
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
’1’
21.5.9 SSPX MASK REGISTER

An SSPx Mask (SSPxMSK) register (Register 21-5) is
available in I2C Slave mode as a mask for the value
held in the SSPxSR register during an address
comparison operation. A zero (‘0’) bit in the SSPxMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSPx operation until written with a mask value.
The SSPx Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSPx mask has no effect during the
reception of the first (high) byte of the address.

PIC16(L)F1526/7
21.6 I2C MASTER MODE 21.6.1 I2C MASTER MODE OPERATION
Master mode is enabled by setting and clearing the The master device generates all of the serial clock
appropriate SSPM bits in the SSPxCON1 register and pulses and the Start and Stop conditions. A transfer is
by setting the SSPEN bit. In Master mode, the SDA and ended with a Stop condition or with a Repeated Start
SCK pins must be configured as inputs. The MSSP condition. Since the Repeated Start condition is also
peripheral hardware will override the output driver TRIS the beginning of the next serial transfer, the I2C bus will
controls when necessary to drive the pins low. not be released.
Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output
generation on the detection of the Start and Stop con- through SDAx, while SCLx outputs the serial clock. The
ditions. The Stop (P) and Start (S) bits are cleared from first byte transmitted contains the slave address of the
a Reset or when the MSSPx module is disabled. Con- receiving device (7 bits) and the Read/Write (R/W) bit.
trol of the I 2C bus may be taken when the P bit is set, In this case, the R/W bit will be logic ‘0’. Serial data is
or the bus is Idle. transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
In Firmware Controlled Master mode, user code conditions are output to indicate the beginning and the
conducts all I 2C bus operations based on Start and end of a serial transfer.
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted con-
other communication is done by the user software tains the slave address of the transmitting device
directly manipulating the SDAx and SCLx lines. (7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
The following events will cause the SSPx Interrupt Flag address followed by a ‘1’ to indicate the receive bit.
bit, SSPxIF, to be set (SSPx interrupt, if enabled): Serial data is received via SDAx, while SCLx outputs
• Start condition detected the serial clock. Serial data is received 8 bits at a time.
After each byte is received, an Acknowledge bit is
• Stop condition detected
transmitted. Start and Stop conditions indicate the
• Data transfer byte transmitted/received beginning and end of transmission.
• Acknowledge transmitted/received
A Baud Rate Generator is used to set the clock
• Repeated Start generated frequency output on SCLx. See Section 21.7 “Baud
Note 1: The MSSPx module, when configured in Rate Generator” for more detail.
I2C Master mode, does not allow queue-
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPxBUF register
to initiate transmission before the Start
condition is complete. In this case, the
SSPxBUF will not be written to and the
WCOL bit will be set, indicating that a
write to the SSPxBUF did not occur
2: When in Master mode, Start/Stop detec-
tion is masked and an interrupt is gener-
ated when the SEN/PEN bit is cleared and
the generation is complete.

PIC16(L)F1526/7
21.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<7:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure 21-25).
FIGURE 21-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDAx DX DX ‚ – 1
SCLx deasserted but slave holds SCLx allowed to transition high

SCLx low (clock arbitration)
SCLx
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
SCLx is sampled high, reload takes

place and BRG starts its count
BRG
Reload
21.6.3 WCOL STATUS FLAG

If the user writes the SSPxBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not Idle.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.

PIC16(L)F1526/7
21.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended,
CONDITION TIMING leaving the SDAx line held low and the Start condition
is complete.
To initiate a Start condition (Figure 21-26), the user
sets the Start Enable bit, SEN bit of the SSPxCON2 Note 1: If at the beginning of the Start condition,
register. If the SDAx and SCLx pins are sampled high, the SDAx and SCLx pins are already sam-
the Baud Rate Generator is reloaded with the contents pled low, or if during the Start condition,
of SSPxADD<7:0> and starts its count. If SCLx and the SCLx line is sampled low before the
SDAx are both sampled high when the Baud Rate SDAx line is driven low, a bus collision
Generator times out (TBRG), the SDAx pin is driven occurs, the Bus Collision Interrupt Flag,
low. The action of the SDAx being driven low while BCLxIF, is set, the Start condition is
SCLx is high is the Start condition and causes the S bit aborted and the I2C module is reset into
of the SSPxSTAT1 register to be set. Following this, its Idle state.
the Baud Rate Generator is reloaded with the contents 2: The Philips I2C Specification states that a
of SSPxADD<7:0> and resumes its count. When the bus collision cannot occur on a Start.
Baud Rate Generator times out (TBRG), the SEN bit of
the SSPxCON2 register will be automatically cleared
FIGURE 21-26: FIRST START BIT TIMING
Write to SEN bit occurs here Set S bit (SSPxSTAT<3>)
At completion of Start bit,

SDAx = 1,
SCLx = 1 hardware clears SEN bit
and sets SSPxIF bit
TBRG TBRG Write to SSPxBUF occurs here
SDAx 1st bit 2nd bit
TBRG
SCLx
S
TBRG

PIC16(L)F1526/7
21.6.5 I2C MASTER MODE REPEATED CON2 register will be automatically cleared and the
START CONDITION TIMING Baud Rate Generator will not be reloaded, leaving the
SDAx pin held low. As soon as a Start condition is
A Repeated Start condition occurs when the RSEN bit detected on the SDAx and SCLx pins, the S bit of the
of the SSPxCON2 register is programmed high and the SSPxSTAT register will be set. The SSPxIF bit will not
master state machine is no longer active. When the be set until the Baud Rate Generator has timed out.
RSEN bit is set, the SCLx pin is asserted low. When the
SCLx pin is sampled low, the Baud Rate Generator is Note 1: If RSEN is programmed while any other
loaded and begins counting. The SDAx pin is released event is in progress, it will not take effect.
(brought high) for one Baud Rate Generator count 2: A bus collision during the Repeated Start
(TBRG). When the Baud Rate Generator times out, if condition occurs if:
SDAx is sampled high, the SCLx pin will be deasserted
(brought high). When SCLx is sampled high, the Baud • SDAx is sampled low when SCLx
Rate Generator is reloaded and begins counting. SDAx goes from low-to-high.
and SCLx must be sampled high for one TBRG. This • SCLx goes low before SDAx is
action is then followed by assertion of the SDAx pin asserted low. This may indicate
(SDAx = 0) for one TBRG while SCLx is high. SCLx is that another master is attempting to
asserted low. Following this, the RSEN bit of the SSPx- transmit a data ‘1’.
FIGURE 21-27: REPEAT START CONDITION WAVEFORM
S bit set by hardware

Write to SSPxCON2
occurs here At completion of Start bit,
SDAx = 1, SDAx = 1,
hardware clears RSEN bit
SCLx (no change) SCLx = 1 and sets SSPxIF
TBRG TBRG TBRG
SDAx 1st bit
Write to SSPxBUF occurs here

TBRG
SCLx
Sr TBRG
Repeated Start

PIC16(L)F1526/7
21.6.6 I2C MASTER MODE TRANSMISSION 21.6.6.3 ACKSTAT Status Flag
Transmission of a data byte, a 7-bit address or the In Transmit mode, the ACKSTAT bit of the SSPxCON2
other half of a 10-bit address is accomplished by simply register is cleared when the slave has sent an Acknowl-
writing a value to the SSPxBUF register. This action will edge (ACK = 0) and is set when the slave does not
set the Buffer Full flag bit, BF and allow the Baud Rate Acknowledge (ACK = 1). A slave sends an Acknowl-
Generator to begin counting and start the next trans- edge when it has recognized its address (including a
mission. Each bit of address/data will be shifted out general call), or when the slave has properly received
onto the SDAx pin after the falling edge of SCLx is its data.
asserted. SCLx is held low for one Baud Rate Genera-
21.6.6.4 Typical transmit sequence:
tor rollover count (TBRG). Data should be valid before
SCLx is released high. When the SCLx pin is released 1. The user generates a Start condition by setting
high, it is held that way for TBRG. The data on the SDAx the SEN bit of the SSPxCON2 register.
pin must remain stable for that duration and some hold 2. SSPxIF is set by hardware on completion of the
time after the next falling edge of SCLx. After the eighth Start.
bit is shifted out (the falling edge of the eighth clock),
3. SSPxIF is cleared by software.
the BF flag is cleared and the master releases SDAx.
This allows the slave device being addressed to 4. The MSSPx module will wait the required start
respond with an ACK bit during the ninth bit time if an time before any other operation takes place.
address match occurred, or if data was received prop- 5. The user loads the SSPxBUF with the slave
erly. The status of ACK is written into the ACKSTAT bit address to transmit.
on the rising edge of the ninth clock. If the master 6. Address is shifted out the SDAx pin until all 8 bits
receives an Acknowledge, the Acknowledge Status bit, are transmitted. Transmission begins as soon
ACKSTAT, is cleared. If not, the bit is set. After the ninth as SSPxBUF is written to.
clock, the SSPxIF bit is set and the master clock (Baud 7. The MSSPx module shifts in the ACK bit from
Rate Generator) is suspended until the next data byte the slave device and writes its value into the
is loaded into the SSPxBUF, leaving SCLx low and ACKSTAT bit of the SSPxCON2 register.
SDAx unchanged (Figure 21-28). 8. The MSSPx module generates an interrupt at
After the write to the SSPxBUF, each bit of the address the end of the ninth clock cycle by setting the
will be shifted out on the falling edge of SCLx until all SSPxIF bit.
seven address bits and the R/W bit are completed. On 9. The user loads the SSPxBUF with eight bits of
the falling edge of the eighth clock, the master will data.
release the SDAx pin, allowing the slave to respond 10. Data is shifted out the SDAx pin until all 8 bits
with an Acknowledge. On the falling edge of the ninth are transmitted.
clock, the master will sample the SDAx pin to see if the
11. The MSSPx module shifts in the ACK bit from
address was recognized by a slave. The status of the
the slave device and writes its value into the
ACK bit is loaded into the ACKSTAT Status bit of the
ACKSTAT bit of the SSPxCON2 register.
SSPxCON2 register. Following the falling edge of the
ninth clock transmission of the address, the SSPxIF is 12. Steps 8-11 are repeated for all transmitted data
set, the BF flag is cleared and the Baud Rate Generator bytes.
is turned off until another write to the SSPxBUF takes 13. The user generates a Stop or Restart condition
place, holding SCLx low and allowing SDAx to float. by setting the PEN or RSEN bits of the SSPx-
CON2 register. Interrupt is generated once the
21.6.6.1 BF Status Flag Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSPxSTAT register
is set when the CPU writes to SSPxBUF and is cleared
when all 8 bits are shifted out.
21.6.6.2 WCOL Status Flag

If the user writes the SSPxBUF when a transmit is
already in progress (i.e., SSPxSR is still shifting out a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.

FIGURE 21-28:
DS40001458D-page 230
Write SSPxCON2<0> SEN = 1 ACKSTAT in
Start condition begins SSPxCON2 = 1
From slave, clear ACKSTAT bit SSPxCON2<6>
SEN = 0
Transmitting Data or Second Half
Transmit Address to Slave R/W = 0 ACK
of 10-bit Address
SDAx A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
SSPxBUF written with 7-bit address and R/W

start transmit
PIC16(L)F1526/7
SCLx 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SCLx held low
while CPU
responds to SSPxIF
SSPxIF
Cleared by software service routine
Cleared by software from SSPx interrupt
Cleared by software
BF (SSPxSTAT<0>)
SSPxBUF written SSPxBUF is written by software

SEN
After Start condition, SEN cleared by hardware
PEN
R/W
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)

PIC16(L)F1526/7
21.6.7 I2C MASTER MODE RECEPTION 21.6.7.4 Typical Receive Sequence:
Master mode reception (Figure 21-29) is enabled by 1. The user generates a Start condition by setting
programming the Receive Enable bit, RCEN bit of the the SEN bit of the SSPxCON2 register.
SSPxCON2 register. 2. SSPxIF is set by hardware on completion of the
Note: The MSSPx module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSPxIF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSPxBUF with the slave address to
The Baud Rate Generator begins counting and on each transmit and the R/W bit set.
rollover, the state of the SCLx pin changes 5. Address is shifted out the SDAx pin until all 8 bits
(high-to-low/low-to-high) and data is shifted into the are transmitted. Transmission begins as soon
SSPxSR. After the falling edge of the eighth clock, the as SSPxBUF is written to.
receive enable flag is automatically cleared, the con- 6. The MSSPx module shifts in the ACK bit from
tents of the SSPxSR are loaded into the SSPxBUF, the the slave device and writes its value into the
BF flag bit is set, the SSPxIF flag bit is set and the Baud ACKSTAT bit of the SSPxCON2 register.
Rate Generator is suspended from counting, holding 7. The MSSPx module generates an interrupt at
SCLx low. The MSSPx is now in Idle state awaiting the the end of the ninth clock cycle by setting the
next command. When the buffer is read by the CPU, SSPxIF bit.
the BF flag bit is automatically cleared. The user can 8. User sets the RCEN bit of the SSPxCON2 regis-
then send an Acknowledge bit at the end of reception ter and the master clocks in a byte from the slave.
by setting the Acknowledge Sequence Enable, ACKEN
9. After the 8th falling edge of SCLx, SSPxIF and
bit of the SSPxCON2 register.
BF are set.
21.6.7.1 BF Status Flag 10. Master clears SSPxIF and reads the received
byte from SSPxUF, clears BF.
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPxSR. It 11. Master sets ACK value sent to slave in ACKDT
is cleared when the SSPxBUF register is read. bit of the SSPxCON2 register and initiates the
ACK by setting the ACKEN bit.
21.6.7.2 SSPOV Status Flag 12. Masters ACK is clocked out to the slave and
In receive operation, the SSPOV bit is set when 8 bits SSPxIF is set.
are received into the SSPxSR and the BF flag bit is 13. User clears SSPxIF.
already set from a previous reception. 14. Steps 8-13 are repeated for each received byte
from the slave.
21.6.7.3 WCOL Status Flag 15. Master sends a not ACK or Stop to end
If the user writes the SSPxBUF when a receive is communication.
already in progress (i.e., SSPxSR is still shifting in a
data byte), the WCOL bit is set and the contents of the
buffer are unchanged (the write does not occur).

Write to SSPxCON2<4>
to start Acknowledge sequence
SDAx = ACKDT (SSPxCON2<5>) = 0
Write to SSPxCON2<0>(SEN = 1),
FIGURE 21-29:
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDAx = ACKDT = 0 SDAx = ACKDT = 1
by programming SSPxCON2<3> (RCEN = 1)
DS40001458D-page 232
SEN = 0
PEN bit = 1
Write to SSPxBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDAx A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Bus master
ACK is not sent terminates
transfer
3 6 7 9
PIC16(L)F1526/7
1 2 4 5 8 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCLx S P
Data shifted in on falling edge of CLK Set SSPxIF at end
of receive Set SSPxIF interrupt
Set SSPxIF interrupt at end of Acknow-
Set SSPxIF interrupt ledge sequence
at end of receive at end of Acknowledge
SSPxIF sequence
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPxSTAT<4>)
SDAx = 0, SCLx = 1 Cleared in
while CPU software and SSPxIF
responds to SSPxIF
BF
(SSPxSTAT<0>) Last bit is shifted into SSPxSR and
contents are unloaded into SSPxBUF
SSPOV
SSPOV is set because

SSPxBUF is still full
ACKEN
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
RCEN
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPxCON2<3> (RCEN = 1) automatically SDAx = ACKDT = 0 automatically

PIC16(L)F1526/7
21.6.8 ACKNOWLEDGE SEQUENCE 21.6.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDAx pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPxCON2 register. At the end of a
SSPxCON2 register. When this bit is set, the SCLx pin is receive/transmit, the SCLx line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDAx pin. If the user wishes to the master will assert the SDAx line low. When the
generate an Acknowledge, then the ACKDT bit should SDAx line is sampled low, the Baud Rate Generator is
be cleared. If not, the user should set the ACKDT bit reloaded and counts down to ‘0’. When the Baud Rate
before starting an Acknowledge sequence. The Baud Generator times out, the SCLx pin will be brought high
Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count)
(TBRG) and the SCLx pin is deasserted (pulled high). later, the SDAx pin will be deasserted. When the SDAx
When the SCLx pin is sampled high (clock arbitration), pin is sampled high while SCLx is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCLx pin SSPxSTAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure 21-31).
matically cleared, the Baud Rate Generator is turned off
and the MSSPx module then goes into Idle mode 21.6.9.1 WCOL Status Flag
(Figure 21-30). If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
21.6.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSPxBUF when an Acknowledge not occur).
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
does not occur).
FIGURE 21-30: ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here, ACKEN automatically cleared
write to SSPxCON2
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDAx D0 ACK
SCLx 8 9
SSPxIF
Cleared in
SSPxIF set at software
the end of receive Cleared in
software SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.

PIC16(L)F1526/7
FIGURE 21-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPxCON2, SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG
set PEN after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
Falling edge of PEN bit (SSPxCON2<2>) is cleared by

9th clock hardware and the SSPxIF bit is set
TBRG
SCLx
SDAx ACK
P
TBRG TBRG TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
21.6.10 SLEEP OPERATION 21.6.13 MULTI -MASTER COMMUNICATION,

2
While in Sleep mode, the I C slave module can receive BUS COLLISION AND BUS
addresses or data and when an address match or ARBITRATION
complete byte transfer occurs, wake the processor Multi-Master mode support is achieved by bus arbitra-
from Sleep (if the MSSPx interrupt is enabled). tion. When the master outputs address/data bits onto
the SDAx pin, arbitration takes place when the master
21.6.11 EFFECTS OF A RESET outputs a ‘1’ on SDAx, by letting SDAx float high and
A Reset disables the MSSPx module and terminates another master asserts a ‘0’. When the SCLx pin floats
the current transfer. high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx pin is
21.6.12 MULTI-MASTER MODE ‘0’, then a bus collision has taken place. The master will
In Multi-Master mode, the interrupt generation on the set the Bus Collision Interrupt Flag, BCLxIF and reset
detection of the Start and Stop conditions allows the the I2C port to its Idle state (Figure 21-32).
determination of when the bus is free. The Stop (P) and If a transmit was in progress when the bus collision
Start (S) bits are cleared from a Reset or when the occurred, the transmission is halted, the BF flag is
MSSPx module is disabled. Control of the I 2C bus may cleared, the SDAx and SCLx lines are deasserted and
be taken when the P bit of the SSPxSTAT register is the SSPxBUF can be written to. When the user
set, or the bus is Idle, with both the S and P bits clear. services the bus collision Interrupt Service Routine and
When the bus is busy, enabling the SSPx interrupt will if the I2C bus is free, the user can resume communica-
generate the interrupt when the Stop condition occurs. tion by asserting a Start condition.
In multi-master operation, the SDAx line must be If a Start, Repeated Start, Stop or Acknowledge
monitored for arbitration to see if the signal level is the condition was in progress when the bus collision
expected output level. This check is performed by occurred, the condition is aborted, the SDAx and SCLx
hardware with the result placed in the BCLxIF bit. lines are deasserted and the respective control bits in
The states where arbitration can be lost are: the SSPxCON2 register are cleared. When the user
services the bus collision Interrupt Service Routine and
• Address Transfer if the I2C bus is free, the user can resume communica-
• Data Transfer tion by asserting a Start condition.
• A Start Condition The master will continue to monitor the SDAx and SCLx
• A Repeated Start Condition pins. If a Stop condition occurs, the SSPxIF bit will be set.
• An Acknowledge Condition A write to the SSPxBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPxSTAT
register, or the bus is Idle and the S and P bits are
cleared.

PIC16(L)F1526/7
FIGURE 21-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDAx. While SCLx is high,
Data changes SDAx line pulled low data does not match what is driven
while SCLx = 0 by another source by the master.
Bus collision has occurred.
SDAx released
by master
SDAx
SCLx Set bus collision

interrupt (BCLxIF)
BCLxIF

PIC16(L)F1526/7
21.6.13.1 Bus Collision During a Start SDAx pin, the SDAx pin is asserted low at the end of
Condition the BRG count. The Baud Rate Generator is then
reloaded and counts down to zero; if the SCLx pin is
During a Start condition, a bus collision occurs if:
sampled as ‘0’ during this time, a bus collision does not
a) SDAx or SCLx are sampled low at the beginning occur. At the end of the BRG count, the SCLx pin is
of the Start condition (Figure 21-33). asserted low.
b) SCLx is sampled low before SDAx is asserted
Note: The reason that bus collision is not a
low (Figure 21-34).
factor during a Start condition is that no
During a Start condition, both the SDAx and the SCLx two bus masters can assert a Start
pins are monitored. condition at the exact same time. There-
If the SDAx pin is already low, or the SCLx pin is fore, one master will always assert SDAx
already low, then all of the following occur: before the other. This condition does not
cause a bus collision because the two
• the Start condition is aborted,
masters must be allowed to arbitrate the
• the BCLxIF flag is set and first address following the Start condition.
• the MSSPx module is reset to its Idle state If the address is the same, arbitration
(Figure 21-33). must be allowed to continue into the data
The Start condition begins with the SDAx and SCLx portion, Repeated Start or Stop
pins deasserted. When the SDAx pin is sampled high, conditions.
the Baud Rate Generator is loaded and counts down. If
the SCLx pin is sampled low while SDAx is high, a bus
collision occurs because it is assumed that another
master is attempting to drive a data ‘1’ during the Start
condition.
If the SDAx pin is sampled low during this count, the
BRG is reset and the SDAx line is asserted early
(Figure 21-35). If, however, a ‘1’ is sampled on the
FIGURE 21-33: BUS COLLISION DURING START CONDITION (SDAX ONLY)

SDAx goes low before the SEN bit is set.
Set BCLxIF,
S bit and SSPxIF set because
SDAx = 0, SCLx = 1.
SDAx
SCLx
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDAx = 1, SCLx = 1 SSPx module reset into Idle state.
SEN
SDAx sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
BCLxIF SDAx = 0, SCLx = 1.
SSPxIF and BCLxIF are
cleared by software
SSPxIF
SSPxIF and BCLxIF are

cleared by software

PIC16(L)F1526/7
FIGURE 21-34: BUS COLLISION DURING START CONDITION (SCLX = 0)
SDAx = 0, SCLx = 1
TBRG TBRG
SDAx
SCLx Set SEN, enable Start

sequence if SDAx = 1, SCLx = 1
SCLx = 0 before SDAx = 0,
bus collision occurs. Set BCLxIF.
SEN
SCLx = 0 before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
by software
S ’0’ ’0’
SSPxIF ’0’ ’0’
FIGURE 21-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDAx = 0, SCLx = 1
Set S Set SSPxIF
Less than TBRG
TBRG
SDAx SDAx pulled low by other master.

Reset BRG and assert SDAx.
SCLx S
SCLx pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDAx = 1, SCLx = 1
BCLxIF ’0’
SSPxIF
SDAx = 0, SCLx = 1, Interrupts cleared
set SSPxIF by software

PIC16(L)F1526/7
21.6.13.2 Bus Collision During a Repeated If SDAx is low, a bus collision has occurred (i.e., another
Start Condition master is attempting to transmit a data ‘0’, Figure 21-36).
If SDAx is sampled high, the BRG is reloaded and
During a Repeated Start condition, a bus collision
begins counting. If SDAx goes from high-to-low before
occurs if:
the BRG times out, no bus collision occurs because no
a) A low level is sampled on SDAx when SCLx two masters can assert SDAx at exactly the same time.
goes from low level to high level (Case 1).
If SCLx goes from high-to-low before the BRG times
b) SCLx goes low before SDAx is asserted low, out and SDAx has not already been asserted, a bus
indicating that another master is attempting to collision occurs. In this case, another master is
transmit a data ‘1’ (Case 2). attempting to transmit a data ‘1’ during the Repeated
When the user releases SDAx and the pin is allowed to Start condition, see Figure 21-37.
float high, the BRG is loaded with SSPxADD and If, at the end of the BRG time-out, both SCLx and SDAx
counts down to zero. The SCLx pin is then deasserted are still high, the SDAx pin is driven low and the BRG
and when sampled high, the SDAx pin is sampled. is reloaded and begins counting. At the end of the
count, regardless of the status of the SCLx pin, the
SCLx pin is driven low and the Repeated Start
condition is complete.
FIGURE 21-36: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDAx
SCLx
Sample SDAx when SCLx goes high.

If SDAx = 0, set BCLxIF and release SDAx and SCLx.
RSEN
BCLxIF
Cleared by software
S ’0’
SSPxIF ’0’
FIGURE 21-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDAx
SCLx
SCLx goes low before SDAx,

BCLxIF set BCLxIF. Release SDAx and SCLx.
Interrupt cleared
by software
RSEN
S ’0’
SSPxIF

PIC16(L)F1526/7
21.6.13.3 Bus Collision During a Stop The Stop condition begins with SDAx asserted low.
Condition When SDAx is sampled low, the SCLx pin is allowed to
float. When the pin is sampled high (clock arbitration),
Bus collision occurs during a Stop condition if:
the Baud Rate Generator is loaded with SSPxADD and
a) After the SDAx pin has been deasserted and counts down to 0. After the BRG times out, SDAx is
allowed to float high, SDAx is sampled low after sampled. If SDAx is sampled low, a bus collision has
the BRG has timed out (Case 1). occurred. This is due to another master attempting to
b) After the SCLx pin is deasserted, SCLx is drive a data ‘0’ (Figure 21-38). If the SCLx pin is
sampled low before SDAx goes high (Case 2). sampled low before SDAx is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 21-39).
FIGURE 21-38: BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG SDAx sampled

low after TBRG,
set BCLxIF
SDAx
SDAx asserted low

SCLx
PEN
BCLxIF
P ’0’
SSPxIF ’0’
FIGURE 21-39: BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDAx
Assert SDAx SCLx goes low before SDAx goes high,

set BCLxIF
SCLx
PEN
BCLxIF
P ’0’
SSPxIF ’0’

PIC16(L)F1526/7
TABLE 21-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION
Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values on
Page:

SSP1ADD ADD<7:0> 247
SSP2ADD ADD<7:0> 247
SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 245
SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 245
SSP1MSK MSK<7:0> 247
SSP2MSK MSK<7:0> 247
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C mode.

PIC16(L)F1526/7
21.7 BAUD RATE GENERATOR module clock line. The logic dictating when the reload
signal is asserted depends on the mode the MSSPx is
The MSSPx module has a Baud Rate Generator avail- being operated in.
able for clock generation in both I2C and SPI Master
Table 21-4 demonstrates clock rates based on
modes. The Baud Rate Generator (BRG) reload value
instruction cycles and the BRG value loaded into
is placed in the SSPxADD register (Register 21-6).
SSPxADD.
When a write occurs to SSPxBUF, the Baud Rate
Generator will automatically begin counting down.
EQUATION 21-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will FOSC
remain in its last state. FCLOCK = -------------------------------------------------
 SSPxADD + 1   4 
An internal signal “Reload” in Figure 21-40 triggers the
value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the
FIGURE 21-40: BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0> SSPxADD<7:0>
SSPM<3:0> Reload Reload

SCLx Control
SSPxCLK BRG Down Counter FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPxADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 21-4: MSSPX CLOCK RATE W/BRG

FCLOCK
FOSC FCY BRG Value
(2 Rollovers of BRG)
16 MHz 4 MHz 09h 400 kHz(1)
16 MHz 4 MHz 0Ch 308 kHz
16 MHz 4 MHz 27h 100 kHz
4 MHz 1 MHz 09h 100 kHz
Note 1: Refer to I/O port electrical and timing specifications in Table 25-3 and Figure 25-7 to ensure the system is
designed to support the I/O timing requirements.

PIC16(L)F1526/7
21.8 Register Definitions: MSSP Control
REGISTER 21-1: SSPxSTAT: SSPx STATUS REGISTER

R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
SMP CKE D/A P S R/W UA BF
bit 7 bit 0
Legend:
bit 7 SMP: SPI Data Input Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C™ mode only:
1 = Enable input logic so that thresholds are compliant with SMBus specification
0 = Disable SMBus specific inputs
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: Stop bit
(I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3 S: Start bit
(I2C mode only. This bit is cleared when the MSSPx module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Idle mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPxADD register
0 = Address does not need to be updated

PIC16(L)F1526/7
REGISTER 21-1: SSPxSTAT: SSPx STATUS REGISTER (CONTINUED)
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPxBUF is full
0 = Receive not complete, SSPxBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty

PIC16(L)F1526/7
REGISTER 21-2: SSPxCON1: SSPx CONTROL REGISTER 1

R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
WCOL SSPxOV SSPEN CKP SSPM<3:0>
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared
bit 7 WCOL: Write Collision Detect bit

Master mode:
1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0 = No collision
Slave mode:
1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6 SSPxOV: Receive Overflow Indicator bit(1)
In SPI mode:
1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPxBUF register (must be cleared in software).
0 = No overflow
2
In I C mode:
1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPxOV is a “don’t care” in Transmit mode
(must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode:
1 = Enables the serial port and configures the SDAx and SCLx pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4 CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C Slave mode:
SCLx release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1101 = Reserved
1100 = Reserved
1011 = I2C firmware controlled Master mode (Slave idle)
1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))(5)
1001 = Reserved
1000 = I2C Master mode, clock = FOSC/(4 * (SSPxADD+1))(4)
0111 = I2C Slave mode, 10-bit address
0110 = I2C Slave mode, 7-bit address
0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin
0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.
2: When enabled, these pins must be properly configured as input or output.
3: When enabled, the SDAx and SCLx pins must be configured as inputs.
4: SSPxADD values of 0, 1 or 2 are not supported for I2C mode.
5: SSPxADD value of ‘0’ is not supported. Use SSPM = 0000 instead.

PIC16(L)F1526/7

R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set
bit 7 GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only)
1 = Acknowledge was not received
0 = Acknowledge was received
bit 5 ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (in I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKx Release Control:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition idle
bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition idle
bit 0 SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).

PIC16(L)F1526/7

R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
bit 7 bit 0
Legend:
bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCLx clock
0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCLx clock
bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4 BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the
SSPxCON1 register is set, and the buffer is not updated
In I2C Master mode and SPI Master mode:
In I2C Slave mode:
1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the
state of the SSPOV bit only if the BF bit = 0.
0 = SSPxBUF is only updated when SSPOV is clear
bit 3 SDAHT: SDAx Hold Time Selection bit (I2C mode only)
1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCLxIF bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the
SSPxCON1 register will be cleared and the SCLx will be held low.
0 = Address holding is disabled
bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit
of the SSPxCON1 register and SCLx is held low.
0 = Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

PIC16(L)F1526/7
REGISTER 21-5: SSPxMSK: SSPx MASK REGISTER

MSK<7:0>
bit 7 bit 0
Legend:
bit 7-1 MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored
REGISTER 21-6: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE)
ADD<7:0>
bit 7 bit 0
Legend:
Master mode:
bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits

SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode — Most Significant Address byte:
bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pat-
tern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode — Least Significant Address byte:
bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:
bit 7-1 ADD<7:1>: 7-bit address

bit 0 Not used: Unused in this mode. Bit state is a “don’t care”.

PIC16(L)F1526/7
22.0 ENHANCED UNIVERSAL These devices typically do not have internal clocks for
baud rate generation and require the external clock
SYNCHRONOUS
signal provided by a master synchronous device.
ASYNCHRONOUS RECEIVER
The EUSART module includes the following capabilities:
TRANSMITTER (EUSART)
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
Note: The PIC16(L)F1526/7 devices have two • One-character output buffer
EUSARTs. Therefore, all information in • Programmable 8-bit or 9-bit character length
this section refers to both EUSART 1 and • Address detection in 9-bit mode
EUSART 2.
• Input buffer overrun error detection
The Enhanced Universal Synchronous Asynchronous • Received character framing error detection
Receiver Transmitter (EUSART) module is a serial I/O • Half-duplex synchronous master
communications peripheral. It contains all the clock
• Half-duplex synchronous slave
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer • Programmable clock and data polarity
independent of device program execution. The The EUSART module implements the following
EUSART, also known as a Serial Communications additional features, making it ideally suited for use in
Interface (SCI), can be configured as a full-duplex Local Interconnect Network (LIN) bus systems:
asynchronous system or half-duplex synchronous • Automatic detection and calibration of the baud rate
system. Full-Duplex mode is useful for
• Wake-up on Break reception
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex • 13-bit Break character transmit
Synchronous mode is intended for communications Block diagrams of the EUSART transmitter and
with peripheral devices, such as A/D or D/A integrated receiver are shown in Figure 22-1 and Figure 22-2.
circuits, serial EEPROMs or other microcontrollers.
FIGURE 22-1: EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXxIE
Interrupt
TXxREG Register TXxIF
8
MSb LSb TXx/CKx pin
(8) 0 Pin Buffer
• • • and Control
Transmit Shift Register (TSR)
TXEN
TRMT
Baud Rate Generator FOSC
÷n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH X 1 1 0 0
BRG16 X 1 0 1 0

PIC16(L)F1526/7
FIGURE 22-2: EUSART RECEIVE BLOCK DIAGRAM
CREN OERR RCIDL
RXx/DTx pin MSb RSR Register LSb

Pin Buffer Data
and Control Recovery
Stop (8) 7 ••• 1 0 START
Baud Rate Generator FOSC RX9

÷n
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH FIFO
X 1 1 0 0 FERR RX9D RCxREG Register
BRG16 X 1 0 1 0
8
Data Bus
RCxIF Interrupt
RCxIE
The operation of the EUSART module is controlled

through three registers:
• Transmit Status and Control (TXxSTA)
• Receive Status and Control (RCxSTA)
• Baud Rate Control (BAUDxCON)
These registers are detailed in Register 22-1,
Register 22-2 and Register 22-3, respectively.
For all modes of EUSART operation, the TRIS control
bits corresponding to the RXx/DTx and TXx/CKx pins
should be set to ‘1’. The EUSART control will
automatically reconfigure the pin from input to output, as
needed.
When the receiver or transmitter section is not enabled
then the corresponding RXx/DTx or TXx/CKx pin may be
used for general purpose input and output.

PIC16(L)F1526/7
22.1 EUSART Asynchronous Mode 22.1.1.2 Transmitting Data
The EUSART transmits and receives data using the A transmission is initiated by writing a character to the
standard non-return-to-zero (NRZ) format. NRZ is TXxREG register. If this is the first character, or the
implemented with two levels: a VOH mark state which previous character has been completely flushed from
represents a ‘1’ data bit, and a VOL space state which the TSR, the data in the TXxREG is immediately
represents a ‘0’ data bit. NRZ refers to the fact that transferred to the TSR register. If the TSR still contains
consecutively transmitted data bits of the same value all or part of a previous character, the new character
stay at the output level of that bit without returning to a data is held in the TXxREG until the Stop bit of the
neutral level between each bit transmission. An NRZ previous character has been transmitted. The pending
transmission port idles in the mark state. Each character character in the TXxREG is then transferred to the TSR
transmission consists of one Start bit followed by eight in one TCY immediately following the Stop bit
or nine data bits and is always terminated by one or transmission. The transmission of the Start bit, data bits
more Stop bits. The Start bit is always a space and the and Stop bit sequence commences immediately
Stop bits are always marks. The most common data following the transfer of the data to the TSR from the
format is 8 bits. Each transmitted bit persists for a period TXxREG.
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate 22.1.1.3 Transmit Data Polarity
frequencies from the system oscillator. See Table 22-5 The polarity of the transmit data can be controlled with
for examples of baud rate configurations. the SCKP bit of the BAUDxCON register. The default
The EUSART transmits and receives the LSb first. The state of this bit is ‘0’ which selects high true transmit
EUSART’s transmitter and receiver are functionally idle and data bits. Setting the SCKP bit to ‘1’ will invert
independent, but share the same data format and baud the transmit data resulting in low true idle and data bits.
rate. Parity is not supported by the hardware, but can The SCKP bit controls transmit data polarity only in
be implemented in software and stored as the ninth Asynchronous mode. In Synchronous mode the SCKP
data bit. bit has a different function.
22.1.1 EUSART ASYNCHRONOUS 22.1.1.4 Transmit Interrupt Flag

TRANSMITTER The TXxIF interrupt flag bit of the PIR1/PIR4 register is
set whenever the EUSART transmitter is enabled and
The EUSART transmitter block diagram is shown in
no character is being held for transmission in the
Figure 22-1. The heart of the transmitter is the serial
TXxREG. In other words, the TXxIF bit is only clear
Transmit Shift Register (TSR), which is not directly
when the TSR is busy with a character and a new
accessible by software. The TSR obtains its data from
character has been queued for transmission in the
the transmit buffer, which is the TXxREG register.
TXxREG. The TXxIF flag bit is not cleared immediately
22.1.1.1 Enabling the Transmitter upon writing TXxREG. TXxIF becomes valid in the
second instruction cycle following the write execution.
The EUSART transmitter is enabled for asynchronous Polling TXxIF immediately following the TXxREG write
operations by configuring the following three control will return invalid results. The TXxIF bit is read-only, it
bits: cannot be set or cleared by software.
• TXEN = 1 The TXxIF interrupt can be enabled by setting the
• SYNC = 0 TXxIE interrupt enable bit of the PIE1/PIE4 register.
• SPEN = 1 However, the TXxIF flag bit will be set whenever the
TXxREG is empty, regardless of the state of TXxIE
All other EUSART control bits are assumed to be in
enable bit.
their default state.
To use interrupts when transmitting data, set the TXxIE
Setting the TXEN bit of the TXxSTA register enables the
bit only when there is more data to send. Clear the
transmitter circuitry of the EUSART. Clearing the SYNC
TXxIE interrupt enable bit upon writing the last
bit of the TXxSTA register configures the EUSART for
character of the transmission to the TXxREG.
asynchronous operation. Setting the SPEN bit of the
RCxSTA register enables the EUSART. The program-
mer must set the corresponding TRIS bit to configure the
TXx/CKx I/O pin as an output. If the TXx/CKx pin is
shared with an analog peripheral, the analog I/O function
must be disabled by clearing the corresponding ANSEL
bit.
Note: The TXxIF transmitter interrupt flag is set
when the TXEN enable bit is set.

PIC16(L)F1526/7
22.1.1.5 TSR Status 22.1.1.7 Asynchronous Transmission Set-up:
The TRMT bit of the TXxSTA register indicates the 1. Initialize the SPxBRGH:SPxBRGL register pair
status of the TSR register. This is a read-only bit. The and the BRGH and BRG16 bits to achieve the
TRMT bit is set when the TSR register is empty and is desired baud rate (see Section 22.4 “EUSART
cleared when a character is transferred to the TSR Baud Rate Generator (BRG)”).
register from the TXxREG. The TRMT bit remains clear 2. Set the RXx/DTx and TXx/CKx TRIS controls to
until all bits have been shifted out of the TSR register. ‘1’.
No interrupt logic is tied to this bit, so the user needs to 3. Enable the asynchronous serial port by clearing
poll this bit to determine the TSR status. the SYNC bit and setting the SPEN bit.
Note: The TSR register is not mapped in data 4. If 9-bit transmission is desired, set the TX9
memory, so it is not available to the user. control bit. A set ninth data bit will indicate that
the 8 Least Significant data bits are an address
22.1.1.6 Transmitting 9-Bit Characters when the receiver is set for address detection.
The EUSART supports 9-bit character transmissions. 5. Set the SCKP control bit if inverted transmit data
When the TX9 bit of the TXxSTA register is set the polarity is desired.
EUSART will shift 9 bits out for each character transmit- 6. Enable the transmission by setting the TXEN
ted. The TX9D bit of the TXxSTA register is the ninth, control bit. This will cause the TXxIF interrupt bit
and Most Significant, data bit. When transmitting 9-bit to be set.
data, the TX9D data bit must be written before writing 7. If interrupts are desired, set the TXxIE interrupt
the 8 Least Significant bits into the TXxREG. All nine enable bit. An interrupt will occur immediately
bits of data will be transferred to the TSR shift register provided that the GIE and PEIE bits of the
immediately after the TXxREG is written. INTCON register are also set.
A special 9-bit Address mode is available for use with 8. If 9-bit transmission is selected, the ninth bit
multiple receivers. See Section 22.1.2.7 “Address should be loaded into the TX9D data bit.
Detection” for more information on the Address mode. 9. Load 8-bit data into the TXxREG register. This
will start the transmission.
FIGURE 22-3: ASYNCHRONOUS TRANSMISSION
Write to TXxREG
Word 1
BRG Output
(Shift Clock)
TXx/CKx pin
Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXxIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
TRMT bit Word 1

Transmit Shift Reg
(Transmit Shift
Reg. Empty Flag)

PIC16(L)F1526/7
FIGURE 22-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXxREG
Word 1 Word 2
BRG Output
(Shift Clock)
TXx/CKx pin Start bit Start bit
bit 0 bit 1 bit 7/8 Stop bit bit 0
TXxIF bit 1 TCY Word 1 Word 2
(Interrupt Reg. Flag)
1 TCY
TRMT bit Word 1 Word 2
(Transmit Shift Transmit Shift Reg
Reg. Empty Flag) Transmit Shift Reg
Note: This timing diagram shows two consecutive transmissions.
TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Register
on page
BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 260
RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 259
SP1BRGL EUSART1 Baud Rate Generator, Low Byte 261*
SP1BRGH EUSART1 Baud Rate Generator, High Byte 261*
TX1REG EUSART1 Transmit Register 250*
TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 258
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous transmission.

PIC16(L)F1526/7
22.1.2 EUSART ASYNCHRONOUS 22.1.2.2 Receiving Data
RECEIVER The receiver data recovery circuit initiates character
The Asynchronous mode would typically be used in reception on the falling edge of the first bit. The first bit,
RS-232 systems. The receiver block diagram is shown also known as the Start bit, is always a zero. The data
in Figure 22-2. The data is received on the RXx/DTx recovery circuit counts one-half bit time to the center of
pin and drives the data recovery block. The data the Start bit and verifies that the bit is still a zero. If it is
recovery block is actually a high-speed shifter not a zero then the data recovery circuit aborts
operating at 16 times the baud rate, whereas the serial character reception, without generating an error, and
Receive Shift Register (RSR) operates at the bit rate. resumes looking for the falling edge of the Start bit. If
When all 8 or 9 bits of the character have been shifted the Start bit zero verification succeeds then the data
in, they are immediately transferred to a two character recovery circuit counts a full bit time to the center of the
First-In-First-Out (FIFO) memory. The FIFO buffering next bit. The bit is then sampled by a majority detect
allows reception of two complete characters and the circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
start of a third character before software must start This repeats until all data bits have been sampled and
servicing the EUSART receiver. The FIFO and RSR shifted into the RSR. One final bit time is measured and
registers are not directly accessible by software. the level sampled. This is the Stop bit, which is always
Access to the received data is via the RCxREG a ‘1’. If the data recovery circuit samples a ‘0’ in the
register. Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
22.1.2.1 Enabling the Receiver character. See Section 22.1.2.4 “Receive Framing
The EUSART receiver is enabled for asynchronous Error” for more information on framing errors.
operation by configuring the following three control bits: Immediately after all data bits and the Stop bit have
• CREN = 1 been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCxIF interrupt
• SYNC = 0
flag bit of the PIR1/PIR4 register is set. The top charac-
• SPEN = 1 ter in the FIFO is transferred out of the FIFO by reading
All other EUSART control bits are assumed to be in the RCxREG register.
their default state.
Note: If the receive FIFO is overrun, no additional
Setting the CREN bit of the RCxSTA register enables characters will be received until the overrun
the receiver circuitry of the EUSART. Clearing the SYNC condition is cleared. See Section 22.1.2.5
bit of the TXxSTA register configures the EUSART for “Receive Overrun Error” for more
asynchronous operation. Setting the SPEN bit of the information on overrun errors.
RCxSTA register enables the EUSART. The
programmer must set the corresponding TRIS bit to
configure the RXx/DTx I/O pin as an input.
Note 1: If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
If the RXx/DTx pin is shared with an analog peripheral
the analog I/O function must be disabled by clearing the
corresponding ANSEL bit.

PIC16(L)F1526/7
22.1.2.3 Receive Interrupts 22.1.2.6 Receiving 9-bit Characters
The RCxIF interrupt flag bit of the PIR1/PIR4 register is The EUSART supports 9-bit character reception. When
set whenever the EUSART receiver is enabled and the RX9 bit of the RCxSTA register is set, the EUSART
there is an unread character in the receive FIFO. The will shift 9 bits into the RSR for each character
RCxIF interrupt flag bit is read-only, it cannot be set or received. The RX9D bit of the RCxSTA register is the
cleared by software. ninth and Most Significant data bit of the top unread
RCxIF interrupts are enabled by setting the following character in the receive FIFO. When reading 9-bit data
bits: from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
• RCxIE interrupt enable bit of the PIE1/PIE4 the RCxREG.
register
• PEIE peripheral interrupt enable bit of the INTCON 22.1.2.7 Address Detection
register A special Address Detection mode is available for use
• GIE global interrupt enable bit of the INTCON when multiple receivers share the same transmission
register line, such as in RS-485 systems. Address detection is
The RCxIF interrupt flag bit will be set when there is an enabled by setting the ADDEN bit of the RCxSTA
unread character in the FIFO, regardless of the state of register.
interrupt enable bits. Address detection requires 9-bit character reception.
When address detection is enabled, only characters
22.1.2.4 Receive Framing Error with the ninth data bit set will be transferred to the
Each character in the receive FIFO buffer has a receive FIFO buffer, thereby setting the RCxIF interrupt
corresponding framing error Status bit. A framing error bit. All other characters will be ignored.
indicates that a Stop bit was not seen at the expected Upon receiving an address character, user software
time. The framing error status is accessed via the determines if the address matches its own. Upon
FERR bit of the RCxSTA register. The FERR bit address match, user software must disable address
represents the status of the top unread character in the detection by clearing the ADDEN bit before the next
receive FIFO. Therefore, the FERR bit must be read Stop bit occurs. When user software detects the end of
before reading the RCxREG. the message, determined by the message protocol
The FERR bit is read-only and only applies to the top used, software places the receiver back into the
unread character in the receive FIFO. A framing error Address Detection mode by setting the ADDEN bit.
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCxSTA register which resets the EUSART.
Clearing the CREN bit of the RCxSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCxREG will not clear the FERR
bit.
22.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCxSTA register is
set. The characters already in the FIFO buffer can be
read but no additional characters will be received until
the error is cleared. The error must be cleared by either
clearing the CREN bit of the RCxSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCxSTA register.

PIC16(L)F1526/7
22.1.2.8 Asynchronous Reception Set-up: 22.1.2.9 9-bit Address Detection Mode Set-up
1. Initialize the SPxBRGH:SPxBRGL register pair This mode would typically be used in RS-485 systems.
and the BRGH and BRG16 bits to achieve the To set up an Asynchronous Reception with Address
desired baud rate (see Section 22.4 “EUSART Detect Enable:
Baud Rate Generator (BRG)”). 1. Initialize the SPxBRGH, SPxBRGL register pair
2. Set the RXx/DTx and TXx/CKx TRIS controls to and the BRGH and BRG16 bits to achieve the
‘1’. desired baud rate (see Section 22.4 “EUSART
3. Enable the serial port by setting the SPEN bit Baud Rate Generator (BRG)”).
and the RXx/DTx pin TRIS bit. The SYNC bit 2. Set the RXx/DTx and TXx/CKx TRIS controls to
must be clear for asynchronous operation. ‘1’.
4. If interrupts are desired, set the RCxIE interrupt 3. Enable the serial port by setting the SPEN bit.
enable bit and set the GIE and PEIE bits of the The SYNC bit must be clear for asynchronous
INTCON register. operation.
5. If 9-bit reception is desired, set the RX9 bit. 4. If interrupts are desired, set the RCxIE interrupt
6. Enable reception by setting the CREN bit. enable bit and set the GIE and PEIE bits of the
7. The RCxIF interrupt flag bit will be set when a INTCON register.
character is transferred from the RSR to the 5. Enable 9-bit reception by setting the RX9 bit.
receive buffer. An interrupt will be generated if 6. Enable address detection by setting the ADDEN
the RCxIE interrupt enable bit was also set. bit.
8. Read the RCxSTA register to get the error flags 7. Enable reception by setting the CREN bit.
and, if 9-bit data reception is enabled, the ninth 8. The RCxIF interrupt flag bit will be set when a
data bit. character with the ninth bit set is transferred
9. Get the received 8 Least Significant data bits from the RSR to the receive buffer. An interrupt
from the receive buffer by reading the RCxREG will be generated if the RCxIE interrupt enable
register. bit was also set.
10. If an overrun occurred, clear the OERR flag by 9. Read the RCxSTA register to get the error flags.
clearing the CREN receiver enable bit. The ninth data bit will always be set.
10. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCxREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 22-5: ASYNCHRONOUS RECEPTION

Start Start Start
RXx/DTx pin bit bit 0 bit 1 bit 7/8 Stop bit bit 0 bit 7/8 Stop bit bit 7/8 Stop
bit bit bit
Rcv Shift
Reg
Rcv Buffer Reg
Word 1 Word 2
RCxREG RCxREG
RCIDL
Read Rcv
Buffer Reg
RCxREG
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third
word, causing the OERR (overrun) bit to be set.

PIC16(L)F1526/7
TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Register
on Page
RC1REG EUSART1 Receive Register 253*
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.

PIC16(L)F1526/7
22.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block
output (HFINTOSC). However, the HFINTOSC
frequency may drift as VDD or temperature changes,
and this directly affects the asynchronous baud rate.
The Auto-Baud Detect feature (refer to section
Section 22.4.1, Auto-Baud Detect) can be used to
compensate for changes in the INTOSC frequency.
There may not be a fine enough resolution when
adjusting the Baud Rate Generator to compensate for
a gradual change in the peripheral clock frequency.
The first (preferred) method uses the OSCTUNE
register to adjust the HFINTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 5.2
“Clock Source Types” for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 22.4.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.

PIC16(L)F1526/7
22.3 Register Definitions: EUSART Control
REGISTER 22-1: TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 CSRC: Clock Source Select bit

Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.

PIC16(L)F1526/7
REGISTER 22-2: RCxSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCxREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC16(L)F1526/7
REGISTER 22-3: BAUDxCON: BAUD RATE CONTROL REGISTER

R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
bit 7 ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmit inverted data to the TXx/CKx pin
0 = Transmit non-inverted data to the TXx/CKx pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care

PIC16(L)F1526/7
22.4 EUSART Baud Rate Generator If the system clock is changed during an active receive
(BRG) operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
The Baud Rate Generator (BRG) is an 8-bit or 16-bit make sure that the receive operation is Idle before
timer that is dedicated to the support of both the changing the system clock.
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the EXAMPLE 22-1: CALCULATING BAUD
BRG16 bit of the BAUDxCON register selects 16-bit RATE ERROR
mode.
For a device with FOSC of 16 MHz, desired baud rate
The SPxBRGH:SPxBRGL register pair determines the of 9600, Asynchronous mode, 8-bit BRG:
period of the free running baud rate timer. In
F OS C
Asynchronous mode the multiplier of the baud rate Desired Baud Rate = --------------------------------------------------------------------------
64  [SPxBRGH:SPxBRG] + 1 
period is determined by both the BRGH bit of the
TXxSTA register and the BRG16 bit of the BAUDxCON Solving for SPxBRGH:SPxBRGL:
register. In Synchronous mode, the BRGH bit is ignored.
F OS C
---------------------------------------------
Example 22-1 provides a sample calculation for deter- Desired Baud Rate
SPxBRGH: SPxBRGL = --------------------------------------------- – 1
mining the desired baud rate, actual baud rate, and 64
baud rate % error. 16000000
------------------------
Typical baud rates and error values for various 9600
= ------------------------ – 1
asynchronous modes have been computed for your 64
convenience and are shown in Table 22-5. It may be =  25.042  = 25
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate 16000000
ActualBaudRate = ---------------------------
64  25 + 1 
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies. = 9615
Writing a new value to the SPxBRGH, SPxBRGL
Calc. Baud Rate – Desired Baud Rate
register pair causes the BRG timer to be reset (or Baud Rate % Error = --------------------------------------------------------------------------------------------
Desired Baud Rate
cleared). This ensures that the BRG does not wait for a
timer overflow before outputting the new baud rate.  9615 – 9600 
= ---------------------------------- = 0.16%
9600
TABLE 22-3: BAUD RATE FORMULAS

Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
0 0 0 8-bit/Asynchronous FOSC/[64 (n+1)]

0 0 1 8-bit/Asynchronous
FOSC/[16 (n+1)]
1 0 x 8-bit/Synchronous FOSC/[4 (n+1)]
1 1 x 16-bit/Synchronous
Legend: x = Don’t care, n = value of SPxBRGH, SPxBRGL register pair

PIC16(L)F1526/7
TABLE 22-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values
on page
Legend: — = unimplemented, read as ‘0’. Shaded bits are not used by the BRG.

PIC16(L)F1526/7
TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
BAUD
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 — — — — — — — — — — — —
1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143
2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71
9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17
10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16
19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8
57.6k — — — 57.60k 0.00 7 — — — 57.60k 0.00 2
115.2k — — — — — — — — — — — —
SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
BAUD
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —
SYNC = 0, BRGH = 1, BRG16 = 0
BAUD FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
300 — — — — — — — — — — — —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5

PIC16(L)F1526/7
TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
SYNC = 0, BRGH = 0, BRG16 = 1
300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303
1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575
2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5
SYNC = 0, BRGH = 0, BRG16 = 1
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —

PIC16(L)F1526/7
TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215
1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303
2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151
9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287
10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264
19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143
57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47
115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —

PIC16(L)F1526/7
22.4.1 AUTO-BAUD DETECT 1/8th the BRG base clock rate. The resulting byte mea-
surement is the average bit time when clocked at full
The EUSART module supports automatic detection
speed.
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the Note 1: If the WUE bit is set with the ABDEN bit,
BRG is reversed. Rather than the BRG clocking the auto-baud detection will occur on the byte
incoming RXx signal, the RXx signal is timing the BRG. following the Break character (see
The Baud Rate Generator is used to time the period of Section 22.4.3 “Auto-Wake-up on
a received 55h (ASCII “U”) which is the Sync character Break”).
for the LIN bus. The unique feature of this character is 2: It is up to the user to determine that the
that it has five rising edges including the Stop bit edge. incoming character baud rate is within the
Setting the ABDEN bit of the BAUDxCON register range of the selected BRG clock source.
starts the auto-baud calibration sequence Some combinations of oscillator frequency
(Figure 22.4.2). While the ABD sequence takes place, and EUSART baud rates are not possible.
the EUSART state machine is held in Idle. On the first 3: During the auto-baud process, the
rising edge of the receive line, after the Start bit, the auto-baud counter starts counting at 1.
SPxBRGL begins counting up using the BRG counter Upon completion of the auto-baud
clock as shown in Table 22-6. The fifth rising edge will sequence, to achieve maximum accu-
occur on the RXx/DTx pin at the end of the eighth bit racy, subtract 1 from the
period. At that time, an accumulated value totaling the SPxBRGH:SPxBRGL register pair.
proper BRG period is left in the SPxBRGH:SPxBRGL
register pair, the ABDEN bit is automatically cleared,
and the RCxIF interrupt flag is set. A read operation on TABLE 22-6: BRG COUNTER CLOCK
the RCxREG needs to be performed to clear the RCxIF RATES
interrupt. RCxREG content should be discarded. When BRG Base BRG ABD
calibrating for modes that do not use the SPxBRGH BRG16 BRGH
Clock Clock
register the user can verify that the SPxBRGL register
did not overflow by checking for 00h in the SPxBRGH 0 0 FOSC/64 FOSC/512
register. 0 1 FOSC/16 FOSC/128
The BRG auto-baud clock is determined by the BRG16
1 0 FOSC/16 FOSC/128
and BRGH bits as shown in Table 22-6. During ABD,
both the SPxBRGH and SPxBRGL registers are used 1 1 FOSC/4 FOSC/32
as a 16-bit counter, independent of the BRG16 bit set- Note: During the ABD sequence, SPxBRGL and
ting. While calibrating the baud rate period, the SPxBRGH registers are both used as a
SPxBRGH and SPxBRGL registers are clocked at 16-bit counter, independent of BRG16
setting.
FIGURE 22-6: AUTOMATIC BAUD RATE CALIBRATION
BRG Value XXXXh 0000h 001Ch

Edge #1 Edge #2 Edge #3 Edge #4 Edge #5
RXx/DTx pin Start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit
BRG Clock
Set by User Auto Cleared

ABDEN bit
RCIDL
RCxIF bit
(Interrupt)
Read
RCxREG
SPxBRGL XXh 1Ch
SPxBRGH XXh 00h
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

PIC16(L)F1526/7
22.4.2 AUTO-BAUD OVERFLOW 22.4.3.1 Special Considerations
During the course of automatic baud detection, the Break Character
ABDOVF bit of the BAUDxCON register will be set if To avoid character errors or character fragments during
the baud rate counter overflows before the fifth rising a wake-up event, the wake-up character must be all
edge is detected on the RX pin. The ABDOVF bit indi- zeros.
cates that the counter has exceeded the maximum
count that can fit in the 16 bits of the When the wake-up is enabled the function works
SPxBRGH:SPxBRGL register pair. The overflow condi- independent of the low time on the data stream. If the
tion will set the RCIF flag. The counter continues to WUE bit is set and a valid non-zero character is
count until the fifth rising edge is detected on the RX received, the low time from the Start bit to the first rising
pin. The RCIDL bit will remain false (‘0’) until the fifth edge will be interpreted as the wake-up event. The
rising edge at which time the RCIDL bit will be set. If the remaining bits in the character will be received as a
RCREG is read after the overflow occurs but before the fragmented character and subsequent characters can
fifth rising edge, then the fifth rising edge will set the result in framing or overrun errors.
RCIF again. Therefore, the initial character in the transmission must
Terminating the auto-baud process early to clear an be all ‘0’s. This must be 10 or more bit times, 13-bit
overflow condition will prevent proper detection of the times recommended for LIN bus, or any number of bit
sync character fifth rising edge. If any falling edges of times for standard RS-232 devices.
the sync character have not yet occurred when the Oscillator Startup Time
ABDEN bit is cleared then those will be falsely detected
Oscillator start-up time must be considered, especially
as Start bits. The following steps are recommended to
in applications using oscillators with longer start-up
clear the overflow condition:
intervals (i.e., LP, XT or HS mode). The Sync Break (or
1. Read RCREG to clear RCIF wake-up signal) character must be of sufficient length,
2. If RCIDL is zero then wait for RCIF and repeat and be followed by a sufficient interval, to allow enough
step 1. time for the selected oscillator to start and provide
3. Clear the ABDOVF bit. proper initialization of the EUSART.
WUE Bit
22.4.3 AUTO-WAKE-UP ON BREAK
The wake-up event causes a receive interrupt by
During Sleep mode, all clocks to the EUSART are setting the RCxIF bit. The WUE bit is cleared by
suspended. Because of this, the Baud Rate Generator hardware by a rising edge on RXx/DTx. The interrupt
is inactive and a proper character reception cannot be condition is then cleared by software by reading the
performed. The Auto-Wake-up feature allows the RCxREG register and discarding its contents.
controller to wake-up due to activity on the RXx/DTx
To ensure that no actual data is lost, check the RCIDL
line. This feature is available only in Asynchronous
bit to verify that a receive operation is not in process
mode.
before setting the WUE bit. If a receive operation is not
The Auto-Wake-up feature is enabled by setting the occurring, the WUE bit may then be set just prior to
WUE bit of the BAUDxCON register. Once set, the entering the Sleep mode.
normal receive sequence on RXx/DTx is disabled, and
the EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RXx/DTx line. (This coincides with the start of a Sync
Break or a wake-up signal character for the LIN
protocol.)
The EUSART module generates an RCxIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 22-7), and asynchronously if
the device is in Sleep mode (Figure 22-8). The interrupt
condition is cleared by reading the RCxREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RXx line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.

PIC16(L)F1526/7
FIGURE 22-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Bit set by user Auto Cleared
WUE bit
RXx/DTx Line
RCxIF
Cleared due to User Read of RCxREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 22-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4

OSC1
Bit Set by User Auto Cleared
WUE bit
RXx/DTx Line Note 1

RCxIF
Cleared due to User Read of RCxREG
Sleep Command Executed Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.

PIC16(L)F1526/7
22.4.4 BREAK CHARACTER SEQUENCE When the TXxREG becomes empty, as indicated by
the TXxIF, the next data byte can be written to TXxREG.
The EUSART module has the capability of sending the
special Break character sequences that are required by
22.4.5 RECEIVING A BREAK CHARACTER
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit. The Enhanced EUSART module can receive a Break
character in two ways.
To send a Break character, set the SENDB and TXEN
bits of the TXxSTA register. The Break character trans- The first method to detect a Break character uses the
mission is then initiated by a write to the TXxREG. The FERR bit of the RCxSTA register and the Received
value of data written to TXxREG will be ignored and all data as indicated by RCxREG. The Baud Rate
‘0’s will be transmitted. Generator is assumed to have been initialized to the
expected baud rate.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user A Break character has been received when;
to preload the transmit FIFO with the next transmit byte • RCxIF bit is set
following the Break character (typically, the Sync • FERR bit is set
character in the LIN specification).
• RCxREG = 00h
The TRMT bit of the TXxSTA register indicates when the
The second method uses the Auto-Wake-up feature
transmit operation is active or Idle, just as it does during
described in Section 22.4.3 “Auto-Wake-up on
normal transmission. See Figure 22-9 for the timing of
Break”. By enabling this feature, the EUSART will
the Break character sequence.
sample the next two transitions on RXx/DTx, cause an
22.4.4.1 Break and Sync Transmit Sequence RCxIF interrupt, and receive the next data byte
followed by another interrupt.
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud Note that following a Break character, the user will
Sync byte. This sequence is typical of a LIN bus typically want to enable the Auto-Baud Detect feature.
master. For both methods, the user can set the ABDEN bit of
the BAUDxCON register before placing the EUSART in
1. Configure the EUSART for the desired mode. Sleep mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXxREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXxREG to load the Sync charac-
ter into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
FIGURE 22-9: SEND BREAK CHARACTER SEQUENCE
Write to TXxREG
Dummy Write
BRG Output
(Shift Clock)
TXx/CKx (pin) Start bit bit 0 bit 1 bit 11 Stop bit

Break
TXxIF bit
(Transmit
interrupt Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)

PIC16(L)F1526/7
22.5 EUSART Synchronous Mode 22.5.1.2 Clock Polarity
Synchronous serial communications are typically used A clock polarity option is provided for Microwire
in systems with a single master and one or more compatibility. Clock polarity is selected with the SCKP
slaves. The master device contains the necessary bit of the BAUDxCON register. Setting the SCKP bit
circuitry for baud rate generation and supplies the clock sets the clock Idle state as high. When the SCKP bit is
for all devices in the system. Slave devices can take set, the data changes on the falling edge of each clock
advantage of the master clock by eliminating the and is sampled on the rising edge of each clock.
internal clock generation circuitry. Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
There are two signal lines in Synchronous mode: a edge of each clock and is sampled on the falling edge
bidirectional data line and a clock line. Slaves use the of each clock.
external clock supplied by the master to shift the serial
data into and out of their respective receive and 22.5.1.3 Synchronous Master Transmission
transmit shift registers. Since the data line is
Data is transferred out of the device on the RXx/DTx
bidirectional, synchronous operation is half-duplex
pin. The RXx/DTx and TXx/CKx pin output drivers are
only. Half-duplex refers to the fact that master and
automatically enabled when the EUSART is configured
slave devices can receive and transmit data but not
for synchronous master transmit operation.
both simultaneously. The EUSART can operate as
either a master or slave device. A transmission is initiated by writing a character to the
TXxREG register. If the TSR still contains all or part of
Start and Stop bits are not used in synchronous
a previous character the new character data is held in
transmissions.
the TXxREG until the last bit of the previous character
22.5.1 SYNCHRONOUS MASTER MODE has been transmitted. If this is the first character, or the
previous character has been completely flushed from
The following bits are used to configure the EUSART the TSR, the data in the TXxREG is immediately trans-
for Synchronous Master operation: ferred to the TSR. The transmission of the character
• SYNC = 1 commences immediately following the transfer of the
• CSRC = 1 data to the TSR from the TXxREG.
• SREN = 0 (for transmit); SREN = 1 (for receive) Each data bit changes on the leading edge of the
• CREN = 0 (for transmit); CREN = 1 (for receive) master clock and remains valid until the subsequent
leading clock edge.
• SPEN = 1
Setting the SYNC bit of the TXxSTA register configures Note: The TSR register is not mapped in data
the device for synchronous operation. Setting the CSRC memory, so it is not available to the user.
bit of the TXxSTA register configures the device as a
master. Clearing the SREN and CREN bits of the
RCxSTA register ensures that the device is in the
Transmit mode, otherwise the device will be configured
to receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART. If the RXx/DTx or TXx/CKx pins
are shared with an analog peripheral the analog I/O
functions must be disabled by clearing the corresponding
ANSEL bits.
The TRIS bits corresponding to the RXx/DTx and
TXx/CKx pins should be set.
22.5.1.1 Master Clock

Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a master transmits the clock on the TXx/CKx line. The
TXx/CKx pin output driver is automatically enabled when
the EUSART is configured for synchronous transmit or
receive operation. Serial data bits change on the leading
edge to ensure they are valid at the trailing edge of each
clock. One clock cycle is generated for each data bit.
Only as many clock cycles are generated as there are
data bits.

PIC16(L)F1526/7
22.5.1.4 Synchronous Master Transmission 4. Disable Receive mode by clearing bits SREN
Set-up: and CREN.
1. Initialize the SPxBRGH, SPxBRGL register pair 5. Enable Transmit mode by setting the TXEN bit.
and the BRGH and BRG16 bits to achieve the 6. If 9-bit transmission is desired, set the TX9 bit.
desired baud rate (see Section 22.4 “EUSART 7. If interrupts are desired, set the TXxIE, GIE and
Baud Rate Generator (BRG)”). PEIE interrupt enable bits.
2. Set the RXx/DTx and TXx/CKx TRIS controls to 8. If 9-bit transmission is selected, the ninth bit
‘1’. should be loaded in the TX9D bit.
3. Enable the synchronous master serial port by 9. Start transmission by loading data to the TXx-
setting bits SYNC, SPEN and CSRC. Set the REG register.
TRIS bits corresponding to the RXx/DTx and
TXx/CKx I/O pins.
FIGURE 22-10: SYNCHRONOUS TRANSMISSION

RXx/DTx
pin bit 0 bit 1 bit 2 bit 7 bit 0 bit 1 bit 7
Word 1 Word 2
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
TXxREG Reg Write Word 1 Write Word 2
TXxIF bit
(Interrupt Flag)
TRMT bit
‘1’ ‘1’
TXEN bit
Note: Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 22-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RXx/DTx pin bit 0 bit 1 bit 2 bit 6 bit 7
TXx/CKx pin
Write to
TXxREG reg
TXxIF bit
TRMT bit
TXEN bit

PIC16(L)F1526/7
TABLE 22-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

TRANSMISSION
Register
on Page
(1)
TRISG — — — TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 132
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master transmission.
* Page provides register information
Note 1: Unimplemented, read as ‘1’..

PIC16(L)F1526/7
22.5.1.5 Synchronous Master Reception If the overrun occurred when the CREN bit is set then
the error condition is cleared by either clearing the
Data is received at the RXx/DTx pin. The RXx/DTx pin
CREN bit of the RCxSTA register or by clearing the
output driver must be disabled by setting the
SPEN bit which resets the EUSART.
corresponding TRIS bits when the EUSART is
configured for synchronous master receive operation.
22.5.1.8 Receiving 9-bit Characters
In Synchronous mode, reception is enabled by setting
The EUSART supports 9-bit character reception. When
either the Single Receive Enable bit (SREN of the
the RX9 bit of the RCxSTA register is set the EUSART
RCxSTA register) or the Continuous Receive Enable
will shift 9-bits into the RSR for each character
bit (CREN of the RCxSTA register).
received. The RX9D bit of the RCxSTA register is the
When SREN is set and CREN is clear, only as many ninth, and Most Significant, data bit of the top unread
clock cycles are generated as there are data bits in a character in the receive FIFO. When reading 9-bit data
single character. The SREN bit is automatically cleared from the receive FIFO buffer, the RX9D data bit must
at the completion of one character. When CREN is set, be read before reading the 8 Least Significant bits from
clocks are continuously generated until CREN is the RCxREG.
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac- 22.5.1.9 Synchronous Master Reception
ter is discarded. If SREN and CREN are both set, then Set-up:
SREN is cleared at the completion of the first character
1. Initialize the SPxBRGH, SPxBRGL register pair
and CREN takes precedence.
for the appropriate baud rate. Set or clear the
To initiate reception, set either SREN or CREN. Data is BRGH and BRG16 bits, as required, to achieve
sampled at the RXx/DTx pin on the trailing edge of the the desired baud rate.
TXx/CKx clock pin and is shifted into the Receive Shift 2. Set the RXx/DTx and TXx/CKx TRIS controls to
Register (RSR). When a complete character is ‘1’.
received into the RSR, the RCxIF bit is set and the
3. Enable the synchronous master serial port by
character is automatically transferred to the two
setting bits SYNC, SPEN and CSRC. Disable
character receive FIFO. The Least Significant eight bits
RXx/DTx and TXx/CKx output drivers by setting
of the top character in the receive FIFO are available in
the corresponding TRIS bits.
RCxREG. The RCxIF bit remains set as long as there
are un-read characters in the receive FIFO. 4. Ensure bits CREN and SREN are clear.
5. If using interrupts, set the GIE and PEIE bits of
22.5.1.6 Slave Clock the INTCON register and set RCxIE.
Synchronous data transfers use a separate clock line, 6. If 9-bit reception is desired, set bit RX9.
which is synchronous with the data. A device configured 7. Start reception by setting the SREN bit or for
as a slave receives the clock on the TXx/CKx line. The continuous reception, set the CREN bit.
TXx/CKx pin output driver must be disabled by setting 8. Interrupt flag bit RCxIF will be set when recep-
the associated TRIS bit when the device is configured tion of a character is complete. An interrupt will
for synchronous slave transmit or receive operation. be generated if the enable bit RCxIE was set.
Serial data bits change on the leading edge to ensure 9. Read the RCxSTA register to get the ninth bit (if
they are valid at the trailing edge of each clock. One data enabled) and determine if any error occurred
bit is transferred for each clock cycle. Only as many during reception.
clock cycles should be received as there are data bits.
10. Read the 8-bit received data by reading the
RCxREG register.
22.5.1.7 Receive Overrun Error
11. If an overrun error occurs, clear the error by
The receive FIFO buffer can hold two characters. An either clearing the CREN bit of the RCxSTA
overrun error will be generated if a third character, in its register or by clearing the SPEN bit which resets
entirety, is received before RCxREG is read to access the EUSART.
the FIFO. When this happens the OERR bit of the
RCxSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCxREG.

PIC16(L)F1526/7
FIGURE 22-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RXx/DTx
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit ‘0’ ‘0’
RCxIF bit
(Interrupt)
Read
RCxREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 22-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION
Register
on Page
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.

PIC16(L)F1526/7
22.5.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXxREG and then the
SLEEP instruction is executed, the following will occur:
The following bits are used to configure the EUSART
for Synchronous slave operation: 1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXxREG
• CSRC = 0
register.
• SREN = 0 (for transmit); SREN = 1 (for receive)
3. The TXxIF bit will not be set.
• CREN = 0 (for transmit); CREN = 1 (for receive)
4. After the first character has been shifted out of
• SPEN = 1 TSR, the TXxREG register will transfer the
Setting the SYNC bit of the TXxSTA register configures second character to the TSR and the TXxIF bit
the device for synchronous operation. Clearing the will now be set.
CSRC bit of the TXxSTA register configures the device as 5. If the PEIE and TXxIE bits are set, the interrupt
a slave. Clearing the SREN and CREN bits of the will wake the device from Sleep and execute the
RCxSTA register ensures that the device is in the next instruction. If the GIE bit is also set, the
Transmit mode, otherwise the device will be configured to program will call the Interrupt Service Routine.
receive. Setting the SPEN bit of the RCxSTA register
enables the EUSART. If the RXx/DTx or TXx/CKx pins 22.5.2.2 Synchronous Slave Transmission
are shared with an analog peripheral the analog I/O Set-up:
functions must be disabled by clearing the corresponding
1. Set the SYNC and SPEN bits and clear the
ANSEL bits.
CSRC bit.
RXx/DTx and TXx/CKx pin output drivers must be 2. Set the RXx/DTx and TXx/CKx TRIS controls to
disabled by setting the corresponding TRIS bits. ‘1’.
22.5.2.1 EUSART Synchronous Slave 3. Clear the CREN and SREN bits.
Transmit 4. If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
The operation of the Synchronous Master and Slave TXxIE bit.
modes are identical (see Section 22.5.1.3
5. If 9-bit transmission is desired, set the TX9 bit.
“Synchronous Master Transmission”), except in the
case of the Sleep mode. 6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant 8 bits to the TXxREG register.

PIC16(L)F1526/7
TABLE 22-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

TRANSMISSION
Register
on Page
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave transmission.

PIC16(L)F1526/7
22.5.2.3 EUSART Synchronous Slave 22.5.2.4 Synchronous Slave Reception
Reception Set-up:
The operation of the Synchronous Master and Slave 1. Set the SYNC and SPEN bits and clear the
modes is identical (Section 22.5.1.5 “Synchronous CSRC bit.
Master Reception”), with the following exceptions: 2. Set the RXx/DTx and TXx/CKx TRIS controls to
• Sleep ‘1’.
• CREN bit is always set, therefore the receiver is 3. If using interrupts, ensure that the GIE and PEIE
never Idle bits of the INTCON register are set and set the
• SREN bit, which is a “don’t care” in Slave mode RCxIE bit.
4. If 9-bit reception is desired, set the RX9 bit.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the 5. Set the CREN bit to enable reception.
word is received, the RSR register will transfer the data 6. The RCxIF bit will be set when reception is
to the RCxREG register. If the RCxIE enable bit is set, complete. An interrupt will be generated if the
the interrupt generated will wake the device from Sleep RCxIE bit was set.
and execute the next instruction. If the GIE bit is also 7. If 9-bit mode is enabled, retrieve the Most
set, the program will branch to the interrupt vector. Significant bit from the RX9D bit of the RCxSTA
register.
8. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCxREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCxSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Register
on Page
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous slave reception.

PIC16(L)F1526/7
23.0 IN-CIRCUIT SERIAL 23.3 Common Programming Interfaces
PROGRAMMING™ (ICSP™) Connection to a target device is typically done through
ICSP™ programming allows customers to manufacture an ICSP™ header. A commonly found connector on
circuit boards with unprogrammed devices. Programming development tools is the RJ-11 in the 6P6C (6 pin, 6
can be done after the assembly process, allowing the connector) configuration. See Figure 23-1.
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™ FIGURE 23-1: ICD RJ-11 STYLE
programming: CONNECTOR INTERFACE
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
ICSPDAT
• VSS
2 4 6 NC
VDD
In Program/Verify mode the program memory, user IDs ICSPCLK
and the Configuration Words are programmed through 1 3 5
Target
serial communications. The ICSPDAT pin is a bidirec- VPP/MCLR PC Board
VSS
tional I/O used for transferring the serial data and the Bottom Side
ICSPCLK pin is the clock input. For more information on
ICSP™ refer to the “PIC16F/LF151X/152X Memory Pro-
gramming Specification” (DS41422). Pin Description*
1 = VPP/MCLR
23.1 High-Voltage Programming Entry 2 = VDD Target
Mode 3 = VSS (ground)
The device is placed into High-Voltage Programming 4 = ICSPDAT
Entry mode by holding the ICSPCLK and ICSPDAT 5 = ICSPCLK

pins low then raising the voltage on MCLR/VPP to VIHH. 6 = No Connect
23.2 Low-Voltage Programming Entry

Mode Another connector often found in use with the PICkit™
The Low-Voltage Programming Entry mode allows the programmers is a standard 6-pin header with 0.1 inch
PIC® Flash MCUs devices to be programmed using spacing. Refer to Figure 23-2.
VDD only, without high voltage. When the LVP bit of
Configuration Words is set to ‘1’, the low-voltage ICSP
programming entry is enabled. To disable the
Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 6.4 “Low-Power
Brown-Out Reset (LPBOR)” for more information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.

PIC16(L)F1526/7
FIGURE 23-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
* The 6-pin header (0.100" spacing) accepts 0.025" square pins.
For additional interface recommendations, refer to your

specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 23-3 for more
information.
FIGURE 23-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming VDD Device to be
Signals Programmed
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
* Isolation devices (as required).

PIC16(L)F1526/7
24.0 INSTRUCTION SET SUMMARY 24.1 Read-Modify-Write Operations
Each instruction is a 14-bit word containing the opera- Any instruction that specifies a file register as part of
tion code (opcode) and all required operands. The the instruction performs a Read-Modify-Write (R-M-W)
opcodes are broken into three broad categories. operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
• Byte Oriented
tion, or the destination designator ‘d’. A read operation
• Bit Oriented is performed on a register even if the instruction writes
• Literal and Control to that register.
The literal and control category contains the most var-
ied instruction word format. TABLE 24-1: OPCODE FIELD
Table 24-3 lists the instructions recognized by the DESCRIPTIONS
MPASMTM assembler. Field Description
All instructions are executed within a single instruction f Register file address (0x00 to 0x7F)
cycle, with the following exceptions, which may take
W Working register (accumulator)
two or three cycles:
b Bit address within an 8-bit file register
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two k Literal field, constant data or label
cycles (RETURN, RETLW, RETFIE) x Don’t care location (= 0 or 1).
• Program branching takes two cycles (GOTO, BRA, The assembler will generate code with x = 0.
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) It is the recommended form of use for
• One additional instruction cycle will be used when compatibility with all Microchip software tools.
any instruction references an indirect file register d Destination select; d = 0: store result in W,
and the file select register is pointing to program d = 1: store result in file register f.
memory. Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for n FSR or INDF number. (0-1)
an oscillator frequency of 4 MHz, this gives a nominal mm Pre-post increment-decrement mode
instruction execution rate of 1 MHz.
selection
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a TABLE 24-2: ABBREVIATION
hexadecimal digit.
DESCRIPTIONS
Field Description
PC Program Counter
TO Time-out bit
C Carry bit
DC Digit carry bit
Z Zero bit
PD Power-down bit

PIC16(L)F1526/7
FIGURE 24-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13 8 7 6 0
OPCODE d f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations

13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address

f = 7-bit file register address
Literal and control operations

General
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
CALL and GOTO instructions only

13 11 10 0
OPCODE k (literal)
MOVLP instruction only

13 7 6 0
OPCODE k (literal)
MOVLB instruction only

13 5 4 0
OPCODE k (literal)
BRA instruction only

13 9 8 0
OPCODE k (literal)
FSR Offset instructions

13 7 6 5 0
OPCODE n k (literal)
n = appropriate FSR
FSR Increment instructions

13 3 2 1 0
OPCODE n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13 0
OPCODE

PIC16(L)F1526/7
TABLE 24-3: INSTRUCTION SET

Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 2
ADDWFC f, d Add with Carry W and f 1 11 1101 dfff ffff C, DC, Z 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 2
ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2
LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2
LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0000 00xx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 2
INCF f, d Increment f 1 00 1010 dfff ffff Z 2
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 2
MOVWF f Move W to f 1 00 0000 1fff ffff 2
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 2
SUBWFB f, d Subtract with Borrow W from f 1 11 1011 dfff ffff C, DC, Z 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 2
BYTE ORIENTED SKIP OPERATIONS
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2

INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 2

BSF f, b Bit Set f 1 01 01bb bfff ffff 2
BIT-ORIENTED SKIP OPERATIONS

BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 1, 2
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 1, 2
LITERAL OPERATIONS
ADDLW k Add literal and W 1 11 1110 kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLB k Move literal to BSR 1 00 0000 001k kkkk
MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk
MOVLW k Move literal to W 1 11 0000 kkkk kkkk
SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.

PIC16(L)F1526/7
TABLE 24-3: INSTRUCTION SET (CONTINUED)
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
CONTROL OPERATIONS
BRA k Relative Branch 2 11 001k kkkk kkkk
BRW – Relative Branch with W 2 00 0000 0000 1011
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CALLW – Call Subroutine with W 2 00 0000 0000 1010
GOTO k Go to address 2 10 1kkk kkkk kkkk
RETFIE k Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 0100 kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
INHERENT OPERATIONS
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
NOP – No Operation 1 00 0000 0000 0000
OPTION – Load OPTION_REG register with W 1 00 0000 0110 0010
RESET – Software device Reset 1 00 0000 0000 0001
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
TRIS f Load TRIS register with W 1 00 0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k Add Literal k to FSRn 1 11 0001 0nkk kkkk
MOVIW n mm Move Indirect FSRn to W with pre/post inc/dec 1 00 0000 0001 0nmm Z 2, 3
modifier, mm
k[n] Move INDFn to W, Indexed Indirect. 1 11 1111 0nkk kkkk Z 2
MOVWI n mm Move W to Indirect FSRn with pre/post inc/dec 1 00 0000 0001 1nmm 2, 3
modifier, mm
k[n] Move W to INDFn, Indexed Indirect. 1 11 1111 1nkk kkkk 2
Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.

PIC16(L)F1526/7
24.2 Instruction Descriptions
ADDFSR Add Literal to FSRn ANDLW AND literal with W

Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW k
Operands: -32  k  31 Operands: 0  k  255
n  [ 0, 1] Operation: (W) .AND. (k)  (W)
Operation: FSR(n) + k  FSR(n)
Status Affected: Z
Status Affected: None Description: The contents of W register are
Description: The signed 6-bit literal ‘k’ is added to AND’ed with the 8-bit literal ‘k’. The
the contents of the FSRnH:FSRnL result is placed in the W register.
register pair.
FSRn is limited to the range 0000h -

FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ADDLW Add literal and W ANDWF AND W with f

Syntax: [ label ] ADDLW k Syntax: [ label ] ANDWF f,d
Operands: 0  k  255 Operands: 0  f  127
d 0,1
Operation: (W) + k  (W)
Operation: (W) .AND. (f)  (destination)
Status Affected: C, DC, Z
Status Affected: Z
Description: The contents of the W register are
added to the 8-bit literal ‘k’ and the Description: AND the W register with register ‘f’. If
result is placed in the W register. ‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ADDWF Add W and f ASRF Arithmetic Right Shift

Syntax: [ label ] ADDWF f,d Syntax: [ label ] ASRF f {,d}
Operands: 0  f  127 Operands: 0  f  127
d 0,1 d [0,1]
Operation: (W) + (f)  (destination) Operation: (f<7>) dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Description: Add the contents of the W register
Status Affected: C, Z
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the Description: The contents of register ‘f’ are shifted
result is stored back in register ‘f’. one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in reg-
ister ‘f’.
ADDWFC ADD W and CARRY bit to f register f C
Syntax: [ label ] ADDWFC f {,d}
Operands: 0  f  127
d [0,1]
Operation: (W) + (f) + (C)  dest
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.

PIC16(L)F1526/7
BCF Bit Clear f BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b

0b7 0b7
Operation: 0  (f<b>) Operation: skip if (f<b>) = 0
Status Affected: None Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BRA Relative Branch BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BRA label Syntax: [ label ] BTFSS f,b
[ label ] BRA $+k Operands: 0  f  127
Operands: -256  label - PC + 1  255 0b<7
-256  k  255 Operation: skip if (f<b>) = 1
Operation: (PC) + 1 + k  PC Status Affected: None
Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Description: Add the signed 9-bit literal ‘k’ to the instruction is executed.
PC. Since the PC will have incre- If bit ‘b’ is ‘1’, then the next
mented to fetch the next instruction, instruction is discarded and a NOP is
the new address will be PC + 1 + k. executed instead, making this a
This instruction is a 2-cycle instruc- 2-cycle instruction.
tion. This branch has a limited range.
BRW Relative Branch with W

Syntax: [ label ] BRW
Operands: None
Operation: (PC) + (W)  PC
Status Affected: None
Description: Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a 2-cycle instruc-
tion.
BSF Bit Set f

Syntax: [ label ] BSF f,b
0b7
Operation: 1  (f<b>)
Description: Bit ‘b’ in register ‘f’ is set.

PIC16(L)F1526/7
CALL Call Subroutine CLRWDT Clear Watchdog Timer

Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT
Operands: 0  k  2047 Operands: None
Operation: (PC)+ 1 TOS, Operation: 00h  WDT
k  PC<10:0>, 0  WDT prescaler,
(PCLATH<6:3>)  PC<14:11> 1  TO
Status Affected: None 1  PD
Description: Call Subroutine. First, return address Status Affected: TO, PD
(PC + 1) is pushed onto the stack. Description: CLRWDT instruction resets the Watch-
The eleven-bit immediate address is dog Timer. It also resets the prescaler
loaded into PC bits <10:0>. The upper of the WDT.
bits of the PC are loaded from Status bits TO and PD are set.
PCLATH. CALL is a 2-cycle instruc-
tion.
CALLW Subroutine Call With W COMF Complement f
Syntax: [ label ] CALLW Syntax: [ label ] COMF f,d
Operands: None Operands: 0  f  127

d  [0,1]
Operation: (PC) +1  TOS,
(W)  PC<7:0>, Operation: (f)  (destination)
(PCLATH<6:0>) PC<14:8> Status Affected: Z
Description: The contents of register ‘f’ are com-
Status Affected: None plemented. If ‘d’ is ‘0’, the result is
Description: Subroutine call with W. First, the stored in W. If ‘d’ is ‘1’, the result is
return address (PC + 1) is pushed stored back in register ‘f’.
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a 2-cycle
instruction.
CLRF Clear f DECF Decrement f

Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d
d  [0,1]
Operation: 00h  (f)
1Z Operation: (f) - 1  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are cleared Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
and the Z bit is set. result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h  (W)
1Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z) is
set.

PIC16(L)F1526/7
DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
d  [0,1] d  [0,1]
Operation: (f) - 1  (destination); Operation: (f) + 1  (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are decre- Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’. is placed back in register ‘f’.
If the result is ‘1’, the next instruction is If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a executed. If the result is ‘0’, a NOP is
NOP is executed instead, making it a executed instead, making it a 2-cycle
2-cycle instruction. instruction.
GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0  k  2047 Operands: 0  k  255
Operation: k  PC<10:0> Operation: (W) .OR. k  (W)
PCLATH<6:3>  PC<14:11> Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. The OR’ed with the 8-bit literal ‘k’. The
eleven-bit immediate value is loaded result is placed in the W register.
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a 2-cycle instruction.
INCF Increment f IORWF Inclusive OR W with f

Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d
d  [0,1] d  [0,1]
Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are incre- Description: Inclusive OR the W register with regis-
mented. If ‘d’ is ‘0’, the result is placed ter ‘f’. If ‘d’ is ‘0’, the result is placed in
in the W register. If ‘d’ is ‘1’, the result the W register. If ‘d’ is ‘1’, the result is
is placed back in register ‘f’. placed back in register ‘f’.

PIC16(L)F1526/7
LSLF Logical Left Shift MOVF Move f

Syntax: [ label ] LSLF f {,d} Syntax: [ label ] MOVF f,d
d [0,1] d  [0,1]
Operation: (f<7>)  C Operation: (f)  (dest)
(f<6:0>)  dest<7:1>
Status Affected: Z
0  dest<0>
Description: The contents of register f is moved to
a destination dependent upon the
Description: The contents of register ‘f’ are shifted status of d. If d = 0,destination is W
one bit to the left through the Carry flag. register. If d = 1, the destination is file
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, register f itself. d = 1 is useful to test a
the result is placed in W. If ‘d’ is ‘1’, the file register since status flag Z is
result is stored back in register ‘f’. affected.
C register f 0 Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
LSRF Logical Right Shift
W = value in FSR register
Syntax: [ label ] LSRF f {,d} Z = 1
d [0,1]
Operation: 0  dest<7>
(f<7:1>)  dest<6:0>,
(f<0>)  C,
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0 register f C

PIC16(L)F1526/7
MOVIW Move INDFn to W MOVLP Move literal to PCLATH

Syntax: [ label ] MOVIW ++FSRn Syntax: [ label ] MOVLP k
[ label ] MOVIW --FSRn Operands: 0  k  127
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-- Operation: k  PCLATH
[ label ] MOVIW k[FSRn] Status Affected: None
Operands: n  [0,1] Description: The 7-bit literal ‘k’ is loaded into the
mm  [00,01, 10, 11] PCLATH register.
-32  k  31
Operation: INDFn  W
Effective address is determined by MOVLW Move literal to W
• FSR + 1 (preincrement)
Syntax: [ label ] MOVLW k
• FSR - 1 (predecrement)
• FSR + k (relative offset) Operands: 0  k  255
After the Move, the FSR value will be
Operation: k  (W)
either:
• FSR + 1 (all increments) Status Affected: None
• FSR - 1 (all decrements) Description: The 8-bit literal ‘k’ is loaded into W reg-
• Unchanged ister. The “don’t cares” will assemble as
Status Affected: Z ‘0’s.
Words: 1
Mode Syntax mm Cycles: 1
Preincrement ++FSRn 00 Example: MOVLW 0x5A
Predecrement --FSRn 01 After Instruction

W = 0x5A
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Description: This instruction is used to move data
between W and one of the indirect Operands: 0  f  127
registers (INDFn). Before/after this Operation: (W)  (f)
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it. Status Affected: None
Description: Move data from W register to register
Note: The INDFn registers are not ‘f’.
physical registers. Any instruction that Words: 1
accesses an INDFn register actually
accesses the register at the address Cycles: 1
specified by the FSRn. Example: MOVWF OPTION_REG
Before Instruction
FFFFh. Incrementing/decrementing it OPTION_REG = 0xFF
beyond these bounds will cause it to W = 0x4F
After Instruction
wrap-around.
OPTION_REG = 0x4F
W = 0x4F
MOVLB Move literal to BSR
Syntax: [ label ] MOVLB k
Operands: 0  k  31
Operation: k  BSR
Description: The 5-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).

PIC16(L)F1526/7
MOVWI Move W to INDFn NOP No Operation
Syntax: [ label ] MOVWI ++FSRn Syntax: [ label ] NOP

[ label ] MOVWI --FSRn Operands: None
[ label ] MOVWI FSRn++ Operation: No operation
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn] Status Affected: None
Operands: n  [0,1] Description: No operation.

mm  [00,01, 10, 11] Words: 1
-32  k  31
Cycles: 1
Operation: W  INDFn
Effective address is determined by Example: NOP
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
Load OPTION_REG Register
OPTION
• FSR + 1 (all increments) with W
• FSR - 1 (all decrements) Syntax: [ label ] OPTION
Unchanged
Operands: None
Operation: (W)  OPTION_REG
Mode Syntax mm
Description: Move data from W register to
Preincrement ++FSRn 00 OPTION_REG register.
Predecrement --FSRn 01
Postincrement FSRn++ 10 Words: 1
Postdecrement FSRn-- 11 Cycles: 1
Example: OPTION
Description: This instruction is used to move data Before Instruction
between W and one of the indirect OPTION_REG = 0xFF
registers (INDFn). Before/after this W = 0x4F
move, the pointer (FSRn) is updated by After Instruction
pre/post incrementing/decrementing it. OPTION_REG = 0x4F
W = 0x4F
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
RESET Software Reset
accesses the register at the address
specified by the FSRn. Syntax: [ label ] RESET
Operands: None
FFFFh. Incrementing/decrementing it Operation: Execute a device Reset. Resets the
beyond these bounds will cause it to RI flag of the PCON register.
wrap-around. Status Affected: None
The increment/decrement operation on Description: This instruction provides a way to

FSRn WILL NOT affect any Status bits. execute a hardware Reset by soft-
ware.

PIC16(L)F1526/7
RETFIE Return from Interrupt RETURN Return from Subroutine

Syntax: [ label ] RETFIE Syntax: [ label ] RETURN
Operands: None Operands: None
Operation: TOS  PC, Operation: TOS  PC
1  GIE Status Affected: None
Status Affected: None Description: Return from subroutine. The stack is
Description: Return from Interrupt. Stack is POPed POPed and the top of the stack (TOS)
and Top-of-Stack (TOS) is loaded in is loaded into the program counter.
the PC. Interrupts are enabled by This is a 2-cycle instruction.
setting Global Interrupt Enable bit,
GIE
(INTCON<7>). This is a 2-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with literal in W RLF Rotate Left f through Carry

Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d
Operands: 0  k  255 Operands: 0  f  127

d  [ 0, 1]
Operation: k  (W);
TOS  PC Operation: See description below
Status Affected: None Status Affected: C
Description: The W register is loaded with the 8-bit Description: The contents of register ‘f’ are rotated
literal ‘k’. The program counter is one bit to the left through the Carry
loaded from the top of the stack (the flag. If ‘d’ is ‘0’, the result is placed in
return address). This is a 2-cycle the W register. If ‘d’ is ‘1’, the result is
instruction. stored back in register ‘f’.
Words: 1 C Register f
Cycles: 2
Words: 1
Example: CALL TABLE;W contains table
;offset value Cycles: 1
• ;W now has table value Example: RLF REG1,0
TABLE •
Before Instruction
•
REG1 = 1110 0110
ADDWF PC ;W = offset
C = 0
RETLW k1 ;Begin table
After Instruction
RETLW k2 ;
REG1 = 1110 0110
•
W = 1100 1100
•
C = 1
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8

PIC16(L)F1526/7
SUBLW Subtract W from literal

RRF Rotate Right f through Carry
Syntax: [ label ] SUBLW k
Syntax: [ label ] RRF f,d
Operands: 0 k 255
d  [0,1] Operation: k - (W) W)
Operation: See description below Status Affected: C, DC, Z
Status Affected: C Description: The W register is subtracted (2’s com-

plement method) from the 8-bit literal
Description: The contents of register ‘f’ are rotated ‘k’. The result is placed in the W regis-
one bit to the right through the Carry ter.
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is C=0 Wk
placed back in register ‘f’.
C=1 Wk
C Register f
DC = 0 W<3:0>  k<3:0>
DC = 1 W<3:0>  k<3:0>
SLEEP Enter Sleep mode SUBWF Subtract W from f

Syntax: [ label ] SLEEP Syntax: [ label ] SUBWF f,d
Operands: None Operands: 0 f 127
d  [0,1]
Operation: 00h  WDT,
0  WDT prescaler, Operation: (f) - (W) destination)
1  TO, Status Affected: C, DC, Z
0  PD
Description: Subtract (2’s complement method) W
Status Affected: TO, PD register from register ‘f’. If ‘d’ is ‘0’, the
Description: The power-down Status bit, PD is result is stored in the W
cleared. Time-out Status bit, TO is register. If ‘d’ is ‘1’, the result is stored
set. Watchdog Timer and its pres- back in register ‘f.
caler are cleared.
The processor is put into Sleep mode C=0 Wf
with the oscillator stopped. C=1 Wf
DC = 0 W<3:0>  f<3:0>
DC = 1 W<3:0>  f<3:0>
SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d}
d  [0,1]
Operation: (f) – (W) – (B) dest
Description: Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.

PIC16(L)F1526/7
SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W

Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k
Operands: 0  f  127 Operands: 0 k 255
d  [0,1]
Operation: (W) .XOR. k W)
Operation: (f<3:0>)  (destination<7:4>),
Status Affected: Z
(f<7:4>)  (destination<3:0>)
Description: The contents of the W register are
XOR’ed with the 8-bit
Description: The upper and lower nibbles of regis- literal ‘k’. The result is placed in the
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the W register.
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
TRIS Load TRIS Register with W XORWF Exclusive OR W with f

Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d
Operands: 5f7 Operands: 0  f  127
d  [0,1]
Operation: (W)  TRIS register ‘f’
Operation: (W) .XOR. (f) destination)
Status Affected: Z
Description: Move data from W register to TRIS
register. Description: Exclusive OR the contents of the W
When ‘f’ = 5, TRISA is loaded. register with register ‘f’. If ‘d’ is ‘0’, the
When ‘f’ = 6, TRISB is loaded. result is stored in the W register. If ‘d’
When ‘f’ = 7, TRISC is loaded. is ‘1’, the result is stored back in regis-
ter ‘f’.

PIC16(L)F1526/7
25.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)

Ambient temperature under bias ....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS, PIC16F1526/7 .......................................................................... -0.3V to +6.5V
Voltage on VCAP with respect to VSS, PIC16F1526/7 ........................................................................ -0.3V to +4.0V
Voltage on VDD with respect to VSS, PIC16LF1526/7 ........................................................................ -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ............................................................................ -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum current out of VSS pin, -40°C  TA  +85°C for industrial............................................................... 350 mA
Maximum current out of VSS pin, -40°C  TA  +125°C for extended ............................................................ 140 mA
Maximum current into VDD pin, -40°C  TA  +85°C for industrial.................................................................. 350 mA
Maximum current into VDD pin, -40°C  TA  +125°C for extended ............................................................... 140 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) 20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 50 mA
Maximum output current sourced by any I/O pin............................................................................................... 50 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x
IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

PIC16(L)F1526/7
FIGURE 25-1: PIC16F1526/7 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C
5.5
VDD (V)
2.5
2.3
0 4 10 16 20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.
FIGURE 25-2: PIC16LF1526/7 VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C

VDD (V)
3.6
2.5
1.8
0 4 10 16 20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.

PIC16(L)F1526/7
FIGURE 25-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
125
-15% to +12.5%
85
Temperature (°C)
60
± 8%
25 ± 6.5%
-15% to +12.5%
-40
1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16(L)F1526/7
25.1 DC Characteristics: Supply Voltage

Standard Operating Conditions (unless otherwise stated)
PIC16LF1526/7 Operating temperature -40°C  TA  +85°C for industrial
-40°C  TA  +125°C for extended
PIC16F1526/7 Operating temperature -40°C  TA  +85°C for industrial
Param. Sym. Characteristic Min. Typ† Max. Units Conditions
No.
Supply Voltage (VDDMIN, VDDMAX)
D001 VDD 1.8 — 3.6 V FOSC  16 MHz
2.5 — 3.6 V FOSC  20 MHz
D001 2.3 — 5.5 V FOSC  16 MHz
2.5 — 5.5 V FOSC  20 MHz
D002* VDR RAM Data Retention Voltage(1)
1.5 — — V Device in Sleep mode
D002* 1.7 — — V Device in Sleep mode
D002A* VPOR* Power-on Reset Release Voltage — 1.6 — V
D002B* VPORR* Power-on Reset Rearm Voltage
— 0.8 — V
D002B* — 1.5 — V
D003 VADFVR Fixed Voltage Reference Voltage for 1.024V, VDD  2.5V
ADC -8 6 % 2.048V, VDD  2.5V
4.096V, VDD  4.75V
D004* SVDD VDD Rise Rate to ensure internal 0.05 — — V/ms See Section 6.1 “Power-On
Power-on Reset signal Reset (POR)” for details.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
FIGURE 25-4: POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR(1)
POR REARM
VSS
TVLOW(2) TPOR(3)
Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.

PIC16(L)F1526/7
25.2 DC Characteristics: Supply Current (IDD)

Param Device Conditions

Min. Typ† Max. Units
No. Characteristics VDD Note
Supply Current (IDD)(1, 2, 3)

D009 LDO Regulator — 350 — A Device operating at 8 MHz
— 13 — A Sleep VREGPM = 0
— 0.3 — A Sleep VREGPM = 1
D010 — 10 20 A 1.8 FOSC = 32 kHz
— 15 35 A 3.0 LP Oscillator
-40°C  TA  +85°C
D010 — 20 35 A 2.3 FOSC = 32 kHz
— 30 A 3.0 LP Oscillator
45
-40°C  TA  +85°C
— 40 50 A 5.0
D011 — 70 100 A 1.8 FOSC = 1 MHz
— 130 A 3.0 XT Oscillator
200
D011 — 120 180 A 2.3 FOSC = 1 MHz
XT Oscillator
— 160 240 A 3.0
— 240 360 A 5.0
D012 — 170 245 A 1.8 FOSC = 4 MHz
XT Oscillator
— 300 440 A 3.0
D012 — 290 475 A 2.3 FOSC = 4 MHz
— 380 A 3.0 XT Oscillator
525
— 460 675 A 5.0
D013 — 25 35 A 1.8 FOSC = 500 kHz
— 42 A 3.0 External Clock (ECL),
60
Low-Power mode
D013 — 50 65 A 2.3 FOSC = 500 kHz
— 60 A 3.0 External Clock (ECL),
80
Low-Power mode
— 70 85 A 5.0
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: 0.1 µF capacitor on VCAP pin (PIC16F1526/7).
4: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k

PIC16(L)F1526/7
25.2 DC Characteristics: Supply Current (IDD) (Continued)


D014 — 150 225 A 1.8 FOSC = 4 MHz
External Clock (ECM)
— 280 400 A 3.0
Medium-Power mode
D014 — 240 325 A 2.3 FOSC = 4 MHz
External Clock (ECM)
— 325 450 A 3.0
Medium-Power mode
— 410 550 A 5.0
D014A — 1.4 1.8 mA 3.0 FOSC = 20 MHz
External Clock (ECH)
— 1.6 2.3 mA 3.6
High-Power mode
D014A — 1.45 1.9 mA 3.0 FOSC = 20 MHz
External Clock (ECH)
— 1.7 2.4 mA 5.0
High-Power mode
D015 — 6.0 15 A 1.8 FOSC = 31 kHz
LFINTOSC
— 15.0 35 A 3.0
-40°C  TA  +85°C
D015 — 18 28 A 2.3 FOSC = 31 kHz
LFINTOSC
— 24 40 A 3.0
-40°C  TA  +85°C
— 26 45 A 5.0
D016 — 245 400 A 1.8 FOSC = 500 kHz
HFINTOSC
— 320 425 A 3.0
D016 — 300 340 A 2.3 FOSC = 500 kHz
— 340 A 3.0 HFINTOSC
370
— 380 450 A 5.0
D017* — 0.6 0.9 mA 1.8 FOSC = 8 MHz
— 0.9 mA 3.0 HFINTOSC
1.1
D017* — 0.7 1.0 mA 2.3 FOSC = 8 MHz
1.2
— 1.1 1.3 mA 5.0
not tested.
consumption.

PIC16(L)F1526/7
25.2 DC Characteristics: Supply Current (IDD) (Continued)


D018 — 0.9 1.4 mA 1.8 FOSC = 16 MHz
HFINTOSC
— 1.5 1.8 mA 3.0
D018 — 1.0 1.5 mA 2.3 FOSC = 16 MHz
1.8
— 1.7 1.9 mA 5.0
D020 — 1.7 2.0 mA 3.0 FOSC = 20 MHz
— 2.1 mA 3.6 HS Oscillator
2.5
D020 — 1.8 2.1 mA 3.0 FOSC = 20 MHz
— 2.2 mA 5.0 HS Oscillator
2.7
D021 — 190 240 A 1.8 FOSC = 4 MHz
EXTRC (Note 4)
— 340 400 A 3.0
D021 — 250 350 A 2.3 FOSC = 4 MHz
— 340 A 3.0 EXTRC (Note 4)
440
— 425 525 A 5.0
not tested.
consumption.

PIC16(L)F1526/7
25.3 DC Characteristics: Power-Down Currents (IPD)

Param Device Max. Max. Conditions

Min. Typ† Units
No. Characteristics +85°C +125°C VDD Note
Power-down Currents (IPD)(2)
D022 Base IPD — 0.02 1.0 8.0 A 1.8 WDT, BOR, FVR and SOSC disabled,
— 0.03 2.0 9.0 A 3.0 all peripherals inactive
D022 Base IPD — 0.20 3.0 10 A 2.3 WDT, BOR, FVR and SOSC disabled,
— 0.30 4.0 12 A 3.0 all peripherals inactive,
Low-power regulator active
— 0.47 6.0 15 A 5.0
D023 — 0.50 6.0 14 A 1.8 WDT Current (Note 1)
— 0.80 7.0 17 A 3.0
D023 — 0.50 6.0 15 A 2.3 WDT Current (Note 1)
— 0.77 7.0 20 A 3.0 VREGPM = 1
— 0.85 8.0 22 A 5.0

D023A — 8.5 24 27 A 3.0 FVR current (Note 1)
D023A — 19 27 37 A 3.0 FVR current (Note 1)
— 20 29 45 A 5.0 VREGPM = 1
D024 — 8.0 17 20 A 3.0 BOR Current (Note 1)

D024 — 8.0 17 30 A 3.0 BOR Current (Note 1)
— 9.0 20 40 A 5.0 VREGPM = 1
D024A — 0.30 4.0 8.0 A 3.0 LPBOR Current (Note 1)

D024A — 0.30 4.0 14 A 3.0 LPBOR Current (Note 1)
— 0.45 8.0 17 A 5.0 VREGPM = 1
D025 — 0.3 5.0 9.0 A 1.8 SOSC Current (Note 1)

— 0.5 8.5 12 A 3.0
D025 — 1.1 6.0 10 A 2.3 SOSC Current (Note 1)
— 1.3 8.5 20 A 3.0 VREGPM = 1
— 1.4 10 25 A 5.0
D026* — 0.10 1.0 9.0 A 1.8 ADC Current (Note 1, 3),
— 0.10 2.0 10 A 3.0 No conversion in progress
D026* — 0.16 3.0 10 A 2.3 ADC Current (Note 1, 3),

— 0.40 4.0 11 A 3.0 No conversion in progress
VREGPM = 1
— 0.50 6.0 16 A 5.0
not tested.
Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max. values should be
used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: ADC clock source is FRC.

PIC16(L)F1526/7
25.3 DC Characteristics: Power-Down Currents (IPD) (Continued)
Param Device Max. Max. Conditions

Min. Typ† Units
No. Characteristics +85°C +125°C VDD Note
(2)
Power-down Base Current (IPD)
D026A* — 250 — — A 1.8 ADC Current (Note 1, 3),
— 250 — — A 3.0 Conversion in progress
D026A* — 280 — — A 2.3 ADC Current (Note 1, 3),

— 280 — — A 3.0 Conversion in progress
VREGPM = 1
— 280 — — A 5.0
not tested.
Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max. values should be
used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: ADC clock source is FRC.

PIC16(L)F1526/7
25.4 DC Characteristics: I/O Ports

DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for industrial
Param
Sym. Characteristic Min. Typ† Max. Units Conditions
No.
VIL Input Low Voltage
I/O PORT:
D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V
D030A — — 0.15 VDD V 1.8V  VDD  4.5V
D031 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V
with I2C levels — — 0.3 VDD V
with SMBus levels — — 0.8 V 2.7V  VDD  5.5V
D032 MCLR, OSC1 (RC mode) — — 0.2 VDD V (Note 1)
D033 OSC1 (HS mode) — — 0.3 VDD V
VIH Input High Voltage
I/O PORT: — —
D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V
D040A 0.25 VDD + — — V 1.8V  VDD  4.5V
0.8
D041 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V
with I2C levels 0.7 VDD — — V
with SMBus levels 2.1 — — V 2.7V  VDD  5.5V
D042 MCLR 0.8 VDD — — V
D043A OSC1 (HS mode) 0.7 VDD — — V
D043B OSC1 (RC mode) 0.9 VDD — — V VDD  2.0V (Note 1)
IIL Input Leakage Current(2)
D060 I/O Ports — ±5 ± 125 nA VSS  VPIN  VDD,
Pin at high impedance, 85°C
— ±5 ± 1000 nA VSS  VPIN  VDD,
D061 MCLR(3) — ± 50 ± 200 nA VSS  VPIN  VDD
IPUR Weak Pull-up Current
D070* 25 100 200 A VDD = 3.3V, VPIN = VSS
25 140 300 A VDD = 5.0V, VPIN = VSS
VOL Output Low Voltage(4)
D080 I/O Ports IOL = 8 mA, VDD = 5V
— — 0.6 V IOL = 6 mA, VDD = 3.3V
IOL = 1.8 mA, VDD = 1.8V
VOH Output High Voltage(4)
D090 I/O Ports IOH = 3.5 mA, VDD = 5V
VDD - 0.7 — — V IOH = 3 mA, VDD = 3.3V
IOH = 1 mA, VDD = 1.8V
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.

PIC16(L)F1526/7
25.4 DC Characteristics: I/O Ports (Continued)
Param
No.
Capacitive Loading Specs on I/O Pins
D101* COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO All I/O pins — — 50 pF
D102 VCAP Capacitor Charging — 200 — A
Charging Current
D102A Source/Sink capability when — 0.0 — mA
charging is complete
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.

PIC16(L)F1526/7
25.5 Memory Programming Requirements

Param
No.
Program Memory Programming
Specifications
D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V (Note 2)
D111 IDDP Supply Current during — — 10 mA
Programming
D112 VBE VDD for Bulk Erase 2.7 — VDDMAX V
D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V
D114 IPPPGM Current on MCLR/VPP during — 1.0 — mA
Erase/Write
D115 IDDPGM Current on VDD during Erase/Write — 5.0 — mA
Program Flash Memory
D121 EP Cell Endurance 10K — — E/W -40C to +85C (Note 1)
D122 VPRW VDD for Read/Write VDDMIN — VDDMAX V
D123 TIW Self-timed Write Cycle Time — 2 2.5 ms
D124 TRETD Characteristic Retention — 40 — Year Provided no other
specifications are violated
D125 EHEFC High-Endurance Flash Cell 100K — — E/W 0C to +60C lower byte
Last 128 addresses
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.

PIC16(L)F1526/7
25.6 Thermal Considerations
Operating temperature -40°C  TA  +125°C
Param
Sym. Characteristic Typ. Units Conditions
No.
TH01 JA Thermal Resistance Junction to 48.3 C/W 64-pin TQFP (10x10 mm) package
Ambient 28.0 C/W 64-pin QFN (9x9 mm) package
TH02 JC Thermal Resistance Junction to Case 26.1 C/W 64-pin TQFP (10x10 mm) package
1.2 C/W 64-pin QFN (9x9 mm) package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD -
VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature; TJ = Junction Temperature.

PIC16(L)F1526/7
25.7 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDIx sc SCKx
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
FIGURE 25-5: LOAD CONDITIONS

Load Condition
Pin CL
VSS
Legend: CL = 50 pF for all pins, 15 pF for

OSC2 output

PIC16(L)F1526/7
25.8 AC Characteristics: PIC16(L)F1526/7-I/E
FIGURE 25-6: CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1/CLKIN
OS02
OS04 OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 25-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Operating temperature -40°C  TA  +125°C
Param
No.
OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz External Clock (ECL)
DC — 4 MHz External Clock (ECM)
DC — 20 MHz External Clock (ECH)
Oscillator Frequency(1) — 32.768 — kHz LP Oscillator
0.1 — 4 MHz XT Oscillator
1 — 4 MHz HS Oscillator
1 — 20 MHz HS Oscillator, VDD > 2.7V
DC — 4 MHz RC Oscillator, VDD >2.0V
OS02 TOSC External CLKIN Period(1) 27 —  s LP Oscillator
250 —  ns XT Oscillator
50 —  ns HS Oscillator
50 —  ns External Clock (EC)
Oscillator Period(1) — 30.5 — s LP Oscillator
250 — 10,000 ns XT Oscillator
50 — 1,000 ns HS Oscillator
250 — — ns RC Oscillator
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
OS04* TosH, External CLKIN High, 2 — — s LP oscillator
TosL External CLKIN Low 100 — — ns XT oscillator
20 — — ns HS oscillator
OS05* TosR, External CLKIN Rise, 0 — — ns LP oscillator
TosF External CLKIN Fall 0 — — ns XT oscillator
0 — — ns HS oscillator
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

PIC16(L)F1526/7
TABLE 25-2: OSCILLATOR PARAMETERS
Operating Temperature -40°C TA +125°C
Param Freq.
No. Tolerance
OS08 HFOSC Internal Calibrated HFINTOSC 6.5% — 16.0 — MHz VDD = 3.0V at 25°C (Note 2)
Frequency (Note 1)
OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz (Note 3)
OS10* TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time — — 5 15 s VREGPM = 0
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 25-3, HFINTOSC Frequency Accuracy over VDD and Temperature.
3: See Figure 26-60 and Figure 26-61, LFINTOSC Frequency Characteristics over VDD and Temperature.

PIC16(L)F1526/7
FIGURE 25-7: CLKOUT AND I/O TIMING
Cycle Write Fetch Read Execute

Q4 Q1 Q2 Q3
FOSC
OS11 OS12
OS20
CLKOUT OS21
OS19 OS16 OS18
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin Old Value New Value
(Output)
OS18, OS19
TABLE 25-3: CLKOUT AND I/O TIMING PARAMETERS

Param
No.
OS11 TosH2ckL FOSC to CLKOUT (1) — — 70 ns VDD = 3.3-5.0V
OS12 TosH2ckH FOSC to CLKOUT (1) — — 72 ns VDD = 3.3-5.0V
OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns
OS14 TioV2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0V
OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid 50 — — ns VDD = 3.3-5.0V
(I/O in setup time)
OS17 TioV2osH Port input valid to Fosc(Q2 cycle) 20 — — ns
(I/O in setup time)
OS18* TioR Port output rise time — 40 72 ns VDD = 1.8V
— 15 32 VDD = 3.3-5.0V
OS19* TioF Port output fall time — 28 55 ns VDD = 1.8V
— 15 30 VDD = 3.3-5.0V
OS20* Tinp INT pin input high or low time 25 — — ns
OS21* Tioc Interrupt-on-change new input level 25 — — ns
time
† Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

PIC16(L)F1526/7
FIGURE 25-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out 32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1: Asserted low.
FIGURE 25-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset) (Device not in Brown-out Reset)
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’.
2 ms delay if PWRTE = 0.

PIC16(L)F1526/7
TABLE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Param
No.
30 TMCL MCLR Pulse Width (low) 2 — — s
30A TMCLR — — — —
31 TWDTLP Low-Power Watchdog Timer 10 16 27 ms VDD = 3.3V-5V,
Time-out Period 1:512 prescaler used
32 TOST Oscillator Start-up Timer Period(1) — 1024 — Tosc (Note 3)
33* TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms
34* TIOZ I/O high impedance from MCLR Low — — 2.0 s
or Watchdog Timer Reset
35 VBOR Brown-out Reset Voltage(2) 2.55 2.70 2.85 V BORV = 0, PIC16(L)F1526/7
2.35 2.45 2.58 V BORV = 1, PIC16F1526/7

1.80 1.90 2.00 V BORV = 1, PIC16LF1526/7
36* VHYST Brown-out Reset Hysteresis 0 25 60 mV -40°C to +85°C
37* TBORDC Brown-out Reset DC Response 1 3 35 s VDD  VBOR
Time
38 VLPBOR Low-Power Brown-out Reset 1.8 2.1 2.5 V LPBOR = 1
Voltage
*These parameters are characterized but not tested.
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device
as possible. 0.1 F and 0.01 F values in parallel are recommended.

PIC16(L)F1526/7
FIGURE 25-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
TABLE 25-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale value
20 or TCY + 40
N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale value
Period 30 or TCY + 40
N
48 FT1 Timer1 Oscillator Input Frequency Range 32.4 32.768 33.1 kHz
(oscillator enabled by setting bit SOSCEN)
49* TCKEZTMR1 Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
Increment mode
tested.

PIC16(L)F1526/7
FIGURE 25-11: CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP
(Capture mode)
CC01 CC02
CC03
Note: Refer to Figure 25-5 for load conditions.
TABLE 25-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Operating Temperature -40°C  TA  +125°C
Param
No.
CC01* TccL CCP Input Low Time No Prescaler 0.5TCY + 20 — — ns

CC02* TccH CCP Input High Time No Prescaler 0.5TCY + 20 — — ns
CC03* TccP CCP Input Period 3TCY + 40 — — ns N = prescale value
N
tested.

PIC16(L)F1526/7
TABLE 25-7: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3)
Operating Temperature Tested at 25°C
Param
No.
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — ±1 ±1.7 LSb VREF = 3.0V
AD03 EDL Differential Error — ±1 ±1 LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V
AD05 EGN Gain Error — ±1 ±2.0 LSb VREF = 3.0V
AD06 VREF Reference Voltage(4) 1.8 — VDD V VREF = (VREF+ minus VREF-)
AD07 VAIN Full-Scale Range VSS — VREF V
AD08 ZAIN Recommended Impedance of — — 10 k Can go higher if external 0.01F capacitor is
Analog Voltage Source present on input pin.
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF, VDD pin or FVR, whichever is selected as reference input.
4: ADC Reference Voltage (Ref+) is the selected reference input, VREF+ pin, VDD pin or the FVR Buffer1. When the FVR is
selected as the reference input, the FVR Buffer1 output selection must be 2.048V or 4.096V (ADFVR<1:0> = 1x).
TABLE 25-8: ADC CONVERSION REQUIREMENTS

Param
No.
AD130* TAD ADC Clock Period 1.0 — 9.0 s FOSC-based
ADC Internal RC Oscillator 1.0 2.0 6.0 s ADCS<2:0> = x11
Period (ADC FRC mode)
AD131 TCNV Conversion Time (not including — 11 — TAD Set GO/DONE bit to conversion
Acquisition Time)(1) complete
AD132* TACQ Acquisition Time — 5.0 — s
AD133 THCD Holding Capacitor Disconnect — 0.5*TAD + 40 ns — ADCS<2:0>  x11
(0.5*TAD + 40 ns) (FOSC-based)
to
— (1.5*TAD + 40 ns) — ADCS<2:0> = x11
(ADC FRC mode)
*These parameters are characterized but not tested.
†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.

PIC16(L)F1526/7
FIGURE 25-12: ADC CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
1 TCY
AD134 (TOSC/2(1))
AD131
Q4
AD130
ADC CLK
ADC Data 7 6 5 4 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 TCY
GO DONE
Sampling Stopped
Sample AD132
Note 1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 25-13: ADC CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134 (TOSC/2 + TCY(1)) 1 TCY
AD131
Q4
AD130
ADC CLK
ADC Data 7 6 5 4 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 TCY
GO DONE
AD132 Sampling Stopped

Sample
Note 1: If the ADC clock source is selected as RC, a time of TCY is added before the ADC clock starts. This allows the
SLEEP instruction to be executed.

PIC16(L)F1526/7
TABLE 25-9: LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS
Param
No.
LDO01 LDO Regulation Voltage — 3.0 — V
LDO02 LDO External Capacitor 0.1 — 1 F
tested.
FIGURE 25-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
US121 US121
DT
US120 US122
TABLE 25-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US120 TCKH2DTV SYNC XMIT (Master and Slave) 3.0-5.5V — 80 ns
Clock high to data-out valid 1.8-5.5V — 100 ns
US121 TCKRF Clock out rise time and fall time 3.0-5.5V — 45 ns
(Master mode) 1.8-5.5V — 50 ns
US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns
1.8-5.5V — 50 ns

PIC16(L)F1526/7
FIGURE 25-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
US125
DT
US126
TABLE 25-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Param.
No.
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK  (DT hold time) 10 — ns
US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns

PIC16(L)F1526/7
FIGURE 25-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SSx
SP70
SCKx
(CKP = 0)
SP71 SP72
SP78 SP79
SCKx
(CKP = 1)
SP79 SP78
SP80
SDOx MSb bit 6 - - - - - -1 LSb
SP75, SP76
SDIx MSb In bit 6 - - - -1 LSb In
SP74
SP73
FIGURE 25-17: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SSx
SP81
SCKx
(CKP = 0)
SP71 SP72
SP79
SP73
SCKx
(CKP = 1)
SP80
SP78
SP75, SP76
SP74

PIC16(L)F1526/7
FIGURE 25-18: SPI SLAVE MODE TIMING (CKE = 0)
SSx
SP70
SCKx SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCKx
(CKP = 1)
SP79 SP78
SP80
SP75, SP76 SP77
SP74
SP73
FIGURE 25-19: SPI SLAVE MODE TIMING (CKE = 1)

SP82
SSx
SP70
SCKx SP83
(CKP = 0)
SP71 SP72
SCKx
(CKP = 1)
SP80
SP77
SP75, SP76
SDIx
MSb In bit 6 - - - -1 LSb In
SP74

PIC16(L)F1526/7
TABLE 25-12: SPI MODE REQUIREMENTS

Param
Symbol Characteristic Min. Typ† Max. Units Conditions
No.
SP70* TSSL2SCH, SS to SCK or SCK input 2.25 TCY — — ns
TSSL2SCL
SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns
SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns
TDIV2SCL
SP74* TSCH2DIL, Hold time of SDI data input to SCK edge 100 — — ns
TSCL2DIL
SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns
1.8-5.5V — 25 50 ns
SP76* TDOF SDO data output fall time — 10 25 ns
SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns
SP78* TSCR SCK output rise time 3.0-5.5V — 10 25 ns
(Master mode) 1.8-5.5V — 25 50 ns
SP79* TSCF SCK output fall time (Master mode) — 10 25 ns
SP80* TSCH2DOV, SDO data output valid after 3.0-5.5V — — 50 ns
TSCL2DOV SCK edge 1.8-5.5V — — 145 ns
SP81* TDOV2SCH, SDO data output setup to SCK edge Tcy — — ns
TDOV2SCL
SP83* TSCH2SSH, SSafter SCK edge 1.5TCY + — — ns
TSCL2SSH 40
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.

PIC16(L)F1526/7
FIGURE 25-20: I2C BUS START/STOP BITS TIMING
SCLx
SP91 SP93
SP90 SP92
SDAx
Start Stop
Condition Condition
TABLE 25-13: I2C BUS START/STOP BITS REQUIREMENTS

Param.
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for
Setup time 400 kHz mode 600 — — repeated Start condition
SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first
Hold time 400 kHz mode 600 — — clock pulse is generated
SP92* TSU:STO Stop condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
FIGURE 25-21: I2C BUS DATA TIMING
SP103 SP100 SP102

SP101
SCLx
SP90
SP106
SP107
SP91 SP92
SDAx
In
SP110
SP109
SP109
SDAx
Out

PIC16(L)F1526/7
TABLE 25-14: I2C BUS DATA REQUIREMENTS

Param.
No.
SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY — —
SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY — —
SP102* TR SDA and SCL rise 100 kHz mode — 1000 ns
time 400 kHz mode 20 + 300 ns CB is specified to be from
0.1CB 10-400 pF
SP103* TF SDA and SCL fall 100 kHz mode — 250 ns
time 400 kHz mode 20 + 250 ns CB is specified to be from
0.1CB 10-400 pF
SP106* THD:DAT Data input hold 100 kHz mode 0 — ns
time 400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup 100 kHz mode 250 — ns (Note 2)
time 400 kHz mode 100 — ns
SP109* TAA Output valid from 100 kHz mode — 3500 ns (Note 1)
clock 400 kHz mode — — ns
SP110* TBUF Bus free time 100 kHz mode 4.7 — s Time the bus must be free
400 kHz mode 1.3 — s before a new
transmission can start
SP111 CB Bus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.

PIC16(L)F1526/7
26.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.

PIC16(L)F1526/7
FIGURE 26-1: IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16LF1526 ONLY
30
25 Max: 85°C + 3ı
Typical: 25°C Max.
20
IDD (μA)
15 Typical
10
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-2: IDD, LP OSCILLATOR, FOSC = 32 kHz, PIC16F1526/7 ONLY
45
Max: 85°C + 3ı Max.
40
Typical: 25°C
35
30 Typical
IDD (μA)
25
20
15
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-3: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16LF1526 ONLY
400
350 Typical: 25°C

4 MHz XT
300
250
IDD (μA)
200
150
1 MHz XT
100
50
1 MHz EXTRC
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-4: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16LF1526 ONLY
450
400 Max: 85°C + 3ı

4 MHz XT
350
300
IDD (μA)
250
200
150 1 MHz XT
100
50 1 MHz EXTRC
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1526/7
FIGURE 26-5: IDD TYPICAL, XT AND EXTRC OSCILLATOR, PIC16F1526/7 ONLY
500
4 MHz XT
450 Typical: 25°C
400
4 MHz EXTRC
350
300
IDD (μA)
250 1 MHz XT
200
150
1 MHz EXTRC
100
50
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 26-6: IDD MAXIMUM, XT AND EXTRC OSCILLATOR, PIC16F1526/7 ONLY
600
4 MHz XT
Max: 85°C + 3ı
500
4 MHz EXTRC
400
IDD (μA)
300 1 MHz XT
200
1 MHz EXTRC
100
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-7: IDD, EXTERNAL CLOCK (ECL), LOW-POWER MODE, FOSC = 32 kHz,
PIC16LF1526 ONLY
30
Max: 85°C + 3ı
25 Typical: 25°C Max.
20
IDD (μA)
15 Typical
10
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
PIC16F1526/7 ONLY
40
35 Typical: 25°C
30
Typical
25
IDD (μA)
20
15
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
PIC16LF1526 ONLY
70
60 Max: 85°C + 3ı
Typical: 25°C Max.
50
40
IDD (μA)
Typical
30
20
10
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
PIC16F1526/7 ONLY
80
70 Max.
60
Typical
50
IDD (μA)
40
30
20
Max: 85°C + 3ı
10 Typical: 25°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-11: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE,
PIC16LF1526 ONLY
400
350 Typical: 25°C

4 MHz
300
250
IDD (μA)
200
150
100 1 MHz
50
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-12: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE,

PIC16LF1526 ONLY
450
400 Max: 85°C + 3ı

4 MHz
350
300
IDD (μA)
250
200
150
1 MHz
100
50
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1526/7
FIGURE 26-13: IDD TYPICAL, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE, PIC16F1526/7
ONLY
450
400 Typical: 25°C
4 MHz
350
300
IDD (μA)
250
200
1 MHz
150
100
50
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 26-14: IDD MAXIMUM, EXTERNAL CLOCK (ECM), MEDIUM-POWER MODE,

PIC16F1526/7 ONLY
500
450 Max: 85°C + 3ı
400 4 MHz
350
300
IDD (μA)
250
1 MHz
200
150
100
50
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-15: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,
PIC16LF1526 ONLY
1.8
20 MHz
1.6 Typical: 25°C
1.4
1.2 16 MHz
IDD (mA)
1.0
0.8
0.6 8 MHz
0.4
0.2
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-16: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,

PIC16LF1526 ONLY
2.0
1.8 Max: 85°C + 3ı 20 MHz
1.6
1.4
16 MHz
1.2
IDD (mA)
1.0
0.8
0.6 8 MHz
0.4
0.2
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1526/7
FIGURE 26-17: IDD TYPICAL, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,
PIC16F1526/7 ONLY
1.8
1.6 Typical: 25°C

20 MHz
1.4
1.2 16 MHz
1.0
IDD (mA)
0.8
0.6 8 MHz
0.4
0.2
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 26-18: IDD MAXIMUM, EXTERNAL CLOCK (ECH), HIGH-POWER MODE,

PIC16F1526/7 ONLY
2.0
1.8 Max: 85°C + 3ı

20 MHz
1.6
1.4
16 MHz
1.2
IDD (mA)
1.0
0.8
8 MHz
0.6
0.4
0.2
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-19: IDD, LFINTOSC, FOSC = 31 kHz, PIC16LF1526 ONLY
30
Max: 85°C + 3ı
25
Typical: 25°C
Max.
20
IDD (μA)
15 Typical
10
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-20: IDD, LFINTOSC, FOSC = 31 kHz, PIC16F1526/7 ONLY
35
Max.
30
25 Typical
IDD (μA)
20
15
10
5 Max: 85°C + 3ı
Typical: 25°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-21: IDD, MFINTOSC, FOSC = 500 kHz, PIC16LF1526 ONLY
400
Max.
Max: 85°C + 3ı
350 Typical: 25°C
300 Typical
IDD (μA)
250
200
150
100
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-22: IDD, MFINTOSC, FOSC = 500 kHz, PIC16F1526/7 ONLY
500
Max.
450 Max: 85°C + 3ı
Typical: 25°C
400 Typical
350
IDD (μA)
300
250
200
150
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-23: IDD TYPICAL, HFINTOSC, PIC16LF1526 ONLY
1.8
16 MHz
1.6 Typical: 25°C
1.4
1.2
8 MHz
IDD (mA)
1.0
0.8 4 MHz
0.6
0.4
0.2
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-24: IDD MAXIMUM, HFINTOSC, PIC16LF1526 ONLY
2.0
16 MHz
1.8 Max: 85°C + 3ı
1.6
1.4
1.2 8 MHz
IDD (mA)
1.0
0.8 4 MHz
0.6
0.4
0.2
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1526/7
FIGURE 26-25: IDD TYPICAL, HFINTOSC, PIC16F1526/7 ONLY
1.8
16 MHz
1.6 Typical: 25°C
1.4
1.2
8 MHz
1.0
IDD (mA)
0.8 4 MHz
0.6
0.4
0.2
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 26-26: IDD MAXIMUM, HFINTOSC, PIC16F1526/7 ONLY
2.0
16 MHz
1.8 Max: 85°C + 3ı
1.6
1.4
8 MHz
1.2
IDD (mA)
1.0
4 MHz
0.8
0.6
0.4
0.2
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-27: IDD TYPICAL, HS OSCILLATOR, PIC16LF1526 ONLY
2.5
Typical: 25°C
2.0 20 MHz
1.5
IDD (mA)
1.0
8 MHz
0.5 4 MHz
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-28: IDD MAXIMUM, HS OSCILLATOR, PIC16LF1526 ONLY
2.5
Max: 85°C + 3ı 20 MHz
2.0
1.5
IDD (mA)
1.0 8 MHz
4 MHz
0.5
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1526/7
FIGURE 26-29: IDD TYPICAL, HS OSCILLATOR, PIC16F1526/7 ONLY
2.5
20 MHz
Typical: 25°C
2.0
1.5
IDD (mA)
8 MHz
1.0
4 MHz
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 26-30: IDD MAXIMUM, HS OSCILLATOR, PIC16F1526/7 ONLY
3.0
20 MHz
2.5 Max: 85°C + 3ı
2.0
IDD (mA)
1.5
8 MHz
1.0
4 MHz
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-31: IPD BASE, SLEEP MODE, PIC16LF1526 ONLY
450
Max: 85°C + 3
M 3ı Max.
400
Typical: 25°C
350
300
D (nA)
250
IPD
200
150
100
Typical
50
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-32: IPD BASE, LOW-POWER SLEEP MODE, VREGPM = 1, PIC16F1526/7 ONLY
600
Max.
Max: 85°C + 3ı
500 Typical: 25°C
400
IPD (nA)
300
Typical
200
100
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-33: IPD, WATCHDOG TIMER (WDT), PIC16LF1526 ONLY
1.4
Max: 85°C + 3ı
1.2 Typical: 25°C
Max.
1.0
0 8
0.8
(μA)
IPD (μA
Typical
0.6
0.4
0.2
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-34: IPD, WATCHDOG TIMER (WDT), PIC16F1526/7 ONLY
1.2
Max: 85°C + 3ı
1.0
Typical: 25°C
Max.
0.8
A)
IPD (μA
0.6 Typical
0.4
0.2
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-35: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16LF1526 ONLY
25
Max.
20 Typical
15
A)
IPD (μA
10
Max: 85°C + 3ı
5
Typical: 25°C
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-36: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC16F1526/7 ONLY
30
25 Max.
20
Typical
IPD (μA)
15
10
5 Max: 85°C + 3ı
Typical: 25°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-37: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16LF1526 ONLY
12

10 Typical: 25°C
8
Typical
D (μA)
6
IPD
0
16
1.6 1 8
1.8 2 0
2.0 2 2
2.2 2 4
2.4 2 6
2.6 2 8
2.8 3 0
3.0 3 2
3.2 3 4
3.4 3 6
3.6 3 8
3.8
VDD (V)
FIGURE 26-38: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC16F1526/7 ONLY
14
Max: 85°C + 3ı
Ma Max
Max.
12 Typical: 25°C
10
Typical
8
IPD (μA)
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-39: IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16LF1526 ONLY
6.0
Max: 85°C + 3ı
5.0
Typical: 25°C
Max.
4.0
A)
IPD (μA
3.0
Typical
2.0
1.0
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-40: IPD, SECONDARY OSCILLATOR, FOSC = 32 kHz, PIC16F1526/7 ONLY
12
Max: 85°C + 3ı
10
Typical: 25°C
Max.
8
IPD (μA)
6 Typical
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-41: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V, PIC16F1526/7 ONLY
4
VOH (V)
3
125°C
Typical
2
-40°C
Graph represents
1
3ı Limits
0
-45 -40 -35 -30 -25 -20 -15 -10 -5 0
IOH (mA)
FIGURE 26-42: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V, PIC16F1526/7 ONLY
125°C
Graph represents
4 3ı Limits
3
VOL (V)
Typical
2
-40°C
0
0 10 20 30 40 50 60 70 80 90 100
IOL (mA)

PIC16(L)F1526/7
FIGURE 26-43: VOH vs. IOH OVER TEMPERATURE, VDD = 3.0V
3.5
Graph represents
3.0 3ı Limits
2.5
VOH (V)
2.0
125°C
1.5
Typical
1.0
-40°C
0.5
0.0
-15 -13 -11 -9 -7 -5 -3 -1
IOH (mA)
FIGURE 26-44: VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V
3.0
125°C
Graph represents
2.5
3ı Limits
Typical
2.0
-40°C
VOL (V)
1.5
1.0
0.5
0.0
0 5 10 15 20 25 30 35 40
IOL (mA)

PIC16(L)F1526/7
FIGURE 26-45: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V, PIC16LF1526 ONLY
2.0
1.8 Graph represents

3ı Limits
1.6
1.4
125°C
1.2
VOH (V)
1.0
Typical
0.8
0.6
-40°C
0.4
0.2
0.0
-4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
IOH (mA)
FIGURE 26-46: VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V, PIC16LF1526 ONLY
1.8
Graph represents
1.6
3ı Limits
1.4
125°C
1.2
Typical
VOL (V)
1.0
-40°C
0.8
0.6
0.4
0.2
0.0
0 1 2 3 4 5 6 7 8 9 10
IOL (mA)

PIC16(L)F1526/7
FIGURE 26-47: POR RELEASE VOLTAGE
1.70
1.68
Max.
1.66
1.64 Typical
1.62
Voltage (V)
Min.
1.60
1.58
1.56
1.54 Max: Typical + 3ı

Typical: 25°C
1.52 Min: Typical - 3ı
1.50
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
FIGURE 26-48: POR REARM VOLTAGE, PIC16F1526/7 ONLY
1.54
1.52 Max: Typical + 3ı

Typical: 25°C
Max.
1.48
1.46
Voltage (V)
1.44
Typical
1.42
1.40
Min.
1.38
1.36
1.34
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

PIC16(L)F1526/7
FIGURE 26-49: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16LF1526 ONLY
2.00
Max.
1.95
Voltage (V)
Typical
1.90
1.85 Min.
Max: Typical + 3ı
Min: Typical - 3ı
1.80
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
FIGURE 26-50: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16LF1526 ONLY
60
50 Max.
Max: Typical + 3ı
40 Typical: 25°C
Min: Typical - 3ı
Voltage (mV)
Typical
30
20
Min.
10
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

PIC16(L)F1526/7
FIGURE 26-51: BROWN-OUT RESET VOLTAGE, BORV = 1, PIC16F1526/7 ONLY
2.60
2.55 Max.
2.50
Typical
Voltage (V)
2.45
Min.
2.40
Max: Typical + 3ı
2.30
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
FIGURE 26-52: BROWN-OUT RESET HYSTERESIS, BORV = 1, PIC16F1526/7 ONLY
70
Max.
60
Max: Typical + 3ı
50 Typical: 25°C
Min: Typical - 3ı
Voltage (mV)
40
Typical
30
20
Min.
10
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

PIC16(L)F1526/7
FIGURE 26-53: BROWN-OUT RESET VOLTAGE, BORV = 0
2.80
2.75
Max.
2.70
Voltage (V)
Typical
2.65
Min.
Max: Typical + 3ı
2.55
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
FIGURE 26-54: BROWN-OUT RESET HYSTERESIS, BORV = 0
90
80
Min.
70
60
Typical
Voltage (mV)
50
40 Max: Typical + 3ı
Typical: 25°C
30 Min: Typical - 3ı
20
Max.
10
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

PIC16(L)F1526/7
FIGURE 26-55: LOW-POWER BROWN-OUT RESET VOLTAGE, LPBOR = 0
2.50
Max.
Max: Typical + 3ı
2.40
Min: Typical - 3ı
2.30
Typical
Voltage (V)
2.20
2.10
2.00
Min.
1.90
1.80
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)
FIGURE 26-56: LOW-POWER BROWN-OUT RESET HYSTERESIS, LPBOR = 0
45
40 Max: Typical + 3ı Max.

Typical: 25°C
35 Min: Typical - 3ı
Typical
30
Voltage (mV)
25
Min.
20
15
10
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C)

PIC16(L)F1526/7
FIGURE 26-57: WDT TIME-OUT PERIOD
24
22 Max.
20
Time (ms)
18 Typical
16
Min.
14
Max: Typical + 3ı (-40°C to +125°C)

12 Typical: statistical mean @ 25°C
Min: Typical - 3ı (-40°C to +125°C)
10
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 26-58: PWRT PERIOD
100

Typical: statistical mean @ 25°C
90
Max.
80
Time (ms)
70 Typical
60
Min.
50
40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-59: FVR STABILIZATION PERIOD
40
Max: Typical + 3ı
35 Max. Typical: statistical mean @ 25°C
30
Typical
25
Time (us)
20
15
Note:
10 The FVR Stabilization Period applies when:
1) coming out of Reset or exiting Sleep mode for PIC12/16LFxxxx devices.
2) when exiting Sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices
5 In all other cases, the FVR is stable when released from Reset.
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1526/7
FIGURE 26-60: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16LF1526 ONLY
36
34
Max.
32
30
Typical
Frequency (kHz)
28
26 Min.
24
20
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
FIGURE 26-61: LFINTOSC FREQUENCY OVER VDD AND TEMPERATURE, PIC16F1526/7 ONLY
36
34
Max.
32
30
Frequency (kHz)
Typical
28
26 Min.
24
20
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
FIGURE 26-62: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE,
PIC16LF1526/7 ONLY
5.0
4.5
Max.
4.0
3.5
3.0 Typical
Time (us)
2.5
2.0
1.5
Max: 85°C + 3ı
1.0 Typical: 25°C
0.5
0.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)

PIC16(L)F1526/7
FIGURE 26-63: LOW-POWER SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE,
VREGPM = 1, PIC16F1526/7 ONLY
35
Max.
30
Typical
25
Time (us)
20
15
10
5 Max: 85°C + 3ı
Typical: 25°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
FIGURE 26-64: SLEEP MODE, WAKE PERIOD WITH HFINTOSC SOURCE,

VREGPM = 0, PIC16F1526/7 ONLY
12
Max.
10
8
Time (us)
Typical
6
2 Max: 85°C + 3ı
Typical: 25°C
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC16(L)F1526/7
27.0 DEVELOPMENT SUPPORT 27.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

PIC16(L)F1526/7
27.2 MPLAB XC Compilers 27.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
• Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
27.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
27.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

PIC16(L)F1526/7
27.6 MPLAB X SIM Software Simulator 27.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB
buffer and logic analyzer display extend the power of IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 27.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
27.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar-
programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati-
with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 27.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display
downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod-
significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

PIC16(L)F1526/7
27.11 Demonstration/Development 27.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and • Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

PIC16(L)F1526/7
28.0 PACKAGING INFORMATION
28.1 Package Marking Information
64-Lead TQFP (10x10x1 mm) Example
XXXXXXXXXX
XXXXXXXXXX PIC16LF1527
XXXXXXXXXX -E/PT e3
YYWWNNN 1527017
64-Lead QFN (9x9x0.9 mm) Example
PIN 1 PIN 1
XXXXXXXXXXX
XXXXXXXXXXX PIC16LF1527
XXXXXXXXXXX -E/MR e3
YYWWNNN 1527017
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC® designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

PIC16(L)F1526/7
28.2 Package Details
The following sections give the technical details of the packages.
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
NOTE 2
E1/2
A B
E1 E
A A
SEE DETAIL 1
N
4X N/4 TIPS
0.20 C A-B D 1 3
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
C 0.05
SEATING
PLANE
A1
64 X b
0.08 C e 0.08 C A-B D
SIDE VIEW
Microchip Technology Drawing C04-085C Sheet 1 of 2

PIC16(L)F1526/7
E
L T
(L1) X=A—B OR D
SECTION A-A X
e/2
DETAIL 1
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 64
Lead Pitch e 0.50 BSC
Overall Height A - - 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle I 0° 3.5° 7°
Overall Width E 12.00 BSC
Overall Length D 12.00 BSC
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.09 - 0.20
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top D 11° 12° 13°
Notes: Mold Draft Angle Bottom E 11° 12° 13°
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2

PIC16(L)F1526/7
C1
C2
Y1
X1
RECOMMENDED LAND PATTERN
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.50 BSC
Contact Pad Spacing C1 11.40
Contact Pad Spacing C2 11.40
Contact Pad Width (X28) X1 0.30
Contact Pad Length (X28) Y1 1.50
Distance Between Pads G 0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2085B Sheet 1 of 1

PIC16(L)F1526/7

PIC16(L)F1526/7

PIC16(L)F1526/7

PIC16(L)F1526/7
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (01/2011)
Original release.
Revision B (05/2011)
Electrical Spec updates.
Revision C (01/2013)
Updated Electrical Spec and added Characterization
Data Graphs.
Revision D (09/2015)
Updated chapters High-Performance RISC CPU,
Device Overview, Memory Organization, Device
Configuration, Enhanced Universal Synchronous
Asynchronous Receiver Transmitter (EUSART),
Packaging Information. Other minor corrections.

PIC16(L)F1526/7
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) - X /XX XXX
Examples:
Device Tape and Reel Temperature Package Pattern a) PIC16F1526T - I/MR 301
Option Range Tape and Reel,
Industrial temperature,
QFN package,
QTP pattern #301
Device: PIC16F1526, PIC16LF1526 b) PIC16F1527 - I/PT
PIC16F1527, PIC16LF1527 Industrial temperature
TQFP package
c) PIC16F1527 - E/MR
Extended temperature,
Tape and Reel Blank = Standard packaging (tube or tray) QFN package
Option: T = Tape and Reel(1)
Temperature I = -40C to +85C (Industrial)

Range: E = -40C to +125C (Extended)
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
Package:(2) MR = Plastic Quad Flat, no lead (QFN) identifier is used for ordering purposes and
PT = Plastic Thin Quad Flatpack (TQFP) is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Pattern: QTP, SQTP, Code or Special Requirements Reel option.
(blank otherwise) 2: Small form-factor packaging options may
be available. Please check
www.microchip.com/packaging for small-
form factor package availability, or contact
your local Sales Office.

PIC16(L)F1526/7
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our web site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design Customers should contact their distributor,
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• General Technical Support – Frequently Asked included in the back of this document.
Questions (FAQ), technical support requests, Technical support is available through the web site
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SERVICE
Microchip’s customer notification service helps keep
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specified product family or development tool of interest.
To register, access the Microchip web site at
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Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB,
MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
SST, SST Logo, SuperFlash and UNI/O are registered
IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the
OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
conveyed, implicitly or otherwise, under any Microchip Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
intellectual property rights unless otherwise stated. Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-823-9
QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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07/14/15

PIC16 (L) F1526/7: 64-Pin Flash Microcontrollers With XLP Technology

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PIC16 (L) F1526/7: 64-Pin Flash Microcontrollers With XLP Technology

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PIC16(L)F1526/7

64-Pin Flash Microcontrollers with XLP Technology

 2011-2015 Microchip Technology Inc. DS40001458D-page 1

High-Endurance Flash (bytes)

PIC16(L)F1512 (1) 2048 128 128 25 17 Y 2/1 1 1 2 I Y

DS40001458D-page 2  2011-2015 Microchip Technology Inc.

Note 1: See Table 1 for list of pin peripheral function.

 2011-2015 Microchip Technology Inc. DS40001458D-page 3

Note 1: See Table 1 for list of pin peripheral function.

DS40001458D-page 4  2011-2015 Microchip Technology Inc.

64-Pin TQFP, QFN

 2011-2015 Microchip Technology Inc. DS40001458D-page 5

64-Pin TQFP, QFN

DS40001458D-page 6  2011-2015 Microchip Technology Inc.

 2011-2015 Microchip Technology Inc. DS40001458D-page 7

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS40001458D-page 8  2011-2015 Microchip Technology Inc.

TABLE 1-1: DEVICE PERIPHERAL

 2011-2015 Microchip Technology Inc. DS40001458D-page 9

Timer0 Timer1/3/5 Timer2/4/6/8/10 EUSARTs

Note 1: See applicable chapters for more information on peripherals.

DS40001458D-page 10  2011-2015 Microchip Technology Inc.

TABLE 1-2: PIC16(L)F1526/7 PINOUT DESCRIPTION

RA0/AN0 RA0 TTL CMOS General purpose I/O.

 2011-2015 Microchip Technology Inc. DS40001458D-page 11

DS40001458D-page 12  2011-2015 Microchip Technology Inc.

 2011-2015 Microchip Technology Inc. DS40001458D-page 13

DS40001458D-page 14  2011-2015 Microchip Technology Inc.

FIGURE 2-1: CORE BLOCK DIAGRAM

 2011-2015 Microchip Technology Inc. DS40001458D-page 15

2.2 16-level Stack with Overflow and

2.3 File Select Registers

2.4 Instruction Set

DS40001458D-page 16  2011-2015 Microchip Technology Inc.

3.1 Program Memory Organization

TABLE 3-1: DEVICE SIZES AND ADDRESSES

 2011-2015 Microchip Technology Inc. DS40001458D-page 17

Stack Level 15 Stack Level 15

Reset Vector 0000h Reset Vector 0000h

Interrupt Vector 0004h Interrupt Vector 0004h

Rollover to Page 3 Rollover to Page 7

DS40001458D-page 18  2011-2015 Microchip Technology Inc.

The BRW instruction makes this type of table very sim-

3.2.1.2 Indirect Read with FSR

 2011-2015 Microchip Technology Inc. DS40001458D-page 19

DS40001458D-page 20  2011-2015 Microchip Technology Inc.

REGISTER 3-1: STATUS: STATUS REGISTER

bit 7-5 Unimplemented: Read as ‘0’

 2011-2015 Microchip Technology Inc. DS40001458D-page 21

3.5.3 DEVICE MEMORY MAPS

DS40001458D-page 22  2011-2015 Microchip Technology Inc.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

Note 1: PIC16F1526/7 only.

General Register General General General General General General

BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30

Legend: = Unimplemented data memory locations, read as ‘0’.