Embedded systems

Exercise session 2
PIC16F Basics
Documentation:
https://www.microchip.com/en-us/product/PIC16F1789

PIC16F1788/9
28-Pin 8-Bit Advanced Analog Flash Microcontroller

High-Performance RISC CPU: Extreme Low-Power Management

• Only 49 Instructions
PIC16LF1788/9 with XLP:
• Operating Speed: • Sleep mode: 50 nA @ 1.8V, typical
- DC – 32 MHz clock input • Watchdog Timer: 500 nA @ 1.8V, typical
- DC – 125 ns instruction cycle • Timer1 Oscillator: 500 nA @ 32 kHz
• Interrupt Capability with Automatic Context • Operating Current:
Saving - 8 A @ 32 kHz, 1.8V, typical
• 16-Level Deep Hardware Stack with optional - 32 A/MHz @ 1.8V, typical
Overflow/Underflow Reset
Analog Peripheral Features:
• Direct, Indirect and Relative Addressing modes:
• Two full 16-bit File Select Registers (FSRs) • Analog-to-Digital Converter (ADC):
- FSRs can read program and data memory - Fully differential 12-bit converter
- Up to 75 ksps conversion rate
Memory Features: - 11 single-ended channels
• Up to 16 KW Flash Program Memory: - 5 differential channels
- Self-programmable under software control - Positive and negative reference selection
- Programmable code protection • One 8-Bit and Three 5-Bit Digital-to-Analog
- Programmable write protection Converters (DAC):
 - Programmable write protection Converters (DAC):
• 256 Bytes of Data EEPROM - Output available externally
• Up to 2048 Bytes of RAM - Positive and negative reference selection
- Internal connections to comparators, op amps,
High-Performance PWM Controller: Fixed Voltage Reference (FVR) and ADC
• Four High-Speed Comparators:
• Four Programmable Switch Mode Controller
(PSMC) modules: - 50 ns response time @ VDD = 5V
- Digital and/or analog feedback control of - Rail-to-rail inputs
PWM frequency and pulse begin/end times - Software selectable hysteresis
- 16-bit Period, Duty Cycle and Phase - Internal connection to op amps, FVR and DAC
- 16 ns clock resolution • Up to Three Operational Amplifiers:
- Supports Single PWM, Complementary, - Rail-to-rail inputs/outputs
Push-Pull and 3-phase modes of operation - High/Low selectable Gain Bandwidth Product
- Dead-band control with 8-bit counter - Internal connection to DAC and FVR
- Auto-shutdown and restart • Fixed Voltage Reference (FVR):
- Leading and falling edge blanking - 1.024V, 2.048V and 4.096V output levels
- Burst mode - Internal connection to ADC, comparators and
DAC

I/O Features:
• Up to 36 I/O Pins and 1 Input-only Pin:
• High Current Sink/Source for LED Drivers
• Individually Programmable Interrupt-on-Change
Pins
• Individually Programmable Weak Pull-Ups
• Individual Input Level Selection
• Individually Programmable Slew Rate Control
• Individually Programmable Open-Drain Outputs

 2013-2015 Microchip Technology Inc. DS40001675C-page 1

PIC16(L)F1788/9
Digital Peripheral Features: General Microcontroller Features:
• Timer0: 8-Bit Timer/Counter with 8-Bit • Power-Saving Sleep mode
Programmable Prescaler • Power-on Reset (POR)
• Enhanced Timer1: • Power-up Timer (PWRT)
- 16-bit timer/counter with prescaler • Oscillator Start-up Timer (OST)
- External Gate Input mode • Brown-out Reset (BOR) with Selectable Trip Point
- Dedicated low-power 32 kHz oscillator driver • Extended Watchdog Timer (WDT)
• Timer2: 8-Bit Timer/Counter with 8-Bit Period • In-Circuit Serial ProgrammingTM (ICSPTM)
Register, Prescaler and Postscaler
• In-Circuit Debug (ICD)
• Two Capture/Compare/PWM modules (CCP):
• Enhanced Low-Voltage Programming (LVP)
- 16-bit capture, maximum resolution 12.5 ns
• Operating Voltage Range:
- 16-bit compare, max resolution 31.25 ns
- 1.8V to 3.6V (PIC16LF1788/9)
- 10-bit PWM, max frequency 32 kHz
- 2.3V to 5.5V (PIC16F1788/9)
• Master Synchronous Serial Port (SSP) with SPI
and I2C with:
- 7-bit address masking
- SMBus/PMBusTM compatibility
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART):
- RS-232, RS-485 and LIN compatible
- Auto-baud detect
- Auto-wake-up on start

Oscillator Features:
• Operate up to 32 MHz from Precision Internal
Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
• Operate up to 32 MHz from Precision Internal
Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
32 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• 32.768 kHz Timer1 Oscillator:
- Available as system clock
- Low-power RTC
• External Oscillator Block with:
- 4 crystal/resonator modes up to 32 MHz
using 4x PLL
- 3 external clock modes up to 32 MHz
• 4x Phase-Locked Loop (PLL)
• Fail-Safe Clock Monitor:
- Detect and recover from external oscillator
failure
• Two-Speed Start-up:
- Minimize latency between code execution
and external oscillator start-up

DS40001675C-page 2  2013-2015 Microchip Technology Inc.

Program memory organization
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1788/9

PC<14:0>
CALL, CALLW 15
RETURN, RETLW
Interrupt, RETFIE
Stack Level 0
Stack Level 1

Stack Level 15

Reset Vector 0000h

Interrupt Vector 0004h

0005h
Page 0
07FFh
0800h
Page 1
0FFFh
1000h
On-chip Page 2
Program 17FFh
Memory 1800h
Page 3
1FFFh
Page 4 2000h

Page 7
3FFFh
Rollover to Page 0 4000h

Rollover to Page 7
7FFFh
FIGURE 3-3: LOADING OF PC IN
DIFFERENT SITUATIONS

14 PCH PCL 0 Instruction with

PC PCL as
Destination

7 8
6 0
PCLATH ALU Result

14 PCH PCL 0
PC GOTO, CALL

6 4 0 11
PCLATH OPCODE <10:0>

14 PCH PCL 0
PC CALLW

6 7 0 8
PCLATH W

14 PCH PCL 0
PC BRW

15
PC + W

14 PCH PCL 0
PC BRA

15
PC + OPCODE <8:0>
Notes:

There exist a special instruction MOVLP for loading a value into

PCLATH, and an assembly directive PAGESEL for computing this
value for you.

If you manage to fit your program in the first 2K page, you do not
need them!
Data memory organization
 FIGURE 3-2: BANKED MEMORY
PARTITIONING

7-bit Bank Offset Memory Region

32 banks of 128 bytes each, selected
00h
by BSR. Core Registers
(12 bytes)
0Bh
0Ch
Special Function Registers
Core registers: WREG, STATUS, PCL, (20 bytes maximum)
PCLATH, BSR, INTCON . . . (identical 1Fh
20h
in every bank)

Special registers: different in every General Purpose RAM

(80 bytes maximum)
bank.

General RAM: different in every bank. 6Fh

70h
Common RAM
(16 bytes)
7Fh
Common RAM: identical in every bank.
 3.3.4 DEVICE MEMORY MAPS
DS40001675CDS40001579EDS40001637C-page 33

PIC16(L)F1788/9
The memory maps for Bank 0 through Bank 31 are shown in the tables in this section.

TABLE 3-3: PIC16(L)F1788 MEMORY MAP (BANKS 0-7)

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h 080h 100h 180h 200h 280h 300h 380h
Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers Core Registers
(Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2)
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh ODCONB 30Dh SLRCONB 38Dh INLVLB
00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh ANSELC 20Eh WPUC 28Eh ODCONC 30Eh SLRCONC 38Eh INLVLC
00Fh — 08Fh — 10Fh — 18Fh — 20Fh — 28Fh — 30Fh — 38Fh —
010h PORTE 090h TRISE 110h — 190h — 210h WPUE 290h — 310h — 390h INLVLE
011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h CCPR3L 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h CCPR3H 392h IOCAN
013h PIR3 093h PIE3 113h CM2CON0 193h EEDATL 213h SSP1MSK 293h CCP1CON 313h CCP3CON 393h IOCAF
014h PIR4 094h PIE4 114h CM2CON1 194h EEDATH 214h SSP1STAT 294h — 314h — 394h IOCBP
015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSP1CON1 295h — 315h — 395h IOCBN
016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSP1CON2 296h — 316h — 396h IOCBF
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h SSP1CON3 297h — 317h — 397h IOCCP
018h T1CON 098h OSCTUNE 118h DAC1CON0 198h — 218h — 298h CCPR2L 318h — 398h IOCCN
019h T1GCON 099h OSCCON 119h DAC1CON1 199h RC1REG 219h — 299h CCPR2H 319h — 399h IOCCF
01Ah TMR2 09Ah OSCSTAT 11Ah CM4CON0 19Ah TX1REG 21Ah — 29Ah CCP2CON 31Ah — 39Ah —
01Bh PR2 09Bh ADRESL 11Bh CM4CON1 19Bh SP1BRGL 21Bh — 29Bh — 31Bh — 39Bh —
01Ch T2CON 09Ch ADRESH 11Ch APFCON2 19Ch SP1BRGH 21Ch — 29Ch — 31Ch — 39Ch —
01Dh — 09Dh ADCON0 11Dh APFCON1 19Dh RC1STA 21Dh — 29Dh — 31Dh — 39Dh —
01Eh — 09Eh ADCON1 11Eh CM3CON0 19Eh TX1STA 21Eh — 29Eh — 31Eh — 39Eh —
01Fh — 09Fh ADCON2 11Fh CM3CON1 19Fh BAUD1CON 21Fh — 29Fh — 31Fh — 39Fh —
020h 0A0h 120h 1A0h 220h 2A0h 320h 3A0h
General General General General General General General General
Purpose Purpose Purpose Purpose Purpose Purpose Purpose Purpose
 2013-2015 Microchip Technology Inc.

Register Register Register Register Register Register Register Register

80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes 80 Bytes

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

070h 0F0h 170h 1F0h 270h 2F0h 370h 3F0h
Common RAM Accesses Accesses Accesses Accesses Accesses Accesses Accesses
70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh 70h – 7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: PIC16F1788 only.
Notes:

There exist a special instruction MOVLB for loading a value into

BSR, and an assembly directive BANKSEL for computing this
value for you.

There exist mechanisms for addressing indirectly data and

program memory, and for addressing linearly the complete 2K
data RAM.
 A first program

PROCESSOR 16F1789

#include <xc.inc>

CONFIG FOSC = INTOSC ; INTOSC oscillator

CONFIG WDTE = OFF ; Watchdog Timer disabled
CONFIG PWRTE = ON ; Power-up Timer enabled
CONFIG FOSC = INTOSC ; INTOSC oscillator
CONFIG WDTE = OFF ; Watchdog Timer disabled
CONFIG PWRTE = ON ; Power-up Timer enabled
CONFIG MCLRE = ON ; MCLR/VPP pin function is MCLR
CONFIG CP = OFF ; Flash Program Memory Code Protection off
CONFIG CPD = OFF ; Data Memory Code Protection off
CONFIG BOREN = ON ; Brown-out Reset enabled
CONFIG CLKOUTEN = OFF ; Clock Out disabled
CONFIG IESO = ON ; Internal/External Switchover enabled
CONFIG FCMEN = ON ; Fail-Safe Clock Monitor enabled
CONFIG WRT = OFF ; Flash Memory Self-Write Protection off
CONFIG VCAPEN = OFF ; Voltage Regulator Capacitor disabled
CONFIG PLLEN = ON ; 4x PLL enabled
CONFIG STVREN = ON ; Stack Overflow/Underflow Reset enabled
CONFIG BORV = LO ; Brown-out Reset Voltage trip point low
CONFIG LPBOR = OFF ; Low Power Brown-Out Reset disabled
CONFIG LVP = OFF ; Low-Voltage Programming disabled

PSECT udata_bank0
counter_l:
DS 1
counter_h:
DS 1
counter_hh:
DS 1

PSECT reset_vec, class = CODE, delta = 2

reset_vec:
goto start

PSECT isr_vec, class = CODE,delta = 2

retfie
PSECT code
start: banksel OSCCON
movlw 0xf8 ; PLL enable, 32MHz HF
movwf OSCCON
banksel ANSELA
clrf ANSELA
banksel TRISA
clrf TRISA
clrf BSR
loop: movlw 0xff
movwf PORTA
call delay
movlw 0x00
movwf PORTA
call delay
goto loop
delay: movlw 0xf8
movwf counter_hh
clrf counter_h
clrf counter_l
delay_loop:
incfsz counter_l, f
goto delay_loop
incfsz counter_h, f
goto delay_loop
incfsz counter_hh, f
goto delay_loop
return

end reset_vec
PIC16(L)F1788/9
6.6 Register Definitions: Oscillator Control

REGISTER 6-1: OSCCON: OSCILLATOR CONTROL REGISTER

R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0
SPLLEN IRCF<3:0> — SCS<1:0>
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements)
If PLLEN in Configuration Words = 0:
1 = 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 = 16 MHz HF or 32 MHz HF(2)
1110 = 8 MHz or 32 MHz HF(2)
1101 = 4 MHz HF
1100 = 2 MHz HF
1011 = 1 MHz HF
1010 = 500 kHz HF(1)
1001 = 250 kHz HF(1)
1000 = 125 kHz HF(1)
 1011 = 1 MHz HF
1010 = 500 kHz HF(1)
1001 = 250 kHz HF(1)
1000 = 125 kHz HF(1)
0111 = 500 kHz MF (default upon Reset)
0110 = 250 kHz MF
0101 = 125 kHz MF
0100 = 62.5 kHz MF
0011 = 31.25 kHz HF(1)
0010 = 31.25 kHz MF
000x = 31 kHz LF
bit 2 Unimplemented: Read as ‘0’
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Timer1 oscillator
00 = Clock determined by FOSC<2:0> in Configuration Words.

Note 1: Duplicate frequency derived from HFINTOSC.

2: 32 MHz when SPLLEN bit is set. Refer to Section 6.2.2.6 “32 MHz Internal Oscillator Frequency
Selection”.

DS40001675C-page 86  2013-2015 Microchip Technology Inc.

 PIC16(L)F1788/9
13.3 PORTA Registers 13.3.5 INPUT THRESHOLD CONTROL
The INLVLA register (Register 13-10) controls the input
13.3.1 DATA REGISTER voltage threshold for each of the available PORTA input
PORTA is an 8-bit wide, bidirectional port. The pins. A selection between the Schmitt Trigger CMOS or
corresponding data direction register is TRISA the TTL Compatible thresholds is available. The input
(Register 13-4). Setting a TRISA bit (= 1) will make the threshold is important in determining the value of a
corresponding PORTA pin an input (i.e., disable the read of the PORTA register and also the level at which
output driver). Clearing a TRISA bit (= 0) will make the an interrupt-on-change occurs, if that feature is
corresponding PORTA pin an output (i.e., enables enabled. See Section TABLE 31-1: “Supply Voltage”
output driver and puts the contents of the output latch for more information on threshold levels.
on the selected pin). Example 13-1 shows how to
Note: Changing the input threshold selection
initialize PORTA.
should be performed while all peripheral
Reading the PORTA register (Register 13-3) reads the modules are disabled. Changing the
status of the pins, whereas writing to it will write to the threshold level during the time a module is
PORT latch. All write operations are read-modify-write active may inadvertently generate a
operations. Therefore, a write to a port implies that the transition associated with an input pin,
port pins are read, this value is modified and then regardless of the actual voltage level on
written to the PORT data latch (LATA). that pin.

13.3.2 DIRECTION CONTROL 13.3.6 ANALOG CONTROL

The TRISA register (Register 13-4) controls the The ANSELA register (Register 13-6) is used to
PORTA pin output drivers, even when they are being configure the Input mode of an I/O pin to analog.
used as analog inputs. The user should ensure the bits Setting the appropriate ANSELA bit high will cause all
in the TRISA register are maintained set when using digital reads on the pin to be read as ‘0’ and allow
them as analog inputs. I/O pins configured as analog analog functions on the pin to operate correctly.
inputs always read ‘0’.
The state of the ANSELA bits has no effect on digital
13.3.3 OPEN-DRAIN CONTROL output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
The ODCONA register (Register 13-8) controls the will be analog. This can cause unexpected behavior
open-drain feature of the port. Open-drain operation is when executing read-modify-write instructions on the
independently selected for each pin. When an affected port.
13.3.3 OPEN-DRAIN CONTROL output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
The ODCONA register (Register 13-8) controls the will be analog. This can cause unexpected behavior
open-drain feature of the port. Open-drain operation is when executing read-modify-write instructions on the
independently selected for each pin. When an affected port.
ODCONA bit is set, the corresponding port output
becomes an open-drain driver capable of sinking Note: The ANSELA bits default to the Analog
current only. When an ODCONA bit is cleared, the mode after Reset. To use any pins as
corresponding port output pin is the standard push-pull digital general purpose or peripheral
drive capable of sourcing and sinking current. inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
13.3.4 SLEW RATE CONTROL
EXAMPLE 13-1: INITIALIZING PORTA
The SLRCONA register (Register 13-9) controls the
; This code example illustrates
slew rate option for each port pin. Slew rate control is
; initializing the PORTA register. The
independently selectable for each port pin. When an ; other ports are initialized in the same
SLRCONA bit is set, the corresponding port pin drive is ; manner.
slew rate limited. When an SLRCONA bit is cleared,
The corresponding port pin drive slews at the maximum BANKSEL PORTA ;
rate possible. CLRF PORTA ;Init PORTA
BANKSEL LATA ;Data Latch
CLRF LATA ;
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
MOVWF TRISA ;and set RA<2:0> as
;outputs

 2013-2015 Microchip Technology Inc. DS40001675C-page 134

Compiling
MPLAB X:

Complete, knows about every type of device.

“Rube Goldberg” machine.

Not so convenient for small projects.

Simpler solution: Use command line.

% /opt/microchip/xc8/v2.32/pic-as/bin/pic-as -mcpu=16F1789 \
-xassembler-with-cpp -Wa,-a -Wl,-preset_vec=0h \
-Wl,-pisr_vec=4h blink.asm

Memory Summary:
Program space used 1Ch ( 28) of 4000h words ( 0.2%)
Data space used 3h ( 3) of 800h bytes ( 0.1%)
EEPROM space used 0h ( 0) of 100h bytes ( 0.0%)
Configuration bits used 2h ( 2) of 2h words (100.0%)
ID Location space used 0h ( 0) of 4h bytes ( 0.0%)
blink.lst:
38 psect udata_bank0
39 0020 counter_l:
40 0020 ds 1
41 0021 counter_h:
42 0021 ds 1
43 0022 counter_hh:
44 0022 ds 1
45
46 psect code
47 0005 start:
48 0005 0021 banksel 153
49 0006 30F8 movlw 248 ; PLL enable, 32MHz HF
50 0007 0099 movwf 153
51 0008 0023 banksel 396
52 0009 018C clrf 396
53 000A 0021 banksel 140
54 000B 018C clrf 140
55 000C 0188 clrf 8
56 000D loop:
57 000D 30FF movlw 255
58 000E 008C movwf 12
59 000F 2014 call delay
60 0010 3000 movlw 0
61 0011 008C movwf 12
62 0012 2014 call delay
63 0013 280D goto loop
Programming
Always double-check connections and power supply voltage before
power-on!
% java -jar /opt/microchip/mplabx/v5.50/mplab_platform/mplab_ipe/\
ipecmd.jar -TPPK4 -E -M -P16F1789 -F"blink.hex" -OL

*****************************************************
Connecting to MPLAB PICkit 4...
Currently loaded versions:
Application version............00.06.87
Boot version...................01.00.00
Script version.................00.04.48
Script build number............7acb7c9d66
Tool pack version .............1.8.1120
Target voltage detected
Target device PIC16F1789 found.
Device Revision Id = 0x2041
*****************************************************
Erasing...
Erase successful
*****************************************************
Calculating memory ranges for operation...
Erasing...
The following memory area(s) will be programmed:
program memory: start address = 0x0, end address = 0x1f
configuration memory
Programming/Verify complete
Program Report
Simple Makefile:
CPU = 16F1789
PROGRAMMER = PPK4

SRCS = blink.asm
EXEC = blink

AS-DIR = /opt/microchip/xc8/v2.32/pic-as/bin/
AS = $(AS-DIR)/pic-as

IPE_DIR = /opt/microchip/mplabx/v5.50/mplab_platform/mplab_ipe/
FLASH_CMD = java -jar $(IPE_DIR)/ipecmd.jar

AS_FLAGS = -mcpu=$(CPU) -xassembler-with-cpp -Wa,-a -Wl,-preset_vec=0h \

-Wl,-pisr_vec=4h
FLASH_ARGS = -T$(PROGRAMMER) -E -M -P$(CPU) -F"$(EXEC).hex" -OL

.PHONY: all clean flash

all: $(EXEC)

$(EXEC):
$(AS) $(AS_FLAGS) $(SRCS) -o $(EXEC)

clean:
-@rm -f $(EXEC).{elf,hex,hxl,cmf,sym,lst,rlf,d,i} MPLABXLog.xml

flash: $(EXEC)
$(FLASH_CMD) $(FLASH_ARGS)
References:

PIC 16F instructions, peripherals: Microcontroller datasheet.

Assembly directives and options, example programs: MPLAB XC8

PIC Assembler User’s Guide, MPLAB XC8 PIC Assembler User’s
Guide for Embedded Engineers.

Programmer features: PICkit 3 Programmer/Debugger User’s

Guide, MPLAB PICkit 4 In-Circuit Debugger User’s Guide.