PIC12F752/HV752: 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

PIC12F752/HV752
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers
High-Performance RISC CPU Peripheral Features

• Only 35 Instructions to Learn: • Five I/O Pins and One Input-only Pin
- All single-cycle instructions except branches • High Current Source/Sink:
• Operating Speed: - 50 mA I/O, (2 pins)
- DC – 20 MHz clock input - 25 mA I/O, (3 pins)
- DC – 200 ns instruction cycle • Two High-Speed Analog Comparator modules:
• 1024 x 14 On-chip Flash Program Memory - 40 ns response time
• Self Read/Write Program Memory - Fixed Voltage Reference (FVR)
• 64 x 8 General Purpose Registers (SRAM) - Programmable on-chip voltage reference via
• Interrupt Capability integrated 5-bit DAC
• 8-Level Deep Hardware Stack - Internal/external inputs and outputs
• Direct, Indirect and Relative Addressing modes (selectable)
- Built-in Hysteresis (software selectable)
Microcontroller Features
• A/D Converter:
• Precision Internal Oscillator: - 10-bit resolution
- Factory calibrated to ±1%, typical - Four external channels
- Software selectable frequency: - Two internal reference voltage channels
8 MHz, 4 MHz, 1 MHz or 31 kHz • Dual Range Digital-to-Analog Converter (DAC):
- Software tunable - 5-bit resolution
• Power-Saving Sleep mode - Full Range or Limited Range output
• Voltage Range (PIC12F752): - 4 mV steps @ 2.0V (Limited Range)
- 2.0V to 5.5V - 65 mV steps @ 2.0V (Full Range)
• Shunt Voltage Regulator (PIC12HV752) • Fixed Voltage Reference (FVR), 1.2V reference
- 2.0V to user defined • Capture, Compare, PWM (CCP) module:
- 5-volt regulation - 16-bit Capture, max. resolution = 12.5 ns
- 1 mA to 50 mA shunt range - Compare, max. resolution = 200 ns
• Multiplexed Master Clear with Pull-up/Input Pin - 10-bit PWM, max. frequency = 20 kHz
• Interrupt-on-Change Pins • Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
• Individually Programmable Weak Pull-ups • Enhanced Timer1:
• Power-on Reset (POR) - 16-bit Timer/Counter with Prescaler
• Power-up Timer (PWRT) - External Timer1 Gate (count enable)
• Brown-out Reset (BOR) - Four Selectable Clock sources
• Watchdog Timer (WDT) with Internal Oscillator for • Timer2: 8-Bit Timer/Counter with Prescaler:
Reliable Operation - 8-bit Period Register and Postscaler
• Industrial and Extended Temperature Range • Hardware Limit Timer (HLT):
• High Endurance Flash: - 8-bit Timer with Prescaler
- 100,000 write Flash endurance - 8-bit period register and postscaler
- Flash retention: >40 years - Asynchronous H/W Reset sources
• Programmable Code Protection • Complementary Output Generator (COG):
• In-Circuit Debug (ICD) via Two Pins - Complementary Waveforms from selectable
• In-Circuit Serial Programming™ (ICSP™) via Two sources
Pins - Two I/O (50 mA) for direct MOSFET drive
- Rising and/or Falling edge dead-band control
eXtreme Low-Power (XLP) Features - Phase control, Blanking control
• Sleep Current: - Auto-shutdown
- 50 nA @ 2.0V, typical
• Operating Current:
- 11 µA @ 32 kHz, 2.0V, typical
- 260 µA @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
• <1 µA @ 2.0V, typical
 2011-2015 Microchip Technology Inc. DS40001576D-page 1

PIC12F752/HV752
TABLE 1: PIC12F752/HV752 FEATURE SUMMARY
Output Generator
Shunt Regulator
Complementary
Self Read/Write
Flash Program
Memory (User)
SRAM (bytes)
10-bit A/D (ch)

Flash Memory
Comparators
(words)
8/16-bit
Timers
(COG)
CCP
XLP
I/Os
Device
PIC12F752 1024 Y 64 6 4 2 3/1 1 Y N Y

PIC12HV752 1024 Y 64 6 4 2 3/1 1 Y Y Y
FIGURE 1: 8-PIN PDIP, SOIC, DFN
VDD 1 8 VSS
RA5 2 7 RA0/ICSPDAT
PIC12F752/HV752
RA4 3 6 RA1/ICSPCLK
MCLR/VPP/RA3 4 5 RA2
Note: See Table 1 for the location of all peripheral functions.
DS40001576D-page 2  2011-2015 Microchip Technology Inc.

PIC12F752/HV752
TABLE 2: 8-PIN ALLOCATION TABLE (PIC12F752/HV752)
8-Pin PDIP/SOIC/DFN
Generator (COG)
Complementary
Comparators
Reference
Interrupts
Voltage
Pull-up
Output
Timers
Basic
ADC
CCP
I/O
RA0(4) 7 AN0 C1IN0+ — — IOC Y COG1OUT1 DACOUT ICSPDAT

C2IN0+ REFOUT
RA1 6 AN1 C1IN0- — — IOC Y — VREF+ ICSPCLK
C2IN0-
RA2(4) 5 AN2 C1OUT T0CKI CCP1 IOC Y COG1OUT0 — —
C2OUT INT
RA3(1) 4 — — T1G(2) — IOC Y(3) COG1FLT(2) — MCLR/VPP
RA4 3 AN3 C1IN1- T1G — IOC Y COG1FLT — CLKOUT
COG1OUT1(2)
RA5 2 — C2IN1- T1CKI — IOC Y COG1OUT0(2) — CLKIN
— 1 — — — — — — — — VDD
— 8 — — — — — — — — VSS
Note 1: Input-only.
2: Alternate pin function via the APFCON register.
3: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.
4: The port pins for the primary COG1OUTx pins have High-Power (HP) output drivers.

PIC12F752/HV752
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 5
2.0 Memory Organization .................................................................................................................................................................. 7
3.0 Flash Program Memory Self Read/Self Write Control ............................................................................................................... 23
4.0 Oscillator Module ....................................................................................................................................................................... 32
5.0 I/O Ports .................................................................................................................................................................................... 37
6.0 Timer0 Module .......................................................................................................................................................................... 47
7.0 Timer1 Module with Gate Control .............................................................................................................................................. 50
8.0 Timer2 Module .......................................................................................................................................................................... 61
9.0 Hardware Limit Timer (HLT) Module ......................................................................................................................................... 63
10.0 Capture/Compare/PWM Modules .............................................................................................................................................. 67
11.0 Complementary Output Generator (COG) Module .................................................................................................................... 74
12.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 89
13.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 100
14.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................. 102
15.0 Comparator Module ................................................................................................................................................................. 107
16.0 Instruction Set Summary ......................................................................................................................................................... 116
17.0 Special Features of the CPU ................................................................................................................................................... 125
18.0 Shunt Regulator (PIC12HV752 Only) ...................................................................................................................................... 145
19.0 Development Support .............................................................................................................................................................. 146
20.0 Electrical Specifications ........................................................................................................................................................... 150
21.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 172
22.0 Packaging Information ............................................................................................................................................................. 196
Appendix A: Data Sheet Revision History ......................................................................................................................................... 206
Appendix B: Migrating from PIC12HV615 ......................................................................................................................................... 206
The Microchip Web Site .................................................................................................................................................................... 207
Customer Change Notification Service ............................................................................................................................................. 207
Customer Support .............................................................................................................................................................................. 207
Product Identification System ............................................................................................................................................................ 208
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PIC12F752/HV752
1.0 DEVICE OVERVIEW Block Diagrams and pinout descriptions of the devices
are in Figure 1-1 and Table 1-1.
The PIC12F752/HV752 devices are covered by this
data sheet. They are available in 8-pin PDIP, SOIC and
DFN packages.
FIGURE 1-1: PIC12F752/HV752 BLOCK DIAGRAM
INT
Configuration
13 8 PORTA
Data Bus
Program Counter
Flash RA0
1K X 14 RA1
Program RAM RA2
Memory 8-Level Stack 64 Bytes RA3
(13-Bit) File RA4
Registers RA5
Program
14
Bus RAM Addr 9
Addr MUX
Instruction Reg
Direct Addr 7 Indirect

8 Addr
FSR Reg
STATUS Reg
8
3
MUX
Instruction Power-up
Decode & Timer
ALU
Control Power-on
Reset 8
CLKIN Timing Watchdog
Timer W Reg Capture/
Generation Compare/
Brown-out PWM
CLKOUT
Reset (CCP)
Shunt Regulator Hardware

Internal Limit
Oscillator (PIC12HV752 only)
Timer1
Block (HLT)
MCLR VDD VSS
T1G
T1CKI
Timer0 Timer1 Timer2 Complementary
T0CKI Output
Generator
(COG)
Dual Range
DAC Analog Comparator
Fixed Voltage
Reference and Reference
(FVR)
C1OUT/C2OUT
C2IN1-
C1IN1-
C1IN0-/C2IN0-
C1IN0+/C2IN0+

PIC12F752/HV752
TABLE 1-1: PIC12F752/HV752 PINOUT DESCRIPTION
Input Output
Name Function Description
Type Type
RA0/COG1OUT1(2)/C1IN0+/ RA0 TTL HP General purpose I/O with IOC and WPU.
C2IN0+/AN0/DACOUT/ COG1OUT1 — HP COG output channel 1.
REFOUT/
C1IN0+ AN — Comparator C1 positive input.
ICSPDAT
C2IN0+ AN — Comparator C2 positive input.
AN0 AN — A/D Channel 0 input.
DACOUT — AN DAC unbuffered Voltage Reference output.
REFOUT — AN DAC/FVR buffered Voltage Reference output.
ICSPDAT ST HP Serial Programming Data I/O.
RA1/C1IN0-/C2IN0-/AN1/ RA1 TTL CMOS General purpose I/O with IOC and WPU.
VREF+/ICSPCLK C1IN0- AN — Comparator C1 negative input.
C2IN0- AN — Comparator C2 negative input.
VREF+ AN — A/D Positive Voltage Reference input.
ICSPCLK ST — Serial Programming Clock.
RA2/INT/CCP1/C2OUT/ RA2 ST HP General purpose I/O with IOC and WPU.
C1OUT/T0CKI/ INT ST — External interrupt.
COG1OUT0(2)/AN2
CCP1 ST HP Capture/Compare/PWM 1.
C2OUT — HP Comparator C2 output.
C1OUT — HP Comparator C1 output.
T0CKI ST — Timer0 clock input.
COG1OUT0 — HP COG output channel 0.
RA3(1)/T1G(3)/COG1FLT(3)/ RA3 TTL — General purpose input with IOC and WPU.
VPP/MCLR(4) T1G ST — Timer1 Gate input.
COG1FLT ST — COG auto-shutdown fault input.
VPP HV — Programming voltage.
MCLR ST — Master Clear w/internal pull-up.
RA4/T1G(2)/COG1OUT1(3)/ RA4 TTL CMOS General purpose I/O with IOC and WPU.
COG1FLT(2)/C1IN1-/AN3/ T1G ST — Timer1 Gate input.
CLKOUT
COG1OUT1 — CMOS COG output channel 1
COG1FLT ST — COG auto-shutdown fault input.
CLKOUT — CMOS FOSC/4 output.
RA5/T1CKI/COG1OUT0(3)/ RA5 TTL CMOS General purpose I/O with IOC and WPU.
C2IN1-/CLKIN T1CKI ST — Timer1 clock input.
COG1OUT0 — CMOS COG output channel 0.
CLKIN ST — External Clock input (EC mode).
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels
HP = High Power HV = High Voltage
Note 1: Input-only.
2: Default pin function via the APFCON register.
3: Alternate pin function via the APFCON register.
4: RA3 pull-up is enabled when pin is configured as MCLR in Configuration Word.

PIC12F752/HV752
2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization
The data memory (see Figure 2-1) is partitioned into four
2.1 Program Memory Organization banks, which contain the General Purpose Registers
The PIC12F752/HV752 has a 13-bit program counter (GPR) and the Special Function Registers (SFR). The
capable of addressing an 8K x 14 program memory Special Function Registers are located in the first 32
space. Only the first 1K x 14 (0000h-03FFh) is locations of each bank. Register locations 40h-6Fh in
physically implemented. Accessing a location above Bank 0 are General Purpose Registers, implemented as
these boundaries will cause a wrap-around within the static RAM. Register locations 70h-7Fh in Bank 0 are
first 1K x 14 space for PIC12F752/HV752. The Reset Common RAM and shared as the last 16 addresses in
vector is at 0000h and the interrupt vector is at 0004h all Banks. All other RAM is unimplemented and returns
(see Figure 2-1). ‘0’ when read. The RP<1:0> bits of the STATUS register
are the bank select bits.
FIGURE 2-1: PROGRAM MEMORY MAP RP1 RP0
AND STACK FOR THE 0 0  Bank 0 is selected
PIC12F752/HV752 0 1  Bank 1 is selected
PC<12:0> 1 0  Bank 2 is selected
CALL, RETURN 13 1 1  Bank 3 is selected
RETFIE, RETLW
2.2.1 GENERAL PURPOSE REGISTER
Stack Level 1 FILE
Stack Level 2
The register file is organized as 64 x 8 in the
PIC12F752/HV752. Each register is accessed, either
Stack Level 8 directly or indirectly, through the File Select Register
(FSR) (see Section 2.5 “Indirect Addressing, INDF
Reset Vector and FSR Registers”).
0000h
2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
Interrupt Vector 0004h the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
0005h
registers are static RAM.
On-chip Program The special registers can be classified into two sets:
Memory core and peripheral. The Special Function Registers
03FFh associated with the “core” are described in this section.
0400h Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
Wraps to 0000h-03FFh
1FFFh

PIC12F752/HV752
TABLE 2-1: DATA MEMORY MAP OF THE PIC12F752/HV752
BANK 0 BANK 1 BANK 2 BANK 3
INDF 00h INDF 80h INDF 100h INDF 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h LATA 105h ANSELA 185h
— 06h — 86h — 106h — 186h
— 07h — 87h — 107h — 187h
IOCAF 08h IOCAP 88h IOCAN 108h APFCON 188h
— 09h — 89h — 109h OSCTUNE 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch WPUA 10Ch PMCON1 18Ch
PIR2 0Dh PIE2 8Dh SLRCONA 10Dh PMCON2 18Dh
— 0Eh — 8Eh — 10Eh PMADRL 18Eh
TMR1L 0Fh OSCCON 8Fh PCON 10Fh PMADRH 18Fh
TMR1H 10h FVRCON 90h TMR2 110h PMDATL 190h
T1CON 11h DACCON0 91h PR2 111h PMDATH 191h
T1GCON 12h DACCON1 92h T2CON 112h COG1PH 192h
CCPR1L 13h — 93h HLTMR1 113h COG1BLK 193h
CCPR1H 14h — 94h HLTPR1 114h COG1DB 194h
CCP1CON 15h — 95h HLT1CON0 115h COG1CON0 195h
— 16h — 96h HLT1CON1 116h COG1CON1 196h
— 17h — 97h — 117h COG1ASD 197h
— 18h — 98h — 118h — 198h
— 19h — 99h — 119h — 199h
— 1Ah — 9Ah — 11Ah — 19Ah
— 1Bh CM2CON0 9Bh — 11Bh — 19Bh
ADRESL 1Ch CM2CON1 9Ch — 11Ch — 19Ch
ADRESH 1Dh CM1CON0 9Dh — 11Dh — 19Dh
ADCON0 1Eh CM1CON1 9Eh — 11Eh — 19Eh
ADCON1 1Fh CMOUT 9Fh — 11Fh — 19Fh
20h A0h 120h 1A0h
Unimplemented
3Fh
General 40h
Unimplemented Unimplemented Unimplemented
Purpose
Register
48 Bytes 6Fh EFh 16Fh 1EFh

Common RAM 70h Common RAM F0h Common RAM 170h Common RAM 1F0h
7Fh (Accesses FFh (Accesses 17Fh (Accesses 1FFh
16 Bytes 70h-7Fh) 70h-7Fh) 70h-7Fh)
Legend: = Unimplemented data memory locations, read as ‘0’.

PIC12F752/HV752
TABLE 2-2: PIC12F752/HV752 SPECIAL REGISTERS SUMMARY BANK 0
Value on Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR/BOR all other
Reset Resets(1)
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Holding register for the 8-bit TMR0 xxxx xxxx uuuu uuuu
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
04h FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
06h — Unimplemented — —
08h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000
0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF(2) 0000 0000 0000 0000
0Ch PIR1 TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 00---000 00---000
0Dh PIR2 — — C2IF C1IF — COG1IF — CCP1IF --00 -0-0 --00 -0-0
0Eh — Unimplemented — —
0Fh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
10h TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
11h T1CON TMR1CS<1:0> T1CKPS<1:0> Reserved T1SYNC — TMR1ON 0000 00-0 uuuu uu-u
12h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0> 0000 0x00 uuuu uxuu
DONE
13h CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx uuuu uuuu
14h CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx uuuu uuuu
15h CCP1CON — — DC1B<1:0> CCP1M<3:0> --00 0000 --00 0000
16h
to — Unimplemented — —
1Bh
1Ch ADRESL Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result xxxx xxxx uuuu uuuu
1Dh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx uuuu uuuu
1Eh ADCON0 ADFM VCFG CHS<3:0> GO/DONE ADON 0000 0000 0000 0000
1Fh ADCON1 — ADCS<2:0> — — — — -000 ---- -000 ----

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: MCLR and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the
mismatch exists.

PIC12F752/HV752
Value on Values on
Reset Resets(1)
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS<2:0> 1111 1111 1111 1111
85h TRISA — — TRISA5 TRISA4 TRISA3(3) TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
88h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000
8Ch PIE1 TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 00-- -000 00-- -000
8Dh PIE2 — — C2IE C1IE — COG1IE — CCP1IE --00 -0-0 --00 -0-0
8Fh OSCCON — — IRCF<1:0> — HTS LTS — --01 -00- --uu -uu-
90h FVRCON FVREN FVRRDY FVRBUFEN FVRBUFSS — — — — 0000 ---- 0000 ----
91h DACCON0 DACEN DACRNG DACOE — — DACPSS0 — — 000- -0-- 000- -0--
92h DACCON1 — — — DACR<4:0> ---0 0000 ---0 0000
93h
9Ah
9Bh CM2CON0 C2ON C2OUT C2OE C2POL C2ZLF C2SP C2HYS C2SYNC 0000 0100 0000 0100
9Ch CM2CON1 C2INTP C2INTN C2PCH<1:0> — — — C2NCH0 0000 ---0 0000 ---0
9Dh CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 0000 0100 0000 0100
9Eh CM1CON1 C1INTP C1INTN C1PCH<1:0> — — — C1NCH0 0000 ---0 0000 ---0
9Fh CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00
2: MCLR and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the mismatch
exists.
3: TRISA3 always reads ‘1’.

PIC12F752/HV752
Value on Value on
Reset Resets(1)
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
101h TMR0 Holding Register for the 8-bit Timer0 Register xxxx xxxx uuuu uuuu
105h LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu
108h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000
10Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --00 0000 --00 0000
10Dh SLRCONA — — — — — SLRA2 — SLRA0 ---- -0-0 ---- -0-0
10Fh PCON — — — — — — POR BOR ---- --qq ---- --uu
110h TMR2 Holding Register for the 8-bit Timer2 Register 0000 0000 0000 0000
111h PR2 Timer2 Period Register 1111 1111 1111 1111
112h T2CON — TOUTPS<3:0> TMR2ON T2CKPS<1:0> -000 0000 -000 0000
113h HLTMR1 Holding Register for the 8-bit Hardware Limit Timer1 Register 0000 0000 0000 0000
114h HLTPR1 Hardware Limit Timer1 Period Register 1111 1111 1111 1111
115h HLT1CON0 — H1OUTPS<3:0> H1ON H1CKPS<1:0> -000 0000 -000 0000
116h HLT1CON1 — — — H1ERS<2:0> H1FEREN H1REREN ---0 0000 ---0 0000
117h
11Fh
2: MCLR and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the
mismatch exists.

PIC12F752/HV752
TABLE 2-5: PIC12F752/HV752 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Value on Values on
Reset Resets(1)
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
181h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS<2:0> 1111 1111 1111 1111
185h ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 --11 -111 --11 -111
188h APFCON — — — T1GSEL — COG1FSEL COG1O1SEL COG1O0SEL ---0 -000 ---0 -000
189h OSCTUNE — — — TUN<4:0> ---0 0000 ---u uuuu

18Ch PMCON1 — — — — — WREN WR RD ---- -000 ---- -000
18Dh PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ----
18Eh PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000
18Fh PMADRH — — — — — — PMADRH<1:0> ---- --00 ---- --00
190h PMDATL Program Memory Data Register Low Byte 0000 0000 0000 0000
191h PMDATH — — Program Memory Data Register High Byte --00 0000 --00 0000
192h COG1PH — — — — G1PH<3:0> ---- xxxx ---- uuuu
193h COG1BLK G1BLKR<3:0> G1BLKF<3:0> xxxx xxxx uuuu uuuu

194h COG1DB G1DBR<3:0> G1DBF<3:0> xxxx xxxx uuuu uuuu
195h COG1CON0 G1EN G1OE1 G1OE0 G1POL1 G1POL0 G1LD G1CS<1:0> 0000 0000 0000 0000
196h COG1CON1 G1FSIM G1RSIM G1FS<2:0> G1RS<2:0> 0000 0000 0000 0000
197h COG1ASD G1ASDE G1ARSEN G1ASDL1 G1ASDL0 G1ASDSHLT G1ASDSC2 G1ASDSC1 G1ASDSFLT 0000 0000 0000 0000
198h
19Fh
2: MCLR and WDT Reset does not affect the previous value data latch. The IOCIF bit will be cleared upon Reset but will set again if the mismatch exists.

PIC12F752/HV752
2.3 Global SFRs writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
2.3.1 STATUS REGISTER intended.
The STATUS register, shown in Register 2-1, contains: For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
• The Arithmetic Status of the ALU
as ‘000u u1uu’ (where u = unchanged).
• The Reset Status
It is recommended, therefore, that only BCF, BSF,
• The Bank Select Bits for Data Memory (RAM)
SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any STATUS register, because these instructions do not
instruction, like any other register. If the STATUS affect any Status bits. For other instructions not
register is the destination for an instruction that affects affecting any Status bits, see Section 16.0
the Z, DC or C bits, then the write to these three bits is “Instruction Set Summary”.
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
REGISTER 2-1: STATUS: STATUS REGISTER

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
(1)
IRP RP1 RP0 TO PD Z DC C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6 RP1: Register Bank Select bit (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 5 RP0: Register Bank Select bit (used for direct addressing)
1 = Bank 1 (80h-FFh)
0 = Bank 0 (00h-7Fh)
bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit(2) (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed.
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(2) (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: The C and DC bits operate as a Borrow and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
2: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

PIC12F752/HV752
2.3.2 OPTION REGISTER
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
• Timer0/WDT Prescaler
• External RA2/INT Interrupt
• Timer0
• Weak Pull-ups on PORTA
Note: To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting PSA bit to ‘1’ of the OPTION
register. See Section 6.1.3 “Software
Programmable Prescaler”.
REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RAPU INTEDG T0CS T0SE PSA PS<2:0>
bit 7 bit 0
Legend:
bit 7 RAPU: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
BIT VALUE TIMER0 RATE WDT RATE
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

PIC12F752/HV752
2.3.3 INTCON REGISTER
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, IOCIE change and external
RA2/INT pin interrupts.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF
bit 7 bit 0
Legend:
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: RA2/INT External Interrupt Enable bit
1 = Enables the RA2/INT external interrupt
0 = Disables the RA2/INT external interrupt
bit 3 IOCIE: Interrupt-on-Change Interrupt Enable bit(1)
1 = Enables the IOC change interrupt
0 = Disables the IOC change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = Timer0 register has overflowed (must be cleared in software)
0 = Timer0 register did not overflow
bit 1 INTF: RA2/INT External Interrupt Flag bit
1 = The RA2/INT external interrupt occurred (must be cleared in software)
0 = The RA2/INT external interrupt did not occur
bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit
1 = An IOC pin has changed state and generated an interrupt
0 = No pin interrupts have been generated
Note 1: IOC register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.

PIC12F752/HV752
2.3.4 PIE1 REGISTER
The PIE1 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-4.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE
bit 7 bit 0
Legend:
bit 7 TMR1GIE: ADC Interrupt Enable bit

1 = Enables the TMR1 gate interrupt
0 = Disables the TMR1 gate interrupt
bit 6 ADIE: ADC Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5-3 Unimplemented: Read as ‘0’
bit 2 HLTMR1IE: Hardware Limit Timer1 Interrupt Enable bit
1 = Enables the HLTMR1 interrupt
0 = Disables the HLTMR1 interrupt
bit 1 TMR2IE: Timer2 Interrupt Enable bit
bit 0 TMR1IE: Timer1 Interrupt Enable bit

PIC12F752/HV752
2.3.5 PIE2 REGISTER
The PIE2 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-5.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
— — C2IE C1IE — COG1IE — CCP1IE
bit 7 bit 0
Legend:

bit 5 C2IE: Comparator 2 Interrupt Enable bit
1 = Enables the Comparator 2 interrupt
0 = Disables the Comparator 2 interrupt
bit 4 C1IE: Comparator 1 Interrupt Enable bit
1 = Enables the Comparator 1 interrupt
0 = Disables the Comparator 1 interrupt
bit 3 Unimplemented: Read as ‘0’
bit 2 COG1IE: COG 1 Interrupt Flag bit
1 = COG1 interrupt enabled
0 = COG1 interrupt disabled
bit 0 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

PIC12F752/HV752
2.3.6 PIR1 REGISTER
The PIR1 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-6.
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF
bit 7 bit 0
Legend:
bit 7 TMR1GIF: TMR1 Gate Interrupt Flag bit

1 = Timer1 gate interrupt is pending
0 = Timer1 gate interrupt is not pending
bit 6 ADIF: ADC Interrupt Flag bit
1 = ADC conversion complete
0 = ADC conversion has not completed or has not been started
bit 2 HLTMR1IF: Hardware Limit Timer1 to HLTPR1 Match Interrupt Flag bit
1 = HLTMR1 to HLTPR1 match occurred (must be cleared in software)
0 = HLTMR1 to HLTPR1 match did not occur
bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag bit
1 = Timer2 to PR2 match occurred (must be cleared in software)
0 = Timer2 to PR2 match did not occur
bit 0 TMR1IF: Timer1 Interrupt Flag bit
1 = Timer1 rolled over (must be cleared in software)
0 = Timer1 has not rolled over

PIC12F752/HV752
2.3.7 PIR2 REGISTER
The PIR2 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-7.
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 1

U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
— — C2IF C1IF COG1IF — CCP1IF
bit 7 bit 0
Legend:

bit 5 C2IF: Comparator 1 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 4 C1IF: Comparator 1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 2 COG1IF: COG 1 Interrupt Flag bit
1 = COG1 has generated an auto-shutdown interrupt
0 = COG1 has NOT generated an auto-shutdown interrupt
bit 0 CCP1IF: ECCP Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode
Unused in this mode

PIC12F752/HV752
2.3.8 PCON REGISTER
The Power Control (PCON) register (see Table 17-2)
contains flag bits to differentiate between:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON register also controls the software enable of
the BOR.
The PCON register bits are shown in Register 2-8.
REGISTER 2-8: PCON: POWER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-q/u R/W-q/u
— — — — — — POR BOR
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

PIC12F752/HV752
2.4 PCL and PCLATH 2.4.2 STACK
The Program Counter (PC) is 13 bits wide. The low byte The PIC12F752/HV752 Family has an 8-level x 13-bit
comes from the PCL register, which is a readable and wide hardware stack (see Figure 2-1). The stack space
writable register. The high byte (PC<12:8>) is not directly is not part of either program or data space and the
readable or writable and comes from PCLATH. On any Stack Pointer is not readable or writable. The PC is
Reset, the PC is cleared. Figure 2-2 shows the two PUSHed onto the stack when a CALL instruction is exe-
situations for the loading of the PC. The upper example cuted or an interrupt causes a branch. The stack is
in Figure 2-2 shows how the PC is loaded on a write to POPed in the event of a RETURN, RETLW or a RETFIE
PCL (PCLATH<4:0>  PCH). The lower example in instruction execution. PCLATH is not affected by a
Figure 2-2 shows how the PC is loaded during a CALL or PUSH or POP operation.
GOTO instruction (PCLATH<4:3>  PCH). The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
FIGURE 2-2: LOADING OF PC IN push overwrites the value that was stored from the first
DIFFERENT SITUATIONS push. The tenth push overwrites the second push (and
so on).
PCH PCL
Instruction with
12 8 7 0 PCL as
Note 1: There are no Status bits to indicate Stack
PC Destination Overflow or Stack Underflow conditions.
PCLATH<4:0> 8 2: There are no instructions/mnemonics

5 ALU Result called PUSH or POP. These are actions
that occur from the execution of the
PCLATH CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
PCH PCL interrupt address.
12 11 10 8 7 0
PC GOTO, CALL
2.5 Indirect Addressing, INDF and
2
PCLATH<4:3> 11
OPCODE <10:0>
FSR Registers
The INDF register is not a physical register. Addressing
PCLATH the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
2.4.1 MODIFYING PCL register. Any instruction using the INDF register
Executing any instruction with the PCL register as the actually accesses data pointed to by the File Select
destination simultaneously causes the Program Register (FSR). Reading INDF itself indirectly will
Counter PC<12:8> bits (PCH) to be replaced by the produce 00h. Writing to the INDF register indirectly
contents of the PCLATH register. This allows the entire results in a no operation (although Status bits may be
contents of the program counter to be changed by affected). An effective 9-bit address is obtained by
writing the desired upper five bits to the PCLATH concatenating the 8-bit FSR and the IRP bit of the
register. When the lower eight bits are written to the STATUS register, as shown in Figure 2-3.
PCL register, all 13 bits of the program counter will A simple program to clear RAM location 40h-7Fh using
change to the values contained in the PCLATH register indirect addressing is shown in Example 2-1.
and those being written to the PCL register.
A computed GOTO is accomplished by adding an offset EXAMPLE 2-1: INDIRECT ADDRESSING
to the program counter (ADDWF PCL). Care should be MOVLW 0x40 ;initialize pointer
exercised when jumping into a look-up table or MOVWF FSR ;to RAM
program branch table (computed GOTO) by modifying NEXT CLRF INDF ;clear INDF register
the PCL register. Assuming that PCLATH is set to the INCF FSR ;inc pointer
table start address, if the table length is greater than BTFSS FSR,7 ;all done?
GOTO NEXT ;no clear next
255 instructions or if the lower eight bits of the memory
CONTINUE ;yes continue
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).

PIC12F752/HV752
FIGURE 2-3: DIRECT/INDIRECT ADDRESSING PIC12F752/HV752
Direct Addressing Indirect Addressing
RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0
Bank Select Location Select Bank Select Location Select

00 01 10 11
00h 180h
Data
Memory
7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Note: For memory map detail, see Figure 2-1.

PIC12F752/HV752
3.0 FLASH PROGRAM MEMORY 3.1 PMADRH and PMADRL Registers
SELF READ/SELF WRITE The PMADRH and PMADRL registers can address up
CONTROL to a maximum of 1K words of program memory.
The Flash program memory is readable and writable When selecting a program address value, the Most
during normal operation (full VDD range). This memory Significant Byte (MSB) of the address is written to the
is not directly mapped in the register file space. PMADRH register and the Least Significant Byte
Instead, it is indirectly addressed through the Special (LSB) is written to the PMADRL register.
Function Registers (see Registers 3-1 to 3-5). There
are six SFRs used to read and write this memory: 3.2 PMCON1 and PMCON2 Registers
• PMCON1 PMCON1 is the control register for the data program
• PMCON2 memory accesses.
• PMDATL Control bits RD and WR initiate read and write,
• PMDATH respectively. These bits cannot be cleared, only set in
• PMADRL software. They are cleared in hardware at completion
• PMADRH of the read or write operation. The inability to clear the
WR bit in software prevents the accidental premature
When interfacing the program memory block, the termination of a write operation.
PMDATL and PMDATH registers form a 2-byte word
which holds the 14-bit data for read/write, and the The WREN bit, when set, will allow a write operation.
PMADRL and PMADRH registers form a 2-byte word On power-up, the WREN bit is clear.
which holds the 10-bit address of the Flash location PMCON2 is not a physical register. Reading PMCON2
being accessed. These devices have 1K words of pro- will read all ‘0’s. The PMCON2 register is used
gram Flash with an address range from 0000h to exclusively in the Flash memory write sequence.
03FFh.
The program memory allows single word read and a
by four word write. A four word write automatically
erases the row of the location and writes the new data
(erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range
of the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the Flash program memory.
Depending on the settings of the Flash Program
Memory Enable (WRT<1:0>) bits, the device may or
may not be able to write certain blocks of the program
memory, however, reads of the program memory are
allowed.
When the Flash program memory Code Protection
(CP) bit in the Configuration Word register is enabled,
the program memory is code-protected, and the
device programmer (ICSP™) cannot access data or
program memory.

PIC12F752/HV752
3.3 Flash Program Memory Control Registers
REGISTER 3-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

PMDATL<7:0>
bit 7 bit 0
Legend:
bit 7-0 PMDATL<7:0>: Eight Least Significant Data bits to Write or Read from Program Memory
REGISTER 3-2: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

PMADRL<7:0>
bit 7 bit 0
Legend:
bit 7-0 PMADRL<7:0>: Eight Least Significant Address bits for Program Memory Read/Write Operation
REGISTER 3-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — PMDATH<5:0>
bit 7 bit 0
Legend:

bit 5-0 PMDATH<5:0>: Six Most Significant Data bits from Program Memory
REGISTER 3-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — PMADRH<1:0>
bit 7 bit 0
Legend:

bit 1-0 PMADRH<1:0>: Specifies the two Most Significant Address bits or High bits for Program Memory
Reads.

PIC12F752/HV752
REGISTER 3-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
— — — — — WREN WR RD
bit 7 bit 0
Legend:
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware

bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1 WR: Write Control bit
1 = Initiates a program Flash program/erase operation
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive
bit 0 RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software.
0 = Does not initiate a program Flash read
Note 1: Unimplemented bit, read as ‘1’.

PIC12F752/HV752
3.4 Reading the Flash Program
Memory
To read a program memory location, the user must
write two bytes of the address to the PMADRL and
PMADRH registers, and then set control bit RD
(PMCON1<0>). Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle after to read the data. This causes the
second instruction immediately following the “BSF
PMCON1,RD” instruction to be ignored. The data is
available in the very next cycle in the PMDATL and
PMDATH registers; it can be read as two bytes in the
following instructions. PMDATL and PMDATH
registers will hold this value until another read or until it
is written to by the user (during a write operation).
EXAMPLE 3-1: FLASH PROGRAM READ

BANKSEL PM_ADR ; Change STATUS bits RP1:0 to select bank with PMADRL
MOVLW MS_PROG_PM_ADDR ;
MOVWF PMADRH ; MS Byte of Program Address to read
MOVLW LS_PROG_PM_ADDR ;
MOVWF PMADRL ; LS Byte of Program Address to read
BANKSEL PMCON1 ; Bank to containing PMCON1
BSF PMCON1, RD ; PM Read
NOP ; First instruction after BSF PMCON1,RD executes normally
NOP ; Any instructions here are ignored as program

; memory is read in second cycle after BSF PMCON1,RD
;
BANKSEL PMDATL ; Bank to containing PMADRL
MOVF PMDATL, W ; W = LS Byte of Program PMDATL
MOVF PMDATH, W ; W = MS Byte of Program PMDATL

PIC12F752/HV752
FIGURE 3-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR PC PC + 1 PMADRH,PMADRL PC+3

PC +3 PC + 4 PC + 5
Flash DATA INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4)
INSTR (PC - 1) BSF PMCON1,RD INSTR (PC + 1) NOP INSTR (PC + 3) INSTR (PC + 4)
Executed here Executed here Executed here Executed here Executed here Executed here
RD bit
PMDATH
PMDATL
Register
PMRHLT

PIC12F752/HV752
3.5 Writing the Flash Program which the erase takes place (i.e., the last word of the
Memory sixteen-word block erase). This is not Sleep mode as
the clocks and peripherals will continue to run. After
A word of the Flash program memory may only be the four-word write cycle, the processor will resume
written to if the word is in an unprotected segment of operation with the third instruction after the PMCON1
memory. write instruction. The above sequence must be
Flash program memory must be written in four-word repeated for the higher 12 words.
blocks. See Figure 3-2 and Figure 3-3 for more details.
A block consists of four words with sequential 3.6 Protection Against Spurious Write
addresses, with a lower boundary defined by an
There are conditions when the device should not write
address, where PMADRL<1:0> = 00. All block writes to
to the program memory. To protect against spurious
program memory are done as 16-word erase by
writes, various mechanisms have been built in. On
four-word write operations. The write operation is
power-up, WREN is cleared. Also, the Power-up Timer
edge-aligned and cannot occur across boundaries.
(64 ms duration) prevents program memory writes.
To write program data, it must first be loaded into the
The write initiate sequence and the WREN bit help
buffer registers (see Figure 3-2). This is accomplished
prevent an accidental write during brown-out, power
by first writing the destination address to PMADRL and
glitch or software malfunction.
PMADRH and then writing the data to PMDATL and
PMDATH. After the address and data have been set
up, then the following sequence of events must be 3.7 Operation During Code-Protect
executed: When the device is code-protected, the CPU is able to
1. Write 55h, then AAh, to PMCON2 (Flash read and write unscrambled data to the program
programming sequence). memory.
2. Set the WR control bit of the PMCON1 register.
All four buffer register locations should be written to 3.8 Operation During Write Protect
with correct data. If less than four words are being When the program memory is write-protected, the
written to in the block of four words, then a read from CPU can read and execute from the program memory.
the program memory location(s) not being written to The portions of program memory that are write
must be performed. This takes the data from the protected can be modified by the CPU using the
program location(s) not being written and loads it into PMCON registers, but the protected program memory
the PMDATL and PMDATH registers. Then the cannot be modified using ICSP mode.
sequence of events to transfer data to the buffer
registers must be executed.
To transfer data from the buffer registers to the program
memory, the PMADRL and PMADRH must point to the
last location in the four-word block
(PMADRL<1:0> = 11). Then the following sequence of
events must be executed:
1. Write 55h, then AAh, to PMCON2 (Flash
programming sequence).
2. Set control bit WR of the PMCON1 register to
begin the write operation.
The user must follow the same specific sequence to
initiate the write for each word in the program block,
writing each program word in sequence (000, 001,
010, 011). When the write is performed on the last
word (PMADRL<1:0> = 11), a block of sixteen words is
automatically erased and the content of the four-word
buffer registers are written into the program memory.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOP instructions after the WR
bit is set. Since data is being written to buffer registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operations for the typical 4 ms, only during the cycle in

PIC12F752/HV752
FIGURE 3-2: BLOCK WRITES TO 1K FLASH PROGRAM MEMORY
7 5 0 7 0 If at a new row
PMDATH PMDATL sixteen words of
Flash are erased,
then four buffers
6 8 are transferred
to Flash
automatically
First word of block after this word
to be written is written
14 14 14 14
PMADRL<1:0> = 00 PMADRL<1:0> = 01 PMADRL<1:0> = 10 PMADRL<1:0> = 11
Buffer Register Buffer Register Buffer Register Buffer Register
Program Memory
FIGURE 3-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash PC + 1 PMADRH,PMADRL PC + 2 PC + 3 PC + 4
ADDR
INSTR INSTR ignored

Flash read PMDATH,PMDATL INSTR (PC+2) INSTR (PC+3)
DATA (PC) (PC + 1)
Processor halted (INSTR (PC + 2)

BSF PMCON1,WR INSTR (PC + 1) NOP INSTR (PC + 3)
Executed here PM Write Time NOP
Executed here Executed here Executed here Executed here
Flash
Memory
Location
WR bit
PMWHLT

PIC12F752/HV752
An example of the complete four-word write sequence
is shown in Example 3-2. The initial address is loaded
into the PMADRH and PMADRL register pair; the four
words of data are loaded using indirect addressing.
EXAMPLE 3-2: WRITING TO FLASH PROGRAM MEMORY

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This write routine assumes the following:
; A valid starting address (the least significant bits = '00')
; is loaded in ADDRH:ADDRL
; ADDRH, ADDRL and DATADDR are all located in data memory
;
BANKSEL PMADRH
MOVF ADDRH,W ;Load initial address
MOVWF PMADRH ;
MOVF ADDRL,W ;
MOVWF PMADRL ;
MOVF DATAADDR,W ;Load initial data address
MOVWF FSR ;
LOOP MOVF INDF,W ;Load first data byte into lower
MOVWF PMDATL ;
INCF FSR,F ;Next byte
MOVF INDF,W ;Load second data byte into upper
MOVWF PMDATH ;
INCF FSR,F ;
BANKSEL PMCON1
BSF PMCON1,WREN ;Enable writes
BCF INTCON,GIE ;Disable interrupts (if using)
BTFSC INTCON,GIE ;See AN576
GOTO $-2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Required Sequence
MOVLW 55h ;Start of required write sequence:
MOVWF PMCON2 ;Write 55h
MOVLW 0AAh ;
MOVWF PMCON2 ;Write 0AAh
BSF PMCON1,WR ;Set WR bit to begin write
NOP ;Required to transfer data to the buffer
NOP ;registers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
BCF PMCON1,WREN ;Disable writes
BSF INTCON,GIE ;Enable interrupts (comment out if not using interrupts)
BANKSEL PMADRL
MOVF PMADRL, W
INCF PMADRL,F ;Increment address
ANDLW 0x03 ;Indicates when sixteen words have been programmed
SUBLW 0x03 ;Change value for different size write blocks
;0x0F = 16 words
;0x0B = 12 words
;0x07 = 8 words
;0x03 = 4 words
BTFSS STATUS,Z ;Exit on a match,
GOTO LOOP ;Continue if more data needs to be written

PIC12F752/HV752
TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
PMCON1 — — — — — WREN WR RD 25
PMCON2 Program Memory Control Register 2 23*
PMADRL PMADRL<7:0> 24
PMADRH — — — — — — PMADRH<1:0> 24
PMDATL PMDATL<7:0> 24
PMDATH — — PMDATH<5:0> 24
INTCON GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF 15
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.
* Page provides register information.
TABLE 3-2: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Register
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0
on Page
13:8 — — DEBUG CLKOUTEN WRT<1:0> BOREN<1:0>

CONFIG 126
7:0 — CP MCLRE PWRTE WDTE — — FOSC0
Legend: — = unimplemented location, read as ‘1’. Shaded cells are not used by Flash program memory.

PIC12F752/HV752
4.0 OSCILLATOR MODULE The internal oscillator module provides the following
selectable System Clock modes:
4.1 Overview • 8 MHz (HFINTOSC)
• 4 MHz (HFINTOSC Postscaler)
The oscillator module has a variety of clock sources
and selection features that allow it to be used in a wide • 1 MHz (HFINTOSC Postscaler)
range of applications while maximizing performance • 31 kHz (LFINTOSC)
and minimizing power consumption. Figure 4-1
illustrates a block diagram of the oscillator module.
The oscillator module can be configured in one of two
clock modes.
1. EC (External Clock)
2. INTOSC (Internal Oscillator)
Clock Source modes are configured by the FOSC bit in
the Configuration Word register (CONFIG).
FIGURE 4-1: PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
EC Enable
(Figure 4-2)
EC
CLKIN 1
Internal Oscillator Prescaler
MUX
÷1 11 System Clock
(CPU and
HFINTOSC Enable HFINTOSC Peripherals)
÷2 10
(Figure 4-2) 8 MHz 0
÷8 01
LFINTOSC Enable LFINTOSC 00 FOSC

31 kHz
(Figure 4-2)
IRCF<1:0>
COG Clock Source
WDT Clock Source
FIGURE 4-2: OSCILLATOR ENABLE
FOSC0
EC Enable
Sleep
FOSC0
IRCF<1:0>  00 HFINTOSC Enable
Sleep
FOSC0
IRCF<1:0> = 00
Sleep LFINTOSC Enable
WDTE

PIC12F752/HV752
4.2 Clock Source Modes 4.2.2 INTERNAL CLOCK MODE
Clock Source modes can be classified as external or Internal Clock mode configures the internal oscillators
internal: as the system clock source. The Internal Clock mode is
selected when the FOSC0 bit of the Configuration
• The External Clock mode relies on an external Word is cleared. The source and frequency are
clock for the clock source, such as a clock module selected with the IRCF<1:0> bits of the OSCCON
or clock output from another circuit. register.
• Internal clock sources are contained internally
When one of the HFINTOSC frequencies is selected,
within the oscillator module. The oscillator module
the frequency of the internal oscillator can be trimmed
has four selectable clock frequencies:
by adjusting the TUN<4:0> bits of the OSCTUNE
- 8 MHz register.
- 4 MHz
Operation after a Power-on Reset (POR) or wake-up
- 1 MHz from Sleep is delayed by the oscillator start-up time.
- 31 kHz Delays are typically longer for the LFINTOSC than
The system clock can be selected between external or HFINTOSC because of the very low-power operation
internal clock sources via the FOSC0 bit of the and relatively narrow bandwidth of the LF internal
Configuration Word register (CONFIG). oscillator. However, when another peripheral keeps the
oscillator running during Sleep, the start-up time is
4.2.1 EC MODE delayed to allow the memory bias to stabilize.
The External Clock (EC) mode allows an externally
generated logic as the system clock source. The EC FIGURE 4-4: INTERNAL CLOCK MODE
clock mode is selected when the FOSC0 bit of the OPERATION
Configuration Word is set.
When operating in this mode, an external clock source I/O CLKIN(1)
must be connected to the CLKIN input. The CLKOUT is
PIC® MCU
available for either general purpose I/O or system clock
output. Figure 4-3 shows the pin connections for EC I/O CLKOUT(1)
mode.
Because the PIC® MCU design is fully static, stopping
Note 1: Alternate pin functions are listed in the
the external clock input will have the effect of halting the
Section 1.0 “Device Overview”.
device while leaving all data intact. Upon restarting the
external clock, the device will resume operation as if no
time had elapsed. 4.2.2.1 Oscillator Ready Bits
The HTS and LTS bits of the OSCCON register indicate
FIGURE 4-3: EXTERNAL CLOCK (EC) the status of the HFINTOSC and LFINTOSC,
MODE OPERATION respectively. When either bit is set, it indicates that the
corresponding oscillator is running and stable.
Clock from CLKIN

Ext. System
PIC® MCU
I/O CLKOUT(1)
Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

PIC12F752/HV752
4.3 System Clock Output 4.4 Oscillator Delay upon Wake-Up,
The CLKOUT pin is available for general purpose I/O or
Power-Up, and Base Frequency
system clock output. The CLKOUTEN bit of the Change
Configuration Word controls the function of the In applications where the OSCTUNE register is used to
CLKOUT pin. shift the HFINTOSC frequency, the application should
When the CLKOUTEN bit is cleared, the CLKOUT pin not expect the frequency to stabilize immediately. In
is driven by the selected internal oscillator frequency this case, the frequency may shift gradually toward the
divided by 4. The corresponding I/O pin always reads new value. The time for this frequency shift is less than
‘0’ in this configuration. eight cycles of the base frequency.
The CLKOUT signal may be used to provide a clock for A short delay is invoked upon power-up and when
external circuitry, synchronization, calibration, test or waking from sleep to allow the memory bias circuitry to
other application requirements. stabilize. Table 4-1 shows examples where the oscillator
When the CLKOUTEN bit is set, the system clock out delay is invoked.
function is disabled and the CLKOUT pin is available for
general purpose I/O.
TABLE 4-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay
Sleep/POR INTOSC 31 kHz to 8 MHz 10 s internal delay to allow memory
Sleep/POR EC DC – 20 MHz bias to stabilize.

PIC12F752/HV752
4.5 Oscillator Control Registers
REGISTER 4-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 U-0 R/W-0/u R/W-1/u U-0 R-0/u R-0/u U-0
— — IRCF<1:0> — HTS LTS —
bit 7 bit 0
Legend:
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared u = Bit is unchanged

bit 5-4 IRCF<1:0>: Internal Oscillator Frequency Select bits
11 = 8 MHz
10 = 4 MHz
01 = 1 MHz (Reset default)
00 = 31 kHz (LFINTOSC)
bit 2 HTS: HFINTOSC Status bit
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC Status bit
1 = LFINTOSC is stable
0 = LFINTOSC is not stable

PIC12F752/HV752
4.5.1 OSCTUNE REGISTER When the OSCTUNE register is modified, the frequency
will begin shifting to the new frequency. Code execution
The oscillator is factory-calibrated, but can be adjusted
continues during this shift. There is no indication that the
in software by writing to the OSCTUNE register
shift has occurred.
(Register 4-2).
The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number.
REGISTER 4-2: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 U-0 R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u
— — — TUN<4:0>
bit 7 bit 0
Legend:

bit 4-0 TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Oscillator module is running at the calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency
TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register
on Page
OSCCON — — IRCF<1:0> — HTS LTS — 35
OSCTUNE — — — TUN<4:0> 36
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
oscillators.
2: See Configuration Word register (Register 17-1) for operation of all register bits.
TABLE 4-3: SUMMARY OF CONFIGURATION WORD CLOCK SOURCES

Register
on Page

CONFIG 126
Legend: — = unimplemented location, read as ‘1’. Shaded cells are not used by oscillator module.

PIC12F752/HV752
5.0 I/O PORTS EXAMPLE 5-1: INITIALIZING PORTA
; This code example illustrates
For this device there is one port available, PORTA. In ; initializing the PORTA register. The
general, when a peripheral is enabled on a port pin, ; other ports are initialized in the same
that pin cannot be used as a general purpose output. ; manner.
However, the pin can still be read.
PORTA has three standard registers for its operation. BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
These registers are:
BANKSEL LATA ;Data Latch
• TRISA Registers (data direction) CLRF LATA ;
• PORTA Registers (read the levels on the pins of BANKSEL ANSELA ;
the device) CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
• LATA Registers (output latch) MOVLW B'00111000' ;Set RA<5:3> as inputs
Some ports may have one or more of the following MOVWF TRISA ;and set RA<2:0> as
additional registers. These registers are: ;outputs
• ANSELA (Analog Select)

• WPUA (Weak Pull-up)
The Data Latch (LATA register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATA register has the same
effect as a write to the corresponding PORTA register.
A read of the LATA register reads the values held in the
I/O PORT latches, while a read of the PORTA register
reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSEL register. When an ANSELA bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 5-1.
FIGURE 5-1: GENERIC I/O PORTA

OPERATION
Read LATA
TRISA
D Q
Write LATA
Write PORTA
CK VDD
Data Register
Data Bus
I/O pin
Read PORTA
To peripherals
VSS
ANSELA

PIC12F752/HV752
5.1 Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 5-1. For this device family, the
following functions can be moved between different
pins:
• Timer1 Gate
• COG1
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
5.2 Alternate Pin Function Control Register

REGISTER 5-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — T1GSEL — COG1FSEL COG1O1SEL COG1O0SEL
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-5 Unimplemented: Read as ‘0’.

bit 4 T1GSEL: Timer 1 Gate Input Pin Selection bit
1 = T1G function is on RA3
0 = T1G function is on RA4
bit 3 Unimplemented: Read as ‘0’.
bit 2 COG1FSEL: COG1 Fault Input Pin Selection bit
1 = COG1FLT is on RA3
0 = COG1FLT is on RA4
bit 1 COG1O1SEL: COG1 Output 1 Pin Selection bit
1 = COG1OUT1 is on RA4
bit 0 COG1O0SEL: COG1 Output 0 Pin Selection bit

PIC12F752/HV752
5.3 PORTA and TRISA Registers
TABLE 5-1: PORTA OUTPUT PRIORITY
PORTA is a 6-bit-wide port with five bidirectional pins and
one input-only pin. The corresponding data direction Pin Name Function Priority(1)
register is TRISA (Register 5-2). Setting a RA0 ICSPDAT
TRISA bit (= 1) will make the corresponding PORTA pin REFOUT
an input (i.e., disable the output driver). Clearing a DACOUT
TRISA bit (= 0) will make the corresponding PORTA pin COG1OUT1(2)
an output (i.e. it enables output driver and puts the RA0
contents of the output latch on the selected pin). The RA1 RA1
exception is RA3, which is input only and its TRIS bit will RA2 COG1OUT0(2)
always read as ‘1’. Example 5-1 shows how to initialize C1OUT
PORTA. C2OUT
Reading the PORTA register (Register 5-2) reads the CCP1
RA2
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write RA3 None
operations. Therefore, a write to a port implies that the RA4 CLKOUT
port pins are read, the read value is modified and then COG1OUT1(3)
written to the PORT data latch. RA3 reads ‘0’ when RA4
MCLRE = 1. RA5 COG1OUT0(3)
RA5
The TRISA register controls the direction of the
PORTA pins, even when they are being used as analog Note 1: Priority listed from highest to lowest.
inputs. The user must ensure the bits in the TRISA 2: Default function pin (see APFCON register).
register are maintained set when using them as analog 3: Alternate function pin (see APFCON register).
inputs. I/O pins configured as analog input always read
‘0’.
Note: The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’ and cannot generate an interrupt.
5.3.1 PORTA FUNCTIONS AND OUTPUT

PRIORITIES
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 5-1.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as comparator inputs, are
not shown in the priority lists. These inputs are active
when the peripheral is enabled and the input multiplexer
for the pin is selected. The Analog mode, set with the
ANSELA register, disables the digital input buffer
thereby preventing excessive input current when the
analog input voltage is between logic states. Digital
output functions may control the pin when it is in Analog
mode with the priority shown in Table 5-1.

PIC12F752/HV752
5.4 PORTA Control Registers
REGISTER 5-2: PORTA: PORTA REGISTER
U-0 U-0 R/W-x/u R/W-x/u R-x/x R/W-x/u R/W-x/u R/W-x/u
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:

bit 5-0 RA<5:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to any PORTx register are written to the corresponding LATx register. Reads from any PORTx register, return
the value present on that PORTx I/O pins.
REGISTER 5-3: TRISA: PORTA TRI-STATE REGISTER

U-0 U-0 R/W-1/1 R/W-1/1 R-1/1 R/W-1/1 R/W-1/1 R/W-1/1
— — TRISA5 TRISA4 TRISA3(1) TRISA2 TRISA1 TRISA0
bit 7 bit 0
Legend:

bit 5-0 TRISA<5:0>: PORTA Tri-State Control bits(1)
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1: TRISA3 always reads ‘1’.
REGISTER 5-4: LATA: PORTA DATA LATCH REGISTER

U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u
— — LATA5 LATA4 — LATA2 LATA1 LATA0
bit 7 bit 0
Legend:

bit 5-4 LATA<5:4>: PORTA Output Latch Value bits(1)
bit 2-0 LATA<2:0>: PORTA Output Latch Value bits(1)
Note 1: Writes to any PORTx register are written to the corresponding LATx register. Reads from any PORTx register, return
the value present on that PORTx I/O pins.

PIC12F752/HV752
5.5 Additional Pin Functions
Every PORTA pin on the PIC12F752 has an
interrupt-on-change option and a weak pull-up option.
The next three sections describe these functions.
5.5.1 ANSELA REGISTER

The ANSELA register (Register 5-8) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note: The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
REGISTER 5-5: ANSELA: PORTA ANALOG SELECT REGISTER

U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1
— — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0
bit 7 bit 0
Legend:

bit 5-4 ANSA<5:4>: Analog Select Between Analog or Digital Function on Pin RA<5:4> bits
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.
bit 2-0 ANSA<2:0>:Analog Select Between Analog or Digital Function on Pin RA<2:0> bits
1 = Analog input. Pin is assigned as analog input.(1)
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.

PIC12F752/HV752
5.5.2 WEAK PULL-UPS pull-ups are disabled on a Power-on Reset by the
RAPU bit of the OPTION_REG register). A weak
Each of the PORTA pins, except RA3, has an
pull-up is automatically enabled for RA3 when
individually configurable internal weak pull-up. Control
configured as MCLR and disabled when RA3 is an I/O.
bits WPUx enable or disable each pull-up. Refer to
There is no software control of the MCLR pull-up.
Register 5-9. Each weak pull-up is automatically turned
off when the port pin is configured as an output. The
REGISTER 5-6: WPUA: WEAK PULL-UP PORTA REGISTER (1,2)

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — WPU5 WPU4 WPU3(3) WPU2 WPU1 WPU0
bit 7 bit 0
Legend:

bit 5-0 WPU<5:0>: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISA = 0).
3: The RA3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled
as an input and reads as ‘0’.
5.5.3 SLEW RATE CONTROL

Two of the PORTA pins (RA0 and RA2) are equipped
with high current driver circuitry. The SLRCONA register
provides reduced slew rate control to mitigate possible
EMI radiation from these pins.
REGISTER 5-7: SLRCONA: SLEW RATE CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 R/W-0
— — — — — SLRA2 — SLRA0
bit 7 bit 0
Legend:

bit 2 SLRA2: Slew Rate Control bit
1 = Pin voltage slews at limited rate
0 = Pin voltage slews at maximum rate
bit 0 SLRA0: Slew Rate Control bit
1 = Pin voltage slews at limited rate
0 = Pin voltage slews at maximum rate

PIC12F752/HV752
5.5.4 INTERRUPT-ON-CHANGE 5.5.4.5 Operation in Sleep
All pins on all ports can be configured to operate as The interrupt-on-change interrupt will wake the device
Interrupt-on-Change (IOC) pins. An interrupt can be from Sleep mode, if the IOCIE bit is set.
generated by detecting a signal that has either a rising If an edge is detected while in Sleep mode, the affected
edge or a falling edge. Any individual pin or combination IOCAF register will be updated prior to the first
of pins can be configured to generate an interrupt. The instruction executed out of Sleep.
interrupt-on-change module has the following features:
• Interrupt-on-Change Enable (Master Switch)
• Individual Pin Configuration
• Rising and Falling Edge Detection
• Individual Pin Interrupt Flags
Figure 14-1 is a block diagram of the IOC module.
5.5.4.1 Enabling the Module

To allow individual pins to generate an interrupt, the
IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
5.5.4.2 Individual Pin Configuration

For each pin, a rising edge detector and a falling edge
detector are present. To enable a pin to detect a rising
edge, the associated bit of the IOCAP register is set. To
enable a pin to detect a falling edge, the associated bit
of the IOCAN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting the associated bits in
both of the IOCAP and IOCAN registers.
5.5.4.3 Interrupt Flags

The bits located in the IOCAF registers are status flags
that correspond to the interrupt-on-change pins of each
port. If an expected edge is detected on an appropriately
enabled pin, then the status flag for that pin will be set,
and an interrupt will be generated if the IOCIE bit is set.
The IOCIF bit of the INTCON register reflects the status
of all IOCAF bits.
5.5.4.4 Clearing Interrupt Flags

The individual status flags (IOCAF register bits) can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 5-2: CLEARING INTERRUPT

FLAGS
(PORTA EXAMPLE)
MOVLW 0xff
XORWF IOCAF, W
ANDWF IOCAF, F

PIC12F752/HV752
FIGURE 5-2: INTERRUPT-ON-CHANGE BLOCK DIAGRAM
IOCBNx D Q4Q1
Q
CK Edge
Detect
R
RBx
Data Bus = S To Data Bus

IOCBPx D Q 0 or 1 D Q IOCBFx
CK Write IOCBFx CK
IOCIE
R
Q2
From all other
IOCBFx individual IOC Interrupt
Pin Detectors to CPU Core
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4 Q4
Q4Q1 Q4Q1 Q4Q1 Q4Q1

PIC12F752/HV752
REGISTER 5-8: IOCAP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
bit 7 bit 0
Legend:

bit 5-0 IOCAP<5:0>: Interrupt-on-Change Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 5-9: IOCAN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
bit 7 bit 0
Legend:

bit 5-0 IOCAN<5:0>: Interrupt-on-Change Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 5-10: IOCAF: INTERRUPT-ON-CHANGE FLAG REGISTER

U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
bit 7 bit 0
Legend:
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware

bit 5-0 IOCAF<5:0>: Interrupt-on-Change Flag bits
1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RBx, or when IOCANx = 1 and a falling edge was
detected on RAx.
0 = No change was detected, or the user cleared the detected change.

PIC12F752/HV752
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
ADCON0 ADFM VCFG CHS<3:0> GO/DONE ADON 94

ADCON1 — ADCS<2:0> — — — — 94
ANSELA — — ANSA5 ANSA4 — ANSA2 ANSA1 ANSA0 41
APFCON — — — T1GSEL — COG1FSEL COG1O1SEL COG1O0SEL 38
CM1CON0 C1ON C1OUT C1OE C1POL C1ZLF C1SP C1HYS C1SYNC 113
CM1CON1 C1INTP C1INTN C1PCH<1:0> — — — C1NCH0 114
CM2CON1 C2NTP C2INTN C2PCH<1:0> — — — C2NCH0 114
DACCON0 DACEN DACRNG DACOE — — DACPSS0 — — 105
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 45
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 45
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 45
LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 40
OPTION_REG RAPU INTEDG T0CS T0SE PSA PS<2:0> 14
PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 40
SLRCONA — — — — — SLRA2 — SLRA0 42
TRISA — — TRISA5 TRISA4 TRISA3(1) TRISA2 TRISA1 TRISA0 40
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

PIC12F752/HV752
6.0 TIMER0 MODULE 6.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the When used as a timer, the Timer0 module can be used
following features: as either an 8-bit timer or an 8-bit counter.
• 8-Bit Timer/Counter Register (TMR0)
6.1.1 8-BIT TIMER MODE
• 8-Bit Prescaler (shared with Watchdog Timer)
When used as a timer, the Timer0 module will
• Programmable Internal or External Clock Source
increment every instruction cycle (without prescaler).
• Programmable External Clock Edge Selection Timer mode is selected by clearing the T0CS bit of the
• Interrupt-on-Overflow OPTION register to ‘0’.
Figure 6-1 is a block diagram of the Timer0 module. When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction-cycle delay when
TMR0 is written.
6.1.2 8-BIT COUNTER MODE

When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION_REG register. Counter mode is
selected by setting the T0CS bit of the OPTION register
to ‘1’.
FIGURE 6-1: TIMER0 WITH SHARED PRESCALE BLOCK DIAGRAM
FOSC/4
Data Bus
0
8
1
Sync
1
2 TCY TMR0
Shared Prescale
T0CKI 0
pin 0
T0SE T0CS PSA Set Flag bit T0IF
8-bit
on Overflow
Prescaler
1
PSA
8
PS<2:0> 1
Watchdog
WDT
Timer
Time-out
LFINTOSC
2 0
(Figure 4-1)
PSA
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG register.
2: WDTE bit is in the Configuration Word register.

PIC12F752/HV752
6.1.3 SOFTWARE PROGRAMMABLE When changing the prescaler assignment from the
PRESCALER WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 6-2).
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler EXAMPLE 6-2: CHANGING PRESCALER
assignment is controlled by the PSA bit of the OPTION (WDT  TIMER0)
register. To assign the prescaler to Timer0, the PSA bit CLRWDT ;Clear WDT and
must be cleared to a ‘0’. ;prescaler
BANKSEL OPTION_REG ;
There are eight prescaler options for the Timer0
MOVLW b’11110000’ ;Mask TMR0 select and
module ranging from 1:2 to 1:256. The prescale values
ANDWF OPTION_REG,W ;prescaler bits
are selectable via the PS<2:0> bits of the OPTION IORLW b’00000011’ ;Set prescale to 1:16
register. In order to have a 1:1 prescaler value for the MOVWF OPTION_REG ;
Timer0 module, the prescaler must be assigned to the
WDT module.
6.1.4 TIMER0 INTERRUPT
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to Timer0 will generate an interrupt when the TMR0
the TMR0 register will clear the prescaler. register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
When the prescaler is assigned to WDT (PSA = 1) a TMR0 register overflows, regardless of whether or not
CLRWDT instruction will clear the prescaler along with the Timer0 interrupt is enabled. The T0IF bit must be
the WDT. cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
6.1.3.1 Switching Prescaler Between
Timer0 and WDT Modules Note: The Timer0 interrupt cannot wake the
processor from Sleep, since the timer is
As a result of having the prescaler assigned to either
frozen during Sleep.
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
6.1.5 USING TIMER0 WITH AN
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence EXTERNAL CLOCK
shown in Example 6-1, must be executed. When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is
EXAMPLE 6-1: CHANGING PRESCALER accomplished by sampling the prescaler output on the
(TIMER0  WDT) Q2 and Q4 cycles of the internal phase clocks.
Therefore, the high and low periods of the external
BANKSEL TMR0 ;
clock source must meet the timing requirements as
CLRWDT ;Clear WDT
shown in Section 20.0 “Electrical Specifications”.
CLRF TMR0 ;Clear TMR0 and
;prescaler
BANKSEL OPTION_REG ;
BSF OPTION_REG,PSA ;Select WDT
CLRWDT ;
;
MOVLW b’11111000’ ;Mask prescaler
ANDWF OPTION_REG,W ;bits
IORLW b’00000101’ ;Set WDT prescaler
MOVWF OPTION_REG ;to 1:32

PIC12F752/HV752
6.2 Option and Timer0 Control Register
REGISTER 6-1: OPTION_REG: OPTION REGISTER
RAPU INTEDG T0CS T0SE PSA PS<2:0>
bit 7 bit 0
Legend:
bit 7 RAPU: PORTA Pull-up Enable bit

1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values in WPU register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register on
Page
TMR0 Holding Register for the 8-bit Timer0 Register 47*
Legend: — Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0
module.

PIC12F752/HV752
7.0 TIMER1 MODULE WITH GATE • Wake-up on Overflow (External Clock,
Asynchronous mode only)
CONTROL
• Time Base for the Capture/Compare Function
The Timer1 module is a 16-bit timer/counter with the • Special Event Trigger (with CCP)
following features:
• Selectable Gate Source Polarity
• 16-Bit Timer/Counter Register Pair • Gate Toggle mode
(TMR1H:TMR1L)
• Gate Single-Pulse mode
• Selectable Internal or External Clock Sources
• Gate Value Status
• 2-Bit Prescaler
• Gate Event Interrupt
• Synchronous or Asynchronous Operation
Figure 7-1 is a block diagram of the Timer1 module.
• Multiple Timer1 Gate (Count Enable) Sources
• Interrupt-on-Overflow
FIGURE 7-1: TIMER1 BLOCK DIAGRAM

T1GSS<1:0>
T1G 00 T1GSPM
From Timer0 01 T1G_IN 0

Overflow 0 T1GVAL Data Bus
D Q
SYNCC1OUT 10 Single Pulse RD
1 T1GCON
Acq. Control Q1 EN
D Q 1
SYNCC2OUT 11 Interrupt
CK Q T1GGO/DONE TMR1GIF
R det
T1GPOL
TMR1ON TMR1GE
T1GTM
TMR1ON
TMR1CS1
TMR1(2) T1SYNC
EN Synchronized
Set flag bit 0
TMR1IF on TMR1H TMR1L T1CLK clock input
Q D
Overflow R
1
CCP Special Event Trigger TMR1CS<1:0>
Temperature Sense
11
Oscillator Prescaler Synchronize(3)
(1)
1, 2, 4, 8 det
T1CKI 10
2
FOSC T1CKPS<1:0>
Internal 01
Clock FOSC/2
Internal Sleep input
FOSC/4 Clock
Internal 00
Clock
Note 1: ST buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.

PIC12F752/HV752
7.1 Timer1 Operation 7.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter The TMR1CS<1:0> bits of the T1CON register are used
which is accessed through the TMR1H:TMR1L register to select the clock source for Timer1. Table 7-2 displays
pair. Writes to TMR1H or TMR1L directly update the the clock source selections.
counter.
When used with an internal clock source, the module is TABLE 7-2: CLOCK SOURCE
a timer and increments on every instruction cycle. SELECTIONS
When used with an external clock source, the module
can be used as either a timer or counter and TMR1CS<1:0> Clock Source
increments on every selected edge of the external 11 Temperature Sense Oscillator
source.
10 External Clocking on T1CKI Pin
Timer1 is enabled by configuring the TMR1ON and
01 System Clock (FOSC)
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 7-1 displays the Timer1 enable 00 Instruction Clock (FOSC/4)
selections.
7.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TABLE 7-1: TIMER1 ENABLE
TMR1H:TMR1L register pair will increment on multiples
SELECTIONS of FOSC or FOSC/4 as determined by the Timer1
Timer1 prescaler.
TMR1ON TMR1GE
Operation
7.2.2 EXTERNAL CLOCK SOURCE
0 0 Off
When the external clock source is selected, the Timer1
0 1 Off
module may work as a timer or a counter. When enabled
1 0 Always On to count, Timer1 is incremented on the rising edge of the
1 1 Count Enabled external clock input T1CKI.
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge (see Figure 7-2)
after any one or more of the following
conditions:
• Timer1 enabled after POR Reset
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high; then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
7.2.3 TEMPERATURE SENSE

OSCILLATOR
When the Temperature Sense Oscillator source is
selected, the TMR1H:TMR1L register pair will increment
on multiples of the Temperature Sense Oscillator as
determined by the Timer1 prescaler. The Temperature
Sense Oscillator operates at 16 kHz typical.

PIC12F752/HV752
7.3 Timer1 Prescaler 7.5 Timer1 Gate
Timer1 has four prescaler options allowing 1, 2, 4 or 8 Timer1 can be configured to count freely or the count
divisions of the clock input. The T1CKPS bits of the can be enabled and disabled using Timer1 gate
T1CON register control the prescale counter. The circuitry. This is also referred to as Timer1 gate count
prescale counter is not directly readable or writable; enable.
however, the prescaler counter is cleared upon a write to Timer1 gate can also be driven by multiple selectable
TMR1H or TMR1L. sources.
7.4 Timer1 Operation in 7.5.1 TIMER1 GATE COUNT ENABLE

Asynchronous Counter Mode The Timer1 gate is enabled by setting the TMR1GE bit
If control bit T1SYNC of the T1CON register is set, the of the T1GCON register. The polarity of the Timer1 gate
external clock input is not synchronized. The timer is configured using the T1GPOL bit of the T1GCON
increments asynchronously to the internal phase register.
clocks. If external clock source is selected, then the When Timer1 Gate (T1G) input is active, Timer1 will
timer will continue to run during Sleep and can increment on the rising edge of the Timer1 clock
generate an interrupt on overflow, which will wake-up source. When Timer1 gate input is inactive, no
the processor. However, special precautions in incrementing will occur and Timer1 will hold the current
software are needed to read/write the timer (see count. See Figure 7-3 for timing details.
Section 7.4.1 “Reading and Writing Timer1 in TABLE 7-3: TIMER1 GATE ENABLE
Asynchronous Counter Mode”). SELECTIONS
Note: When switching from synchronous to T1CLK T1GPOL T1G Timer1 Operation
asynchronous operation, it is possible to
skip an increment. When switching from  0 0 Counts
asynchronous to synchronous operation,  0 1 Holds Count
it is possible to produce an additional  1 0 Holds Count
increment.
 1 1 Counts
7.4.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read, which is taken care of in hardware. However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.

PIC12F752/HV752
7.5.2 TIMER1 GATE SOURCE 7.5.4 TIMER1 GATE SINGLE-PULSE
SELECTION MODE
The Timer1 gate source can be selected from one of When Timer1 Gate Single-Pulse mode is enabled, it is
four different sources. Source selection is controlled by possible to capture a single pulse gate event. Timer1
the T1GSS bits of the T1GCON register. The polarity Gate Single-Pulse mode is first enabled by setting the
for each available source is also selectable. Polarity T1GSPM bit in the T1GCON register. Next, the
selection is controlled by the T1GPOL bit of the T1GGO/DONE bit in the T1GCON register must be set.
T1GCON register. The Timer1 will be fully enabled on the next
TABLE 7-4: TIMER1 GATE SOURCES incrementing edge. On the next trailing edge of the
pulse, the T1GGO/DONE bit will automatically be
T1GSS Timer1 Gate Source cleared. No other gate events will be allowed to
11 SYNCC2OUT increment Timer1 until the T1GGO/DONE bit is once
again set in software.
10 SYNCC1OUT
Clearing the T1GSPM bit of the T1GCON register will
01 Overflow of Timer0
also clear the T1GGO/DONE bit. See Figure 7-5 for
(TMR0 increments from FFh to 00h)
timing details.
00 Timer1 Gate Pin
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
7.5.2.1 T1G Pin Gate Operation
together. This allows the cycle times on the Timer1 gate
The T1G pin is one source for Timer1 gate control. It source to be measured. See Figure 7-6 for timing
can be used to supply an external source to the Timer1 details.
gate circuitry.
7.5.5 TIMER1 GATE VALUE STATUS
7.5.2.2 Timer0 Overflow Gate Operation
When Timer1 gate value status is utilized, it is possible
When Timer0 increments from FFh to 00h, a to read the most current level of the gate control value.
low-to-high pulse will automatically be generated and The value is stored in the T1GVAL bit in the T1GCON
internally supplied to the Timer1 gate circuitry. register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
7.5.2.3 C1OUT/C2OUT Gate Operation
The outputs from the Comparator C1 and C2 modules 7.5.6 TIMER1 GATE EVENT INTERRUPT
can be used as gate sources for the Timer1 module. When Timer1 gate event interrupt is enabled, it is
possible to generate an interrupt upon the completion
7.5.3 TIMER1 GATE TOGGLE MODE of a gate event. When the falling edge of T1GVAL
When Timer1 Gate Toggle mode is enabled, it is occurs, the TMR1GIF flag bit in the PIR1 register will be
possible to measure the full-cycle length of a Timer1 set. If the TMR1GIE bit in the PIE1 register is set, then
gate signal, as opposed to the duration of a single level an interrupt will be recognized.
pulse. The TMR1GIF flag bit operates even when the Timer1
The Timer1 gate source is routed through a flip-flop that gate is not enabled (TMR1GE bit is cleared).
changes state on every incrementing edge of the
signal. See Figure 7-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note: Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.

PIC12F752/HV752
7.6 Timer1 Interrupt 7.8 CCP Capture/Compare Time Base
The Timer1 register pair (TMR1H:TMR1L) increments The CCP module uses the TMR1H:TMR1L register
to FFFFh and rolls over to 0000h. When Timer1 rolls pair as the time base when operating in Capture or
over, the Timer1 interrupt flag bit of the PIR1 register is Compare mode.
set. To enable the Interrupt-on-Rollover, you must set In Capture mode, the value in the TMR1H:TMR1L
these bits: register pair is copied into the CCPR1H:CCPR1L
• TMR1ON bit of the T1CON register register pair on a configured event.
• TMR1IE bit of the PIE1 register In Compare mode, an event is triggered when the value
• PEIE bit of the INTCON register CCPR1H:CCPR1L register pair matches the value in
• GIE bit of the INTCON register the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine. For more information, see Section 10.0 “Capture/
Compare/PWM Modules”.
Note: The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
7.9 CCP Special Event Trigger
enabling interrupts.
When the CCP is configured to trigger a special event,
7.7 Timer1 Operation During Sleep the trigger will clear the TMR1H:TMR1L register pair.
This special event does not cause a Timer1 interrupt.
Timer1 can only operate during Sleep when setup in The CCP module may still be configured to generate a
Asynchronous Counter mode. In this mode, the clock CCP interrupt.
source can be used to increment the counter. To set up
In this mode of operation, the CCPR1H:CCPR1L
the timer to wake the device:
register pair becomes the period register for Timer1.
• TMR1ON bit of the T1CON register must be set
Timer1 should be synchronized to the FOSC/4 to utilize
• TMR1IE bit of the PIE1 register must be set the Special Event Trigger. Asynchronous operation of
• PEIE bit of the INTCON register must be set Timer1 can cause a Special Event Trigger to be
• T1SYNC bit of the T1CON register must be set missed.
• TMR1CS bits of the T1CON register must be In the event that a write to TMR1H or TMR1L coincides
configured with a Special Event Trigger from the CCP, the write will
• TMR1GE bit of the T1GCON register must be take precedence.
configured For more information, see Section 12.2.5 “Special
The device will wake-up on an overflow and execute Event Trigger”.
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
FIGURE 7-2: TIMER1 INCREMENTING EDGE
T1CKI
T1CKI
TMR1 enabled
Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

PIC12F752/HV752
FIGURE 7-3: TIMER1 GATE COUNT ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TIMER1 N N+1 N+2 N+3 N+4
FIGURE 7-4: TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TIMER1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8

PIC12F752/HV752
FIGURE 7-5: TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1 N N+1 N+2
Cleared by
TMR1GIF Cleared by software Set by hardware on software
falling edge of T1GVAL

PIC12F752/HV752
FIGURE 7-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
Cleared by hardware on
T1GGO/ Set by software falling edge of T1GVAL
DONE Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1 N N+1 N+2 N+3 N+4
Set by hardware on Cleared by

TMR1GIF Cleared by software falling edge of T1GVAL software

PIC12F752/HV752
7.10 Timer1 Control Registers
REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
TMR1CS<1:0> T1CKPS<1:0> Reserved T1SYNC — TMR1ON
bit 7 bit 0
Legend:
bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits

11 = Temperature Sense Oscillator
10 = External clock from T1CKI pin (on the rising edge)
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
bit 3 Reserved: Do not use.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS<1:0> = 1X
1 = Do not synchronize external clock input
0 = Synchronize external clock input with system clock (FOSC)
TMR1CS<1:0> = 0X
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Clears Timer1 gate flip-flop

PIC12F752/HV752
REGISTER 7-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0>
DONE
bit 7 bit 0
Legend:
bit 7 TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6 T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 T1GTM: Timer1 Gate Toggle mode bit
1 = Timer1 Gate Toggle mode is enabled.
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 T1GSPM: Timer1 Gate Single Pulse mode bit
1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
This bit is automatically cleared when T1GSPM is cleared.
bit 2 T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits
11 = SYNCC2OUT
10 = SYNCC1OUT
01 = Timer0 overflow output
00 = Timer1 gate pin

PIC12F752/HV752
Register
on Page
APFCON — — — T1GSEL — COG1SEL COG1O1SEL COG1O0SEL 38
CCP1CON — — DC1B<1:0> CCP1M<3:0> 73
PIE1 TMR1GIE ADIE — — — HLTMR1IE TMR2IE TMR1IE 16
PIR1 TMR1GIF ADIF — — — HLTMR1IF TMR2IF TMR1IF 18
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 50*
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 50*
TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 40
T1CON TMR1CS<1:0> T1CKPS<1:0> Reserved T1SYNC — TMR1ON 58
T1GGO/
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GVAL T1GSS<1:0> 59
DONE
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

PIC12F752/HV752
8.0 TIMER2 MODULE The match output of the Timer2/PR2 comparator is
then fed into the Timer2 postscaler. The postscaler has
The Timer2 module is an 8-bit timer with the following postscale options of 1:1 to 1:16 inclusive. The output of
features: the Timer2 postscaler is used to set the TMR2IF
• 8-Bit Timer Register (TMR2) interrupt flag bit in the PIR1 register.
• 8-Bit Period Register (PR2) The TMR2 and PR2 registers are both fully readable
• Interrupt on TMR2 Match with PR2 and writable. On any Reset, the TMR2 register is set to
• Software Programmable Prescaler (1:1, 1:4, 1:16) 00h and the PR2 register is set to FFh.
• Software Programmable Postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Timer2 is turned off by clearing
See Figure 8-1 for a block diagram of Timer2.
the TMR2ON bit to a ‘0’.
8.1 Timer2 Operation The Timer2 prescaler is controlled by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
The clock input to the Timer2 module is the system controlled by the TOUTPS bits in the T2CON register.
instruction clock (FOSC/4). The clock is fed into the The prescaler and postscaler counters are cleared
Timer2 prescaler, which has prescale options of 1:1, when:
1:4 or 1:16. The output of the prescaler is then used to • A write to TMR2 occurs
increment the TMR2 register.
• A write to T2CON occurs
The values of TMR2 and PR2 are constantly compared • Any device Reset occurs (Power-on Reset, MCLR
to determine when they match. TMR2 will increment Reset, Watchdog Timer Reset, or Brown-out
from 00h until it matches the value in PR2. When a Reset)
match occurs, two things happen:
Note: TMR2 is not cleared when T2CON is
• TMR2 is reset to 00h on the next increment cycle written.
• The Timer2 postscaler is incremented
FIGURE 8-1: TIMER2 BLOCK DIAGRAM
Prescaler Reset
FOSC/4 TMR2 TMR2 Output
1:1, 1:4, 1:16
2 Postscaler
Comparator Sets Flag bit TMR2IF
EQ 1:1 to 1:16
T2CKPS<1:0>
PR2 4
TOUTPS<3:0>

PIC12F752/HV752
8.2 Timer2 Control Registers
REGISTER 8-1: T2CON: TIMER 2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS<3:0> TMR2ON T2CKPS<1:0>
bit 7 bit 0
Legend:

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

Register on
Page
PR2 Timer2 Module Period Register 61*
TMR2 Holding Register for the 8-bit TMR2 Register 61*
T2CON — TOUTPS<3:0> TMR2ON T2CKPS<1:0> 62
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

PIC12F752/HV752
9.0 HARDWARE LIMIT TIMER (HLT) The HLT module incorporates the following features:
MODULE • 8-Bit Read-Write Timer Register (HLTMR1)
• 8-Bit Read-Write Period Register (HLTPR1)
The Hardware Limit Timer (HLT) module is a version of
the Timer2-type modules. In addition to all the • Software Programmable Prescaler
Timer2-type features, the HLT can be reset on rising - 1:1
and falling events from selected peripheral outputs. - 1:4
The HLT primary purpose is to act as a timed hardware - 1:16
limit to be used in conjunction with asynchronous • Software Programmable Postscaler:
analog feedback applications. The external reset - 1:1 to 1:16, inclusive
source synchronizes the HLTMR1 to an analog • Interrupt on HLTMR1 Match with HLTPR1
application.
• Eight Selectable Timer Reset Inputs (five
In normal operation, the external reset source from the reserved)
analog application should occur before the HLTMR1 • Reset on Rising and Falling Event
matches the HLTPR1. This resets HLTMR1 for the next
period and prevents the HLTimer1 Output from going Refer to Figure 9-1 for a block diagram of the HLT.
active.
When the external reset source fails to generate a
signal within the expected time, allowing the HLTMR1 to
match the HLTPR1, then the HLTimer1 Output
becomes active.
FIGURE 9-1: HLTMR1 BLOCK DIAGRAM
CCP1 out 000

C1OUT H1REREN
Detect
C2OUT
COG1FLT
COG1OUT0
COG1OUT1
‘0’ Detect
‘0’ 111 H1FEREN
3
H1ERS<2:0>
FOSC/4 Prescaler Reset

HLTMR1
H1ON 1:1, 1:4, 1:16 HLTimer1 Output
(to COG module)
EQ Postscaler
2 Comparator Sets Flag bit HLTMR1IF
1:1 to 1:16
H1CKPS<1:0>
HLTPR1 4
H1OUTPS<3:0>

PIC12F752/HV752
9.1 HLT Operation 9.2 HLT Interrupt
The clock input to the HLT module is the system The HLT can also generate an optional device interrupt.
instruction clock (FOSC/4). HLTMR1 increments on The HLTMR1 output signal (HLTMR1-to-HLTPR1
each rising clock edge. match) provides the input for the 4-bit counter/
A 4-bit counter/prescaler on the clock input provides the postscaler. The overflow output of the postscaler sets
following prescale options: the HLTMR1IF bit of the PIR1 register. The interrupt is
enabled by setting the HLTMR1 Match Interrupt Enable
• Direct Input bit, HLTMR1IE of the PIE1 register.
• Divide-by-4
A range of 16 postscale options (from 1:1 through 1:16
• Divide-by-16 inclusive) can be selected with the postscaler control
The prescale options are selected by the prescaler bits, H1OUTPS<3:0>, of the HLT1CON0 register.
control bits, H1CKPS<1:0> of the HLT1CON0 register.
The value of HLTMR1 is compared to that of the Period 9.3 Peripheral Resets
register, HLTPR1, on each clock cycle. When the two Resets driven from the selected peripheral output
values match,then the comparator generates a match prevents the HLTMR1 from matching the HLTPR1
signal as the HLTimer1 output. This signal also resets register and generating an output. In this manner, the
the value of HLTMR1 to 00h on the next clock rising HLT can be used as a hardware time limit to other
edge and drives the output counter/postscaler (see peripherals.
Section 9.2 “HLT Interrupt”).
In this device, the primary purpose of the HLT is to limit
The time from HLT reset to the HLT output pulse is the COG PWM duty cycle. Normally, the COG
calculated as shown in Equation 9-1 below. operation uses analog feedback to determine the PWM
duty cycle. The same feedback signal is used as an
EQUATION 9-1: HLT OUTPUT HLT Reset input. The HLTPR1 register is set to occur
at the maximum allowed duty cycle. If the analog
feedback to the COG exceeds the maximum time, then
HLT Time =  HLTPR1 + 2   4  Fosc an HLTMR1-to-HLTPR1 match will occur and generate
the output needed to limit the COG drive output.
Unexpected operation may occur for HLT periods less The HLTMR1 can be reset by one of several selectable
than half the period of the expected external HLT Reset peripheral sources. Reset inputs include:
input. • CCP1 Output
The HLTMR1 and HLTPR1 registers are both directly • Comparator 1 Output
readable and writable. The HLTMR1 register is cleared • Comparator 2 Output
on any device Reset, whereas the HLTPR1 register
The Reset input is selected with the H1ERS<2:0> bits
initializes to FFh. Both the prescaler and postscaler
of the HLT1CON1 register.
counters are cleared on any of the following events:
HLTMR1 Resets are synchronous with the HLT clock,
• A Write to the HLTMR1 Register
i.e. HLTMR1 is cleared on the rising edge of the HLT
• A Write to the HLT1CON0 Register clock after the enabled Reset event occurs.
• Power-on Reset (POR)
The Reset can be enabled to occur on the rising and
• Brown-out Reset (BOR) falling input event. Rising and falling event enables are
• MCLR Reset selected with the respective H1REREN and H1FEREN
• Watchdog Timer (WDT) Reset bits of the HLT1CON1 register. External Resets do not
• Stack Overflow Reset cause an HLTMR1 output event.
• Stack Underflow Reset
• RESET Instruction. 9.4 HLTimer1 Output
Note: HLTMR1 is not cleared when HLT1CON0 is The unscaled output of HLTMR1 is available only to the
written. COG module, where it is used as a selectable limit to
the maximum COG period.
9.5 HLT Operation During Sleep

The HLT cannot be operated while the processor is in
Sleep mode. The contents of the HLTMR1 register will
remain unchanged while the processor is in Sleep
mode.

PIC12F752/HV752
9.6 HLT Control Registers
REGISTER 9-1: HLT1CON0: HLT1 CONTROL REGISTER 0

U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— H1OUTPS<3:0> H1ON H1CKPS<1:0>
bit 7 bit 0
Legend:

bit 6-3 H1OUTPS<3:0>: Hardware Limit Timer 1 Output Postscaler Select bits
bit 2 H1ON: Hardware Limit Timer 1 On bit
1 = Timer is on
0 = Timer is off
bit 1-0 H1CKPS<1:0>: Hardware Limit Timer 1 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

PIC12F752/HV752
REGISTER 9-2: HLT1CON1: HLT1 CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — H1ERS<2:0> H1FEREN H1REREN
bit 7 bit 0
Legend:

bit 4-2 H1ERS<2:0>: Hardware Limit Timer 1 Peripheral Reset Select bits
000 = CCP1 Out
001 = C1OUT
010 = C2OUT
011 = COG1FLT
100 = COG1OUT0
101 = COG1OUT1
110 = Reserved - ‘0’ input
111 = Reserved - ‘0’ input
bit 1 H1FEREN: Hardware Limit Timer 1 Falling Edge Reset Enable bit
1 = HLTMR1 will reset on the first clock after a falling edge of selected Reset source
0 = Falling edges of selected source have no effect
bit 0 H1REREN: Hardware Limit Timer 1 Rising Edge Reset Enable bit
1 = HLTMR1 will reset on the first clock after a rising edge of selected Reset source
0 = Rising edges of selected source have no effect
TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH HLT

Register
on Page
CCP1CON — — DC1B<1:0> CCP1M<3:0> 73

HLTMR1 Holding Register for the 8-bit Hardware Limit Timer1 Register 63*
HLTPR1 HLTMR1 Module Period Register 63*
HLT1CON0 — H1OUTPS<3:0> H1ON H1CKPS<1:0> 65
HLT1CON1 — — — H1ERS<2:0> H1FEREN H1REREN 66
Legend: — = unimplemented location, read as ‘0’. Shaded cells do not affect the HLT module operation.

PIC12F752/HV752
10.0 CAPTURE/COMPARE/PWM 10.1.2 TIMER1 MODE RESOURCE
MODULES Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP1 module to use the capture
The Capture/Compare/PWM modules is a peripheral feature. In Asynchronous Counter mode, the capture
which allows the user to time and control different operation may not work.
events, and to generate Pulse-Width Modulation
(PWM) signals. In Capture mode, the peripheral allows See Section 7.0 “Timer1 Module with Gate Control”
the timing of the duration of an event. The Compare for more information on configuring Timer1.
mode allows the user to trigger an external event when
a predetermined amount of time has expired. The 10.1.3 SOFTWARE INTERRUPT MODE
PWM mode can generate Pulse-Width Modulated When the Capture mode is changed, a false capture
signals of varying frequency and duty cycle. interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit of the PIE2 register clear to
10.1 Capture Mode avoid false interrupts. Additionally, the user should
clear the CCP1IF interrupt flag bit of the PIR2 register
Capture mode makes use of the 16-bit Timer1 following any change in Operating mode.
resource. When an event occurs on the CCP1 pin, the
16-bit CCPR1H:CCPR1L register pair captures and Note: Clocking Timer1 from the system clock
stores the 16-bit value of the TMR1H:TMR1L register (FOSC) should not be used in Capture
pair, respectively. An event is defined as one of the mode. In order for Capture mode to
following and is configured by the CCP1M<3:0> bits of recognize the trigger event on the CCP1
the CCP1CON register: pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
• Every Falling Edge external clock source.
• Every Rising Edge
• Every 4th Rising Edge 10.1.4 CCP1 PRESCALER
• Every 16th Rising Edge There are four prescaler settings specified by the
When a capture is made, the Interrupt Request Flag bit CCP1M<3:0> bits of the CCP1CON register.
CCP1IF of the PIR2 register is set. The interrupt flag Whenever the CCP1 module is turned off or the CCP1
must be cleared in software. If another capture occurs module is not in Capture mode, the prescaler counter
before the value in the CCPR1H, CCPR1L register pair is cleared. Any Reset will clear the prescaler counter.
is read, the old captured value is overwritten by the new Switching from one capture prescaler to another does not
captured value. clear the prescaler and may generate a false interrupt. To
Figure 10-1 shows a simplified diagram of the Capture avoid this unexpected operation, turn the module off by
operation. clearing the CCP1CON register before changing the
prescaler. Example 10-1 demonstrates the code to
10.1.1 CCP1 PIN CONFIGURATION perform this function.
In Capture mode, the CCP1 pin should be configured
as an input by setting the associated TRIS control bit. EXAMPLE 10-1: CHANGING BETWEEN
CAPTURE PRESCALERS
Note: If the CCP1 pin is configured as an output,
a write to the port can cause a capture BANKSEL CCP1CON ;Set Bank bits to point
;to CCP1CON
condition.
CLRF CCP1CON ;Turn CCP1 module off
MOVLW NEW_CAPT_PS ;Load the W reg with
FIGURE 10-1: CAPTURE MODE ;the new prescaler
OPERATION BLOCK ;move value and CCP1 ON
MOVWF CCP1CON ;Load CCP1CON with this
DIAGRAM
;value
Set Flag bit CCP1IF
(PIR2 register)
Prescaler
 1, 4, 16
CCP1 CCPR1H CCPR1L
pin
and Capture
Edge Detect Enable
TMR1H TMR1L
CCP1M<3:0>
System Clock (FOSC)

PIC12F752/HV752
10.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. If the Timer1 clock input source is a
clock that is not disabled during Sleep, Timer1 will
continue to operate and Capture mode will operate
during Sleep to wake the device. The T1CKI is an
example of a clock source that will operate during
Sleep.
When the input source to Timer1 is disabled during
Sleep, such as the HFINTOSC, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Register
on Page
CCP1CON — — DC1B<1:0> CCP1M<3:0> 73
CCPR1L Capture/Compare/PWM Register x Low Byte (LSB) 67*
CCPR1H Capture/Compare/PWM Register x High Byte (MSB) 67*
PIE2 — — C2IE C1IE — COG1IE — CCP1IE 17
PIR2 — — C2IF C1IF — COG1IF — CCP1IF 19
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ T1GVAL T1GSS<1:0>
59
DONE
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Capture mode.

PIC12F752/HV752
10.2 Compare Mode 10.2.2 TIMER1 MODE RESOURCE
Compare mode makes use of the 16-bit Timer1 In Compare mode, Timer1 must be running in either
resource. The 16-bit value of the CCPR1H:CCPR1L Timer mode or Synchronized Counter mode. The
register pair is constantly compared against the 16-bit compare operation may not work in Asynchronous
value of the TMR1H:TMR1L register pair. When a Counter mode.
match occurs, one of the following events can occur: See Section 7.0 “Timer1 Module with Gate Control”
• Toggle the CCP1 Output for more information on configuring Timer1.
• Set the CCP1 Output Note: Clocking Timer1 from the system clock
• Clear the CCP1 Output (FOSC) should not be used in Compare
• Generate a Special Event Trigger mode. In order for Compare mode to
• Generate a Software Interrupt recognize the trigger event on the CCP1
The action on the pin is based on the value of the pin, Timer1 must be clocked from the
CCP1M<3:0> control bits of the CCP1CON register. At instruction clock (FOSC/4) or from an
the same time, the interrupt flag CCP1IF bit is set. external clock source.
All Compare modes can generate an interrupt.
10.2.3 SOFTWARE INTERRUPT MODE
Figure 10-2 shows a simplified diagram of the
Compare operation. When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 module does not
assert control of the CCP1 pin (see the CCP1CON
FIGURE 10-2: COMPARE MODE
register).
OPERATION BLOCK
DIAGRAM 10.2.4 SPECIAL EVENT TRIGGER
CCP1M<3:0> When Special Event Trigger mode is chosen
Mode Select
(CCP1M<3:0> = 1011), the CCP1 module does the
following:
Set CCP1IF Interrupt Flag
(PIR2) • It resets Timer1
CCP1 4
Pin CCPR1H CCPR1L • It starts an ADC conversion if ADC is enabled
Q S The CCP1 module does not assert control of the CCP1
Output Comparator
Logic Match pin in this mode.
R
The Special Event Trigger output of the CCP1 occurs
TMR1H TMR1L
TRIS immediately upon a match between the TMR1H,
Output Enable TMR1L register pair and the CCPR1H, CCPR1L
Special Event Trigger register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. The
Special Event Trigger output starts an A/D conversion
10.2.1 CCP1 PIN CONFIGURATION (if the A/D module is enabled). This allows the
The user must configure the CCP1 pin as an output by CCPR1H, CCPR1L register pair to effectively provide a
clearing the associated TRIS bit. 16-bit programmable period register for Timer1.
TABLE 10-2: SPECIAL EVENT TRIGGER
Note: Clearing the CCP1CON register will force
the CCP1 compare output latch to the Device CCP1
default low level. This is not the PORT I/O PIC12F752 CCP1
data latch. PIC12HV752
Refer to Section 12.0 “Analog-to-Digital Converter
(ADC) Module” for more information.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
2: Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will
preclude the Reset from occurring.

PIC12F752/HV752
10.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Register
on Page
CCP1CON — — DC1B<1:0> CCP1M<3:0> 73
CCPR1L Capture/Compare/PWM Register 1 Low Byte (LSB) 67*
CCPR1H Capture/Compare/PWM Register 1 High Byte (MSB) 67*
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 59
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.

PIC12F752/HV752
10.3 PWM Overview FIGURE 10-3: CCP1 PWM OUTPUT
SIGNAL
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between Period
fully-on and fully-off states. The PWM signal resembles
a square wave where the high portion of the signal is Pulse Width
considered the on state and the low portion of the signal TMR2 = PR2
is considered the off state. The high portion, also known TMR2 = CCPR1H:CCP1CON<5:4>
as the pulse width, can vary in time and is defined in
TMR2 = 0
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The FIGURE 10-4: SIMPLIFIED PWM BLOCK
PWM period is defined as the duration of one complete DIAGRAM
cycle or the total amount of on and off time combined.
CCP1CON<5:4>
Duty Cycle Registers
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher CCPR1L
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
The term duty cycle describes the proportion of the on CCPR1H(2) (Slave)
CCP1
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty Comparator R Q
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied. (1) S
TMR2
Figure 10-3 shows a typical waveform of the PWM TRIS
signal.
Comparator
Clear Timer,
10.3.1 STANDARD PWM OPERATION toggle CCP1 pin and
latch duty cycle
The standard PWM mode generates a Pulse-Width PR2
modulation (PWM) signal on the CCP1 pin with up to
Note 1: The 8-bit timer TMR2 register is concatenated
ten bits of resolution. The period, duty cycle and
with the 2-bit internal system clock (FOSC), or
resolution are controlled by the following registers:
two bits of the prescaler, to create the 10-bit
• PR2 Registers time base.
• T2CON Registers 2: In PWM mode, CCPR1H is a read-only register.
• CCPR1L Registers
• CCP1CON Registers
Figure 10-4 shows a simplified block diagram of PWM
operation.
Note 1: The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCP1 pin.
2: Clearing the CCP1CON register will
relinquish control of the CCP1 pin.

PIC12F752/HV752
10.3.2 SETUP FOR PWM OPERATION 10.3.4 PWM DUTY CYCLE
The following steps should be taken when configuring The PWM duty cycle is specified by writing a 10-bit
the CCP1 module for standard PWM operation: value to multiple registers: CCPR1L register and
1. Disable the CCP1 pin output driver by setting DC1B<1:0> bits of the CCP1CON register. The
the associated TRIS bit CCPR1L contains the eight MSbs and the DC1B<1:0>
bits of the CCP1CON register contain the two LSbs.
2. Load the PR2 register with the PWM period
CCPR1L and DC1B<1:0> bits of the CCP1CON
value
register can be written to at any time. The duty cycle
3. Configure the CCP1 module for the PWM mode value is not latched into CCPR1H until after the period
by loading the CCP1CON register with the completes (i.e. a match between PR2 and TMR2
appropriate values registers occurs). While using the PWM, the CCPR1H
4. Load the CCPR1L register and the DC1B<1:0> register is read-only.
bits of the CCP1CON register, with the PWM
Equation 10-2 is used to calculate the PWM pulse
duty cycle value
width.
5. Configure and start Timer2:
Equation 10-3 is used to calculate the PWM duty cycle
• Clear the TMR2IF interrupt flag bit of the
ratio.
PIR1 register (see Note below)
• Configure the T2CKPS bits of the T2CON
EQUATION 10-2: PULSE WIDTH
register with the Timer prescale value
• Enable the Timer by setting the TMR2ON
Pulse Width =  CCPR1L:CCP1CON<5:4>  
bit of the T2CON register
6. Enable PWM output pin: T OSC  (TMR2 Prescale Value)
• Wait until the Timer overflows and the
TMR2IF bit of the PIR1 register is set. See
Note below EQUATION 10-3: DUTY CYCLE RATIO
• Enable the CCP1 pin output driver by clear-
ing the associated TRIS bit  CCPRxL:CCPxCON<5:4> 
Duty Cycle Ratio = -----------------------------------------------------------------------
4  PRx + 1 
Note: In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup The CCPR1H register and a 2-bit internal latch are
sequence. If it is not critical to start with a used to double buffer the PWM duty cycle. This double
complete PWM signal on the first output, buffering is essential for glitchless PWM operation.
then step 6 may be ignored.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or two bits
10.3.3 PWM PERIOD of the prescaler, to create the 10-bit time base. The
The PWM period is specified by the PR2 register of system clock is used if the Timer2 prescaler is set to 1:1.
Timer2. The PWM period can be calculated using the When the 10-bit time base matches the CCPR1H and
formula of Equation 10-1. 2-bit latch, then the CCP1 pin is cleared (see
Figure 10-4).
EQUATION 10-1: PWM PERIOD
PWM Period =   PR2  + 1   4  T OSC 
(TMR2 Prescale Value)
Note 1: TOSC = 1/FOSC
When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: If the PWM duty
cycle = 0%, the pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: The Timer postscaler (see Section 8.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.

PIC12F752/HV752
10.4 CCP Control Registers
REGISTER 10-1: CCP1CON: CCP1 CONTROL REGISTER

U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — DC1B<1:0> CCP1M<3:0>
bit 7 bit 0
Legend:
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset

bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0 CCP1M<3:0>: CCP1 Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0001 = Reserved
0010 = Compare mode: toggle output on match
0011 = Reserved
0100 = Capture mode: every falling edge

0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
1000 = Compare mode: initialize CCP1 pin low; set output on compare match (set CCP1IF)
1001 = Compare mode: initialize CCP1 pin high; clear output on compare match (set CCP1IF)
1010 = Compare mode: generate software interrupt only; CCP1 pin reverts to I/O state
1011 = Compare mode: Special Event Trigger (CCP1 resets Timer, sets CCP1IF bit, and starts A/D
conversion if A/D module is enabled)
11xx = PWM mode

PIC12F752/HV752
11.0 COMPLEMENTARY OUTPUT 11.1 Fundamental Operation
GENERATOR (COG) MODULE The COG generates a two output complementary
The primary purpose of the Complementary Output PWM waveform from rising and falling event sources.
Generator (COG) is to convert a single output PWM In the simplest configuration, the rising and falling
signal into a two output complementary PWM signal. event sources are the same signal, which is a PWM
The COG can also convert two separate input events signal with the desired period and duty cycle. The COG
into a single or complementary PWM output. converts this single PWM input into a dual
complementary PWM output. The frequency and duty
The COG PWM frequency and duty cycle are cycle of the dual PWM output match those of the single
determined by a rising event input and a falling event input PWM signal. The off-to-on transition of each
input. The rising event and falling event may be the output can be delayed from the on-to-off transition of
same source. Sources may be synchronous or the other output, thereby, creating a time immediately
asynchronous to the COG_clock. after the PWM transition where neither output is driven.
The rate at which the rising event occurs determines This is referred to as dead time and is covered in
the PWM frequency. The time from the rising event Section 11.5 “Dead-Band Control”.
input to the falling event input determines the duty A typical operating waveform, with dead band, generated
cycle. from a single CCP1 input is shown in Figure 11-2.
A selectable clock input is used to generate the phase The COG can also generate a PWM waveform from a
delay, blanking and dead-band times. periodic rising event and a separate falling event. In
A simplified block diagram of the COG is shown in this case, the falling event is usually derived from
Figure 11-1. analog feedback within the external PWM driver circuit.
In this configuration, high-power switching transients
The COG module has the following features:
may trigger a false falling event that needs to be
• Selectable clock source blanked out. The COG can be configured to blank
• Selectable rising event source falling (and rising) event inputs for a period of time
• Selectable falling event source immediately following the rising (and falling) event drive
• Selectable edge or level event sensitivity output. This is referred to as input blanking and is
covered in Section 11.6 “Blanking Control”.
• Independent output enables
• Independent output polarity selection It may be necessary to guard against the possibility of
circuit faults. In this case, the active drive must be
• Phase delay
terminated before the Fault condition causes damage.
• Dead-band control with independent rising and This is referred to as auto-shutdown and is covered in
falling event dead-band times Section 11.8 “Auto-Shutdown Control”.
• Blanking control with independent rising and
A feedback falling event arriving too late or not at all
falling event blanking times
can be terminated with auto-shutdown or by using one
• Auto-shutdown control with: of the event inputs that is logically or’d with the
- Selectable shutdown sources hardware limit timer (HLT). See Section 9.0
- Auto-restart enable “Hardware Limit Timer (HLT) Module” for more
- Auto-shutdown pin override control information about the HLT.
The COG can be configured to operate in phase
delayed conjunction with another PWM. The active
drive cycle is delayed from the rising event by a phase
delay timer. Phase delay is covered in more detail in
Section 11.7 “Phase Delay”.
A typical operating waveform, with phase delay and
dead band, generated from a single CCP1 input is
shown in Figure 11-3.

FIGURE 11-1: SIMPLIFIED COG BLOCK DIAGRAM
 2011-2015 Microchip Technology Inc.
HFINTOSC 10
COG_clock
Fosc/4 01
Fosc 00
GxCS<1:0>
GxDBR<3:0> GxOE0
HLTimer1 or COGxFLT 7 GxPH<3:0>
HLTimer1 or CCP1 6 GxOUT0SS COG1OUT0
Dead Band 1
HLTimer1 or C2OUT 5 Rising event source Phase
HLTimer1 or C1OUT 4 Reset Dominates Cnt/R =
Delay 1 0
COGxFLT 3
CCP1 2 Blanking S Q
C2OUT 1 =
Cnt/R 0 GxPOL0
C1OUT 0 R Q
GxBLKF<3:0> GxRSIM
GxRS0<2:0>
HLTimer1 or COGxFLT 7 GxDBF<3:0> GxOE1

HLTimer1 or CCP1 6 GxOUT1SS
HLTimer1 or C2OUT Dead Band COG1OUT1
5 1
HLTimer1 or C1OUT 4 Falling event source Cnt/R =
COGxFLT 3 1 0
CCP1 2 Blanking
C2OUT 1 = 0
C1OUT Cnt/R GxPOL1
0
GxFS0<2:0> GxBLKR<3:0> GxFSIM
S
D Q
COGxFLT
GxASDSFLT
C1OUT
PIC12F752/HV752
GxASDSC1 Auto-shutdown source GxASDE
S Q
C2OUT GxARSEN
GxASDSC2 R
GxEN
HLTimer1 output Set Dominates
GxASDSHLT Write GxASDE Low
Write GxASDE High

DS40001576D-page 75
PIC12F752/HV752
FIGURE 11-2: TYPICAL COG OPERATION WITH CCP1
COG_clock
Source
CCP1
COGxOUT0
Rising Source Dead Band

Falling Source Dead Band Falling Source Dead Band
COGxOUT1
FIGURE 11-3: COG OPERATION WITH CCP1 AND PHASE DELAY
COG_clock
Source
CCP1
COGxOUT0
Rising Source Dead Band

Falling Source Dead Band Phase Delay Falling Source Dead
Band
COGxOUT1
11.2 Clock Sources 11.3 Selectable Event Sources

The COG_clock is used as the reference clock to the The COG uses two independently selectable event
various timers in the peripheral. Timers that use the sources to generate the complementary waveform:
COG_clock include: • Rising event source
• Rising and falling dead-band time • Falling event source
• Rising and falling blanking time Level or edge sensitive modes are available for each
• Rising event phase delay event input.
Clock sources available for selection include: The rising event source is selected with the GxRS<2:0>
• 8 MHz HFINTOSC bits and the mode is controlled with the GxRSIM bit.
• Instruction clock (Fosc/4) The falling event source is selected with the GxFS<2:0>
bits and the mode is controlled with the GxFSIM bit.
• System clock (Fosc)
Selection and mode control bits for both sources are
The clock source is selected with the GxCS<1:0> bits located in the COGxCON1 register (Register 11-2).
of the COGxCON0 register (Register 11-1).

PIC12F752/HV752
11.3.1 EDGE VS. LEVEL SENSING 11.3.2 RISING EVENT
Event input detection may be selected as level or edge The rising event starts the PWM output active duty
sensitive. In general, events that are driven from a cycle period. The rising event is the low-to-high
periodic source should be edge detected and events transition of the selected rising event source. When the
that are derived from voltage thresholds at the target phase delay and rising event dead-band time values
circuit should be level sensitive. Consider the following are zero, the COGxOUT0 output starts immediately.
two examples: Otherwise, the COGxOUT0 output is delayed. The
1. The first example is an application in which the rising event causes all the following actions:
period is determined by a 50% duty cycle clock and the • Start rising event phase delay counter (if enabled)
COG output duty cycle is determined by a voltage level • Clear COGxOUT1 after phase delay
fed back through a comparator. If the clock input is level • Start falling event input blanking (if enabled)
sensitive, then duty cycles less than 50% will exhibit
• Start dead-band counter (if enabled)
erratic operation.
• Set COGxOUT0 output after dead-band counter
2. The second example is similar to the first except that expires
the duty cycle is close to 100%. The feedback
comparator high-to-low transition trips the COG drive 11.3.3 FALLING EVENT
off but almost immediately the period source turns the
drive back on. If the off cycle is short enough then the The falling event terminates the PWM output active duty
comparator input may not reach the low side of the cycle period. The falling event is the high-to-low
hysteresis band precluding an output change. The transition of the selected falling event source. When the
comparator output stays low and without a high-to-low falling event dead-band time value is zero, the
transition to trigger the edge sense then the drive of the COGxOUT1 output starts immediately. Otherwise, the
COG output will be stuck in a constant drive-on COGxOUT1 output is delayed. The falling event causes
condition. See Figure 11-4 all the following actions:
• Clear COGxOUT0
FIGURE 11-4: EDGE VS LEVEL SENSE • Start rising event input blanking (if enabled)
• Start falling event dead-band counter (if enabled)
Rising (CCP1) • Set COGxOUT1 output after dead-band counter
Level Sensitive
expires
Falling (C1OUT)
C1In- hyst
COGOUT
Edge Sensitive
Rising (CCP1)
Falling (C1OUT)
C1In- hyst
COGOUT

PIC12F752/HV752
11.4 Output Control 11.5 Dead-Band Control
Immediately after the COG module is enabled, the The dead-band control provides for non-overlapping
complementary drive is configured with COGxOUT0 PWM output signals to prevent shoot through current
drive cleared and COGxOUT1 drive active. in the external power switches.
The COG contains two 4-bit dead-band counters. One
11.4.1 OUTPUT ENABLES
dead-band counter is used for rising event dead-band
Each COG output pin has individual output enable control. The other is used for falling event dead-band
controls. Output enables are selected with the GxOE0 control.
and GxOE1 bits of the COGxCON0 register. When an
Dead band is timed by counting COG_clock periods
output enable control is cleared, the module asserts
from zero up to the value in the dead-band count
no control over the pin. When an output enable is set,
register. Use Equation 11-1 to calculate dead-band
the override value or active PWM waveform is applied
times.
to the pin per the port priority selection.
The output pin enables are independent of the module 11.5.1 RISING EVENT DEAD BAND
enable bit, GxEN. When GxEN is cleared, the Rising event dead band delays the turn-on of
shutdown override levels are present on the COG COGxOUT0 from when COGxOUT1 is turned off. The
output pins for which the output enables are active. rising event dead-band time starts when the rising
event output goes true.
11.4.2 POLARITY CONTROL
The rising event output into the dead-band counter
The polarity of each COG output can be selected
may be delayed by the phase delay. When the phase
independently. When the output polarity bit is set, the
delay time is zero, the rising event output goes true
corresponding output is active low. Clearing the output
coincident with the unblanked rising input event. When
polarity bit configures the corresponding output as
the phase delay time is not zero, the rising event
active high. However, polarity does not affect the
output goes true at the completion of the phase delay
override levels.
time.
Output polarity is selected with the GxPOL0 and
The rising event dead-band time is set by the value
GxPOL1 bits of the COGxCON0 register.
contained in the GxDBR<3:0> bits of the COGxDB
register. When the value is zero, rising event dead
band is disabled.
11.5.2 FALLING EVENT DEAD BAND

Falling event dead band delays the turn-on of
COGxOUT1 from when COGxOUT0 is turned off. The
falling event dead-band time starts when the falling
event output goes true. The falling event output goes
true coincident with the unblanked falling input event.
The falling event dead-band time is set by the value
contained in the GxDBF<3:0> bits of the COGxDB
register. When the value is zero, falling event dead
band is disabled.
11.5.3 DEAD-BAND TIME UNCERTAINTY

When the rising and falling events that trigger the
dead-band counters come from asynchronous inputs,
it creates uncertainty in the dead-band time. The
maximum uncertainty is equal to one COG_clock
period. Refer to Equation 11-1 for more detail.

PIC12F752/HV752
11.5.4 DEAD-BAND OVERLAP 11.6.2 FALLING EVENT INPUT BLANKING
There are two cases of dead-band overlap: The rising event blanking counter inhibits the falling
• Rising-to-falling input from triggering a falling event. The rising event
blanking time starts when the falling event output drive
• Falling-to-rising
goes false.
11.5.4.1 Rising-to-Falling Overlap The rising event blanking time is set by the value
contained in the GxBLKR<3:0> bits of the COGxBLK
In this case, the falling event occurs while the rising
register.
event dead-band counter is still counting. When this
happens, the COGxOUT0 drive is suppressed and the When the GxBLKR<3:0> value is ‘0’, rising event
dead band extends by the falling event dead-band blanking is disabled and the blanking counter output is
time. At the termination of the extended dead-band true, thereby, allowing the event signal to pass straight
time, the COGxOUT1 drive goes true. through to the event trigger circuit.
11.5.4.2 Falling-to-Rising Overlap 11.6.3 BLANKING TIME UNCERTAINTY

In this case, the rising event occurs while the falling When the rising and falling events that trigger the
event dead-band counter is still counting. When this blanking counters are asynchronous to the
happens, the COGxOUT1 drive is suppressed and the COG_clock, it creates uncertainty in the blanking time.
dead band extends by the rising event dead-band The maximum uncertainty is equal to one COG_clock
time. At the termination of the extended dead-band period. Refer to Equation 11-1 and Example 11-1 for
time, the COGxOUT0 drive goes true. more detail.
11.6 Blanking Control

Input blanking is a function whereby the event inputs
can be masked or blanked for a short period of time.
This is to prevent electrical transients caused by the
turn-on/off of power components from generating a
false input event.
The COG contains two 4-bit blanking counters. The
counters are cross coupled with the events they are
blanking. The falling event blanking counter is used to
blank rising input events and the rising event blanking
counter is used to blank falling input events. Once
started, blanking extends for the time specified by the
corresponding blanking counter.
Blanking is timed by counting COG_clock periods from
zero up to the value in the blanking count register. Use
Equation 11-1 to calculate blanking times.
11.6.1 RISING EVENT INPUT BLANKING

The falling event blanking counter inhibits the rising
input from triggering a rising event. The falling event
blanking time starts when the rising event output drive
goes false.
The falling event blanking time is set by the value
contained in the GxBLKF<3:0> bits of the COGxBLK
register. Blanking times are calculated using the
formula shown in Equation 11-1.
When the GxBLKF<3:0> value is ‘0’, falling event
blanking is disabled and the blanking counter output is
true, thereby, allowing the event signal to pass straight
through to the event trigger circuit.

PIC12F752/HV752
11.7 Phase Delay EXAMPLE 11-1: TIMER UNCERTAINTY
It is possible to delay the assertion of the rising event. Given:
This is accomplished by placing a non-zero value in Count = Ah = 10d
COGxPH register. Refer to Register 11-6 and F COG_Clock = 8MHz
Figure 11-3 for COG operation with CCP1 and phase
delay. The delay from the input rising event signal Therefore:
1
switching to the actual assertion of the events is T uncertainty = --------------------------
calculated the same as the dead-band and blanking F COG_clock
delays. Please see Equation 11-1. 1
When the COGxPH value is ‘0’, phase delay is = --------------- = 125ns
8MHz
disabled and the phase delay counter output is true,
thereby, allowing the event signal to pass straight
through to complementary output driver flop. Proof:
Count
11.7.1 CUMULATIVE UNCERTAINTY T min = --------------------------
F COG_clock
It is not possible to create more than one COG_clock of
uncertainty by successive stages. Consider that the = 125ns  10d = 1.25s
phase delay stage comes after the blanking stage, the
dead-band stage comes after either the blanking or Count + 1
T max = --------------------------
phase delay stages, and the blanking stage comes F COG_clock
after the dead-band stage. When the preceding stage
is enabled, the output of that stage is necessarily = 125ns   10d + 1 
synchronous with the COG_clock, which removes any
possibility of uncertainty in the succeeding stage. = 1.375s
Therefore:
EQUATION 11-1: PHASE, DEAD-BAND,
AND BLANKING TIME T uncertainty = T max – T min
CALCULATION
= 1.375s – 1.25s
T min = Count = 125ns
F COG_clock
Count + 1
T max = --------------------------
F COG_clock
T uncertainty = T max – T min
Also:
1
T uncertainty = --------------------------
F COG_clock
Where:
T Count
Phase Delay GxPH<3:0>
Rising Dead Band GxDBR<3:0>
Falling Dead Band GxDBF<3:0>
Rising Event Blanking GxBLKR<3:0>
Falling Event Blanking GxBLKF<3:0>

PIC12F752/HV752
11.8 Auto-Shutdown Control 11.8.2 PIN OVERRIDE LEVELS
Auto-shutdown is a method to immediately override The levels driven to the output pins, while the
the COG output levels with specific overrides that shutdown input is true, are controlled by the GxASDL0
allow for safe shutdown of the circuit. and GxASDL1 bits of the COGxASD register
(Register 11-3). GxASDL0 controls the GxOUT0
The shutdown state can be either cleared override level and GxASDL1 controls the GxOUT1
automatically or held until cleared by software. override level. The control bit logic level corresponds
to the output logic drive level while in the shutdown
11.8.1 SHUTDOWN
state.
The shutdown state can be entered by either of the
Note: The polarity control does not apply to the
following two mechanisms:
override level.
• Software generated
• External Input 11.8.3 AUTO-SHUTDOWN RESTART
After an auto-shutdown event has occurred, there are
11.8.1.1 Software Generated Shutdown
two ways to have the module resume operation:
Setting the GxASDE bit of the COGxASD register will
• Software controlled
force the COG into the shutdown state.
• Auto-restart
When auto-restart is disabled, the shutdown state will
persist as long as the GxASDE bit is set. The restart method is selected with the GxARSEN bit
of the COGxASD register. Waveforms of a software
When auto-restart is enabled, the GxASDE bit will controlled automatic restart are shown in Figure 11-5.
clear automatically and resume operation on the next
rising event. See Figure 11-5. 11.8.3.1 Software Controlled Restart
11.8.1.2 External Shutdown Source When the GxARSEN bit of the COGxASD register is
cleared, the COG must be restarted after an
External shutdown inputs provide the fastest way to auto-shutdown event by software.
safely suspend COG operation in the event of a fault
condition. When any of the selected shutdown inputs The COG will resume operation on the first rising
goes true, the output drive latches are reset and the event after the GxASDE bit is cleared. Clearing the
COG outputs will immediately go to the selected shutdown state requires all selected shutdown inputs
override levels without software delay. to be false, otherwise, the GxASDE bit will remain set.
Any combination of four input sources can be selected 11.8.3.2 Auto-Restart

to cause a shutdown condition. The four sources
When the GxARSEN bit of the COGxASD register is
include:
set, then the COG will restart from the auto-shutdown
• HLTimer1 output state automatically.
• C2OUT (low true) The GxASDE bit will clear automatically and the COG
• C1OUT (low true) will resume operation on the first rising event after all
• COG1FLT pin (low true) selected shutdown inputs go false.
Shutdown inputs are selected independently with bits
<3:0> of the COGxASD register (Register 11-3).
Note: Shutdown inputs are level sensitive, not

edge sensitive. The shutdown state cannot
be cleared as long as the shutdown input
level persists, except by disabling
auto-shutdown,

FIGURE 11-5:
DS40001576D-page 82
1 2 3 4 5
SOURCE
CCP1
GxARSEN
Next rising event

Shutdown input
PIC12F752/HV752
Next rising event Cleared in hardware

GxASDE Cleared in software
GxASDL0
GxASDL1
COGxOUT0
COGxOUT1
Operating State
NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT
SOFTWARE CONTROLLED RESTART AUTO-RESTART

AUTO-SHUTDOWN WAVEFORM – CCP1 AS RISING AND FALLING EVENT INPUT
 2011-2015 Microchip Technology Inc.

PIC12F752/HV752
11.9 Buffer Updates 11.12 Configuring the COG
Changes to the phase, dead band, and blanking count The following steps illustrate how to properly configure
registers need to occur simultaneously during COG the COG to ensure a synchronous start with the rising
operation to avoid unintended operation that may event input:
occur as a result of delays between each register 1. Configure the desired COGxFLT input,
write. This is accomplished with the GxLD bit of the COGxOUT0 and COGxOUT1 pins with the
COGxCON0 register and double buffering of the corresponding bits in the APFCON register.
phase, blanking, and dead-band count registers.
2. Clear all ANSELA register bits associated with
Before the COG module is enabled, writing the count pins that are used for COG functions.
registers loads the count buffers without need of the 3. Ensure that the TRIS control bits corresponding
GxLD bit. However, when the COG is enabled, the to COGxOUT0 and COGxOUT1 are set so that
count buffers updates are suspended after writing the both are configured as inputs. These will be set
count registers until after the GxLD bit is set. When the as outputs later.
GxLD bit is set, the phase, dead band and blanking
4. Clear the GxEN bit, if not already cleared.
register values are transferred to the corresponding
buffers synchronous with COG operation. The GxLD 5. Set desired dead-band times with the COGxDB
bit is cleared by hardware to indicate that the transfer register.
is complete. 6. Set desired blanking times with the COGxBLK
register.
11.10 Alternate Pin Selection 7. Set desired phase delay with the COGxPH
register.
The COGxOUT0, COGxOUT1 and COGxFLT
8. Setup the following controls in COGxASD
functions can be directed to alternate pins with control
auto-shutdown register:
bits of the APFCON register. Refer to Register 5-1.
• Select desired shutdown sources.
Note: The default COG outputs have high drive • Select both output overrides to the desired
strength capability, whereas the alternate levels (this is necessary, even if not using
outputs do not. auto-shutdown because start-up will be from
a shutdown state).
11.11 Operation During Sleep • Set the GxASDE bit and clear the GxARSEN
The COG continues to operate in Sleep provided that bit.
the COG_clock, rising event and falling event sources 9. Select the desired rising and falling event
remain active. sources and input modes with the COGxCON1
register.
The HFINTSOC remains active during Sleep when the
COG is enabled and the HFINTOSC is selected as the 10. Configure the following controls in COGxCON0
COG_clock source. register:
• Select the desired clock source
• Select the desired output polarities
• Set the output enables of the outputs to be
used.
11. Set the GxEN bit.
12. Clear TRIS control bits corresponding to
COGxOUT0 and COGxOUT1 to be used
thereby configuring those pins as outputs.
13. If auto-restart is to be used, set the GxARSEN bit
and the GxASDE will be cleared automatically.
Otherwise, clear the GxASDE bit to start the
COG.

PIC12F752/HV752
11.13 COG Control Registers
REGISTER 11-1: COGxCON0: COG CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
GxEN GxOE1 GxOE0 GxPOL1 GxPOL0 GxLD GxCS<1:0>
bit 7 bit 0
Legend:
bit 7 GxEN: COGx Enable bit

1 = Module is enabled
0 = Module is disabled
bit 6 GxOE1: COGxOUT1 Output Enable bit
1 = COGxOUT1 is available on associated I/O pin
0 = COGxOUT1 is not available on associated I/O pin
bit 5 GxOE0: COGxOUT0 Output Enable bit
1 = COGxOUT0 is available on associated I/O pin
0 = COGxOUT0 is not available on associated I/O pin
bit 4 GxPOL1: COGxOUT1 Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 3 GxPOL0: COGxOUT0 Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 2 GxLD: COGx Load Buffers bit
1 = Phase, blanking, and dead-band buffers to be loaded with register values on next input events
0 = Register to buffer transfer is complete
bit 1-0 GxCS<1:0>: COGx Clock Source Select bits
11 = Reserved
10 = 8 MHz HFINTOSC clock
01 = Instruction clock (Fosc/4)
00 = System clock (Fosc)

PIC12F752/HV752
REGISTER 11-2: COGxCON1: COG CONTROL REGISTER 1

GxFSIM GxRSIM GxFS<2:0> GxRS<2:0>
bit 7 bit 0
Legend:
bit 7 GxFSIM: COGx Falling Source Input Mode bit

1 = Input is edge sensitive
0 = Input is level sensitive
bit 6 GxRSIM: COGx Rising Source Input Mode bit
1 = Input is edge sensitive
0 = Input is level sensitive
bit 5-3 GxFS<2:0>: COGx Falling Source Select bits
111 = COGxFLT or HLTimer1
110 = CCP1 or HLTimer1
101 = C2OUT or HLTimer1
011 = COGxFLT
010 = CCP1
001 = C2OUT
000 = C1OUT
bit 2-0 GxRS<2:0>: COGx Rising Source Select bits
111 = COGxFLT or HLTimer1
110 = CCP1 or HLTimer1
011 = COGxFLT
010 = CCP1
001 = C2OUT
000 = C1OUT

PIC12F752/HV752
REGISTER 11-3: COGxASD: COG AUTO-SHUTDOWN CONTROL REGISTER

GxASDE GxARSEN GxASDL1 GxASDL0 GxASDSHLT GxASDSC2 GxASDSC1 GxASDSFLT
bit 7 bit 0
Legend:
bit 7 GxASDE: Auto-Shutdown Event Status bit

1 = COG is in the shutdown state
0 = COG is not in the shutdown state
bit 6 GxARSEN: Auto-Restart Enable bit
1 = Auto-restart is enabled
0 = Auto-restart is disabled
bit 5 GxASDL1: COGxOUT1 Auto-shutdown Override Level bit
1 = A logic ‘1’ is placed on COGxOUT1 when a shutdown input is true
bit 4 GxASDL0: COGxOUT0 Auto-shutdown Override Level bit
bit 3 GxASDSHLT: COG Auto-shutdown Source Enable bit 3
1 = COG is shutdown when HLTMR equals HLTPR is low
0 = HLTimer1 pin has no effect on shutdown
bit 2 GxASDSC2: COG Auto-shutdown Source Enable bit 2
1 = COG is shutdown when C2OUT is low
0 = C2OUT pin has no effect on shutdown
bit 1 GxASDSC1: COG Auto-shutdown Source Enable bit 1
1 = COG is shutdown when C1OUT is low
0 = C1OUT pin has no effect on shutdown
bit 0 GxASDSFLT: COG Auto-shutdown Source Enable bit 0
1 = COG is shutdown when COGxFLT pin is low
0 = COGxFLT pin has no effect on shutdown

PIC12F752/HV752
REGISTER 11-4: COGxDB: COG DEAD-BAND COUNT REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
GxDBR<3:0> GxDBF<3:0>
bit 7 bit 0
Legend:
bit 7-4 GxDBR<3:0>: Rising Event Dead-band Count Value bits

Number of COG clock periods to delay primary output after rising event input
bit 3-0 GxDBF<3:0>: Falling Event Dead-band Count Value bits
Number of COG clock periods to delay complementary output after falling event input
REGISTER 11-5: COGxBLK: COG BLANKING COUNT REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
GxBLKR<3:0> GxBLKF<3:0>
bit 7 bit 0
Legend:
bit 7-4 GxBLKR<3:0>: Rising Event Blanking Count Value bits

Number of COGx clock periods to inhibit falling event input
bit 3-0 GxBLKF<3:0>: Falling Event Blanking Count Value bits
Number of COGx clock periods to inhibit rising event input
REGISTER 11-6: COGxPH: COG PHASE COUNT REGISTER
U-0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — GxPH<3:0>
bit 7 bit 0
Legend:

bit 3-0 GxPH<3:0>: Rising Event Phase Delay Count Value bits
Number of COG clock periods to delay rising edge event

PIC12F752/HV752
TABLE 11-1: SUMMARY OF REGISTERS ASSOCIATED WITH COG
Register
on Page
APFCON — — — T1GSEL — COG1FSEL COG1O1SEL COG1O0SEL 38
COG1PH — — — — G1PH<3:0> 87
COG1BLK G1BLKR<3:0> G1BLKF<3:0> 87
COG1DB G1DBR<3:0> G1DBF<3:0> 87
COG1CON0 G1EN G1OE1 G1OE0 G1POL1 G1POL0 G1LD G1CS1 G1CS0 84
COG1CON1 G1FSIM G1RSIM G1FS<2:0> G1RS<2:0> 85
COG1ASD G1ASDE G1ARSEN G1ASDL1 G1ASDL0 G1ASDSHLT G1ASDSC2 G1ASDSC1 G1ASDSFLT 86
TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 40
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by COG.
2: See Configuration Word register (Register 17-1) for operation of all register bits.

PIC12F752/HV752
12.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD or a voltage applied to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 12-1 shows the block diagram of the ADC.
Note: The ADRESL and ADRESH registers are
read-only.
FIGURE 12-1: ADC BLOCK DIAGRAM
VDD
VCFG = 0
VREF+ VCFG = 1
AN0 0000
AN1/VREF+ 0001
AN2 0010
AN3 0011 A/D
GO/DONE 10
dac_ref 1110
0 = Left Justify
fvr_ref 1111 ADFM
1 = Right Justify
ADON 10
CHS<3:0> Vss ADRESH ADRESL

PIC12F752/HV752
12.1 ADC Configuration 12.1.4 CONVERSION CLOCK
When configuring and using the ADC the following The source of the conversion clock is software
functions must be considered: selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
• Port configuration
• FOSC/2
• Channel selection
• FOSC/4
• ADC voltage reference selection
• FOSC/8
• ADC conversion clock source
• FOSC/16
• Interrupt control
• FOSC/32
• Results formatting
• FOSC/64
12.1.1 PORT CONFIGURATION • FRC (dedicated internal oscillator)
The ADC can be used to convert both analog and digital The time to complete one bit conversion is defined as
signals. When converting analog signals, the I/O pin TAD. One full 10-bit conversion requires 11 TAD periods
should be configured for analog by setting the associated as shown in Figure 12-2.
TRIS and ANSEL bits. See the corresponding port For correct conversion, the appropriate TAD specification
section for more information. must be met. See A/D conversion requirements in
Note: Analog voltages on any pin that is defined Section 20.0 “Electrical Specifications” for more
as a digital input may cause the input buf- information. Table 12-1 gives examples of appropriate
fer to conduct excess current. ADC clock selections.
Note: Unless using the FRC, any changes in the
12.1.2 CHANNEL SELECTION system clock frequency will change the
The CHS bits of the ADCON0 register determine which ADC clock frequency, which may
channel is connected to the sample and hold circuit. adversely affect the ADC result.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 12.2
“ADC Operation” for more information.
12.1.3 ADC VOLTAGE REFERENCE

The VCFG bit of the ADCON0 register provides control
of the positive voltage reference. The positive voltage
reference can be either VDD or an external voltage
source. The negative voltage reference is always
connected to the ground reference.

PIC12F752/HV752
TABLE 12-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz

FOSC/2 000 100 ns (2)
250 ns (2)
500 ns (2)
2.0 s
FOSC/4 100 200 ns (2)
500 ns (2)
1.0 s (2)
4.0 s
FOSC/8 001 400 ns(2) 1.0 s(2) 2.0 s 8.0 s(3)
FOSC/16 101 800 ns(2) 2.0 s 4.0 s 16.0 s(3)
FOSC/32 010 1.6 s 4.0 s 8.0 s (3)
32.0 s(3)
FOSC/64 110 3.2 s 8.0 s(3) 16.0 s(3) 64.0 s(3)
FRC x11 2-6 s (1,4)
2-6 s (1,4)
2-6 s (1,4)
2-6 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
FIGURE 12-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit

ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
12.1.5 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.

PIC12F752/HV752
12.1.6 RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 12-4 shows the two output formats.
FIGURE 12-3: 10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
10-bit A/D Result Unimplemented: Read as ‘0’
(ADFM = 1) MSB LSB

bit 7 bit 0 bit 7 bit 0
Unimplemented: Read as ‘0’ 10-bit A/D Result
12.2 ADC Operation 12.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This
12.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC
To enable the ADC module, the ADON bit of the option. When the FRC clock source is selected, the
ADCON0 register must be set to a ‘1’. Setting the GO/ ADC waits one additional instruction before starting the
DONE bit of the ADCON0 register to a ‘1’ will start the conversion. This allows the SLEEP instruction to be
Analog-to-Digital conversion. executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
Note: The GO/DONE bit should not be set in the
will wake-up from Sleep when the conversion
same instruction that turns on the ADC.
completes. If the ADC interrupt is disabled, the ADC
Refer to Section 12.2.6 “A/D Conver-
module is turned off after the conversion completes,
sion Procedure”.
although the ADON bit remains set.
12.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present
When the conversion is complete, the ADC module will: conversion to be aborted and the ADC module is
• Clear the GO/DONE bit turned off, although the ADON bit remains set.
• Set the ADIF flag bit
12.2.5 SPECIAL EVENT TRIGGER
• Update the ADRESH:ADRESL registers with new
conversion result The CCP Special Event Trigger allows periodic ADC
measurements without software intervention. When
12.2.3 TERMINATING A CONVERSION this trigger occurs, the GO/DONE bit is set by hardware
If a conversion must be terminated before completion, and the Timer1 counter resets to zero.
the GO/DONE bit can be cleared in software. The Using the Special Event Trigger does not assure proper
ADRESH:ADRESL registers will not be updated with ADC timing. It is the user’s responsibility to ensure that
the partially complete Analog-to-Digital conversion the ADC timing requirements are met.
sample. Instead, the ADRESH:ADRESL register pair See Section 10.0 “Capture/Compare/PWM
will retain the value of the previous conversion. Modules” for more information.
Additionally, a 2 TAD delay is required before another
acquisition can be initiated. Following this delay, an
input acquisition is automatically started on the
selected channel.
Note: A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.

PIC12F752/HV752
12.2.6 A/D CONVERSION PROCEDURE EXAMPLE 12-1: A/D CONVERSION
This is an example procedure for using the ADC to ;This code block configures the ADC
perform an Analog-to-Digital conversion: ;for polling, Vdd reference, Frc clock
;and RA0 input.
1. Configure Port:
;
• Disable pin output driver (See TRIS register) ;Conversion start & polling for completion
• Configure pin as analog ; are included.
;
2. Configure the ADC module:
BANKSEL TRISA ;
• Select ADC conversion clock BSF TRISA,0 ;Set RA0 to input
• Configure voltage reference BANKSEL ADCON1 ;
• Select ADC input channel MOVLW B’01110000’ ;ADC Frc clock,
IORWF ADCON1 ; and RA0 as analog
• Select result format BANKSEL ADCON0 ;
• Turn on ADC module MOVLW B’10000001’ ;Right justify,
3. Configure ADC interrupt (optional): MOVWF ADCON0 ;Vdd Vref, AN0, On
CALL SampleTime ;Acquisiton delay
• Clear ADC interrupt flag
BSF ADCON0,GO ;Start conversion
• Enable ADC interrupt TEST AGAIN
• Enable peripheral interrupt BTFSC ADCON0,GO ;Is conversion done?
GOTO TEST AGAIN ;No, test again
• Enable global interrupt(1)
BANKSEL ADRESH ;
4. Wait the required acquisition time(2) MOVF ADRESH,W ;Read upper 2 bits
5. Start conversion by setting the GO/DONE bit MOVWF RESULTHI ;Store in GPR space
6. Wait for ADC conversion to complete by one of BANKSEL ADRESL ;
the following: MOVF ADRESL,W ;Read lower 8 bits
MOVWF RESULTLO ;Store in GPR space
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result
8. Clear the ADC interrupt flag (required if interrupt
is enabled)
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: See Section 12.4 “A/D Acquisition
Requirements”.

PIC12F752/HV752
12.3 ADC Control Registers
REGISTER 12-1: ADCON0: A/D CONTROL REGISTER 0
ADFM VCFG CHS<3:0> GO/DONE ADON
bit 7 bit 0
Legend:
bit 7 ADFM: A/D Conversion Result Format Select bit

1 = Right justified
0 = Left justified
bit 6 VCFG: Voltage Reference bit
1 = VREF pin
0 = VDD
bit 5-2 CHS<3:0>: Analog Channel Select bits
0000 = Channel 00 (AN0)
0001 = Channel 01 (AN1)
0010 = Channel 02 (AN2)
0011 = Channel 03 (AN3)
0100 = Reserved. Do not use.
•
•
•
1101 = Reserved. Do not use.
1110 = Digital-to-Analog Converter (DAC output)
1111 = Fixed Voltage Reference (FVR)
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current

PIC12F752/HV752
REGISTER 12-2: ADCON1: A/D CONTROL REGISTER 1
U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
— ADCS<2:0> — — — —
bit 7 bit 0
Legend:

bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock supplied from an internal oscillator with a divisor of 16)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64

PIC12F752/HV752
REGISTER 12-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY)
R-x R-x R-x R-x R-x R-x R-x R-x
ADRES<9:2>
bit 7 bit 0
Legend:
bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result
REGISTER 12-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY)
R-x R-x U-0 U-0 U-0 U-0 U-0 U-0
ADRES<1:0> — — — — — —
bit 7 bit 0
Legend:

Lower two bits of 10-bit conversion result
REGISTER 12-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY)
U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x
— — — — — — ADRES<9:8>
bit 7 bit 0
Legend:

Upper two bits of 10-bit conversion result
REGISTER 12-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY)
R-x R-x R-x R-x R-x R-x R-x R-x
ADRES<7:0>
bit 7 bit 0
Legend:

Lower eight bits of 10-bit conversion result

PIC12F752/HV752
12.4 A/D Acquisition Requirements After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
For the ADC to meet its specified accuracy, the charge can be started. To calculate the minimum acquisition
holding capacitor (CHOLD) must be allowed to fully time, Equation 12-1 may be used. This equation
charge to the input channel voltage level. The Analog assumes that 1/2 LSb error is used (1024 steps for the
Input model is shown in Figure 12-4. The source ADC). The 1/2 LSb error is the maximum error allowed
impedance (RS) and the internal sampling switch (RSS) for the ADC to meet its specified resolution.
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 12-4.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
EQUATION 12-1: ACQUISITION TIME EXAMPLE
Assumptions: Temperature = 50°C and external impedance of 10k  5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2µs + T C +   Temperature - 25°C   0.05µs/°C  
The value for TC can be approximated with the following equations:
V AP PLIE D  1 – ------------ = V CHOLD

1
;[1] VCHOLD charged to within 1/2 lsb
2047
–TC
 ----------
RC
V AP P LI ED  1 – e  = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
 
– Tc
 ---------
V AP P LIED  1 – e  = V A P PLIE D  1 – ------------
RC 1 ;combining [1] and [2]
  2047
Solving for TC:
T C = – C HOLD  R IC + R SS + R S  ln(1/2047)
= – 10pF  1k  + 7k  + 10k   ln(0.0004885)
= 1.37 µs
Therefore:
T ACQ = 2µs + 1.37µs +   50°C- 25°C   0.05µs/°C  
= 4.67µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

PIC12F752/HV752
FIGURE 12-4: ANALOG INPUT MODEL
VDD
Sampling
Switch
Vt = 0.6V
Rs ANx Ric  1k SS Rss
VA Cpin I leakage
Vt = 0.6V Chold = 10 pF
5 pF ± 500 nA
Vss/VREF-
6V
5V Rss
Legend: Cpin = Input Capacitance VDD 4V
Vt = Threshold Voltage 3V
I leakage = Leakage current at the pin due to 2V
various junctions
Ric = Interconnect Resistance 5 6 7 8 9 10 11
SS = Sampling Switch Sampling Switch
Chold = Sample/Hold Capacitance (k)
FIGURE 12-5: ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
1 LSB ideal
3FBh
Full-Scale
004h Transition
003h
002h
001h
000h Analog Input Voltage
1 LSB ideal
VSS/VREF- Zero-Scale VDD/VREF+

Transition

PIC12F752/HV752
TABLE 12-2: SUMMARY OF ASSOCIATED ADC REGISTERS
Register on
Page
ADCON0 ADFM VCFG CHS<3:0> GO/DONE ADON 94

ADCON1 — ADCS<2:0> — — — — 94
ADRESH(2) A/D Result Register High Byte 96*
ADRESL(2) A/D Result Register Low Byte 94*
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
2: Read-only register.

PIC12F752/HV752
13.0 FIXED VOLTAGE REFERENCE 13.2 FVR Stabilization Period
(FVR) When the Fixed Voltage Reference module is enabled, it
The Fixed Voltage Reference (FVR) is a stable voltage requires time for the reference circuit to stabilize. Once
reference, independent of VDD, with 1.2V output level. the circuit stabilizes and is ready for use, the FVRRDY bit
The output of the FVR can be configured to supply a of the FVRCON register will be set. See Section 20.0
reference voltage to the following: “Electrical Specifications” for the minimum delay
requirement.
• ADC input channel
• Comparator 1 positive input (C1VP) 13.3 Operation During Sleep
• Comparator 2 positive input (C2VP)
When the device wakes up from Sleep through an
• REFOUT pin
interrupt or a Watchdog Timer time-out, the contents of
On the PIC12F752, the FVR is enabled by setting the the FVRCON register are not affected. To minimize
FVREN bit of the FVRCON register. The FVR is always current consumption in Sleep mode, FVR the voltage
enabled on the PIC12HV752 device. reference should be disabled.
13.1 Fixed Voltage Reference Output 13.4 Effects of a Reset

The FVR output can be applied to the REFOUT pin by A device Reset clears the FVRCON register. As a result:
setting the FVRBUFSS and FVRBUFEN bits of the
• The FVR module is disabled
FVRCON register. The FVRBUFSS bit selects either
the FVR or DAC output reference to the REFOUT pin • The FVR voltage output is disabled on the
buffer. The FVRBUFEN bit enables the output buffer to REFOUT pin
the REFOUT pin.
Enabling the REFOUT pin automatically overrides any
digital input or output functions of the pin. Reading the
REFOUT pin when it has been configured for a
reference voltage output will always return a ‘0’.
FIGURE 13-1: VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
5V Shunt
VREF+
Regulator
DACPSS
PIC12HV752 only
DACR<4:0>
DACRNG DAC dac_ref
DACEN EN To ADC, Comparators
C1 and C2.
Vss
dac_ref 0
VDD x1 REFOUT
1 DACOUT
fvr_ref
ref FVRBUFSS
fvr_ref
DACOE
To ADC, Comparators FVRBUFEN
+
C1 and C2.
1.2V
-
12HV752
EN rdy FVRRDY
FVREN
VSS

PIC12F752/HV752
13.5 FVR Control Registers
REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0 R-q/q R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
FVREN FVRRDY FVRBUFEN FVRBUFSS — — — —
bit 7 bit 0
Legend:
bit 7 FVREN: Fixed Voltage Reference Enable bit

0 = Fixed Voltage Reference is disabled
1 = Fixed Voltage Reference is enabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit
0 = Fixed Voltage Reference output is not ready or not enabled bit
1 = Fixed Voltage Reference output is ready for use
bit 5 FVRBUFEN: Voltage Reference Output Pin Buffer Enable
0 = Output buffer is disabled
1 = Output buffer is enabled
bit 4 FVRBUFSS: Voltage Reference Pin Buffer Source Select bit
0 = Bandgap (1.2V) is the input to the output voltage buffer
1 = dac_out is the input to the output voltage buffer
TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Register
on page
FVRCON FVREN FVRRDY FVRBUFEN FVRBUFSS — — — — 101
Legend: Shaded cells are not used with the Fixed Voltage Reference.

PIC12F752/HV752
14.0 DIGITAL-TO-ANALOG The output of the DAC module provides a reference
voltage to the following:
CONVERTER (DAC) MODULE
• Comparator positive input
The 5-bit, dual range Digital-to-Analog Converter
• ADC input channel
(DAC) module supplies a variable voltage reference,
with 64 selectable output levels of which three levels • FVR input reference
are duplicated. The output is ratiometric with respect to • DACOUT pin
the input source, VSRC+. See Figure 14-1 for a block The DAC is enabled by setting the DACEN bit of the
diagram of the DAC module. DACCON0 register.
The input of the DAC can be connected to two external
voltage connections:
• VDD pin
• VREF+ pin
FIGURE 14-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
VREF+ 1 VSRC+
VDD 0
R2(31)
DACPSS
11111
DACEN R2(30)
11110
dac_ref
Full Range (to Comparator, FVR
FVR and ADC modules)
R2(2)
00010
00001
DACOUT
1
00000
0
DACR<4:0>
5
DACRNG
R1(31)
DACOE
11111
R1(30)
R2(1) 11110
R1(16)
10000
R1(15)
01111 Limited Range
R2(0)
R1(1)
00001
R1(0)
00000
Note: R2 = 16*R1

PIC12F752/HV752
14.1 DAC Positive Voltage Source 14.3 Ratiometric Output Level
The DACPSS bit of the DACCON0 register selects the The DAC output value is derived using a resistor ladder
positive voltage source, VSRC+. The following voltage with one end of the ladder tied to the positive voltage
sources are available: reference and the other end tied to VSS. If the voltage of
• VDD pin (default) the input source fluctuates, a similar fluctuation will
result in the DAC output value.
• VREF+ pin
The resistor values within the ladder can be found in
DAC module can select the positive voltage source
Section 20.0 “Electrical Specifications”.
using the DACPSS bit of the DACCON0 register. The
default source, DACPSS = 0, connects VDD to the
positive voltage source (VSRC+). VSRC+ can be 14.4 DAC Output Voltage
changed to the VREF+ pin by setting DACPSS = 1. The DAC output voltage level of the DAC is determined
by the DACRNG and the DACR<4:0> bits of the
14.2 DAC Range Selection DACCON0 and DACCON1 registers, respectively.
The DACRNG bit of the DACCON0 register selects Use Equation 14-1 to determine the value of the DAC
between full-range or limited-range DAC output output voltage. Example 14-1 illustrates the calculations
voltage. of the minimum, maximum and increment size of the
DAC output voltage in Full Range mode. Example 14-2
Each range selects the output in 32 equal steps.
illustrates the Limited Range mode of the DAC output
In Full-Range mode, the output is (31/32)*VSRC+. In voltage values.
Limited-Range mode, the maximum VOUT is limited to
6% of VSRC+, (31/512) * VSRC+.
EQUATION 14-1: DAC OUTPUT VOLTAGE
  DACR  4:0  
V OUT =   VSRC+   ------------------------------ 
  2
n 
Note: The value of ‘n’ is determined by the DACRNG bit.

When: DACRNG = 0 (Limited Range mode); n = 9;
DACRNG = 1 (Full Range mode); n = 5.
EXAMPLE 14-1: FULL RANGE MODE

Given: VSRC = VDD = 5V, DACRNG = 1 VOUT = [VSRC+ * (DACR<4:0>/25)]
Minimum VOUT Calculation: Maximum VOUT Calculation: Step Increment Calculation:

DACR<4:0> = 0 0000b, (0d); DACR<4:0> = 1 1111b, (31d); DACR<4:0> = 0 0001b, (1d);
VOUT = [5V * (0/32)] = 0V; VOUT = [5V * (31/32)] = 4.84V; VOUT = [5V * (1/32)] = 156 mV
Full Range Mode Operation:

0V VOUT 4.84V, with 32-step increments of 156 mV.
EXAMPLE 14-2: LIMITED RANGE MODE

Given: VSRC = VDD = 5V, DACRNG = 0 VOUT = [VSRC+ * (DACR<4:0>/29)]
Minimum VOUT Calculation: Maximum VOUT Calculation: Step Increment Calculation:

DACR<4:0> = 0 0000b, (0d); DACR<4:0> = 1 1111b, (31d); DACR<4:0> = 0 0001b, (1d);
VOUT = [5V * (0/512)] = 0V; VOUT = [5V * (31/512)] = 303 mV; VOUT = [5V * (1/512)] = 9.8 mV
Limited Range Mode Operation:

0V VOUT 303 mV, with 32-step increments of 9.8 mV.

PIC12F752/HV752
FIGURE 14-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
Module R
+
Voltage DACOUT Buffered DAC Output
–
Reference
Output
Impedance
14.5 DAC Voltage Reference Output 14.6 Operation During Sleep

The DAC output (dac_ref) can be applied to the When the device wakes up from Sleep through an
DACOUT pin as an unbuffered signal by: interrupt or a Watchdog Timer time-out, the contents of
• Setting the DACOE bit of the DACCON0 register the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
• Clearing the FVRBUFSS bit of the FVRCON
reference should be disabled.
register
• Clearing the FVRBUFEN bit of the FVRCON
14.7 Effects of a Reset
register
Figure 14-3 shows a block diagram pin configuration A device Reset clears the DACCON0 and DACCON1
for the dac_ref and fvr_ref signals. This unbuffered registers. As a result:
DACOUT pin has limited current drive capability. When • The DAC module is disabled
a higher drive current is required, an external buffer can • The DAC voltage output is disabled on the
be used on the DACOUT pin. Figure 14-2 shows an DACOUT pin
example of buffering technique.
The DAC output can also be configured to use an
internal buffer by:
• Setting the FVRBUFEN bit of the FVRCON
register changing the pin configuration to be the
REFOUT pin
Enabling the DACOUT pin automatically overrides any
digital input or output functions of the pin. Reading the
DACOUT pin when it has been configured for DAC
reference voltage output will always return a ‘0’.
FIGURE 14-3: DAC/FVR OUTPUT PIN
dac_ref 0
x1 REFOUT
1 DACOUT
fvr_ref
FVRBUFSS
DACOE
FVRBUFEN

PIC12F752/HV752
14.8 DAC Control Registers
REGISTER 14-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 U-0 U-0
DACEN DACRNG DACOE — — DACPSS — —
bit 7 bit 0
Legend:
bit 7 DACEN: DAC Enable bit

1 = DAC is enabled
0 = DAC is disabled
bit 6 DACRNG: DAC Range Selection bit(1)
1 = DAC is operating in Full Range mode
0 = DAC is operating in Limited Range mode
bit 5 DACOE: DAC Voltage Output Enable bit
1 = DAC reference output is enabled to the DACOUT pin(2)
0 = DAC reference output is disabled
bit 2 DACPSS: DAC Positive Source Select bits
0 = VDD
1 = VREF+ pin
Note 1: Refer to Equation 14-1.
2: The DACOUT pin configuration requires additional control bits in the FVRCON register (see Figure 14-3).
REGISTER 14-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — DACR<4:0>
bit 7 bit 0
Legend:

bit 4-0 DACR<4:0>: DAC Voltage Output Select bits
1 1111 = DAC Voltage Maximum Output



0 0000 = DAC Voltage Minimum Output
Note 1: Refer to Equation 14-1 to calculate the value of the DAC Voltage Output.

PIC12F752/HV752
TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE
Register
on page
DACCON0 DACEN DACRNG DACOE — — DACPSS — — 105
DACCON1 — — — DACR<4:0> 105
FVRCON FVREN FVRRDY FVRBUFEN FVRBUFSS — — — — 101
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the DAC module.

PIC12F752/HV752
15.0 COMPARATOR MODULE FIGURE 15-1: SINGLE COMPARATOR
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and VIN+ +
providing a digital indication of their relative magnitudes. Output
Comparators are very useful mixed signal building VIN- –
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
• Independent comparator control VIN-
• Programmable input selection VIN+
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
• Wake-up from Sleep Output
• Programmable Speed/Power optimization
• PWM shutdown
Note: The black areas of the output of the
• Programmable and fixed voltage reference
comparator represents the uncertainty
15.1 Comparator Overview due to input offsets and response time.
A single comparator is shown in Figure 15-1 along with

the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.

PIC12F752/HV752
FIGURE 15-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
CxNCH0 Interrupt CxINTP

CxON(1)
det
Set CxIF
CXIN0- 0
MUX Interrupt CxINTN
(2)
CXIN1- 1 det
CXPOL
CxVN 0 CXOUT
- D Q To Data Bus
MCXOUT
Cx ZLF 1
+ Q1 EN
CxVP
CXIN+ 0 CXZLF
CxHYS
To COG Module
dac_ref 1 MUX CxSP
(2)
fvr_ref 2
CXSYNC
3 CXOE
TRIS bit
VSS CxON
CXOUT
0
CXPCH<1:0>
2 D Q 1
(from Timer1)
T1CLK To Timer1
SYNCCXOUT
Note 1: When CxON = 0, the comparator will produce a ‘0’ at the output.
2: When CxON = 0, all multiplexer inputs are disconnected.

PIC12F752/HV752
15.2 Comparator Control 15.2.3 COMPARATOR OUTPUT POLARITY
Each comparator has two control registers: CMxCON0 Inverting the output of the comparator is functionally
and CMxCON1. equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
The CMxCON0 registers (see Register 15-1) contain setting the CxPOL bit of the CMxCON0 register.
Control and Status bits for the following: Clearing the CxPOL bit results in a non-inverted output.
• Enable Table 15-1 shows the output state versus input
• Output selection conditions, including polarity control.
• Output pin enable TABLE 15-1: COMPARATOR OUTPUT
• Output polarity STATE VS. INPUT
• Speed/Power selection CONDITIONS
• Hysteresis enable Input Condition CxPOL CxOUT
• Output synchronization
CxVN > CxVP 0 0
The CMxCON1 registers (see Register 15-2) contain
CxVN < CxVP 0 1
Control bits for the following:
CxVN > CxVP 1 1
• Interrupt edge polarity (rising and/or falling)
CxVN < CxVP 1 0
• Positive input channel selection
• Negative input channel selection 15.2.4 COMPARATOR SPEED/POWER
15.2.1 COMPARATOR ENABLE SELECTION
The trade-off between speed or power can be
Setting the CxON bit of the CMxCON0 register enables
optimized during program execution with the CxSP
the comparator for operation. Clearing the CxON bit
control bit. The default state for this bit is ‘1’ which
disables the comparator resulting in minimum current
selects the normal speed mode. Device power
consumption.
consumption can be optimized at the cost of slower
15.2.2 COMPARATOR OUTPUT comparator propagation delay by clearing the CxSP bit
to ‘0’.
SELECTION
The output of the comparator can be monitored by 15.3 Comparator Hysteresis
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to A selectable amount of separation voltage can be
make the output available for an external connection, added to the input pins of each comparator to provide a
the following conditions must be true: hysteresis function to the overall operation. Hysteresis
• CxOE bit of the CMxCON0 register must be set is enabled by setting the CxHYS bit of the CMxCON0
register.
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set See Section 20.0 “Electrical Specifications” for more
information.
Note 1: The CxOE bit of the CMxCON0 register 15.4 Timer1 Gate Operation
overrides the PORT data latch. Setting
The output resulting from a comparator operation can
the CxON bit of the CMxCON0 register
be used as a source for gate control of Timer1. See
has no impact on the port override.
Section 7.5 “Timer1 Gate” for more information. This
2: The internal output of the comparator is feature is useful for timing the duration or interval of an
latched with each instruction cycle. analog event.
Unless otherwise specified, external
It is recommended that the comparator output be
outputs are not latched.
synchronized to Timer1. This ensures that Timer1 does
not increment while a change in the comparator is
occurring.

PIC12F752/HV752
15.4.1 COMPARATOR OUTPUT 15.6 Comparator Positive Input
SYNCHRONIZATION Selection
The output from either comparator, C1 or C2, can be Configuring the CxPCH<1:0> bits of the CMxCON1
synchronized with Timer1 by setting the CxSYNC bit of register directs an internal voltage reference or an
the CMxCON0 register. analog pin to the non-inverting input of the comparator:
Once enabled, the comparator output is latched on the • CxIN0+ analog pin
falling edge of the Timer1 source clock. If a prescaler is
• DAC Reference Voltage (dac_ref)
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the • FVR Reference Voltage (fvr_ref)
comparator output is latched on the falling edge of the • VSS (Ground)
Timer1 clock source and Timer1 increments on the See Section 13.0 “Fixed Voltage Reference (FVR)”
rising edge of its clock source. See the Comparator for more information on the Fixed Voltage Reference
Block Diagram (Figure 15-2) and the Timer1 Block module.
Diagram (Figure 7-1) for more information.
See Section 14.0 “Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
15.5 Comparator Interrupt signal.
An interrupt can be generated upon a change in the Any time the comparator is disabled (CxON = 0), all
output value of the comparator for each comparator, a comparator inputs are disabled.
rising edge detector and a Falling edge detector are
present. 15.7 Comparator Negative Input
When either edge detector is triggered and its associ- Selection
ated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt The CxNCH0 bit of the CMxCON0 register selects the
Flag bit (CxIF bit of the PIR2 register) will be set. analog input pin to the comparator inverting input.
To enable the interrupt, you must set the following bits: Note: To use CxIN0+ and CxIN1x- pins as
• CxON, CxPOL and CxSP bits of the CMxCON0 analog input, the appropriate bits must be
register set in the ANSEL register and the
corresponding TRIS bits must also be set
• CxIE bit of the PIE2 register
to disable the output drivers.
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
15.8 Comparator Response Time
• CxINTN bit of the CMxCON1 register (for a falling
edge detection) The comparator output is indeterminate for a period of
• PEIE and GIE bits of the INTCON register time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
The associated interrupt flag bit, CxIF bit of the PIR2
the response time. The response time of the comparator
register, must be cleared in software. If another edge is
differs from the settling time of the voltage reference.
detected while this flag is being cleared, the flag will still
Therefore, both of these times must be considered when
be set at the end of the sequence.
determining the total response time to a comparator
Note: Although a comparator is disabled, an input change. See the Comparator and Voltage Refer-
interrupt can be generated by changing ence Specifications in Section 20.0 “Electrical Specifi-
the output polarity with the CxPOL bit of cations” for more details.
the CMxCON0 register, or by switching
the comparator on or off with the CxON bit 15.9 Interaction with the COG Module
of the CMxCON0 register.
The comparator outputs can be brought to the COG
module in order to facilitate auto-shutdown. If auto-
restart is also enabled, the comparators can be
configured as a closed loop analog feedback to the
COG, thereby creating an analog controlled PWM.

PIC12F752/HV752
15.10 Zero Latency Filter
In high-speed operation, and under proper circuit
conditions, it is possible for the comparator output to
oscillate. This oscillation can have adverse effects on
the hardware and software relying on this signal.
Therefore, a digital filter has been added to the
comparator output to suppress the comparator output
oscillation. Once the comparator output changes, the
output is prevented from reversing the change for a
nominal time of 20 ns. This allows the comparator
output to stabilize without affecting other dependent
devices. Refer to Figure 15-3.
FIGURE 15-3: COMPARATOR ZERO LATENCY FILTER OPERATION
CxOUT From Comparator
CxOUT From ZLF

TZLF
Output waiting for TZLF to expire before an output change is allowed
TZLF has expired so output change of ZLF is immediate based on

comparator output change

PIC12F752/HV752
15.11 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 15-4. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
FIGURE 15-4: ANALOG INPUT MODEL

VDD
Analog
Input
pin VT  0.6V RIC
Rs < 10K
To Comparator
CPIN ILEAKAGE(1)
VA
5 pF VT  0.6V
Vss
Legend: CPIN = Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
VT = Threshold Voltage
Note 1: See Section 20.0 “Electrical Specifications”

PIC12F752/HV752
15.12 Comparator Control Registers
REGISTER 15-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0
CxON CxOUT CxOE CxPOL CxZLF CxSP CxHYS CxSYNC
bit 7 bit 0
Legend:
bit 7 CxON: Comparator Enable bit

1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6 CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5 CxOE: Comparator Output Enable bit
1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually
drive the pin. Not affected by CxON.
0 = CxOUT is internal only
bit 4 CxPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3 CxZLF: Zero Latency Filter Enable bit
1 = Zero latency filter is enabled
0 = Zero latency filter is disabled
bit 2 CxSP: Comparator Speed/Power Select bit
1 = Comparator operates in normal power, higher speed mode
0 = Comparator operates in low-power, low-speed mode
bit 1 CxHYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0 CxSYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous.

PIC12F752/HV752
REGISTER 15-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0
CxINTP CxINTN CxPCH<1:0> — — — CxNCH0
bit 7 bit 0
Legend:
bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bit

1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits
1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits
00 = CxVP connects to CxIN+ pin
01 = CxVP connects to DAC Voltage Reference (dac_ref)
10 = CxVP connects to FVR Voltage Reference (fvr_ref)
11 = CxVP connects to VSS
bit 0 CxNCH0: Comparator Negative Input Channel Select bits
0 = CxVN connects to CXIN0- pin
1 = CxVN connects to CXIN1- pin
REGISTER 15-3: CMOUT: COMPARATOR OUTPUT REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0
— — — — — — MC2OUT MC1OUT
bit 7 bit 0
Legend:

bit 1 MC2OUT: Mirror Copy of C2OUT bit
bit 0 MC1OUT: Mirror Copy of C1OUT bit

PIC12F752/HV752
TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Register
on Page
CMOUT — — — — — — MCOUT2 MCOUT1 114
DACCON0 DACEN DACRNG DACOE — — DACPSS0 — — 105
DACCON1 — — — DACR<4:0> 105
FVRCON FVREN FVRRDY FVR- FVR- — — — —
101
BUFEN BUFSS
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.

PIC12F752/HV752
16.0 INSTRUCTION SET SUMMARY
TABLE 16-1: OPCODE FIELD
The PIC12F752/HV752 instruction set is highly
DESCRIPTIONS
orthogonal and is comprised of three basic categories:
• Byte-oriented operations Field Description
• Bit-oriented operations f Register file address (0x00 to 0x7F)
• Literal and control operations W Working register (accumulator)
Each PIC16 instruction is a 14-bit word divided into an b Bit address within an 8-bit file register
opcode, which specifies the instruction type and one or k Literal field, constant data or label
more operands, which further specify the operation of
x Don’t care location (= 0 or 1).
the instruction. The formats for each of the categories
The assembler will generate code with x = 0.
is presented in Figure 16-1, while the various opcode
It is the recommended form of use for
fields are summarized in Table 16-1.
compatibility with all Microchip software tools.
Table 16-2 lists the instructions recognized by the d Destination select; d = 0: store result in W,
MPASMTM assembler. d = 1: store result in file register f.
For byte-oriented instructions, ‘f’ represents a file Default is d = 1.
register designator and ‘d’ represents a destination PC Program Counter
designator. The file register designator specifies which
TO Time-out bit
file register is to be used by the instruction.
C Carry bit
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is DC Digit carry bit
placed in the W register. If ‘d’ is one, the result is placed Z Zero bit
in the file register specified in the instruction. PD Power-down bit
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the FIGURE 16-1: GENERAL FORMAT FOR
operation, while ‘f’ represents the address of the file in INSTRUCTIONS
which the bit is located.
Byte-oriented file register operations
For literal and control operations, ‘k’ represents an
13 8 7 6 0
8-bit or 11-bit constant, or literal value.
OPCODE d f (FILE #)
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal d = 0 for destination W
d = 1 for destination f
instruction execution time of 1 s. All instructions are f = 7-bit file register address
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
Bit-oriented file register operations
changed as a result of an instruction. When this occurs,
13 10 9 7 6 0
the execution takes two instruction cycles, with the
OPCODE b (BIT #) f (FILE #)
second cycle executed as a NOP.
All instruction examples use the format ‘0xhh’ to b = 3-bit bit address
f = 7-bit file register address
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
Literal and control operations
16.1 Read-Modify-Write Operations General

13 8 7 0
Any instruction that specifies a file register as part of OPCODE k (literal)
the instruction performs a Read-Modify-Write (RMW)
operation. The register is read, the data is modified, k = 8-bit immediate value
and the result is stored according to either the
instruction or the destination designator ‘d’. A read CALL and GOTO instructions only
operation is performed on a register even if the 13 11 10 0
instruction writes to that register.
OPCODE k (literal)
For example, a CLRF PORTA instruction will read
k = 11-bit immediate value
PORTA, clear all the data bits, then write the result back
to PORTA. This example would have the unintended
consequence of clearing the condition that set the
IOCIF flag.

PIC12F752/HV752
TABLE 16-2: PIC12F752/HV752 INSTRUCTION SET

Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP – No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE – Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.

PIC12F752/HV752
16.2 Instruction Descriptions
ADDLW Add literal and W BCF Bit Clear f
Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b

Operands: 0  k  255 Operands: 0  f  127
0b7
Operation: (W) + k  (W)
Operation: 0  (f<b>)
Status Affected: C, DC, Z
Status Affected: None
Description: The contents of the W register
are added to the 8-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared.
and the result is placed in the
W register.
ADDWF Add W and f BSF Bit Set f
Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b

Operands: 0  f  127 Operands: 0  f  127
d 0,1 0b7
Operation: (W) + (f)  (destination) Operation: 1  (f<b>)
Status Affected: C, DC, Z Status Affected: None
Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set.
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSC f,b

0b7
Operation: (W) .AND. (k)  (W)
Operation: skip if (f<b>) = 0
Status Affected: Z
Description: The contents of W register are
AND’ed with the 8-bit literal ‘k’. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
The result is placed in the W instruction is executed.
register. If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is discarded, and a NOP
is executed instead, making this a
2-cycle instruction.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0  f  127
d 0,1
Operation: (W) .AND. (f)  (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.

PIC12F752/HV752
BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer
Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT

Operands: 0  f  127 Operands: None
0b<7 Operation: 00h  WDT
Operation: skip if (f<b>) = 1 0  WDT prescaler,
1  TO
1  PD
Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Status Affected: TO, PD
instruction is executed.
If bit ‘b’ is ‘1’, then the next Description: CLRWDT instruction resets the
instruction is discarded and a NOP Watchdog Timer. It also resets the
is executed instead, making this a prescaler of the WDT.
2-cycle instruction. Status bits TO and PD are set.
CALL Call Subroutine COMF Complement f

Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d
Operation: (PC)+ 1 TOS, d  [0,1]
k  PC<10:0>, Operation: (f)  (destination)
(PCLATH<4:3>)  PC<12:11>
Status Affected: Z
Description: The contents of register ‘f’ are
Description: Call Subroutine. First, return complemented. If ‘d’ is ‘0’, the
address (PC + 1) is pushed onto result is stored in W. If ‘d’ is ‘1’,
the stack. The 11-bit immediate the result is stored back in
address is loaded into PC bits register ‘f’.
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a 2-cycle instruction.
CLRF Clear f DECF Decrement f

Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d
Operation: 00h  (f) d  [0,1]
1Z Operation: (f) - 1  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are Description: Decrement register ‘f’. If ‘d’ is ‘0’,
cleared and the Z bit is set. the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h  (W)
1Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.

PIC12F752/HV752
DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
d  [0,1] d  [0,1]
Operation: (f) - 1  (destination); Operation: (f) + 1  (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is
‘1’, the result is placed back in ‘1’, the result is placed back in
register ‘f’. register ‘f’.
If the result is ‘1’, the next If the result is ‘1’, the next
instruction is executed. If the instruction is executed. If the
result is ‘0’, then a NOP is result is ‘0’, a NOP is executed
executed instead, making it a instead, making it a 2-cycle
2-cycle instruction. instruction.
GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0  k  2047 Operands: 0  k  255
Operation: k  PC<10:0> Operation: (W) .OR. k  (W)
PCLATH<4:3>  PC<12:11> Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. OR’ed with the 8-bit literal ‘k’. The
The 11-bit immediate value is result is placed in the
loaded into PC bits <10:0>. The W register.
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
2-cycle instruction.
INCF Increment f IORWF Inclusive OR W with f

Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d
d  [0,1] d  [0,1]
Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are Description: Inclusive OR the W register with
incremented. If ‘d’ is ‘0’, the result register ‘f’. If ‘d’ is ‘0’, the result is
is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is
‘1’, the result is placed back in ‘1’, the result is placed back in
register ‘f’. register ‘f’.

PIC12F752/HV752
MOVF Move f MOVWF Move W to f

Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f
d  [0,1] Operation: (W)  (f)
Operation: (f)  (dest) Status Affected: None
Status Affected: Z Description: Move data from W register to
Description: The contents of register ‘f’ is register ‘f’.
moved to a destination dependent Words: 1
upon the status of ‘d’. If d = 0,
destination is W register. If d = 1, Cycles: 1
the destination is file register ‘f’ Example: MOVW OPTION
itself. d = 1 is useful to test a file F
register since Status flag Z is Before Instruction
affected. OPTION = 0xFF
Words: 1 W = 0x4F
Cycles: 1 After Instruction
OPTION = 0x4F
Example: MOVF FSR, 0 W = 0x4F
After Instruction
W = value in FSR
register
Z = 1
MOVLW Move literal to W NOP No Operation

Syntax: [ label ] MOVLW k Syntax: [ label ] NOP
Operands: 0  k  255 Operands: None
Operation: k  (W) Operation: No operation
Description: The 8-bit literal ‘k’ is loaded into W Description: No operation
register. The “don’t cares” will Words: 1
assemble as ‘0’s.
Cycles: 1
Words: 1
Example: NOP
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W = 0x5A

PIC12F752/HV752
RETFIE Return from Interrupt RETLW Return with literal in W

Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k
Operands: None Operands: 0  k  255
Operation: TOS  PC, Operation: k  (W);
1  GIE TOS  PC
Description: Return from Interrupt. Stack is Description: The W register is loaded with the
POPed and Top-of-Stack (TOS) is 8-bit literal ‘k’. The program
loaded in the PC. Interrupts are counter is loaded from the top of
enabled by setting Global the stack (the return address).
Interrupt Enable bit, GIE This is a 2-cycle instruction.
(INTCON<7>). This is a 2-cycle Words: 1
instruction.
Cycles: 2
Words: 1
Example: CALL TABLE;W contains
Cycles: 2 ;table offset
Example: RETFIE ;value
After Interrupt GOTO DONE
PC = TOS TABLE •
GIE = 1 •
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ;End of table
DONE
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine

Syntax: [ label ] RETURN
Operands: None
Operation: TOS  PC
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a 2-cycle instruc-
tion.

PIC12F752/HV752
RLF Rotate Left f through Carry SLEEP Enter Sleep mode

Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP
Operands: 0  f  127 Operands: None
d  [0,1] Operation: 00h  WDT,
Operation: See description below 0  WDT prescaler,
Status Affected: C 1  TO,
0  PD
Description: The contents of register ‘f’ are
rotated one bit to the left through Status Affected: TO, PD
the Carry flag. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is
result is placed in the W register. cleared. Time-out Status bit, TO
If ‘d’ is ‘1’, the result is stored is set. Watchdog Timer and its
back in register ‘f’. prescaler are cleared.
C Register f The processor is put into Sleep
mode with the oscillator stopped.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110 0110
C = 0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C = 1
RRF Rotate Right f through Carry SUBLW Subtract W from literal
Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k

Operands: 0  f  127 Operands: 0 k 255
d  [0,1] Operation: k - (W) W)
Operation: See description below Status Affected: C, DC, Z
Status Affected: C Description: The W register is subtracted (2’s
Description: The contents of register ‘f’ are complement method) from the 8-bit
rotated one bit to the right through literal ‘k’. The result is placed in the
the Carry flag. If ‘d’ is ‘0’, the W register.
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed Result Condition
back in register ‘f’. C=0 Wk
C Register f C=1 Wk
DC = 0 W<3:0>  k<3:0>
DC = 1 W<3:0>  k<3:0>

PIC12F752/HV752
SUBWF Subtract W from f XORWF Exclusive OR W with f

Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORWF f,d
Operands: 0 f 127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f) - (W) destination) Operation: (W) .XOR. (f) destination)
Status Affected: C, DC, Z Status Affected: Z
Description: Subtract (2’s complement method) Description: Exclusive OR the contents of the
W register from register ‘f’. If ‘d’ is W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’. stored back in register ‘f’.
C=0 Wf
C=1 Wf
DC = 0 W<3:0>  f<3:0>
DC = 1 W<3:0>  f<3:0>
SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d
Operands: 0  f  127
d  [0,1]
Operation: (f<3:0>)  (destination<7:4>),
(f<7:4>)  (destination<3:0>)
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
XORLW Exclusive OR literal with W

Syntax: [ label ] XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register
are XOR’ed with the 8-bit
literal ‘k’. The result is placed in
the W register.

PIC12F752/HV752
17.0 SPECIAL FEATURES OF THE 17.1 Configuration Bits
CPU The Configuration bits can be programmed (read as
The PIC12F752/HV752 has a host of features intended ‘0’) or left unprogrammed (read as ‘1’) to select various
to maximize system reliability, minimize cost through device configurations as shown in Register 17-1.
elimination of external components, provide These bits are mapped in program memory location
power-saving features and offer code protection. 2007h.
These features are: Note: Address 2007h is beyond the user program
memory space. It belongs to the special
• Reset:
configuration memory space
- Power-on Reset (POR) (2000h-3FFFh), which can be accessed
- Power-up Timer (PWRT) only during programming. See
- Brown-out Reset (BOR) “PIC12F752/HV752 Flash Memory
• Interrupts Programming Specification” (DS41561)
for more information.
• Watchdog Timer (WDT)
• Oscillator selection
• Sleep
• Code protection
• ID Locations
• In-Circuit Serial Programming
The Power-up Timer (PWRT), which provides a fixed
delay of 64 ms (nominal) on power-up only, is designed
to keep the part in Reset while the power supply
stabilizes. There is also circuitry to reset the device if a
brown-out occurs, which can use the Power-up Timer
to provide at least a 64 ms Reset. With these
functions-on-chip, most applications need no external
Reset circuitry.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through:
• External Reset
• Watchdog Timer Wake-up
• An interrupt
Oscillator selection options are available to allow the
part to fit the application. The INTOSC options save
system cost, while the External Clock (EC) option
provides a means for specific frequency and accurate
clock sources. Configuration bits are used to select
various options (see Register 17-1).

PIC12F752/HV752
REGISTER 17-1: CONFIGURATION WORD

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
DEBUG CLKOUTEN WRT<1:0> BOREN<1:0>
bit 13 bit 8
U-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 U-1 R/P-1

— CP MCLRE PWRTE WDTE — — FOSC0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 13 DEBUG: Debug Mode Enable bit(2)

1 = Background debugger is disabled
0 = Background debugger is enabled
bit 12 CLKOUTEN: Clock Out Enable bit
1 = Clock out function disabled. CLKOUT pin acts as I/O pin
0 = General purpose I/O disabled. CLKOUT pin acts as CLKOUT
bit 11-10 WRT<1:0>: Flash Program Memory Self Write Enable bit
11 = Write protection off
10 = 000h to FFh write-protected, 100h to 3FFh may be modified by PMCON1 control
01 = 000h to 1FFh write-protected, 200h to 3FFh may be modified by PMCON1 control
00 = 000h to 3FFh write-protected, entire program is write-protected
bit 8-9 BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
0x = BOR disabled
bit 7 Unimplemented: Read as ‘1’.
bit 6 CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 5 MCLRE: MCLR/VPP Pin Function Select bit
1 = MCLR pin is MCLR function and weak internal pull-up is enabled
0 = MCLR pin is input function, MCLR function is internally disabled
bit 4 PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-1 Unimplemented: Read as ‘1’.
bit 0 FOSC: Oscillator Selection bits
1 = EC oscillator selected: CLKIN on RA5/CLKIN
0 = Internal oscillator: I/O function on RA5/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The Configuration bit is managed automatically by the device development tools. The user should not
attempt to manually write this bit location. However, the user should ensure that this location has been
programmed to a ‘1’ and the device checksum is correct for proper operation of production software.

PIC12F752/HV752
17.2 Calibration Bits Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
The 8 MHz internal oscillator is factory calibrated. other Reset. Most other registers are reset to a “Reset
These calibration values are stored in fuses located in state” on:
the Calibration Word (2008h). The Calibration Word is
not erased when using the specified bulk erase • Power-on Reset
sequence in the “PIC12F752/HV752 Flash Memory • MCLR Reset
Programming Specification” (DS41561) and thus, does • MCLR Reset during Sleep
not require reprogramming. • WDT Reset
• Brown-out Reset (BOR)
17.3 Reset
WDT wake-up does not cause register resets in the
The PIC12F752/HV752 device differentiates between same manner as a WDT Reset since wake-up is
various kinds of Reset: viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
a) Power-on Reset (POR)
situations, as indicated in Table 17-2. Software can use
b) WDT Reset during normal operation these bits to determine the nature of the Reset. See
c) WDT Reset during Sleep Table 17-4 for a full description of Reset states of all
d) MCLR Reset during normal operation registers.
e) MCLR Reset during Sleep A simplified block diagram of the On-Chip Reset Circuit
f) Brown-out Reset (BOR) is shown in Figure 17-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 20.0 “Electrical
Specifications” for pulse-width specifications.
FIGURE 17-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP pin
Sleep
WDT WDT
Module Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out(1)
Reset
BOREN
S
PWRT Chip_Reset
On-Chip 11-bit Ripple Counter R Q
RC OSC
Enable PWRT
Note 1: Refer to the Configuration Word register (Register 17-1).

PIC12F752/HV752
TABLE 17-1: TIME-OUT IN VARIOUS SITUATIONS
Power-up Brown-out Reset Wake-up from
Oscillator Configuration
PWRTE = 0 PWRTE = 1 PWRTE = 0 PWRTE = 1 Sleep
EC, INTOSC TPWRT — TPWRT — —
TABLE 17-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE

POR BOR TO PD Condition
0 x 1 1 Power-on Reset
u 0 1 1 Brown-out Reset
u u 0 u WDT Reset
u u 0 0 WDT Wake-up
u u u u MCLR Reset during normal operation
u u 1 0 MCLR Reset during Sleep
Legend: u = unchanged, x = unknown

PIC12F752/HV752
17.3.1 POWER-ON RESET (POR) FIGURE 17-2: RECOMMENDED MCLR
The on-chip POR circuit holds the chip in Reset until CIRCUIT
VDD has reached a high enough level for proper
VDD
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This
PIC®
will eliminate external RC components usually needed R1 MCU
to create Power-on Reset. A maximum rise time for 1 kor greater)
VDD is required. See Section 20.0 “Electrical
Specifications” for details. If the BOR is enabled, the R2
maximum rise time specification does not apply. The MCLR
100 
BOR circuitry will keep the device in Reset until VDD needed with capacitor)
SW1
reaches VBOR (see Section 17.3.4 “Brown-out Reset (optional)
(BOR)”).
C1
0.1 F
Note: The POR circuit does not produce an
(optional, not critical)
internal Reset when VDD declines. To
re-enable the POR, VDD must reach Vss
for a minimum of 100 s.
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e., 17.3.3 POWER-UP TIMER (PWRT)
voltage, frequency, temperature, etc.) must be met to
The Power-up Timer provides a fixed 64 ms (nominal)
ensure proper operation. If these conditions are not
time-out on power-up only, from POR or Brown-out
met, the device must be held in Reset until the
Reset. The Power-up Timer operates from an internal
operating conditions are met.
RC oscillator. For more information, see Section 4.2.2
For additional information, refer to Application Note “Internal Clock Mode”. The chip is kept in Reset as
AN607, “Power-up Trouble Shooting” (DS00000607). long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
17.3.2 MCLR PWRTE, can disable (if set) or enable (if cleared or
PIC12F752/HV752 has a noise filter in the MCLR programmed) the Power-up Timer. The Power-up
Reset path. The filter will detect and ignore small Timer should be enabled when Brown-out Reset is
pulses. enabled, although it is not required.
It should be noted that a WDT Reset does not drive The Power-up Timer delay will vary from chip-to-chip
MCLR pin low. due to:
Voltages applied to the MCLR pin that exceed its • VDD variation
specification can result in both MCLR Resets and • Temperature variation
excessive current beyond the device specification • Process variation
during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied See DC parameters for details (Section 20.0
directly to VDD. The use of an RC network, as shown in “Electrical Specifications”).
Figure 17-2, is suggested. Note: Voltage spikes below VSS at the MCLR
An internal MCLR option is enabled by clearing the pin, inducing currents greater than 80 mA,
MCLRE bit in the Configuration Word register. When may cause latch-up. Thus, a series
MCLRE = 0, the Reset signal to the chip is generated resistor of 50-100  should be used when
internally. When the MCLRE = 1, the MCLR pin applying a “low” level to the MCLR pin,
becomes an external Reset input. In this mode, the rather than pulling this pin directly to VSS.
MCLR pin has a weak pull-up to VDD.

PIC12F752/HV752
17.3.4 BROWN-OUT RESET (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog
timer, etc.), the chip will remain in Reset until VDD rises
The BOREN<1:0> bits in the Configuration Word
above VBOR (see Figure 17-3). If enabled, the
register select one of three BOR modes. One mode
Power-up Timer will be invoked by the Reset and keep
has been added to allow control of the BOR enable for
the chip in Reset an additional 64 ms.
lower current during Sleep. By selecting BOREN<1:0>
= 10, the BOR is automatically disabled in Sleep to Note: The Power-up Timer is enabled by the
conserve power and enabled on wake-up. See PWRTE bit in the Configuration Word
Register 17-1 for the Configuration Word definition. register.
A brown-out occurs when VDD falls below VBOR for If VDD drops below VBOR while the Power-up Timer is
greater than parameter TBOR (see Section 20.0 running, the chip will go back into a Brown-out Reset
“Electrical Specifications”). The brown-out condition and the Power-up Timer will be re-initialized. Once VDD
will reset the device. This will occur regardless of VDD rises above VBOR, the Power-up Timer will execute a
slew rate. A Brown-out Reset may not occur if VDD falls 64 ms Reset.
below VBOR for less than parameter TBOR.
Table 17-3 summarizes the registers associated with
BOR.
FIGURE 17-3: BROWN-OUT SITUATIONS

VDD
Vbor
Internal
Reset 64 ms(1)
VDD
Vbor
Internal < 64 ms
Reset 64 ms(1)
Vdd
Vbor
Internal
Reset 64 ms(1)
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET

Register on
Page
PCON — — — — — — POR BOR 20
STATUS IRP RP1 RP0 TO PD Z DC C 13
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition.
Shaded cells are not used by BOR.

PIC12F752/HV752
17.3.5 TIME-OUT SEQUENCE 17.3.6 POWER CONTROL (PCON)
On power-up, the time-out sequence is as follows: REGISTER
• PWRT time-out is invoked after POR has expired The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset occurred
• OST is activated after the PWRT time-out has
last.
expired
Bit 0 is BOR (Brown-out). BOR is unknown on
The total time-out will vary based on oscillator
Power-on Reset. It must then be set by the user and
configuration and PWRTE bit status. For example, in EC
checked on subsequent Resets to see if BOR = 0,
mode with PWRTE bit erased (PWRT disabled), there
indicating that a Brown-out has occurred. The BOR
will be no time-out at all. Figure 17-4, Figure 17-5 and
Status bit is a “don’t care” and is not necessarily
Figure 17-6 depict time-out sequences.
predictable if the brown-out circuit is disabled
Since the time-outs occur from the POR pulse, if MCLR (BOREN<1:0> = 00 in the Configuration Word
is kept low long enough, the time-outs will expire. Then, register).
bringing MCLR high will begin execution immediately
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
(see Figure 17-5). This is useful for testing purposes or
Reset and unaffected otherwise. The user must write a
to synchronize more than one PIC12F752/HV752
‘1’ to this bit following a Power-on Reset. On a
device operating in parallel.
subsequent Reset, if POR is ‘0’, it will indicate that a
Table 17-5 shows the Reset conditions for some Power-on Reset has occurred (i.e., VDD may have
special registers, while Table 17-4 shows the Reset gone too low).
conditions for all the registers.
For more information, see Section 17.3.4 “Brown-out
Reset (BOR)”.
FIGURE 17-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TIOSCST
OST Time-out
Internal Reset

PIC12F752/HV752
FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TIOSCST
OST Time-out
Internal Reset
FIGURE 17-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TIOSCST
OST Time-out
Internal Reset

PIC12F752/HV752
TABLE 17-4: INITIALIZATION CONDITION FOR REGISTERS
Wake-up from Sleep through
MCLR Reset
Interrupt
Register Address Power-on Reset WDT Reset
Brown-out Reset(1)
WDT Time-out
W — xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h/ xxxx xxxx xxxx xxxx uuuu uuuu
100h/180h
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h/ 0000 0000 0000 0000 PC + 1(3)
102h/182h
STATUS 03h/83h/ 0001 1xxx 000q quuu(4) uuuq quuu(4)
103h/183h
FSR 04h/84h/ xxxx xxxx uuuu uuuu uuuu uuuu
104h/184h
PORTA 05h --xx xxxx --uu uuuu --uu uuuu
IOCAF 08h --00 0000 --00 0000 --uu uuuu
PCLATH 0Ah/8Ah/ ---0 0000 ---0 0000 ---u uuuu
10Ah/18Ah
INTCON 0Bh/8Bh/ 0000 0000 0000 0000 uuuu uuuu(2)
10Bh/18Bh
PIR1 0Ch 00-- -0-0 00-- -0-0 uu-- -u-u(2)
PIR2 0Dh --00 -0-0 --00 -0-0 --uu -u-u(2)
TMR1L 0Fh xxxx xxxx uuuu uuuu uuuu uuuu
TMR1H 10h xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 11h 0000 00-0 uuuu uu-u uuuu uu-u
T1GCON 12h 0000 0x00 0000 0x00 uuuu uuuu
(1)
CCPR1L 13h xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1H(1) 14h xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON(1) 15h --00 0000 --00 0000 --uu uuuu
ADRESL(1) 1Ch xxxx xxxx uuuu uuuu uuuu uuuu
ADRESH(1) 1Dh xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0(1) 1Eh 0000 0000 0000 0000 uuuu uuuu
ADCON1(1) 1Fh -000 ---- -000 ---- -uuu ----
OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h --11 1111 --11 1111 --uu uuuu
IOCAP 88h --00 0000 --00 0000 --uu uuuu
PIE1 8Ch 00-- -000 00-- -000 uu-- -uuu
PIE2 8Dh --00 -0-0 --00 -0-0 --uu -u-u
OSCCON 8Fh --01 -00- --uu -uu- --uu -uu-
FVRCON 90h 0000 ---- 0000 ---- uuuu ----
DACCON0 91h 000- -0-- 000- -0-- uuu- -u--
DACCON1 92h ---0 0000 ---0 0000 ---u uuuu
CM2CON0 9Bh 0000 0100 0000 0100 uuuu uuuu
CM2CON1 9Ch 0000 ---0 0000 ---0 uuuu ---u
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIRx will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 17-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

PIC12F752/HV752
TABLE 17-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
MCLR Reset
Interrupt
Register Address Power-on Reset WDT Reset (Continued)
Brown-out Reset(1)
WDT Time-out
CM1CON0 9Dh 0000 0100 0000 0100 uuuu uuuu
CM1CON1 9Eh 0000 ---0 0000 ---0 uuuu ---u
CMOUT 9Fh ---- --00 ---- --00 ---- --uu
LATA 105h --xx -xxx --uu -uuu --uu -uuu
IOCAN 108h --00 0000 --00 0000 --uu uuuu
WPUA 10Ch --00 0000 --00 0000 --uu uuuu
SLRCON0 10Dh ---- -0-0 ---- -0-0 ---- -u-u
(1, 5)
PCON 10Fh ---- --qq ---- --uu ---- --uu
TMR2 110h 0000 0000 0000 0000 uuuu uuuu
PR2 111h 1111 1111 1111 1111 uuuu uuuu
T2CON 112h -000 0000 -000 0000 -uuu uuuu
HLTMR1 113h 0000 0000 0000 0000 uuuu uuuu
HLTPR1 114h 1111 1111 1111 1111 uuuu uuuu
HLT1CON0 115h -000 0000 -000 0000 -uuu uuuu
HLT1CON1 116h ---0 0000 ---0 0000 ---u uuuu
ANSELA 185h --11 -111 --11 -111 --uu -uuu
APFCON 188h ---0 -000 ---0 -000 ---u -uuu
OSCTUNE 189h ---0 0000 ---u uuuu ---u uuuu
PMCON1 18Ch ---- -000 ---- -000 ---- -uuu
PMCON2 18Dh ---- ---- ---- ---- ---- ----
PMADRL 18Eh 0000 0000 0000 0000 uuuu uuuu
PMADRH 18Fh ---- --00 ---- --00 ---- --uu
PMDATL 190h 0000 0000 0000 0000 uuuu uuuu
PMDATH 191h --00 0000 --00 0000 --uu uuuu
COG1PH 192h ---- xxxx ---- uuuu ---- uuuu
COG1BLK 193h xxxx xxxx uuuu uuuu uuuu uuuu
COG1DB 194h xxxx xxxx uuuu uuuu uuuu uuuu
COG1CON0 195h 0000 0000 0000 0000 uuuu uuuu
COG1CON1 196h --00 0000 --00 0000 --uu uuuu
COG1ASD 197h 0000 0000 0000 0000 uuuu uuuu
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIRx will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 17-5 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

PIC12F752/HV752
TABLE 17-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program Status PCON
Condition
Counter Register Register
Power-on Reset 000h 0001 1xxx ---- --0x
MCLR Reset during normal operation 000h 000u uuuu ---- --uu
MCLR Reset during Sleep 000h 0001 0uuu ---- --uu
WDT Reset 000h 0000 uuuu ---- --uu
WDT Wake-up PC + 1 uuu0 0uuu ---- --uu
Brown-out Reset 000h 0001 1uuu ---- --u0
Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu
Legend: u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with
the interrupt vector (0004h) after execution of PC + 1.

PIC12F752/HV752
17.4 Interrupts Figure 17-8). The latency is the same for one or
two-cycle instructions. Once in the Interrupt Service
The PIC12F752/HV752 has multiple sources of inter- Routine, the source(s) of the interrupt can be
rupt: determined by polling the interrupt flag bits. The
• External Interrupt (INT pin) interrupt flag bit(s) must be cleared in software before
• Interrupt-On-Change (IOC) Interrupts re-enabling interrupts to avoid multiple interrupt
requests.
• Timer0 Overflow Interrupt
• Timer1 Overflow Interrupt Note 1: Individual interrupt flag bits are set,
• Timer2 Match Interrupt regardless of the status of their
corresponding mask bit or the GIE bit.
• Hardware Limit Timer (HLT) Interrupt
• Comparator Interrupt (C1/C2) 2: When an instruction that clears the GIE
bit is executed, any interrupts that were
• ADC Interrupt
pending for execution in the next cycle
• Complementary Output Generator (COG) are ignored. The interrupts, which were
• CCP1 Interrupt ignored, are still pending to be serviced
• Flash Memory Self Write when the GIE bit is set again.
The Interrupt Control register (INTCON) and Peripheral For additional information on Timer1, Timer2,
Interrupt Request Registers (PIRx) record individual comparators, ADC, Enhanced CCP modules, refer to
interrupt requests in flag bits. The INTCON register the respective peripheral section.
also has individual and global interrupt enable bits.
The Global Interrupt Enable bit, GIE of the INTCON 17.4.1 RA2/INT INTERRUPT
register, enables (if set) all unmasked interrupts, or The external interrupt on the RA2/INT pin is
disables (if cleared) all interrupts. Individual interrupts edge-triggered; either on the rising edge if the INTEDG
can be disabled through their corresponding enable bit of the OPTION register is set, or the falling edge, if
bits in the INTCON register and PIEx registers. GIE is the INTEDG bit is clear. When a valid edge appears on
cleared on Reset. the RA2/INT pin, the INTF bit of the INTCON register is
When an interrupt is serviced, the following actions set. This interrupt can be disabled by clearing the INTE
occur automatically: control bit of the INTCON register. The INTF bit must
be cleared by software in the Interrupt Service Routine
• The GIE is cleared to disable any further interrupt before re-enabling this interrupt. The RA2/INT interrupt
• The return address is pushed onto the stack can wake-up the processor from Sleep, if the INTE bit
• The PC is loaded with 0004h was set prior to going into Sleep. See Section 17.7
The Return from Interrupt instruction, RETFIE, exits “Power-down Mode (Sleep)” for details on Sleep and
the interrupt routine, as well as sets the GIE bit, which Figure 17-10 for timing of wake-up from Sleep through
re-enables unmasked interrupts. RA2/INT interrupt.
The following interrupt flags are contained in the Note: The ANSEL register must be initialized to
INTCON register: configure an analog channel as a digital
input. Pins configured as analog inputs
• INT Pin Interrupt
will read ‘0’ and cannot generate an
• Interrupt-On-Change (IOC) Interrupts interrupt.
The peripheral interrupt flags are contained in the PIR1 17.4.2 TIMER0 INTERRUPT
and PIR2 registers. The corresponding interrupt enable An overflow (FFh  00h) in the TMR0 register will set
bit is contained in the PIE1 and PIE2 registers. the T0IF bit of the INTCON register. The interrupt can
The following interrupt flags are contained in the PIR1 be enabled/disabled by setting/clearing T0IE bit of the
register: INTCON register. See Section 6.0 “Timer0 Module”
for operation of the Timer0 module.
• A/D Interrupt
• Comparator Interrupt
• Timer2 Match Interrupt
• Enhanced CCP Interrupt
For external interrupt events, such as the INT pin or
PORTA change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see

PIC12F752/HV752
17.4.3 PORTA INTERRUPT-ON-CHANGE
An input change on PORTA sets the IOCIF bit of the
INTCON register. The interrupt can be enabled/
disabled by setting/clearing the IOCIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
Note: If a change on the I/O pin should occur
when any PORTA operation is being
executed, then the IOCIF interrupt flag
may not get set.
FIGURE 17-7: INTERRUPT LOGIC
T0IF Wake-up
T0IE (If in Sleep mode)
INTF
Peripheral Interrupts INTE
(TMR1IF) PIR1<0>
IOCIF Interrupt
(TMR1IF) PIR1<0> IOCIE to CPU
PEIE
PIRn<7>
PIEn<7> GIE

PIC12F752/HV752
FIGURE 17-8: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag (5) Interrupt Latency (2)
(INTCON reg.)
GIE bit
(INTCON reg.)
INSTRUCTION FLOW
PC PC PC + 1 PC + 1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h)
Instruction Dummy Cycle Dummy Cycle Inst (0004h)

Executed Inst (PC – 1) Inst (PC)
Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 20.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 17-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Register
on Page
IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 45
IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 45
IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 45
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the Interrupt module.

PIC12F752/HV752
17.5 Context Saving during Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Temporary holding registers W_TEMP and
STATUS_TEMP should be placed in the last 16 bytes
of GPR (see Figure 2-1). These 16 locations are
common to all banks and do not require banking. This
makes context save and restore operations simpler.
The code shown in Example 17-1 can be used to:
• Store the W register
• Store the STATUS register
• Execute the ISR code
• Restore the Status (and Bank Select Bit register)
• Restore the W register.
Note: The PIC12F752/HV752 does not require
saving the PCLATH. However, if com-
puted GOTOs are used in both the ISR and
the main code, the PCLATH must be
saved and restored in the ISR.
EXAMPLE 17-1: SAVING STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register
SWAPF STATUS,W ;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR) ;Insert user code here
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W

PIC12F752/HV752
17.6 Watchdog Timer (WDT) 17.6.1 WDT PERIOD
The Watchdog Timer is a free running timer, using The WDT has a nominal time-out period of 18 ms (with
LFINTOSC oscillator as its clock source. The WDT is no prescaler). The time-out periods vary with
enabled by setting the WDTE bit of the Configuration temperature, VDD and process variations from part to
Word (default setting). When WDTE is set, the part (see DC specs). If longer time-out periods are
LFINTOSC will always be enabled to provide a clock desired, a prescaler with a division ratio of up to 1:128
source to the WDT module. can be assigned to the WDT under software control by
writing to the OPTION register. Thus, time-out periods
During normal operation, a WDT time-out generates a
up to 2.3 seconds can be realized.
device Reset. If the device is in Sleep mode, a WDT
time-out causes the device to wake-up and continue The CLRWDT and SLEEP instructions clear the WDT
with normal operation. and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The WDT can be permanently disabled by
programming the Configuration bit, WDTE, as clear The TO bit in the STATUS register will be cleared upon
(Section 17.1 “Configuration Bits”). a Watchdog Timer time-out.
17.6.2 WDT PROGRAMMING

CONSIDERATIONS
It should also be taken in account that under worst-
case conditions (i.e., VDD = Min., Temperature = Max.,
Max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
FIGURE 17-9: WATCHDOG TIMER WITH SHARED PRESCALE BLOCK DIAGRAM
FOSC/4
Data Bus
0
8
1
Sync
1
2 TCY TMR0
Shared Prescale
T0CKI 0
pin 0
T0SE T0CS PSA Set Flag bit T0IF
8-bit
on Overflow
Prescaler
1
PSA
8
PS<2:0> 1
Watchdog
WDT
Timer
Time-out
LFINTOSC
2 0
(Figure 4-1)
PSA
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG register.
2: WDTE bit is in the Configuration Word register.

PIC12F752/HV752
TABLE 17-7: WDT STATUS
Conditions WDT
WDTE = 0
CLRWDT Command Cleared
Exit Sleep
TABLE 17-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Register on
Page
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 17-1 for operation of all Configuration Word register bits.
TABLE 17-9: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register
on Page
CONFIG 126
Legend: — = unimplemented location, read as ‘1’. Shaded cells are not used by Watchdog Timer.

PIC12F752/HV752
17.7 Power-down Mode (Sleep) When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
The Power-Down mode is entered by executing a wake-up through an interrupt event, the corresponding
SLEEP instruction. interrupt enable bit must be set (enabled). Wake-up is
If the Watchdog Timer is enabled: regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
• WDT will be cleared but keeps running
instruction after the SLEEP instruction. If the GIE bit is
• PD bit in the STATUS register is cleared set (enabled), the device executes the instruction after
• TO bit is set the SLEEP instruction, then branches to the interrupt
• Oscillator driver is turned off address (0004h). In cases where the execution of the
• I/O ports maintain the status they had before SLEEP instruction following SLEEP is not desirable, the user
was executed (driving high, low or high-impedance) should have a NOP after the SLEEP instruction.
For lowest current consumption in this mode, all I/O pins Note: If the global interrupts are disabled (GIE is
should be either at VDD or VSS, with no external circuitry cleared) and any interrupt source has both
drawing current from the I/O pin and the comparators, its interrupt enable bit and the
DAC and FVR should be disabled. I/O pins that are high- corresponding interrupt flag bits set, the
impedance inputs should be pulled high or low externally device will immediately wake-up from
to avoid switching currents caused by floating inputs. Sleep.
The T0CKI input should also be at VDD or VSS for lowest
The WDT is cleared when the device wakes up from
current consumption. The contribution from on-chip pull-
Sleep, regardless of the source of wake-up.
ups on PORTA should be considered.
The MCLR pin must be at a logic high level. 17.7.2 WAKE-UP USING INTERRUPTS
Note: It should be noted that a Reset generated When global interrupts are disabled (GIE cleared) and
by a WDT time-out does not drive MCLR any interrupt source has both its interrupt enable bit
pin low. and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
17.7.1 WAKE-UP FROM SLEEP SLEEP instruction, the SLEEP instruction will
The device can wake-up from Sleep through one of the complete as a NOP. Therefore, the WDT and WDT
following events: prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
1. External Reset input on MCLR pin
will not be cleared.
2. Watchdog Timer wake-up
• If the interrupt occurs during or after the
3. Interrupt from INT pin execution of a SLEEP instruction, the device will
4. Interrupt-On-Change input change Immediately wake-up from Sleep. The SLEEP
5. Peripheral interrupt instruction is executed. Therefore, the WDT and
WDT prescaler and postscaler (if enabled) will be
The first event will cause a device Reset. The other
cleared, the TO bit will be set and the PD bit will
events are considered a continuation of program
be cleared.
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device Reset. Even if the flag bits were checked before executing a
The PD bit, which is set on power-up, is cleared when SLEEP instruction, it may be possible for flag bits to
Sleep is invoked. TO bit is cleared if WDT wake-up become set before the SLEEP instruction completes. To
occurred. determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
The following peripheral interrupts can wake the device
was executed as a NOP.
from Sleep:
To ensure that the WDT is cleared, a CLRWDT instruction
1. Timer1 interrupt. Timer1 must be operating as
should be executed before a SLEEP instruction. See
an asynchronous counter
Figure 17-10 for more details.
2. CCP Capture mode interrupt
3. A/D conversion (when A/D clock source is RC)
4. Comparator output changes state
5. Interrupt-on-change
6. External Interrupt from INT pin
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.

PIC12F752/HV752
FIGURE 17-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN
CLKOUT TIOSCST
INT pin
INTF flag
(INTCON reg.) Interrupt Latency
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Dummy Cycle Dummy Cycle
Executed Inst(PC – 1) Inst(0004h)
Note 1: HFINTOSC Oscillator mode assumed.

2: GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line.
17.8 Code Protection

If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification purposes.
Note: The entire Flash program memory will be
erased when the code protection is turned
off. See the “PIC12F752/HV752 Flash
Memory Programming Specification”
(DS41561) for more information.
17.9 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant seven bits of the ID locations
are reported when using MPLAB® IDE.

PIC12F752/HV752
17.10 In-Circuit Serial Programming™
ThePIC12F752/HV752 microcontrollers can be serially Note: To erase the device, VDD must be above
programmed while in the end application circuit. This is the Bulk Erase VDD minimum given in the
simply done with five connections for: “PIC12F752/HV752 Flash Memory
Programming Specification” (DS41561)
• Clock
• Data
• Power
• Ground
• Programming Voltage
This allows customers to manufacture boards with
unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
The device is placed into a Program/Verify mode by
holding the ICSPDAT and ICSPCLK pins low, while
raising the MCLR (VPP) pin from VIL to VIHH. See the
“PIC12F752/HV752 Flash Memory Programming
Specification” (DS41561) for more information.
ICSPDAT becomes the programming data and
ICSPCLK becomes the programming clock. Both
ICSPDAT and ICSPCLK are Schmitt Trigger inputs in
Program/Verify mode.
A typical In-Circuit Serial Programming connection is
shown in Figure 17-11.
FIGURE 17-11: TYPICAL IN-CIRCUIT

SERIAL
PROGRAMMING™
CONNECTION
To Normal
Connections
External
Connector * PIC12F752/HV752
Signals
+5V VDD
0V VSS
VPP MCLR/VPP
CLK ICSPCLK
Data I/O ICSPDAT
* * *
To Normal
Connections
* Isolation devices (as required)

PIC12F752/HV752
18.0 SHUNT REGULATOR An external current limiting resistor, RSER, located
between the unregulated supply, VUNREG, and the VDD
(PIC12HV752 ONLY) pin, drops the difference in voltage between VUNREG
The PIC12HV752 devices include a permanent internal and VDD. RSER must be between RMAX and RMIN as
5 volt (nominal) shunt regulator in parallel with the VDD defined by Equation 18-1.
pin. This eliminates the need for an external voltage
regulator in systems sourced by an unregulated supply. EQUATION 18-1: RSER LIMITING RESISTOR
All external devices connected directly to the VDD pin
will share the regulated supply voltage and contribute (VUMIN - 5V)
to the total VDD supply current (ILOAD). RMAX =
1.05 • (1 MA + ILOAD)
18.1 Regulator Operation

(VUMAX - 5V)
A shunt regulator generates a specific supply voltage RMIN =
0.95 • (50 MA)
by creating a voltage drop across a pass resistor RSER.
The voltage at the VDD pin of the microcontroller is
monitored and compared to an internal voltage Where:
reference. The current through the resistor is then RMAX = maximum value of RSER (ohms)
adjusted, based on the result of the comparison, to
RMIN = minimum value of RSER (ohms)
produce a voltage drop equal to the difference between
the supply voltage VUNREG and the VDD of the VUMIN = minimum value of VUNREG
microcontroller. See Figure 18-1 for voltage regulator VUMAX = maximum value of VUNREG
schematic.
VDD = regulated voltage (5V nominal)
FIGURE 18-1: SHUNT REGULATOR ILOAD = maximum expected load current in mA
including I/O pin currents and external
VUNREG circuits connected to VDD.
1.05 = compensation for +5% tolerance of RSER
ILOAD
ISUPPLY RSER 0.95 = compensation for -5% tolerance of RSER
VDD
CBYPASS
ISHUNT
Feedback
18.2 Regulator Considerations
The supply voltage VUNREG and load current are not
VSS constant. Therefore, the current range of the regulator
is limited. Selecting a value for RSER must take these
Device
three factors into consideration.
Since the regulator uses the band gap voltage as the
regulated voltage reference, this voltage reference is
permanently enabled in the PIC12HV752 devices.
The shunt regulator will still consume current when
below operating voltage range for the shunt regulator.
18.3 Design Considerations

For more information on using the shunt regulator and
managing current load, see Application Note AN1035,
“Designing with HV Microcontrollers” (DS01035).

PIC12F752/HV752
19.0 DEVELOPMENT SUPPORT 19.1 MPLAB X Integrated Development
Environment Software
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment: hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers: software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators: that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators:
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers: users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers:
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

PIC12F752/HV752
19.2 MPLAB XC Compilers 19.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
• Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
19.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
19.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:
The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

PIC12F752/HV752
19.6 MPLAB X SIM Software Simulator 19.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by The MPLAB ICD 3 In-Circuit Debugger System is
simulating the PIC MCUs and dsPIC DSCs on an Microchip’s most cost-effective, high-speed hardware
instruction level. On any given instruction, the data debugger/programmer for Microchip Flash DSC and
areas can be examined or modified and stimuli can be MCU devices. It debugs and programs PIC Flash
applied from a comprehensive stimulus controller. microcontrollers and dsPIC DSCs with the powerful,
Registers can be logged to files for further run-time yet easy-to-use graphical user interface of the MPLAB
analysis. The trace buffer and logic analyzer display IDE.
extend the power of the simulator to record and track
The MPLAB ICD 3 In-Circuit Debugger probe is
program execution, actions on I/O, most peripherals
connected to the design engineer’s PC using a
and internal registers.
high-speed USB 2.0 interface and is connected to the
The MPLAB X SIM Software Simulator fully supports target with a connector compatible with the MPLAB
symbolic debugging using the MPLAB XC Compilers, ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB
and the MPASM and MPLAB Assemblers. The ICD 3 supports all MPLAB ICD 2 headers.
software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory 19.9 PICkit 3 In-Circuit Debugger/
environment, making it an excellent, economical
software development tool.
Programmer
The MPLAB PICkit 3 allows debugging and
19.7 MPLAB REAL ICE In-Circuit programming of PIC and dsPIC Flash microcontrollers
Emulator System at a most affordable price point using the powerful
graphical user interface of the MPLAB IDE. The
The MPLAB REAL ICE In-Circuit Emulator System is MPLAB PICkit 3 is connected to the design engineer’s
Microchip’s next generation high-speed emulator for PC using a full-speed USB interface and can be
Microchip Flash DSC and MCU devices. It debugs and connected to the target via a Microchip debug (RJ-11)
programs all 8, 16 and 32-bit MCU, and DSC devices connector (compatible with MPLAB ICD 3 and MPLAB
with the easy-to-use, powerful graphical user interface of REAL ICE). The connector uses two device I/O pins
the MPLAB X IDE. and the Reset line to implement in-circuit debugging
The emulator is connected to the design engineer’s and In-Circuit Serial Programming™ (ICSP™).
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector 19.10 MPLAB PM3 Device Programmer
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal,
Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable
(CAT5). voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
The emulator is field upgradable through future firmware (128 x 64) for menus and error messages, and a mod-
downloads in MPLAB X IDE. MPLAB REAL ICE offers ular, detachable socket assembly to support various
significant advantages over competitive emulators package types. The ICSP cable assembly is included
including full-speed emulation, run-time variable as a standard item. In Stand-Alone mode, the MPLAB
watches, trace analysis, complex breakpoints, logic PM3 Device Programmer can read, verify and program
probes, a ruggedized probe interface and long (up to PIC devices without a PC connection. It can also set
three meters) interconnection cables. code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

PIC12F752/HV752
19.11 Demonstration/Development 19.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide and Trace Systems
application firmware and source code for examination • Protocol Analyzers from companies, such as
and modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and
demonstration software for analog filter design,
KEELOQ® security ICs, CAN, IrDA®, PowerSmart
battery management, SEEVAL® evaluation system,
Sigma-Delta ADC, flow rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

PIC12F752/HV752
20.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings(†)

Ambient temperature under bias ......................................................................................................... -40° to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC12HV752 .......................................................................................................... -0.3V to +6.5V
PIC12F752 ............................................................................................................. -0.3V to +6.5V
on MCLR ......................................................................................................................... -0.3V to +13.5V
on all other pins........................................................................................ ...............-0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C  TA  +85°C ............................................................................................................. 95 mA
-40°C  TA  +125°C ........................................................................................................... 95 mA
on VDD pin(1)
-40°C  TA  +85°C ............................................................................................................. 95 mA
-40°C  TA  +125°C ........................................................................................................... 95 mA
on RA1, RA4, RA5 .......................................................................................................................... 25 mA
on RA0, RA2 ................................................................................................................................... 50 mA
Clamp current, IK (VPIN < 0 or VPIN >VDD) 20 mA
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characteristics. See Table 20-6 to calculate device specific
limitations.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.

PIC12F752/HV752
20.1 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage: VDDMIN VDD VDDMAX
Operating Temperature: TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC12F752
VDDMIN (Fosc  8 MHz) ........................................................................................................... +2.0V
VDDMIN (8 MHz Fosc  10 MHz) ........................................................................................... +3.0V
VDDMAX (10 MHz Fosc  20 MHz) ........................................................................................ +5.5V
PIC12HV752
VDDMIN (Fosc  8 MHz) ........................................................................................................... +2.0V
VDDMIN (8 MHz Fosc  10 MHz) ........................................................................................... +3.0V
VDDMAX (10 MHz Fosc  20 MHz) ........................................................................................ +5.0V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Extended Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................. +125°C
Note 1: See Parameter D001, DS Characteristics: Supply Voltage.

PIC12F752/HV752
FIGURE 20-1: PIC12F752 VOLTAGE-FREQUENCY GRAPH,
-40°C TA +125°C
5.5
5.0
4.5
VDD (V)
4.0
3.5
3.0
2.5
2.0
0 8 10 20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 20-2: PIC12HV752 VOLTAGE-FREQUENCY GRAPH,

-40°C TA +125°C
5.0
4.5
VDD (V)
4.0
3.5
3.0
2.5
2.0
0 8 10 20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

PIC12F752/HV752
20.2 DC Characteristics
TABLE 20-1: SUPPLY VOLTAGE
PIC12F752 Standard Operating Conditions (unless otherwise stated)
PIC12HV752
Param.
Sym. Characteristic Min. Typ.† Max. Units Conditions
No.
D001 VDD Supply Voltage
VDDMIN VDDMAX
2.0 — 5.5 V FOSC  8 MHz
3.0 — 5.5 V FOSC  10 MHz
4.5 — 5.5 V FOSC 20 MHz
D001 2.0 — 5.0 V FOSC  8 MHz(2)
3.0 — 5.0 V FOSC  10 MHz(2)
4.5 — 5.0 V FOSC  20 MHz(2)
D002* VDR RAM Data Retention Voltage(1)
1.5 — — V Device in Sleep mode
D002 1.5 — — V Device in Sleep mode
D003* VPOR VDD Start Voltage to ensure internal Power-on Reset signal
— 1.6 — V
D003 — 1.6 — V
D004* SVDD VDD Rise Rate to ensure VDD Rise Rate internal Power-on Reset signal
0.05 — — V/ms See Table 17-1 for details.
* These parameters are characterized but not tested.
† Data in “Typ.” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: On the PIC12HV752, VDD is regulated by a Shunt Regulator and is dependent on series resistor
(connected between the unregulated supply voltage and the VDD pin) to limit the current to 50 mA. See
Section “” for design requirements.

PIC12F752/HV752
TABLE 20-2: SUPPLY CURRENT (IDD)(1,2)
PIC12HV752
Param. Max. Max. Conditions

Device Characteristics Min. Typ.† Units
No. 85°C 125°C VDD Note
(1, 2)
Supply Current (IDD)
D010 — 13 25 25 A 2.0 FOSC = 31 kHz
— 19 29 29 A 3.0 LFINTOSC mode
— 32 51 51 A 5.0
D010 — 160 230 230 A 2.0 FOSC = 31 kHz
— 240 310 310 A 3.0 LFINTOSC mode
— 280 400 400 A 4.5
D016 — 75 280 280 A 2.0 FOSC = 1 MHz
— 155 320 320 A 3.0 EC Oscillator mode
— 345 530 530 A 5.0
D016 — 215 310 310 A 2.0 FOSC = 1 MHz
— 570 650 650 A 4.5
D011 — 130 280 280 A 2.0 FOSC = 1 MHz
— 175 320 320 A 3.0 HFINTOSC mode
— 290 535 535 A 5.0
D011 — 195 296 296 A 2.0 FOSC = 1 MHz
— 315 440 440 A 3.0 HFINTOSC mode
— 425 650 650 A 4.5
D012 — 185 340 340 A 2.0 FOSC = 4 MHz
— 665 845 845 A 5.0
D012 — 330 475 475 A 2.0 FOSC = 4 MHz
— 850 1200 1200 A 4.5
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.

PIC12F752/HV752
TABLE 20-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED)
PIC12HV752
Param. Max. Max. Conditions

Device Characteristics Min. Typ.† Units
No. 85°C 125°C VDD Note
(1, 2)
Supply Current (IDD)
D013 — 245 340 340 A 2.0 FOSC = 4 MHz
— 360 485 485 A 3.0 HFINTOSC mode
— 620 845 845 A 5.0
D013 — 310 435 435 A 2.0 FOSC = 4 MHz
— 500 700 700 A 3.0 HFINTOSC mode
— 740 1100 1100 A 4.5
D014 — 395 550 550 A 2.0 FOSC = 8 MHz
— 620 850 850 A 3.0 HFINTOSC mode
— 1.2 1.6 1.6 mA 5.0
D014 — 460 650 650 A 2.0 FOSC = 8 MHz
— 750 1100 1100 A 3.0 HFINTOSC mode
— 1.2 1.6 1.6 mA 4.5
D015 — 1.9 2.6 2.6 mA 4.5 FOSC = 20 MHz
— 2.2 3 3 mA 5.0 EC Oscillator mode
D015 — 2.1 3 3 mA 4.5 FOSC = 20 MHz
EC Oscillator mode
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.

PIC12F752/HV752
TABLE 20-3: POWER-DOWN CURRENTS (IPD) (1,2)
Standard Operating Conditions (unless otherwise stated)
PIC12F752
Sleep mode
PIC12HV752
Param. Device Max. Max. Conditions

Min. Typ.† Units
No. Characteristics 85°C 125°C VDD Note
Power-down Base Current (IPD)(2)
D020 — 0.05 1.2 4.5 A 2.0 WDT, BOR, Comparator, VREF and
— 0.15 1.6 5.5 A 3.0 T1OSC disabled
— 0.35 2.1 9 A 5.0
D020 — 135 200 200 A 2.0
— 210 280 280 A 3.0
— 260 350 350 A 4.5
Power-down Base Current (IPD)(2, 3)
D021 — 0.5 1.5 5 A 2.0 WDT Current(1)
— 2.5 4 8 A 3.0
— 9.5 17 19 A 5.0
D021 — 135 200 200 A 2.0
— 210 285 285 A 3.0
— 265 360 360 A 4.5
D022 — 5 9 15 A 3.0 BOR Current(1)
— 6 12 19 A 5.0
D022 — 215 285 285 A 3.0
— 265 360 360 A 4.5
D023 — 160 235 245 A 2.0 CxSP = 1, Comparator Current(1),
— 180 270 280 A 3.0 single comparator enabled
— 220 350 360 A 5.0
D023 — 280 415 415 A 2.0
— 385 540 540 A 3.0
— 455 735 735 A 4.5
D024 — 50 70 75 A 2.0 CxSP = 0, Comparator Current(1),
— 55 80 90 A 3.0 single comparator enabled
— 70 90 120 A 5.0
D024 — 185 205 205 A 2.0
— 265 315 315 A 3.0
— 320 445 445 A 4.5
Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max values
should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: Shunt regulator is always on and always draws operating current.

PIC12F752/HV752
TABLE 20-3: POWER-DOWN CURRENTS (IPD) (CONTINUED)(1,2)
PIC12F752
Sleep mode
PIC12HV752
Param. Device Max. Max. Conditions

Min. Typ.† Units
No. Characteristics 85°C 125°C VDD Note
Power-down Base Current (IPD)(2, 3)
D025 — 0.2 3.0 6.5 A 3.0 A/D Current(1), no conversion in
— 0.36 3.5 10 A 5.0 progress
D025 — 210 280 280 A 3.0
— 260 350 350 A 4.5
D026 — 20.0 30 30 A 2.0 DAC Current(1)
— 30.0 40 40 A 3.0
— 50.0 70 70 A 5.0
D026 — 160 238 238 A 2.0
— 250 322 322 A 3.0
— 310 448 448 A 4.5
D027 — 295.0 436 485 A 2.0 FVR Current(1), FVRBUFEN = 1,
— 300 450 500 A 3.0 REFOUT buffer enabled
— 325 475 515 A 5.0
D027 — 395.0 605 605 A 2.0
— 470 710 710 A 3.0
— 505 765 765 A 4.5
D028 — 5.5 10 16 A 2.0 T1OSC Current,
— 7.0 12 18 A 3.0 TMR1CS <1:0> = 11
— 8.5 14 22 A 5.0
D028 — 140.0 205 205 A 2.0
— 220.0 290 290 A 3.0
— 270.0 360 360 A 4.5
Note 1: The peripheral  current can be determined by subtracting the base IPD current from this limit. Max values
should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: Shunt regulator is always on and always draws operating current.

PIC12F752/HV752
TABLE 20-4: I/O PORTS
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Param.
No.
VIL Input Low Voltage
I/O PORT:
D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V
D030A — — 0.15 VDD V 2.0V  VDD  4.5V
D031 with Schmitt Trigger buffer — — 0.2 VDD V 2.0V  VDD  5.5V
D032 MCLR — — 0.2 VDD V 2.0V  VDD  5.5V
VIH Input High Voltage
I/O PORT:
D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V
D040A 0.25 VDD + 0.8 — — V 2.0V  VDD  4.5V
D041 with Schmitt Trigger buffer 0.8 VDD — — V 2.0V  VDD  5.5V
D042 MCLR 0.8 VDD — — V 2.0V  VDD  5.5V
(1)
IIL Input Leakage Current
D060 I/O ports — 0.1 1 A VSS VPIN VDD,
Pin at high-impedance, 85°C
D061 RA3/MCLR(2) — 0.7 5 A VSS VPIN VDD,
Pin at high-impedance, 85°C
D063 — 0.1 5 A EC Configuration
(3)
IPUR Weak Pull-up Current
D070* 50 250 400 A VDD = 5.0V, VPIN = VSS
VOL Output Low Voltage
D080 I/O Ports RA1, RA4 and RA5 — — 0.6 V IOL = 7 mA, VDD = 4.5V
-40°C TA +125°C
— — 0.6 V IOL = 8.5 mA, VDD = 4.5V
-40°C TA +85°C
I/O Ports RA0 and RA2 — — 0.6 V IOL = 14 mA, VDD = 4.5V
-40°C TA +125°C
— — 0.6 V IOL = 17 mA, VDD = 4.5V
-40°C TA +85°C
VOH Output High Voltage
D090 I/O Ports RA1, RA4 and RA5 VDD-0.7 — — V IOH = -2.5 mA, VDD = 4.5V
-40°C TA +125°C
VDD-0.7 — — V IOH = -3 mA, VDD = 4.5V
-40°C TA +85°C
I/O Ports RA0 and RA2 VDD-0.7 — — V IOH = -5 mA, VDD = 4.5V
-40°C TA +125°C
VDD-0.7 — — V IOH = -6 mA, VDD = 4.5V
-40°C TA +85°C
† Data in “Typ.” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: This specification applies to all weak pull-up pins, including the weak pull-up found on RA3/MCLR. When RA3/MCLR is
configured as MCLR Reset pin, the weak pull-up is always enabled.

PIC12F752/HV752
TABLE 20-4: I/O PORTS (CONTINUED)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Param.
No.
Capacitive Loading Specs on Output Pins
D101* COSC2 OSC2 pin — — 15 pF
D101A* CIO All I/O pins — — 50 pF
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: This specification applies to all weak pull-up pins, including the weak pull-up found on RA3/MCLR. When RA3/MCLR is
configured as MCLR Reset pin, the weak pull-up is always enabled.
TABLE 20-5: MEMORY PROGRAMMING SPECIFICATIONS

Param.
No.
Program Memory
Programming Specifications
D110 VIHH Voltage on MCLR/VPP pin 10.0 — 13.0 V (Note 1)
D112 VBE VDD for Bulk Erase 4.5 — VDDMAX V
D113 VPEW VDD for Write or Row Erase 4.5 — VDDMAX V
D114 IPPPGM Current on MCLR/VPP during — 300 1000 A
Erase/Write
Program Flash Memory
D121 EP Cell Endurance 10K 100K — E/W -40C  TA +85C
(Note 2)
D121A EP Cell Endurance 1K 10K — E/W -40C  TA +125C
(Note 2)
D122 VPRW VDD for Read/Write VDDMIN — VDDMAX V
D123 TIW Self-timed Write Cycle Time — 2 2.5 ms
D124 TRETD Characteristic Retention 40 — — Year Provided no other
specifications are violated
Note 1: Required only if single-supply programming is disabled.
2: Self-write and Block Erase.

PIC12F752/HV752
TABLE 20-6: THERMAL CHARACTERISTICS
Param.
Sym. Characteristic Typ. Units Conditions
No.
TH01 JA Thermal Resistance Junction to Ambient 84.6 °C/W 8-pin PDIP package
149.5 °C/W 8-pin SOIC package
60 °C/W 8-pin DFN 3x3mm package
TH02 JC Thermal Resistance Junction to Case 41.2 °C/W 8-pin PDIP package
39.9 °C/W 8-pin SOIC package
9 °C/W 8-pin DFN 3x3mm package
TH03 TJMAX Maximum Junction Temperature 150 °C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/O I/O Power Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD
- VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient temperature; TJ = Junction Temperature

PIC12F752/HV752
20.3 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O Port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (High-Impedance) V Valid
L Low Z High-Impedance
FIGURE 20-3: LOAD CONDITIONS
Load Condition
Pin CL
VSS
Note: CL = 50 pF for all pins.

PIC12F752/HV752
20.4 AC Characteristics: PIC12F752/HV752 (Industrial, Extended)
FIGURE 20-4: CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
CLKIN
OS02
OS04 OS04
OS03
CLKOUT
CLKOUT
(CLKOUT Mode)
TABLE 20-7: CLOCK OSCILLATOR TIMING REQUIREMENTS

Param.
No.
OS01 FOSC External CLKIN Frequency(1) DC — 20 MHz EC Oscillator mode
OS02 TOSC External CLKIN Period (1)
50 —  ns EC Oscillator mode
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
† Data in “Typ.” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

PIC12F752/HV752
TABLE 20-8: OSCILLATOR PARAMETERS
Param. Freq.
No. Tolerance
OS06 TWARM Internal Oscillator Switch when — — — 2 TOSC
running
OS07 INTOSC Internal Calibrated 1% 3.96 4.0 4.04 MHz VDD = 3.5V, TA = 25°C
INTOSC Frequency(1) 2% 3.92 4.0 4.08 MHz 2.5V VDD  5.5V,
(4 MHz) 0°C  TA  +85°C
5% 3.80 4.0 4.20 MHz 2.0V VDD  5.5V,
-40°C  TA  +85°C (Ind.),
-40°C  TA  +125°C (Ext.)
OS08 HFOSC Internal Calibrated 1% 7.92 8 8.08 MHz VDD = 3.5V, TA = 25°C
HFINTOSC Frequency(1) 2% 7.84 8 8.16 MHz 2.5V VDD  5.5V,
0°C  TA  +85°C
5% 7.60 8 8.40 MHz 2.0V VDD  5.5V,
-40°C  TA  +85°C (Ind.),
-40°C  TA  +125°C (Ext.)
OS09 LFOSC Internal LFINTOSC — — 31 — kHz
Frequency
OS10* TIOSC ST HFINTOSC Wake-up from — — 12 24 s VDD = 2.0V -40°C  TA  +85°C
Sleep Start-up Time — 7 14 s VDD = 3.0V -40°C  TA  +85°C
— 6 11 s VDD = 5.0V -40°C  TA  +85°C
not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.

PIC12F752/HV752
FIGURE 20-5: CLKOUT AND I/O TIMING
Cycle Write Fetch Read Execute
Q4 Q1 Q2 Q3
FOSC
OS20
CLKOUT OS21
OS19 OS18
OS16
OS13 OS17
I/O pin
(Input)
OS15 OS14
I/O pin New Value

Old Value
(Output)
OS18, OS19
TABLE 20-9: CLKOUT AND I/O TIMING PARAMETERS

Param.
No.
OS13 TCKL2IOV CLKOUT to Port out valid(1) — — 20 ns
OS14 TIOV2CKH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TOSH2IOV FOSC (Q1 cycle) to Port out valid — 50 70* ns VDD =5.0V
OS16 TOSH2IOI FOSC (Q2 cycle) to Port input invalid 50 — — ns VDD =5.0V
(I/O in setup time)
OS17 TIOV2OSH Port input valid to FOSC(Q2 cycle) 20 — — ns
(I/O in setup time)
OS18* TIOR Port output rise time — 40 72 ns VDD =2.0V
— 15 32 ns VDD =5.0V
OS19* TIOF Port output fall time — 28 55 ns VDD =2.0V
— 15 30 ns VDD =5.0V
OS20* TINP INT pin input high or low time 25 — — ns
OS21* TIOC Interrupt-on-change new input level TCY — — ns
time
† Data in “Typ.” column is at 5.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

PIC12F752/HV752
FIGURE 20-6: RESET, WATCHDOG TIMER AND POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note: Asserted low.
FIGURE 20-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR + VHYST
VBOR
(Device in Brown-out Reset) (Device not in Brown-out Reset)
37
Reset
33*
(due to BOR)
* 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.

PIC12F752/HV752
TABLE 20-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Param.
No.
30 TMCL MCLR Pulse Width (low) 2 — — s VDD = 5V, -40°C to +85°C

5 — — s VDD = 5V, -40°C to +125°C
31 TWDTLP Low-Power Watchdog Timer 10 20 30 ms VDD = 5V, -40°C to +85°C
Time-out Period 10 20 35 ms VDD = 5V, -40°C to +125°C
32* TPWRT Power-up Timer Period, 40 65 140 ms
PWRTE = 0 (No Prescaler)
33* TIOZ I/O high-impedance from — — 2.0 s
MCLR Low or Watchdog Timer
Reset
34 VBOR Brown-out Reset Voltage (1) 2 2.15 2.3 V
35* VHYST Brown-out Reset Hysteresis — 100 — mV -40°C  TA  +85°C
36* TBOR Brown-out Reset DC Minimum 100 — — s VDD  VBOR
Detection Period
† Data in “Typ.” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device
as possible. 0.1 F and 0.01 F values in parallel are recommended.

PIC12F752/HV752
FIGURE 20-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
TABLE 20-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param.
No.
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
42* TT0P T0CKI Period Greater of: — — ns N = prescale
20 or TCY + 40 value
N
45* TT1H T1CKI High Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Time Synchronous, with Prescaler 15 — — ns
47* TT1P T1CKI Input Synchronous Greater of: — — ns N = prescale
Period 30 or TCY + 40 value
N
49* TCKEZT- Delay from External Clock Edge to Timer 2 TOSC — 7 TOSC — Timers in Sync
MR1 Increment mode
† Data in “Typ.” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.

PIC12F752/HV752
FIGURE 20-9: PIC12F752/HV752 CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP1
(Capture mode)
CC01 CC02
CC03
Note: Refer to Figure 20-3 for load conditions.
TABLE 20-12: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Param.
No.
CC01* TccL CCP1 Input Low Time No Prescaler 0.5TCY + 20 — — ns
CC02* TccH CCP1 Input High Time No Prescaler 0.5TCY + 20 — — ns
CC03* TccP CCP1 Input Period 3TCY + 40 — — ns N = prescale
N value (1, 4 or
16)
TABLE 20-13: COMPARATOR SPECIFICATIONS(1)

Param.
Sym. Characteristics Min. Typ.† Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage —  10  20 mV CxSP = 1
 10  20 mV CxSP = 0
CM02 VICM Input Common Mode Voltage 0 — VDD – 1.5 V
CM03 CMRR Common Mode Rejection Ratio — 50 — dB
CM04A* TRT Response Time — 38 45 ns CxSP = 1
— 81 100 ns CxSP = 0
CM05* TMC20V Comparator Mode Change to Output Valid — — 10 s
CM06 CHYSTER Comparator Hysteresis — 35 50 mV
Note 1: See Section 21.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.

PIC12F752/HV752
TABLE 20-14: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS(1)
Param.
Sym. Characteristics Min. Typ.† Max. Units Comments
No.
DAC01* CLSB Step Size(2) — VDD/ 32 — V
DAC02* CACC Absolute Accuracy — —  1/2 LSb
DAC03* CR Unit Resistor Value (R) — 5K — 
DAC04* CST Settling Time(3) — — 10 s
Note 1: See Section 21.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
2: Setting DACRNG = 1 for full range mode. See Example 14-2 for limited range calculation.
3: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.
TABLE 20-15: FIXED VOLTAGE REFERENCE SPECIFICATIONS

Param
Symbol Characteristics Min. Typ. Max. Units Comments
No.
VR01 VFVR FVR Voltage Output 1.116 1.2 1.284 V
VR02* TSTABLE FVR Turn On Time — 200 — s
TABLE 20-16: SHUNT REGULATOR SPECIFICATIONS (PIC12HV752 only)

Param.
Symbol Characteristics Min. Typ. Max. Units Comments
No.
SR01 VSHUNT Shunt Voltage 4.75 5 5.5 V
SR02 ISHUNT Shunt Current 1 — 50 mA
SR03* TSETTLE Settling Time — — 150 ns To 1% of final value
SR04 CLOAD Load Capacitance 0.01 — 10 F Bypass capacitor on VDD
pin
SR05 ISNT Regulator operating current — 180 — A Includes band gap
reference current

PIC12F752/HV752
TABLE 20-17: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3)
Param.
No.
AD01 NR Resolution — — 10 bit
AD02 EIL Integral Error — — 1 LSb VREF = 3.0V
AD03 EDL Differential Error — — 1 LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error — 1.5 2.0 LSb VREF = 3.0V
AD05 EGN Gain Error — — 1.0 LSb VREF = 3.0V
AD06 VREF Reference Voltage 2.2 — — V Absolute minimum to ensure 1 LSb
2.5 — VDD accuracy
AD07 VAIN Full-Scale Range VSS — VREF V
AD08 ZAIN Recommended — — 10 k Can go higher if external 0.01 F
Impedance of Analog capacitor is present on input pin.
Voltage Source
AD09* IREF VREF Input Current 10 — 1000 A During VAIN acquisition.
Based on differential of VHOLD to
VAIN.
— — 50 A During A/D conversion cycle.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: See Section 21.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.

PIC12F752/HV752
TABLE 20-18: ADC CONVERSION REQUIREMENTS
Param.
No.
AD130 TAD ADC Internal FRC 3.0 6.0 9.0 s At VDD = 2.5V
* Oscillator Period
1.6 4.0 6.0 s At VDD = 5.0V
ADC Clock Period 1.6 — 9.0 s FOSC-based, VREF 3.0V
3.0 — 9.0 s TOSC-based, VREF full range(2)
AD131 TCNV Conversion Time — 11 — TAD Set GO/DONE bit to conversion
(not including complete
Acquisition Time)(1)
AD132 TACQ Acquisition Time — 11.5 — s
*
AD133 TAMP Amplifier Settling — — 5 s
* Time
AD134 TGO Q4 to A/D Clock Start — TOSC/2 — —
THCD Holding Capacitor — 1/2 TAD — — FOSC-based
Disconnect Time — 1/2 TAD + 1 TCY — ADCS<2:0> = x11 (ADC FRC mode)
Note 1: The ADRES register may be read on the following TCY cycle. See Section 12.4 “A/D Acquisition
Requirements” for minimum conditions.
2: Full range for PIC12HV752 powered by the shunt regulator is the 5V regulated voltage.
FIGURE 20-10: PIC12F752/HV752 A/D CONVERSION TIMING (ADC CLOCK FOSC-BASED)
BSF ADCON0, GO
1 TCY
AD134 (TOSC/2)
AD131
Q4
AD130
A/D CLK
A/D Data 9 8 7 6 3 2 1 0
ADRES OLD_DATA NEW_DATA
ADIF 1 TCY
GO DONE
Sampling Stopped
AD132
Sample

PIC12F752/HV752
21.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each
temperature range.

PIC12F752/HV752
FIGURE 21-1: IDD, LFINTOSC, FOSC = 31 kHz, PIC12F752 ONLY
60
Max: Mean + 3ı (125°C)

50 Typical: Mean (25°C) Max
40
IDD (µA)
Typical
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-2: IDD, LFINTOSC, FOSC = 31 kHz, PIC12HV752 ONLY
450
400 Max
350 Typical: Mean (25°C)
300
Typical
IDD (µA)
250
200
150
100
50
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-3: IDD TYPICAL, HFINTOSC, PIC12F752 ONLY
1400
Typical: Mean (25°C)

1200 8 MHz
1000
800
IDD (µA)
600 4 MHz
400
1 MHz
200
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-4: IDD MAXIMUM, HFINTOSC, PIC12F752 ONLY
1800
1600 Max: Mean + 3ı (125°C)

8 MHz
1400
1200
1000
IDD (µA)
800 4 MHz
600
1 MHz
400
200
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC12F752/HV752
FIGURE 21-5: IDD TYPICAL, HFINTOSC, PIC12HV752 ONLY
1400

1200 8 MHz
1000
800
IDD (µA)
4 MHz
600
400 1 MHz
200
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)
FIGURE 21-6: IDD MAXIMUM, HFINTOSC, PIC12HV752 ONLY
1800
1600 Max: Mean + 3ı (125°C) 8 MHz
1400
1200
4 MHz
IDD (µA)
1000
800
1 MHz
600
400
200
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-7: IDD TYPICAL, EXTERNAL CLOCK (EC), PIC12F752 ONLY
700
4 MHz
600
500
IDD (µA)
400
1 MHz
300
200
100
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-8: IDD MAXIMUM, EXTERNAL CLOCK (EC), PIC12F752 ONLY
900
4 MHz
800 Max: Mean + 3ı (125°C)
700
600
IDD (µA)
1 MHz
500
400
300
200
100
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC12F752/HV752
FIGURE 21-9: IDD TYPICAL, EXTERNAL CLOCK (EC), PIC12HV752 ONLY
900
4 MHz
800
700
600
1 MHz
500
IDD (µA)
400
300
200
100
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)
FIGURE 21-10: IDD MAXIMUM, EXTERNAL CLOCK (EC), PIC12HV752 ONLY
1400
1200 Max: Mean + 3ı (125°C) 4 MHz
1000
IDD (µA)
800
1 MHz
600
400
200
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-11: IDD, EXTERNAL CLOCK (EC), FOSC = 20 MHz, PIC12F752 ONLY
3.5
3.0 Typical: Mean (25°C) Max
2.5
Typical
2.0
IDD (mA)
1.5
1.0
0.5
0.0
4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1
VDD (V)

PIC12F752/HV752
FIGURE 21-12: IPD BASE, PIC12F752 ONLY
10
9 Max125
Max125: Mean + 3ı (125°C)
8 Max 85: Mean + 3ı (85°C)
7
6
IPD (µA)
2 Max85
1
Typical
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-13: IPD BASE, PIC12HV752 ONLY
400
300
Typical
250
IPD (µA)
200
150
100
50
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-14: IPD, WATCHDOG TIMER (WDT), PIC12F752 ONLY
20
Max125
18 Max125: Mean + 3ı (125°C)
Max 85: Mean + 3ı (85°C) Max85
16
14
12
(µA)
IPD (µ
10
Typical
8
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-15: IPD, WATCHDOG TIMER (WDT), PIC12HV752 ONLY
400
350 Max
300
Typical
250
(µA)
IPD (µA
200
150
100
50
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-16: IPD FIXED VOLTAGE REFERENCE (FVR), PIC12F752 ONLY
600
500 Max125
Max85
400
(µA)
Typical
IPD (µ
300
Max125:
M 125 MMean + 33ı (125°C)
200
Max 85: Mean + 3ı (85°C)
100
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-17: IPD FIXED VOLTAGE REFERENCE (FVR), PIC12HV752 ONLY
900
800 M
Max: M
Mean + 33ı (125°C)
Typical: Mean (25°C) Max
700
600
500 Typical
yp
(µA)
IPD (µA
400
300
200
100
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-18: IPD, BROWN-OUT RESET (BOR), PIC12F752 ONLY
22
20 Max125: Mean + 3ı (125°C)

Max 85: Mean + 3ı (85°C) Max125
16
14
IPD (µA)
12 Max85
10
6 Typical
2
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-19: IPD, BROWN-OUT RESET (BOR), PIC12HV752 ONLY
400
Max: Mean + 3ı (125°C) Max

300
Typical
250
µA)
IPD (µA)
200
150
100
50
2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-20: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC12F752 ONLY
25
Max125: Mean + 3ı (125°C)
Max 85: Mean + 3ı (85°C) Max125
15
(µA)
Max85
IPD (µ
10
Typical
0
1 5
1.5 2 0
2.0 2 5
2.5 3 0
3.0 3 5
3.5 4 0
4.0 4 5
4.5 5 0
5.0 5 5
5.5
VDD (V)
FIGURE 21-21: IPD, TIMER1 OSCILLATOR, FOSC = 32 kHz, PIC12HV752 ONLY
400
Max
350 Max: Mean + 3ı (125°C)
300
Typical
250
(µA)
IPD (µA
200
150
100
50
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-22: IPD, DAC, PIC12F752 ONLY
80
70 Max: Mean + 3ı (125°C) Max

60
50 Typical
(µA)
IPD (µA
40
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-23: IPD, DAC, PIC12HV752 ONLY
500
450 Max
350
Typical
300
(µA)
IPD (µA
250
200
150
100
50
0
15
1.5 2
2.0
0 2
2.5
5 3
3.0
0 3
3.5
5 4
4.0
0 4
4.5
5 5
5.0
0
VDD (V)

PIC12F752/HV752
FIGURE 21-24: IPD, COMPARATOR, LOW-POWER MODE, CxSP = 0, PIC12F752 ONLY
140
Max125:
M 125 MMean + 33ı (125°C)
120 Max 85: Mean + 3ı (85°C) Max125
100
Max85
80
(µA)
IPD (µA
Typical
60
40
20
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-25: IPD, COMPARATOR, LOW-POWER MODE, CxSP = 0, PIC12HV752 ONLY
500
450 Max
350
Typical
IPD ((µA)
300
250
200
150
100
50
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-26: IPD, COMPARATOR, NORMAL-POWER MODE, CxSP = 1, PIC12F752 ONLY
400
Max125: Mean + 3ı (125°C) Max125
Max 85: Mean + 3ı (85°C)
Max85
300
(µA)
IPD (µA
250
Typical
200
150
100
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-27: IPD, COMPARATOR, NORMAL-POWER MODE, CxSP = 1, PIC12HV752 ONLY
800
Max
700 Max: Mean + 3ı (125°C)
600
500
Typical
(µA)
IPD (µA
400
300
200
100
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-28: IPD, ADC NO CONVERSION IN PROGRESS, PIC12F752 ONLY
12
Max125: Mean + 3ı (125°C)

10 Max 85: Mean + 3ı (85°C) Max125
8
(µA)
IPD (µA
4
Max85
2
Typical
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-29: IPD, ADC NO CONVERSION IN PROGRESS, PIC12HV752 ONLY
400

300
(µA)
Typical
IPD (µA
250
200
150
100
2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)

PIC12F752/HV752
FIGURE 21-30: VOH vs. IOH, RA0/RA2, OVER TEMPERATURE, VDD = 5.0V
5.1
5.0
Max125: Mean + 3ı (125°C)
4.9 Max 85: Mean + 3ı (85°C)
4.8 Min: Mean - 3ı (-40°C)
4.7
VOH (V)
4.6
Min
4.5
Typical
4.4
Max85
4.3
Max125
4.2
4.1
-21 -18 -15 -12 -9 -6 -3 0
IOH (mA)
FIGURE 21-31: VOH vs. IOH, RA1/RA4/RA5, OVER TEMPERATURE, VDD = 5.0V
5.2
5.0 Typical: Mean (25°C)
Min: Mean - 3ı (-40°C)
4.8
Min
Voh (V)
4.6
Typical
4.4
4.2
Max
4.0
-5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
Ioh (mA)

PIC12F752/HV752
FIGURE 21-32: ( VOH vs.)IOH, RA0/RA2, OVER TEMPERATURE, VDD = 3.0V
3.0
Max125: Mean + 3ı (125°C)

2.8 Max 85: Mean + 3ı (85°C)
2.6
VOH (V)
Min
2.4
Typical
Max85
2.2
Max125
2.0
-15 -12 -9 -6 -3 0
IOH (mA)
FIGURE 21-33: VOH vs. IOH, RA1/RA4/RA5, OVER TEMPERATURE, VDD = 3.0V
3.5
3.0
Min
2.5
VOH (V)
Typical
2.0

Max Typical: Mean (25°C)
1.5
1.0
-4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
IOH (mA)

PIC12F752/HV752
FIGURE 21-34: VOL vs. IOL, RA0/RA2, OVER TEMPERATURE, VDD = 5.0V
0.7
Max125
0.6
Max125: Mean + 3ı (125°C)
Typical
0.4
VOL (V)
Min
0.3
0.2
0.1
0
0 10 20 30 40
IOL (mA)
FIGURE 21-35: VOL vs. IOL, RA1/RA4/RA5, OVER TEMPERATURE, VDD = 5.0V
0.45
0.40 Max125: Mean + 3ı (125°C)

Max125
Max85: Mean + 3ı (85°C)
0.35 Min: Mean - 3ı (-40°C) Max85
0.30
VOL (V)
Typical
0.25
0.20
Min
0.15
0.10
0.05
4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5
IOL (mA)

PIC12F752/HV752
FIGURE 21-36: VOL vs. IOL, RA0/RA2, OVER TEMPERATURE, VDD = 3.0V
1.2
1.1
Max125: Mean + 3ı (125°C) Max125
1.0
0.8
Typical
0.7
VOL (V)
0.6
Min
0.5
0.4
0.3
0.2
0.1
0.0
0 5 10 15 20 25 30 35 40
IOL (mA)
FIGURE 21-37: VOL vs. IOL, RA1/RA4/RA5, OVER TEMPERATURE, VDD = 3.0V
0.8
0.7 Max125: Mean + 3ı (125°C)

Max125
Max85: Mean + 3ı (85°C)
Typical: Mean (25°C) Max85
0.6
Min: Mean - 3ı (-40°C
0.5
VOL (V)
Typical
0.4
0.3
Min
0.2
0.1
0.0
4 5 6 7 8 9 10 11
IOL (mA)

PIC12F752/HV752
FIGURE 21-38: SCHMITT TRIGGER INPUT THRESHOLD, VIN vs. VDD, OVER TEMPERATURE
4.0
Min
3.5
Max125: Mean + 3ı (125°C)
Typical
Max85: Mean + 3ı (85°C)
2.5
VIN(V)
2.0
Max85
1.5
Max125
1.0
0.5
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD(V)
FIGURE 21-39: TTL INPUT THRESHOLD, VIN vs. VDD, OVER TEMPERATURE
1.7
1.5 Max125: Mean + 3ı (125°C)

Min
1.3 Typical
VIN (V)
Max
1.1
0.9
0.7
0.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC12F752/HV752
FIGURE 21-40: SHUNT REGULATOR VOLTAGE, PIC12HV752 ONLY
5.16
5.14 Max125: Mean + 3ı (125°C) Min
Max85: Mean + 3ı (85°C) Typical
5.12
Shunt Regulator Voltage(V)

Min: Mean - 3ı (-40°C) Max85
5.10
Max125
5.08
5.06
5.04
5.02
5.00
4.98
4.96
4.94
0 10 20 30 40 50 60
Input Current (mA)
FIGURE 21-41: TYPICAL HFINTOSC, START-UP TIMES vs. VDD, OVER TEMPERATURE
16
Max
14 Max: Mean + 3ı (85°C)
12 Min: Mean - 3ı (-40°C)
Typical
10 Min
Time (us)
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)

PIC12F752/HV752
FIGURE 21-42: WDT TIME-OUT PERIOD
55
50
Max125: Mean + 3ı (125°C)
45 Max85: Mean + 3ı (85°C)
40 Min: Mean - 3ı (-40°C)
35
Time (ms)
30
Max125
25 Max85
20
Typical
15
10 Min
5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC12F752/HV752
FIGURE 21-43: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER
S MODE,
G G CxSP = 1, RISING EDGE
80
75
70 Max: Mean + 3ı (125°C)

65 Min: Mean - 3ı (-40°C)
Time (ns)
60
55
50
45
Max
40
Typical
35 Min
30
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 21-44: COMPARATOR RESPONSE TIME OVER TEMPERATURE, NORMAL-POWER

MODE, CxSP = 1, FALLING EDGE
90
80 Max: Mean + 3ı (125°C)

Time (ns)
70
60
50
Max
40 Typical
Min
30
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC12F752/HV752
22.0 PACKAGING INFORMATION
22.1 Package Marking Information
8-Lead PDIP (300 mil) Example
XXXXXXXX 12F752
XXXXXNNN E/P e3 121
YYWW 1109
8-Lead SOIC (3.90 mm) Example
12F752
ESN1109
NNN 121
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC® designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.

PIC12F752/HV752
22.1 Package Marking Information (Continued)
8-Lead DFN (3x3x0.9 mm) Example
XXXX MFU0
YYWW 1109
NNN 121
PIN 1 PIN 1
TABLE 22-1: 8-LEAD 3x3 DFN (MF) TOP MARKING

Part Number Marking
PIC12F752-E/MF MFU0
PIC12F752-I/MF MFV0
PIC12HV752-E/MF MFW0
PIC12HV752-I/MF MFX0
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.

PIC12F752/HV752
22.2 Package Details
The following sections give the technical details of the packages.
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D A
N B
E1
NOTE 1
1 2
TOP VIEW
C A A2
PLANE
L c
A1
e eB
8X b1
8X b
.010 C
SIDE VIEW END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2

PIC12F752/HV752
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
ALTERNATE LEAD DESIGN

(VENDOR DEPENDENT)
DATUM A DATUM A
b b
e e
2 2
e e
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 - -
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB - - .430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2

PIC12F752/HV752

PIC12F752/HV752

PIC12F752/HV752

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($)

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PIC12F752/HV752

PIC12F752/HV752

PIC12F752/HV752

PIC12F752/HV752
APPENDIX A: DATA SHEET APPENDIX B: MIGRATING FROM
REVISION HISTORY PIC12HV615
Revision A (04/2011) This compares the features of the PIC12HV615 to the
PIC12HV752 family of devices.
Original release.
B.1 PIC12HV615 to PIC12HV752
Revision B (11/2011) TABLE B-1: FEATURE COMPARISON
Redefined operation of the COG module; Added slew Feature PIC12HV615 PIC12HV752
rate control to the COG module; Added zero latency
filter to the comparator; Updated Electrical Max Operating Speed 20 MHz 20 MHz
Specifications. Max Program 1024 1024
Memory (Words)
Revision C (11/2013) Flash Self Read/ No Yes
Self Write
Redefined operation of the COG module; Updated the SRAM (bytes) 64 64
I/O Ports chapter; Updated the Electrical Specifications
Oscillator modes 8 2
chapter; Added graphs to the DC and AC
Characteristics Graphs and Charts chapter; Other INTOSC Frequencies 4/8 MHz 1/4/8 MHz
and 31 kHz
minor corrections.
Brown-out Reset (BOR) Y Y
Revision D (10/2015) Internal Pull-ups GP0/1/2/3/4/5 RA0/1/2/3/4/5

Interrupt-on-change GP0/1/2/3/4/5 RA0/1/2/3/4/5
Updated the eXtreme Low-Power Features section,
Analog-to-Digital 4 4
Table 1, Figure 1 and the RA3 pin description in Converter (ADC)
Table1-1; Updated PDIP package drawings in Section Channels
22.2 (Package Details); Other minor corrections.
A/D Resolution 10-bit 10-bit
Timers (8/16-bit) 2/1 3/1
Comparator 1 2 High Speed
ECCP/CCP 1/0 0/1
Complementary Output No Yes
Generator (COG)
Digital-to-Analog Converter No Yes
(DAC) 5-bit Dual Range
Fixed Voltage Reference No Yes
(FVR)
Internal Shunt Regulator Yes Yes
Note: This device has been designed to perform

to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performance characteristics than its earlier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.

PIC12F752/HV752
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our web site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design Customers should contact their distributor,
resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for
documents, latest software releases and archived support. Local sales offices are also available to help
software customers. A listing of sales offices and locations is
• General Technical Support – Frequently Asked included in the back of this document.
Questions (FAQ), technical support requests, Technical support is available through the web site
online discussion groups, Microchip consultant at: http://www.microchip.com/support
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

PIC12F752/HV752
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. [X](1) - X /XX XXX

Examples:
Device Tape and Reel Temperature Package Pattern a) PIC12F752T - I/MF 301
Option Range Tape and Reel,
Industrial temperature,
DFN 3x3 package,
QTP pattern #301
Device: PIC12F752 b) PIC12F752 - E/P
PIC12HV752 Extended temperature
PDIP package
c) PIC12F752 - E/SN
Tape and Reel Blank = Standard packaging (tube or tray) Extended temperature,
Option: T = Tape and Reel(1) SOIC package
d) PIC12HV752 - E/MF
Extended temperature,
Temperature I = -40C to +85C (Industrial) DFN 3x3 package
Range: E = -40C to +125C (Extended)
Package: P = Plastic DIP (PDIP)

SN = 8-lead Small Outline (3.90 mm) (SOIC) Note 1: Tape and Reel identifier only appears in the
MF = 8-lead Plastic Dual Flat, No Lead (3x3) (DFN) catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
Pattern: QTP, SQTP, Code or Special Requirements availability with the Tape and Reel option.
(blank otherwise)

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
ensure that your application meets with your specifications.
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
MICROCHIP MAKES NO REPRESENTATIONS OR
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
SST, SST Logo, SuperFlash and UNI/O are registered
IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the
OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
conveyed, implicitly or otherwise, under any Microchip Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
intellectual property rights unless otherwise stated. Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-887-1
QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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01/27/15

PIC12F752/HV752: 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

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PIC12F752/HV752: 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

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PIC12F752/HV752

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers

High-Performance RISC CPU Peripheral Features

 2011-2015 Microchip Technology Inc. DS40001576D-page 1

TABLE 1: PIC12F752/HV752 FEATURE SUMMARY

10-bit A/D (ch)

PIC12F752 1024 Y 64 6 4 2 3/1 1 Y N Y

FIGURE 1: 8-PIN PDIP, SOIC, DFN

Note: See Table 1 for the location of all peripheral functions.

DS40001576D-page 2  2011-2015 Microchip Technology Inc.

RA0(4) 7 AN0 C1IN0+ — — IOC Y COG1OUT1 DACOUT ICSPDAT

 2011-2015 Microchip Technology Inc. DS40001576D-page 3

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

DS40001576D-page 4  2011-2015 Microchip Technology Inc.

FIGURE 1-1: PIC12F752/HV752 BLOCK DIAGRAM

Direct Addr 7 Indirect

Shunt Regulator Hardware

 2011-2015 Microchip Technology Inc. DS40001576D-page 5

DS40001576D-page 6  2011-2015 Microchip Technology Inc.

2.2.2 SPECIAL FUNCTION REGISTERS

 2011-2015 Microchip Technology Inc. DS40001576D-page 7

48 Bytes 6Fh EFh 16Fh 1EFh

Legend: = Unimplemented data memory locations, read as ‘0’.

DS40001576D-page 8  2011-2015 Microchip Technology Inc.

1Fh ADCON1 — ADCS<2:0> — — — — -000 ---- -000 ----

 2011-2015 Microchip Technology Inc. DS40001576D-page 9

DS40001576D-page 10  2011-2015 Microchip Technology Inc.

 2011-2015 Microchip Technology Inc. DS40001576D-page 11

189h OSCTUNE — — — TUN<4:0> ---0 0000 ---u uuuu

193h COG1BLK G1BLKR<3:0> G1BLKF<3:0> xxxx xxxx uuuu uuuu

DS40001576D-page 12  2011-2015 Microchip Technology Inc.

REGISTER 2-1: STATUS: STATUS REGISTER

 2011-2015 Microchip Technology Inc. DS40001576D-page 13

REGISTER 2-2: OPTION_REG: OPTION REGISTER

bit 7 RAPU: PORTA Pull-up Enable bit

DS40001576D-page 14  2011-2015 Microchip Technology Inc.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

bit 7 GIE: Global Interrupt Enable bit

Note 1: IOC register must also be enabled.

 2011-2015 Microchip Technology Inc. DS40001576D-page 15

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

bit 7 TMR1GIE: ADC Interrupt Enable bit

DS40001576D-page 16  2011-2015 Microchip Technology Inc.

REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 1

bit 7-6 Unimplemented: Read as ‘0’

 2011-2015 Microchip Technology Inc. DS40001576D-page 17

REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

bit 7 TMR1GIF: TMR1 Gate Interrupt Flag bit

DS40001576D-page 18  2011-2015 Microchip Technology Inc.

REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 1

bit 7-6 Unimplemented: Read as ‘0’

 2011-2015 Microchip Technology Inc. DS40001576D-page 19

bit 7-2 Unimplemented: Read as ‘0’

DS40001576D-page 20  2011-2015 Microchip Technology Inc.

PCLATH<4:0> 8 2: There are no instructions/mnemonics

 2011-2015 Microchip Technology Inc. DS40001576D-page 21

Direct Addressing Indirect Addressing