Stm32h753xi PDF

STM32H753xI
32-bit Arm® Cortex®-M7 480MHz MCUs, 2MB Flash,

1MB RAM, 46 com. and analog interfaces, crypto
Datasheet - production data
Features FBGA FBGA
Core
• 32-bit Arm® Cortex®-M7 core with double-
LQFP100 TFBGA100 UFBGA169
precision FPU and L1 cache: 16 Kbytes of data (14 x 14 mm) (8 x 8 mm)(1) (7 x 7 mm)
and 16 Kbytes of instruction cache; frequency LQFP144 TFBGA240+25 UFBGA176+25
(20 x 20 mm) (14 x 14 mm) (10 x 10 mm)
up to 480 MHz, MPU, 1027 DMIPS/ LQFP176
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP (24 x 24 mm)
LQFP208
instructions (28 x 28 mm)
Memories
• 2 Mbytes of Flash memory with read-while- • 1.62 to 3.6 V application supply and I/Os
write support • POR, PDR, PVD and BOR
• 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. • Dedicated USB power embedding a 3.3 V
64 Kbytes of ITCM RAM + 128 Kbytes of internal regulator to supply the internal PHYs
DTCM RAM for time critical routines), • Embedded regulator (LDO) with configurable
864 Kbytes of user SRAM, and 4 Kbytes of scalable output to supply the digital circuitry
SRAM in Backup domain
• Voltage scaling in Run and Stop mode (6
• Dual mode Quad-SPI memory interface configurable ranges)
running up to 133 MHz
• Backup regulator (~0.9 V)
• Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM, • Voltage reference for analog peripheral/VREF+
SDRAM/LPSDR SDRAM, NOR/NAND Flash • Low-power modes: Sleep, Stop, Standby and
memory clocked up to 100 MHz in VBAT supporting battery charging
Synchronous mode
• CRC calculation unit Low-power consumption
• VBAT battery operating mode with charging
Security capability
• ROP, PC-ROP, active tamper, secure firmware • CPU and domain power state monitoring pins
upgrade support, Secure access mode • 2.95 µA in Standby mode (Backup SRAM OFF,
RTC/LSE ON)
General-purpose input/outputs
• Up to 168 I/O ports with interrupt capability Clock management
• Internal oscillators: 64 MHz HSI, 48 MHz
Reset and power management HSI48, 4 MHz CSI, 32 kHz LSI
• 3 separate power domains which can be • External oscillators: 4-48 MHz HSE,
independently clock-gated or switched off: 32.768 kHz LSE
– D1: high-performance capabilities • 3× PLLs (1 for the system clock, 2 for kernel
– D2: communication peripherals and timers clocks) with Fractional mode
– D3: reset/clock control/power management
April 2019 DS12117 Rev 7 1/356

This is information on a product in full production. www.st.com
STM32H753xI
Interconnect matrix • Chrom-ART graphical hardware Accelerator™

(DMA2D) to reduce CPU load
• 3 bus matrices (1 AXI and 2 AHB)
• Hardware JPEG Codec
• Bridges (5× AHB2-APB, 2× AXI2-AHB)
4 DMA controllers to unload the CPU Up to 22 timers and watchdogs

• 1× high-speed master direct memory access • 1× high-resolution timer (2.1 ns max
controller (MDMA) with linked list support resolution)
• 2× dual-port DMAs with FIFO • 2× 32-bit timers with up to 4 IC/OC/PWM or

pulse counter and quadrature (incremental)
• 1× basic DMA with request router capabilities encoder input (up to 240 MHz)
Up to 35 communication peripherals • 2× 16-bit advanced motor control timers (up to
240 MHz)
• 4× I2Cs FM+ interfaces (SMBus/PMBus)
• 10× 16-bit general-purpose timers (up to
• 4× USARTs/4x UARTs (ISO7816 interface, 240 MHz)
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
• 5× 16-bit low-power timers (up to 240 MHz)
• 6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external • 2× watchdogs (independent and window)
clock, 1x I2S in LP domain (up to 150 MHz) • 1× SysTick timer
• 4x SAIs (serial audio interface) • RTC with sub-second accuracy and hardware
• SPDIFRX interface calendar
• SWPMI single-wire protocol master I/F Cryptographic acceleration

• MDIO Slave interface
• AES 128, 192, 256, TDES,
• 2× SD/SDIO/MMC interfaces (up to 125 MHz)
• HASH (MD5, SHA-1, SHA-2), HMAC
• 2× CAN controllers: 2 with CAN FD, 1 with
• True random number generators
time-triggered CAN (TT-CAN)
• 2× USB OTG interfaces (1FS, 1HS/FS) crystal- Debug mode
less solution with LPM and BCD
• SWD & JTAG interfaces
• Ethernet MAC interface with DMA controller
• 4-Kbyte Embedded Trace Buffer
• HDMI-CEC
• 8- to 14-bit camera interface (up to 80 MHz) 96-bit unique ID
11 analog peripherals All packages are ECOPACK®2 compliant

• 3× ADCs with 16-bit max. resolution (up to 36 Table 1. Device summary
channels, up to 3.6 MSPS) Reference Part number
• 1× temperature sensor STM32H753VI, STM32H753ZI,
• 2× 12-bit D/A converters (1 MHz) STM32H753xI STM32H753II, STM32H753BI,
STM32H753XI, STM32H753AI
• 2× ultra-low-power comparators
• 2× operational amplifiers (7.3 MHz bandwidth)
• 1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
Graphics
• LCD-TFT controller up to XGA resolution
2/356 DS12117 Rev 7

STM32H753xI Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2 Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 33
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 33
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 33
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Contents STM32H753xI
3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 37
3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.26 JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.27 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.28 Cryptographic acceleration (CRYP and HASH) . . . . . . . . . . . . . . . . . . . . 40
3.29 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.29.1 High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.29.2 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.3 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.4 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 44
3.29.6 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.7 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.30 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 45
3.31 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.32 Universal synchronous/asynchronous receiver transmitter (USART) . . . 46
3.33 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47
3.34 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 48
3.35 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.36 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.37 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 49
3.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 50
3.39 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 50
3.40 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 50
3.41 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 51
3.42 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 51
3.43 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.44 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6 Electrical characteristics (rev Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 108
6.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 109
6.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 136
6.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 177
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Contents STM32H753xI
6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

6.3.24 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.27 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 185
6.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 188
6.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 189
6.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.3.32 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.3.33 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7 Electrical characteristics (rev V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

7.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 211
7.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
7.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
7.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 216
7.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 217
7.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 231
7.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 236
7.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 244
7.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
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7.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

7.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
7.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
7.3.21 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
7.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 290
7.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.3.24 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
7.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
7.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
7.3.27 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 294
7.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 296
7.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 299
7.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 300
7.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
7.3.32 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

8.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
8.2 TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
8.4 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
8.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
8.8 TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
8.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
8.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
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List of tables STM32H753xI
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32H753xI features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4. DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 8. Pin/ball definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 9. Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 10. Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 11. Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 12. Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 13. Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 14. Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 15. Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 16. Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 17. Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 18. Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 19. Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 23. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 24. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 25. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 108
Table 26. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 27. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 28. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
running from Flash memory, cache ON, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
running from Flash memory, cache OFF, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 32. Typical consumption in Run mode and corresponding performance
versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 33. Typical current consumption batch acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 34. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 114
Table 35. Typical and maximum current consumption in Stop mode, regulator ON. . . . . . . . . . . . . 115
Table 36. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 115
Table 37. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 116
Table 38. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 39. Peripheral current consumption in Stop, Standby and VBAT mode . . . . . . . . . . . . . . . . . 123
Table 40. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 41. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 42. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 43. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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Table 45. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Table 46. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 47. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 48. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 49. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 50. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 51. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 52. Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 134
Table 53. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 54. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 55. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 56. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 57. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 58. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 59. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 60. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 140
Table 61. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 141
Table 62. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 63. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 64. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 148
Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 148
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 149
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 150
Table 69. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 70. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 151
Table 71. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 72. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 153
Table 73. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 74. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 75. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 76. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 77. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 78. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 79. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 80. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 81. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 82. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 83. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 84. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 85. Dynamics characteristics: Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 86. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 87. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 88. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 89. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 90. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 91. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 92. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 93. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 94. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 95. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 96. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
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Table 97. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Table 98. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 99. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 100. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 101. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 102. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 103. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 104. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 105. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 106. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 107. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 108. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 109. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 200
Table 110. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 201
Table 111. USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 112. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 113. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 114. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 115. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 116. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 117. Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 118. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 119. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 121. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 122. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 123. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 124. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 216
Table 125. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 126. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 127. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
running from ITCM, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
running from Flash memory, cache ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
running from Flash memory, cache OFF,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 131. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 132. Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 222
Table 133. Typical and maximum current consumption in Sleep mode, LDO regulator. . . . . . . . . . . 223
Table 134. Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 135. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 224
Table 136. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 137. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 138. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 140. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 142. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
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Table 143. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Table 144. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 145. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 146. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 147. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 148. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 149. Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 241
Table 150. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 151. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 152. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 153. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 154. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 155. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 156. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 157. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 248
Table 158. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 249
Table 159. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 160. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 161. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 162. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 255
Table 163. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 255
Table 164. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 257
Table 165. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 257
Table 166. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 167. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 259
Table 168. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 169. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 260
Table 170. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 171. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 172. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 173. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 174. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 175. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 176. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 177. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 178. SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 179. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 180. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 181. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 182. Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 183. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 184. Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 185. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 186. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 187. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 188. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 189. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 190. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 191. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 192. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 193. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 194. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
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Table 195. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Table 196. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 197. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 198. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 199. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 200. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 201. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 202. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 203. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 204. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Table 205. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Table 206. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 207. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Table 208. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 314
Table 209. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 315
Table 210. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Table 211. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 318
Table 212. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 213. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 214. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 215. Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Table 216. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Table 217. TFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Table 218. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 327
Table 219. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table 220. UFBGA169 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Table 223. UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Table 224. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 344
Table 225. TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 226. TFBGA240+25 recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . 348
Table 228. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
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STM32H753xI List of figures
List of figures
Figure 1. STM32H753xI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 2. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3. STM32H753xI bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 5. TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 7. UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 9. UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10. LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 11. TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 12. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 13. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 14. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 15. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 16. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 18. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 21. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 22. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 147
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 149
Figure 25. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 26. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 27. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 28. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 29. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 30. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 31. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 32. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 33. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 161
Figure 34. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 162
Figure 35. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 36. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 37. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 38. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 39. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 40. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 41. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 173
Figure 42. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 173
Figure 43. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 44. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 45. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 46. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 47. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 48. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
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List of figures STM32H753xI
Figure 49. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 50. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 51. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 52. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 53. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 54. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 55. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 56. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 57. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 58. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 59. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 60. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 61. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 62. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 63. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 64. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 65. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 66. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 67. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 68. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 69. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 70. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 71. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 72. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 73. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 74. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 75. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 254
Figure 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 256
Figure 78. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 79. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 80. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 81. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 82. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 83. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 84. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 85. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 270
Figure 86. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 271
Figure 87. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 88. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 89. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 90. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 91. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 92. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 93. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 285
Figure 94. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 285
Figure 95. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 96. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 97. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 98. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 99. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 100. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
14/356 DS12117 Rev 7

STM32H753xI List of figures
Figure 101. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Figure 102. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 103. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 104. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 105. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 106. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 107. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 108. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 109. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 110. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 111. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 112. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 113. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 114. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 115. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Figure 116. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 117. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 118. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 119. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 120. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 121. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 122. TFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 123. TFBGA100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 124. TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Figure 126. LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Figure 127. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 128. UFBGA169 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 129. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Figure 136. UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Figure 137. UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Figure 138. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 139. TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 140. TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 141. TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 348
DS12117 Rev 7 15/356

15
Introduction STM32H753xI
1 Introduction
This document provides information on STM32H53xI microcontrollers, such as description,

functional overview, pin assignment and definition, electrical characteristics, packaging, and
ordering information.
This document should be read in conjunction with the STM32H53xI reference manual
(RM0433), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, please refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
16/356 DS12117 Rev 7

STM32H753xI Description
2 Description
STM32H753xI devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC
core operating at up to 480 MHz. The Cortex® -M7 core features a floating point unit (FPU)
which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-
processing instructions and data types. STM32H753xI devices support a full set of DSP
instructions and a memory protection unit (MPU) to enhance application security.
STM32H753xI devices incorporate high-speed embedded memories with a dual-bank Flash
memory of 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to
864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of
enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB
bus matrix and a multi layer AXI interconnect supporting internal and external memory
access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers, a true random number generator (RNG), and a cryptographic
acceleration cell. The devices support four digital filters for external sigma-delta modulators
(DFSDM). They also feature standard and advanced communication interfaces.
• Standard peripherals
– Four I2Cs
– Four USARTs, four UARTs and one LPUART
– Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
– Four SAI serial audio interfaces
– One SPDIFRX interface
– One SWPMI (Single Wire Protocol Master Interface)
– Management Data Input/Output (MDIO) slaves
– Two SDMMC interfaces
– A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
– One FDCAN plus one TT-FDCAN interface
– An Ethernet interface
– Chrom-ART Accelerator™
– HDMI-CEC
• Advanced peripherals including
– A flexible memory control (FMC) interface
– A Quad-SPI Flash memory interface
– A camera interface for CMOS sensors
– An LCD-TFT display controller
– A JPEG hardware compressor/decompressor
Refer to Table 2: STM32H753xI features and peripheral counts for the list of peripherals
available on each part number.
DS12117 Rev 7 17/356

53
Description STM32H753xI
STM32H753xI devices operate in the –40 to +85 °C temperature range from a 1.62 to 3.6 V
power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages
except LQFP100 to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H753xI devices are offered in 8 packages ranging from 100 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H753xI microcontrollers suitable for a wide range of
applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
• Mobile applications, Internet of Things
• Wearable devices: smart watches.
Figure 1 shows the device block diagram.
18/356 DS12117 Rev 7

Table 2. STM32H753xI features and peripheral counts

STM32H753 STM32H753 STM32H753 STM32H753 STM32H753 STM32H753
Peripherals
VI ZI AI II BI XI
Flash memory in Kbytes 2 x 1 Mbyte

SRAM mapped
512
onto AXI bus
SRAM1 (D2
128
domain)
SRAM2 (D2
SRAM in Kbytes 128
domain)
SRAM3 (D2
32
domain)
SRAM4 (D3
64
domain)
ITCM RAM
64
(instruction)
TCM RAM in Kbytes
DTCM RAM
128
(data)
Backup SRAM (Kbytes) 4
FMC Yes
GPIOs 82 114 131 140 168
Quad-SPI Yes
Ethernet Yes
High-resolution 1
General-
10
purpose
Timers Advanced-
2
control (PWM)
Basic 2
Low-power 5
Random number generator Yes
Cryptographic accelerator Yes
DS12117 Rev 7 19/356

53
Table 2. STM32H753xI features and peripheral counts (continued)

STM32H753 STM32H753 STM32H753 STM32H753 STM32H753 STM32H753
Peripherals
VI ZI AI II BI XI
SPI / I2S 6/3(1)

I2C 4
USART/UART/ 4/4
LPUART /1
SAI 4
SPDIFRX 4 inputs
Communication
SWPMI Yes
interfaces
MDIO Yes
SDMMC 2
FDCAN/TT-
1/1
FDCAN
USB OTG_FS Yes
USB OTG_HS Yes
Ethernet and camera interface Yes
LCD-TFT Yes
JPEG Codec Yes
Chrom-ART Accelerator™ (DMA2D) Yes
16-bit ADCs 3
Number of channels Up to 36
12-bit DAC Yes
Number of channels 2
Comparators 2
Operational amplifiers 2
DFSDM Yes
Maximum CPU frequency 480MHz(2)(3)/400 MHz
1.71 to
Operating voltage 1.62 to 3.6 V(5)
3.6 V(4)
Ambient temperatures: –40 up to +85 °C(6)
Operating temperatures
Junction temperature: –40 to + 125 °C
LQFP176
LQFP100 UFBGA169 TFBGA240+
Package LQFP144 UFBGA176+ LQFP208
TFBGA100(7) (7)
25
25
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
2. The maximum CPU frequency of 480 MHz can be obtained on devices revision V.
3. The product junction temperature must be kept within the –40 to +105 °C temperature range.
4. Since the LQFP100 package does not feature the PDR_ON pin (tied internally to VDD), the minimum VDD value for this
package is 1.71 V.
20/356 DS12117 Rev 7

5. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and
connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage
detector enabled.
6. The product junction temperature must be kept within the –40 to +125 °C temperature range.
7. This package is under development. Please contact STMicroelectronics for details.
DS12117 Rev 7 21/356

53
Figure 1. STM32H753xI block diagram

DP, DM, STP,
MII / RMII SDMMC_
To APB1-2 NXT,ULPI:CK DP, DM, ID,
MDIO D[7:0],
peripherals , D[7:0], DIR, VBUS
as AF CMD, CK as AF
ID, VBUS
AHB1 (200MHz)
I-TCM D-TCM D-TCM
64KB 64KB 64KB PHY PHY
ETHER
DMA1 DMA2 SDMMC2 OTG_HS OTG_FS
MAC
AHBP
AXI/AHB12 (200MHz) 8 Stream 8 Stream DMA/ DMA/ DMA/

JTRST, JTDI, FIFO
Arm CPU FIFOs FIFOs FIFO FIFO FIFO
JTCK/SWCLK JTAG/SW
Cortex-M7 1 MB FLASH
JTDO/SWD, JTDO AXIM
400 MHz
TRACECK ETM
1 MB FLASH 32-bit AHB BUS-MATRIX
TRACED[3:0] I-Cache D-Cache
AHB1 (200MHz)
16KB 16KB 512 KB AXI DMA
AHBS SRAM Mux1 SRAM1 SRAM2 SRAM3
128 KB 128 KB 32 KB
AHB4 (200MHz)
AHB2 (200MHz)
MDMA
16 Streams FMC
64-bit AXI BUS-MATRIX

FIFO RNG ADC1
FMC_signals Up to 20 analog inputs
HASH common to ADC1 & 2
CHROM-ART ADC2
FIFO Quad-SPI
(DMA2D) 3DES/AES AHB/APB
CLK, CS,D[7:0]
LCD_R[7:0], LCD_G[7:0], LCD-TFT FIFO 32b
TIM2 4 channels, ETR as AF
LCD_B[7:0], LCD_HSYNC, AXI/AHB34 (200MHz)
LCD_VSYNC, LCD_DE, LCD_CLK TIM6 16b TIM3 4 channels, ETR as AF
AHB3 16b
WWDG JPEG TIM7 16b TIM4
16b 4 channels, ETR as AF
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir AHB/APB
SDMMC_D0dir, SDMMC_D2dir SWPMI
SDMMC1 FIFO 32b
TIM5 4 channels
CMD, CMDdir, CK, Ckin,
CKio as AF
16b
TIM12 2 channels as AF
Delay block AHB2 (200MHz) 16b

TIM13 1 channel as AF
TIM14 1 channel as AF
HSYNC, VSYNC, PIXCLK, D[13:0] DCMI 16b
AHB/APB smcard
HRTIM1_CH[A..E]x RX, TX, SCK, CTS,
USART2
HRTIM1_FLT[5:1], HRTIM1 irDA RTS as AF
HRTIM1_FLT[5:1]_in, SYSFLT smcard RX, TX, SCK
DFSDM1_CKOUT, USART3 CTS, RTS as AF
DFSDM1_DATAIN[0:7],
DFSDM1 irDA
DFSDM1_CKIN[0:7] UART4 RX, TX as AF
FIFO FIFO FIFO
SD, SCK, FS, MCLK, D/CK[4:1] as SAI3

AF
UART5 RX, TX as AF
SD, SCK, FS, MCLK, CK[2:1] as AF SAI2
UART7 RX, TX as AF
A P B 10 MHz
SD, SCK, FS, MCLK, D[3:1], SAI1 3
CK[2:1] as AF UART8 RX, TX as AF
MOSI, MISO, SCK, NSS /
SPI5
APB2 100 MHz (max)
MOSI, MISO, SCK, NSS as AF SPI2/I2S2 SDO, SDI, CK, WS, MCK, as AF
1 compl. chan.(TIM17_CH1N), MOSI, MISO, SCK, NSS /
TIM17 SPI3/I2S3
APB1 100 MHz (max)
1 chan. (TIM17_CH1, BKIN as AF SDO, SDI, CK, WS, MCK, as AF

1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF TIM16 SCL, SDA, SMBAL as AF
I2C1/SMBUS
10 KB SRAM
Digital filter
2 compl. chan.(TIM15_CH1[1:2]N), TIM15 DMA
AHB4
2 chan. (TIM_CH15[1:2], BKIN as AF Mux2 I2C2/SMBUS SCL, SDA, SMBAL as AF

AHB4
AHB4
MOSI, MISO, SCK, NSS as AF SPI4 AHB4

BDMA DAP
I2C3/SMBUS SCL, SDA, SMBAL as AF
MOSI, MISO, SCK, NSS /
SPI1/I2S1
SDO, SDI, CK, WS, MCK, as AF MDIOs MDC, MDIO
AHB4
smcard
RX, TX, SCK, CTS, RTS as AF
irDA USART6 32-bit AHB BUS-MATRIX RAM TT-FDCAN1 TX, RX
FIFO
smcard I/F
RX, TX, SCK, CTS, RTS as AF
irDA USART1 FDCAN2 TX, RX
AHB4 (200MHz)
4 compl. chan. (TIM1_CH1[1:4]N), TIM1/PWM

4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF 16b USBCR
4 compl. chan.(TIM8_CH1[1:4]N),
HSEM
4 chan. (TIM8_CH1[1:4], ETR, BKIN as TIM8/PWM 64 KB SRAM 4 KB BKP SPDIFRX1 IN[1:4] as AF
16b CRC RAM
AF
Up to 17 analog inputs HDMI-CEC CEC as AF
common to ADC1 and 2 ADC3
DAC DAC_OUT1, DAC_OUT2 as AF
AHB4
PA..J[15:0] GPIO PORTA.. J

LPTIM1_IN1, LPTIM1_IN2,
PK[7:0] LPTIM1 16b LPTIM1_OUT as AF
GPIO PORTK RCC
Reset &
AHB4 (200MHz)
OPAMPx_VINM
control OPAMP1&2
OPAMPx_VINP
@VDD33 OPAMPx_VOUT as AF
SD, SCK, FS, MCLK,
D[3;1], CK[2:1] as AF
SAI4 VDD12 BBgen + POWER MNGT
VDDMMC33 = 1.8 to 3.6V
PWRCTRL
COMPx_INP, COMPx_INM, COMP1&2 Voltage VDDUSB33 = 3.0 to 3.6 V

COMPx_OUT as AF VDD = 1.8 to 3.6 V
regulator VSS
LPTIM5_OUT as AF LPTIM5 3.3 to 1.2V VCAP
VREF AHB/APB
LPTIM4_OUT as AF LPTIM4 @VSW
SYSCFG
APB4 100 MHz (max)
LPTIM3 XTAL 32 kHz OSC32_IN

LPTIM3_OUT as AF OSC32_OUT
EXTI WKUP
LS
RTC
(max)
SCL, SDA, SMBAL as AF I2C4 RTC_TS

IWDG
(max)
MOSI, MISO, SCK, NSS / Backup registers RTC_TAMP[1:3]

SPI6/I2S6 RTC_OUT
MHz
SDO, SDI, CK, WS, MCK, as AF AWU

LS
Temperature RTC_REFIN
MHz
sensor
100100
RX, TX, CK, CTS, RTS as AF LPUART1 @VDD

APB4
LPTIM2_IN1, LPTIM2_IN2 and HS RC VBAT = 1.8 to 3.6 V

LPTIM2 CSI
APB4
LPTIM2_OUT HSI48 @VDD

LS RC
HSI XTAL OSC OSC_IN
LSI PLL1+PLL2+PLL3 4- 48 MHz OSC_OUT
WDG_LS_D1
@VDD
SUPPLY SUPERVISION
POR VDDA, VSSA
reset POR/PDR/BOR NRESET
Int WKUP[5:0]
PVD
MSv40887V15
22/356 DS12117 Rev 7

STM32H753xI Functional overview
3 Functional overview
3.1 Arm® Cortex®-M7 with FPU

The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
• Six-stage dual-issue pipeline
• Dynamic branch prediction
• Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
• 64-bit AXI interface
• 64-bit ITCM interface
• 2x32-bit DTCM interfaces
The following memory interfaces are supported:
• Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
• Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
• AXI Bus interface to optimize Burst transfers
• Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H753xI family.
Note: Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
3.2 Memory protection unit (MPU)

The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
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Functional overview STM32H753xI
3.3 Memories
3.3.1 Embedded Flash memory

The STM32H753xI devices embed 2 Mbytes of Flash memory that can be used for storing
programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
• One Flash word (8 words, 32 bytes or 256 bits)
• 10 ECC bits.
The Flash memory is divided into two independent banks. Each bank is organized as
follows:
• 1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes
(4 K Flash memory words)
• 128 Kbytes of System Flash memory from which the device can boot
• 2 Kbytes (64 Flash words) of user option bytes for user configuration
3.3.2 Secure access mode

In addition to other typical memory protection mechanism (RDP, PCROP), STM32H753xI
devices introduce the Secure access mode, a new enhanced security feature. This mode
allows developing user-defined secure services by ensuring, on the one hand code and
data protection and on the other hand code safe execution.
Two types of secure services are available:
• STMicroelectronics Root Secure Services:
These services are embedded in System memory. They provide a secure solution for
firmware and third-party modules installation. These services rely on cryptographic
algorithms based on a device unique private key.
• User-defined secure services:
These services are embedded in user Flash memory. Examples of user secure
services are proprietary user firmware update solution, secure Flash integrity check or
any other sensitive applications that require a high level of protection.
The secure firmware is embedded in specific user Flash memory areas configured
through option bytes.
Secure services are executed just after a reset and preempt all other applications to
guarantee protected and safe execution. Once executed, the corresponding code and data
are no more accessible.
The above secure services are available only for Cortex®-M7 core operating in Secure
access mode. The other masters cannot access the option bytes involved in Secure access
mode settings or the Flash secured areas.
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3.3.3 Embedded SRAM

All devices feature:
• 512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
• SRAM1 mapped on D2 domain: 128 Kbytes
• 4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or VBAT mode.
• RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. either They can be accessed
either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave
of the CPU(AHBP):
– 64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
– 128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
Error code correction (ECC)

Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
• 7 ECC bits are added per 32-bit word.
• 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
3.4 Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
• All Flash address space
• All RAM address space: ITCM, DTCM RAMs and SRAMs
• The System memory bootloader
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The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5 Power supply management
3.5.1 Power supply scheme

STM32H53xI power supply voltages are the following:
• VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
• VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
• VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
• VDD33USB and VDD50USB:
VDD50USB can be supplied through the USB cable to generate the VDD33USB via the
USB internal regulator. This allows supporting a VDD supply different from 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
• VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
• VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and
ODEN bit in the SYSCFG_PWRCR register. The VCORE domain is split into the
following power domains that can be independently switch off.
– D1 domain containing some peripherals and the Cortex®-M7 core.
– D2 domain containing a large part of the peripherals.
– D3 domain containing some peripherals and the system control.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 2):
• When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must
remain below VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
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Figure 2. Power-up/power-down sequence
3.6
VDDX(1)
VDD
VBOR0
0.3
Power-on Operating mode Power-down time
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB.
3.5.2 Power supply supervisor

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
• Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in Reset mode when VDD is below this threshold,
• Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
• Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.
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3.5.3 Voltage regulator

The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
• Run mode (VOS0 to VOS3)
– Scale 0: boosted performance (available only with LDO regulator)
– Scale 1: high performance
– Scale 2: medium performance and consumption
– Scale 3: optimized performance and low-power consumption
• Stop mode (SVOS3 to SVOS5)
– Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
– Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible
through GPIO or asynchronous interrupt.
3.6 Low-power strategy

There are several ways to reduce power consumption on STM32H753xI:
• Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode and by individually clock gating the peripherals that are not used.
• Save power consumption when the CPU is idle, by selecting among the available low-
power mode according to the user application needs. This allows achieving the best
compromise between short startup time, low-power consumption, as well as available
wakeup sources.
The devices feature several low-power modes:
• CSleep (CPU clock stopped)
• CStop (CPU sub-system clock stopped)
• DStop (Domain bus matrix clock stopped)
• Stop (System clock stopped)
• DStandby (Domain powered down)
• Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
the Cortex®-Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
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Table 3. System vs domain low-power mode

D1 domain power D2 domain power D3 domain power
System power mode
mode mode mode
Run DRun/DStop/DStandby DRun/DStop/DStandby DRun

Stop DStop/DStandby DStop/DStandby DStop
Standby DStandby DStandby DStandby
3.7 Reset and clock controller (RCC)

The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
3.7.1 Clock management

The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
• Internal oscillators:
– 64 MHz HSI clock
– 48 MHz RC oscillator
– 4 MHz CSI clock
– 32 kHz LSI clock
• External oscillators:
– HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
– LSE clock: 32.768 kHz
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
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3.7.2 System reset sources

Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
• Power-on reset (pwr_por_rst)
• Brownout reset
• Low level on NRST pin (external reset)
• Window watchdog
• Independent watchdog
• Software reset
• Low-power mode security reset
• Exit from Standby
3.8 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.9 Bus-interconnect matrix

The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
interconnecting bus masters with bus slaves (see Figure 3).
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Figure 3. STM32H753xI bus matrix
STM32H753xI
AHBS
CPU ITCM
Cortex-M7 64 Kbyte
I$ D$ DTCM Ethernet SDMMC2 USBHS1
16KB 16KB 128 Kbyte DMA1 DMA2 USBHS2
MAC
AXIM
AHBP
DMA1_PERIPH
DMA2_PERIPH
DMA1_MEM
DMA2_MEM
SDMMC1 MDMA DMA2D LTDC
D1-to-D2 AHB
SRAM1 128
APB3 Kbyte
SRAM2 128
AHB3 Kbyte
SRAM3
32 Kbyte
Flash A
Up to 1 Mbyte
AHB1
DS12117 Rev 7
Flash B
Up to 1 Mbyte
AHB2
AXI SRAM
512 Kbyte
APB1
QSPI
APB2
FMC
64-bit AXI bus matrix 32-bit AHB bus matrix

D1 domain D2 domain
D2-to-D1 AHB
D2-to-D3 AHB
D1-to-D3 AHB
BDMA
32-bit AHB bus matrix
Functional overview
D3 domain
Legend
AHB4 APB4
TCM AHB
32-bit bus AXI APB SRAM4
64-bit bus Master interface 64 Kbyte
Bus multiplexer Slave interface Backup

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SRAM
4 Kbyte
MSv46613V2
3.10 DMA controllers

The devices feature four DMA instances to unload CPU activity:
• A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
access Cortex®-M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
• Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
• One basic DMA (BDMA) located in D3 domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing managing the
DMA requests with a high flexibility, maximizing the number of DMA requests that run
concurrently, as well as generating DMA requests from peripheral output trigger or DMA
event.
3.11 Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphical accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
• Rectangle filling with a fixed color
• Rectangle copy
• Rectangle copy with pixel format conversion
• Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also
supports block based YCbCr to handle JPEG decoder output.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
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3.12 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines
of the Cortex®-M7 with FPU core.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13 Extended interrupt and event controller (EXTI)

The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events
and 61 direct events .
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.14 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
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3.15 Flexible memory controller (FMC)

The FMC controller main features are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-,16-,32-bit data bus width
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• Read FIFO for SDRAM controller
• The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
3.16 Quad-SPI memory interface (QUADSPI)

All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and
double datarate operations.
It can operate in any of the following modes:
• Direct mode through registers
• External Flash status register polling mode
• Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data
accesses are supported as well as code execution.
The opcode and the frame format are fully programmable.
3.17 Analog-to-digital converters (ADCs)

The STM32H753xI devices embed three analog-to-digital converters, which resolution can
be configured to 16, 14, 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in the Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
converted values to a destination location without any software action.
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In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
3.18 Temperature sensor

STM32H753xI devices embed a temperature sensor that generates a voltage (VTS) that
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from − 40 up to +125 °C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.19 VBAT operation

The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the
voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched
when the PDR detects that VDD dropped below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by VDD, in which case, the VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
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3.20 Digital-to-analog converters (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
• two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• dual DAC channel independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• external triggers for conversion
• input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
3.21 Ultra-low-power comparators (COMP)

STM32H753xI devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
• An external I/O
• A DAC output channel
• An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.22 Operational amplifiers (OPAMP)

STM32H753xI devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
• PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
• One positive input connected to DAC
• Output connected to internal ADC
• Low input bias current down to 1 nA
• Low input offset voltage down to 1.5 mV
• Gain bandwidth up to 7.3 MHz
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The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
3.23 Digital filter for sigma-delta modulators (DFSDM)

The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
• 8 multiplexed input digital serial channels:
– configurable SPI interface to connect various SD modulator(s)
– configurable Manchester coded 1 wire interface support
– PDM (Pulse Density Modulation) microphone input support
– maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
– clock output for SD modulator(s): 0..20 MHz
• alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
– internal sources: ADC data or memory data streams (DMA)
• 4 digital filter modules with adjustable digital signal processing:
– Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
– integrator: oversampling ratio (1..256)
• up to 24-bit output data resolution, signed output data format
• automatic data offset correction (offset stored in register by user)
• continuous or single conversion
• start-of-conversion triggered by:
– software trigger
– internal timers
– external events
– start-of-conversion synchronously with first digital filter module (DFSDM0)
• analog watchdog feature:
– low value and high value data threshold registers
– dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
– input from final output data or from selected input digital serial channels
– continuous monitoring independently from standard conversion
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• short circuit detector to detect saturated analog input values (bottom and top range):
– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
– monitoring continuously each input serial channel
• break signal generation on analog watchdog event or on short circuit detector event
• extremes detector:
– storage of minimum and maximum values of final conversion data
– refreshed by software
• DMA capability to read the final conversion data
• interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
• “regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority
Table 4. DFSDM implementation

DFSDM features DFSDM1
Number of filters 4
Number of input
8
transceivers/channels
Internal ADC parallel input X
Number of external triggers 16
Regular channel information in
X
identification register
3.24 Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12- or 14-bit
• Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
• Supports Continuous mode or Snapshot (a single frame) mode
• Capability to automatically crop the image
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3.25 LCD-TFT controller

The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
• 2 display layers with dedicated FIFO (64x64-bit)
• Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
• Up to 8 input color formats selectable per layer
• Flexible blending between two layers using alpha value (per pixel or constant)
• Flexible programmable parameters for each layer
• Color keying (transparency color)
• Up to 4 programmable interrupt events
• AXI master interface with burst of 16 words
3.26 JPEG Codec (JPEG)

The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 10918-
1 specification. It provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features are as follows:
• 8-bit/channel pixel depths
• Single clock per pixel encoding and decoding
• Support for JPEG header generation and parsing
• Up to four programmable quantization tables
• Fully programmable Huffman tables (two AC and two DC)
• Fully programmable minimum coded unit (MCU)
• Encode/decode support (non simultaneous)
• Single clock Huffman coding and decoding
• Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
• Support for single greyscale component
• Ability to enable/disable header processing
• Fully synchronous design
• Configuration for High-speed decode mode
3.27 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
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3.28 Cryptographic acceleration (CRYP and HASH)

The devices embed a cryptographic processor that supports the advanced cryptographic
algorithms usually required to ensure confidentiality, authentication, data integrity and non-
repudiation when exchanging messages with a peer:
• Encryption/Decryption
– DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
– AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (Counter
mode) chaining algorithms, 128, 192 or 256-bit key
• Universal HASH
– SHA-1 and SHA-2 (secure HASH algorithms)
– MD5
– HMAC
The cryptographic accelerator supports DMA request generation.
3.29 Timers and watchdogs

The devices include one high-resolution timer, two advanced-control timers, ten general-
purpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 5 compares the features of the advanced-control, general-purpose and basic timers.
Table 5. Timer feature comparison

Max
Max
DMA Capture/ Comple- timer
Timer Counter Counter Prescaler interface
Timer request compare mentary clock
type resolution type factor clock
generation channels output (MHz)
(MHz) (1)
/1 /2 /4
High-
(x2 x4 x8
resolution HRTIM1 16-bit Up Yes 10 Yes 480 480
x16 x32,
timer
with DLL)
Any
Up, integer
Advanced TIM1,
16-bit Down, between 1 Yes 4 Yes 120 240
-control TIM8
Up/down and
65536
40/356 DS12117 Rev 7

Table 5. Timer feature comparison (continued)

Max
Max
DMA Capture/ Comple- timer
Timer Counter Counter Prescaler interface
Timer request compare mentary clock
type resolution type factor clock
generation channels output (MHz)
(MHz) (1)
Any
Up, integer
TIM2,
32-bit Down, between 1 Yes 4 No 120 240
TIM5
Up/down and
65536
Any
Up, integer
TIM3,
16-bit Down, between 1 Yes 4 No 120 240
TIM4
Up/down and
65536
Any
integer
TIM12 16-bit Up between 1 No 2 No 120 240
and
General 65536
purpose Any
integer
TIM13,
16-bit Up between 1 No 1 No 120 240
TIM14
and
65536
Any
integer
TIM15 16-bit Up between 1 Yes 2 1 120 240
and
65536
Any
integer
TIM16,
16-bit Up between 1 Yes 1 1 120 240
TIM17
and
65536
Any
integer
TIM6,
Basic 16-bit Up between 1 Yes 0 No 120 240
TIM7
and
65536
LPTIM1,
Low- LPTIM2, 1, 2, 4, 8,
power LPTIM3, 16-bit Up 16, 32, 64, No 0 No 120 240
timer LPTIM4, 128
LPTIM5
1. The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
DS12117 Rev 7 41/356

53
3.29.1 High-resolution timer (HRTIM1)

The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
The HRTIM1 timer is made of a digital kernel clocked at 480 MHz The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, Burst mode
controller, Push-pull and Resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
42/356 DS12117 Rev 7

3.29.2 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (Edge- or Center-aligned modes)
• One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.29.3 General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32H753xI
devices (see Table 5 for differences).
• TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and
TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit
prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature 4 independent channels for input capture/output
compare, PWM or One-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
• TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
DS12117 Rev 7 43/356

53
3.29.4 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.29.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)

The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous / One-shot mode
• Selectable software / hardware input trigger
• Selectable clock source:
• Internal clock source: LSE, LSI, HSI or APB clock
• External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
• Programmable digital glitch filter
• Encoder mode
3.29.6 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.29.7 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.
3.29.8 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
• A 24-bit downcounter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.
44/356 DS12117 Rev 7

3.30 Real-time clock (RTC), backup SRAM and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Three anti-tamper detection pins with programmable filter.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
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53
3.31 Inter-integrated circuit interface (I2C)

STM32H753xI devices embed four I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and Master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
3.32 Universal synchronous/asynchronous receiver transmitter

(USART)
STM32H753xI devices have four embedded universal synchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7 and UART8). Refer to Table 6 for a summary of
USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
46/356 DS12117 Rev 7

All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
• Start bit detection
• Any received data frame
• A specific programmed data frame
• Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
Table 6. USART features

USART modes/features(1) USART1/2/3/6 UART4/5/7/8
Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode (Master/Slave) X -
Smartcard mode X -
Single-wire Half-duplex communication X X
IrDA SIR ENDEC block X X
LIN mode X X
Dual clock domain and wakeup from low power mode X X
Receiver timeout interrupt X X
Modbus communication X X
Auto baud rate detection X X
Driver Enable X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X
Tx/Rx FIFO size 16
1. X = supported.
3.33 Low-power universal asynchronous receiver transmitter

(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
DS12117 Rev 7 47/356

53
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
• Start bit detection
• Any received data frame
• A specific programmed data frame
• Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.34 Serial peripheral interface (SPI)/inter- integrated sound

interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full-
duplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in Simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in Master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8-
bit embedded Rx and Tx FIFOs with DMA capability.
3.35 Serial audio interfaces (SAI)

The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo
or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An
SPDIF output is available when the audio block is configured as a transmitter. To bring this
level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks.
Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
48/356 DS12117 Rev 7

3.36 SPDIFRX Receiver Interface (SPDIFRX)

The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
• Up to 4 inputs available
• Automatic symbol rate detection
• Maximum symbol rate: 12.288 MHz
• Stereo stream from 32 to 192 kHz supported
• Supports Audio IEC-60958 and IEC-61937, consumer applications
• Parity bit management
• Communication using DMA for audio samples
• Communication using DMA for control and user channel information
• Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.37 Single wire protocol master interface (SWPMI)

The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
• Full-duplex communication mode
• automatic SWP bus state management (active, suspend, resume)
• configurable bitrate up to 2 Mbit/s
• automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
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53
3.38 Management Data Input/Output (MDIO) slaves

The devices embed an MDIO slave interface it includes the following features:
• 32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
– 32 x 16-bit firmware read/write, MDIO read-only output data registers
– 32 x 16-bit firmware read-only, MDIO write-only input data registers
• Configurable slave (port) address
• Independently maskable interrupts/events:
– MDIO Register write
– MDIO Register read
– MDIO protocol error
• Able to operate in and wake up from Stop mode
3.39 SD/SDIO/MMC card host interfaces (SDMMC)

Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.40 Controller area network (FDCAN1, FDCAN2)

The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
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3.41 Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2
supports only full-speed operations. They both integrate the transceivers for full-speed
operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1
features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using
the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the
OTG 2.0 specification. They have software-configurable endpoint setting and supports
suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
• Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 9 bidirectional endpoints (including EP0)
• 16 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Battery Charging Specification Revision 1.2 support
• Internal FS OTG PHY support
• External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can
be clocked using the 60 MHz output.
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.42 Ethernet MAC interface with dedicated DMA controller (ETH)

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
DS12117 Rev 7 51/356

53
The devices include the following features:

• Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and
group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time
3.43 High-definition multimedia interface (HDMI)

- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.44 Debug infrastructure

The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
• Breakpoint debugging
• Code execution tracing
• Software instrumentation
• JTAG debug port
• Serial-wire debug port
• Trigger input and output
• Serial-wire trace port
• Trace port
• Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools.
The trace port performs data capture for logging and analysis.
52/356 DS12117 Rev 7

STM32H753xI Memory mapping
4 Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
DS12117 Rev 7 53/356

53
Pin descriptions STM32H753xI
5 Pin descriptions
Figure 4. LQFP100 pinout
BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VCAP
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 100-pins 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2_C 17 59 PD12
PC3_C 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VSS
VDD
PA4
PA5
PA6
PA7
PE11
PB11
MSv41918V4
1. The above figure shows the package top view.
54/356 DS12117 Rev 7

STM32H753xI Pin descriptions
Figure 5. TFBGA100 pinout
1 2 3 4 5 6 7 8 9 10
PC14-
A PC13 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13
OSC32_IN
PC15-
B VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12
OSC32_OUT
C PH0-OSC_IN VSS PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11
PH1-
D VDD PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10
OSC_OUT
E NRST PC2_C PE6 VSS VSS VSS VCAP PD1 PC9 PC7
F PC0 PC1 PC3_C VDDLDO VDD VDD33USB PDR_ON VCAP PC8 PC6
G VSSA PA0 PA4 PC4 PB2 PE10 PE14 PD15 PD11 PB15
H VDDA PA1 PA5 PC5 PE7 PE11 PE15 PD14 PD10 PB14
J VSS PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13
K VDD PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12
MSv46177V2
DS12117 Rev 7 55/356

102
PDR_ON
BOOT0
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
VDD
VDD
VDD
VSS
PG9
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
109
119
118
117
116
115
114
113
112
110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VCAP
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD33USB
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 144-pins 91 PG6
PF7 19 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2_C 28 81 PD12
PC3_C 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VDD
PA3
PA4
PA5
PA6
PA7
PF11
PE11
PB11
MSv41917V4
56/356 DS12117 Rev 7

Figure 7. UFBGA169 ballout
1 2 3 4 5 6 7 8 9 10 11 12 13
A PE4 PE2 VDD PI6 PB6 PI2 VDD PG10 PD5 VDD PC12 PC10 PI0
PC15-
B OSC32_ PE3 VSS VDDLDO PB8 PB4 PI3 PG11 PD6 VSS PC11 PA14 PI1
OUT
PC14-
C OSC32_ PE6 PE5 PDR_ON PB9 PB5 PG14 PG9 PD4 PD1 PA15 VSS VDD
IN
D VDD VSS PC13 PE1 PE0 PB7 PG13 PD7 PD3 PD0 PA13 VDDLDO VCAP
E PI11 PI7 VBAT PF1 PF3 BOOT0 PG15 PG12 PD2 PA10 PA9 PA8 PA12
F PI13 PI12 PF0 PF2 PF5 PF7 PB3 PG4 PC6 PC7 PC9 PC8 PA11
G VDD50_ VDD33_
VDD VSS PF4 PF6 PF9 NRST PF13 PE7 PG6 PG7 PG8
USB USB
PH0- PH1-
H OSC_ OSC_ PF10 PF8 PJ1 PA4 PF14 PE8 PG2 PG3 PG5 VSS VDD
IN OUT
J PC0 PC1 VSSA PJ0 PA7 PF15 PE9 PE14 PD11 PD13 PD15 PD14
PA0
K PC3_C PC2_C PH4 PA1 PA6 PC4 PG0 PE13 PH10 PH12 PD9 PD10 PD12
L VDDA VREF+ PH5 PA5 PB1 PB2 PG1 PE12 PB10 PH11 PB13 VSS VDD
M VDD VSS PH3 PB0 PF11 VSS PE10 PB11 VDDLDO VSS PD8 PB15
VSS
N PA2 PH2 PA3 VDD PC5 PF12 VDD PE11 PE15 VCAP VDD PB12 PB14
MSv45339V4
DS12117 Rev 7 57/356

102
PDR_ON
BOOT0
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
VDD
VDD
VDD
VDD
VSS
PG9
VSS
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PI7
PI6
PI5
PI4
PI3
PI2
PINOUT UNDER DEVELOPMENT
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1 132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8 7 126 VSS
PC13 8 125 VCAP
PC14-OSC32_IN 9 124 PA13
PC15-OSC32_OUT 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDD33USB
PF4 20 113 VSS
PF5 21 112 PG8
VSS 22 176-pins 111 PG7
VDD 23 110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
PF10 28 105 PD15
PH0-OSC_IN 29 104 PD14
PH1-OSC_OUT 30 103 VDD
NRST 31 102 VSS
PC0 32 101 PD13
PC1 33 100 PD12
PC2_C 34 99 PD11
PC3_C 35 98 PD10
VDD 36 97 PD9
VSSA 37 96 PD8
VREF+ 38 95 PB15
VDDA 39 94 PB14
PA0 40 93 PB13
PA1 41 92 PB12
PA2 42 91 VDD
PH2 43 90 VSS
PH3 44 89 PH12
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
PH4
PH5
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VDD
PH6
PH7
PH8
PH9
PH10
PA3
PA4
PA5
PA6
PA7
PF11
PE11
PB11
PH11
MSv41916V5
58/356 DS12117 Rev 7

Figure 9. UFBGA176+25 ballout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
C VBAT PI7 PI6 PI5 VDD PDR_ON VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11
D PC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10
PC14-
E OSC32_ PF0 PI10 PI11 PH13 PH14 PI0 PA9
IN
PC15-
F OSC32_ VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP PC9 PA8
OUT
PH0-
G VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
OSC_IN
PH1- VDD
H OSC_ PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS PG8 PC6
33USB
OUT
J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6
K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
L PF10 PF9 PF8 VSS PH11 PH10 PD15 PG2
M VSSA PC0 PC1 PC2_C PC3_C PB2 PG1 VSS VSS VCAP PH6 PH8 PH9 PD14 PD13
N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10
P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15
MSv41912V3
DS12117 Rev 7 59/356

102
PDR_ON
BOOT0
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
PJ15
PJ14
PJ13
PJ12
VDD
VDD
VDD
VDD
VSS
VSS
PG9
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PK7
PK6
PK5
PK4
PK3
PI7
PI6
PI5
PI4
PI3
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PE2 1 156 PI2
PE3 2 155 PI1
PE4 3 154 PI0
PE5 4 153 PH15
PE6 5 152 PH14
VBAT 6 151 PH13
PI8 7 150 VDD
PC13 8 149 VSS
PC14-OSC32_IN 9 148 VCAP
PC15-OSC32_OUT 10 147 PA13
PI9 11 146 PA12
PI10 12 145 PA11
PI11 13 144 PA10
VSS 14 143 PA9
VDD 15 142 PA8
PF0 16 141 PC9
PF1 17 140 PC8
PF2 18 139 PC7
PI12 19 138 PC6
PI13 20 137 VDD33USB
PI14 21 136 VSS
PF3 22 135 PG8
PF4 23 134 PG7
PF5 24 133 PG6
VSS 25 208-pins 132 PG5
VDD 26 131 PG4
PF6 27 130 PG3
PF7 28 129 PG2
PF8 29 128 PK2
PF9 30 127 PK1
PF10 31 126 PK0
PH0-OSC_IN 32 125 VSS
PH1-OSC_OUT 33 124 VDD
NRST 34 123 PJ11
PC0 35 122 PJ10
PC1 36 121 PJ9
PC2_C 37 120 PJ8
PC3_C 38 119 PJ7
VDD 39 118 PJ6
VSSA 40 117 PD15
VREF+ 41 116 PD14
VDDA 42 115 VDD
PA0 43 114 VSS
PA1 44 113 PD13
PA2 45 112 PD12
PH2 46 111 PD11
PH3 47 110 PD10
PH4 48 109 PD9
PH5 49 108 PD8
PA3 50 107 PB15
VSS 51 106 PB14
100
101
102
103
104
VDD 52 105 PB13
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
PC4
PC5
VDD
VSS
PB0
PB1
PB2
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
VSS
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VDD
PJ5
PH6
PH7
PH8
PH9
PH10
PH12
VDD
PB12
PA4
PA5
PA6
PA7
PF11
PE11
PB11
PH11
MSv41915V3
60/356 DS12117 Rev 7

Figure 11. TFBGA240+25 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
VDD
A VSS PI6 PI5 PI4 PB5 VCAP PK5 PG10 PG9 PD5 PD4 PC10 PA15 PI1 PI0 VSS
LDO
B VBAT VSS PI7 PE1 PB6 VSS PB4 PK4 PG11 PJ15 PD6 PD3 PC11 PA14 PI2 PH15 PH14
PC15- PC14-
VDD
C OSC32_ OSC32_ PE2 PE0 PB7 PB3 PK6 PK3 PG12 VSS PD7 PC12 VSS PI3 PA13 VSS
LDO
OUT IN
D PE5 PE4 PE3 PB9 PB8 PG15 PK7 PG14 PG13 PJ14 PJ12 PD2 PD0 PA10 PA9 PH13 VCAP
PDR_ BOO
E NC PI9 PC13 PI8 PE6 VDD VDD PJ13 VDD PD1 PC8 PC9 PA8 PA12 PA11
ON T0
VDD33
F NC NC PI10 PI11 VDD PC7 PC6 PG8 PG7
USB
VDD50
G PF2 NC PF1 PF0 VDD VSS VSS VSS VSS VSS VDD PG5 PG6 VSS
USB
H PI12 PI13 PI14 PF3 VDD VSS VSS VSS VSS VSS VDD PG4 PG3 PG2 PK2
PH0-
PH0- VSS VSS VSS VSS VSS
J OSC_
OSC_IN
VSS PF5 PF4 VDD PK0 PK1 VSS VSS
OUT
K NRST PF6 PF7 PF8 VDD VSS VSS VSS VSS VSS VDD PJ11 VSS NC NC
L VDDA PC0 PF10 PF9 VDD VSS VSS VSS VSS VSS VDD PJ10 VSS NC NC
M VREF+ PC1 PC2 PC3 VDD VDD PJ9 VSS NC NC
N VREF- PH2 PA2 PA1 PA0 PJ0 VDD VDD PE10 VDD VDD VDD PJ8 PJ7 PJ6 VSS NC
P VSSA PH3 PH4 PH5 PI15 PJ1 PF13 PF14 PE9 PE11 PB10 PB11 PH10 PH11 PD15 PD14 VDD
R PC2_C PC3_C PA6 VSS PA7 PB2 PF12 VSS PF15 PE12 PE15 PJ5 PH9 PH12 PD11 PD12 PD13
T PA0_C PA1_C PA5 PC4 PB1 PJ2 PF11 PG0 PE8 PE13 PH6 VSS PH8 PB12 PB15 PD10 PD9
VCAP VDD
U VSS PA3 PA4 PC5 PB0 PJ3 PJ4 PG1 PE7 PE14
LDO
PH7 PB13 PB14 PD8 VSS
MSv41911V2
DS12117 Rev 7 61/356

102
Table 7. Legend/abbreviations used in the pinout table

Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during
Pin name
and after reset is the same as the actual pin name
S Supply pin
I Input only pin
Pin type
I/O Input / output pin
ANA Analog-only Input
FT 5 V tolerant I/O
TT 3.3 V tolerant I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
I/O structure Option for TT and FT I/Os
_f I2C FM+ option

_a analog option (supplied by VDDA)
_u USB option (supplied by VDD33USB)
_h High-speed low-voltage I/O
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
Notes
after reset.
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin functions
Additional
Functions directly selected/enabled through peripheral registers
functions
62/356 DS12117 Rev 7

Table 8. Pin/ball definition

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
(function Additional
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TRACECLK, SAI1_CK1,
SPI4_SCK,
SAI1_MCLK_A,
SAI4_MCLK_A,
1 A3 1 A2 A2 1 1 C3 PE2 I/O FT_h - -
QUADSPI_BK1_IO2,
SAI4_CK1,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
TRACED0, TIM15_BKIN,
2 B3 2 B2 A1 2 2 D3 PE3 I/O FT_h - SAI1_SD_B, SAI4_SD_B, -
FMC_A19, EVENTOUT
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N,
3 C3 3 A1 B1 3 3 D2 PE4 I/O FT_h - SPI4_NSS, SAI1_FS_A, -
SAI4_FS_A, SAI4_D2,
FMC_A20, DCMI_D4,
LCD_B0, EVENTOUT
TRACED2, SAI1_CK2,
DFSDM1_CKIN3,
TIM15_CH1, SPI4_MISO,
4 D3 4 C3 B2 4 4 D1 PE5 I/O FT_h - SAI1_SCK_A, -
SAI4_SCK_A, SAI4_CK2,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
5 E3 5 C2 B3 5 5 E5 PE6 I/O FT_h - -
SAI2_MCLK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
- - - M4 H10 - - A1 VSS S - - - -
- - - A3 - - - - VDD S - - - -
6 B2 6 E3 C1 6 6 B1 VBAT S - - - -
- - - - J6 - - B2 VSS S - - - -
RTC_TAMP2/
- - - - D2 7 7 E4 PI8 I/O FT - EVENTOUT
WKUP3
RTC_TAMP1/
7 A2 7 D3 D1 8 8 E3 PC13 I/O FT - EVENTOUT RTC_TS/
WKUP2
- - - - J7 - - B6 VSS S - - - -
DS12117 Rev 7 63/356

102
Table 8. Pin/ball definition (continued)

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
PC14-
OSC32_
8 A1 8 C1 E1 9 9 C2 IN I/O FT - EVENTOUT OSC32_IN
(OSC32_
IN)(1)
PC15-
OSC32_
OSC32_
9 B1 9 B1 F1 10 10 C1 OUT I/O FT - EVENTOUT
OUT
(OSC32_
OUT)(1)
UART4_RX,
FDCAN1_RX, FMC_D30,
- - - - D3 11 11 E2 PI9 I/O FT_h - -
LCD_VSYNC,
EVENTOUT
FDCAN1_RXFD_MODE,
ETH_MII_RX_ER,
- - - - E3 12 12 F3 PI10 I/O FT_h -
FMC_D31, LCD_HSYNC,
EVENTOUT
LCD_G6,
- - - E1 E4 13 13 F4 PI11 I/O FT - OTG_HS_ULPI_DIR, WKUP4
EVENTOUT
- C2 - D2 F2 14 14 A17 VSS S - - - -
- D2 - D1 F3 15 15 E6 VDD S - - - -
- - - - - - - E1(2) NC - - - - -
- - - - - - - F1(3) NC - - - - -
- - - - - - - G2(4) NC - - - - -
I2C2_SDA, FMC_A0,
- - 10 F3 E2 16 16 G4 PF0 I/O FT_f - -
EVENTOUT
I2C2_SCL, FMC_A1,
- - 11 E4 H3 17 17 G3 PF1 I/O FT_f - -
EVENTOUT
I2C2_SMBA, FMC_A2,
- - 12 F4 H2 18 18 G1 PF2 I/O FT - -
EVENTOUT
LCD_HSYNC,
- - - F2 - - 19 H1 PI12 I/O FT - -
EVENTOUT
LCD_VSYNC,
- - - F1 - - 20 H2 PI13 I/O FT - -
EVENTOUT
- - - - - - 21 H3 PI14 I/O FT_h - LCD_CLK, EVENTOUT -
FT_
- - 13 E5 J2 19 22 H4 PF3 I/O - FMC_A3, EVENTOUT ADC3_INP5
ha
64/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
FT_ ADC3_INN5,
- - 14 G3 J3 20 23 J5 PF4 I/O - FMC_A4, EVENTOUT
ha ADC3_INP9
FT_
- - 15 F5 K3 21 24 J4 PF5 I/O - FMC_A5, EVENTOUT ADC3_INP4
ha
10 - 16 B10 G2 22 25 C10 VSS S - - - -
11 - 17 G1 G3 23 26 E9 VDD S - - - -
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
FT_ ADC3_INN4,
- - 18 G4 K2 24 27 K2 PF6 I/O - SAI4_SD_B,
ha ADC3_INP8
QUADSPI_BK1_IO3,
EVENTOUT
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B,
FT_ UART7_TX,
- - 19 F6 K1 25 28 K3 PF7 I/O - ADC3_INP3
ha SAI4_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
FT_ UART7_RTS/UART7_DE ADC3_INN3,
- - 20 H4 L3 26 29 K4 PF8 I/O -
ha , SAI4_SCK_B, ADC3_INP7
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
TIM17_CH1N,
SPI5_MOSI, SAI1_FS_B,
FT_ UART7_CTS,
- - 21 G5 L2 27 30 L4 PF9 I/O - ADC3_INP2
ha SAI4_FS_B, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
TIM16_BKIN, SAI1_D3,
FT_ QUADSPI_CLK, ADC3_INN2,
- - 22 H3 L1 28 31 L3 PF10 I/O -
ha SAI4_D3, DCMI_D11, ADC3_INP6
LCD_DE, EVENTOUT
PH0-
12 C1 23 H1 G1 29 32 J2 OSC_IN I/O FT - EVENTOUT OSC_IN
(PH0)
PH1-
13 D1 24 H2 H1 30 33 J1 OSC_OUT I/O FT - EVENTOUT OSC_OUT
(PH1)
14 E1 25 G6 J1 31 34 K1 NRST I/O RST - - -
DS12117 Rev 7 65/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
DFSDM1_CKIN0,
DFSDM1_DATIN4,
SAI2_FS_B, ADC123_
15 F1 26 J1 M2 32 35 L2 PC0 I/O FT_a -
OTG_HS_ULPI_STP, INP10
FMC_SDNWE, LCD_R5,
EVENTOUT
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
ADC123_
DFSDM1_CKIN4,
INN10,
SPI2_MOSI/I2S2_SDO,
FT_ ADC123_
16 F2 27 J2 M3 33 36 M2 PC1 I/O - SAI1_SD_A, SAI4_SD_A,
ha INP11,
SDMMC2_CK, SAI4_D1,
RTC_TAMP3/W
ETH_MDC,
KUP5
MDIOS_MDC,
EVENTOUT
CDSLEEP, ADC123_
DFSDM1_CKIN1, INN11,
- - - - - - - M3(5) PC2 I/O FT_a -
SPI2_MISO/I2S2_SDI, ADC123_
DFSDM1_CKOUT, INP12
OTG_HS_ULPI_DIR,
17 ETH_MII_TXD2, ADC3_INN1,
(6) E2(6) 28(6) K2(6) M4(6) 34(6) 37(6) R1(5) PC2_C ANA TT_a - FMC_SDNE0, ADC3_INP0
EVENTOUT
CSLEEP, ADC12_INN12,
- - - - - - - M4(5) PC3 I/O FT_a -
DFSDM1_DATIN1, ADC12_INP13
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
18 ETH_MII_TX_CLK,
(6) F3(6) 29(6) K1(6) M5(6) 35(6) 38(6) R2(5) PC3_C ANA TT_a - ADC3_INP1
FMC_SDCKE0,
EVENTOUT
- F5 30 - G3 36 39 E11 VDD S - - - -
- E6 - B3 J10 - - C13 VSS S - - - -
19 G1 31 J3 M1 37 40 P1 VSSA S - - - -
- - - - N1 - - N1 VREF- S - - - -
20 -(7) 32 L2 P1 38 41 M1 VREF+ S - - - -
21 H1 33 L1 R1 39 42 L1 VDDA S - - - -
66/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TIM2_CH1/TIM2_ETR, ADC1_INP16,
22 G2 34 J5 N3 40 43 N5(5) PA0 I/O FT_a -
TIM5_CH1, TIM8_ETR, WKUP0
TIM15_BKIN,
USART2_CTS/USART2_
NSS, UART4_TX,
SDMMC2_CMD, ADC12_INN1,
- - - - - - - T1(5) PA0_C ANA TT_a -
SAI2_SD_B, ADC12_INP0
ETH_MII_CRS,
EVENTOUT
FT_ TIM2_CH2, TIM5_CH2, ADC1_INN16,

23 H2 35 K4 N2 41 44 N4(5) PA1 I/O -
ha LPTIM3_OUT, ADC1_INP17
TIM15_CH1N,
USART2_RTS/USART2_
DE, UART4_RX,
QUADSPI_BK1_IO3,
- - - - - - - T2(5) PA1_C ANA TT_a - SAI2_MCLK_B, ADC12_INP1
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
LCD_R2, EVENTOUT
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT,
TIM15_CH1,
USART2_TX, ADC12_INP14,
24 J2 36 N1 P2 42 45 N3 PA2 I/O FT_a -
SAI2_SCK_B, WKUP1
ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
LPTIM1_IN2,
QUADSPI_BK2_IO0,
FT_ SAI2_SCK_B,
- - - N2 F4 43 46 N2 PH2 I/O - ADC3_INP13
ha ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
- K1 - M1 - - - F5 VDD S - - - -
- J1 - M7 J8 - - C16 VSS S - - - -
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
FT_ ADC3_INN13,
- - - M3 G4 44 47 P2 PH3 I/O - ETH_MII_COL,
ha ADC3_INP14
FMC_SDNE0, LCD_R1,
EVENTOUT
I2C2_SCL, LCD_G5,
ADC3_INN14,
- - - K3 H4 45 48 P3 PH4 I/O FT_fa - OTG_HS_ULPI_NXT,
ADC3_INP15
LCD_G4, EVENTOUT
I2C2_SDA, SPI5_NSS,
ADC3_INN15,
- - - L3 J4 46 49 P4 PH5 I/O FT_fa - FMC_SDNWE,
ADC3_INP16
EVENTOUT
DS12117 Rev 7 67/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT,
TIM15_CH2,
FT_
25 K2 37 N3 R2 47 50 U2 PA3 I/O - USART2_RX, LCD_B2, ADC12_INP15
ha
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
26 - 38 G2 K6 - 51 F2(4) VSS S - - - -
- - - - L4 48 - - VSS S - - - -
27 - 39 - K4 49 52 G5 VDD S - - - -
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, SPI6_NSS, ADC12_INP18,
28 G3 40 H6 N4 50 53 U3 PA4 I/O TT_a -
OTG_HS_SOF, DAC1_OUT1
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N, ADC12_INN18,
TT_
29 H3 41 L4 P4 51 54 T3 PA5 I/O - SPI1_SCK/I2S1_CK, ADC12_INP19,
ha
SPI6_SCK, DAC1_OUT2
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO, TIM13_CH1,
30 J3 42 K5 P3 52 55 R3 PA6 I/O FT_a - TIM8_BKIN_COMP12, ADC12_INP3
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
ADC12_INN3,
SPI6_MOSI, TIM14_CH1,
31 K3 43 J6 R3 53 56 R5 PA7 I/O TT_a - ADC12_INP7,
ETH_MII_RX_DV/ETH_R
OPAMP1_VINM
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
68/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
DFSDM1_CKIN2,
I2S1_MCK, ADC12_INP4,
SPDIFRX1_IN3, OPAMP1_
32 G4 44 K6 N5 54 57 T4 PC4 I/O TT_a -
ETH_MII_RXD0/ETH_R VOUT,
MII_RXD0, FMC_SDNE0, COMP1_INM
EVENTOUT
SAI1_D3,
DFSDM1_DATIN2,
SPDIFRX1_IN4,
ADC12_INN4,
SAI4_D3,
ADC12_INP8,
33 H4 45 N5 P5 55 58 U4 PC5 I/O TT_a - ETH_MII_RXD1/ETH_R
OPAMP1_
MII_RXD1,
VINM
FMC_SDCKE0,
COMP1_OUT,
EVENTOUT
- - - N4 - - 59 G13 VDD S - - - -
- - - H12 J9 - 60 R4 VSS S - - - -
TIM8_CH2N,
ADC12_INN5,
DFSDM1_CKOUT,
ADC12_INP9,
34 J4 46 M5 R5 56 61 U5 PB0 I/O FT_a - UART4_CTS, LCD_R3,
OPAMP1_VINP,
OTG_HS_ULPI_D1,
COMP1_INP
ETH_MII_RXD2,
LCD_G1, EVENTOUT
TIM8_CH3N,
DFSDM1_DATIN1,
ADC12_INP5,
35 K4 47 L5 R4 57 62 T5 PB1 I/O TT_u - LCD_R6,
COMP1_INM
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
LCD_G0, EVENTOUT
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1,
SAI1_SD_A,
FT_
36 G5 48 L6 M6 58 63 R6 PB2 I/O - SPI3_MOSI/I2S3_SDO, COMP1_INP
ha
SAI4_SD_A,
QUADSPI_CLK,
SAI4_D1, EVENTOUT
LCD_G2, LCD_R0,
- - - - - - 64 P5 PI15 I/O FT - -
EVENTOUT
LCD_R7, LCD_R1,
- - - J4 - - 65 N6 PJ0 I/O FT - -
EVENTOUT
- - - H5 - - 66 P6 PJ1 I/O FT - LCD_R2, EVENTOUT -
- - - - - - 67 T6 PJ2 I/O FT - LCD_R3, EVENTOUT -
DS12117 Rev 7 69/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
- - - - - - 68 U6 PJ3 I/O FT - LCD_R4, EVENTOUT -
- - - - - - 69 U7 PJ4 I/O FT - LCD_R5, EVENTOUT -
SPI5_MOSI, SAI2_SD_B,
- - 49 M6 R6 59 70 T7 PF11 I/O FT_a - FMC_SDNRAS, ADC1_INP2
DCMI_D12, EVENTOUT
FT_ ADC1_INN2,
- - 50 N6 P6 60 71 R7 PF12 I/O - FMC_A6, EVENTOUT
ha ADC1_INP6
- - 51 M11 M8 61 72 J3 VSS S - - - -
- - 52 - N8 62 73 H5 VDD S - - - -
DFSDM1_DATIN6,
FT_
- - 53 G7 N6 63 74 P7 PF13 I/O - I2C4_SMBA, FMC_A7, ADC2_INP2
ha
EVENTOUT
DFSDM1_CKIN6,
FT_ ADC2_INN2,
- - 54 H7 R7 64 75 P8 PF14 I/O - I2C4_SCL, FMC_A8,
fha ADC2_INP6
EVENTOUT
I2C4_SDA, FMC_A9,
- - 55 J7 P7 65 76 R9 PF15 I/O FT_fh - -
EVENTOUT
- - 56 K7 N7 66 77 T8 PG0 I/O FT_h - FMC_A10, EVENTOUT -
- - - M2 F6 - - J16 VSS S - - - -
- - - A10 - - - H13 VDD S - - - -

OPAMP2_
- - 57 L7 M7 67 78 U8 PG1 I/O TT_h - FMC_A11, EVENTOUT
VINM
TIM1_ETR,
DFSDM1_DATIN2,
OPAMP2_
TT_ UART7_RX,
37 H5 58 G8 R8 68 79 U9 PE7 I/O - VOUT,
ha QUADSPI_BK2_IO0,
COMP2_INM
FMC_D4/FMC_DA4,
EVENTOUT
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_TX,
TT_ OPAMP2_
38 J5 59 H8 P8 69 80 T9 PE8 I/O - QUADSPI_BK2_IO1,
ha VINM
FMC_D5/FMC_DA5,
COMP2_OUT,
EVENTOUT
TIM1_CH1,
DFSDM1_CKOUT,
TT_ UART7_RTS/UART7_DE OPAMP2_VINP,
39 K5 60 J8 P9 70 81 P9 PE9 I/O -
ha , QUADSPI_BK2_IO2, COMP2_INP
FMC_D6/FMC_DA6,
EVENTOUT
70/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
- - 61 C12 M9 71 82 J17 VSS S - - - -
- - 62 C13 N9 72 83 J13 VDD S - - - -

TIM1_CH2N,
DFSDM1_DATIN4,
FT_ UART7_CTS,
40 G6 63 M8 R9 73 84 N9 PE10 I/O - COMP2_INM
ha QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7,
EVENTOUT
TIM1_CH2,
DFSDM1_CKIN4,
FT_
41 H6 64 N8 P10 74 85 P10 PE11 I/O - SPI4_NSS, SAI2_SD_B, COMP2_INP
ha
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK,
42 J6 65 L8 R10 75 86 R10 PE12 I/O FT_h - SAI2_SCK_B, -
FMC_D9/FMC_DA9,
COMP1_OUT, LCD_B4,
EVENTOUT
TIM1_CH3,
DFSDM1_CKIN5,
SPI4_MISO, SAI2_FS_B,
43 K6 66 K8 N11 76 87 T10 PE13 I/O FT_h - -
FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
- - - L12 F7 - - T12 VSS S - - - -
- - - H13 - - - K13 VDD S - - - -
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
44 G7 67 J9 P11 77 88 U10 PE14 I/O FT_h - -
FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
TIM1_BKIN,
FMC_D12/FMC_DA12,
45 H7 68 N9 R11 78 89 R11 PE15 I/O FT_h - TIM1_BKIN_COMP12/ -
COMP_TIM1_BKIN,
LCD_R7, EVENTOUT
DS12117 Rev 7 71/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TIM2_CH3,
HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
46 J7 69 L9 R12 79 90 P11 PB10 I/O FT_f - -
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
TIM2_CH4,
HRTIM_SCIN,
LPTIM2_ETR,
I2C2_SDA,
DFSDM1_CKIN7,
47 K7 70 M9 R13 80 91 P12 PB11 I/O FT_f - -
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, LCD_G5,
EVENTOUT
48 F8 71 N10 M10 81 92 U11 VCAP S - - - -
49 E4 - - K7 - 93 - VSS S - - - -
VDDLDO
- - - M10 - - - U12 (8) S - - - -
50 - 72 M1 N10 82 94 L13 VDD S - - - -
- - - - - - 95 R12 PJ5 I/O FT - LCD_R6, EVENTOUT -
TIM12_CH1,
I2C2_SMBA, SPI5_SCK,
- - - - M11 83 96 T11 PH6 I/O FT - ETH_MII_RXD2, -
FMC_SDNE1, DCMI_D8,
EVENTOUT
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
- - - - N12 84 97 U13 PH7 I/O FT_fa - -
FMC_SDCKE1,
DCMI_D9, EVENTOUT
TIM5_ETR, I2C3_SDA,
FT_fh FMC_D16,
- - - - M12 85 98 T13 PH8 I/O - -
a DCMI_HSYNC, LCD_R2,
EVENTOUT
- - - - F8 - - - VSS S - - - -
- - - L13 - - - M13 VDD S - - - -
72/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TIM12_CH2,
I2C3_SMBA, FMC_D17,
- - - - M13 86 99 R13 PH9 I/O FT_h - -
DCMI_D0, LCD_R3,
EVENTOUT
TIM5_CH1, I2C4_SMBA,
- - - K9 L13 87 100 P13 PH10 I/O FT_h - FMC_D18, DCMI_D1, -
LCD_R4, EVENTOUT
TIM5_CH2, I2C4_SCL,
- - - L10 L12 88 101 P14 PH11 I/O FT_fh - FMC_D19, DCMI_D2, -
LCD_R5, EVENTOUT
TIM5_CH3, I2C4_SDA,
- - - K10 K12 89 102 R14 PH12 I/O FT_fh - FMC_D20, DCMI_D3, -
LCD_R6, EVENTOUT
- - - - H12 90 - N16 VSS S - - - -
- - - N11 J12 91 103 P17 VDD S - - - -
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK,
FDCAN2_RX,
51 K8 73 N12 P12 92 104 T14 PB12 I/O FT_u -
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RM
II_TXD0, OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
TIM1_CH1N,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
USART3_CTS/USART3_ OTG_HS_
52 J8 74 L11 P13 93 105 U14 PB13 I/O FT_u -
NSS, FDCAN2_TX, VBUS
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RM
II_TXD1, UART5_TX,
EVENTOUT
DS12117 Rev 7 73/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
53 H10 75 N13 R14 94 106 U15 PB14 I/O FT_u - -
USART3_RTS/
USART3_DE,
UART4_RTS/UART4_DE
, SDMMC2_D0,
OTG_HS_DM,
EVENTOUT
RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
54 G10 76 M13 R15 95 107 T15 PB15 I/O FT_u - SPI2_MOSI/I2S2_SDO, -
DFSDM1_CKIN2,
UART4_CTS,
SDMMC2_D1,
OTG_HS_DP,
EVENTOUT
DFSDM1_CKIN3,
SAI3_SCK_B,
USART3_TX,
55 K9 77 M12 P15 96 108 U16 PD8 I/O FT_h - -
SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
DFSDM1_DATIN3,
SAI3_SD_B,
USART3_RX,
56 J9 78 K11 P14 97 109 T17 PD9 I/O FT_h - -
FDCAN2_RXFD_MODE,
FMC_D14/FMC_DA14,
EVENTOUT
DFSDM1_CKOUT,
SAI3_FS_B,
USART3_CK,
57 H9 79 K12 N15 98 110 T16 PD10 I/O FT_h - -
FDCAN2_TXFD_MODE,
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
- - - N7 - - - N12 VDD S - - - -
- - - - F9 - - U17 VSS S - - - -
74/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/USART3_
58 G9 80 J10 N14 99 111 R15 PD11 I/O FT_h - NSS, -
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
USART3_RTS/USART3_
59 K10 81 K13 N13 100 112 R16 PD12 I/O FT_fh - -
DE, QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
60 J10 82 J11 M15 101 113 R17 PD13 I/O FT_fh - QUADSPI_BK1_IO3, -
SAI2_SCK_A, FMC_A18,
EVENTOUT
- - 83 - K8 102 114 - VSS S - - - -
- - 84 - J13 103 115 N11 VDD S - - - -

TIM4_CH3,
SAI3_MCLK_B,
61 H8 85 J13 M14 104 116 P16 PD14 I/O FT_h - UART8_CTS, -
FMC_D0/FMC_DA0,
EVENTOUT
TIM4_CH4,
SAI3_MCLK_A,
62 G8 86 J12 L14 105 117 P15 PD15 I/O FT_h - UART8_RTS/UART8_DE -
, FMC_D1/FMC_DA1,
EVENTOUT
TIM8_CH2, LCD_R7,
- - - - - - 118 N15 PJ6 I/O FT - -
EVENTOUT
TRGIN, TIM8_CH2N,
- - - - - - 119 N14 PJ7 I/O FT - -
LCD_G0, EVENTOUT
- - - - - - - N10 VDD S - -
- - - - F10 - - R8 VSS S - -
- - - - - - 120 N13 PJ8 I/O FT - UART8_TX, LCD_G1, -
EVENTOUT
TIM1_CH3, TIM8_CH1N,
- - - - - - 121 M14 PJ9 I/O FT - UART8_RX, LCD_G2, -
EVENTOUT
DS12117 Rev 7 75/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
- - - - - - 122 L14 PJ10 I/O FT - SPI5_MOSI, LCD_G3, -
EVENTOUT
- - - - - - 123 K14 PJ11 I/O FT - SPI5_MISO, LCD_G4, -
EVENTOUT
- - - - - - 124 N8 VDD S - -
- - - - G6 - 125 U1 VSS S - - - -
N17
- - - - - - - (2) NC - - - - -
M16
- - - - - - - (2) NC - - - - -
M17
- - - - - - - (2) NC - - - - -
- - - - - - - K15 VSS S - - - -
(2)
- - - - - - - L16 NC - - - - -
(2)
- - - - - - - L17 NC - - - - -
K16
- - - - - - - (2) NC - - - - -
K17
- - - - - - - (2) NC - - - - -
- - - - - - - L15 VSS S - - - -
- - - - - - 126 J14 PK0 I/O FT - SPI5_SCK, LCD_G5, -
EVENTOUT
- - - - - - 127 J15 PK1 I/O FT - SPI5_NSS, LCD_G6, -
EVENTOUT
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
- - - - - - 128 H17 PK2 I/O FT - -
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT
TIM8_BKIN,
- - 87 H9 L15 106 129 H16 PG2 I/O FT_h - TIM8_BKIN_COMP12, -
FMC_A12, EVENTOUT
TIM8_BKIN2,
- - 88 H10 K15 107 130 H15 PG3 I/O FT_h - TIM8_BKIN2_COMP12, -
FMC_A13, EVENTOUT
- - - - G7 - - - VSS S - - - -
76/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
- - - - - - - N7 VDD S - - - -
TIM1_BKIN2,
TIM1_BKIN2_COMP12,
- - 89 F8 K14 108 131 H14 PG4 I/O FT_h - -
FMC_A14/FMC_BA0,
EVENTOUT
TIM1_ETR,
- - 90 H11 K13 109 132 G14 PG5 I/O FT_h - FMC_A15/FMC_BA1, -
EVENTOUT
TIM17_BKIN,
HRTIM_CHE1,
- - 91 G9 J15 110 133 G15 PG6 I/O FT_h - QUADSPI_BK1_NCS, -
FMC_NE3, DCMI_D12,
LCD_R7, EVENTOUT
HRTIM_CHE2,
SAI1_MCLK_A,
- - 92 G10 J14 111 134 F16 PG7 I/O FT_h - USART6_CK, FMC_INT, -
DCMI_D13, LCD_CLK,
EVENTOUT
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6_
DE, SPDIFRX1_IN3,
- - 93 G11 H14 112 135 F15 PG8 I/O FT_h - -
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
- - 94 - G12 113 136 G16 VSS S - - - -
VDD50
- - - G12 - - - G17 S - - - -
USB
VDD33
- F6 95 G13 H13 114 137 F17 S - - - -
USB
- - - - - - - M5 VDD S - - - -
HRTIM_CHA1,
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
I2S2_MCK, USART6_TX,
SDMMC1_D0DIR,
63 F10 96 F9 H15 115 138 F14 PC6 I/O FT_h - SWPMI_IO
FMC_NWAIT,
SDMMC2_D6,
SDMMC1_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT
DS12117 Rev 7 77/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
I2S3_MCK,
USART6_RX,
64 E10 97 F10 G15 116 139 F13 PC7 I/O FT_h - SDMMC1_D123DIR, -
FMC_NE1,
SDMMC2_D7,
SWPMI_TX,
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
TRACED1,
HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
65 F9 98 F12 G14 117 140 E13 PC8 I/O FT_h - UART5_RTS/UART5_DE -
, FMC_NE2/FMC_NCE,
SWPMI_RX,
SDMMC1_D0, DCMI_D2,
EVENTOUT
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
66 E9 99 F11 F14 118 141 E14 PC9 I/O FT_fh - -
LCD_G3,
SWPMI_SUSPEND,
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT
- - - - G8 - - - VSS S - - -
- - - - - - - L5 VDD S - - -
MCO1, TIM1_CH1,
HRTIM_CHB2,
TIM8_BKIN2, I2C3_SCL,
USART1_CK,
FT_
67 D9 100 E12 F15 119 142 E15 PA8 I/O - OTG_FS_SOF, -
fha
UART7_RX,
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
78/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TIM1_CH2,
HRTIM_CHC1,
LPUART1_TX,
I2C3_SMBA,
68 C9 101 E11 E15 120 143 D15 PA9 I/O FT_u - SPI2_SCK/I2S2_CK, OTG_FS_VBUS
USART1_TX,
FDCAN1_RXFD_MODE,
DCMI_D0, LCD_R5,
EVENTOUT
TIM1_CH3,
HRTIM_CHC2,
LPUART1_RX,
USART1_RX,
69 D10 102 E10 D15 121 144 D14 PA10 I/O FT_u - FDCAN1_TXFD_MODE, -
OTG_FS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1, LCD_B1,
EVENTOUT
TIM1_CH4,
HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
70 C10 103 F13 C15 122 145 E17 PA11 I/O FT_u - UART4_RX, -
USART1_CTS/USART1_
NSS, FDCAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
TIM1_ETR,
HRTIM_CHD2,
LPUART1_RTS/
LPUART1_DE,
SPI2_SCK/I2S2_CK,
71 B10 104 E13 B15 123 146 E16 PA12 I/O FT_u - UART4_TX, -
USART1_RTS/USART1_
DE, SAI2_FS_B,
FDCAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
PA13
JTMS-SWDIO,
72 A10 105 D11 A15 124 147 C15 (JTMS/SW I/O FT - -
EVENTOUT
DIO)
73 E7 106 D13 F13 125 148 D17 VCAP S - - - -
74 E5 107 - F12 126 149 - VSS S - - - -
VDDLDO
- - - D12 - - - C17 (8) - - - -
75 - 108 - G13 127 150 K5 VDD S - - - -
DS12117 Rev 7 79/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TIM8_CH1N, UART4_TX,
- - - - E12 128 151 D16 PH13 I/O FT_h - FDCAN1_TX, FMC_D21, -
LCD_G2, EVENTOUT
TIM8_CH2N,
UART4_RX,
- - - - E13 129 152 B17 PH14 I/O FT_h - FDCAN1_RX, FMC_D22, -
DCMI_D4, LCD_G3,
EVENTOUT
TIM8_CH3N,
FDCAN1_TXFD_MODE,
- - - - D13 130 153 B16 PH15 I/O FT_h - -
FMC_D23, DCMI_D11,
LCD_G4, EVENTOUT
TIM5_CH4,
SPI2_NSS/I2S2_WS,
- - - A13 E14 131 154 A16 PI0 I/O FT_h - FDCAN1_RXFD_MODE, -
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
- - - - G9 - - - VSS S - - - -
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
- - - B13 D14 132 155 A15 PI1 I/O FT_h - TIM8_BKIN2_COMP12, -
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
TIM8_CH4,
SPI2_MISO/I2S2_SDI,
- - - A6 C14 133 156 B15 PI2 I/O FT_h - -
FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
- - - B7 C13 134 157 C14 PI3 I/O FT_h - -
FMC_D27, DCMI_D10,
EVENTOUT
- - - - D9 135 - - VSS S - - - -
- - - - C9 136 158 - VDD S - - - -
PA14
JTCK-SWCLK,
76 A9 109 B12 A14 137 159 B14 (JTCK/SW I/O FT - -
EVENTOUT
CLK)
80/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
JTDI,
TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
SPI1_NSS/I2S1_WS,
PA15
77 A8 110 C11 A13 138 160 A14 I/O FT - SPI3_NSS/I2S3_WS, -
(JTDI)
SPI6_NSS,
UART4_RTS/UART4_DE
, UART7_TX,
EVENTOUT
HRTIM_EEV1,
DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
FT_ USART3_TX,
78 B9 111 A12 B14 139 161 A13 PC10 I/O - -
ha UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
HRTIM_FLT2,
DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX,
79 B8 112 B11 B13 140 162 B13 PC11 I/O FT_h - -
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
TRACED3,
HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
80 C8 113 A11 A12 141 163 C12 PC12 I/O FT_h - USART3_CK, -
UART5_TX,
SDMMC1_CK, DCMI_D9,
EVENTOUT
- - - - G10 - - - VSS S - - - -
DFSDM1_CKIN6,
SAI3_SCK_A,
UART4_RX,
81 D8 114 D10 B12 142 164 D13 PD0 I/O FT_h - -
FDCAN1_RX,
FMC_D2/FMC_DA2,
EVENTOUT
DFSDM1_DATIN6,
SAI3_SD_A, UART4_TX,
82 E8 115 C10 C12 143 165 E12 PD1 I/O FT_h - FDCAN1_TX, -
FMC_D3/FMC_DA3,
EVENTOUT
DS12117 Rev 7 81/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TRACED2, TIM3_ETR,
UART5_RX,
83 B7 116 E9 D12 144 166 D12 PD2 I/O FT_h - -
SDMMC1_CMD,
DCMI_D11, EVENTOUT
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_
84 C7 117 D9 D11 145 167 B12 PD3 I/O FT_h - -
NSS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
HRTIM_FLT3,
SAI3_FS_A,
USART2_RTS/USART2_
85 D7 118 C9 D10 146 168 A12 PD4 I/O FT_h - -
DE,
FDCAN1_RXFD_MODE,
FMC_NOE, EVENTOUT
HRTIM_EEV3,
USART2_TX,
86 B6 119 A9 C11 147 169 A11 PD5 I/O FT_h - -
FDCAN1_TXFD_MODE,
FMC_NWE, EVENTOUT
- - 120 - D8 148 170 - VSS S - - - -
- - 121 - C8 149 171 - VDD S - - - -
SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
USART2_RX,
87 C6 122 B9 B11 150 172 B11 PD6 I/O FT_h - -
SAI4_SD_A,
FDCAN2_RXFD_MODE,
SAI4_D1, SDMMC2_CK,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
88 D6 123 D8 A11 151 173 C11 PD7 I/O FT_h - USART2_CK, -
SPDIFRX1_IN1,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
TRGOUT, LCD_G3,
- - - - - - 174 D11 PJ12 I/O FT - -
LCD_B0, EVENTOUT
LCD_B4, LCD_B1,
- - - - - - 175 E10 PJ13 I/O FT - -
EVENTOUT
82/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
- - - - - - 176 D10 PJ14 I/O FT - LCD_B2, EVENTOUT -
- - - - - - 177 B10 PJ15 I/O FT - LCD_B3, EVENTOUT -
- - - - H6 - - - VSS S - - - -
- - - A7 - - - - VDD S - - - -
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX1_IN4,
QUADSPI_BK2_IO2,
- - 124 C8 C10 152 178 A10 PG9 I/O FT_h - -
SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
HRTIM_FLT5,
SPI1_NSS/I2S1_WS,
- - 125 A8 B10 153 179 A9 PG10 I/O FT_h - LCD_G3, SAI2_SD_B, -
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT
LPTIM1_IN2,
HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1,
- - 126 B8 B9 154 180 B9 PG11 I/O FT_h - -
SDMMC2_D2,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
LPTIM1_IN1,
HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6_
- - 127 E8 B8 155 181 C9 PG12 I/O FT_h - DE, SPDIFRX1_IN2, -
LCD_B4,
ETH_MII_TXD1/ETH_RM
II_TXD1, FMC_NE4,
LCD_B1, EVENTOUT
TRACED0,
LPTIM1_OUT,
HRTIM_EEV10,
SPI6_SCK,
- - 128 D7 A8 156 182 D9 PG13 I/O FT_h - USART6_CTS/USART6_ -
NSS,
ETH_MII_TXD0/ETH_RM
II_TXD0, FMC_A24,
LCD_R0, EVENTOUT
DS12117 Rev 7 83/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TRACED1,
LPTIM1_ETR,
SPI6_MOSI,
USART6_TX,
- - 129 C7 A7 157 183 D8 PG14 I/O FT_h - -
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RM
II_TXD1, FMC_A25,
LCD_B0, EVENTOUT
- - 130 - D7 158 184 - VSS S - - - -
- - 131 - C7 159 185 - VDD S - - - -
- - - - - - 186 C8 PK3 I/O FT - LCD_B4, EVENTOUT -

- - - - - - 187 B8 PK4 I/O FT - LCD_B5, EVENTOUT -
- - - - - - 188 A8 PK5 I/O FT - LCD_B6, EVENTOUT -
- - - - - - 189 C7 PK6 I/O FT - LCD_B7, EVENTOUT -

- - - - - - 190 D7 PK7 I/O FT - LCD_DE, EVENTOUT -
- - - - H7 - - - VSS S - - - -
USART6_CTS/USART6_
- - 132 E7 B7 160 191 D6 PG15 I/O FT_h - NSS, FMC_SDNCAS, -
DCMI_D13, EVENTOUT
JTDO/TRACESWO,
TIM2_CH2,
HRTIM_FLT4,
PB3(JTDO SPI1_SCK/I2S1_CK,
89 A7 133 F7 A10 161 192 C6 /TRACES I/O FT - SPI3_SCK/I2S3_CK, -
WO) SPI6_SCK,
SDMMC2_D2,
CRS_SYNC, UART7_RX,
EVENTOUT
NJTRST, TIM16_BKIN,
TIM3_CH1,
HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
PB4(NJTR
90 A6 134 B6 A9 162 193 B7 I/O FT - SPI3_MISO/I2S3_SDI, -
ST)
SPI2_NSS/I2S2_WS,
SPI6_MISO,
SDMMC2_D3,
UART7_TX, EVENTOUT
84/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TIM17_BKIN, TIM3_CH2,
HRTIM_EEV7,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
91 C5 135 C6 A6 163 194 A5 PB5 I/O FT - SPI6_MOSI, -
FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
- - - - H8 - - - VSS S - - - -
TIM16_CH1N,
TIM4_CH1,
HRTIM_EEV8,
I2C1_SCL, CEC,
I2C4_SCL, USART1_TX,
92 B5 136 A5 B6 164 195 B5 PB6 I/O FT_f - LPUART1_TX, -
FDCAN2_TX,
QUADSPI_BK1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1, DCMI_D5,
UART5_TX, EVENTOUT
TIM17_CH1N,
TIM4_CH2,
HRTIM_EEV9,
I2C1_SDA, I2C4_SDA,
USART1_RX,
93 A5 137 D6 B5 165 196 C5 PB7 I/O FT_fa - PVD_IN
LPUART1_RX,
FDCAN2_TXFD_MODE,
DFSDM1_CKIN5,
FMC_NL, DCMI_VSYNC,
EVENTOUT
94 D5 138 E6 D6 166 197 E8 BOOT0 I B - - VPP
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
UART4_RX,
95 B4 139 B5 A5 167 198 D5 PB8 I/O FT_fh - -
FDCAN1_RX,
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
DS12117 Rev 7 85/356

102

Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C4_SDA,
SDMMC1_CDIR,
96 A4 140 C5 B4 168 199 D4 PB9 I/O FT_fh - -
UART4_TX,
FDCAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5, DCMI_D7,
LCD_B7, EVENTOUT
LPTIM1_ETR,
TIM4_ETR,
HRTIM_SCIN,
LPTIM2_ETR,
97 D4 141 D5 A4 169 200 C4 PE0 I/O FT_h - UART8_RX, -
FDCAN1_RXFD_MODE,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
LPTIM1_IN2,
HRTIM_SCOUT,
UART8_TX,
98 C4 142 D4 A3 170 201 B4 PE1 I/O FT_h - -
FDCAN1_TXFD_MODE,
FMC_NBL1, DCMI_D3,
EVENTOUT
- - - - - - - A7 VCAP S - - - -
99 - - - D5 - 202 - VSS S - - - -
- F7 143 C4 C6 171 203 E7 PDR_ON I FT - - -
VDDLDO
- F4 - B4 - - - A6 (8) S - - - -
100 - 144 - C5 172 204 - VDD S - - - -
TIM8_BKIN,
SAI2_MCLK_A,
- - - - D4 173 205 A4 PI4 I/O FT_h - TIM8_BKIN_COMP12, -
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
TIM8_CH1,
SAI2_SCK_A,
- - - - C4 174 206 A3 PI5 I/O FT_h - FMC_NBL3, -
DCMI_VSYNC, LCD_B5,
EVENTOUT
86/356 DS12117 Rev 7


Pin/ball name
I/O structure
Pin name
TFBGA240 +25
UFBGA176+25
Pin type
Notes
UFBGA169
TFBGA100
LQFP100
LQFP144
LQFP176
LQFP208
Alternate functions
after functions
reset)
TIM8_CH2, SAI2_SD_A,
- - - A4 C3 175 207 A2 PI6 I/O FT_h - FMC_D28, DCMI_D6, -
LCD_B6, EVENTOUT
TIM8_CH3, SAI2_FS_A,
- - - E2 C2 176 208 B3 PI7 I/O FT_h - FMC_D29, DCMI_D7, -
LCD_B7, EVENTOUT
- - - - H9 - - - VSS S - - - -
- - - - K9 - - - VSS S - - - -
- - - - K10 - - M15 VSS S - - - -
1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is
valid for all resets except for power-on reset.
2. This ball should remain floating.
3. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.
4. This ball should be connected to VSS.
5. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG
register. Refer to the product reference manual for a detailed description of the switch configuration bits.
6. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on
Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product
reference manual for a detailed description of the switch configuration bits.
7. VREF+ pin, and consequently the internal voltage reference, are not available on the TFBGA100 package. On this package,
this pin is double-bonded to VDDA which can be connected to an external reference. The internal voltage reference buffer is
not available and must be kept disabled
8. When it is not available on a package, the VDDLDO pin is internally tied to VDD.
DS12117 Rev 7 87/356

102
88/356
Pin descriptions
Table 9. Port A alternate functions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
LPUART/ SPI6/SAI2/ TIM8/ TIM1/8/FMC
USART1/ SPI2/3/SAI1/ SPI2/3/6/ TIM13/14/ SWPMI1/
Port TIM1/2/16/ SAI1/TIM3/ TIM8/ 4/UART4/5/ QUADSPI/ /SDMMC1/ TIM1/DCMI
TIM15/ SPI1/2/3/4/ 3/I2C4/ USART1/2/ QUADSPI/ TIM1/8/ UART5/
SYS 17/LPTIM1/ 4/5/12/ LPTIM2/3/4/ 8/LPUART/ SDMMC2/ MDIOS/ /LCD/ SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ FMC/ DFSDM1/ LCD
HRTIM1 HRTIM1 5/HRTIM1/ SDMMC1/ OTG1_HS/ OTG1_FS/ COMP
DFSDM1/ DFSDM1 SDMMC1 SDMMC2/ SDMMC2/
DFSDM1 SPDIFRX1 OTG2_FS/ LCD
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
USART2_
TIM2_CH1/ CTS/ SDMMC2_ ETH_MII_ EVENT-
PA0 - TIM5_CH1 TIM8_ETR TIM15_BKIN - - UART4_TX SAI2_SD_B - - -
TIM2_ETR USART2_ CMD CRS OUT
NSS
USART2_ ETH_MII_
LPTIM3_ TIM15_ RTS/ QUADSPI_ SAI2_MCLK RX_CLK/ EVENT-
PA1 - TIM2_CH2 TIM5_CH2 - - UART4_RX - - LCD_R2
OUT CH1N USART2_ BK1_IO3 _B ETH_RMII_ OUT
DE REF_CLK
LPTIM4_ USART2_ SAI2_SCK_ MDIOS_ EVENT-

PA2 - TIM2_CH3 TIM5_CH3 TIM15_CH1 - - - - ETH_MDIO - LCD_R1
OUT TX B MDIO OUT
LPTIM5_ USART2_ OTG_HS_ ETH_MII_ EVENT-

PA3 - TIM2_CH4 TIM5_CH4 TIM15_CH2 - - - LCD_B2 - - LCD_B5
DS12117 Rev 7
OUT RX ULPI_D0 COL OUT
D1 SPI1_NSS/ SPI3_NSS/ USART2_ OTG_HS_ DCMI_ LCD_ EVENT-

PA4 - TIM5_ETR - - SPI6_NSS - - -
PWREN I2S1_WS I2S3_WS CK SOF HSYNC VSYNC OUT
D2 TIM2_CH1/ TIM8_ SPI1_SCK OTG_HS_ EVENT-

PA5 - - - - SPI6_SCK - - - - LCD_R4
PWREN TIM2_ETR CH1N /I2S1_CK ULPI_CK OUT
SPI1_MISO TIM13_ TIM8_BKIN MDIOS_ TIM1_BKIN DCMI_PIX EVENT-

PA6 - TIM1_BKIN TIM3_CH1 TIM8_BKIN - - - SPI6_MISO LCD_G2
/I2S1_SDI CH1 _COMP12 MDC _COMP12 CLK OUT
Port A
ETH_MII_
TIM8_CH1 SPI1_MOSI TIM14_ RX_DV/ FMC_SDN EVENT-
PA7 - TIM1_CH1N TIM3_CH2 - - - SPI6_MOSI - - -
N /I2S1_SDO CH1 ETH_RMII_ WE OUT
CRS_DV
HRTIM_CH TIM8_BKIN USART1_ OTG_FS_ TIM8_BKIN EVENT-

PA8 MCO1 TIM1_CH1 I2C3_SCL - - - - UART7_RX LCD_B3 LCD_R6
B2 2 CK SOF 2_COMP12 OUT
FDCAN1_
HRTIM_CH LPUART1_ SPI2_SCK/ USART1_ EVENT-
PA9 - TIM1_CH2 I2C3_SMBA - - RXFD_ - - - DCMI_D0 LCD_R5
C1 TX I2S2_CK TX OUT
MODE
FDCAN1_
HRTIM_CH LPUART1_ USART1_ MDIOS_ EVENT-
PA10 - TIM1_CH3 - - - - TXFD_ OTG_FS_ID LCD_B4 DCMI_D1 LCD_B1
C2 RX RX MDIO OUT
MODE
USART1_
HRTIM_CH LPUART1_ SPI2_NSS CTS/ FDCAN1_ OTG_FS_ EVENT-
STM32H753xI
PA11 - TIM1_CH4 - UART4_RX - - - - LCD_R4
D1 CTS /I2S2_WS USART1_ RX DM OUT
NSS
LPUART1_ USART1_
HRTIM_CH RTS/ SPI2_SCK/ RTS/ FDCAN1_ OTG_FS_ EVENT-
PA12 - TIM1_ETR - UART4_TX SAI2_FS_B - - - LCD_R5
D2 LPUART1_ I2S2_CK USART1_ TX DP OUT
DE DE
Table 9. Port A alternate functions (continued)
STM32H753xI
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
USART1/ SPI2/3/SAI1/ SPI2/3/6/ TIM13/14/ SWPMI1/
TIM15/ SPI1/2/3/4/ 3/I2C4/ USART1/2/ QUADSPI/ TIM1/8/ UART5/
SYS 17/LPTIM1/ 4/5/12/ LPTIM2/3/4/ 8/LPUART/ SDMMC2/ MDIOS/ /LCD/ SYS
HRTIM1 HRTIM1 5/HRTIM1/ SDMMC1/ OTG1_HS/ OTG1_FS/ COMP
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
JTMS- EVENT-
PA13 - - - - - - - - - - - - - -
SWDIO OUT
JTCK- EVENT-
PA14 - - - - - - - - - - - - - -
Port A
SWCLK OUT
UART4_
TIM2_CH1/ HRTIM_ SPI1_NSS/ SPI3_NSS/ RTS/ EVENT-
PA15 JTDI - CEC SPI6_NSS - - UART7_TX - - -
TIM2_ETR FLT1 I2S1_WS I2S3_WS UART4_ OUT
DE
Table 10. Port B alternate functions

DS12117 Rev 7
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
USART1/ SPI2/3/SAI1 SPI2/3/6/ TIM13/14/ SWPMI1/
Port TIM1/2/16/ SAI1/TIM3/ TIM8/ 4/UART4/5/ QUADSPI/ /SDMMC1/ TIM1/
TIM15/ SPI1/2/3/4/5/ /3/I2C4/ USART1/2/3 QUADSPI/ TIM1/8/ UART5/
SYS 17/LPTIM1/ 4/5/12/ LPTIM2/3/4 8/LPUART/ SDMMC2/ MDIOS/ DCMI/LCD SYS
LPTIM2/ 6/CEC UART4/ /6/UART7/S FMC/ DFSDM1/ LCD
HRTIM1 HRTIM1 /5/HRTIM1/ SDMMC1/ OTG1_HS/ OTG1_FS/ /COMP
DFSDM1/ DFSDM1 DMMC1 SDMMC2/ SDMMC2/
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
TIM8_ DFSDM1_ UART4_ OTG_HS_ ETH_MII_ EVENT-

PB0 - TIM1_CH2N TIM3_CH3 - - - LCD_R3 - - LCD_G1
CH2N CKOUT CTS ULPI_D1 RXD2 OUT
TIM8_ DFSDM1_ OTG_HS_ ETH_MII_ EVENT-

PB1 - TIM1_CH3N TIM3_CH4 - - - - LCD_R6 - - LCD_G0
CH3N DATIN1 ULPI_D2 RXD3 OUT
SPI3_
DFSDM1_ SAI4_SD_ QUADSPI_ EVENT-
PB2 RTC_OUT - SAI1_D1 - - SAI1_SD_A MOSI/I2S3_ SAI4_D1 - - - -
CKIN1 A CLK OUT
SDO
JTDO/TRA HRTIM_ SPI1_SCK/ SPI3_SCK/ SDMMC2_ EVENT-

PB3 TIM2_CH2 - - - SPI6_SCK CRS_SYNC UART7_RX - - -
CESWO FLT4 I2S1_CK I2S3_CK D2 OUT
Port B
TIM16_ HRTIM_ SPI1_MISO/ SPI3_MISO/ SPI2_NSS/I SPI6_ SDMMC2_ EVENT-

PB4 NJTRST TIM3_CH1 - - UART7_TX - - -
BKIN EEV6 I2S1_SDI I2S3_SDI 2S2_WS MISO D3 OUT
Pin descriptions
TIM17_ HRTIM_ SPI1_MOSI/ SPI3_MOSI/ SPI6_ FDCAN2_ OTG_HS_ ETH_PPS_ FMC_ DCMI_ UART5_ EVENT-
PB5 - TIM3_CH2 I2C1_SMBA I2C4_SMBA
BKIN EEV7 I2S1_SDO I2S3_SDO MOSI RX ULPI_D7 OUT SDCKE1 D10 RX OUT
TIM16_ HRTIM_ USART1_ LPUART1_ FDCAN2_ QUADSPI_ DFSDM1_ FMC_ UART5_ EVENT-
PB6 - TIM4_CH1 I2C1_SCL CEC I2C4_SCL DCMI_D5
CH1N EEV8 TX TX TX BK1_NCS DATIN5 SDNE1 TX OUT
FDCAN2_
89/356
TIM17_ HRTIM_ USART1_ LPUART1_ DFSDM1_ DCMI_ EVENT-

PB7 - TIM4_CH2 I2C1_SDA - I2C4_SDA TXFD_ - FMC_NL -
CH1N EEV9 RX RX CKIN5 VSYNC OUT
MODE
Table 10. Port B alternate functions (continued)
90/356
Pin descriptions
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
Port TIM1/2/16/ SAI1/TIM3/ TIM8/ 4/UART4/5/ QUADSPI/ /SDMMC1/ TIM1/
TIM15/ SPI1/2/3/4/5/ /3/I2C4/ USART1/2/3 QUADSPI/ TIM1/8/ UART5/
SYS 17/LPTIM1/ 4/5/12/ LPTIM2/3/4 8/LPUART/ SDMMC2/ MDIOS/ DCMI/LCD SYS
LPTIM2/ 6/CEC UART4/ /6/UART7/S FMC/ DFSDM1/ LCD
HRTIM1 HRTIM1 /5/HRTIM1/ SDMMC1/ OTG1_HS/ OTG1_FS/ /COMP
DFSDM1/ DFSDM1 DMMC1 SDMMC2/ SDMMC2/
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
DFSDM1_ SDMMC1_ FDCAN1_ SDMMC2_ ETH_MII_ SDMMC1_ EVENT-

PB8 - TIM16_CH1 TIM4_CH3 I2C1_SCL - I2C4_SCL UART4_RX DCMI_D6 LCD_B6
CKIN7 CKIN RX D4 TXD3 D4 OUT
DFSDM1_ SPI2_NSS/ SDMMC1_ FDCAN1_ SDMMC2_ I2C4_ SDMMC1_ EVENT-

PB9 - TIM17_CH1 TIM4_CH4 I2C1_SDA I2C4_SDA UART4_TX DCMI_D7 LCD_B7
DATIN7 I2S2_WS CDIR TX D5 SMBA D5 OUT
HRTIM_ LPTIM2_IN SPI2_SCK/ DFSDM1_ USART3_ QUADSPI_ OTG_HS_ ETH_MII_ EVENT-

PB10 - TIM2_CH3 I2C2_SCL - - - LCD_G4
SCOUT 1 I2S2_CK DATIN7 TX BK1_NCS ULPI_D3 RX_ER OUT
ETH_MII_
HRTIM_ LPTIM2_ DFSDM1_ USART3_ OTG_HS_ TX_EN/ EVENT-
PB11 - TIM2_CH4 I2C2_SDA - - - - - LCD_G5
SCIN ETR CKIN7 RX ULPI_D4 ETH_RMII_ OUT
TX_EN
Port B
ETH_MII_ TIM1_
SPI2_NSS/ DFSDM1_ USART3_ FDCAN2_ OTG_HS_ OTG_HS_ UART5_ EVENT-
PB12 - TIM1_BKIN - - I2C2_SMBA - TXD0/ETH_ BKIN_
DS12117 Rev 7
I2S2_WS DATIN1 CK RX ULPI_D5 ID RX OUT

RMII_TXD0 COMP12
USART3_
ETH_MII_
LPTIM2_ SPI2_SCK/ DFSDM1_ CTS/ FDCAN2_ OTG_HS_ UART5_ EVENT-
PB13 - TIM1_CH1N - - - TXD1/ETH_ - -
OUT I2S2_CK CKIN1 USART3_ TX ULPI_D6 TX OUT
RMII_TXD1
NSS
USART3_ UART4_
TIM12_ TIM8_ SPI2_MISO/ DFSDM1_ RTS/ RTS/ SDMMC2_ OTG_HS_ EVENT-
PB14 - TIM1_CH2N USART1_TX - - - -
CH1 CH2N I2S2_SDI DATIN2 USART3_ UART4_ D0 DM OUT
DE DE
RTC_ TIM12_ TIM8_ SPI2_MOSI/ DFSDM1_ UART4_ SDMMC2_ OTG_HS_ EVENT-

PB15 TIM1_CH3N USART1_RX - - - - -
REFIN CH2 CH3N I2S2_SDO CKIN2 CTS D1 DP OUT
STM32H753xI
Table 11. Port C alternate functions
STM32H753xI
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ QUADSPI/ TIM1/8/ UART5/
SYS 17/LPTIM1/ 4/5/12/ LPTIM2/3/4 8/LPUART/ SDMMC2/ MDIOS/ /LCD/ SYS
HRTIM1 HRTIM1 /5/HRTIM1/ SDMMC1/ OTG1_HS/ OTG1_FS/ COMP
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
DFSDM1_ DFSDM1_ OTG_HS_ FMC_ EVENT-

PC0 - - - - - - SAI2_FS_B - - - LCD_R5
CKIN0 DATIN4 ULPI_STP SDNWE OUT
SPI2_
DFSDM1_ DFSDM1_ SAI4_SD_ SDMMC2_ MDIOS_ EVENT-
PC1 TRACED0 - SAI1_D1 MOSI/I2S2 SAI1_SD_A - SAI4_D1 ETH_MDC - -
DATIN0 CKIN4 A CK MDC OUT
_SDO
SPI2_
DFSDM1_ DFSDM1_ OTG_HS_ ETH_MII_ FMC_SDNE EVENT-
PC2 CDSLEEP - - - MISO/I2S2 - - - - -
CKIN1 CKOUT ULPI_DIR TXD2 0 OUT
_SDI
SPI2_
DFSDM1_ OTG_HS_ ETH_MII_ FMC_SDCK EVENT-
PC3 CSLEEP - - - MOSI/I2S2 - - - - - -
DATIN1 ULPI_NXT TX_CLK E0 OUT
_SDO
ETH_MII_
DS12117 Rev 7
DFSDM1_ I2S1_ SPDIFRX1 FMC_SDNE EVENT-

PC4 - - - - - - - - RXD0/ETH_ - -
CKIN2 MCK _IN3 0 OUT
RMII_RXD0
ETH_MII_
DFSDM1_ SPDIFRX1 FMC_SDCK COMP1_ EVENT-
PC5 - - SAI1_D3 - - - - SAI4_D3 RXD1/ETH_ -
DATIN2 _IN4 E0 OUT OUT
RMII_RXD1
Port C
HRTIM_CH DFSDM1_ I2S2_ USART6_ SDMMC1_ FMC_ SDMMC2_ SDMMC1_ LCD_ EVENT-
PC6 - TIM3_CH1 TIM8_CH1 - - DCMI_D0
A1 CKIN3 MCK TX D0DIR NWAIT D6 D6 HSYNC OUT
HRTIM_CH DFSDM1_ USART6_ SDMMC1_ SDMMC2_ SDMMC1_ EVENT-

PC7 TRGIO TIM3_CH2 TIM8_CH2 - I2S3_MCK FMC_NE1 SWPMI_TX DCMI_D1 LCD_G6
A2 DATIN3 RX D123DIR D7 D7 OUT
UART5_
HRTIM_CH USART6_ RTS/ FMC_NE2/ SDMMC1_ EVENT-
PC8 TRACED1 TIM3_CH3 TIM8_CH3 - - - - SWPMI_RX DCMI_D2 -
B1 CK UART5_ FMC_NCE D0 OUT
DE
UART5_ QUADSPI_ SWPMI_ SDMMC1_ EVENT-

PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - - LCD_G3 DCMI_D3 LCD_B2
CTS BK1_IO0 SUSPEND D1 OUT
HRTIM_ DFSDM1_ SPI3_SCK/ USART3_ QUADSPI_ SDMMC1_ EVENT-

PC10 - - - - UART4_TX - - DCMI_D8 LCD_R2
EEV1 CKIN5 I2S3_CK TX BK1_IO1 D2 OUT
HRTIM_ DFSDM1_ SPI3_MISO/ USART3_ QUADSPI_ SDMMC1_ EVENT-

PC11 - - - - UART4_RX - - DCMI_D4 -
FLT2 DATIN5 I2S3_SDI RX BK2_NCS D3 OUT
Pin descriptions
HRTIM_ SPI3_MOSI/ USART3_ SDMMC1_ EVENT-
PC12 TRACED3 - - - - UART5_TX - - - DCMI_D9 -
EEV2 I2S3_SDO CK CK OUT
EVENT-
PC13 - - - - - - - - - - - - - - -
OUT
91/356
Table 11. Port C alternate functions (continued)
92/356
Pin descriptions
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
EVENT-
PC14 - - - - - - - - - - - - - - -
OUT
Port C
EVENT-
PC15 - - - - - - - - - - - - - - -
OUT
Table 12. Port D alternate functions

SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
DS12117 Rev 7

CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
DFSDM1_ SAI3_SCK_ FDCAN1_ FMC_D2/ EVENT-

PD0 - - - - - - UART4_RX - - - -
CKIN6 A RX FMC_DA2 OUT
DFSDM1_ FDCAN1_ FMC_D3/ EVENT-

PD1 - - - - - SAI3_SD_A - UART4_TX - - - -
DATIN6 TX FMC_DA3 OUT
SDMMC1_ EVENT-
PD2 TRACED2 - TIM3_ETR - - - - - UART5_RX - - - DCMI_D11 -
CMD OUT
USART2_
DFSDM1_ SPI2_SCK/ CTS/ EVENT-
PD3 - - - - - - - - - FMC_CLK DCMI_D5 LCD_G7
CKOUT I2S2_CK USART2_ OUT
NSS
Port D
USART2_
HRTIM_ RTS/ FDCAN1_R EVENT-
PD4 - - - - - SAI3_FS_A - - - FMC_NOE - -
FLT3 USART2_ XFD_MODE OUT
DE
HRTIM_ USART2_ FDCAN1_T EVENT-

PD5 - - - - - - - - - FMC_NWE - -
EEV3 TX XFD_MODE OUT
STM32H753xI
SPI3_
DFSDM1_ DFSDM1_ USART2_ SAI4_SD_ FDCAN2_R SDMMC2_ FMC_ EVENT-
PD6 - - SAI1_D1 MOSI/I2S3 SAI1_SD_A SAI4_D1 DCMI_D10 LCD_B2
CKIN4 DATIN1 RX A XFD_MODE CK NWAIT OUT
_SDO
SPI1_
DFSDM1_ DFSDM1_ USART2_ SPDIFRX1_ SDMMC2_ EVENT-
PD7 - - - - MOSI/I2S1 - - FMC_NE1 - -
DATIN4 CKIN1 CK IN1 CMD OUT
_SDO
Table 12. Port D alternate functions (continued)
STM32H753xI
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
DFSDM1_ SAI3_SCK_ USART3_ SPDIFRX1_ FMC_D13/ EVENT-

PD8 - - - - - - - - - -
CKIN3 B TX IN2 FMC_DA13 OUT
DFSDM1_ USART3_ FDCAN2_R FMC_D14/ EVENT-

PD9 - - - - - SAI3_SD_B - - - - -
DATIN3 RX XFD_MODE FMC_DA14 OUT
DFSDM1_ USART3_ FDCAN2_T FMC_D15/ EVENT-

PD10 - - - - - SAI3_FS_B - - - - LCD_B3
CKOUT CK XFD_MODE FMC_DA15 OUT
USART3_
LPTIM2_ CTS/ QUADSPI_ EVENT-
PD11 - - - I2C4_SMBA - - - SAI2_SD_A - FMC_A16 - -
IN2 USART3_N BK1_IO0 OUT
SS
Port D
USART3_
LPTIM2_ RTS/ QUADSPI_ EVENT-
DS12117 Rev 7
PD12 - LPTIM1_IN1 TIM4_CH1 I2C4_SCL - - - SAI2_FS_A - FMC_A17 - -

IN1 USART3_ BK1_IO1 OUT
DE
LPTIM1_ QUADSPI_ SAI2_SCK_ EVENT-

PD13 - TIM4_CH2 - I2C4_SDA - - - - FMC_A18 - -
OUT BK1_IO3 A OUT
SAI3_MCLK UART8_ FMC_D0/ EVENT-

PD14 - - TIM4_CH3 - - - - - - - - -
_B CTS FMC_DA0 OUT
UART8_
SAI3_MCLK RTS/ FMC_D1/ EVENT-
PD15 - - TIM4_CH4 - - - - - - - - -
_A UART8_ FMC_DA1 OUT
DE
Pin descriptions
93/356
Table 13. Port E alternate functions
94/356
Pin descriptions
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
Port TIM1/2/16/1 SAI1/TIM3/ TIM8/ 4/UART4/5/ QUADSPI/ /SDMMC1/ TIM1/DCMI
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
FDCAN1_
LPTIM1_ HRTIM_ LPTIM2_ SAI2_ EVENT-
PE0 - TIM4_ETR - - - UART8_RX RXFD_ - FMC_NBL0 DCMI_D2 -
ETR SCIN ETR MCLK_A OUT
MODE
FDCAN1_
HRTIM_ EVENT-
PE1 - LPTIM1_IN2 - - - - - UART8_TX TXFD_ - - FMC_NBL1 DCMI_D3 -
SCOUT OUT
MODE
TRACE SAI1_MCLK SAI4_ QUADSPI_ ETH_MII_ EVENT-

PE2 - SAI1_CK1 - - SPI4_SCK - SAI4_CK1 FMC_A23 - -
CLK _A MCLK_A BK1_IO2 TXD3 OUT
SAI4_SD_ EVENT-
PE3 TRACED0 - - - TIM15_BKIN - SAI1_SD_B - - - - FMC_A19 - -
B OUT
DFSDM1_ TIM15_CH1 EVENT-

PE4 TRACED1 - SAI1_D2 SPI4_NSS SAI1_FS_A - SAI4_FS_A - SAI4_D2 - FMC_A20 DCMI_D4 LCD_B0
DATIN3 N OUT
DS12117 Rev 7
DFSDM1_ SPI4_ SAI1_SCK_ SAI4_SCK EVENT-

PE5 TRACED2 - SAI1_CK2 TIM15_CH1 - - SAI4_CK2 - FMC_A21 DCMI_D6 LCD_G0
CKIN3 MISO A _A OUT
TIM1_ SPI4_ SAI4_SD_ SAI2_ TIM1_BKIN EVENT-

PE6 TRACED3 SAI1_D1 - TIM15_CH2 SAI1_SD_A - SAI4_D1 FMC_A22 DCMI_D7 LCD_G1
BKIN2 MOSI A MCLK_B 2_COMP12 OUT
Port E
DFSDM1_ QUADSPI_ FMC_D4/ EVENT-

PE7 - TIM1_ETR - - - - UART7_RX - - - - -
DATIN2 BK2_IO0 FMC_DA4 OUT
DFSDM1_ QUADSPI_ FMC_D5/ COMP2_ EVENT-

PE8 - TIM1_CH1N - - - - UART7_TX - - - -
CKIN2 BK2_IO1 FMC_DA5 OUT OUT
UART7_
DFSDM1_ RTS/ QUADSPI_ FMC_D6/ EVENT-
PE9 - TIM1_CH1 - - - - - - - - -
CKOUT UART7_ BK2_IO2 FMC_DA6 OUT
DE
DFSDM1_ UART7_ QUADSPI_ FMC_D7/ EVENT-

PE10 - TIM1_CH2N - - - - - - - - -
DATIN4 CTS BK2_IO3 FMC_DA7 OUT
DFSDM1_ FMC_D8/ EVENT-

PE11 - TIM1_CH2 - - SPI4_NSS - - - - SAI2_SD_B - - LCD_G3
CKIN4 FMC_DA8 OUT
DFSDM1_ SAI2_SCK_ FMC_D9/ COMP1_ EVENT-

PE12 - TIM1_CH3N - - SPI4_SCK - - - - - LCD_B4
DATIN5 B FMC_DA9 OUT OUT
DFSDM1_ SPI4_ FMC_D10/ COMP2_ EVENT-
STM32H753xI
PE13 - TIM1_CH3 - - - - - - SAI2_FS_B - LCD_DE
CKIN5 MISO FMC_DA10 OUT OUT
Table 13. Port E alternate functions (continued)
STM32H753xI
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
SPI4_ SAI2_ FMC_D11/ EVENT-

PE14 - TIM1_CH4 - - - - - - - - - LCD_CLK
MOSI MCLK_B FMC_DA11 OUT
Port E
TIM1_BKIN
FMC_D12/ _COMP12/ EVENT-
PE15 - TIM1_BKIN - - - - - - - - - LCD_R7
FMC_DA12 COMP_ OUT
TIM1_BKIN
DS12117 Rev 7
Pin descriptions
95/356
Table 14. Port F alternate functions
96/356
Pin descriptions
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
EVENT-
PF0 - - - - I2C2_SDA - - - - - - - FMC_A0 - -
OUT
EVENT-
PF1 - - - - I2C2_SCL - - - - - - - FMC_A1 - -
OUT
EVENT-
PF2 - - - - I2C2_SMBA - - - - - - - FMC_A2 - -
OUT
EVENT-
PF3 - - - - - - - - - - - - FMC_A3 - -
OUT
EVENT-
PF4 - - - - - - - - - - - - FMC_A4 - -
OUT
EVENT-
DS12117 Rev 7
PF5 - - - - - - - - - - - - FMC_A5 - -
OUT
SAI4_SD_ QUADSPI_ EVENT-

PF6 - TIM16_CH1 - - - SPI5_NSS SAI1_SD_B UART7_RX - - - - -
B BK1_IO3 OUT
SAI1_MCLK SAI4_ QUADSPI_ EVENT-

PF7 - TIM17_CH1 - - - SPI5_SCK UART7_TX - - - - -
_B MCLK_B BK1_IO2 OUT
Port F
UART7_
TIM16_ SPI5_ SAI1_SCK_ RTS/ SAI4_SCK TIM13_ QUADSPI_ EVENT-
PF8 - - - - - - - -
CH1N MISO B UART7_ _B CH1 BK1_IO0 OUT
DE
TIM17_ SPI5_ UART7_ TIM14_CH QUADSPI_ EVENT-

PF9 - - - - SAI1_FS_B SAI4_FS_B - - - -
CH1N MOSI CTS 1 BK1_IO1 OUT
TIM16_ QUADSPI_ EVENT-

PF10 - SAI1_D3 - - - - - - SAI4_D3 - - DCMI_D11 LCD_DE
BKIN CLK OUT
SPI5_ FMC_ EVENT-

PF11 - - - - - - - - - SAI2_SD_B - DCMI_D12 -
MOSI SDNRAS OUT
EVENT-
PF12 - - - - - - - - - - - - FMC_A6 - -
OUT
DFSDM1_ EVENT-
PF13 - - - I2C4_SMBA - - - - - - - FMC_A7 - -
DATIN6 OUT
STM32H753xI
DFSDM1_ EVENT-
PF14 - - - I2C4_SCL - - - - - - - FMC_A8 - -
CKIN6 OUT
EVENT-
PF15 - - - - I2C4_SDA - - - - - - - FMC_A9 - -
OUT
Table 15. Port G alternate functions
STM32H753xI
SAI4/
I2C1/2/3/4/ FDCAN1/2/ SAI2/4/TIM8/ I2C4/UART7
LPUART/ SPI6/SAI2/ TIM1/8/FMC
USART1/ SPI2/3/SAI1 SPI2/3/6/ TIM13/14/ QUADSPI/ /SWPMI1/
Port TIM1/2/16/ SAI1/TIM3/ TIM8/ 4/UART4/5/ /SDMMC1/ TIM1/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ QUADSPI/ SDMMC2/ TIM1/8/ UART5/
SYS 17/LPTIM1/ 4/5/12/ LPTIM2/3/4 8/LPUART/ MDIOS/ DCMI/LCD SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ FMC/ OTG1_HS/ DFSDM1/ LCD
HRTIM1 HRTIM1 /5/HRTIM1/ SDMMC1/ OTG1_FS/ /COMP
DFSDM1/ DFSDM1 SDMMC1 SDMMC2/ OTG2_FS/ SDMMC2/
DFSDM1 SPDIFRX1 LCD
CEC LCD/ LCD MDIOS/ETH
SPDIFRX1
EVENT
PG0 - - - - - - - - - - - - FMC_A10 - -
-OUT
EVENT
PG1 - - - - - - - - - - - - FMC_A11 - -
-OUT
TIM8_BKIN_ EVENT
PG2 - - - TIM8_BKIN - - - - - - - FMC_A12 - -
COMP12 -OUT
TIM8_ TIM8_BKIN2 EVENT

PG3 - - - - - - - - - - FMC_A13 - -
BKIN2 _COMP12 -OUT
TIM1_ TIM1_BKIN2 FMC_A14/ EVENT

PG4 - - - - - - - - - - - -
BKIN2 _COMP12 FMC_BA0 -OUT
FMC_A15/ EVENT
DS12117 Rev 7
PG5 - TIM1_ETR - - - - - - - - - - - -
FMC_BA1 -OUT
TIM17_ HRTIM_ QUADSPI_ DCMI_ LCD_ EVENT

PG6 - - - - - - - - - FMC_NE3
BKIN CHE1 BK1_NCS D12 R7 -OUT
HRTIM_ SAI1_ USART6_ DCMI_ LCD_ EVENT

PG7 - - - - - - - - - FMC_INT
CHE2 MCLK_A CK D13 CLK -OUT
Port G
USART6_
RTS/ SPDIFRX1 ETH_PPS_ FMC_ LCD_ EVENT
PG8 - - - TIM8_ETR - SPI6_NSS - - - -
USART6_ _IN3 OUT SDCLK G7 -OUT
DE
SPI1_
USART6_ SPDIFRX1 QUADSPI_ FMC_NE2/ DCMI_ EVENT
PG9 - - - - - MISO/I2S1 - SAI2_FS_B - -
RX _IN4 BK2_IO2 FMC_NCE VSYNC -OUT
_SDI
HRTIM_ SPI1_NSS/ LCD_ EVENT

PG10 - - - - - - - LCD_G3 SAI2_SD_B - FMC_NE3 DCMI_D2
FLT5 I2S1_WS B2 -OUT
ETH_MII_
HRTIM_ SPI1_SCK/ SPDIFRX1 TX_EN/ LCD_ EVENT
PG11 - LPTIM1_IN2 - - - - - SDMMC2_D2 - DCMI_D3
EEV4 I2S1_CK _IN1 ETH_RMII_ B3 -OUT
TX_EN
USART6_
Pin descriptions
ETH_MII_
HRTIM_ SPI6_ RTS/ SPDIFRX1 LCD_ EVENT
PG12 - LPTIM1_IN1 - - LCD_B4 - TXD1/ETH_ FMC_NE4 -
EEV5 MISO USART6_ _IN2 B1 -OUT
RMII_TXD1
DE
USART6_
ETH_MII_
LPTIM1_ HRTIM_ CTS/ LCD_ EVENT
PG13 TRACED0 - - SPI6_SCK - - - - TXD0/ETH_ FMC_A24 -
OUT EEV10 USART6_ R0 -OUT
RMII_TXD0
97/356
NSS
Table 15. Port G alternate functions (continued)
98/356
Pin descriptions
SAI4/
I2C1/2/3/4/ FDCAN1/2/ SAI2/4/TIM8/ I2C4/UART7
LPUART/ SPI6/SAI2/ TIM1/8/FMC
USART1/ SPI2/3/SAI1 SPI2/3/6/ TIM13/14/ QUADSPI/ /SWPMI1/
Port TIM1/2/16/ SAI1/TIM3/ TIM8/ 4/UART4/5/ /SDMMC1/ TIM1/
TIM15/ SPI1/2/3/4/ /3/I2C4/ USART1/2/ QUADSPI/ SDMMC2/ TIM1/8/ UART5/
SYS 17/LPTIM1/ 4/5/12/ LPTIM2/3/4 8/LPUART/ MDIOS/ DCMI/LCD SYS
LPTIM2/ 5/6/CEC UART4/ 3/6/UART7/ FMC/ OTG1_HS/ DFSDM1/ LCD
HRTIM1 HRTIM1 /5/HRTIM1/ SDMMC1/ OTG1_FS/ /COMP
DFSDM1/ DFSDM1 SDMMC1 SDMMC2/ OTG2_FS/ SDMMC2/
DFSDM1 SPDIFRX1 LCD
CEC LCD/ LCD MDIOS/ETH
SPDIFRX1
ETH_MII_
LPTIM1_ SPI6_ USART6_ QUADSPI_ LCD_ EVENT
PG14 TRACED1 - - - - - TXD1/ETH_ FMC_A25 -
ETR MOSI TX BK2_IO3 B0 -OUT
RMII_TXD1
Port G
USART6_
CTS/ FMC_ DCMI_ EVENT
PG15 - - - - - - - - - - - -
USART6_ SDNCAS D13 -OUT
NSS
DS12117 Rev 7
STM32H753xI
Table 16. Port H alternate functions
STM32H753xI
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
EVENT-
PH0 - - - - - - - - - - - - - - -
OUT
EVENT-
PH1 - - - - - - - - - - - - - - -
OUT
QUADSPI_ SAI2_SCK_ ETH_MII_ FMC_ EVENT-

PH2 - LPTIM1_IN2 - - - - - - - - LCD_R0
BK2_IO0 B CRS SDCKE0 OUT
QUADSPI_ SAI2_ ETH_MII_ FMC_ EVENT-

PH3 - - - - - - - - - - LCD_R1
BK2_IO1 MCLK_B COL SDNE0 OUT
OTG_HS_ EVENT-
PH4 - - - - I2C2_SCL - - - - LCD_G5 - - - LCD_G4
ULPI_NXT OUT
FMC_ EVENT-
DS12117 Rev 7
PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - - -

SDNWE OUT
TIM12_ ETH_MII_ FMC_ EVENT-

PH6 - - - I2C2_SMBA SPI5_SCK - - - - - DCMI_D8 -
CH1 RXD2 SDNE1 OUT
SPI5_ ETH_MII_ FMC_ EVENT-

PH7 - - - - I2C3_SCL - - - - - DCMI_D9 -
MISO RXD3 SDCKE1 OUT
Port H
DCMI_ EVENT-
PH8 - - TIM5_ETR - I2C3_SDA - - - - - - - FMC_D16 LCD_R2
HSYNC OUT
TIM12_ EVENT-
PH9 - - - I2C3_SMBA - - - - - - - FMC_D17 DCMI_D0 LCD_R3
CH2 OUT
EVENT-
PH10 - - TIM5_CH1 - I2C4_SMBA - - - - - - - FMC_D18 DCMI_D1 LCD_R4
OUT
EVENT-
PH11 - - TIM5_CH2 - I2C4_SCL - - - - - - - FMC_D19 DCMI_D2 LCD_R5
OUT
EVENT-
PH12 - - TIM5_CH3 - I2C4_SDA - - - - - - - FMC_D20 DCMI_D3 LCD_R6
OUT
TIM8_ FDCAN1_ EVENT-

PH13 - - - - - - - UART4_TX - - FMC_D21 - LCD_G2
CH1N TX OUT
Pin descriptions
TIM8_ FDCAN1_ EVENT-
PH14 - - - - - - - UART4_RX - - FMC_D22 DCMI_D4 LCD_G3
CH2N RX OUT
FDCAN1_
TIM8_ EVENT-
PH15 - - - - - - - - TXFD_ - - FMC_D23 DCMI_D11 LCD_G4
CH3N OUT
MODE
99/356
Table 17. Port I alternate functions
100/356
Pin descriptions
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
FDCAN1_
SPI2_NSS/ EVENT-
PI0 - - TIM5_CH4 - - - - - RXFD_ - - FMC_D24 DCMI_D13 LCD_G5
I2S2_WS OUT
MODE
TIM8_ SPI2_SCK/ TIM8_BKIN EVENT-

PI1 - - - - - - - - - FMC_D25 DCMI_D8 LCD_G6
BKIN2 I2S2_CK 2_COMP12 OUT
SPI2_
EVENT-
PI2 - - - TIM8_CH4 - MISO/I2S2 - - - - - - FMC_D26 DCMI_D9 LCD_G7
OUT
_SDI
SPI2_
EVENT-
PI3 - - - TIM8_ETR - MOSI/I2S2 - - - - - - FMC_D27 DCMI_D10 -
OUT
_SDO
SAI2_ TIM8_BKIN EVENT-

DS12117 Rev 7
PI4 - - - TIM8_BKIN - - - - - - FMC_NBL2 DCMI_D5 LCD_B4

MCLK_A _COMP12 OUT
SAI2_SCK_ DCMI_ EVENT-

PI5 - - - TIM8_CH1 - - - - - - - FMC_NBL3 LCD_B5
A VSYNC OUT
EVENT-
PI6 - - - TIM8_CH2 - - - - - - SAI2_SD_A - FMC_D28 DCMI_D6 LCD_B6
OUT
EVENT-
Port I
PI7 - - - TIM8_CH3 - - - - - - SAI2_FS_A - FMC_D29 DCMI_D7 LCD_B7

OUT
EVENT-
PI8 - - - - - - - - - - - - - - -
OUT
FDCAN1_ LCD_ EVENT-

PI9 - - - - - - - - UART4_RX - - FMC_D30 -
RX VSYNC OUT
FDCAN1_
ETH_MII_ LCD_ EVENT-
PI10 - - - - - - - - - RXFD_ - FMC_D31 -
RX_ER HSYNC OUT
MODE
OTG_HS_ EVENT-
PI11 - - - - - - - - - LCD_G6 - - - -
ULPI_DIR OUT
LCD_ EVENT-
PI12 - - - - - - - - - - - - - -
HSYNC OUT
LCD_ EVENT-
STM32H753xI
PI13 - - - - - - - - - - - - - -
VSYNC OUT
EVENT-
PI14 - - - - - - - - - - - - - - LCD_CLK
OUT
EVENT-
PI15 - - - - - - - - - LCD_G2 - - - - LCD_R0
OUT
Table 18. Port J alternate functions
STM32H753xI
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
EVENT-
PJ0 - - - - - - - - - LCD_R7 - - - - LCD_R1
OUT
EVENT-
PJ1 - - - - - - - - - - - - - - LCD_R2
OUT
EVENT-
PJ2 - - - - - - - - - - - - - - LCD_R3
OUT
EVENT-
PJ3 - - - - - - - - - - - - - - LCD_R4
OUT
EVENT-
PJ4 - - - - - - - - - - - - - - LCD_R5
OUT
EVENT-
DS12117 Rev 7
PJ5 - - - - - - - - - - - - - - LCD_R6
OUT
EVENT-
PJ6 - - - TIM8_CH2 - - - - - - - - - - LCD_R7
OUT
TIM8_ EVENT-
PJ7 TRGIN - - - - - - - - - - - - LCD_G0
CH2N OUT
Port J
EVENT-
PJ8 - TIM1_CH3N - TIM8_CH1 - - - - UART8_TX - - - - - LCD_G1
OUT
TIM8_ EVENT-
PJ9 - TIM1_CH3 - - - - - UART8_RX - - - - - LCD_G2
CH1N OUT
SPI5_ EVENT-
PJ10 - TIM1_CH2N - TIM8_CH2 - - - - - - - - - LCD_G3
MOSI OUT
TIM8_ SPI5_ EVENT-

PJ11 - TIM1_CH2 - - - - - - - - - - LCD_G4
CH2N MISO OUT
EVENT-
PJ12 TRGOUT - - - - - - - - LCD_G3 - - - - LCD_B0
OUT
EVENT-
PJ13 - - - - - - - - - LCD_B4 - - - - LCD_B1
OUT
Pin descriptions
EVENT-
PJ14 - - - - - - - - - - - - - - LCD_B2
OUT
EVENT-
PJ15 - - - - - - - - - - - - - - LCD_B3
OUT
101/356
Table 19. Port K alternate functions
102/356
Pin descriptions
SAI4/ I2C4/
SAI2/4/
I2C1/2/3/4/ FDCAN1/2/ UART7/
CEC LCD/ MDIOS/
LCD
SPDIFRX1 ETH
EVENT-
PK0 - TIM1_CH1N - TIM8_CH3 - SPI5_SCK - - - - - - - - LCD_G5
OUT
TIM8_ EVENT-
PK1 - TIM1_CH1 - - SPI5_NSS - - - - - - - - LCD_G6
CH3N OUT
TIM8_BKIN TIM1_BKIN EVENT-

PK2 - TIM1_BKIN - TIM8_BKIN - - - - - - - - LCD_G7
_COMP12 _COMP12 OUT
EVENT-
PK3 - - - - - - - - - - - - - - LCD_B4
OUT
Port K
EVENT-
PK4 - - - - - - - - - - - - - - LCD_B5
OUT
EVENT-
DS12117 Rev 7
PK5 - - - - - - - - - - - - - - LCD_B6
OUT
EVENT-
PK6 - - - - - - - - - - - - - - LCD_B7
OUT
EVENT-
PK7 - - - - - - - - - - - - - - LCD_DE
OUT
STM32H753xI
STM32H753xI Electrical characteristics (rev Y)
6 Electrical characteristics (rev Y)
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 12.
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 13.
Figure 12. Pin loading conditions Figure 13. Pin input voltage
MCU pin MCU pin
C = 50 pF VIN
MS19011V2 MS19010V2
DS12117 Rev 7 103/356

321
Electrical characteristics (rev Y) STM32H753xI
Figure 14. Power supply scheme
100 nF
100 nF
VDD33USB VDD50USB
VDD33USB VDD50USB
VSS USB
IOs
USB
VDDLDO VSS
regulator
VCAP
2 x 2.2μF
Core domain (VCORE)

VDDLDO Voltage
4..7μF
regulator
Power
Power
switch
switch
VSS
D3 domain
(System
Level shifter
logic, D1 domain
IO EXTI, D2 domain (CPU, peripherals,
IOs (peripherals, RAM)
logic Peripherals,
RAM) RAM) Flash
VDD
VSS
N(1) x 100 nF
VDD domain
+ 1 x 4.7 μF
HSI, CSI,
VDD
HSI48,
VBAT HSE, PLLs Backup domain
charging
VBAT VSW Backup VBKP
1.2 to 3.6V VBAT regulator
Power switch
Power switch
LSI, LSE,
RTC, Wakeup
Backup
logic, backup
BKUP IO RAM
registers,
IOs logic Reset
VREF
VDDA VSS
VDDA VSS
Analog domain
100 nF + 1 x 1 μF
100 nF + 1 x 1 μF
REF_BUF ADC, DAC

VREF+ VREF+ OPAMP,
VREF- Comparator
VREF-
VSSA
MSv46116V3
1. N corresponds to the number of VDD pins available on the package.

2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
104/356 DS12117 Rev 7

device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
6.1.7 Current consumption measurement
Figure 15. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics,
Table 21: Current characteristics, and Table 22: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 20. Voltage characteristics (1)

Symbols Ratings Min Max Unit
External main supply voltage (including VDD,

VDDX - VSS −0.3 4.0 V
VDDLDO, VDDA, VDD33USB, VBAT)
Min(VDD, VDDA,
Input voltage on FT_xxx pins VSS−0.3 VDD33USB, VBAT) V
+4.0(3)(4)
VIN(2) Input voltage on TT_xx pins VSS-0.3 4.0 V
Input voltage on BOOT0 pin VSS 9.0 V
Input voltage on any other pins VSS-0.3 4.0 V
Variations between different VDDX power pins
|∆VDDX| - 50 mV
of the same domain
|VSSx-VSS| Variations between all the different ground pins - 50 mV
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 58 for the maximum allowed injected current
values.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
DS12117 Rev 7 105/356

321
Table 21. Current characteristics

Symbols Ratings Max Unit
ΣIVDD Total current into sum of all VDD power lines (source)(1) 620
(1)
ΣIVSS Total current out of sum of all VSS ground lines (sink) 620
(1)
IVDD Maximum current into each VDD power pin (source) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
IIO Output current sunk by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins (2)
140 mA
ΣI(PIN)
Total output current sourced by sum of all I/Os and control pins(2) 140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
−5/+0
IINJ(PIN)(3)(4) PA5
Injected current on PA4, PA5 −0/0
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 22. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range − 65 to +150

°C
TJ Maximum junction temperature 125
106/356 DS12117 Rev 7

6.3 Operating conditions
6.3.1 General operating conditions
Table 23. General operating conditions

Symbol Parameter Operating conditions Min Max Unit
VDD (1)
Standard operating voltage - 1.62 3.6
VDDLDO Supply voltage for the internal regulator VDDLDO ≤ VDD 1.62(1) 3.6
USB used 3.0 3.6
VDD33USB Standard operating voltage, USB domain
USB not used 0 3.6
ADC or COMP used 1.62
DAC used 1.8
OPAMP used 2.0
VDDA Analog operating voltage 3.6 V
VREFBUF used 1.8
ADC, DAC, OPAMP,
COMP, VREFBUF not 0
used
TT_xx I/O −0.3 VDD+0.3
BOOT0 0 9
VIN I/O Input voltage
Min(VDD, VDDA,
All I/O except BOOT0
−0.3 VDD33USB) +3.6V
and TT_xx
< 5.5V(2)(3)
TFBGA240+25 - - 1093
LQFP208 - - 943
LQFP176 - - 930
Power dissipation at UFBGA176+25 - - 1070

PD mW
TA = 85 °C for suffix 6(4) UFBGA169 - - 1061
LQFP144 - - 915
LQFP100 - - 889
TFBGA100 - - 1018
Ambient temperature for Maximum power dissipation –40 85

the suffix 6 version Low-power dissipation(5) –40 105
TA °C
Ambient temperature for Maximum power dissipation –40 125
the suffix 3 version Low-power dissipation(5) –40 130
Junction temperature
TJ Suffix 6 version –40 125 °C
range
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
DS12117 Rev 7 107/356

321
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 8.9: Thermal characteristics).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.9:
Thermal characteristics).
6.3.2 VCAP external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP pin. CEXT is specified in Table 24. Two external capacitors can be connected to
VCAP pins.
Figure 16. External capacitor CEXT
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
Table 24. VCAP operating conditions(1)

Symbol Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF(2)

ESR ESR of external capacitor < 100 mΩ
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
6.3.3 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.
Table 25. Operating conditions at power-up / power-down (regulator ON)

Symbol Parameter Min Max Unit
VDD rise time rate 0 ∞

tVDD
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
tVDDA µs/V
VDDA fall time rate 10 ∞
VDDUSB rise time rate 0 ∞
tVDDUSB
VDDUSB fall time rate 10 ∞
108/356 DS12117 Rev 7

6.3.4 Embedded reset and power control block characteristics

The parameters given in Table 26 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 23: General operating
conditions.
Table 26. Reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit
Reset temporization
tRSTTEMPO(1) - - 377 - µs
after BOR0 released
Rising edge(1) 1.62 1.67 1.71
VBOR0 Brown-out reset threshold 0
Falling edge 1.58 1.62 1.68
Rising edge 2.04 2.10 2.15
Rising edge 2.34 2.41 2.47
Rising edge 2.63 2.70 2.78
Programmable Voltage Rising edge 1.90 1.96 2.01

VPVD0
Detector threshold 0 Falling edge 1.81 1.86 1.91

VPVD1 V

VPVD2

VPVD3

VPVD4

VPVD5

VPVD6
Detector threshold 6 Falling edge in Run mode 2.69 2.76 2.83
Hysteresis voltage of BOR
Vhyst_BOR_PVD Hysteresis in Run mode - 100 - mV
(unless BOR0) and PVD
BOR(2) (unless BOR0) and
IDD_BOR_PVD(1) - - 0.630 µA
PVD consumption from VDD
DS12117 Rev 7 109/356

321
Table 26. Reset and power control block characteristics (continued)

Analog voltage detector for Rising edge 1.66 1.71 1.76

VAVM_0
VDDA threshold 0 Falling edge 1.56 1.61 1.66

VAVM_1
V
VAVM_2

VAVM_3
Hysteresis of VDDA voltage
Vhyst_VDDA - - 100 - mV
detector
PVM consumption from
IDD_PVM - - - 0.25 µA
VDD(1)
Voltage detector
IDD_VDDA Resistor bridge - - 2.5 µA
consumption on VDDA(1)
1. Guaranteed by design.
2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to
Section 6.3.6: Supply current characteristics).
6.3.5 Embedded reference voltage

temperature and VDD supply voltage conditions summarized in Table 23: General operating
conditions.
Table 27. Embedded reference voltage

-40°C < TJ < 105°C,
VREFINT Internal reference voltages 1.180 1.216 1.255 V
VDD = 3.3 V
ADC sampling time when
tS_vrefint(1)(2) reading the internal reference - 4.3 - -
voltage
µs
VBAT sampling time when
tS_vbat(1)(2) reading the internal VBAT - 9 - -
reference voltage
Reference Buffer
Irefbuf(2) VDDA=3.3 V 9 13.5 23 µA
consumption for ADC
Internal reference voltage
ΔVREFINT(2) spread over the temperature -40°C < TJ < 105°C - 5 15 mV
range
Average temperature Average temperature
Tcoeff(2) - 20 70 ppm/°C
coefficient coefficient
VDDcoeff(2) Average Voltage coefficient 3.0V < VDD < 3.6V - 10 1370 ppm/V
110/356 DS12117 Rev 7

Table 27. Embedded reference voltage (continued)

VREFINT_DIV1 1/4 reference voltage - - 25 -
%
VREFINT
1. The shortest sampling time for the application can be determined by multiple iterations.
Table 28. Internal reference voltage calibration values

Symbol Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1E860 - 1FF1E861
6.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 15: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (frcc_c_ck) frequency and VCORE range” available in the reference manual).
• When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in Table 29 to Table 37 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 23: General
operating conditions.
DS12117 Rev 7 111/356

321
running from ITCM, regulator ON(1)
Max(2)
frcc_c_ck
Symbol Parameter Conditions Typ TJ = TJ = TJ = TJ = unit
(MHz)
25°C 85°C 105°C 125°C
400 71 110 210 290 540
VOS1
300 56 - - - -
300 50 72 170 230 370
VOS2 216 37 58 150 210 380
200 35.5 - - - -
All
peripherals 200 33 50 130 190 300
disabled
180 30 47 130 180 290
Supply 168 28 45 130 180 290
IDD current in Run VOS3 mA
mode 144 25 41 120 180 290
60 13 28 110 160 280
25 10 24 99 160 270
400 165 220(3) 400 500(3) 840
VOS1
300 130 - - - -
All
peripherals 300 120 170 300 390 570
enabled VOS2
200 83 - - - -
VOS3 200 78 110 220 300 470
1. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.
2. Guaranteed by characterization results unless otherwise specified.
3. Guaranteed by test in production.
112/356 DS12117 Rev 7

running from Flash memory, cache ON, regulator ON
Max(1)
frcc_c_ck
(MHz)
25°C 85°C 105°C 125°C
400 105 160 310 420 750
VOS1
300 55 - - - -
300 50 72 160 230 370
VOS2 216 38 - - - -
200 36 - - - -
All
peripherals 200 33 50 130 190 300
disabled
180 30 - - - -
Supply 168 29 - - - -
IDD current in Run VOS3 mA
mode 144 26 - - - -
60 14 - - - -
25 14 - - - -
400 160 220 400 500 750
VOS1
300 130 - - - -
All
peripherals 300 120 160 300 390 560
enabled VOS2
200 81 - - - -
VOS3 200 77 110 220 300 460
1. Guaranteed by characterization results unless otherwise specified.
running from Flash memory, cache OFF, regulator ON
Max(1)
frcc_c_ck
(MHz)
25°C 85°C 105°C 125°C
VOS1 400 73 110 220 290 540
All
peripherals VOS2 300 52 75 170 230 370
Supply disabled
VOS3 200 34 52 130 190 300
IDD current in Run mA
mode VOS1 400 135 190 360 470 730
All
peripherals VOS2 300 100 150 270 370 550
enabled
VOS3 200 70 100 210 300 460
1. Guaranteed by characterization results.
DS12117 Rev 7 113/356

321
Table 32. Typical consumption in Run mode and corresponding performance

versus code position
Conditions frcc_c_ck IDD/
Symbol Parameter CoreMark Typ Unit Unit
Peripheral Code (MHz) CoreMark
ITCM 400 2012 71 35

FLASH
400 2012 105 52
All A
peripherals
AXI
disabled, 400 2012 105 52
SRAM
cache ON
SRAM1 400 2012 105 52
Supply current SRAM4 400 2012 105 52 µA/

IDD mA
in Run mode ITCM 400 2012 71 35 CoreMark
FLASH
400 593 70.5 119
All A
peripherals
AXI
disabled 400 344 70.5 205
SRAM
cache OFF
SRAM1 400 472 74.5 158
SRAM4 400 432 72 167
Table 33. Typical current consumption batch acquisition mode

frcc_ahb_ck(AHB4)
Symbol Parameter Conditions Typ unit
(MHz)
D1Standby,
Supply current in D2Standby, VOS3 64 6.5
IDD batch acquisition D3Run mA
mode D1Stop, D2Stop,
VOS3 64 12
D3Run
Table 34. Typical and maximum current consumption in Sleep mode, regulator ON
Max(1)
frcc_c_ck
(MHz)
25°C 85°C 105°C 125°C
400 31.0 64 220 330 660
VOS1
300 24.5 57 210 330 650
Supply All
IDD(Sleep) current in peripherals 300 22.0 48 180 270 500 mA
Sleep mode disabled VOS2
200 17.0 42 170 270 490
VOS3 200 15.5 37 150 230 400
114/356 DS12117 Rev 7

Table 35. Typical and maximum current consumption in Stop mode, regulator ON
Max(1)
25°C 85°C 105°C 125°C
Flash SVOS5 1.4 7.2(2) 49 75(2) 140
memory in
SVOS4 1.95 11 66 110 200
low-power
D1Stop, mode, no
SVOS3 2.85 16(2) 91 150(2) 240
D2Stop, IWDG
D3Stop SVOS5 1.65 7.2 49 75 140
Flash
memory ON, SVOS4 2.2 11 66 110 180
no IWDG
SVOS3 3.15 16 91 150 300
Flash SVOS5 0.99 5.1 35 60 97
memory
SVOS4 1.4 7.5 47 79 130
OFF, no
D1Stop, IWDG SVOS3 2.05 12 64 110 170
IDD(Stop) mA
D2Standby,
D3Stop SVOS5 1.25 5.5 35 61 98
Flash
memory ON, SVOS4 1.65 7.8 47 80 130
no IWDG
SVOS3 2.3 12 65 110 170
SVOS5 0.57 3 21 36 57
D1Standby,
D2Stop, SVOS4 0.805 4.5 27 47 74
D3Stop
Flash OFF, SVOS3 1.2 6.7 37 63 99
no IWDG SVOS5 0.17 1.1(2)
8 13(2) 20
D1Standby,
D2Standby, SVOS4 0.245 1.5 11 17 26
D3Stop
SVOS3 0.405 2.4(2) 15 23(2) 35
Table 36. Typical and maximum current consumption in Standby mode

Conditions Typ(3) Max (3 V)(1)
Symbol Parameter Backup RTC TJ = TJ = TJ = TJ = Unit
1.62 V 2.4 V 3V 3.3 V
SRAM & LSE 25°C 85°C 105°C 125°C
OFF OFF 1.8 1.9 1.95 2.05 4(2) 18(3) 40(2) 90(3)
Supply
IDD current in ON OFF 3.4 3.4 3.5 3.7 8.2(3) 47(3) 83(3) 141(3)
µA
(Standby) Standby OFF ON 2.4 3.5 3.86 4.12 - - - -
mode
ON ON 3.95 5.1 5.46 5.97 - - - -
1. The maximum current consumption values are given for PDR OFF (internal reset OFF). When the PDR is OFF (internal
reset OFF), the current consumption is reduced by 1.2 µA compared to PDR ON.
DS12117 Rev 7 115/356

321
Table 37. Typical and maximum current consumption in VBAT mode

Conditions Typ(1) Max (3 V)
Symbol Parameter Backup RTC & TJ = TJ = TJ = TJ = Unit
1.2 V 2V 3V 3.4 V
SRAM LSE 25°C 85°C 105°C 125°C
OFF OFF 0.024 0.035 0.062 0.096 0.5(1) 4.1(1) 10(1) 24(1)
Supply
IDD current in ON OFF 1.4 1.6 1.8 1.8 4.4(1) 22(1) 48(1) 87(1)
µA
(VBAT) standby OFF ON 0.24 0.45 0.62 0.73 - - - -
mode
ON ON 1.97 2.37 2.57 2.77 - - - -
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 59: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 38: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
I SW = V DDx × f SW × C L
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT
116/356 DS12117 Rev 7

The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption

• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• The I/O compensation cell is enabled.
• frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
– frcc_c_ck = 400 MHz (Scale 1), frcc_c_ck = 300 MHz (Scale 2),
frcc_c_ck = 200 MHz (Scale 3)
• The ambient operating temperature is 25 °C and VDD=3.3 V.
DS12117 Rev 7 117/356

321
Table 38. Peripheral current consumption in Run mode

IDD(Typ)
Peripheral Unit
VOS1 VOS2 VOS3
MDMA 8.3 7.6 7

DMA2D 21 20 18
JPEG 24 23 21
FLASH 9.9 9 8.3
FMC registers 0.9 0.9 0.8
FMC kernel 6.1 5.5 5.3
QUADSPI
1.5 1.4 1.3
registers
AHB3 QUADSPI kernel 0.9 0.8 0.7
SDMMC1
8 7.2 6.8
registers
SDMMC1 kernel 2.4 2 1.8
DTCM1 5.7 5 4.5
DTCM2 5.5 4.8 4.3
ITCM 3.2 2.9 2.6
D1SRAM1 7.6 6.8 6.1
AHB3 bridge 7.5 6.8 6.3
µA/MHz
DMA1 1.1 1 1
DMA2 1.7 1.4 1.1
ADC1/2 registers 3.9 3.2 3.1
ADC1/2 kernel 0.9 0.8 0.7
ART accelerator 5.5 4.5 4.2
ETH1MAC
ETH1TX 16 14 13
ETH1RX
AHB1
USB1 OTG
15 14 13
registers
USB1 OTG kernel - 8.5 8.5
USB1 ULPI 0.3 0.3 0.1
USB2 OTG
15 13 12
registers
USB2 OTG kernel - 8.6 8.6
USB2 ULPI 16 16 16
AHB1 Bridge 10 9.6 8.6
118/356 DS12117 Rev 7

Table 38. Peripheral current consumption in Run mode (continued)

IDD(Typ)
Peripheral Unit
VOS1 VOS2 VOS3
DCMI 1.7 1.7 1.7

CRYP 0.1 0.1 0.1
HASH 0.1 0.1 0.1
RNG registers 1.8 1.4 1.2
RNG kernel - 9.6 9.6
SDMMC2
AHB2 13 12 11
registers
SDMMC2 kernel 2.7 2.5 2.4
D2SRAM1 3.3 3.1 2.8
D2SRAM2 2.9 2.7 2.5
D2SRAM3 1.9 1.8 1.7
AHB2 bridge 0.1 0.1 0.1
GPIOA 1.1 1 0.9
GPIOB 1 0.9 0.9
GPIOC 1.4 1.3 1.3 µA/MHz
GPIOD 1.1 1 0.9
GPIOE 1 0.9 0.8
GPIOF 0.9 0.8 0.8
GPIOG 0.9 0.7 0.7
GPIOH 1 0.9 0.9
AHB4 GPIOI 0.9 0.9 0.8
GPIOJ 0.9 0.8 0.8
GPIOK 0.9 0.8 0.7
CRC 0.5 0.4 0.4
BDMA 6.2 5.8 5.5
ADC3 registers 1.8 1.7 1.7
ADC3 kernel 0.1 0.1 0.1
Backup SRAM 1.9 1.8 1.8
Bridge AHB4 0.1 0.1 0.1
LCD-TFT 12 11 10
APB3 WWDG1 0.5 0.4 0.3 µA/MHz
APB3 bridge 0.5 0.2 0.1
DS12117 Rev 7 119/356

321

IDD(Typ)
Peripheral Unit
VOS1 VOS2 VOS3
TIM2 3.5 3.2 2.9

TIM3 3.4 3.1 2.7
TIM4 2.7 2.5 1.9
TIM5 3.2 2.9 2.5
TIM6 1 0.8 0.7
TIM7 1 0.9 0.7
TIM12 1.7 1.5 1.2
TIM13 1.5 1.3 1
TIM14 1.4 1.3 0.9
LPTIM1 registers 0.7 0.6 0.5
LPTIM1 kernel 2.3 2.1 1.9
WWDG2 0.6 0.4 0.4
APB1 SPI2 registers 1.8 1.5 1.2 µA/MHz
SPI2 kernel 0.6 0.5 0.5

SPI3 registers 1.5 1.3 1.1
SPI3 kernel 0.6 0.5 0.5
SPDIFRX1
0.6 0.5 0.3
registers
SPDIFRX1 kernel 2.9 2.4 2.4
USART2 registers 1.4 1.3 1
USART2 kernel 4.7 4.1 4
USART3 registers 1.4 1.3 1
USART3 kernel 4.2 3.8 3.5
UART4 registers 1.5 1.1 1
UART4 kernel 3.7 3.6 3.2
120/356 DS12117 Rev 7


IDD(Typ)
Peripheral Unit
VOS1 VOS2 VOS3
UART5 registers 1.4 1.4 1

UART5 kernel 3.6 3.2 3.1
I2C1 registers 0.8 0.8 0.6
I2C1 kernel 2 1.8 1.7
I2C2 kernel 1.9 1.7 1.6
I2C3 kernel 2.1 1.9 1.9
HDMI-CEC
0.5 0.3 0.3
registers
DAC1/2 1.4 1.1 0.9
USART7 registers 1.9 1.8 1.3
APB1
µA/MHz
(continued) USART7 kernel 4 3.5 3.3
USART8 kernel 4 3.6 3.3
CRS 3.4 3.1 2.9
SWPMI registers 2.3 2 2
SWPMI kernel 0.1 0.1 0.1
OPAMP 0.5 0.4 0.4
MDIO 2.7 2.4 2.3
FDCAN registers 16 15 14
FDCAN kernel 7.8 7.6 7.1
Bridge APB1 0.1 0.1 0.1
DS12117 Rev 7 121/356

321

IDD(Typ)
Peripheral Unit
VOS1 VOS2 VOS3
TIM1 5.1 4.8 4.3

TIM8 5.4 4.9 4.6
SPI1 kernel 1 0.8 0.6
SPI4 kernel 0.5 0.4 0.4
TIM15 3.1 2.8 2.7
TIM16 2.4 2.1 2.1
APB2 TIM17 2.2 2 1.9 µA/MHz
SPI5 kernel 0.6 0.5 0.3
SAI1 registers 1.5 1.4 1.4
SAI1 kernel 2 1.7 1.5
SAI2 kernel 2.2 1.9 1.8
SAI3 kernel 2.5 2.3 2.1
DFSDM1 registers 6 5.4 5.2
DFSDM1 kernel 0.9 0.8 0.7
HRTIM 40 37 35
Bridge APB2 0.1 0.1 0.1
122/356 DS12117 Rev 7


IDD(Typ)
Peripheral Unit
VOS1 VOS2 VOS3
SYSCFG 1 0.7 0.7

LPUART1
1.1 1.1 1.1
registers
LPUART1 kernel 2.6 2.4 2.1
SPI6 kernel 0.2 0.2 0.2
I2C4 kernel 2.4 2.1 2
LPTIM2 kernel 2.3 2.1 1.8
APB4 LPTIM3 kernel 2 2.1 1.5 µA/MHz

LPTIM4 kernel 2 2 1.9
LPTIM5 kernel 2 1.8 1.5
COMP1/2 0.7 0.5 0.5
VREFBUF 0.6 0.4 0.4
RTC 1.2 1.1 1.1
SAI4 kernel 1.3 1.3 1.2
Bridge APB4 0.1 0.1 0.1
Table 39. Peripheral current consumption in Stop, Standby and VBAT mode
Typ
Symbol Parameter Conditions Unit
3V
RTC+LSE low drive - 2.32
RTC+LSE medium-
- 2.4
low drive
IDD µA
RTC+LSE medium-
- 2.7
high drive
RTC+LSE High drive - 3
DS12117 Rev 7 123/356

321
6.3.7 Wakeup time from low-power modes

The wakeup times given in Table 40 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
Table 40. Low-power mode wakeup timings

Symbol Parameter Conditions Typ(1) Max(1) Unit
CPU
tWUSLEEP(2) Wakeup from Sleep - 9 10 clock
cycles
VOS3, HSI, Flash memory in normal mode 4.4 5.6
VOS3, HSI, Flash memory in low-power
12 15
mode
VOS4, HSI, Flash memory in normal mode 15 20
23 28
mode
38 47
mode
tWUSTOP(2) Wakeup from Stop
VOS3, CSI, Flash memory in normal mode 27 37
VOS3, CSI, Flash memory in low power
36 50
mode µs
VOS4, CSI, Flash memory in low-power
47 61
mode
62 77
mode
Wakeup from Stop, VOS3, HSI, Flash memory in normal mode 2.6 3.4
tWUSTOP2(2)
clock kept running VOS3, CSI, Flash memory in normal mode 26 36
Wakeup from Standby

tWUSTDBY(2) - 390 500
mode

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
124/356 DS12117 Rev 7

6.3.8 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 59: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 17.
Table 41. High-speed external user clock characteristics(1)

Symbol Parameter Min Typ Max Unit
fHSE_ext User external clock source frequency 4 25 50 MHz

VSW
OSC_IN amplitude 0.7VDD - VDD
(VHSEH − VHSEL) V
VDC OSC_IN input voltage VSS - 0.3VSS
tW(HSE) OSC_IN high or low time 7 - - ns
Figure 17. High-speed external clock source AC timing diagram
VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t
THSE
External fHSE_ext
IL
clock source OSC_IN
STM32
ai17528b
DS12117 Rev 7 125/356

321
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 59: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 18.
Table 42. Low-speed external user clock characteristics(1)

fLSE_ext User external clock source frequency - - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx
V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 18. Low-speed external clock source AC timing diagram
VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t
TLSE
External fLSE_ext
OSC32_IN IL
clock source
STM32
ai17529b
126/356 DS12117 Rev 7

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 43. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 43. 4-48 MHz HSE oscillator characteristics(1)

Operating
conditions(2)
F Oscillator frequency - 4 - 48 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 4
VDD=3 V, Rm=30 Ω
- 0.35 -
CL=10pF@4MHz
VDD=3 V, Rm=30 Ω
- 0.40 -
CL=10 pF at 8 MHz
IDD(HSE) HSE current consumption VDD=3 V, Rm=30 Ω mA
- 0.45 -
CL=10 pF at 16 MHz
VDD=3 V, Rm=30 Ω
- 0.65 -
CL=10 pF at 32 MHz
VDD=3 V, Rm=30 Ω
- 0.95 -
CL=10 pF at 48 MHz
Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V
tSU (4) Start-up time VDD is stabilized - 2 - ms
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 19). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
DS12117 Rev 7 127/356

321
Figure 19. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain
REXT(1) OSC_OU T STM32

CL2
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

Symbol Parameter Operating conditions(2) Min Typ Max Unit
F Oscillator frequency - - 32.768 - kHz

LSEDRV[1:0] = 00,
- 290 -
Low drive capability
LSEDRV[1:0] = 01,
- 390 -
LSE current Medium Low drive capability
IDD nA
consumption LSEDRV[1:0] = 10,
- 550 -
Medium high drive capability
LSEDRV[1:0] = 11,
- 900 -
High drive capability
LSEDRV[1:0] = 00,
- - 0.5
LSEDRV[1:0] = 01,
- - 0.75
Maximum critical crystal Medium Low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10,
- - 1.7
LSEDRV[1:0] = 11,
- - 2.7
tSU(3) Startup time VDD is stabilized - 2 - s
128/356 DS12117 Rev 7

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
Figure 20. Typical application with a 32.768 kHz crystal
Resonator with
CL1
OSC32_IN fLSE
Bias
32.768 kH z RF controlled
resonator
gain
OSC32_OU T STM32
CL2
ai17531b
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
6.3.9 Internal clock source characteristics

The parameters given in Table 45 and Table 48 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 23: General
48 MHz high-speed internal RC oscillator (HSI48)
Table 45. HSI48 oscillator characteristics

fHSI48 HSI48 frequency VDD=3.3 V, TJ=30 °C 47.5(1) 48 48.5(1) MHz

(2)
TRIM USER trimming step - - 0.17 - %
USER TRIM
USER TRIMMING Coverage ± 32 steps - ±5.45 - %
COVERAGE(3)
DuCy(HSI48)(2) Duty Cycle - 45 - 55 %
Accuracy of the HSI48 oscillator over VDD=1.62 to 3.6 V,
ACCHSI48_REL(3) –4.5 - 3.5 %
temperature (factory calibrated) TJ=-40 to 125 °C
HSI48 oscillator frequency drift with VDD=3 to 3.6 V - 0.025 0.05

∆VDD(HSI48)(3) %
VDD(4) VDD=1.62 V to 3.6 V - 0.05 0.1
tsu(HSI48)(2) HSI48 oscillator start-up time - - 2.1 3.5 µs
IDD(HSI48)(2) HSI48 oscillator power consumption - - 350 400 µA
Next transition jitter
NT jitter - - ± 0.15 - ns
Accumulated jitter on 28 cycles(5)
Paired transition jitter
PT jitter - - ± 0.25 - ns
DS12117 Rev 7 129/356

321

3. Guaranteed by characterization.
4. These values are obtained by using the formula:
(Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) / Freq(1.62V).
5. Jitter measurements are performed without clock source activated in parallel.
64 MHz high-speed internal RC oscillator (HSI)
Table 46. HSI oscillator characteristics(1)

fHSI HSI frequency VDD=3.3 V, TJ=30 °C 63.7(2) 64 64.3(2) MHz

Trimming is not a multiple
- 0.24 0.32
of 32
Trimming is 128, 256 and
−5.2 −1.8 -
384
TRIM HSI user trimming step Trimming is 64, 192, 320 %

−1.4 −0.8 -
and 448
Other trimming are a
multiple of 32 (not
−0.6 −0.25 -
including multiple of 64
and 128)
DuCy(HSI) Duty Cycle - 45 - 55 %
HSI oscillator frequency drift over
ΔVDD (HSI) VDD=1.62 to 3.6 V −0.12 - 0.03 %
VDD (reference is 3.3 V)
HSI oscillator frequency drift over TJ=-20 to 105 °C −1(3) - 1(3) %

ΔTEMP (HSI)
temperature (reference is 64 MHz) TJ=−40 to TJmax °C −2(3) - 1(3)
tsu(HSI) HSI oscillator start-up time - - 1.4 2 µs
tstab(HSI) HSI oscillator stabilization time at 1% of target frequency - 4 8 µs
IDD(HSI) HSI oscillator power consumption - - 300 400 µA
1. Guaranteed by design unless otherwise specified.
4 MHz low-power internal RC oscillator (CSI)
Table 47. CSI oscillator characteristics(1)

fCSI CSI frequency VDD=3.3 V, TJ=30 °C 3.96(2) 4 4.04(2) MHz

TRIM Trimming step - - 0.35 - %
DuCy(CSI) Duty Cycle - 45 - 55 %
130/356 DS12117 Rev 7

Table 47. CSI oscillator characteristics(1) (continued)

(3) (3)
CSI oscillator frequency drift over TJ = 0 to 85 °C - −3.7 4.5
∆TEMP (CSI) %
temperature TJ = −40 to 125 °C - −11(3) 7.5(3)
CSI oscillator frequency drift over
DVDD (CSI) VDD = 1.62 to 3.6 V - −0.06 0.06 %
VDD
tsu(CSI) CSI oscillator startup time - - 1 2 µs
CSI oscillator stabilization time
tstab(CSI) - - 4 8 cycle
(to reach ±3% of fCSI)
IDD(CSI) CSI oscillator power consumption - - 23 30 µA
Low-speed internal (LSI) RC oscillator
Table 48. LSI oscillator characteristics

VDD = 3.3 V, TJ = 25 °C 31.4 32 32.6

fLSI(1) LSI frequency TJ = –40 to 105 °C, VDD = kHz
29.76 - 33.60
1.62 to 3.6 V
tsu(LSI)(2) LSI oscillator startup time - - 80 130
LSI oscillator stabilization µs
tstab(LSI)(2) - - 120 170
time (5% of final value)
LSI oscillator power
IDD(LSI)(2) - - 130 280 nA
consumption
6.3.10 PLL characteristics

The parameters given in Table 49 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 23: General operating conditions.
Table 49. PLL characteristics (wide VCO frequency range)(1)

PLL input clock - 2 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 10 - 90 %
DS12117 Rev 7 131/356

321
Table 49. PLL characteristics (wide VCO frequency range)(1) (continued)

(2)
VOS1 1.5 - 400
fPLL_P_OUT PLL multiplier output clock P VOS2 1.5 - 300
VOS3 1.5 - 200
VOS1 1.5 - 400(2) MHz
fPLL_Q_OUT PLL multiplier output clock Q/R VOS2 1.5 - 300
VOS3 1.5 - 200
fVCO_OUT PLL VCO output - 192 - 836
(3)
Normal mode - 50 150(3)
tLOCK PLL lock time Sigma-delta mode µs
- 58(3) 166(3)
(CKIN ≥ 8 MHz)
VCO = 192 MHz - 134 -
VCO = 200 MHz - 134 -
Cycle-to-cycle jitter(4) ±ps
VCO = 400 MHz - 76 -
VCO = 800 MHz - 39 -
Jitter
Normal mode - ±0.7 -
Long term jitter Sigma-delta mode %
- ±0.8 -
(CKIN = 16 MHz)
VCO freq = VDDA - 440 1150

420 MHz VCORE - 530 -
IDD(PLL)(3) PLL power consumption on VDD µA
150 MHz VCORE - 200 -
2. This value must be limited to the maximum frequency due to the product limitation (400 MHz for VOS1, 300 MHz for VOS2,
200 MHz for VOS3).
4. Integer mode only.
Table 50. PLL characteristics (medium VCO frequency range)(1)


fPLL_IN
VOS1 1.17 - 210
PLL multiplier output clock P, Q,
fPLL_OUT VOS2 1.17 - 210 MHz
R
VOS3 1.17 - 200
fVCO_OUT PLL VCO output - 150 - 420 MHz
Normal mode - 60(2) 100(2) µs
tLOCK PLL lock time
Sigma-delta mode forbidden - - µs
132/356 DS12117 Rev 7

Table 50. PLL characteristics (medium VCO frequency range)(1) (continued)

VCO =
- 145 -
150 MHz
VCO =
- 91 -
300 MHz +/-
Cycle-to-cycle jitter(3) -
VCO = ps
- 64 -
400 MHz
VCO =
- 63 -
420 MHz
VCO =
Jitter - 55 -
fPLL_OUT = 150 MHz +/-
Period jitter
50 MHz VCO = ps
- 30 -
400 MHz
VCO =
- - -
150 MHz
VCO =
Long term jitter Normal mode - - - %
300 MHz
VCO =
- +/-0.3 -
400 MHz
VCO freq = VDD - 440 1150

420MHz VCORE - 530 -
I(PLL)(2) PLL power consumption on VDD µA
6.3.11 Memory characteristics

Flash memory
The characteristics are given at TJ = –40 to 125 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 51. Flash memory characteristics

Write / Erase 8-bit mode - 6.5 -

IDD Supply current mA
Write / Erase 32-bit mode - 20 -
DS12117 Rev 7 133/356

321
Table 52. Flash memory programming (single bank configuration nDBANK=1)

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Program/erase parallelism x 8 - 290 580(2)
Word (266 bits) programming Program/erase parallelism x 16 - 180 360

tprog µs
time Program/erase parallelism x 32 - 130 260
Program/erase parallelism x 64 - 100 200
tERASE128KB Sector (128 KB) erase time Program/erase parallelism x 16 - 1.8 3.6
Program/erase parallelism x 32 -
Program/erase parallelism x 8 - 13 26 s
tME Mass erase time
Program parallelism x 8
Program parallelism x 16 1.62 - 3.6
Vprog Programming voltage V
2. The maximum programming time is measured after 10K erase operations.
Table 53. Flash memory endurance and data retention

Value
Min(1)
NEND Endurance TJ = –40 to +125 °C (6 suffix versions) 10 kcycles

Data retention 1 kcycle at TA = 85 °C 30
tRET Years
10 kcycles at TA = 55 °C 20
134/356 DS12117 Rev 7

6.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 54. They are based on the EMS levels and classes
defined in application note AN1709.
Table 54. EMS characteristics

Level/
Class
Voltage limits to be applied on any I/O pin to induce

VFESD VDD = 3.3 V, TA = +25 °C, 3B
a functional disturbance
UFBGA240, frcc_c_ck =
Fast transient voltage burst limits to be applied 400 MHz, conforms to
VFTB through 100 pF on VDD and VSS pins to induce a IEC 61000-4-2 4B
functional disturbance
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as

possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
DS12117 Rev 7 135/356

321
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 55. EMI characteristics

Max vs.
Monitored [fHSE/fCPU]
frequency band
8/400 MHz
0.1 to 30 MHz 6
30 to 130 MHz 5
VDD = 3.6 V, TA = 25 °C, UFBGA240 package, dBµV
SEMI Peak level 130 MHz to 1 GHz 13
conforming to IEC61967-2
1 GHz to 2 GHz 7
EMI Level 2.5 -
6.3.13 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 56. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)
Electrostatic discharge TA = +25 °C conforming to

VESD(HBM) voltage (human body ANSI/ESDA/JEDEC JS- All 1C 1000
model) 001
V
VESD(CDM) voltage (charge device ANSI/ESDA/JEDEC JS- All C1 250
model) 002
136/356 DS12117 Rev 7

Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 57. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latchup class TA = +25 °C conforming to JESD78 II level A
6.3.14 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 58. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
5 0
PJ12, PB4
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11 0 NA
IINJ mA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
0 0
PA5, PH4, PH5, BOOT0
All other I/Os 5 NA
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6.3.15 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 59: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 23: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Table 59. I/O static characteristics

Symbol Parameter Condition Min Typ Max Unit
I/O input low level voltage except

- - 0.3VDD(1)
BOOT0
I/O input low level voltage except 0.4VDD−
VIL 1.62 V<VDDIOx<3.6 V - - V
BOOT0 0.1(2)
0.19VDD+
BOOT0 I/O input low level voltage - -
0.1(2)
I/O input high level voltage except
0.7VDD(1) - -
BOOT0
I/O input high level voltage except 0.47VDD+
VIH 1.62 V<VDDIOx<3.6 V - - V
BOOT0(3) 0.25(2)
BOOT0 I/O input high level 0.17VDD+
- -
voltage(3) 0.6(2)
TT_xx, FT_xxx and NRST I/O
- 250 -
VHYS(2) input hysteresis 1.62 V< VDDIOx <3.6 V mV
BOOT0 I/O input hysteresis - 200 -
0< VIN ≤ Max(VDDXXX)(9) - - +/-250
FT_xx Input leakage current(2) Max(VDDXXX) < VIN ≤ 5.5 V
(5)(6)(9) - - 1500
0< VIN ≤ Max(VDDXXX)(9) - - +/- 350

Ileak (4) FT_u IO Max(VDDXXX) < VIN ≤ 5.5 V nA
(5)(6)(9) - - 5000(7)
TT_xx Input leakage current 0< VIN ≤ Max(VDDXXX) (9) - - +/-250

0< VIN ≤ VDDIOX - - 15
VPP (BOOT0 alternate function)
VDDIOX < VIN ≤ 9 V 35
Weak pull-up equivalent
RPU VIN=VSS 30 40 50
resistor(8)
kΩ
Weak pull-down equivalent
RPD VIN=VDD(9) 30 40 50
resistor(8)
CIO I/O pin capacitance - - 5 - pF
1. Compliant with CMOS requirement.
3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. All FT_xx IO except FT_lu, FT_u and PC3.
138/356 DS12117 Rev 7

6. VIN must be less than Max(VDDXXX) + 3.6 V.

7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
9. Max(VDDXXX) is the maximum value of all the I/O supplies.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 21.
Figure 21. VIL/VIH for all I/Os except BOOT0
2.5
TLL requirement: VIHmin = 2 V

0.7V D
D
2 in=
V IHm
ent:
uirem
S req +0.25
CMO 0.47VDD
in=
imulation VIHm
1.5 Bas ed on s
Voltage
-0.1
0.4VDD
VILmax=
n s im ulation
1 Based
o =0.3VDD
ment: VIL
max
require
CMOS
TLL requirement: VILmin = 0.8 V
0.5
0
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
MSv46121V3
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 21).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 21).
DS12117 Rev 7 139/356

321
Output voltage levels

Unless otherwise specified, the parameters given in Table 60 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 23: General operating conditions. All I/Os are CMOS and TTL compliant.
Table 60. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1)
Symbol Parameter Conditions(3) Min Max Unit
CMOS port(2)
VOL Output low level voltage IIO=8 mA - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
VOH Output high level voltage IIO=-8 mA VDD−0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOL(3) Output low level voltage IIO=8 mA - 0.4
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOH (3) Output high level voltage IIO=-8 mA 2.4 -
2.7 V≤ VDD ≤3.6 V
V
IIO=20 mA
VOL(3) Output low level voltage - 1.3
2.7 V≤ VDD ≤3.6 V
IIO=-20 mA
VOH(3) Output high level voltage VDD−1.3 -
2.7 V≤ VDD ≤3.6 V
IIO=4 mA
1.62 V≤ VDD ≤3.6 V
IIO=-4 mA
VOH (3) Output high level voltage VDD−-0.4 -
1.62 V≤VDD<3.6 V
IIO= 20 mA
- 0.4
Output low level voltage for an FTf 2.3 V≤ VDD≤3.6 V
VOLFM+(3)
I/O pin in FM+ mode IIO= 10 mA
- 0.4
1.62 V≤ VDD ≤3.6 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 20:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
140/356 DS12117 Rev 7

Table 61. Output voltage characteristics for PC13, PC14, PC15 and PI8(1)
CMOS port(2)
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
2.7 V≤ VDD ≤3.6 V
TTL port(2)
V
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOH (3)
Output high level voltage IIO=-3 mA 2.4 -
2.7 V≤ VDD ≤3.6 V
IIO=1.5 mA
1.62 V≤ VDD ≤3.6 V
IIO=-1.5 mA
1.62 V≤ VDD ≤3.6 V
DS12117 Rev 7 141/356

321
Output buffer timing characteristics (HSLV option disabled)

The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.5 V.
Table 62. Output timing characteristics (HSLV OFF)(1)(2)

Speed Symbol Parameter conditions Min Max Unit
C=50 pF, 2.7 V≤ VDD≤3.6 V - 12

C=50 pF, 1.62 V≤VDD≤2.7 V - 3
C=30 pF, 2.7 V≤VDD≤3.6 V - 12
Fmax(3) Maximum frequency MHz
C=30 pF, 1.62 V≤VDD≤2.7 V - 3
C=10 pF, 2.7 V≤VDD≤3.6 V - 16
C=10 pF, 1.62 V≤VDD≤2.7 V - 4
00
C=50 pF, 2.7 V≤ VDD≤3.6 V - 16.6
C=50 pF, 1.62 V≤VDD≤2.7 V - 33.3
Output high to low level C=30 pF, 2.7 V≤VDD≤3.6 V - 13.3
tr/tf(4) fall time and output low ns
to high level rise time C=30 pF, 1.62 V≤VDD≤2.7 V - 25
C=10 pF, 2.7 V≤VDD≤3.6 V - 10
C=10 pF, 1.62 V≤VDD≤2.7 V - 20
C=50 pF, 2.7 V≤ VDD≤3.6 V - 60
C=50 pF, 1.62 V≤VDD≤2.7 V - 15
C=30 pF, 2.7 V≤VDD≤3.6 V - 80
C=30 pF, 1.62 V≤VDD≤2.7 V - 15
C=10 pF, 2.7 V≤VDD≤3.6 V - 110
C=10 pF, 1.62 V≤VDD≤2.7 V - 20
01
C=50 pF, 2.7 V≤ VDD≤3.6 V - 5.2
C=50 pF, 1.62 V≤VDD≤2.7 V - 10
to high level rise time C=30 pF, 1.62 V≤VDD≤2.7 V - 7.5
C=10 pF, 2.7 V≤VDD≤3.6 V - 2.8
C=10 pF, 1.62 V≤VDD≤2.7 V - 5.2
142/356 DS12117 Rev 7

Table 62. Output timing characteristics (HSLV OFF)(1)(2) (continued)

C=50 pF, 2.7 V≤VDD≤3.6 V (5)

- 85
C=50 pF, 1.62 V≤VDD≤2.7 V(5) - 35
(5)
C=30 pF, 2.7 V≤VDD≤3.6 V - 110
(5)
C=30 pF, 1.62 V≤VDD≤2.7 V - 40
C=10 pF, 2.7 V≤VDD≤3.6 V(5) - 166
C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 100
10
(5)
C=50 pF, 2.7 V≤VDD≤3.6 V - 3.8
(5)
C=50 pF, 1.62 V≤VDD≤2.7 V - 6.9
Output high to low level C=30 pF, 2.7 V≤VDD≤3.6 V(5) - 2.8
to high level rise time C=30 pF, 1.62 V≤VDD≤2.7 V(5) - 5.2
C=10 pF, 2.7 V≤VDD≤3.6 V(5) - 1.8
C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 3.3
C=50 pF, 2.7 V≤VDD≤3.6 V(5) - 100
C=50 pF, 1.62 V≤VDD≤2.7 V(5) - 50
C=30 pF, 2.7 V≤VDD≤3.6 V(5) - 133
C=30 pF, 1.62 V≤VDD≤2.7 V(5) - 66
C=10 pF, 2.7 V≤VDD≤3.6 V(5) - 220
C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 85
11
C=50 pF, 2.7 V≤VDD≤3.6 V(5) - 3.3
C=50 pF, 1.62 V≤VDD≤2.7 V(5) - 6.6
C=10 pF, 2.7 V≤VDD≤3.6 V(5) - 1.5
C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 2.7
2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz
3. The maximum frequency is defined with the following conditions:
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
5. Compensation system enabled.
DS12117 Rev 7 143/356

321
Output buffer timing characteristics (HSLV option enabled)
Table 63. Output timing characteristics (HSLV ON)(1)

C=50 pF, 1.62 V≤VDD≤2.7 V - 10

(2)
Fmax Maximum frequency C=30 pF, 1.62 V≤VDD≤2.7 V - 10 MHz
C=10 pF, 1.62 V≤VDD≤2.7 V - 10
00
C=50 pF, 1.62 V≤VDD≤2.7 V - 11
Output high to low level
tr/tf(3) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V - 9 ns
to high level rise time
C=10 pF, 1.62 V≤VDD≤2.7 V - 6.6
C=50 pF, 1.62 V≤VDD≤2.7 V - 50
(3)
C=10 pF, 1.62 V≤VDD≤2.7 V - 66
01
C=50 pF, 1.62 V≤VDD≤2.7 V - 6.6
tr/tf(4) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V - 4.8 ns
C=10 pF, 1.62 V≤VDD≤2.7 V - 3
C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 55
Fmax (3) Maximum frequency C=30 pF, 1.62 V≤VDD≤2.7 V(5) - 80 MHz
C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 133
10
C=50 pF, 1.62 V≤VDD≤2.7 V(5) - 5.8
tr/tf(4) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V(5) - 4 ns
C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 2.4
C=50 pF, 1.62 V≤VDD≤2.7 V(5) - 60
C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 175
11
C=50 pF, 1.62 V≤VDD≤2.7 V(5) - 5.3
tr/tf(4) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V(5) - 3.6 ns
to high level rise time (5)
C=10 pF, 1.62 V≤VDD≤2.7 V - 1.9
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
144/356 DS12117 Rev 7

6.3.16 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 59: I/O static characteristics).
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 23: General operating conditions.
Table 64. NRST pin characteristics


RPU(2) VIN = VSS 30 40 50 ㏀
resistor(1)
VF(NRST)(2) NRST Input filtered pulse 1.71 V < VDD < 3.6 V - - 50
1.71 V < VDD < 3.6 V 300 - - ns
VNF(NRST)(2) NRST Input not filtered pulse
1.62 V < VDD < 3.6 V 1000 - -
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
Figure 22. Recommended NRST pin protection
VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 59. Otherwise the reset is not taken into account by the device.
DS12117 Rev 7 145/356

321
6.3.17 FMC characteristics

Unless otherwise specified, the parameters given in Table 65 to Table 78 for the FMC
interface are derived from tests performed under the ambient temperature, frcc_c_ck
frequency and VDD supply voltage conditions summarized in Table 23: General operating
conditions, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings

Figure 23 through Figure 26 represent asynchronous waveforms and Table 65 through
Table 72 provide the corresponding timings. The results shown in these tables are obtained
with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capcitive load CL = 30 pF
In all timing tables, the TKERCK is the fmc_ker_ck clock period.
146/356 DS12117 Rev 7

Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE) t w(NOE) t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE) t h(A_NOE)
FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE) th(Data_NOE)
t su(Data_NE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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321
Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

tw(NE) FMC_NE low time 2Tfmc_ker_ck − 1 2 Tfmc_ker_ck +1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
th(A_NOE) Address hold time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
ns
th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time 11 -
tsu(Data_NOE) Data to FMC_NOEx high setup time 11 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1
Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1)(2)

tw(NE) FMC_NE low time 7Tfmc_ker_ck +1 7Tfmc_ker_ck +1
tw(NOE) FMC_NWE low time 5Tfmc_ker_ck −1 5Tfmc_ker_ck +1

ns
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck −0.5
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4Tfmc_ker_ck +11 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 3Tfmc_ker_ck+11.5 -
2. NWAIT pulse width is equal to 1 AHB cycle.
148/356 DS12117 Rev 7

Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)
FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

tw(NE) FMC_NE low time 3Tfmc_ker_ck − 1 3Tfmc_ker_ck
tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck Tfmc_ker_ck + 1
tw(NWE) FMC_NWE low time Tfmc_ker_ck − 0.5 Tfmc_ker_ck + 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck -
tv(A_NE) FMC_NEx low to FMC_A valid - 2
th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck − 0.5 -
ns
th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck − 0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck + 2.5
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck+0.5 -
tw(NADV) FMC_NADV low time - Tfmc_ker_ck + 1
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321
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2)

tw(NE) FMC_NE low time 8Tfmc_ker_ck − 1 8Tfmc_ker_ck + 1
tw(NWE) FMC_NWE low time 6Tfmc_ker_ck − 1.5 6Tfmc_ker_ck + 0.5 ns

tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck + 13 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck+ 13 -
Figure 25. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)
FMC_ NE
tv(NOE_NE) t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
tv(A_NE) th(A_NOE)
FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)
FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)
FMC_ AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
150/356 DS12117 Rev 7

Table 69. Asynchronous multiplexed PSRAM/NOR read timings(1)

tw(NE) FMC_NE low time 3Tfmc_ker_ck − 1 3Tfmc_ker_ck + 1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck 2Tfmc_ker_ck + 0.5
ttw(NOE) FMC_NOE low time Tfmc_ker_ck − 1 Tfmc_ker_ck + 1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Tfmc_ker_ck − 0.5 Tfmc_ker_ck+1
FMC_AD(address) valid hold time after
th(AD_NADV) Tfmc_ker_ck + 0.5 - ns
FMC_NADV high
th(A_NOE) Address hold time after FMC_NOE high Tfmc_ker_ck − 0.5 -
th(BL_NOE) FMC_BL time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck − 2 -
tsu(Data_NOE) Data to FMC_NOE high setup time Tfmc_ker_ck − 2 -
Table 70. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

tw(NE) FMC_NE low time 8Tfmc_ker_ck − 1 8Tfmc_ker_ck
tw(NOE) FMC_NWE low time 5Tfmc_ker_ck − 1.5 5Tfmc_ker_ck + 0.5 ns

FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 4Tfmc_ker_ck -
invalid
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Figure 26. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)
FMC_ NEx
FMC_NOE
FMC_NWE
tv(A_NE) th(A_NWE)

FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
Table 71. Asynchronous multiplexed PSRAM/NOR write timings(1)

tw(NE) FMC_NE low time 4Tfmc_ker_c − 1 4Tfmc_ker_ck

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_c − 1 Tfmc_ker_ck + 0.5
tw(NWE) FMC_NWE low time 2Tfmc_ker_ck− 0.5 2Tfmc_ker_ck+ 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck − 0.5 -
tw(NADV) FMC_NADV low time Tfmc_ker_ck Tfmc_ker_ck+ 1 ns
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck+0.5 -
th(A_NWE) Address hold time after FMC_NWE high Tfmc_ker_ck+0.5 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high Tfmc_ker_ck − 0.5 -
tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck + 2
152/356 DS12117 Rev 7

Table 72. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)

tw(NE) FMC_NE low time 9Tfmc_ker_ck – 1 9Tfmc_ker_ck
tw(NWE) FMC_NWE low time 7Tfmc_ker_ck – 0.5 7Tfmc_ker_ck + 0.5 ns

th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck -
Synchronous waveforms and timings

Figure 27 through Figure 30 represent synchronous waveforms and Table 73 through
Table 76 provide the corresponding timings. The results shown in these tables are obtained
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
• For 2.7 V<VDD<3.6 V, FMC_CLK =100 MHz at 20 pF
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321
Figure 27. Synchronous multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
154/356 DS12117 Rev 7

Table 73. Synchronous multiplexed NOR/PSRAM read timings(1)

tw(CLK) FMC_CLK period 2Tfmc_ker_ck − 1 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5 ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck − 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 2 -
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 1 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
DS12117 Rev 7 155/356

321
Figure 28. Synchronous multiplexed PSRAM write timings
FMC_CLK
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
FMC_A[25:16]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
td(CLKH-NBLH)
FMC_NBL
MS32758V1
156/356 DS12117 Rev 7

Table 74. Synchronous multiplexed PSRAM write timings(1)


td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.5
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
ns
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck + 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2.5
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 2.5
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck + 0.5 -
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321
Figure 29. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
MS32759V1
Table 75. Synchronous non-multiplexed NOR/PSRAM read timings(1)


t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck + 0.5 -
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Tfmc_ker_ck - ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck + 0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 2 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 1 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
158/356 DS12117 Rev 7

Figure 30. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
FMC_NWE
td(CLKL-Data) td(CLKL-Data)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
MS32760V1
Table 76. Synchronous non-multiplexed PSRAM write timings(1)

t(CLK) FMC_CLK period 2Tfmc_ker_ck − 1 -

t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck + 0.5 -
ns
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck + 1 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3.5
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck + 1 -
DS12117 Rev 7 159/356

321
NAND controller waveforms and timings

Figure 31 through Figure 34 represent synchronous waveforms, and Table 77 and Table 78
provide the corresponding timings. The results shown in this table are obtained with the
following FMC configuration:
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
• CL = 30 pF
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 31. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
td(ALE-NOE) th(NOE-ALE)
FMC_NOE (NRE)
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MS32767V1
160/356 DS12117 Rev 7

Figure 32. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) th(NWE-ALE)
FMC_NWE
FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32768V1
Figure 33. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
tw(NOE)
FMC_NOE
FMC_D[15:0]
MS32769V1
DS12117 Rev 7 161/356

321
Figure 34. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)
FMC_NWE
FMC_N OE
td(D-NWE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32770V1
Table 77. Switching characteristics for NAND Flash read cycles(1)

tw(N0E) FMC_NOE low width 4Tfmc_ker_ck –0.5 4Tfmc_ker_ck + 0.5

tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 8 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Tfmc_ker_ck + 1
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Tfmc_ker_ck − 2 -
Table 78. Switching characteristics for NAND Flash write cycles(1)

tw(NWE) FMC_NWE low width 4Tfmc_ker_ck − 0.5 4Tfmc_ker_ck + 0.5

tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2Tfmc_ker_ck − 0.5 -
ns
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5Tfmc_ker_ck − 1 -
td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3Tfmc_ker_ck + 0.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2Tfmc_ker_ck − 1 -
162/356 DS12117 Rev 7

SDRAM waveforms and timings

In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
• For 1.8 V<VDD<3.6V: FMC_CLK =100 MHz at 20 pF
• For 1.62 V<DD<1.8 V, FMC_CLK =100 MHz at 30 pF
Figure 35. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
FMC_A[12:0] Row n Col1 Col2 Coli Coln
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)
FMC_D[31:0] Data1 Data2 Datai Datan
MS32751V2
Table 79. SDRAM read timings(1)

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 0.5

tsu(SDCLKH _Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 1 -

td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 1.5
ns
th(SDCLKL_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 0.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
DS12117 Rev 7 163/356

321
Table 80. LPSDR SDRAM read timings(1)

tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 0.5

tsu(SDCLKH_Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 1.5 -
td(SDCLKL_SDNE) Chip select valid time - 2.5
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 0.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
Figure 36. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddC)
FMC_SDNE[1:0]
FMC_SDNRAS
FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_SDNWE
td(SDCLKL_Data)
td(SDCLKL_NBL) th(SDCLKL_Data)
FMC_NBL[3:0]
MS32752V2
164/356 DS12117 Rev 7

Table 81. SDRAM write timings(1)


td(SDCLKL _Data) Data output valid time - 3
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_SDNWE) SDNWE valid time - 1.5
th(SDCLKL_SDNWE) SDNWE hold time 0.5 -
ns
td(SDCLKL_ SDNE) Chip select valid time - 1.5
th(SDCLKL-_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 -
Table 82. LPSDR SDRAM write timings(1)

td(SDCLKL _Data) Data output valid time - 2.5

td(SDCLKL-SDNWE) SDNWE valid time - 2.5
th(SDCLKL-SDNWE) SDNWE hold time 0 -
ns
td(SDCLKL- SDNE) Chip select valid time - 3
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5
td(SDCLKL-SDNCAS) SDNCAS hold time 0 -
DS12117 Rev 7 165/356

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6.3.18 Quad-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 83 and Table 84 for QUADSPI
are derived from tests performed under the ambient temperature, frcc_c_ck frequency and
VDD supply voltage conditions summarized in Table 23: General operating conditions, with
the following configuration:
• I/O compensation cell enabled
• HSLV activated when VDD≤2.7 V
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 83. QUADSPI characteristics in SDR mode(1)

2.7 V ≤ VDD<3.6 V
- - 133
CL=20 pF
Fck1/TCK QUADSPI clock frequency MHz
1.62 V<VDD<3.6 V
- - 100
CL=15 pF
tw(CKH) QUADSPI clock high and low TCK/2–0.5 - TCK/2
-
tw(CKL) time TCK/2 - TCK/2 + 0.5
ts(IN) Data input setup time 1.5 - -
- ns
th(IN) Data input hold time 2 - -
tv(OUT) Data output valid time - - 1.5 2
th(OUT) Data output hold time - 0.5 - -
166/356 DS12117 Rev 7

Table 84. QUADSPI characteristics in DDR mode(1)

2.7 V<VDD<3.6 V
- - 100
QUADSPI clock CL=20 pF
Fck1/t(CK) MHz
frequency 1.62 V<VDD<3.6 V
- - 100
CL=15 pF
tw(CKH) QUADSPI clock high and TCK/2 –0.5 - TCK/2
-
tw(CKL) low time TCK/2 - TCK/2+0.5
tsr(IN), tsf(IN) Data input setup time - 2 - -
thr(IN), thf(IN) Data input hold time - 2 - -
DHHC=0 - 3.5 4 ns
tvr(OUT),
Data output valid time DHHC=1
tvf(OUT) - TCK/4+3.5 TCK/4+4
Pres=1, 2...
DHHC=0 3 - -
thr(OUT),
Data output hold time DHHC=1
thf(OUT) TCK/4+3 - -
Pres=1, 2...
Figure 37. Quad-SPI timing diagram - SDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V1
Figure 38. Quad-SPI timing diagram - DDR mode

Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output D0 D1 D2 D3 D4 D5
tsf(IN) thf(IN) tsr(IN) thr(IN)
Data input D0 D1 D2 D3 D4 D5
MSv36879V1
DS12117 Rev 7 167/356

321
6.3.19 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 86 for the delay block are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 23: General operating conditions.
Table 85. Dynamics characteristics: Delay Block characteristics(1)

tinit Initial delay - 1400 2200 2400
ps
t∆ Unit Delay - 35 40 45
6.3.20 16-bit ADC characteristics

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 23: General operating conditions.
Table 86. ADC characteristics(1)
VDDA Analog power supply - 1.62 - 3.6

VDDA ≥ 2 V 2 - VDDA
VREF+ Positive reference voltage V
VDDA< 2 V VDDA
VREF- Negative reference voltage - VSSA
BOOST = 1 - - 36
fADC ADC clock frequency 2 V ≤ VDDA ≤ 3.3 V MHz
BOOST = 0 - - 20
16-bit resolution - - 3.60(2)
Sampling rate for Fast
channels, BOOST = 1, 12-bit resolution - - 4.50(2)
fADC = 36 MHz(2)
8-bit resolution 6.00(2)
Sampling rate for Fast
fS channels, BOOST = 0, 12-bit resolution - - 2.50(2) MSPS
fADC = 20 MHz
8-bit resolution 3.30(2)
16-bit resolution - - 1.00
Sampling rate for Slow
channels, BOOST = 0, 12-bit resolution - - 1.00
fADC = 10 MHz
8-bit resolution 1.00
168/356 DS12117 Rev 7

Table 86. ADC characteristics(1) (continued)

fADC = 36 MHz - - 3.6 MHz

fTRIG External trigger frequency
16-bit resolution - - 10 1/fADC
VAIN(3) Conversion voltage range - 0 - VREF+
Common mode input VREF/2− V /2+ V
VCMIV - VREF/2 REF
voltage 10% 10%
RAIN External input impedance - - - 50 ㏀
Internal sample and hold
CADC - - 4 - pF
capacitor
tADCREG_
ADC LDO startup time - - 5 10 µs
STUP
conversion
tSTAB ADC power-up time LDO already started 1
cycle
Offset and linearity
tCAL - 165,010
calibration time
tOFF_CAL Offset calibration time - 1,280
CKMODE = 00 1.5 2 2.5
Trigger conversion latency
for regular and injected CKMODE = 01 - - 2
tLATR
channels without aborting CKMODE = 10 2.25
the conversion 1/fADC
CKMODE = 11 2.125
CKMODE = 00 2.5 3 3.5
Trigger conversion latency
for regular and injected CKMODE = 01 - - 3
tLATRINJ
channels when a regular CKMODE = 10 - - 3.25
conversion is aborted
CKMODE = 11 - - 3.125
tS Sampling time - 1.5 - 640.5
tS + 0.5 + N/2
Total conversion time
tCONV N-bit resolution (9 to 648 cycles in 14-bit
(including sampling time)
mode)
2. These values are obtained using the following formula: fS = fADC/ tCONV ,
where fADC = 36 MHz and tCONV = 1,5 cycle sampling time + tSAR sampling time.
Refer to the product reference manual for the value of tSAR depending on resolution.
3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
DS12117 Rev 7 169/356

321
Table 87. ADC accuracy(1)(2)(3)

Symbol Parameter Conditions(4) Min Typ Max Unit
Single BOOST = 1 - ±6 -
Total ended BOOST = 0 - ±8 -
ET unadjusted
error BOOST = 1 - ±10 -
Differential
BOOST = 0 - ±16 -
Single BOOST = 1 - 2 -
Differential ended BOOST = 0 - 1 -
ED linearity ±LSB
error BOOST = 1 - 8 -
Differential
BOOST = 0 - 2 -
Single BOOST = 1 - ±6 -
Integral ended BOOST = 0 - ±4 -
EL linearity
error BOOST = 1 - ±6 -
Differential
BOOST = 0 - ±4 -
Single BOOST = 1 - 11.6 -

Effective
ended BOOST = 0 - 12 -
number of
ENOB(5) bits
bits BOOST = 1 - 13.3 -
(2 MSPS) Differential
BOOST = 0 - 13.5 -
Signal-to- Single BOOST = 1 - 71.6 -

noise and ended BOOST = 0 - 74 -
SINAD(5) distortion
ratio BOOST = 1 - 81.83 -
Differential
(2 MSPS) BOOST = 0 - 83 -
Single BOOST = 1 - 72 -
Signal-to- ended BOOST = 0 - 74 -
SNR(5) noise ratio dB
(2 MSPS) BOOST = 1 - 82 -
Differential
BOOST = 0 - 83 -
Single BOOST = 1 - −78 -

Total ended BOOST = 0 - −80 -
THD(5) harmonic
distortion BOOST = 1 - −90 -
Differential
BOOST = 0 - −95 -
1. Guaranteed by characterization for BGA packages, the values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. The above table gives the ADC performance in 16-bit mode.
4. ADC clock frequency ≤ 36 MHz, 2 V ≤ VDDA ≤3.3 V, 1.6 V ≤ VREF ≤ VDDA, BOOSTEN (for I/O) = 1.
5. ENOB, SINAD, SNR and THD are specified for VDDA = VREF = 3.3 V.
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
170/356 DS12117 Rev 7

being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.14 does not affect the ADC accuracy.
Figure 39. ADC accuracy characteristics (12-bit resolution)

V REF+ V DDA
[1LSB IDEAL = (or depending on package)]
4096 4096
EG
4095
4094
4093
(2)
ET
7 (3)
(1)
6
5
EO EL
4
3
ED
2
1L SBIDEAL
1
0
1 2 3 456 7 4093 4094 4095 4096
V SSA VDDA
ai14395c
1. Example of an actual transfer curve.

2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
DS12117 Rev 7 171/356

321
Figure 40. Typical connection diagram using the ADC
VDD STM32
Sample and hold ADC
VT converter
0.6 V
RAIN(1) AINx RADC(1)
12-bit
converter
VT
VAIN
0.6 V C ADC(1)
Cparasitic
IL±1 μA
ai17534b
1. Refer to Table 86 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
172/356 DS12117 Rev 7

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 41 or Figure 42,
depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 41. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32
VREF+(1)
1 μF // 100 nF
VDDA
1 μF // 100 nF
VSSA/VREF+(1)
MSv50648V1
1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and
TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.
Figure 42. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32
VREF+/VDDA(1)
1 μF // 100 nF
VREF-/VSSA(1)
MSv50649V1
DS12117 Rev 7 173/356

321
6.3.21 DAC electrical characteristics
Table 88. DAC characteristics(1)

VDDA Analog supply voltage - 1.8 3.3 3.6

VREF+ Positive reference voltage - 1.80 - VDDA
V
Negative reference
VREF- - - VSSA -
voltage
connected to
5 - -
DAC output VSSA
RL Resistive Load
buffer ON connected to
25 - - ㏀
VDDA
RO(2) Output Impedance DAC output buffer OFF 10.3 13 16
VDD = 2.7 V - - 1.6

Output impedance sample
DAC output
RBON and hold mode, output
buffer ON ㏀
buffer ON VDD = 2.0 V - - 2.6
VDD = 2.7 V - - 17.8

Output impedance sample
DAC output
RBOFF and hold mode, output
buffer OFF ㏀
buffer OFF
VDD = 2.0 V - - 18.7
CL(2) DAC output buffer OFF - - 50 pF

Capacitive Load
CSH (2) Sample and Hold mode - 0.1 1 µF
VREF+
Voltage on DAC_OUT DAC output buffer ON 0.2 -
VDAC_OUT −0.2 V
output
DAC output buffer OFF 0 - VREF+
Settling time (full scale: for
a 12-bit code transition
between the lowest and
the highest input codes Normal mode, DAC output buffer
tSETTLING - 1.7(2) 2(2) µs
when DAC_OUT reaches OFF, ±1LSB CL=10 pF
the final value of ±0.5LSB,
±1LSB, ±2LSB, ±4LSB,
±8LSB)
Wakeup time from off
state (setting the Enx bit in Normal mode, DAC output buffer
tWAKEUP(3) - 5 7.5 µs
the DAC Control register) ON, CL ≤ 50 pF, RL = 5 ㏀
until the ±1LSB final value
Middle code offset for 1 VREF+ = 3.6 V - 850 -

Voffset(2) µV
trim code step VREF+ = 1.8 V - 425 -
174/356 DS12117 Rev 7

Table 88. DAC characteristics(1) (continued)

No load, middle
- 360 -
DAC output code (0x800)
buffer ON No load, worst
- 490 -
code (0xF1C)
DAC quiescent
IDDA(DAC) No load,
consumption from VDDA DAC output
middle/worst - 20 -
buffer OFF
code (0x800)
Sample and Hold mode, 360*TON/
- -
CSH=100 nF (TON+TOFF)
No load, middle
- 170 - µA
DAC output code (0x800)
buffer ON No load, worst
- 170 -
code (0xF1C)
No load,
DAC consumption from DAC output
IDDV(DAC) middle/worst - 160 -
VREF+ buffer OFF
code (0x800)
Sample and Hold mode, Buffer 170*TON/
- -
ON, CSH=100 nF (worst code) (TON+TOFF)
Sample and Hold mode, Buffer 160*TON/
- -
OFF, CSH=100 nF (worst code) (TON+TOFF)
3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
Table 89. DAC accuracy(1)

Differential non DAC output buffer ON - ±2 -

DNL LSB
linearity(2) DAC output buffer OFF - ±2 -
DAC output buffer ON, CL ≤ 50 pF,

- ±4 -
RL ≥ 5 ㏀
(3)
INL Integral non linearity LSB
DAC output buffer OFF,
- ±4 -
CL ≤ 50 pF, no RL
DAC output VREF+ = 3.6 V - - ±12

buffer ON,
Offset error at code CL ≤ 50 pF,
Offset RL ≥ 5 ㏀ VREF+ = 1.8 V - - ±25 LSB
0x800 (3)

- - ±8
CL ≤ 50 pF, no RL
DS12117 Rev 7 175/356

321
Table 89. DAC accuracy(1) (continued)

Offset error at code DAC output buffer OFF,

Offset1 - - ±5 LSB
0x001(4) CL ≤ 50 pF, no RL

Offset error at code buffer ON,
OffsetCal 0x800 after factory LSB
CL ≤ 50 pF,
calibration VREF+ = 1.8 V - - ±7
RL ≥ 5 ㏀
DAC output buffer ON,CL ≤ 50 pF,

- - ±1
RL ≥ 5 ㏀
Gain Gain error(5) %
- - ±1
CL ≤ 50 pF, no RL

TUE Total unadjusted error - - ±12 LSB
CL ≤ 50 pF, no RL

SNR Signal-to-noise ratio(6) - 67.8 - dB
RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz
Signal-to-noise and DAC output buffer ON, CL ≤ 50 pF,

SINAD - 67.5 - dB
distortion ratio(6) RL ≥ 5 ㏀ , 1 kHz
Effective number of DAC output buffer ON,

ENOB - 10.9 - bits
bits CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is -0.5dBFS with Fsampling=1 MHz.
176/356 DS12117 Rev 7

Figure 43. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RL
12-bit DAC_OUTx
digital to
analog
converter
CL
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
6.3.22 Voltage reference buffer characteristics
Table 90. VREFBUF characteristics(1)

VSCALE = 000 2.8 3.3 3.6
VSCALE = 001 2.4 - 3.6
Normal mode
VSCALE = 010 2.1 - 3.6
VSCALE = 011 1.8 - 3.6
VDDA Analog supply voltage
VSCALE = 000 1.62 - 2.80
VSCALE = 001 1.62 - 2.40
Degraded mode
VSCALE = 010 1.62 - 2.10
VSCALE = 011 1.62 - 1.80
VSCALE = 000 - 2.5 -
VSCALE = 001 - 2.048 - V
Normal mode
VSCALE = 010 - 1.8 -
VSCALE = 011 - 1.5 -
VDDA−
VREFBUF Voltage Reference VSCALE = 000 - VDDA
150 mV
_OUT Buffer Output
VDDA−
VSCALE = 001 - VDDA
150 mV
(2)
Degraded mode
VDDA−
VSCALE = 010 - VDDA
150 mV
VDDA−
VSCALE = 011 - VDDA
150 mV
TRIM Trim step resolution - - - ±0.05 ±0.2 %
CL Load capacitor - - 0.5 1 1.50 uF
DS12117 Rev 7 177/356

321
Table 90. VREFBUF characteristics(1) (continued)

Equivalent Serial
esr
Resistor of CL
- - - - 2 Ω
Iload Static load current - - - - 4 mA

Iload = 500 µA - 200 -
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V ppm/V
Iload = 4 mA - 100 -
ppm/
Iload_reg Load regulation 500 µA ≤ ILOAD ≤ 4 mA Normal Mode - 50 -
mA
Tcoeff
ppm/
Tcoeff Temperature coefficient −40 °C < TJ < +125 °C - - - xVREFINT
°C
+ 75
DC - - 60 -
PSRR Power supply rejection dB
100KHz - - 40 -
CL=0.5 µF - - 300 -
tSTART Start-up time CL=1 µF - - 500 - µs
CL=1.5 µF - - 650 -
Control of maximum
DC current drive on
IINRUSH - - 8 - mA
VREFBUF_OUT during
startup phase(3)
ILOAD = 0 µA - - 15 25
VREFBUF
IDDA(VRE
consumption from ILOAD = 500 µA - - 16 30 µA
FBUF) VDDA
ILOAD = 4 mA - - 32 50
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
6.3.23 Temperature sensor characteristics
Table 91. Temperature sensor characteristics

TL(1) VSENSE linearity with temperature - - 3 °C

(2)
Avg_Slope Average slope - 2 - mV/°C
V30(3) Voltage at 30°C ± 5 °C - 0.62 - V
(1)
tstart_run Startup time in Run mode (buffer startup) - - 25.2
µs
(1)
tS_temp ADC sampling time when reading the temperature 9 - -
Isens(1) Sensor consumption - 0.18 0.31
µA
Isensbuf(1) Sensor buffer consumption - 3.8 6.5
178/356 DS12117 Rev 7

3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 92. Temperature sensor calibration values

Temperature sensor raw data acquired value at

TS_CAL1 0x1FF1 E820 -0x1FF1 E821
30 °C, VDDA=3.3 V
TS_CAL2 0x1FF1 E840 - 0x1FF1 E841
110 °C, VDDA=3.3 V
6.3.24 Temperature and VBAT monitoring
Table 93. VBAT monitoring characteristics

R Resistor bridge for VBAT - 26 - KΩ

Q Ratio on VBAT measurement - 4 - -
(1)
Er Error on Q –10 - +10 %
tS_vbat(1) ADC sampling time when reading VBAT input 9 - - µs
VBAThigh High supply monitoring - 3.55 -
V
VBATlow Low supply monitoring - 1.36 -
Table 94. VBAT charging characteristics

VBRS in PWR_CR3= 0 - 5 -
RBC Battery charging resistor KΩ
VBRS in PWR_CR3= 1 1.5 -
Table 95. Temperature monitoring characteristics

TEMPhigh High temperature monitoring - 117 -

°C
TEMPlow Low temperature monitoring - –25 -
DS12117 Rev 7 179/356

321
6.3.25 Voltage booster for analog switch
Table 96. Voltage booster for analog switch characteristics(1)

VDD Supply voltage - 1.62 2-6 3.6 V

tSU(BOOST) Booster startup time - - - 50 µs
1.62 V ≤ VDD ≤ 2.7 V - - 125
IDD(BOOST) Booster consumption µA
2.7 V < VDD < 3.6 V - - 250
180/356 DS12117 Rev 7

6.3.26 Comparator characteristics
Table 97. COMP characteristics(1)


Comparator input voltage
VIN - 0 - VDDA V
range
VBG(2) Scaler input voltage - Refer to VREFINT
VSC Scaler offset voltage - - ±5 ±10 mV
Scaler static consumption BRG_EN=0 (bridge disable) - 0.2 0.3

IDDA(SCALER) µA
from VDDA BRG_EN=1 (bridge enable) - 0.8 1
tSTART_SCALER Scaler startup time - - 140 250 µs
High-speed mode - 2 5
Comparator startup time to
tSTART reach propagation delay Medium mode - 5 20 µs
specification
Ultra-low-power mode - 15 80
High-speed mode - 50 80 ns
Propagation delay for
200 mV step with 100 mV Medium mode - 0.5 1.2
overdrive µs
Ultra-low-power mode - 2.5 7
tD
Propagation delay for step High-speed mode - 50 120 ns
> 200 mV with 100 mV
Medium mode - 0.5 1.2
overdrive only on positive µs
inputs Ultra-low-power mode - 2.5 7
Voffset Comparator offset error Full common mode range - ±5 ±20 mV
No hysteresis - 0 -
Low hysteresis - 10 -
Vhys Comparator hysteresis mV
Medium hysteresis - 20 -
High hysteresis - 30 -
Static - 400 600
Ultra-low- With 50 kHz nA
power mode ±100 mV overdrive - 800 -
square signal
Static - 5 7
Comparator consumption
IDDA(COMP) Medium mode With 50 kHz
from VDDA ±100 mV overdrive - 6 -
square signal
µA
Static - 70 100
High-speed With 50 kHz
mode ±100 mV overdrive - 75 -
square signal
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 27: Embedded reference voltage.
DS12117 Rev 7 181/356

321
6.3.27 Operational amplifier characteristics
Table 98. OPAMP characteristics(1)

Analog supply voltage

VDDA - 2 3.3 3.6
Range
V
Common Mode Input
CMIR - 0 - VDDA
Range
25°C, no load on output - - ±1.5

VIOFFSET Input offset voltage mV
All voltages and
- - ±2.5
temperature, no load
ΔVIOFFSET Input offset voltage drift - - ±3.0 - μV/°C
Offset trim step at low
TRIMOFFSETP
common input voltage - - 1.1 1.5
TRIMLPOFFSETP (0.1*V
DDA)
mV
TRIMOFFSETN Offset trim step at high
TRIMLPOFFSETN (0.9*V
DDA)
ILOAD Drive current - - - 500

μA
ILOAD_PGA Drive current in PGA mode - - - 270

CLOAD Capacitive load - - - 50 pF
Common mode rejection

CMRR - - 80 - dB
ratio
CLOAD ≤ 50pf /
Power supply rejection
PSRR RLOAD ≥ 4 kΩ(2) at 1 kHz, 50 66 - dB
ratio
Vcom=VDDA/2
Gain bandwidth for high

GBW - 4 7.3 12.3 MHz
supply range
Slew rate (from 10% and Normal mode - 3 -

SR V/µs
90% of output voltage) High-speed mode - 30 -
AO Open loop gain - 59 90 129 dB
φm Phase margin - - 55 - °
GM Gain margin - - 12 - dB
182/356 DS12117 Rev 7

Table 98. OPAMP characteristics(1) (continued)

Iload=max or RLOAD=min(2), VDDA

VOHSAT High saturation voltage - -
Input at VDDA −100 mV
mV
Iload=max or RLOAD=min(2),
VOLSAT Low saturation voltage - - 100
Input at 0 V
CLOAD ≤ 50pf,
Normal RLOAD ≥ 4 kΩ(2),
- 0.8 3.2
mode follower
Wake up time from OFF configuration
tWAKEUP µs
state CLOAD ≤ 50pf,
High RLOAD ≥ 4 kΩ(2),
- 0.9 2.8
speed follower
configuration
- - 2 - -
- - 4 - -
Non inverting gain value
- - 8 - -
- - 16 - -
PGA gain
- - −1 - -
- - −3 - -
Inverting gain value
- - −7 - -
- - −15 - -
PGA Gain=2 - 10/10 -
R2/R1 internal resistance PGA Gain=4 - 30/10 -
values in non-inverting
PGA mode(3) PGA Gain=8 - 70/10 -
PGA Gain=16 - 150/10 -

kΩ/
Rnetwork
PGA Gain=-1 - 10/10 - kΩ
R2/R1 internal resistance PGA Gain=-3 - 30/10 -

values in inverting PGA
mode(3) PGA Gain=-7 - 70/10 -
PGA Gain=-15 - 150/10 -
Resistance variation (R1 or

Delta R - −15 - 15 %
R2)
Gain=2 - GBW/2 -
PGA bandwidth for Gain=4 - GBW/4 -

PGA BW MHz
different non inverting gain Gain=8 - GBW/8 -
Gain=16 - GBW/16 -
DS12117 Rev 7 183/356

321
Table 98. OPAMP characteristics(1) (continued)

at
- 140 -
1 KHz
output loaded nV/√
en Voltage noise density
with 4 kΩ Hz
at
- 55 -
10 KHz
Normal
- 570 1000
mode no Load,
OPAMP consumption from
IDDA(OPAMP) quiescent mode, µA
VDDA High- follower
speed - 610 1200
mode
2. RLOAD is the resistive load connected to VSSA or to VDDA.
3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
184/356 DS12117 Rev 7

6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 99 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
summarized in Table 23: General operating conditions, with the following configuration:
• Capacitive load C = 30 pF
function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for
DFSDMx).
Table 99. DFSDM measured timing 1.62-3.6 V(1)

fDFSDMCLK DFSDM clock 1.62 V < VDD < 3.6 V - - 133
SPI mode (SITP[1:0]=0,1),

External clock mode 20
- -
(SPICKSEL[1:0]=0), (fDFSDMCLK/4)
1.62 V < VDD < 3.6 V

External clock mode 20
- -
(SPICKSEL[1:0]=0), (fDFSDMCLK/4)
2.7 < VDD < 3.6 V
fCKIN Input clock SPI mode (SITP[1:0]=0,1),
(1/TCKIN) frequency Internal clock mode 20 MHz
- -
(SPICKSEL[1:0]≠0), (fDFSDMCLK/4)
1.62 < VDD < 3.6 V

Internal clock mode 20
- -
(SPICKSEL[1:0]≠0), (fDFSDMCLK/4)
2.7 < VDD < 3.6 V
Output clock
fCKOUT 1.62 < VDD < 3.6 V - - 20
frequency
Output clock
DuCyCKOUT frequency duty 1.62 < VDD < 3.6 V 45 50 55 %
cycle
DS12117 Rev 7 185/356

321
Table 99. DFSDM measured timing 1.62-3.6 V(1) (continued)


twh(CKIN) Input clock high External clock mode
TCKIN/2 - 0.5 TCKIN/2 -
twl(CKIN) and low time (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V

Data input setup External clock mode
tsu 4 - -
time (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
ns

Data input hold External clock mode
th 0.5 - -
time (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Manchester mode
Manchester data (SITP[1:0]=2,3),
(CKOUTDIV+1) (2*CKOUTDIV)
TManchester period (recovered Internal clock mode -
* TDFSDMCLK * TDFSDMCLK
clock period) (SPICKSEL[1:0]≠0),
1.62 < VDD < 3.6 V
186/356 DS12117 Rev 7

Figure 44. Channel transceiver timing diagrams
DFSDM_CKINy (SPICKSEL=0)
SPI timing : SPICKSEL = 0
twl twh tr tf
tsu th
DFSDM_DATINy
SITP = 00
tsu th
SITP = 01
SPICKSEL=3
DFSDM_CKOUT
SPICKSEL=2
SPI timing : SPICKSEL = 1, 2, 3
SPICKSEL=1
twl twh tr tf
tsu th
DFSDM_DATINy
SITP = 0
tsu th
SITP = 1
SITP = 2
DFSDM_DATINy
Manchester timing
SITP = 3
recovered clock
recovered data 0 0 1 1 0
MS30766V2
DS12117 Rev 7 187/356

321
6.3.29 Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 100 for DCMI are derived
from tests performed under the ambient temperature, frcc_c_ck frequency and VDD
supply voltage summarized in Table 23: General operating conditions, with the following
configuration:
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load C=30 pF
Table 100. DCMI characteristics(1)

- Frequency ratio DCMI_PIXCLK/frcc_c_ck - 0.4 -

DCMI_PIXCLK Pixel clock input - 80 MHz
DPixel Pixel clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 1 -
th(DATA) Data input hold time 1 -
tsu(HSYNC) ns
DCMI_HSYNC/DCMI_VSYNC input setup time 1.5 -
tsu(VSYNC)
th(HSYNC)
DCMI_HSYNC/DCMI_VSYNC input hold time 1 -
th(VSYNC)
Figure 45. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
tsu(HSYNC) th(HSYNC)
DCMI_HSYNC
tsu(VSYNC) th(HSYNC)
DCMI_VSYNC
tsu(DATA) th(DATA)
DATA[0:13]
MS32414V2
188/356 DS12117 Rev 7

6.3.30 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 101 for LCD-TFT are derived
voltage summarized in Table 23: General operating conditions, with the following
configuration:
• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
Table 101. LTDC characteristics (1)

Symbol Parameter Conditions Min Max Unit
2.7 V < VDD < 3.6 V,

- 150
20 pF
fCLK LTDC clock output frequency MHz
2.7 V < VDD < 3.6 V - 133
1.62 V < VDD < 3.6 V - 90
DCLK LTDC clock output duty cycle - 45 55 %
tw(CLKH),
Clock High time, low time tw(CLK)/2−0.5 tw(CLK)/2+0.5
tw(CLKL)
tv(DATA) Data output valid time - 0.5
th(DATA) Data output hold time 0 -
tv(HSYNC), ns
HSYNC/VSYNC/DE output valid
tv(VSYNC), - 0.5
time
tv(DE)
th(HSYNC),
HSYNC/VSYNC/DE output hold
th(VSYNC), 0.5 -
time
th(DE)
DS12117 Rev 7 189/356

321
Figure 46. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC) tv(HSYNC)
LCD_HSYNC
tv(DE) th(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7] Pixel Pixel Pixel
1 2 N
LCD_B[0:7]
th(DATA)
HSYNC Horizontal Active width Horizontal

width back porch back porch
One line
MS32749V1
Figure 47. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC) tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]
VSYNC Vertical Active width Vertical

One frame
MS32750V1
190/356 DS12117 Rev 7

6.3.31 Timer characteristics

The parameters given in Table 102 are guaranteed by design.
Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 102. TIMx characteristics(1)(2)

AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK = 1 - tTIMxCLK
200 MHz
tres(TIM) Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK = 1 - tTIMxCLK
100 MHz
Timer external clock
fEXT 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 f
TIMxCLK = 200 MHz
ResTIM Timer resolution - 16/32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
3. The maximum timer frequency on APB1 or APB2 is up to 200 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2.
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321
6.3.32 Communications interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
• Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0433 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
Table 103. Minimum i2c_ker_ck frequency in all I2C modes

Symbol Parameter Condition Min Unit
Standard-mode 2
Analog filter ON
8
DNF=0
Fast-mode
Analog filter OFF
I2CCLK 9
f(I2CCLK) DNF=1 MHz
frequency
Analog filter ON
17
DNF=0
Fast-mode Plus
Analog filter OFF
16
DNF=1
The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDD is disabled, but still present.
• The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load Cload supported in Fm+, which is given by these formulas:
tr(SDA/SCL)=0.8473xRpxCload
Rp(min)= (VDD-VOL(max))/IOL(max)
Where Rp is the I2C lines pull-up. Refer to Section 6.3.15: I/O port characteristics for
the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 104 for the analog filter
characteristics:
Table 104. I2C analog filter characteristics(1)

Maximum pulse width of spikes that

tAF 50(2) 260(3) ns
are suppressed by the analog filter
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.
192/356 DS12117 Rev 7

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 105 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 23: General operating conditions, with the
following configuration:
• HSLV activated when VDD ≤ 2.7 V
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 105. SPI dynamic characteristics(1)

Master mode
90
1.62 V≤VDD≤3.6 V
Master mode
2.7 V≤VDD≤3.6 V 133
SPI1,2,3
Master mode
2.7 V≤VDD≤3.6 V 100
SPI4,5,6
Slave receiver mode
fSCK 1.62 V≤VDD≤3.6 V 150
SPI clock frequency - - MHz
1/tc(SCK) SPI1,2,3
Slave receiver mode
1.62 V≤VDD≤3.6 V 100
SPI4,5,6
Slave mode transmitter/full
duplex 31
2.7 V≤VDD≤3.6 V
Slave mode transmitter/full
duplex 25
1.62 V≤VDD≤3.6 V
tsu(NSS) NSS setup time 2 - -
Slave mode
th(NSS) NSS hold time 1 - -
ns
tw(SCKH),
SCK high and low time Master mode TPLCK - 2 TPLCK TPLCK + 2
tw(SCKL)
DS12117 Rev 7 193/356

321
Table 105. SPI dynamic characteristics(1) (continued)

tsu(MI) Master mode 1 - -

Data input setup time
tsu(SI) Slave mode 2 - -
th(MI) Master mode 2 - -
Data input hold time
th(SI) Slave mode 1 - -
ta(SO) Data output access time Slave mode 9 13 27
tdis(SO) Data output disable time Slave mode 0 1 5 ns
Slave mode, 2.7 V≤VDD≤3.6 V - 11.5 16
tv(SO)
Data output valid time Slave mode 1.62 V≤VDD≤3.6 V - 13 20
tv(MO) Master mode - 1 3
th(SO) Slave mode, 1.62 V≤VDD≤3.6 V 9 - -
Data output hold time
th(MO) Master mode 0 - -
Figure 48. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
194/356 DS12117 Rev 7

Figure 49. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
tsu(SI) th(SI)
MSv41659V1
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Figure 50. SPI timing diagram - master mode(1)
High
NSS input
tc(SCK)
SCK Output
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136c
DS12117 Rev 7 195/356

321
I2S interface characteristics

Unless otherwise specified, the parameters given in Table 106 for the I2S interface are
function characteristics (CK, SD, WS).
Table 106. I2S dynamic characteristics(1)

fMCK I2S Main clock output - 256x8K 256FS MHz

Master data - 64FS
fCK I2S clock frequency MHz
Slave data - 64FS
tv(WS) WS valid time Master mode - 3.5
th(WS) WS hold time Master mode 0 -
tsu(WS) WS setup time Slave mode 1 -
th(WS) WS hold time Slave mode 1 -
tsu(SD_MR) Master receiver 1 -
tsu(SD_SR) Slave receiver 1 -
ns
th(SD_MR) Master receiver 4 -
th(SD_SR) Slave receiver 2 -
tv(SD_ST) Slave transmitter (after enable edge) - 20
Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 3
th(SD_ST) Slave transmitter (after enable edge) 9 -
th(SD_MT) Master transmitter (after enable edge) 0 -
196/356 DS12117 Rev 7

Figure 51. I2S slave timing diagram (Philips protocol)(1)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 52. I2S master timing diagram (Philips protocol)(1)
byte.
DS12117 Rev 7 197/356

321
SAI characteristics
Unless otherwise specified, the parameters given in Table 107 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 23: General operating conditions, with the following
configuration:
• Measurement points are performed at CMOS levels: 0.5VDD
function characteristics (SCK,SD,WS).
Table 107. SAI characteristics(1)

fMCK SAI Main clock output - 256 x 8K 256xFs MHz

Master data: 32 bits - 128xFs(3)
FCK SAI clock frequency(2) MHz
Slave data: 32 bits - 128xFs
Master mode
- 15
2.7≤VDD≤3.6V
tv(FS) FS valid time
Master mode
- 20
1.71≤VDD≤3.6V
tsu(FS) FS setup time Slave mode 7 -
Master mode 1 - ns
th(FS) FS hold time
Slave mode 1 -
tsu(SD_A_MR) Master receiver 0.5 -
tsu(SD_B_SR) Slave receiver 1 -
th(SD_A_MR) Master receiver 3.5 -
th(SD_B_SR) Slave receiver 2 -
Slave transmitter (after enable edge)
- 17
2.7≤VDD≤3.6V
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge)
- 20
1.62≤VDD≤3.6V
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 7 -
ns
Master transmitter (after enable edge)
- 17
2.7≤VDD≤3.6V
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
- 20
1.62≤VDD≤3.6V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 7.55 -
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
198/356 DS12117 Rev 7

Figure 53. SAI master timing waveforms

1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)
SAI_SD_X Slot n
(receive)
MS32771V1
Figure 54. SAI slave timing waveforms

1/fSCK
SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X Slot n
(receive)
MS32772V1
MDIO characteristics
Table 108. MDIO Slave timing parameters

FsDC Management data clock - - 40 MHz

td(MDIO) Management data input/output output valid time 7 8 20
tsu(MDIO) Management data input/output setup time 4 - - ns
th(MDIO) Management data input/output hold time 1 - -
The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at
least 1.5 times the MDC frequency: FPCLK2 ≥ 1.5 * FMDC.
DS12117 Rev 7 199/356

321
Figure 55. MDIO Slave timing diagram

tMDC)
td(MDIO)
tsu(MDIO) th(MDIO)
MSv40460V1
SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 109 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
characteristics.
Table 109. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)(2)

fPP Clock frequency in data transfer mode - 0 - 125 MHz

tW(CKL) Clock low time 9.5 10.5 -
fPP =50 MHz ns
tW(CKH) Clock high time 8.5 9.5 -
CMD, D inputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tISU Input setup time HS 2 - -

tIH Input hold time HS fPP ≥ 50 MHz 1.5 - - ns
tIDW(3) Input valid window (variable window) 3 - -
CMD, D outputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tOV Output valid time HS - 3.5 5

fPP ≥ 50 MHz ns
tOH Output hold time HS 2 - -
200/356 DS12117 Rev 7

Table 109. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)(2)

CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD 2 - -

fPP =25 MHz ns
tIHD Input hold time SD 1.5 - -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD - 1 2

fPP =25 MHz ns
tOHD Output hold default time SD 0 - -
2. Above 100 MHz, CL = 20 pF.
3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Table 110. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V(1)(2)


tW(CKL) Clock low time 9.5 10.5 -
fPP =50 MHz ns
tW(CKH) Clock high time 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS 1.5 - -

tIH Input hold time HS fPP ≥ 50 MHz 2 - - ns
tIDW(3) Input valid window (variable window) 3.5 - -
CMD, D outputs (referenced to CK) in eMMC mode
tOV Output valid time HS - 5 7

fPP ≥ 50 MHz ns
tOH Output hold time HS 3 - -
2. CL = 20 pF.
DS12117 Rev 7 201/356

321
Figure 56. SDIO high-speed mode
Figure 57. SD default mode
CK
tOVD tOHD
D, CMD
(output)
ai14888
Figure 58. DDR mode

Clock
MSv36879V1
CAN (controller area network) interface

function characteristics (FDCANx_TX and FDCANx_RX).
202/356 DS12117 Rev 7

USB OTG_FS characteristics

The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF
certified (for Full-speed device operation).
Table 111. USB OTG_FS electrical characteristics

USB transceiver operating

VDD33USB - 3.0(1) - 3.6 V
voltage
Embedded USB_DP pull-up
RPUI - 900 1250 1600
value during idle
Embedded USB_DP pull-up
RPUR - 1400 2300 3200 Ω
value during reception
Driver high
ZDRV Output driver impedance(2) 28 36 44
and low
1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are
degraded in the 2.7 to 3.0 V voltage range.
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
USB OTG_HS characteristics

Unless otherwise specified, the parameters given in Table 112 for ULPI are derived from
tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage
configuration:
• Measurement points are done at CMOS levels: 0.5VDD.
characteristics.
Table 112. Dynamic characteristics: USB ULPI(1)

tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 0.5 - -

tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 6.5 - -
tSD Data in setup time - 2.5 - -
tHD Data in hold time - 0 - -
ns
2.7 V < VDD < 3.6 V,
- 6.5 8.5
CL = 20 pF
tDC/tDD Data/control output delay - -

1.7 V < VDD < 3.6 V, 6.5 13
-
CL = 15 pF
DS12117 Rev 7 203/356

321
Figure 59. ULPI timing diagram
Clock
tSC tHC
Control In
(ULPI_DIR,
ULPI_NXT) tSD tHD
data In
(8-bit)
tDC tDC
Control out
(ULPI_STP)
tDD
data out
(8-bit)
ai17361c
Ethernet characteristics
Unless otherwise specified, the parameters given in Table 113, Table 114 and Table 115 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
frcc_c_ck frequency summarized in Table 23: General operating conditions, with the following
configuration:
• Measurement points are done at CMOS levels: 0.5VDD.
characteristics.
Table 113 gives the list of Ethernet MAC signals for the SMI and Figure 60 shows the
corresponding timing diagram.
Table 113. Dynamics characteristics: Ethernet MAC signals for SMI(1)

tMDC MDC cycle time(2.5 MHz) 400 400 403

Td(MDIO) Write data valid time 1 1.5 3
ns
tsu(MDIO) Read data setup time 8 - -
th(MDIO) Read data hold time 0 - -
204/356 DS12117 Rev 7

Figure 60. Ethernet SMI timing diagram

tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO) th(MDIO)
ETH_MDIO(I)
MS31384V1
Table 114 gives the list of Ethernet MAC signals for the RMII and Figure 61 shows the
Table 114. Dynamics characteristics: Ethernet MAC signals for RMII(1)

tsu(RXD) Receive data setup time 2 - -

tih(RXD) Receive data hold time 3 - -
tsu(CRS) Carrier sense setup time 2.5 - -
ns
tih(CRS) Carrier sense hold time 2 - -
td(TXEN) Transmit enable valid delay time 4 4.5 7
td(TXD) Transmit data valid delay time 7 7.5 11.5
Figure 61. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
Table 115 gives the list of Ethernet MAC signals for MII and Figure 62 shows the
DS12117 Rev 7 205/356

321
Table 115. Dynamics characteristics: Ethernet MAC signals for MII(1)


tsu(DV) Data valid setup time 1.5 - -
tih(DV) Data valid hold time 1 - -
ns
tsu(ER) Error setup time 1.5 - -
tih(ER) Error hold time 0.5 - -
td(TXEN) Transmit enable valid delay time 4.5 6.5 11
td(TXD) Transmit data valid delay time 7 7.5 15
Figure 62. Ethernet MII timing diagram
MII_RX_CLK
tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
6.3.33 JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 116 and Table 117 for JTAG/SWD
are derived from tests performed under the ambient temperature, frcc_c_ck frequency and
VDD supply voltage summarized in Table 23: General operating conditions, with the
• Output speed is set to OSPEEDRy[1:0] = 0x10
characteristics.
206/356 DS12117 Rev 7

Table 116. Dynamics JTAG characteristics(1)

Fpp 2.7 V <VDD< 3.6 V - - 37
TCK clock
MHz
frequency
1/tc(TCK) 1.62 V <VDD< 3.6 V - - 27.5
TMS input
tisu(TMS) - 2 - -
setup time
TMS input
tih(TMS) - 1 - -
hold time
TDI input
tisu(TDI) - 1.5 - -
setup time
TDI input ns
tih(TDI) - 1 - -
hold time
2.7 V <VDD< 3.6 V - 8 13.5

TDO output
tov (TDO)
valid time
1.62 V <VDD< 3.6 V - 8 18
TDO output
toh(TDO) - 7 - -
hold time
Table 117. Dynamics SWD characteristics(1)

Fpp 2.7 V <VDD< 3.6 V - - 71

SWCLK
clock MHz
1/tc(SWCLK) frequency 1.62 V <VDD< 3.6 V - - 55.5
SWDIO input
tisu(SWDIO) - 2.5 - -
setup time
SWDIO input
tih(SWDIO) - 1 - -
hold time
SWDIO 2.7 V <VDD< 3.6 V - 8.5 14 ns

tov (SWDIO) output valid
time 1.62 V <VDD< 3.6 V - 8.5 18
SWDIO
toh(SWDIO) output hold - 8 - -
time
DS12117 Rev 7 207/356

321
Figure 63. JTAG timing diagram

tc(TCK)
TCK
tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO) toh(TDO)
TDO
MSv40458V1
Figure 64. SWD timing diagram

tc(SWCLK)
SWCLK
tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)
tov(SWDIO) toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
208/356 DS12117 Rev 7

STM32H753xI Electrical characteristics (rev V)
7 Electrical characteristics (rev V)
7.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
7.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of junction temperature, supply voltage and frequencies by tests in production on
100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
7.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
7.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
7.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 65.
7.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 66.
Figure 65. Pin loading conditions Figure 66. Pin input voltage
MCU pin MCU pin
C = 50 pF VIN
MS19011V2 MS19010V2
DS12117 Rev 7 209/356

321
Electrical characteristics (rev V) STM32H753xI
Figure 67. Power supply scheme
100 nF
100 nF
VDD33USB VDD50USB
VDD33USB VDD50USB
VSS USB
IOs
USB
VDDLDO VSS
regulator
VCAP
2 x 2.2μF
Core domain (VCORE)

VDDLDO Voltage
4..7μF
regulator
Power
Power
switch
switch
VSS
D3 domain
(System
Level shifter
logic, D1 domain
IO EXTI, D2 domain (CPU, peripherals,
IOs (peripherals, RAM)
logic Peripherals,
RAM) RAM) Flash
VDD
VSS
N(1) x 100 nF
VDD domain
+ 1 x 4.7 μF
HSI, CSI,
VDD
HSI48,
VBAT HSE, PLLs Backup domain
charging
VBAT VSW Backup VBKP
1.2 to 3.6V VBAT regulator
Power switch
Power switch
LSI, LSE,
RTC, Wakeup
Backup
logic, backup
BKUP IO RAM
registers,
IOs logic Reset
VREF
VDDA VSS
VDDA VSS
Analog domain
100 nF + 1 x 1 μF
100 nF + 1 x 1 μF
REF_BUF ADC, DAC

VREF+ VREF+ OPAMP,
VREF- Comparator
VREF-
VSSA
MSv46116V3
1. N corresponds to the number of VDD pins available on the package.

2. A tolerance of +/- 20% is acceptable on decoupling capacitors.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
210/356 DS12117 Rev 7

device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
7.1.7 Current consumption measurement
Figure 68. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
7.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 118: Voltage characteristics,
Table 119: Current characteristics, and Table 120: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and the functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 118. Voltage characteristics (1)

Symbols Ratings Min Max Unit
External main supply voltage (including VDD,

VDDX - VSS −0.3 4.0 V
VDDLDO, VDDA, VDD33USB, VBAT)
Min(VDD, VDDA,
Input voltage on FT_xxx pins VSS−0.3 VDD33USB, VBAT) V
+4.0(3)(4)
VIN(2) Input voltage on TT_xx pins VSS-0.3 4.0 V
Input voltage on BOOT0 pin VSS 9.0 V
Input voltage on any other pins VSS-0.3 4.0 V
Variations between different VDDX power pins
|∆VDDX| - 50 mV
of the same domain
|VSSx-VSS| Variations between all the different ground pins - 50 mV
1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 155: I/O current injection susceptibility for the
maximum allowed injected current values.
3. This formula has to be applied on power supplies related to the IO structure described by the pin definition
table.
4. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
DS12117 Rev 7 211/356

321
Table 119. Current characteristics

Symbols Ratings Max Unit
ΣIVDD Total current into sum of all VDD power lines (source)(1) 620
(1)
ΣIVSS Total current out of sum of all VSS ground lines (sink) 620
(1)
IVDD Maximum current into each VDD power pin (source) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
IIO Output current sunk by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins (2)
140 mA
ΣI(PIN)
Total output current sourced by sum of all I/Os and control pins(2) 140
Injected current on FT_xxx, TT_xx, RST and B pins except PA4,
−5/+0
IINJ(PIN)(3)(4) PA5
Injected current on PA4, PA5 −0/0
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the
external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
QFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer also to Table 118: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 120. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range − 65 to +150

°C
TJ Maximum junction temperature 125
212/356 DS12117 Rev 7

7.3 Operating conditions
7.3.1 General operating conditions
Table 121. General operating conditions

Operating
conditions
VDD Standard operating voltage - 1.62(1) -

3.6 V
Supply voltage for the internal
VDDLDO VDDLDO ≤ VDD 1.62(1) - 3.6
regulator
Standard operating voltage, USB USB used 3.0 - 3.6

VDD33USB
domain USB not used 0 - 3.6
ADC or COMP used 1.62 -
DAC used 1.8 -
OPAMP used 2.0 -
VDDA Analog operating voltage 3.6
VREFBUF used 1.8 -
ADC, DAC, OPAMP, V
COMP, VREFBUF not 0 -
used
TT_xx I/O −0.3 - VDD+0.3
BOOT0 0 - 9
VIN I/O Input voltage Min(VDD, VDDA,
All I/O except BOOT0 VDD33USB)
−0.3 -
and TT_xx +3.6V <
5.5V(2)(3)
VOS3 (max frequency
0.95 1.0 1.26
200 MHz)
VOS2 (max frequency
1.05 1.10 1.26
300 MHz)
Internal regulator ON (LDO)
VOS1 (max frequency
1.15 1.20 1.26
400 MHz)
VOS0(4) (max
1.26 1.35 1.40
frequency 480 MHz(5))
VOS3 (max frequency
0.98 1.03 1.26
200 MHz)
VOS2 (max frequency
VCORE Regulator OFF: external VCORE 1.08 1.13 1.26 V
300 MHz)
voltage must be supplied from external
regulator on two VCAP pins VOS1 (max frequency
1.17 1.23 1.26
400 MHz)
VOS0 (max frequency
1.37 1.38 1.40
480 MHz(5))
DS12117 Rev 7 213/356

321
Table 121. General operating conditions (continued)

Operating
conditions
VOS3 - - 200
VOS2 - - 300
fCPU Arm® Cortex®-M7 clock frequency
VOS1 - - 400
VOS0 - - 480(5)
VOS3 - - 100
VOS2 - - 150
fHCLK AHB clock frequency
VOS1 - - 200
VOS0 - - 240(5)
MHz
VOS3 - - 50(6)
VOS2 - - 75
fPCLK APB clock frequency
VOS1 - - 100
VOS0 - - 120(5)
TFBGA240+25 - - 1093
LQFP208 - - 943
LQFP176 - - 930
Power dissipation at UFBGA176+25 - - 1070

PD mW
TA = 85 °C for suffix 6(7) UFBGA169 - - 1061
LQFP144 - - 915
LQFP100 - - 889
TFBGA100 - - 1018
Ambient temperature for the suffix 6 Maximum power dissipation –40 85

version Low-power dissipation(8) –40 105
TA °C
Ambient temperature for the suffix 3 Maximum power dissipation –40 125
version Low-power dissipation(5) –40 130
TJ Junction temperature range Suffix 6 version –40 125 °C
1. When RESET is released functionality is guaranteed down to VBOR0 min
2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must
be disabled.
4. VOS0 is available only when the LDO regulator is ON.
5. TJmax = 105 °C.
6. Maximum APB clock frequency when at least one peripheral is enabled.
7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 8.9: Thermal characteristics).
8. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.9:
Thermal characteristics).
214/356 DS12117 Rev 7

Table 122. Supply voltage and maximum frequency configuration

Power scale VCORE source Max TJ (°C) Max frequency (MHz) Min VDD (V)
VOS0 LDO 105 480 1.7

VOS1 LDO 125 400 1.62
VOS2 LDO 125 300 1.62
VOS3 LDO 125 200 1.62
SVOS4 LDO 105 N/A 1.62
SVOS5 LDO 105 N/A 1.62
7.3.2 VCAP external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP pin. CEXT is specified in Table 123. Two external capacitors can be connected to
VCAP pins.
Figure 69. External capacitor CEXT
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
Table 123. VCAP operating conditions(1)

CEXT Capacitance of external capacitor 2.2 µF(2)

ESR ESR of external capacitor < 100 mΩ
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.
DS12117 Rev 7 215/356

321
7.3.3 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.
Table 124. Operating conditions at power-up / power-down (regulator ON)

VDD rise time rate 0 ∞

tVDD
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
tVDDA µs/V
VDDA fall time rate 10 ∞
VDDUSB rise time rate 0 ∞
tVDDUSB
VDDUSB fall time rate 10 ∞
216/356 DS12117 Rev 7

7.3.4 Embedded reset and power control block characteristics

temperature and VDD supply voltage conditions summarized in Table 121: General
Table 125. Reset and power control block characteristics

Reset temporization
tRSTTEMPO(1) - - 377 - µs
after BOR0 released
Rising edge(1) 1.62 1.67 1.71
Rising edge 2.04 2.10 2.15
Rising edge 2.34 2.41 2.47
Rising edge 2.63 2.70 2.78

VPVD0

VPVD1 V

VPVD2

VPVD3

VPVD4

VPVD5

VPVD6
Detector threshold 6 Falling edge in Run mode 2.69 2.76 2.83
Hysteresis voltage of BOR
Vhyst_BOR_PVD Hysteresis in Run mode - 100 - mV
(unless BOR0) and PVD
BOR(2) (unless BOR0) and
IDD_BOR_PVD(1) - - 0.630 µA
PVD consumption from VDD
DS12117 Rev 7 217/356

321
Table 125. Reset and power control block characteristics (continued)


VAVM_0

VAVM_1
V
VAVM_2

VAVM_3
Hysteresis of VDDA voltage
Vhyst_VDDA - - 100 - mV
detector
PVM consumption from
IDD_PVM - - - 0.25 µA
VDD(1)
Voltage detector
IDD_VDDA Resistor bridge - - 2.5 µA
consumption on VDDA(1)
2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to
Section 7.3.6: Supply current characteristics).
7.3.5 Embedded reference voltage

temperature and VDD supply voltage conditions summarized in Table 121: General
Table 126. Embedded reference voltage

-40°C < TJ < 125 °C,
VREFINT Internal reference voltages 1.180 1.216 1.255 V
VDD = 3.3 V
ADC sampling time when
tS_vrefint(1)(2) reading the internal reference - 4.3 - -
voltage
µs
VBAT sampling time when
tS_vbat(1)(2) reading the internal VBAT - 9 - -
reference voltage
Reference Buffer
Irefbuf(2) VDDA=3.3 V 9 13.5 23 µA
consumption for ADC
Internal reference voltage
ΔVREFINT(2) spread over the temperature -40°C < TJ < 125 °C - 5 15 mV
range
Average temperature Average temperature
Tcoeff(2) - 20 70 ppm/°C
coefficient coefficient
VDDcoeff(2) Average Voltage coefficient 3.0V < VDD < 3.6V - 10 1370 ppm/V
218/356 DS12117 Rev 7

Table 126. Embedded reference voltage (continued)

%
VREFINT
1. The shortest sampling time for the application can be determined by multiple iterations.
Table 127. Internal reference voltage calibration values

VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 1FF1E860 - 1FF1E861
7.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 68: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a CoreMark code.
Typical and maximum current consumption

• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The Flash memory access time is adjusted with the minimum wait states number,
depending on the fACLK frequency (refer to the table “Number of wait states according to
CPU clock (frcc_c_ck) frequency and VCORE range” available in the reference manual).
• When the peripherals are enabled, the AHB clock frequency is the CPU frequency
divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.
The parameters given in the below tables are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 121: General operating
conditions.
DS12117 Rev 7 219/356

321
running from ITCM, LDO regulator ON(1)
Max(2)
fHCLK
Symbol Parameter Conditions Typ Unit
(MHz) Tj=25 Tj=85 Tj=105 Tj=125
°C °C °C °C
480 148 226 307 390 -

VOS0
400 125 - - - -
400 110 168 230 296 384
VOS1
300 84 - - - -
300 76 114 170 224 297
VOS2 216 56 88 152 205 278
All
peripherals 200 53 - - - -
disabled
200 47 71 121 164 223
180 43 64 116 159 218
Supply 168 40 63 115 158 217
IDD current in VOS3 mA
Run mode 144 35 55 109 153 212
60 16 36 92 135 194
25 12 24 83 126 185
480 226 348 439 550 -
VOS0
400 190 - - - -
400 167 256 327 416 536
All VOS1
enabled
300 122 183 248 320 419
VOS2
200 85 - - - -
VOS3 200 76 116 174 233 313
1. Data are in DTCM for best computation performance, the cache has no influence on consumption in this case.
2. Guaranteed by characterization results, unless otherwise specified.
220/356 DS12117 Rev 7

running from Flash memory, cache ON,
LDO regulator ON
Max(1)
fHCLK
(MHz) Tj=25 Tj=85 Tj=105 Tj=125
°C °C °C °C
480 110 222 304 388 -

VOS0
400 91 - - - -
400 80 162 228 294 381
All VOS1
peripherals 300 61.5 - - - -
disabled
216 55 111 168 222 294
VOS2
200 38.5 - - - -
Supply VOS3 200 34.5 69 120 163 222
IDD current in mA
Run mode 480 220 342 436 546 -
VOS0
400 195 - - - -
400 175 264 336 424 544
All VOS1
enabled
300 120 180 246 318 418
VOS2
200 83 - - - -
VOS3 200 75 114 173 232 312
running from Flash memory, cache OFF,
LDO regulator ON
Max(1)
fHCLK
(MHz) Tj=105 Tj=125
Tj=25°C Tj=85°C
°C °C
VOS0 480 87 157 259 342 453

All VOS1 400 73 123 201 267 355
peripherals
disabled VOS2 300 52 85 150 204 277
Supply VOS3 200 34 54 109 152 212
IDD current in mA
Run mode VOS0 480 168 276 390 504 658
All VOS1 400 135 224 308 397 519
peripherals
enabled VOS2 300 100 154 228 301 401
VOS3 200 70 103 167 226 307
DS12117 Rev 7 221/356

321
Table 131. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON
Max(1)
fHCLK
(MHz) Tj=105 Tj=125
Tj=25°C Tj=85°C
°C °C
D1 64 2.7 4.7 12.9 19.0 27.5

Standby,
Supply D2 VOS3
current in Standby, 8 1.1 - - - -
IDD batch D3 Run mA
acquisition
mode D1 Stop, 64 5.4 18.4 83.7 132.6 202.4
D2 Stop, VOS3
D3 Run 8 3.8 - - - -
Table 132. Typical and maximum current consumption in Stop, LDO regulator ON
Max(1)
Tj=105 Tj=125
Tj=25°C Tj=85°C
°C °C
Flash SVOS5 1.27 6.3 42.5 72.0 -

memory
SVOS4 1.96 9.4 57.4 94.6 -
OFF, no
D1 Stop, IWDG SVOS3 2.78 13.8 75.9 121.3 183.8
D2 Stop,
D3 Stop Flash SVOS5 1.27 6.3 42.5 72.0 -
memory
SVOS4 2.25 9.8 57.9 95.2 -
ON, no
IWDG SVOS3 3.07 14.1 76.4 122.0 184.8
Flash SVOS5 0.91 4.6 30.4 51.2 -
memory
SVOS4 1.42 6.8 41.1 67.3 -
OFF, no
D1 Stop, IWDG SVOS3 2.02 10.0 54.4 86.6 130.0
IDD (Stop) D2 Standby, mA
D3 Stop Flash SVOS5 0.91 4.6 30.4 51.2 -
memory
SVOS4 1.70 7.2 41.5 67.9 -
ON, no
IWDG SVOS3 2.31 10.3 54.9 87.1 130.8
SVOS5 0.49 2.4 16.5 28.0 -
D1 Standby,
D2 Stop, SVOS4 0.76 3.6 22.2 36.6 -
D3 Stop Flash
memory SVOS3 1.10 5.3 29.3 46.9 71.2
OFF, no SVOS5 0.15 0.7 4.3 7.3 -
D1 Standby, IWDG
D2 Standby, SVOS4 0.22 1.0 5.8 9.6 -
D3 Stop
SVOS3 0.35 1.5 7.8 12.3 18.6
222/356 DS12117 Rev 7

Table 133. Typical and maximum current consumption in Sleep mode, LDO regulator
Max(1)
fHCLK
(MHz) Tj=25 Tj=85 Tj=105 Tj=125
°C °C °C °C
480 50.7 96.3 253.4 366.1 -

VOS0
400 43.4 87.8 245.5 357.9 -
400 35.3 66.5 181.3 265.8 379.6
All VOS1
peripherals 300 27.9 - - - -
disabled
300 24.6 47.3 139.1 207.3 300.4
VOS2
200 18.8 - - - -
Supply VOS3 200 16.5 33.6 106.4 160.9 236.1
IDD (Sleep) current in mA
Sleep mode 480 136.0 194.7 348.5 464.4 -
VOS0
400 115.0 169.0 325.9 441.7 -
400 97.7 138.2 251.3 338.4 456.4
All VOS1
peripherals 300 74.9 - - - -
enabled
300 67.3 95.8 187.6 257.9 354.1
VOS2
200 52.8 - - - -
VOS3 200 47.1 69.3 141.4 197.7 275.1
Table 134. Typical and maximum current consumption in Standby

Typ Max(1)
Conditions
3V
Symbol Parameter Unit
RTC 1.62 V 2.4 V 3V 3.3 V
Backup Tj=25 Tj=85 Tj=105 Tj=125
and
SRAM °C °C °C °C
LSE
OFF OFF 1,92 1,95 2,06 2,16 4 18 40 90

Supply
IDD current in ON OFF 3,33 3,44 3,6 3,79 8.2 47 83 141
µA
(Standby) Standby OFF ON 2,43 2,57 2,77 2,95 - - - -
mode
ON ON 3,82 4,05 4,31 4,55 - - - -
DS12117 Rev 7 223/356

321
Table 135. Typical and maximum current consumption in VBAT mode

Conditions Typ Max(1)
3V
Symbol Parameter RTC Unit
Backup
and 1.2 V 2V 3V 3.4 V
SRAM Tj=25 Tj=85 Tj=105 Tj=125
LSE
°C °C °C °C
OFF OFF 0,02 0,02 0,03 0,05 0,5 4,1 10 24

Supply ON OFF 1,33 1,45 1,58 1,7 4,4 22 48 87
IDD
current in µA
(VBAT) VBAT mode OFF ON 0,46 0,57 0,75 0,87 - - - -
ON ON 1,77 2 2,3 2,5 - - - -
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate a current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 156: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid a current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
224/356 DS12117 Rev 7

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 136: Peripheral current
consumption in Run mode), the I/Os used by an application also contribute to the current
consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to
supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external)
connected to the pin:
I SW = V DDx × f SW × C L
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDx is the MCU supply voltage
fSW is the I/O switching frequency
CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
On-chip peripheral current consumption

• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• The I/O compensation cell is enabled.
• frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
– frcc_c_ck = 400 MHz (Scale 1), frcc_c_ck = 300 MHz (Scale 2),
frcc_c_ck = 200 MHz (Scale 3)
• The ambient operating temperature is 25 °C and VDD=3.3 V.
DS12117 Rev 7 225/356

321
Table 136. Peripheral current consumption in Run mode

Bus Peripheral VOS0 VOS1 VOS2 VOS3 Unit
MDMA 4.6 3.8 3.4 3.2

DMA2D 2.9 2.4 2.1 1.9
JPGDEC 4.1 3.7 3.4 3.1
FLASH 17.0 15.0 14.0 12.0
FMC registers 0.9 1.1 0.9 0.8
FMC kernel 7.0 6.1 5.6 5.0
QUADSPI registers 1.5 1.5 1.4 1.3
QSPI kernel 1.0 0.9 0.8 0.7
AHB3
SDMMC1 registers 8.2 7.2 6.7 6.0
SDMMC1 kernel 1.3 1.2 0.9 0.9
DTCM1 7.9 6.8 6.0 5.3
DTCM2 8.3 7.2 6.4 5.7
ITCM 7.0 6.3 5.6 5.1
D1SRAM1 13.0 11.0 9.9 8.7
AHB3 bridge 35.0 32.0 29.0 26.0
Total AHB3 120 106 96 86
µA/MHz
DMA1 54.0 48.0 41.0 37.0
DMA2 55.0 49.0 42.0 37.0
ADC12 registers 4.5 4.1 3.7 3.3
ADC12 kernel 1.0 0.7 0.4 0.6
ART accelerator 4.1 3.7 3.2 2.9
ETH1MAC 17.0 15.0 14.0 12.0
ETH1TX 0.1 0.1 0.1 0.1
ETH1RX 0.1 0.1 0.1 0.1
AHB1
USB1 OTG registers 23.0 21.0 19.0 17.0
USB1 OTG kernel 8.2 0.5 8.3 8.2
USB1 ULPI 0.1 0.1 0.1 0.1
USB2 OTG registers 21.0 19.0 17.0 15.0
USB2 OTG kernel 8.5 0.4 8.6 8.3
USB2 ULPI 23.0 19.0 20.0 19.0
AHB1 bridge 0.1 0.1 0.1 0.1
Total AHB1 220 181 178 161
226/356 DS12117 Rev 7


DCMI 2.1 1.9 1.8 1.6

CRYPT 0.1 0.1 0.1 0.1
HASH 0.1 0.1 0.1 0.1
RNG registers 1.7 2.0 1.3 1.2
RNG kernel 11.0 0.1 9.7 9.4
SDMMC2 registers 47.0 41.0 37.0 34.0
AHB2
SDMMC2 kernel 1.7 1.2 1.1 1.0
D2SRAM1 5.7 4.9 4.4 3.9
D2SRAM2 5.2 4.5 4.0 3.5
D2SRAM3 4.1 3.6 3.2 2.8
AHB2 bridge 0.1 0.1 0.1 0.1
Total AHB2 79 60 63 58
GPIOA 1.5 1.3 1.3 1.1
GPIOB 1.2 1.0 1.0 0.9
GPIOC 0.8 0.7 0.7 0.6
µA/MHz
GPIOD 1.1 1.0 1.0 0.9
GPIOE 0.7 0.7 0.7 0.6
GPIOF 0.8 0.8 0.7 0.6
GPIOG 0.9 0.8 0.8 0.7
GPIOH 1.1 1.0 1.0 0.9
GPIOI 0.9 0.9 0.8 0.7
AHB4
GPIOJ 0.8 0.8 0.7 0.7
GPIOK 0.7 0.8 0.7 0.6
CRC 0.4 0.5 0.4 0.3
BDMA 6.6 5.9 5.3 4.8
ADC3 registers 1.7 1.5 1.2 1.2
ADC3 kernel 0.4 0.3 0.5 0.2
BKPRAM 2.3 1.9 1.7 1.5
AHB4 bridge 0.1 0.1 0.1 0.1
Total AHB4 22 20 19 16
WWDG1 0.7 0.5 0.5 0.2
LCD-TFT 81.0 36.0 33.0 30.0
APB3 bridge 0.3 0.2 0.1 0.1
APB3 µA/MHz
Total APB3 87 41 38 34
DS12117 Rev 7 227/356

321

TIM2 7.7 3.6 3.3 3.0

TIM3 6.7 3.2 3.0 2.7
TIM4 6.3 3.1 2.8 2.5
TIM5 7.4 3.5 3.2 2.8
TIM6 1.4 0.7 0.8 0.6
TIM7 1.4 0.7 0.7 0.6
TIM12 3.2 1.5 1.5 1.3
TIM13 2.3 1.1 1.1 0.9
TIM14 2.1 1.1 1.1 0.9
LPTIM1 registers 0.7 0.5 0.8 0.7
LPTIM1 kernel 2.4 2.3 1.9 1.7
WWDG2 0.6 0.5 0.5 0.4
SPI2 registers 2.0 1.8 1.7 1.4
SPI2 kernel 0.8 0.6 0.5 0.6
APB1 SPI3 registers 1.8 1.6 1.6 1.3 µA/MHz
SPI3 kernel 0.7 0.9 0.7 0.7
SPDIFRX1 registers 0.5 0.7 0.7 0.6
SPDIFRX1 kernel 3.5 2.8 2.4 2.2
USART2 registers 1.9 1.7 1.4 1.3
USART2 kernel 4.3 3.9 3.6 3.2
USART3 kernel 4.4 3.9 3.5 3.2
UART4 registers 1.7 1.5 1.4 1.4
UART4 kernel 3.9 3.4 3.1 2.8
UART5 registers 1.6 1.4 1.4 1.3
UART5 kernel 3.8 3.4 3.0 2.7
I2C1 registers 1.1 0.8 0.9 0.8
I2C1 kernel 2.5 2.3 2.0 1.9
I2C2 registers 1.0 0.8 0.9 0.8
228/356 DS12117 Rev 7


I2C2 kernel 2.3 2.2 1.9 1.7

I2C3 registers 0.8 1.0 0.8 0.8
I2C3 kernel 2.4 1.9 1.8 1.6
HDMI-CEC registers 0.7 0.5 0.6 0.5
HDMI-CEC kernel 0.1 0.1 3.2 0.1
DAC12 3.6 1.3 1.2 1.0
USART7 kernel 4.0 3.3 3.0 2.8
APB1
USART8 kernel 3.9 3.4 3.1 2.8
(continued)
CRS 6.4 5.5 5.0 4.5
SWPMI registers 2.7 2.4 2.3 1.9
SWPMI kernel 0.1 0.1 0.1 0.1
OPAMP 0.2 0.3 0.3 0.2
MDIO 3.3 2.9 2.6 2.3
FDCAN registers 19.0 17.0 15.0 13.0
FDCAN kernel 9.1 7.9 6.9 6.4
APB1 bridge 0.1 0.1 0.1 0.1 µA/MHz
Total APB1 142 108 102 88
TIM1 11.0 5.0 4.5 4.0
TIM8 10.0 4.7 4.3 3.8
USART1 kernel 0.1 0.1 0.1 0.1
USART6 kernel 0.1 0.1 0.1 0.1
SPI1 kernel 0.9 0.8 0.7 0.6
APB2
SPI4 kernel 0.6 0.5 0.5 0.3
TIM15 5.5 2.5 2.3 2.1
TIM16 4.1 2.0 1.8 1.7
TIM17 4.1 1.9 1.8 1.6
SPI5 kernel 0.5 0.4 0.4 0.5
SAI1 registers 1.3 1.1 1.1 1.0
DS12117 Rev 7 229/356

321

SAI1 kernel 1.4 1.1 1.0 0.8

SAI2 kernel 1.1 1.0 0.9 0.9
APB2 SAI3 kernel 1.1 1.2 1.1 0.9

(continued) DFSDM1 registers 6.5 5.8 5.2 4.7
DFSDM1 kernel 0.3 0.2 0.2 0.4
HRTIM 84.0 39.0 35.0 32.0
APB2 bridge 0.2 0.1 0.1 0.2
Total APB2 150 81 74 68
SYSCFG 0.9 1.0 0.7 0.8
LPUART1 registers 1.1 1.3 1.0 0.8
LPUART1 kernel 2.9 2.2 2.2 2.1
SPI6 kernel 0.4 0.4 0.5 0.3
I2C4 registers 0.9 0.7 0.7 0.4
µA/MHz
I2C4 kernel 2.2 2.1 1.9 1.8
LPTIM2 kernel 2.3 2.1 1.8 1.4
LPTIM3 kernel 2.1 1.7 1.6 1.5
APB4
LPTIM4 kernel 2.2 2.0 1.7 1.5
LPTIM5 kernel 2.0 1.8 1.5 1.2
COMP12 0.6 0.4 0.5 0.2
VREF 0.4 0.2 0.2 0.1
RTC 1.1 0.9 1.0 0.6
SAI4 kernel 2.0 2.0 1.8 1.6
APB4 bridge 0.1 0.1 0.1 0.1
Total APB4 28 24.4 22.4 18.9
230/356 DS12117 Rev 7

7.3.7 Wakeup time from low-power modes

The wakeup times given in Table 137 are measured starting from the wakeup event trigger
up to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
Table 137. Low-power mode wakeup timings

Symbol Parameter Conditions Typ(1) Max(1) Unit
CPU
tWUSLEEP(2) Wakeup from Sleep - 9 10 clock
cycles
VOS3, HSI, Flash memory in normal mode 4.4 5.6
12 15
mode
23 28
mode
39 47
mode
(2)
tWUSTOP Wakeup from Stop
VOS3, CSI, Flash memory in low power
36 50
mode µs
47 61
mode
68 77
mode
tWUSTOP_ Wakeup from Stop, VOS3, HSI, Flash memory in normal mode 2.6 3.4
(2)
KERON clock kept running VOS3, CSI, Flash memory in normal mode 26 36
Wakeup from Standby

tWUSTDBY(2) - 390 500
mode

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
DS12117 Rev 7 231/356

321
7.3.8 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
The external clock signal has to respect the Table 156: I/O static characteristics. However,
the recommended clock input waveform is shown in Figure 70.
Table 138. High-speed external user clock characteristics(1)

fHSE_ext User external clock source frequency 4 25 50 MHz

VSW
OSC_IN amplitude 0.7VDD - VDD
(VHSEH − VHSEL) V
VDC OSC_IN input voltage VSS - 0.3VSS
tW(HSE) OSC_IN high or low time 7 - - ns
Figure 70. High-speed external clock source AC timing diagram
VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t
THSE
External fHSE_ext
IL
clock source OSC_IN
STM32
ai17528b
232/356 DS12117 Rev 7

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 156: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 71.

fLSE_ext User external clock source frequency - - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx
V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
Figure 71. Low-speed external clock source AC timing diagram
VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t
TLSE
External fLSE_ext
OSC32_IN IL
clock source
STM32
ai17529b
DS12117 Rev 7 233/356

321
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
Table 140. 4-48 MHz HSE oscillator characteristics(1)

Operating
conditions(2)
F Oscillator frequency - 4 - 48 MHz

RF Feedback resistor - - 200 - kΩ
During startup(3) - - 4
VDD=3 V, Rm=30 Ω
- 0.35 -
CL=10pF@4MHz
VDD=3 V, Rm=30 Ω
- 0.40 -
CL=10 pF at 8 MHz
IDD(HSE) HSE current consumption VDD=3 V, Rm=30 Ω mA
- 0.45 -
CL=10 pF at 16 MHz
VDD=3 V, Rm=30 Ω
- 0.65 -
CL=10 pF at 32 MHz
VDD=3 V, Rm=30 Ω
- 0.95 -
CL=10 pF at 48 MHz
Gmcritmax Maximum critical crystal gm Startup - - 1.5 mA/V
tSU(4) Start-up time VDD is stabilized - 2 - ms
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typical), designed for high-frequency applications, and selected to
match the requirements of the crystal or resonator (see Figure 72). CL1 and CL2 are usually
the same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included
(10 pF can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2.
234/356 DS12117 Rev 7

Figure 72. Typical application with an 8 MHz crystal
Resonator with
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain
REXT(1) OSC_OU T STM32

CL2
ai17530b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic

Symbol Parameter Operating conditions(2) Min Typ Max Unit
F Oscillator frequency - - 32.768 - kHz

LSEDRV[1:0] = 00,
- 290 -
LSEDRV[1:0] = 01,
- 390 -
LSE current Medium Low drive capability
IDD nA
consumption LSEDRV[1:0] = 10,
- 550 -
LSEDRV[1:0] = 11,
- 900 -
LSEDRV[1:0] = 00,
- - 0.5
LSEDRV[1:0] = 01,
- - 0.75
Maximum critical crystal Medium Low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10,
- - 1.7
LSEDRV[1:0] = 11,
- - 2.7
tSU(3) Startup time VDD is stabilized - 2 - s
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is
DS12117 Rev 7 235/356

321
Figure 73. Typical application with a 32.768 kHz crystal
Resonator with
CL1
OSC32_IN fLSE
Bias
32.768 kH z RF controlled
resonator
gain
OSC32_OU T STM32
CL2
ai17531b
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
7.3.9 Internal clock source characteristics

The parameters given in Table 142 to Table 145 are derived from tests performed under
48 MHz high-speed internal RC oscillator (HSI48)
Table 142. HSI48 oscillator characteristics

VDD=3.3 V,
fHSI48 HSI48 frequency 47.5(1) 48 48.5(1) MHz
TJ=30 °C
TRIM(2) USER trimming step - - 0.175 - %
USER TRIM
USER TRIMMING Coverage ± 32 steps ±4.79 ±5.60 - %
COVERAGE(3)
DuCy(HSI48)(2) Duty Cycle - 45 - 55 %
Accuracy of the HSI48 oscillator over
ACCHSI48_REL(3)(4) TJ=-40 to 125 °C –4.5 - 3.5 %
temperature (factory calibrated)
HSI48 oscillator frequency drift with VDD=3 to 3.6 V - 0.025 0.05

∆VDD(HSI48)(3) %
VDD(5) VDD=1.62 V to 3.6 V - 0.05 0.1
tsu(HSI48)(2) HSI48 oscillator start-up time - - 2.1 4.0 µs
IDD(HSI48)(2) HSI48 oscillator power consumption - - 350 400 µA
Next transition jitter
NT jitter - - ± 0.15 - ns
Paired transition jitter
PT jitter - - ± 0.25 - ns
4. ∆fHSI = ACCHSI48_REL + ∆VDD.
236/356 DS12117 Rev 7

5. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) /
Freq(1.62V).
6. Jitter measurements are performed without clock source activated in parallel.
64 MHz high-speed internal RC oscillator (HSI)
Table 143. HSI oscillator characteristics(1)

fHSI HSI frequency VDD=3.3 V, TJ=30 °C 63.7(2) 64 64.3(2) MHz

Trimming is not a multiple
- 0.24 0.32
of 32
Trimming is 128, 256 and
−5.2 −1.8 -
384
TRIM HSI user trimming step Trimming is 64, 192, 320 %

−1.4 −0.8 -
and 448
Other trimming are a
multiple of 32 (not
−0.6 −0.25 -
including multiple of 64
and 128)
DuCy(HSI) Duty Cycle - 45 - 55 %
HSI oscillator frequency drift over
ΔVDD (HSI) VDD=1.62 to 3.6 V −0.12 - 0.03 %
VDD (reference is 3.3 V)
HSI oscillator frequency drift over TJ=-20 to 105 °C −1(3) - 1(3) %

ΔTEMP (HSI)
temperature (reference is 64 MHz) TJ=−40 to TJmax °C −2(3) - 1(3)
tsu(HSI) HSI oscillator start-up time - - 1.4 2 µs
tstab(HSI) HSI oscillator stabilization time at 1% of target frequency - 4 8 µs
IDD(HSI) HSI oscillator power consumption - - 300 400 µA
4 MHz low-power internal RC oscillator (CSI)
Table 144. CSI oscillator characteristics(1)

fCSI CSI frequency VDD=3.3 V, TJ=30 °C 3.96(2) 4 4.04(2) MHz

TRIM Trimming step - - 0.35 - %
DuCy(CSI) Duty Cycle - 45 - 55 %
CSI oscillator frequency drift over TJ = 0 to 85 °C - −3.7(3) 4.5(3)

∆TEMP (CSI) %
temperature TJ = −40 to 125 °C - −11(3) 7.5(3)
CSI oscillator frequency drift over
DVDD (CSI) VDD = 1.62 to 3.6 V - −0.06 0.06 %
VDD
DS12117 Rev 7 237/356

321
Table 144. CSI oscillator characteristics(1) (continued)

tsu(CSI) CSI oscillator startup time - - 1 2 µs

CSI oscillator stabilization time
tstab(CSI) - - - 4 cycle
(to reach ±3% of fCSI)
IDD(CSI) CSI oscillator power consumption - - 23 30 µA
Low-speed internal (LSI) RC oscillator
Table 145. LSI oscillator characteristics

VDD = 3.3 V, TJ = 25 °C 31.4(1) 32 32.6(1)

TJ = –40 to 110 °C, VDD = 1.62 to
29.76(2) - 33.6(2)
3.6 V
fLSI LSI frequency TJ = –40 to 125 °C, VDD = 1.62 to kHz
29.4 - 33.6
3.6 V
LSI oscillator
tsu(LSI)(3) - - 80 130
startup time
LSI oscillator µs
stabilization
tstab(LSI)(3) - - 120 170
time (5% of
final value)
LSI oscillator
IDD(LSI)(3) power - - 130 280 nA
consumption
238/356 DS12117 Rev 7

7.3.10 PLL characteristics

The parameters given in Table 146 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 121: General operating conditions.
Table 146. PLL characteristics (wide VCO frequency range)(1)


fPLL_IN
(2)
VOS0 1.5 - 480
VOS1 1.5 - 400(2)
fPLL_P_OUT PLL multiplier output clock P
VOS2 1.5 - 300(2) MHz
VOS3 1.5 - 200(2)
(3)
Normal mode - 50 150(3)
tLOCK PLL lock time Sigma-delta mode µs
- 58(3) 166(3)
(CKIN ≥ 8 MHz)
VCO =
- 134 -
192 MHz
VCO =
- 134 -
200 MHz
Cycle-to-cycle jitter(4) - ±ps
VCO =
- 76 -
400 MHz
VCO =
- 39 -
800 MHz
VCO =
Normal mode - ±0.7 -
Jitter 800 MHz
Long term jitter Sigma-delta %
VCO =
mode (CKIN = - ±0.8 -
800 MHz
16 MHz)

836 MHz VCORE - 720 -
IDD(PLL)(3) PLL power consumption on VDD µA
192 MHz VCORE - 280 -
2. This value must be limited to the maximum frequency due to the product limitation (480 MHz for VOS0, 400 MHz for VOS1,
300 MHz for VOS2, 200 MHz for VOS3).
DS12117 Rev 7 239/356

321
Table 147. PLL characteristics (medium VCO frequency range)(1)


fPLL_IN
VOS1 1.17 - 210
PLL multiplier output clock P, Q,
fPLL_OUT VOS2 1.17 - 210
R MHz
VOS3 1.17 - 200
Normal mode - 60(2) 100(2)
tLOCK PLL lock time µs
Sigma-delta mode forbidden
VCO =
- 145 -
150 MHz
VCO =
- 91 -
300 MHz
Cycle-to-cycle jitter(3) - ±ps
VCO =
- 64 -
400 MHz
VCO =
Jitter - 63 -
420 MHz
VCO =
- 55 -
fPLL_OUT = 150 MHz
Period jitter ±-ps
50 MHz VCO =
- 30 -
400 MHz
VCO =
Long term jitter Normal mode - ±0.3 - %
400 MHz

I(PLL)(2) PLL power consumption on VDD µA
240/356 DS12117 Rev 7

7.3.11 Memory characteristics

Flash memory
The characteristics are given at TJ = –40 to 125 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 148. Flash memory characteristics


IDD Supply current mA
Table 149. Flash memory programming (single bank configuration nDBANK=1)

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Program/erase parallelism x 8 - 290 580(2)
Word (266 bits) programming Program/erase parallelism x 16 - 180 360

tprog µs
time Program/erase parallelism x 32 - 130 260
tERASE128KB Sector (128 KB) erase time Program/erase parallelism x 16 - 1.8 3.6
Program/erase parallelism x 32 -
Program/erase parallelism x 8 - 13 26 s
tME Mass erase time
Vprog Programming voltage V
2. The maximum programming time is measured after 10K erase operations.
DS12117 Rev 7 241/356

321
Table 150. Flash memory endurance and data retention

Value
Min(1)
NEND Endurance TJ = –40 to +125 °C (6 suffix versions) 10 kcycles

Data retention 1 kcycle at TA = 85 °C 30
tRET Years
10 kcycles at TA = 55 °C 20
7.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 151. They are based on the EMS levels and classes
defined in application note AN1709.
Table 151. EMS characteristics

Level/
Class
Voltage limits to be applied on any I/O pin to induce

VFESD VDD = 3.3 V, TA = +25 °C, 3B
a functional disturbance
UFBGA240, frcc_c_ck =
Fast transient voltage burst limits to be applied 400 MHz, conforms to
VFTB through 100 pF on VDD and VSS pins to induce a IEC 61000-4-2 5A
functional disturbance
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as

possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
242/356 DS12117 Rev 7

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 152. EMI characteristics

Max vs.
Monitored [fHSE/fCPU]
frequency band
8/400 MHz
0.1 to 30 MHz 11
30 to 130 MHz 6
VDD = 3.6 V, TA = 25 °C, UFBGA240 package, dBµV
SEMI Peak level 130 MHz to 1 GHz 12
conforming to IEC61967-2
1 GHz to 2 GHz 7
EMI Level 2.5 -
DS12117 Rev 7 243/356

321
7.3.13 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each
sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC
JS-001 and ANSI/ESDA/JEDEC JS-002 standards.
Table 153. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)

VESD(HBM) voltage (human body ANSI/ESDA/JEDEC JS- All 1C 1000
model) 001
V
VESD(CDM) voltage (charge device ANSI/ESDA/JEDEC JS- All C1 250
model) 002
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 154. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latchup class TA = +25 °C conforming to JESD78 II level A
244/356 DS12117 Rev 7

7.3.14 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when an abnormal injection accidentally happens, susceptibility
tests are performed on a sample basis during the device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator frequency
deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and
positive induced leakage current by positive injection.
Table 155. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection
PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15,
5 0
PJ12, PB4
PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11 0 NA
IINJ mA
PA0, PA_C, PA1, PA1_C, PC2, PC2_C, PC3, PC3_C, PA4,
0 0
PA5, PH4, PH5, BOOT0
All other I/Os 5 NA
DS12117 Rev 7 245/356

321
7.3.15 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 156: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 121: General
operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).
Table 156. I/O static characteristics

I/O input low level voltage except

- - 0.3VDD(1)
BOOT0
I/O input low level voltage except 0.4VDD−0.
VIL 1.62 V<VDDIOx<3.6 V - - V
BOOT0 1(2)
0.19VDD+
BOOT0 I/O input low level voltage - -
0.1(2)
I/O input high level voltage except
0.7VDD(1) - -
BOOT0
I/O input high level voltage except 0.47VDD+0.
VIH 1.62 V<VDDIOx<3.6 V - - V
BOOT0(3) 25(2)
BOOT0 I/O input high level 0.17VDD+0.
- -
voltage(3) 6(2)
TT_xx, FT_xxx and NRST I/O
- 250 -
VHYS(2) input hysteresis 1.62 V< VDDIOx <3.6 V mV
BOOT0 I/O input hysteresis - 200 -
0< VIN ≤ Max(VDDXXX)(9) - - +/-250
FT_xx Input leakage current(2) Max(VDDXXX) < VIN ≤ 5.5 V
(5)(6)(9) - - 1500
0< VIN ≤ Max(VDDXXX)(9) - - +/- 350

Ileak (4) FT_u IO Max(VDDXXX) < VIN ≤ 5.5 V nA
(5)(6)(9) - - 5000(7)
TT_xx Input leakage current 0< VIN ≤ Max(VDDXXX) (9) - - +/-250

0< VIN ≤ VDDIOX - - 15
VPP (BOOT0 alternate function)
VDDIOX < VIN ≤ 9 V 35
RPU VIN=VSS 30 40 50
resistor(8)
kΩ
Weak pull-down equivalent
RPD VIN=VDD(9) 30 40 50
resistor(8)
CIO I/O pin capacitance - - 5 - pF
1. Compliant with CMOS requirements.
3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.
4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
5. All FT_xx IO except FT_lu, FT_u and PC3.
246/356 DS12117 Rev 7

6. VIN must be less than Max(VDDXXX) + 3.6 V.

7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be
disabled.
8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
9. Max(VDDXXX) is the maximum value of all the I/O supplies.
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 74.
Figure 74. VIL/VIH for all I/Os except BOOT0
2.5
TLL requirement: VIHmin = 2 V

0.7V D
D
2 in=
V IHm
ent:
uirem
S req +0.25
CMO 0.47VDD
in=
imulation VIHm
1.5 Bas ed on s
Voltage
-0.1
0.4VDD
VILmax=
n s im ulation
1 Based
o =0.3VDD
ment: VIL
max
require
CMOS
TLL requirement: VILmin = 0.8 V
0.5
0
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
MSv46121V3
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 7.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 119).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 119).
DS12117 Rev 7 247/356

321
Output voltage levels

Unless otherwise specified, the parameters given in Table 157: Output voltage
characteristics for all I/Os except PC13, PC14, PC15 and PI8 and Table 158: Output voltage
characteristics for PC13, PC14, PC15 and PI8 are derived from tests performed under
operating conditions. All I/Os are CMOS and TTL compliant.
Table 157. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1)
CMOS port(2)
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
2.7 V≤ VDD ≤3.6 V
TTL port(2)
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOH (3) Output high level voltage IIO=-8 mA 2.4 -
2.7 V≤ VDD ≤3.6 V
V
IIO=20 mA
2.7 V≤ VDD ≤3.6 V
IIO=-20 mA
2.7 V≤ VDD ≤3.6 V
IIO=4 mA
1.62 V≤ VDD ≤3.6 V
IIO=-4 mA
VOH (3) Output high level voltage VDD−-0.4 -
1.62 V≤VDD<3.6 V
IIO= 20 mA
- 0.4
Output low level voltage for an FTf 2.3 V≤ VDD≤3.6 V
VOLFM+(3)
I/O pin in FM+ mode IIO= 10 mA
- 0.4
1.62 V≤ VDD ≤3.6 V
248/356 DS12117 Rev 7

Table 158. Output voltage characteristics for PC13, PC14, PC15 and PI8(1)
CMOS port(2)
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
2.7 V≤ VDD ≤3.6 V
TTL port(2)
V
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOH (2)
Output high level voltage IIO=-3 mA 2.4 -
2.7 V≤ VDD ≤3.6 V
IIO=1.5 mA
1.62 V≤ VDD ≤3.6 V
IIO=-1.5 mA
1.62 V≤ VDD ≤3.6 V
DS12117 Rev 7 249/356

321
Output buffer timing characteristics (HSLV option disabled)

The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is below 2.7 V.
Table 159. Output timing characteristics (HSLV OFF)(1)(2)

C=50 pF, 2.7 V≤ VDD≤3.6 V - 12

C=50 pF, 1.62 V≤VDD≤2.7 V - 3
C=30 pF, 2.7 V≤VDD≤3.6 V - 12
C=30 pF, 1.62 V≤VDD≤2.7 V - 3
C=10 pF, 2.7 V≤VDD≤3.6 V - 16
C=10 pF, 1.62 V≤VDD≤2.7 V - 4
00
C=50 pF, 2.7 V≤ VDD≤3.6 V - 16.6
C=50 pF, 1.62 V≤VDD≤2.7 V - 33.3
to high level rise time C=30 pF, 1.62 V≤VDD≤2.7 V - 25
C=10 pF, 2.7 V≤VDD≤3.6 V - 10
C=10 pF, 1.62 V≤VDD≤2.7 V - 20
C=50 pF, 2.7 V≤ VDD≤3.6 V - 60
C=50 pF, 1.62 V≤VDD≤2.7 V - 15
C=30 pF, 2.7 V≤VDD≤3.6 V - 80
C=30 pF, 1.62 V≤VDD≤2.7 V - 15
C=10 pF, 2.7 V≤VDD≤3.6 V - 110
C=10 pF, 1.62 V≤VDD≤2.7 V - 20
01
C=50 pF, 2.7 V≤ VDD≤3.6 V - 5.2
C=50 pF, 1.62 V≤VDD≤2.7 V - 10
to high level rise time C=30 pF, 1.62 V≤VDD≤2.7 V - 7.5
C=10 pF, 2.7 V≤VDD≤3.6 V - 2.8
C=10 pF, 1.62 V≤VDD≤2.7 V - 5.2
250/356 DS12117 Rev 7

Table 159. Output timing characteristics (HSLV OFF)(1)(2) (continued)

C=50 pF, 2.7 V≤VDD≤3.6 V (5)

- 85
C=50 pF, 1.62 V≤VDD≤2.7 V(5) - 35
(5)
C=30 pF, 2.7 V≤VDD≤3.6 V - 110
(5)
C=30 pF, 1.62 V≤VDD≤2.7 V - 40
C=10 pF, 2.7 V≤VDD≤3.6 V(5) - 166
C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 100
10
(5)
C=50 pF, 2.7 V≤VDD≤3.6 V - 3.8
(5)
C=50 pF, 1.62 V≤VDD≤2.7 V - 6.9
C=10 pF, 2.7 V≤VDD≤3.6 V(5) - 1.8
C=10 pF, 1.62 V≤VDD≤2.7 Vv - 3.3
C=50 pF, 2.7 V≤VDD≤3.6 Vv - 100
C=50 pF, 1.62 V≤VDD≤2.7 V(5) - 50
C=30 pF, 2.7 V≤VDD≤3.6 Vv - 133
C=30 pF, 1.62 V≤VDD≤2.7 V(5) - 66
C=10 pF, 2.7 V≤VDD≤3.6 V(5) - 220
C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 85
11
C=50 pF, 2.7 V≤VDD≤3.6 V(5) - 3.3
C=50 pF, 1.62 V≤VDD≤2.7 V(5) - 6.6
C=10 pF, 2.7 V≤VDD≤3.6 V(5) - 1.5
C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 2.7
2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
DS12117 Rev 7 251/356

321
Output buffer timing characteristics (HSLV option enabled)
Table 160. Output timing characteristics (HSLV ON)(1)

C=50 pF, 1.62 V≤VDD≤2.7 V - 10

(2)
C=10 pF, 1.62 V≤VDD≤2.7 V - 10
00
C=50 pF, 1.62 V≤VDD≤2.7 V - 11
tr/tf(3) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V - 9 ns
C=10 pF, 1.62 V≤VDD≤2.7 V - 6.6
C=50 pF, 1.62 V≤VDD≤2.7 V - 50
(2)
C=10 pF, 1.62 V≤VDD≤2.7 V - 66
01
C=50 pF, 1.62 V≤VDD≤2.7 V - 6.6
tr/tf(3) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V - 4.8 ns
C=10 pF, 1.62 V≤VDD≤2.7 V - 3
C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 55
C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 133
10
C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 5.8
tr/tf(3) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 4 ns
C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 2.4
C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 60
C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 175
11
C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 5.3
tr/tf(3) fall time and output low C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 3.6 ns
to high level rise time (4)
C=30 pF, 1.62 V≤VDD≤2.7 V - 1.9
(tr+tf) ≤ 2/3 T
Skew ≤ 1/20 T
45%<Duty cycle<55%
252/356 DS12117 Rev 7

7.3.16 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 156: I/O static characteristics).
performed under the ambient temperature and VDD supply voltage conditions summarized
Table 161. NRST pin characteristics


RPU(2) VIN = VSS 30 40 50 ㏀
resistor(1)
VF(NRST)(2) NRST Input filtered pulse 1.71 V < VDD < 3.6 V - - 50
1.71 V < VDD < 3.6 V 300 - - ns
VNF(NRST)(2) NRST Input not filtered pulse
1.62 V < VDD < 3.6 V 1000 - -
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
Figure 75. Recommended NRST pin protection
VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter
0.1 μF
STM32
ai14132d
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 156. Otherwise the reset is not taken into account by the device.
7.3.17 FMC characteristics

Unless otherwise specified, the parameters given in Table 162 to Table 175 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 121: General operating conditions,
with the following configuration:
• IO Compensation cell activated.
• VOS level set to VOS1.
DS12117 Rev 7 253/356

321
Asynchronous waveforms and timings

Figure 76 through Figure 78 represent asynchronous waveforms and Table 162 through
Table 169 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all timing tables, the TKERCK is the fmc_ker_ck clock period.
Figure 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE) t w(NOE) t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE) t h(A_NOE)
FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE) th(Data_NOE)
t su(Data_NE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
254/356 DS12117 Rev 7

Table 162. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

tw(NE) FMC_NE low time 3Tfmc_ker_ck–1 3Tfmc_ker_ck+1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2Tfmc_ker_ck –1 2Tfmc_ker_ck+1
FMC_NOE high to FMC_NE high
th(NE_NOE) 0 -
hold time
Address hold time after
th(A_NOE) 0 -
FMC_NOE high
Data to FMC_NEx high setup ns
tsu(Data_NE) 11 -
time
Data to FMC_NOEx high setup
tsu(Data_NOE) 11 -
time
Data hold time after FMC_NOE
th(Data_NOE) 0 -
high
Data hold time after FMC_NEx
th(Data_NE) 0 -
high
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+1
Table 163. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT

timings(1)(2)
tw(NE) FMC_NE low time 7Tfmc_ker_ck+1 7Tfmc_ker_ck+1

tw(NOE) FMC_NOE low time 5Tfmc_ker_ck–1 5Tfmc_ker_ck +1
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck– 0.5 -
ns
FMC_NWAIT valid before FMC_NEx
tsu(NWAIT_NE) 4Tfmc_ker_ck +11 -
high
FMC_NEx hold time after
th(NE_NWAIT) 3Tfmc_ker_ck+11.5 -
FMC_NWAIT invalid
DS12117 Rev 7 255/356

321
Figure 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)
FMC_NEx
FMC_NOE
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_A[25:0] Address
FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
256/356 DS12117 Rev 7

Table 164. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

tw(NE) FMC_NE low time 3Tfmc_ker_ck –1 3Tfmc_ker_ck

tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck Tfmc_ker_ck+1
tw(NWE) FMC_NWE low time Tfmc_ker_ck –0.5 Tfmc_ker_ck+0.5
FMC_NWE high to FMC_NE high
th(NE_NWE) Tfmc_ker_ck -
hold time
Address hold time after FMC_NWE
th(A_NWE) Tfmc_ker_ck –0.5 -
high ns
FMC_BL hold time after FMC_NWE
th(BL_NWE) Tfmc_ker_ck –0.5 -
high
tv(Data_NE) Data to FMC_NEx low to Data valid - Tfmc_ker_ck+ 2.5
tw(NADV) FMC_NADV low time - Tfmc_ker_ck+ 1
Table 165. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT

timings(1)(2)
tw(NE) FMC_NE low time 8Tfmc_ker_ck –1 8Tfmc_ker_ck+1

tw(NWE) FMC_NWE low time 6Tfmc_ker_ck –1.5 6Tfmc_ker_ck+0.5
FMC_NWAIT valid before FMC_NEx ns
tsu(NWAIT_NE) 5Tfmc_ker_ck+13 -
high
th(NE_NWAIT) 4Tfmc_ker_ck+13 -
FMC_NWAIT invalid
DS12117 Rev 7 257/356

321
Figure 78. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)
FMC_ NE
tv(NOE_NE) t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
tv(A_NE) th(A_NOE)

tv(BL_NE) th(BL_NOE)
FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
258/356 DS12117 Rev 7

Table 166. Asynchronous multiplexed PSRAM/NOR read timings(1)

tw(NE) FMC_NE low time 4Tfmc_ker_ck –1 4Tfmc_ker_ck +1

2Tfmc_ker_ck
tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck
+0.5
ttw(NOE) FMC_NOE low time Tfmc_ker_ck –1

Tfmc_ker_ck +1
FMC_NOE high to FMC_NE high hold
th(NE_NOE) 0 -
time
ns
tw(NADV) FMC_NADV low time Tfmc_ker_ck –0.5 Tfmc_ker_ck +1
FMC_AD(address) valid hold time
th(AD_NADV) Tfmc_ker_ck +0.5 -
after FMC_NADV high)
Address hold time after FMC_NOE
th(A_NOE) Tfmc_ker_ck –0.5 -
high
tsu(Data_NE) Data to FMC_NEx high setup time 11 -
tsu(Data_NOE) Data to FMC_NOE high setup time 11 -
Table 167. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2)


tw(NOE) FMC_NWE low time 5Tfmc_ker_ck –1.5 5Tfmc_ker_ck +0.5
FMC_NWAIT valid before ns
FMC_NEx high
th(NE_NWAIT) 3Tfmc_ker_ck +11.5 -
FMC_NWAIT invalid
DS12117 Rev 7 259/356

321
Table 168. Asynchronous multiplexed PSRAM/NOR write timings(1)


tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck –1 Tfmc_ker_ck +0.5
tw(NWE) FMC_NWE low time 2Tfmc_ker_ck –0.5 2Tfmc_ker_ck +0.5
FMC_NWE high to FMC_NE high hold
th(NE_NWE) Tfmc_ker_ck –0.5 -
time
tw(NADV) FMC_NADV low time Tfmc_ker_ck Tfmc_ker_ck + 1
ns
FMC_AD(adress) valid hold time after
th(AD_NADV) Tfmc_ker_ck +0.5 -
FMC_NADV high)
Address hold time after FMC_NWE
th(A_NWE) Tfmc_ker_ck +0.5 -
high
FMC_BL hold time after FMC_NWE
th(BL_NWE) Tfmc_ker_ck – 0.5 -
high
tv(Data_NADV) FMC_NADV high to Data valid - Tfmc_ker_ck +2
th(Data_NWE) Data hold time after FMC_NWE high Tfmc_ker_ck +0.5 -
Table 169. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)


tw(NWE) FMC_NWE low time 7Tfmc_ker_ck –0.5 7Tfmc_ker_ck +0.5
FMC_NWAIT valid before FMC_NEx ns
high
th(NE_NWAIT) 4Tfmc_ker_ck +11.5 -
FMC_NWAIT invalid
Synchronous waveforms and timings

Figure 79 through Figure 82 represent synchronous waveforms and Table 170 through
Table 173 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
260/356 DS12117 Rev 7

In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following
FMC_CLK maximum values:
• For 2.7 V<VDD<3.6 V, FMC_CLK = 125 MHz at 20 pF
Figure 79. Synchronous multiplexed NOR/PSRAM read timings
FMC_CLK
Data latency = 0
FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
FMC_A[25:16]
FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
MS32757V1
DS12117 Rev 7 261/356

321
Table 170. Synchronous multiplexed NOR/PSRAM read timings(1)

tw(CLK) FMC_CLK period 2Tfmc_ker_ck –1 -

td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Tfmc_ker_ck+0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 2.5
FMC_CLK high to FMC_Ax invalid
td(CLKH-AIV) Tfmc_ker_ck -
(x=16…25)
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Tfmc_ker_ck –0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
FMC_A/D[15:0] valid data before FMC_CLK
tsu(ADV-CLKH) 2 -
high
FMC_A/D[15:0] valid data after FMC_CLK
th(CLKH-ADV) 1 -
high
262/356 DS12117 Rev 7

Figure 80. Synchronous multiplexed PSRAM write timings
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:16]
FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
td(CLKH-NBLH)
FMC_NBL
MS32758V1
DS12117 Rev 7 263/356

321
Table 171. Synchronous multiplexed PSRAM write timings(1)

2Tfmc_ker_ck –1
tw(CLK) FMC_CLK period, VDD = 2.7 to 3.6 V -
1
td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x =0..2) - 1
FMC_CLK high to FMC_NEx high
td(CLKH-NExH) Tfmc_ker_ck +0.5 -
(x = 0…2)
FMC_CLK low to FMC_Ax valid
td(CLKL-AV) - 2
(x =16…25)
td(CLKH-AIV) Tfmc_ker_ck -
(x =16…25)
Ns
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck +0.5 -
td(CLKL-ADV) FMC_CLK low to to FMC_AD[15:0] valid - 2.5
FMC_A/D[15:0] valid data after FMC_CLK
td(CLKL-DATA) - 2.5
low
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck +0.5 -
264/356 DS12117 Rev 7

Figure 81. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
FMC_NOE
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
MS32759V1
DS12117 Rev 7 265/356

321
Table 172. Synchronous non-multiplexed NOR/PSRAM read timings(1)

tw(CLK) FMC_CLK period 2Tfmc_ker_ck –1 -

t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 1
td(CLKH-NExH) 2Tfmc_ker_ck+0.5 -
(x= 0…2)
td(CLKL-AV) - 2
(x=16…25)
td(CLKH-AIV) 2Tfmc_ker_ck - ns
(x=16…25)
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high 2Tfmc_ker_ck-0.5 -
FMC_D[15:0] valid data before FMC_CLK
tsu(DV-CLKH) 2 -
high
FMC_D[15:0] valid data after FMC_CLK
th(CLKH-DV) 1 -
high
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 -
266/356 DS12117 Rev 7

Figure 82. Synchronous non-multiplexed PSRAM write timings

tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
FMC_NWE
td(CLKL-Data) td(CLKL-Data)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
MS32760V1
DS12117 Rev 7 267/356

321
Table 173. Synchronous non-multiplexed PSRAM write timings(1)

t(CLK) FMC_CLK period 2Tfmc_ker_ck –1 -

t(CLKH-NExH) Tfmc_ker_ck+0.5 -
(x= 0…2)
td(CLKL-AV) - 2.
(x=16…25)
td(CLKH-AIV) Tfmc_ker_ck - ns
(x=16…25)
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Tfmc_ker_ck+1 -
FMC_D[15:0] valid data after FMC_CLK
td(CLKL-Data) - 3.5
low
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck+1 -
268/356 DS12117 Rev 7

NAND controller waveforms and timings

Figure 83 through Figure 86 represent synchronous waveforms, and Table 174 and
Table 175 provide the corresponding timings. The results shown in this table are obtained
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Figure 83. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
FMC_NOE (NRE)
FMC_D[15:0]
MS32767V1
DS12117 Rev 7 269/356

321
Figure 84. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) th(NWE-ALE)
FMC_NWE
FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32768V1
Figure 85. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
tw(NOE)
FMC_NOE
FMC_D[15:0]
MS32769V1
270/356 DS12117 Rev 7

Figure 86. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)
FMC_NWE
FMC_N OE
td(D-NWE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32770V1
Table 174. Switching characteristics for NAND Flash read cycles(1)

tw(N0E) FMC_NOE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck+0.5

FMC_D[15-0] valid data before
tsu(D-NOE) 8 -
FMC_NOE high
FMC_D[15-0] valid data after ns
th(NOE-D) 0 -
FMC_NOE high
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Tfmc_ker_ck +1
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Tfmc_ker_ck –2 -
Table 175. Switching characteristics for NAND Flash write cycles(1)

tw(NWE) FMC_NWE low width 4Tfmc_ker_ck – 0.5 4Tfmc_ker_ck +0.5

FMC_NWE low to FMC_D[15-0]
tv(NWE-D) 0 -
valid
FMC_NWE high to FMC_D[15-0]
th(NWE-D) 2Tfmc_ker_ck – 0.5 -
invalid
FMC_D[15-0] valid before ns
td(D-NWE) 5Tfmc_ker_ck – 1 -
FMC_NWE high
FMC_ALE valid before FMC_NWE
td(ALE-NWE) - 3Tfmc_ker_ck +0.5
low
FMC_NWE high to FMC_ALE
th(NWE-ALE) 2Tfmc_ker_ck – 1 -
invalid
DS12117 Rev 7 271/356

321
SDRAM waveforms and timings

In all timing tables, the TKERCK is the fmc_ker_ck clock period, with the following
FMC_SDCLK maximum values:
• For 2.7 V<VDD<3.6 V: FMC_CLK =110 MHz at 20 pF
• For 1.8 V<VDD<1.9 V: FMC_CLK =100 MHz at 20 pF
• For 1.62 V<DD<1.8 V, FMC_CLK =100 MHz at 15 pF
Figure 87. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddC)
FMC_SDNE[1:0]
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)
MS32751V2
272/356 DS12117 Rev 7

Table 176. SDRAM read timings(1)

2Tfmc_ker_ck
tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 1
+0.5
tsu(SDCLKH _Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 1 -
td(SDCLKL- SDNE) Chip select valid time - 1.5 ns
th(SDCLKL_SDNE) Chip select hold time 0.5 -
Table 177. LPSDR SDRAM read timings(1)

tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5

tsu(SDCLKH_Data) Data input setup time 2 -
th(SDCLKH_Data) Data input hold time 1.5 -
td(SDCLKL_SDNE) Chip select valid time - 2.5
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 0.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
DS12117 Rev 7 273/356

321
Figure 88. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
th(SDCLKL_AddC)
FMC_SDNE[1:0]
FMC_SDNRAS
FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_SDNWE
td(SDCLKL_Data)
td(SDCLKL_NBL) th(SDCLKL_Data)
FMC_NBL[3:0]
MS32752V2
Table 178. SDRAM Write timings(1)

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5

td(SDCLKL _Data) Data output valid time - 1
td(SDCLKL_SDNWE) SDNWE valid time - 1.5
th(SDCLKL_SDNWE) SDNWE hold time 0.5 -
ns
td(SDCLKL_ SDNE) Chip select valid time - 1.5
th(SDCLKL-_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1
td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 -
274/356 DS12117 Rev 7

Table 179. LPSDR SDRAM Write timings(1)

tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck – 1 2Tfmc_ker_ck+0.5

td(SDCLKL _Data) Data output valid time - 2.5
td(SDCLKL-SDNWE) SDNWE valid time - 2.5
th(SDCLKL-SDNWE) SDNWE hold time 0 -
ns
td(SDCLKL- SDNE) Chip select valid time - 3
th(SDCLKL- SDNE) Chip select hold time 0 -
td(SDCLKL-SDNRAS) SDNRAS valid time - 1.5
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 1.5
td(SDCLKL-SDNCAS) SDNCAS hold time 0 -
7.3.18 Quad-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 180 and Table 181 for QUADSPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
• VOS level set to VOS1
The following table summarizes the parameters measured in SDR mode.
Table 180. QUADSPI characteristics in SDR mode(1)

2.7<VDD<3.6 V
- - 133
QUADSPI clock CL = 20 pF
Fck11/TCK MHz
frequency 1.62<VDD<3.6 V
- - 100
CL = 15 pF
DS12117 Rev 7 275/356

321
Table 180. QUADSPI characteristics in SDR mode(1) (continued)

tw(CKH) QUADSPI clock high TCK/2–0.5 - TCK/2

PRESCALER[7:0] =
and low time Even
tw(CKL) n = 0,1,3,5... TCK/2 - TCK/2+0.5
division
ts(IN) QUADSPI clock high (n/2)*TCK/(n+1)-0.5 - (n/2)*TCK/ (n+1)
PRESCALER[7:0] =
and low time Odd (n/2+1)*TCK/
th(IN) n = 2,4,6,8... (n/2+1)*TCK/(n+1) -
division (n+1)+0.5 ns
tv(OUT) Data input setup time 1 - -
-
th(OUT) Data input hold time 3.5 - -
tw(CKH) Data output valid time - - 1 2
tw(CKL) Data output hold time - 0 - -
The following table summarizes the parameters measured in DDR mode.
Table 181. QUADSPI characteristics in DDR mode(1)

2.7<VDD<3.6 V
- - 100
CL = 20 pF
Fck11/TCK QUADSPI clock frequency MHz
1.62<VDD<3.6 V
- - 100
CL = 15 pF
tw(CKH) QUADSPI clock high and PRESCALER[7:0] = TCK/2–0.5 - TCK/2
tw(CKL) low time Even division n = 0,1,3,5... TCK/2 - TCK/2+0.5
(n/2)*TCK/ (n/2)*TCK/
tw(CKH) -
QUADSPI clock high and PRESCALER[7:0] = (n+1)-0.5 (n+1)
low time Odd division n = 2,4,6,8... (n/2+1)*TCK/ (n/2+1)*TCK /
tw(CKL) -
(n+1) (n+1)+0.5
tsr(IN), tsf(IN) Data input setup time - 1.5 - -
thr(IN),thf(IN) Data input hold time - 3.5 - - ns
DHHC=0 - 5 6
tvr(OUT), DHHC=1
tvf(OUT) PRESCALER[7:0] = - TCK/4+1 TCK/4+2
1,2…
DHHC=0 3 - -
thr(OUT), DHHC=1
thf(OUT) PRESCALER[7:0]=1 TCK/4 - -
,2…
276/356 DS12117 Rev 7

Figure 89. Quad-SPI timing diagram - SDR mode

Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V1
Figure 90. Quad-SPI timing diagram - DDR mode

Clock
MSv36879V1
7.3.19 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 182 for Delay Block are derived
configuration:
Table 182. Delay Block characteristics

tinit Initial delay - 1400 2200 2400 ps

t∆ Unit Delay - 35 40 45 -
DS12117 Rev 7 277/356

321
7.3.20 16-bit ADC characteristics

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
Table 183. ADC characteristics(1)(2)

Analog supply
VDDA voltage for ADC - 1.62 - 3.6 V
ON
Positive reference
VREF+ - 1.62 - VDDA V
voltage
Negative
VREF- - VSSA V
reference voltage
BOOST = 11 0.12 - 50
BOOST = 10 0.12 - 25
ADC clock
fADC 1.62 V ≤ VDDA ≤ 3.6 V MHz
frequency
BOOST = 01 0.12 - 12.5
BOOST = 00 - - 6.25
Resolution = 16 bits,
fADC=36 MHz SMP = 1.5 - - 3.60
VDDA >2.5 V TJ = 90 °C
Resolution = 16 bits fADC=37 MHz SMP = 2.5 - - 3.35
Sampling rate for Resolution = 14 bits fADC = 50 MHz SMP = 2.5 - - 5.00
Direct channels(4)
Resolution = 12 bits fADC = 50 MHz SMP = 2.5 - - 5.50
TJ = 125 °C
Resolution = 16 bits,
fADC=32 MHz SMP = 2.5 - - 2.90
VDDA >2.5 V TJ = 90 °C
Resolution = 16 bits fADC=31 MHz SMP = 2.5 - - 2.80
fs(3) MSps
Sampling rate for Resolution = 14 bits fADC = 33 MHz SMP = 2.5 - - 3.30
Fast channels
TJ = 125 °C
Resolution = 16 bits TJ = 90 °C - -
resolution = 14 bits - -
Sampling rate for
resolution = 12 bits fADC = 10 MHz SMP = 1.5 - - 1.00
Slow channels
TJ = 125 °C
External trigger 1/
tTRIG Resolution = 16 bits - - 10
period fADC
Conversion
VAIN(5) - 0 - VREF+ V
voltage range
Common mode VREF/2 VREF/ VREF/2

VCMIV - V
input voltage − 10% 2 + 10%
278/356 DS12117 Rev 7

Table 183. ADC characteristics(1)(2) (continued)

Resolution = 16 bits, TJ = 125 °C - - - - 170

External input
RAIN(6) Resolution = 12 bits, TJ =125 °C - - - - 1150 Ω
impedance
Internal sample
CADC and hold - - 4 - pF
capacitor
tADCVREG ADC LDO startup

- - 5 10 us
_STUP time
conver
ADC Power-up
tSTAB LDO already started 1 - - sion
time
cycle
Offset and
tCAL linearity - 165010 - - 1/fADC
calibration time
tOFF_ Offset calibration

- 1280 - - 1/fADC
CAL time
Trigger CKMODE = 00 1.5 2 2.5

conversion
CKMODE = 01 - - 2.5
latency regular
tLATR 1/fADC
and injected
CKMODE = 10 - - 2.5
channels without
conversion abort CKMODE = 11 - - 2.25
Trigger CKMODE = 00 2.5 3 3.5

conversion
CKMODE = 01 - - 3.5
latency regular
tLATRINJ 1/fADC
injected channels
CKMODE = 10 - - 3.5
aborting a regular
conversion CKMODE = 11 - - 3.25
tS Sampling time - 1.5 - 810.5 1/fADC
Total conversion
ts + 0.5
tCONV time (including Resolution = N bits - - 1/fADC
+ N/2
sampling time)
DS12117 Rev 7 279/356

321
Table 183. ADC characteristics(1)(2) (continued)

ADC consumption Resolution = 16 bits, fADC=25 MHz - - - 1440 -

on VDDA,
Resolution = 14 bits, fADC=30 MHz - - - 1350 -
BOOST=11,
Differential mode Resolution = 12 bits, fADC=40 MHz - - - 990 -
ADC consumption Resolution = 16 bits - - - 1080 -

on VDDA
BOOST=10, Resolution = 14 bits - - - 810 -
Differential mode
fADC=25 MHz Resolution = 12 bits - - - 585 -
IDDA_D
(ADC) ADC consumption Resolution = 16 bits - - - 630 -
on VDDA
Differential mode
fADC=12.5 MHz Resolution = 12 bits - - - 315 -

on VDDA
Differential mode
fADC=6.25 MHz Resolution = 12 bits - - - 225 -
ADC consumption Resolution = 16 bits, fADC=25 MHz - - - 720 -

on VDDA
BOOST=11, Resolution = 14 bits, fADC=30 MHz - - - 675 -
Single-ended
mode Resolution = 12 bits, fADC=40 MHz - - - 495 -
µA
on VDDA
Singl-ended mode
fADC=25 MHz Resolution = 12 bits - - - 292.5 -
IDDA_SE(
ADC) on VDDA
Single-ended
mode Resolution = 12 bits - - - 157.5 -
fADC=12.5 MHz

on VDDA
Single-ended
mode Resolution = 12 bits - - - 112.5 -
fADC=6.25 MHz
fADC=50 MHz - - - 400 -
fADC=25 MHz - - - 220 -

ADC consumption
IDD
on VDD fADC=12.5 MHz - - - 180 -
(ADC)
BOOST=11
fADC=6.25 MHz - - - 120 -
fADC=3.125 MHz - - - 80 -
2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
3. These values are valid for UFBGA169 and one ADC. The values for other packages and multiple ADCs may be different.
4. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
5. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
6. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and 8-bit resolutions.
280/356 DS12117 Rev 7

Table 184. Minimum sampling time vs RAIN(1)(2)

Minimum sampling time (s)
Resolution RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)
16 bits 47 7.37E-08 1.14E-07 1.72E-07

47 6.29E-08 9.74E-08 1.55E-07
68 6.84E-08 1.02E-07 1.58E-07
14 bits 100 7.80E-08 1.12E-07 1.62E-07
150 9.86E-08 1.32E-07 1.80E-07
220 1.32E-07 1.61E-07 2.01E-07
47 5.32E-08 8.00E-08 1.29E-07
68 5.74E-08 8.50E-08 1.32E-07
100 6.58E-08 9.31E-08 1.40E-07
150 8.37E-08 1.10E-07 1.51E-07
12 bits
220 1.11E-07 1.34E-07 1.73E-07
330 1.56E-07 1.78E-07 2.14E-07
470 2.16E-07 2.39E-07 2.68E-07
680 3.01E-07 3.29E-07 3.54E-07
47 4.34E-08 6.51E-08 1.08E-07
68 4.68E-08 6.89E-08 1.11E-07
100 5.35E-08 7.55E-08 1.16E-07
150 6.68E-08 8.77E-08 1.26E-07
220 8.80E-08 1.08E-07 1.40E-07
330 1.24E-07 1.43E-07 1.71E-07
10 bits
470 1.69E-07 1.89E-07 2.13E-07
680 2.38E-07 2.60E-07 2.80E-07
1000 3.45E-07 3.66E-07 3.84E-07
1500 5.15E-07 5.35E-07 5.48E-07
2200 7.42E-07 7.75E-07 7.78E-07
3300 1.10E-06 1.14E-06 1.14E-06
DS12117 Rev 7 281/356

321
Table 184. Minimum sampling time vs RAIN(1)(2) (continued)

Minimum sampling time (s)
Resolution RAIN (Ω)
Direct
Fast channels(4) Slow channels(5)
channels(3)
47 3.32E-08 5.10E-08 8.61E-08

68 3.59E-08 5.35E-08 8.83E-08
100 4.10E-08 5.83E-08 9.22E-08
150 5.06E-08 6.76E-08 9.95E-08
220 6.61E-08 8.22E-08 1.11E-07
330 9.17E-08 1.08E-07 1.32E-07
470 1.24E-07 1.40E-07 1.63E-07
680 1.74E-07 1.91E-07 2.12E-07
8 bits
1000 2.53E-07 2.70E-07 2.85E-07
1500 3.73E-07 3.93E-07 4.05E-07
2200 5.39E-07 5.67E-07 5.75E-07
3300 8.02E-07 8.36E-07 8.38E-07
4700 1.13E-06 1.18E-06 1.18E-06
6800 1.62E-06 1.69E-06 1.68E-06
10000 2.36E-06 2.47E-06 2.45E-06
15000 3.50E-06 3.69E-06 3.65E-06
2. Data valid at up to 125 °C, with a 47 pF PCB capacitor, and VDDA=1.6 V.
3. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.
4. Fast channels correspond to PC0, PC1, PC2, PC3, PA0, and PA1.
5. Slow channels correspond to all ADC inputs except for the Fast channels.
282/356 DS12117 Rev 7

Table 185. ADC accuracy(1)(2)

Symbol Parameter Conditions(3) Min Typ Max Unit
Direct Single ended - +10/–20 -

channel Differential - ±15 -
Single ended - +10/–20 -
ET Total undadjusted error Fast channel
Differential - ±15 -
Slow Single ended - ±10 -

channel Differential ±10 -
EO Offset error - - ±10 -
EG Gain error - - ±15 -
LSB
Single ended - +3/–1 -
ED Differential linearity error
Differential - +4.5/–1 -
Direct Single ended - ±11 -

Single ended - ±13 -
EL Integral linearity error Fast channel
Differential - ±7 -
Slow Single ended - ±10 -

Single ended - 12.2 -
ENOB Effective number of bits Bits
Differential - 13.2 -
Signal-to-noise and Single ended - 75.2 -

SINAD
distortion ratio Differential - 81.2 -
Single ended - 77.0 -
SNR Signal-to-noise ratio dB
Differential - 81.0 -
Single ended - 87 -
THD Total harmonic distortion
Differential - 90 -
1. Data guaranteed by characterization for BGA packages. The values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V and BOOST=11.
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 7.3.14 does not affect the ADC accuracy.
DS12117 Rev 7 283/356

321
Figure 91. ADC accuracy characteristics (12-bit resolution)

V REF+ V DDA
[1LSB IDEAL = (or depending on package)]
4096 4096
EG
4095
4094
4093
(2)
ET
7 (3)
(1)
6
5
EO EL
4
3
ED
2
1L SBIDEAL
1
0
1 2 3 456 7 4093 4094 4095 4096
V SSA VDDA
ai14395c
1. Example of an actual transfer curve.

2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 92. Typical connection diagram using the ADC
VDD STM32
Sample and hold ADC
VT converter
0.6 V
RAIN(1) AINx RADC(1)
12-bit
converter
VT
VAIN
0.6 V C ADC(1)
Cparasitic
IL±1 μA
ai17534b
1. Refer to Table 183 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
284/356 DS12117 Rev 7

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 93 or Figure 94,
depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 93. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32
VREF+(1)
1 μF // 100 nF
VDDA
1 μF // 100 nF
VSSA/VREF+(1)
MSv50648V1
Figure 94. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32
VREF+/VDDA(1)
1 μF // 100 nF
VREF-/VSSA(1)
MSv50649V1
DS12117 Rev 7 285/356

321
7.3.21 DAC characteristics
Table 186. DAC characteristics(1)(2)


VREF+ Positive reference voltage - 1.80 - VDDA
V
Negative reference
VREF- - - VSSA -
voltage
connected
5 - -
DAC output buffer to VSSA
RL Resistive Load
ON connected kΩ
25 - -
to VDDA
RO Output Impedance DAC output buffer OFF 10.3 13 16
VDD =
Output impedance - - 1.6
DAC output buffer 2.7 V
RBON sample and hold mode, kΩ
ON VDD =
output buffer ON - - 2.6
2.0 V
VDD =
Output impedance - - 17.8
DAC output buffer 2.7 V
RBOFF sample and hold mode, kΩ
OFF VDD =
output buffer OFF - - 18.7
2.0 V
CL DAC output buffer OFF - - 50 pF
Capacitive Load
CSH Sample and Hold mode - 0.1 1 µF
VDDA
Voltage on DAC_OUT DAC output buffer ON 0.2 -
VDAC_OUT −0.2 V
output
DAC output buffer OFF 0 - VREF+
±0.5 LSB - 2.05 -
Settling time (full scale:
for a 12-bit code transition Normal mode, DAC ±1 LSB - 1.97 -
between the lowest and output buffer ON,
±2 LSB - 1.67 -
the highest input codes CL ≤ 50 pF,
tSETTLING RL ≥ 5 ㏀ ±4 LSB - 1.66 - µs
when DAC_OUT reaches
the final value of ±0.5LSB, ±8 LSB - 1.65 -
±1LSB, ±2LSB, ±4LSB,
±8LSB) Normal mode, DAC output buffer
- 1.7 2
OFF, ±1LSB CL=10 pF
Wakeup time from off Normal mode, DAC output buffer
- 5 7.5
state (setting the ENx bit ON, CL ≤ 50 pF, RL = 5 ㏀
tWAKEUP(3) in the DAC Control µs
register) until the final Normal mode, DAC output buffer
2 5
value of ±1LSB is reached OFF, CL ≤ 10 pF
DC VDDA supply rejection Normal mode, DAC output buffer

PSRR - −80 −28 dB
ratio ON, CL ≤ 50 pF, RL = 5 ㏀
286/356 DS12117 Rev 7

Table 186. DAC characteristics(1)(2) (continued)

Sampling time in Sample MODE<2:0>_V12=100/101

and Hold mode - 0.7 2.6
(BUFFER ON)
CL=100 nF ms
MODE<2:0>_V12=110
tSAMP (code transition between - 11.5 18.7
(BUFFER OFF)
the lowest input code and
the highest input code
MODE<2:0>_V12=111
when DAC_OUT reaches - 0.3 0.6 µs
the ±1LSB final value) (INTERNAL BUFFER OFF)
Internal sample and hold

CIint - 1.8 2.2 2.6 pF
capacitor
Middle code offset trim Minimum time to verify the each
tTRIM 50 - - µs
time code
Middle code offset for 1 VREF+ = 3.6 V - 850 -

Voffset µV
trim code step VREF+ = 1.8 V - 425 -
No load,
middle
- 360 -
code
DAC output buffer (0x800)
ON
No load,
worst code - 490 -
DAC quiescent (0xF1C)
IDDA(DAC)
consumption from VDDA No load,
DAC output buffer middle/wor
- 20 -
OFF st code
(0x800)
360*TON/
Sample and Hold mode,
- (TON+TOFF) -
CSH=100 nF (4)
No load,
middle µA
- 170 -
code
DAC output buffer (0x800)
ON
No load,
worst code - 170 -
(0xF1C)
No load,
DAC consumption from
IDDV(DAC) DAC output buffer middle/wor
VREF+ - 160 -
OFF st code
(0x800)
170*TON/
Sample and Hold mode, Buffer
- (TON+TOFF) -
ON, CSH=100 nF (worst code) (4)
160*TON/
Sample and Hold mode, Buffer
- (TON+TOFF) -
OFF, CSH=100 nF (worst code) (4)
DS12117 Rev 7 287/356

321
2. TBD stands for “to be defined”.

3. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).
4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference manual for more
details.
Table 187. DAC accuracy(1)

Differential non DAC output buffer ON −2 - 2

DNL LSB
linearity(2) DAC output buffer OFF −2 - 2
- Monotonicity 10 bits - - - -
−4 - 4
RL ≥ 5 ㏀
INL Integral non linearity(3) LSB
−4 - 4
CL ≤ 50 pF, no RL
buffer ON,
Offset error at code CL ≤ 50 pF, VREF+ = 1.8 V - - ±30
Offset RL ≥ 5 ㏀ LSB
0x800 (3)
- - ±8
CL ≤ 50 pF, no RL
Offset error at code DAC output buffer OFF,
Offset1 - - ±5 LSB
0x001(4) CL ≤ 50 pF, no RL
Offset error at code buffer ON,
OffsetCal 0x800 after factory LSB
CL ≤ 50 pF, VREF+ = 1.8 V - - ±7
calibration
RL ≥ 5 ㏀
- - ±1
RL ≥ 5 ㏀
Gain Gain error(5) %
- - ±1
CL ≤ 50 pF, no RL
- 67.8 -
RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz
SNR Signal-to-noise ratio(6) DAC output buffer OFF, dB
CL ≤ 50 pF, no RL,1 kHz, BW = - 67.8 -
500 KHz
- −78.6 -
Total harmonic RL ≥ 5 ㏀ , 1 kHz
THD dB
distortion(6) DAC output buffer OFF,
- −78.6 -
CL ≤ 50 pF, no RL, 1 kHz
- 67.5 -
Signal-to-noise and RL ≥ 5 ㏀ , 1 kHz
SINAD dB
distortion ratio(6) DAC output buffer OFF,
- 67.5 -
288/356 DS12117 Rev 7

Table 187. DAC accuracy(1) (continued)

DAC output buffer ON,
- 10.9 -
Effective number of CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz
ENOB bits
bits DAC output buffer OFF,
- 10.9 -
2. Difference between two consecutive codes minus 1 LSB.
3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and
last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF
when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.
6. Signal is −0.5dBFS with Fsampling=1 MHz.
Figure 95. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RL
12-bit DAC_OUTx
digital to
analog
converter
CL
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DS12117 Rev 7 289/356

321
7.3.22 Voltage reference buffer characteristics
Table 188. VREFBUF characteristics(1)

VSCALE = 000 2.8 3.3 3.6
VSCALE = 001 2.4 - 3.6
Normal mode
VSCALE = 010 2.1 - 3.6
VSCALE = 011 1.8 - 3.6
VDDA Analog supply voltage
VSCALE = 000 1.62 - 2.80
VSCALE = 001 1.62 - 2.40
Degraded mode
VSCALE = 010 1.62 - 2.10
VSCALE = 011 1.62 - 1.80
VSCALE = 000 2.498 2.5 2.5035
VSCALE = 001 2.046 2.049 2.052 V
Normal mode
VSCALE = 010 1.801 1.804 1.806
VSCALE = 011 1.4995 1.5015 1.504
Voltage Reference VDDA−

VREFBUF VSCALE = 000 - VDDA
Buffer Output, at 30 °C, 150 mV
_OUT Iload= 100 µA VDDA−
VSCALE = 001 - VDDA
150 mV
Degraded mode(2)
VDDA−
VSCALE = 010 - VDDA
150 mV
VDDA−
VSCALE = 011 - VDDA
150 mV
TRIM Trim step resolution - - - ±0.05 ±0.1 %
CL Load capacitor - - 0.5 1 1.50 uF
Equivalent Serial
esr
Resistor of CL
- - - - 2 Ω
Iload Static load current - - - - 4 mA

Iload = 500 µA - 200 -
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V ppm/V
Iload = 4 mA - 100 -
ppm/
Iload_reg Load regulation 500 µA ≤ ILOAD ≤ 4 mA Normal Mode - 50 -
mA
Tcoeff
ppm/
Tcoeff Temperature coefficient −40 °C < TJ < +125 °C - - VREFINT
°C
+ 100
DC - - 60 -
PSRR Power supply rejection dB
100KHz - - 40 -
290/356 DS12117 Rev 7

Table 188. VREFBUF characteristics(1) (continued)

CL=0.5 µF - - 300 -
tSTART Start-up time CL=1 µF - - 500 - µs
CL=1.5 µF - - 650 -
Control of maximum
DC current drive on
IINRUSH - - 8 - mA
VREFBUF_OUT during
startup phase(3)
ILOAD = 0 µA - - 15 25
VREFBUF
IDDA(VRE
consumption from ILOAD = 500 µA - - 16 30 µA
FBUF) VDDA
ILOAD = 4 mA - - 32 50
2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA−drop voltage).
3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in
the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.
7.3.23 Temperature sensor characteristics
Table 189. Temperature sensor characteristics

TL(1) VSENSE linearity with temperature - - 3 °C

(2)
Avg_Slope Average slope - 2 - mV/°C
V30(3) Voltage at 30°C ± 5 °C - 0.62 - V
tstart_run Startup time in Run mode (buffer startup) - - 25.2
µs
(1)
tS_temp ADC sampling time when reading the temperature 9 - -
Isens(1) Sensor consumption - 0.18 0.31
µA
Isensbuf(1) Sensor buffer consumption - 3.8 6.5
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1
byte.
Table 190. Temperature sensor calibration values


TS_CAL1 0x1FF1 E820 -0x1FF1 E821
30 °C, VDDA=3.3 V
TS_CAL2 0x1FF1 E840 - 0x1FF1 E841
110 °C, VDDA=3.3 V
DS12117 Rev 7 291/356

321
7.3.24 Temperature and VBAT monitoring
Table 191. VBAT monitoring characteristics

R Resistor bridge for VBAT - 26 - KΩ

Q Ratio on VBAT measurement - 4 - -
(1)
Er Error on Q –10 - +10 %
tS_vbat(1) ADC sampling time when reading VBAT input 9 - - µs
VBAThigh High supply monitoring - 3.55 -
V
VBATlow Low supply monitoring - 1.36 -
Table 192. VBAT charging characteristics

VBRS in PWR_CR3= 0 - 5 -
RBC Battery charging resistor KΩ
VBRS in PWR_CR3= 1 1.5 -
Table 193. Temperature monitoring characteristics

TEMPhigh High temperature monitoring - 117 -

°C
TEMPlow Low temperature monitoring - –25 -
7.3.25 Voltage booster for analog switch
Table 194. Voltage booster for analog switch characteristics(1)

VDD Supply voltage - 1.62 2.6 3.6 V

tSU(BOOST) Booster startup time - - - 50 µs
1.62 V ≤ VDD ≤ 2.7 V - - 125
IDD(BOOST) Booster consumption µA
2.7 V < VDD < 3.6 V - - 250
292/356 DS12117 Rev 7

7.3.26 Comparator characteristics
Table 195. COMP characteristics(1)


Comparator input voltage
VIN - 0 - VDDA V
range
(2)
VBG Scaler input voltage -
VSC Scaler offset voltage - - ±5 ±10 mV
Scaler static consumption BRG_EN=0 (bridge disable) - 0.2 0.3

IDDA(SCALER) µA
from VDDA BRG_EN=1 (bridge enable) - 0.8 1
tSTART_SCALER Scaler startup time - - 140 250 µs
High-speed mode - 2 5
Comparator startup time to
tSTART reach propagation delay Medium mode - 5 20 µs
specification
Ultra-low-power mode - 15 80
High-speed mode - 50 80 ns
Propagation delay for
200 mV step with 100 mV Medium mode - 0.5 1.2
overdrive µs
Ultra-low-power mode - 2.5 7
tD(3)
Propagation delay for step High-speed mode - 50 120 ns
> 200 mV with 100 mV
Medium mode - 0.5 1.2
overdrive only on positive µs
inputs Ultra-low-power mode - 2.5 7
Voffset Comparator offset error Full common mode range - ±5 ±20 mV
No hysteresis - 0 -
Low hysteresis 5 10 22
Vhys Comparator hysteresis mV
Medium hysteresis 8 20 37
High hysteresis 16 30 52
Static - 400 600
Ultra-low- With 50 kHz nA
power mode ±100 mV overdrive - 800 -
square signal
Static - 5 7
Comparator consumption
IDDA(COMP) Medium mode With 50 kHz
from VDDA ±100 mV overdrive - 6 -
square signal
µA
Static - 70 100
High-speed With 50 kHz
mode ±100 mV overdrive - 75 -
square signal
2. Refer to Table 126: Embedded reference voltage.
DS12117 Rev 7 293/356

321
7.3.27 Operational amplifier characteristics
Table 196. Operational amplifier characteristics

Analog supply voltage

VDDA - 2 3.3 3.6
Range
V
Common Mode Input
CMIR - 0 - VDDA
Range
25°C, no load on output - - ±1.5
VIOFFSET Input offset voltage All voltages and mV
- - ±2.5
temperature, no load
ΔVIOFFSET Input offset voltage drift - - ±3.0 - μV/°C
Offset trim step at low
TRIMOFFSETP
TRIMLPOFFSETP (0.1*VDDA)
mV
Offset trim step at high
TRIMOFFSETN
TRIMLPOFFSETN (0.9*VDDA)
ILOAD Drive current - - - 500
μA
ILOAD_PGA Drive current in PGA mode - - - 270
CLOAD Capacitive load - - - 50 pF
Common mode rejection
CMRR - - 80 - dB
ratio
CLOAD ≤ 50pf /
Power supply rejection
PSRR RLOAD ≥ 4 kΩ(1) at 1 kHz, 50 66 - dB
ratio
Vcom=VDDA/2
Gain bandwidth for high 200 mV ≤ Output dynamic
GBW 4 7.3 12.3 MHz
supply range range ≤ VDDA - 200 mV
Slew rate (from 10% and Normal mode - 3 -

SR V/µs
90% of output voltage) High-speed mode - 30 -
200 mV ≤ Output dynamic
AO Open loop gain 59 90 129 dB
range ≤ VDDA - 200 mV
φm Phase margin - - 55 - °
GM Gain margin - - 12 - dB
Iload=max or RLOAD=min, VDDA
VOHSAT High saturation voltage - -
Input at VDDA −100 mV
mV
Iload=max or RLOAD=min,
VOLSAT Low saturation voltage - - 100
Input at 0 V
294/356 DS12117 Rev 7

Table 196. Operational amplifier characteristics (continued)

CLOAD ≤ 50pf,
Normal RLOAD ≥ 4 kΩ,
- 0.8 3.2
mode follower
Wake up time from OFF configuration
tWAKEUP µs
state CLOAD ≤ 50pf,
High
RLOAD ≥ 4 kΩ,
speed - 0.9 2.8
follower
mode
configuration
PGA gain = 2 −1 - 1
Non inverting gain error PGA gain = 4 −2 - 2

value PGA gain = 8 −2.5 - 2.5
PGA gain = 16 −3 - 3
PGA gain = 2 −1 - 1
PGA gain = 4 −1 - 1
PGA gain Inverting gain error value %
PGA gain = 8 −2 - 2
PGA gain = 16 −3 - 3
PGA gain = 2 −1 - 1
External non-inverting gain PGA gain = 4 −3 - 3

error value PGA gain = 8 −3.5 - 3.5
PGA gain = 16 −4 - 4
PGA Gain=2 - 10/10 -
R2/R1 internal resistance PGA Gain=4 - 30/10 -
values in non-inverting
PGA mode(2) PGA Gain=8 - 70/10 -
PGA Gain=16 - 150/10 - kΩ/
Rnetwork
PGA Gain = -1 - 10/10 - kΩ
R2/R1 internal resistance PGA Gain = -3 - 30/10 -
values in inverting PGA
mode(2) PGA Gain = -7 - 70/10 -
PGA Gain = -15 - 150/10 -
Resistance variation (R1
Delta R - −15 - 15 %
or R2)
DS12117 Rev 7 295/356

321
Table 196. Operational amplifier characteristics (continued)

Gain=2 - GBW/2 -
PGA bandwidth for Gain=4 - GBW/4 -

MHz
different non inverting gain Gain=8 - GBW/8 -
Gain=16 - GBW/16 -
PGA BW
Gain = -1 - 5.00 -
PGA bandwidth for Gain = -3 - 3.00 -

MHz
different inverting gain Gain = -7 - 1.50 -
Gain = -15 - 0.80 -
at
- 140 -
1 KHz output loaded nV/√
en Voltage noise density
at with 4 kΩ Hz
- 55 -
10 KHz
Normal
- 570 1000
mode no Load,
OPAMP consumption from
IDDA(OPAMP) High- quiescent mode, µA
VDDA
speed follower - 610 1200
mode
1. RLOAD is the resistive load connected to VSSA or to VDDA.
2. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance
between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
7.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 197 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).
296/356 DS12117 Rev 7

Table 197. DFSDM measured timing 1.62-3.6 V

DFSDM
fDFSDMCLK 1.62 < VDD < 3.6 V - - 133
clock
External clock mode
- - 20
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
External clock mode
- - 20
(SPICKSEL[1:0]=0),
fCKIN Input clock 2.7 < VDD < 3.6 V MH
(1/TCKIN) frequency SPI mode (SITP[1:0]=0,1), z
Internal clock mode
- - 20
(SPICKSEL[1:0]¹0),
1.62 < VDD < 3.6 V
Internal clock mode
- - 20
(SPICKSEL[1:0]¹0),
2.7 < VDD < 3.6 V
Output clock
fCKOUT 1.62 < VDD < 3.6 V - - 20
frequency
Output clock
DuCyCKOU
frequency 1.62 < VDD < 3.6 V 45 50 55 %
T duty cycle
Input clock
twh(CKIN) External clock mode
high and low TCKIN/2-0.5 TCKIN/2 -
twl(CKIN) (SPICKSEL[1:0]=0),
time
1.62 < VDD < 3.6 V
Data input External clock mode
tsu 1.5 - -
setup time (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
ns
Data input External clock mode
th 0.5 - -
hold time (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
Manchester Manchester mode (SITP[1:0]=2,3),
data period Internal clock mode (CKOUTDIV+1) (2*CKOUTDIV)
TManchester -
(recovered (SPICKSEL[1:0]¹0), * TDFSDMCLK * TDFSDMCLK
clock period) 1.62 < VDD < 3.6 V
DS12117 Rev 7 297/356

321
Figure 96. Channel transceiver timing diagrams
DFSDM_CKINy (SPICKSEL=0)
SPI timing : SPICKSEL = 0
twl twh tr tf
tsu th
DFSDM_DATINy
SITP = 00
tsu th
SITP = 01
SPICKSEL=3
DFSDM_CKOUT
SPICKSEL=2
SPI timing : SPICKSEL = 1, 2, 3
SPICKSEL=1
twl twh tr tf
tsu th
DFSDM_DATINy
SITP = 0
tsu th
SITP = 1
SITP = 2
DFSDM_DATINy
Manchester timing
SITP = 3
recovered clock
recovered data 0 0 1 1 0
MS30766V2
298/356 DS12117 Rev 7

7.3.29 Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 198 for DCMI are derived from
tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage
• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load CL=30 pF
Table 198. DCMI characteristics(1)

- Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 -

DCMI_PIXCLK Pixel Clock input - 80 MHz
Dpixel Pixel Clock input duty cycle 30 70 %
tsu(DATA) Data input setup time 3 -
-
th(DATA) Data hold time 1 -
tsu(HSYNC),
DCMI_HSYNC/ DCMI_VSYNC input setup time 2 - ns
tsu(VSYNC)
th(HSYNC),
DCMI_HSYNC/ DCMI_VSYNC input hold time 1 - -
th(VSYNC)
Figure 97. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
tsu(HSYNC) th(HSYNC)
DCMI_HSYNC
tsu(VSYNC) th(HSYNC)
DCMI_VSYNC
tsu(DATA) th(DATA)
DATA[0:13]
MS32414V2
DS12117 Rev 7 299/356

321
7.3.30 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 199 for LCD-TFT are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply
configuration:
• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
Table 199. LTDC characteristics(1)

2.7<VDD<3.6 V
150
LTDC clock 20pF
fCLK output - MHz
frequency 2.7<VDD<3.6 V 133
1.62<VDD<3.6 V 90
DCLK LTDC clock output duty cycle 45 55 %
tw(CLKH),
Clock High time, low time tw(CLK)//2-0.5 tw(CLK)//2+0.5
tw(CLKL)
tv(DATA) 2.7<VDD<3.6 V 0.5 -
Data output valid time -
th(DATA) 1.62<VDD<3.6 V 5
tv(DATA) Data output hold time 0 -
tv(HSYNC), 2.7<VDD<3.6 V - 0.5
HSYNC/VSYNC/DE output
tv(VSYNC),
valid time 1.62<VDD<3.6 V - 5
tv(DE)
th(HSYNC),
th(VSYNC), HSYNC/VSYNC/DE output hold time 0 -
th(DE)
300/356 DS12117 Rev 7

Figure 98. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC) tv(HSYNC)
LCD_HSYNC
tv(DE) th(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
LCD_G[0:7] Pixel Pixel Pixel
1 2 N
LCD_B[0:7]
th(DATA)
HSYNC Horizontal Active width Horizontal

One line
MS32749V1
Figure 99. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC) tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]
VSYNC Vertical Active width Vertical

One frame
MS32750V1
DS12117 Rev 7 301/356

321
7.3.31 Timer characteristics

The parameters given in Table 200 are guaranteed by design.
Refer to Section 7.3.15: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 200. TIMx characteristics(1)(2)

AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK = 1 - tTIMxCLK
240 MHz
tres(TIM) Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK = 1 - tTIMxCLK
120 MHz
Timer external clock
fEXT 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 f
TIMxCLK = 240 MHz
ResTIM Timer resolution - 16/32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.
3. The maximum timer frequency on APB1 or APB2 is up to 240 MHz, by setting the TIMPRE bit in the
RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x
Frcc_pclkx_d2.
7.3.32 Communication interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual revision 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0399 reference manual) and when the i2c_ker_ck frequency is
greater than the minimum shown in the table below:
302/356 DS12117 Rev 7

Table 201. Minimum i2c_ker_ck frequency in all I2C modes

Symbol Parameter Condition Min Unit
Standard-mode - 2
Analog Filtre ON
8
DNF=0
Fast-mode
Analog Filtre OFF MHz
I2CCLK 9
f(I2CCLK) DNF=1
frequency
Analog Filtre ON
17
DNF=0
Fast-mode Plus
Analog Filtre OFF
16 -
DNF=1
The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain,
the PMOS connected between the I/O pin and VDDIOx is disabled, but still present.
• The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load CLoad supported in Fm+, which is given by these formulas:
tr(SDA/SCL)=0.8473xRPxCLoad
RP(min)= (VDD-VOL(max))/IOL(max)
Where RP is the I2C lines pull-up. Refer to Section 7.3.15: I/O port characteristics for
the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog fil-
ter characteristics:
Table 202. I2C analog filter characteristics(1)

Maximum pulse width of spikes

tAF that are suppressed by analog 50(2) 80(3) ns
filter
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.
USART interface characteristics

Unless otherwise specified, the parameters given in Table 203 for USART are derived from
configuration:
DS12117 Rev 7 303/356

321
function characteristics (NSS, CK, TX, RX for USART).
Table 203. USART characteristics(1)

Master mode 12.5

fCK USART clock frequency - - MHz
Slave mode 25
tsu(NSS) NSS setup time Slave mode tker+1 - -
th(NSS) NSS hold time Slave mode 2 - -
-
tw(SCKH),
CK high and low time Master mode 1/fCK/2-2 1/fCK/2 1/fCK/2+2
tw(SCKL)
Master mode tker+6 - -
tsu(RX) Data input setup time
Slave mode 1.5 - -
Master mode 0 - -
th(RX) Data input hold time
Slave mode 1.5 - -
ns
Slave mode - 12 20
tv(TX) Data output valid time
Master mode - 0.5 1
Slave mode 9 - -
th(TX) Data output hold time
Master mode 0 - -
304/356 DS12117 Rev 7

Figure 100. USART timing diagram in Master mode
High
NSS input
tc(SCK)
SCK Output
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
MISO
th(MI)
MOSI
OUTPUT
tv(MO) th(MO)
ai14136c
Figure 101. USART timing diagram in Slave mode
NSS input
tc(SCK) th(NSS)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
th(SI)
tsu(SI)
MSv41658V1
DS12117 Rev 7 305/356

321
SPI interface characteristics

Unless otherwise specified, the parameters given in Table 204 for SPI are derived from tests
configuration:
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 204. SPI characteristics(1)

Master mode
1.62<VDD<3.6 V 80
SPI1, 2, 3
Master mode
2.7<VDD<3.6 V 100
SPI1, 2, 3
Master mode
fSCK SPI clock frequency 1.62<VDD<3.6 V - - 50 MHz
SPI4, 5, 6
Slave receiver mode
100
1.62<VDD<3.6 V
Slave mode transmitter/full duplex
31
2.7<VDD<3.6 V
Slave mode transmitter/full duplex
29
1.62 <VDD<3.6 V
tsu(NSS) NSS setup time Slave mode 2 - -
th(NSS) NSS hold time Slave mode 1 - -
-
tw(SCKH),
SCK high and low time Master mode TPCLK-2 TPCLK TPCLK+2
tw(SCKL)
306/356 DS12117 Rev 7

Table 204. SPI characteristics(1) (continued)

tsu(MI) Master mode 1 - -

tsu(SI) Slave mode 1 - -
th(MI) Master mode 4 - -
th(SI) Slave mode 2 - -
ta(SO) Data output access time Slave mode 9 13 27
tdis(SO) Data output disable time Slave mode 0 1 5
Slave mode ns
- 12.5 16
2.7<VDD<3.6 V
tv(SO)
Data output valid time Slave mode
- 12.5 17
1.62<VDD<3.6 V
tv(MO) Master mode - 1 3
Slave mode
th(SO) 10 - -
Data output hold time 1.62<VDD<3.6 V
th(MO) Master mode 0 - -
Figure 102. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
th(SI)
tsu(SI)
MSv41658V1
DS12117 Rev 7 307/356

321
Figure 103. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
tsu(SI) th(SI)
MSv41659V1
Figure 104. SPI timing diagram - master mode(1)
High
NSS input
tc(SCK)
SCK Output
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
MISO
th(MI)
MOSI
OUTPUT
tv(MO) th(MO)
ai14136c
308/356 DS12117 Rev 7

I2S Interface characteristics

Unless otherwise specified, the parameters given in Table 205 for I2S are derived from tests
configuration:
function characteristics (CK,SD,WS).
Table 205. I2S dynamic characteristics(1)

fMCK I2S main clock output - 256x8K 256FS MHz

Master data - 64FS
fCK I2S clock frequency MHz
Slave data - 64FS
tv(WS) WS valid time Master mode - 3
th(WS) WS hold time Master mode 0 -
tsu(WS) WS setup time Slave mode 1 -
th(WS) WS hold time Slave mode 1 -
tsu(SD_MR) Master receiver 1 -
tsu(SD_SR) Slave receiver 1 -
th(SD_MR) Master receiver 4 -
th(SD_SR) Slave receiver 2 - ns
Slave transmitter (after enable

tv(SD_ST) - 17
edge)
Master transmitter (after
tv(SD_MT) - 3
enable edge)
th(SD_ST) 9 -
edge)
Master transmitter (after
th(SD_MT) 0 -
enable edge)
DS12117 Rev 7 309/356

321
Figure 105. I2S slave timing diagram (Philips protocol)(1)
byte.
Figure 106. I2S master timing diagram (Philips protocol)(1)
byte.
310/356 DS12117 Rev 7

SAI characteristics
Unless otherwise specified, the parameters given in Table 206 for SAI are derived from tests
configuration:
• VOS level set to VOS1.
alternate function characteristics (SCK,SD,WS).
Table 206. SAI characteristics(1)

fMCK SAI Main clock output - 256x8K 256xFS
SAI clock Master Data: 32 bits - 128xFS(3) MHz

fCK
frequency(2) Slave Data: 32 bits - 128xFS(3)
DS12117 Rev 7 311/356

321
Table 206. SAI characteristics(1) (continued)

Master mode
- 13
2.7≤VDD≤3.6
tv(FS) FS valid time
Master mode
- 20
1.62≤VDD≤3.6
tsu(FS) FS hold time Master mode 8 -
FS setup time Slave mode 1 -
th(FS)
FS hold time Slave mode 1 -
tsu(SD_A_MR) Master receiver 0.5 -
tsu(SD_B_SR) Slave receiver 1 -
th(SD_A_MR) Master receiver 3.5 -
th(SD_B_SR) Slave receiver 2 -
edge) - 14 ns
2.7≤VDD≤3.6
tv(SD_B_ST) Data output valid time
edge) - 20
1.62≤VDD≤3.6
th(SD_B_ST) Data output hold time 9 -
edge)
Master transmitter (after enable
edge) - 12
2.7≤VDD≤3.6
tv(SD_A_MT) Data output valid time
edge) - 19
1.62≤VDD≤3.6
th(SD_A_MT) Data output hold time 7.5 -
edge)
2. APB clock frequency must be at least twice SAI clock frequency.
3. With FS=192 kHz.
312/356 DS12117 Rev 7

Figure 107. SAI master timing waveforms

1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)
SAI_SD_X Slot n
(receive)
MS32771V1
Figure 108. SAI slave timing waveforms

1/fSCK
SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X Slot n
(receive)
MS32772V1
MDIO characteristics
Table 207. MDIO Slave timing parameters

FMDC Management Data Clock - - 30 MHz

td(MDIO) Management Data Iput/output output valid time 8 10 19
tsu(MDIO) Management Data Iput/output setup time 1 - - ns
th(MDIO) Management Data Iput/output hold time 1 - -
DS12117 Rev 7 313/356

321
Figure 109. MDIO Slave timing diagram

tMDC)
td(MDIO)
tsu(MDIO) th(MDIO)
MSv40460V1
SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 208 and Table 209 for SDIO are
supply voltage summarized in Table 121: General operating conditions, with the following
configuration:
characteristics.
Table 208. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2)


- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fPP =52MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP =52MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(3)/DDR(3) mode
tISU Input setup time HS - 1.5 - -

ns
tIH Input hold time HS - 1.5 - -
tIDW(4) Input valid window (variable window) - 3 - - -
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR(3) mode
tOV Output valid time HS - - 3.5 5

ns
tOH Output hold time HS - 2 - -
314/356 DS12117 Rev 7

Table 208. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V(1)(2) (continued)
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD - 1.5 -

ns
tIHD Input hold time SD - 1.5 -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD - - 0.5 2

ns
tOHD Output hold default time SD - 0 - -
2. Above 100 MHz, CL = 20 pF.
3. An external voltage converter is required to support SD 1.8 V.
Table 209. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V(1)(2)

Clock frequency in data transfer

fPP - 0 - 120 MHz
mode
- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fPP =52 MHz 8.5 9.5 -
ns
tW(CKH) Clock high time fPP =52 MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS - 1 - -

tIH Input hold time HS - 2.5 - -
ns
Input valid window (variable
tIDW(3) - 3.5 - -
window)
CMD, D outputs (referenced to CK) in eMMC mode
tOVD Output valid time HS - - 5 7

ns
tOHD Output hold time HS - 3 - -
2. CL = 20 pF.
DS12117 Rev 7 315/356

321
Figure 110. SDIO high-speed mode
Figure 111. SD default mode
CK
tOVD tOHD
D, CMD
(output)
ai14888
Figure 112. DDR mode

Clock
MSv36879V1
316/356 DS12117 Rev 7

USB OTG_HS characteristics

Unless otherwise specified, the parameters given in Table 210 for ULPI are derived from
characteristics.
Table 210. Dynamics characteristics: USB ULPI(1)

Control in (ULPI_DIR , ULPI_NXT) setup

tSC - 2.5 - -
time
Control in (ULPI_DIR, ULPI_NXT) hold
tHC - 2 - -
time
tSD Data in setup time - 2.5 - -
ns
tHD Data in hold time - 0 - -
2.7<VDD<3.6 V
- 9 9.5
CL=20 pF
tDC/tDD Control/Datal output delay
1.71<VDD<3.6 V
- 9 14
CL=15 pF
Figure 113. ULPI timing diagram
Clock
tSC tHC
Control In
(ULPI_DIR,
ULPI_NXT) tSD tHD
data In
(8-bit)
tDC tDC
Control out
(ULPI_STP)
tDD
data out
(8-bit)
ai17361c
DS12117 Rev 7 317/356

321
Ethernet interface characteristics

Unless otherwise specified, the parameters given in Table 211, Table 212 and Table 213 for
SMI, RMII and MII are derived from tests performed under the ambient temperature,
frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 121: General
operating conditions, with the following configuration:
characteristics:
Table 211. Dynamics characteristics: Ethernet MAC signals for SMI (1)
tMDC MDC cycle time( 2.5 MHz) 400 400 403

Td(MDIO) Write data valid time 0.5 1.5 4
ns
tsu(MDIO) Read data setup time 12.5 - -
th(MDIO) Read data hold time 0 - -
Figure 114. Ethernet SMI timing diagram

tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO) th(MDIO)
ETH_MDIO(I)
MS31384V1
318/356 DS12117 Rev 7

Table 212. Dynamics characteristics: Ethernet MAC signals for RMII (1)

tsu(CRS) Carrier sense setup time 1.5 - -
ns
tih(CRS) Carrier sense hold time 1.5 - -
td(TXEN) Transmit enable valid delay time 7 8 9.5
td(TXD) Transmit data valid delay time 8 9 11
Figure 115. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667b
Table 213. Dynamics characteristics: Ethernet MAC signals for MII (1)

tsu(DV) Data valid setup time 1.5 - -
tih(DV) Data valid hold time 1.5 - -
ns
tsu(ER) Error setup time 1.5 - -
tih(ER) Error hold time 0.5 - -
td(TXEN) Transmit enable valid delay time 9 10 11
td(TXD) Transmit data valid delay time 8.5 9.5 12.5
DS12117 Rev 7 319/356

321
Figure 116. Ethernet MII timing diagram
MII_RX_CLK
tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668b
JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 214 and Table 215 for
JTAG/SWD are derived from tests performed under the ambient temperature, frcc_c_ck
frequency and VDD supply voltage summarized in Table 121: General operating conditions,
with the following configuration:
characteristics:
Table 214. Dynamics JTAG characteristics

Fpp 2.7V <VDD< 3.6 V - - 37

TCK clock frequency
1/tc(TCK) 1.62 <VDD< 3.6 V - - 27.5
MHz
tisu(TMS) TMS input setup time - 2.5 - -
tih(TMS) TMS input hold time - 1 - -
tisu(TDI) TDI input setup time - 1.5 - - -
tih(TDI) TDI input hold time - 1 - - -
2.7V <VDD< 3.6 V - 8 13.5 -
tov(TDO) TDO output valid time
1.62 <VDD< 3.6 V - 8 18 -
toh(TDO) TDO output hold time - 7 - - -
320/356 DS12117 Rev 7

Table 215. Dynamics SWD characteristics:

Fpp 2.7V <VDD< 3.6 V - - 71

SWCLK clock frequency MHz
1/tc(SWCLK) 1.62 <VDD< 3.6 V - - 52.5
tisu(SWDIO) SWDIO input setup time - 2.5 - - -
tih(SWDIO) SWDIO input hold time - 1 - - -
2.7V <VDD< 3.6 V - 8.5 14 -
tov(SWDIO) SWDIO output valid time 1.62 <VDD< 3.6 V
- 8.5 19 -
toh(SWDIO) SWDIO output hold time - 8 - - -
Figure 117. JTAG timing diagram

tc(TCK)
TCK
tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO) toh(TDO)
TDO
MSv40458V1
Figure 118. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH)

SWDIO
(receive)
tov(SWDIO) toh(SWDIO)
SWDIO
(transmit)
MSv40459V1
DS12117 Rev 7 321/356

321
Package information STM32H753xI
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at www.st.com.
ECOPACK® is an ST trademark.
8.1 LQFP100 package information

LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package.
Figure 119. LQFP100 package outline
SEATING PLANE
C
0.25 mm
A2
A
A1
c
GAUGE PLANE
ccc C
A1
K
L
D1
L1
D3
75 51
76 50
b
E1
E3
100 26
PIN 1 1 25
IDENTIFICATION
e 1L_ME_V5
1. Drawing is not to scale.
322/356 DS12117 Rev 7

STM32H753xI Package information
Table 216. LQPF100 package mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DS12117 Rev 7 323/356

351
Figure 120. LQFP100 recommended footprint

75 51
76 50
0.5
0.3
16.7 14.3
100 26
1.2
1 25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
324/356 DS12117 Rev 7

Device marking for LQFP100

The following figure gives an example of topside marking versus pin 1 position identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which depend on supply chain operations, are
not indicated below.
Figure 121. LQFP100 marking example (package top view)
Product identification(1)
ES32H753VIT6
R Revision code
Date code
Y WW
Pin 1
indentifier
MSv46105V1
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not approved for use in production. ST is not responsible for any consequences
resulting from such use. In no event will ST be liable for the customer using any of these engineering
samples in production. ST’s Quality department must be contacted prior to any decision to use these
engineering samples to run a qualification activity.
DS12117 Rev 7 325/356

351
8.2 TFBGA100 package information

TFBGA100 is a 100-ball, 8 x 8 mm, 0.8 mm pitch, thin fine-pitch ball grid array package.
Figure 122. TFBGA100 package outline
ddd C
SEATING
PLANE
A1
A
A2
A1 ball
index
B
D1 A1 ball area
identifier
e D
F
A
B
C
G
D
E
E1
E
F
G
e
H A
J
K
10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW TOP VIEW

b (100 BALLS)
eee C A B
fff C
A08Q_ME_V1
Table 217. TFBGA100 package mechanical data

Symbol
A - - 1.100 - - 0.0433
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 7.850 8.000 8.150 0.3091 0.3150 0.3209
326/356 DS12117 Rev 7

Table 217. TFBGA100 package mechanical data (continued)

Symbol
D1 - 7.200 - 0.2835 -
E 7.850 8.000 8.150 0.3091 0.3150 0.3209
E1 - 7.200 - - 0.2835 -
e - 0.800 - - 0.0315 -
F - 0.400 - - 0.0157 -
G - 0.400 - - 0.0157 -
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0031
Figure 123. TFBGA100 package recommended footprint
Dpad
Dsm
Table 218. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA)
Dimension Recommended values
Pitch 0.8
Dpad 0.400 mm
0.470 mm typ (depends on the soldermask
Dsm
registration tolerance)
DS12117 Rev 7 327/356

351
Table 218. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA) (contin-
Stencil opening 0.400 mm

Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm
Device marking for TFBGA100

location.
Figure 124. TFBGA100 marking example (package top view)
Product
identification(1)
ESH753 Revision code
VHI6
R
Date code
Ball Y WW
A1identifier
MSv61383V1
328/356 DS12117 Rev 7



SEATING
PLANE
C
A
A1
A2
c
0.25 mm
ccc C GAUGE PLANE
A1
D
L
K
D1
L1
D3
108 73
109
72
b
E1
E3
37
144
PIN 1 1 36
IDENTIFICATION
e
1A_ME_V4
DS12117 Rev 7 329/356

351
Table 219. LQFP144 package mechanical data

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.6890 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
330/356 DS12117 Rev 7

Figure 126. LQFP144 package recommended footprint
1.35
108 73
109 0.35 72
0.5
19.9 17.85
22.6
144 37
1 36
19.9
22.6
ai14905e
DS12117 Rev 7 331/356

351

location.
Revision code
R
ES32H753ZIT6
Date code
Y WW
Pin 1 identifier
MSv46107V2
332/356 DS12117 Rev 7

8.4 UFBGA169 package information

UFBGA169 is a 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 128. UFBGA169 package outline

Z Seating plane
A2 A4
ddd Z
A
A3 A1
b
SIDE VIEW A1 ball A1 ball
identifier index area X
E
E1
e F
A
F
D1 D
e
Y
N
13 1
BOTTOM VIEW Øb (169 balls) TOP VIEW

Ø eee M Z X Y
Ø fff M Z
A0YV_ME_V2
1. Drawing is not in scale.
Table 220. UFBGA169 package mechanical data

Symbol
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.950 6.000 6.050 0.2343 0.2362 0.2382
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.950 6.000 6.050 0.2343 0.2362 0.2382
e - 0.500 - - 0.0197 -
F 0.450 0.500 0.550 0.0177 0.0197 0.0217
DS12117 Rev 7 333/356

351
Table 220. UFBGA169 package mechanical data (continued)

Symbol
ddd - - 0.100 - - 0.0039

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
Device marking for UFBGA169

location.
Figure 129. UFBGA169 marking example (package top view)
Ball A1
identifier
ES32H753
AII6
Date code
Y WW
Revision code
MSv61384V1
334/356 DS12117 Rev 7


LQFP176 is a 176-pin, 24 x 24 mm low profile quad flat package.
C Seating plane
A
c
A1
A2
0.25 mm
gauge plane
k
A1
L
HD L1
PIN 1 D
IDENTIFICATION
ZE
E
HE
ZD
b
1T_ME_V2

Dimensions
Ref. Millimeters Inches(1)
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 - 1.450 0.0531 - 0.0571
b 0.170 - 0.270 0.0067 - 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
DS12117 Rev 7 335/356

351
Table 221. LQFP176 package mechanical data (continued)

Dimensions
Ref. Millimeters Inches(1)
D 23.900 - 24.100 0.9409 - 0.9488

HD 25.900 - 26.100 1.0197 - 1.0276
ZD - 1.250 - - 0.0492 -
E 23.900 - 24.100 0.9409 - 0.9488
HE 25.900 - 26.100 1.0197 - 1.0276
ZE - 1.250 - - 0.0492 -
e - 0.500 - - 0.0197 -
L(2) 0.450 - 0.750 0.0177 - 0.0295
L1 - 1.000 - - 0.0394 -
k 0° - 7° 0° - 7°
ccc - - 0.080 - - 0.0031
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
336/356 DS12117 Rev 7

1.2
176 133
1 0.5 132
0.3
26.7
21.8
44 89
45 88
1.2
21.8
26.7
1T_FP_V1
DS12117 Rev 7 337/356

351

location.
ES32H753IIT6
Date code
Revision code
Y WW
R
Pin 1identifier
MSv46109V2
338/356 DS12117 Rev 7


SEATING
PLANE
C
A2
A
A1
c
ccc C
0.25 mm
GAUGE PLANE
A1
K
L
D L1
D1
D3
156 105
157 104
b
E1
E3
208
53
PIN 1
IDENTIFICATION 1 52
e
UH_ME_V2
DS12117 Rev 7 339/356

351

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 29.800 30.000 30.200 1.1811 1.1732 1.1890
D1 27.800 28.000 28.200 1.1024 1.0945 1.1102
D3 - 25.500 - - 1.0039 -
E 29.800 30.000 30.200 1.1811 1.1732 1.1890
E1 27.800 28.000 28.200 1.1024 1.0945 1.1102
E3 - 25.500 - - 1.0039 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
340/356 DS12117 Rev 7


208 157
1 0.5
156
1.25
0.3
28.3
30.7
52 105
53 104 1.2
25.8
30.7
UH_FP_V2
DS12117 Rev 7 341/356

351

location.
Revision code
Product identification(1) R
ES32H753BIT6
Y WW
Pin 1 identifier Date code
MSv46111V2
342/356 DS12117 Rev 7

8.7 UFBGA176+25 package information

UFBGA176+25 is a 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package.
Figure 136. UFBGA176+25 package outline

Seating plane
C A4
ddd C
A
A3 A2 b A1
A1 ball A
A1 ball index E
identifier area
E1
e Z
A
Z
D1 D
e
B
R
15 1
Øb (176 + 25 balls)
BOTTOM VIEW Ø eee M C A B
TOP VIEW
Ø fff M C
A0E7_ME_V8
Table 223. UFBGA176+25 package mechanical data

Symbol
A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.130 - - 0.0051 -
A3 - 0.450 - - 0.0177 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 9.850 10.000 10.150 0.3878 0.3937 0.3996
D1 - 9.100 - - 0.3583 -
E 9.850 10.000 10.150 0.3878 0.3937 0.3996
E1 - 9.100 - - 0.3583 -
e - 0.650 - - 0.0256 -
Z - 0.450 - - 0.0177 -
ddd - - 0.080 - - 0.0031
DS12117 Rev 7 343/356

351
Table 223. UFBGA176+25 package mechanical data (continued)

Symbol
eee - - 0.150 - - 0.0059

fff - - 0.050 - - 0.0020
Figure 137. UFBGA176+25 package recommended footprint
Dpad
Dsm
A0E7_FP_V1
Table 224. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Pitch 0.65 mm
Dpad 0.300 mm
0.400 mm typ. (depends on the soldermask
Dsm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
344/356 DS12117 Rev 7

Device marking for UFBGA176+25

location.
Figure 138. UFBGA176+25 marking example (package top view)
Revision code
R
ES32H753
IIK6
Date code
Ball
A1identifier
Y WW
MSv46113V1
DS12117 Rev 7 345/356

351
8.8 TFBGA240+25 package information

TFBGA240+25 is a 265 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array
package.
Figure 139. TFBGA240+25 package outline
ddd C
SEATING
PLANE
C
A2
A1
A
D1 A1 ball identifier D
e
A
E
E1
S
17 1
F
b (240 + 25 balls)
BOTTOM VIEW TOP VIEW
A07U_ME_V1
346/356 DS12117 Rev 7

Table 225. TFBG240+25 ball package mechanical data

Symbol
A - - 1.100 - - 0.0433
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 13.850 14.000 14.150 0.5453 0.5512 0.5571
D1 - 12.800 - - 0.5039 -
E 13.850 14.000 14.150 0.5453 0.5512 0.5571
E1 - 12.800 - - 0.5039 -
e - 0.800 - - 0.0315 -
F - 0.600 - - 0.0236 -
G - 0.600 - - 0.0236 -
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0031
Figure 140. TFBGA240+25 package recommended footprint
Dpad
Dsm
A07U_FP_V2
DS12117 Rev 7 347/356

351
Table 226. TFBGA240+25 recommended PCB design rules (0.8 mm pitch)

Pitch 0.8 mm
Dpad 0.225 mm
0.290 mm typ. (depends on the soldermask
Dsm
Stencil thickness 0.100 mm
Device marking for TFBGA240+25

location.
Figure 141. TFBGA240+25 marking example (package top view)
Product
identification(1)
STM32H753XIH6 Revision code
R
Date code
Ball
A1identifier Y WW
MSv46115V1
348/356 DS12117 Rev 7

8.9 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
• TA max is the maximum ambient temperature in ° C,
• ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 227. Thermal characteristics(1)

Symbol Definition Parameter Value Unit
Thermal resistance junction-ambient
45.0
LQFP100 - 14 x 14 mm /0.5 mm pitch
39.3
TFBGA100 - 8 x 8 mm /0.8 mm pitch
43.7
37.7
Thermal resistance UFBGA169 - 7 x 7 mm /0.5 mm pitch
ΘJA °C/W
junction-ambient Thermal resistance junction-ambient
43.0
42.4
37.4
UFBGA176+25 - 10 x 10 mm /0.65 mm pitch
36.6
TFBGA240+25 - 14 x 14 mm / 0.8 mm pitch
DS12117 Rev 7 349/356

351
Table 227. Thermal characteristics(1) (continued)

Symbol Definition Parameter Value Unit
11.5
17.1
11.3
TBD
ΘJC °C/W
junction-case Thermal resistance junction-ambient
11.2
11.1
23.9
7.4
36.3
21.1
38.3
TBD
ΘJB °C/W
junction-board Thermal resistance junction-ambient
39.4
40.3
19.3
24.3
1. TBD stands for “to be defined”.
8.9.1 Reference document

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
• For information on thermal management, refer to application note “Thermal
management guidelines for STM32 32-bit Arm Cortex MCUs applications” (AN5036)
available from www.st.com.
350/356 DS12117 Rev 7

STM32H753xI Ordering information
9 Ordering information
Example: STM32 H 753 X I T 6 TR
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
H = High performance
Device subfamily
753 = STM32H7x3 with cryptographic accelerator
Pin count
V = 100 pins
Z = 144 pins
A = 169 pins
I = 176 pins/balls
B = 208 pins
X = 240 balls
Flash memory size

I = 2 Mbytes
Package
T = LQFP ECOPACK®2
K = UFBGA pitch 0.65 mm ECOPACK®2
I = UFBGA pitch 0.5 mm ECOPACK®2
H = TFBGA ECOPACK®2
Temperature range
6 = Industrial temperature range, –40 to 85 °C
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
DS12117 Rev 7 351/356

351
Revision history STM32H753xI
10 Revision history
Table 228. Document revision history

Date Revision Changes
22-Jun-2017 1 Initial release.

Updated list of features.
Changed datasheet status to “production data”.
Added UFBGA169 and TFBGA100 packages as well as notes related to
TFBGA100 and UFBGA169 status on cover page and in Table 2: STM32H753xI
features and peripheral counts.
Differentiated number of GPIOs for each package in Table 2: STM32H753xI
features and peripheral counts.
Updated Error code correction (ECC) in Section 3.3.3: Embedded SRAM.
Change PWR_CR3 into PWR_D3CR in Section 3.5.1: Power supply scheme.
Updated Section 3.12: Nested vectored interrupt controller (NVIC).
Added Table 4: DFSDM implementation in Section 3.23: Digital filter for sigma-
delta modulators (DFSDM).
Changed PC2/3 to PC2/3_C and VDD33USB to VDD in Figure 4: LQFP100
pinout. Changed PC2/3 to PC2/3_C in Figure 6: LQFP144 pinout. Changed PC2/3
to PC2/3_C in Figure 8: LQFP176 pinout. Changed PC2/3 to PC2/3_C in
Figure 10: LQFP208 pinout.
27-Sep-2017 2
Table 8: Pin/ball definition:
– Modified PA7, PC4, PC5, PB1, PG1, PE7, PE8 and PE9 I/O structure
– TFBGA240 +25: removed duplicate occurrence of F1, F2 and P17 pin; added
notes related to F1, F2, G2 pin connection; added note on E1, L16, L17, M16,
M17, K16, K17, N17.
– UFBGA176+25: changed G10 pin name to VSS.
– Added note to VREF+ pin.
Added current consumption corresponding to 125 °C ambient temperature in
Section 6.3.6: Supply current characteristics.
Replaced FMC_CLK by FMC_SDCLK in Section : SDRAM waveforms and
timings.
Changed description of the last five fS values and updated tLATRINJin Table 86:
ADC characteristics.
For TFBGA100, TFBGA240+25 and UFBGA169, updated thermal resistance
power-junction in Table 227: Thermal characteristics as well as power dissipation
Total current consumption changed to 4 µA minimum in Features.
Updated Figure 7: UFBGA169 ballout.
23-Oct-2017 3
Updated dpad and dsm in Table 226: TFBGA240+25 recommended PCB design
rules (0.8 mm pitch).
352/356 DS12117 Rev 7

STM32H753xI Revision history

Updated LSI clock frequency and ADC on cover page. Removed note related to
UFBGA169 package.
Updated ADC features on cover page and in Table 2: STM32H753xI features and
peripheral counts.
Added Arm trademark notice in Section 1: Introduction.
Updated USB OTG interfaces to add crystal-less capability.
Updated Figure 1: STM32H753xI block diagram.
Updated GPIO default mode in Section 3.8: General-purpose input/outputs
(GPIOs).
Added ADC sampling rate values in Section 3.17: Analog-to-digital converters
(ADCs).
Updated Section 3.18: Temperature sensor.
Updated LCD-TFT FIFO Size in Section 3.25: LCD-TFT controller.
Section 3.34: Serial peripheral interface (SPI)/inter- integrated sound interfaces
(I2S): changed maximum SPI frequency to 150 Mbits/s.
Modified number of bidirectional endpoints in Section 3.41: Universal serial bus
on-the-go high-speed (OTG_HS).
Table 8: Pin/ball definition:
– Updated PC14 and PC15 function after reset.
18-May-2018 4 – Changed CAN1_TX/RX to FDCAN1_TX/RX and CAN1_TXFD/RXFD to
FDCAN1_TXFD_MODE/RXFD_MODE
– Changed CAN2_TX/RX to FDCAN2_TX/RX and CAN2_TXFD/RXFD to
FDCAN2_TXFD_MODE/RXFD_MODE
Replaced VCAP1/2/3 and VDDLDO1/2/3 by VCAP and VDDLDO, respectively.
Updated PA0, PA13, PA14, PC14 and PC15 pin/ball signals in pinout/ballout
schematics.
Replaced fACLK by frcc_c_ck in Section : Typical and maximum current
consumption. Replaced system clock by CPU clock and fACLK by frcc_c_ck in
Section : On-chip peripheral current consumption.
Updated Note 2. in Table 26: Reset and power control block characteristics.
Updated Table 27: Embedded reference voltage, Table 29: Typical and maximum
current consumption in Run mode, code with data processing running from ITCM,
regulator ON, Table 30: Typical and maximum current consumption in Run mode,
code with data processing running from Flash memory, cache ON, regulator ON
and Table 35: Typical and maximum current consumption in Stop mode, regulator
ON.
Updated typical and maximum current consumption in Table 36: Typical and
maximum current consumption in Standby mode and Table 37: Typical and
maximum current consumption in VBAT mode.
Added note to fLSI in Table 48: LSI oscillator characteristics.
DS12117 Rev 7 353/356

355
Revision history STM32H753xI

Updated Figure 21: VIL/VIH for all I/Os except BOOT0.

Added note in Table 83: QUADSPI characteristics in SDR mode, Table 84:
QUADSPI characteristics in DDR mode and Table 85: Dynamics characteristics:
Delay Block characteristics.
Section 6.3.20: 16-bit ADC characteristics: updated THD conditions in Table 87:
ADC accuracy; removed formula to compute RAIN.
Changed decoupling capacitor value to 100 nF in Section : General PCB design
18-May-2018 4 (continued) guidelines.
Added note in Table 88: DAC characteristics, Table 96: Voltage booster for analog
switch characteristics, Table 99: DFSDM measured timing 1.62-3.6 V, Table 116:
Dynamics JTAG characteristics and Table 117: Dynamics SWD characteristics.
Updated Figure 127: LQFP144 marking example (package top view), Figure 132:
LQFP176 marking example (package top view) and Figure 135: LQFP208 marking
example (package top view).
Updated TFBGA240+25 package information to final mechanical data.
Added description of power-up and power-down phases in Section 3.5.1: Power
supply scheme.
Removed ETH_TX_ER from Table 8: Pin/ball definition and Table 9: Port A
alternate functions to Table 19: Port K alternate functions.
Added note related to decoupling capacitor tolerance below Figure 14: Power
supply scheme.
Added note 2. related to CEXT in Table 24: VCAP operating conditions.
13-Jul-2018 5 Updated Table 45: HSI48 oscillator characteristics, Table 46: HSI oscillator
characteristics and Table 47: CSI oscillator characteristics.
Renamed Table 49 into “PLL characteristics (wide VCO frequency range)” and
updated note 2.. Added Table 50: PLL characteristics (medium VCO frequency
range).
Updated Tcoeff in Table 90: VREFBUF characteristics.
Updated tS_vbat in Table 93: VBAT monitoring characteristics.
Updated Table 98: OPAMP characteristics.
354/356 DS12117 Rev 7

STM32H753xI Revision history

Changed maximum Arm Core-M7 frequency to 480 MHz.

Features:
– Changed operational amplifier bandwidth to 7.3 MHz
– Updated high-resolution timer to 2.1 ns
– Updated low-power consumption feature
Changed FMC NOR/NAND maximum clock frequency to 100 MHz in Features
and Synchronous waveforms and timings.
Updated voltage scaling in Section 3.5.1: Power supply scheme. Added VOS0 in
Section 3.5.3: Voltage regulator.
Updated HSE clock in Section 3.7.1: Clock management.
Added note related to VDDLDO in Table 8: Pin/ball definition.
Updated Section 6: Electrical characteristics (rev Y):
– Added note 2. related to CEXT in Table 24: VCAP operating conditions
– Updated fHSI48 in Table 45: HSI48 oscillator characteristics.
– Updated tstab in Table 46: HSI oscillator characteristics.
– Added Table 61: Output voltage characteristics for PC13, PC14, PC15 and PI8.
05-Apr-2019 6 – Updated Table 59: I/O static characteristics and Figure 21: VIL/VIH for all I/Os
except BOOT0.
– Added note related to PC13, PC14, PC15 an PI8 limited frequency in Table 62:
Output timing characteristics (HSLV OFF).
– Updated note 2 below Figure 22: Recommended NRST pin protection.
– Table 86: ADC characteristics: updated fS and added note related to fS formula;
updated tCAL.
– Renamed Section 6.3.24 into Temperature and VBAT monitoring and content
updated.
– Updated fDFSDMCLK in Table 99: DFSDM measured timing 1.62-3.6 V.
Added Section 7: Electrical characteristics (rev V).
Section 8: Package information:
– Updated paragraph introducing all package marking schematics to add the new
sentence “The printed markings may differ depending on the supply chain.”
– Added Section : Device marking for TFBGA100 and Section : Device marking
for UFBGA169.
– Updated Table 227: Thermal characteristics.
Added note related to ECOPACK®2 compliance in Table 9: Ordering information.
Updated Figure 1: STM32H753xI block diagram
Updated Table 8: Pin/ball definition.
Updated Table 9 to Table 19 (alternate functions).
Updated Table 38: Peripheral current consumption in Run mode.
24-Apr-2019 7
Updated Table 136: Peripheral current consumption in Run mode.
Updated Table 183: ADC characteristics.
Updated Table 184: Minimum sampling time vs RAIN.
Updated Table 185: ADC accuracy.
DS12117 Rev 7 355/356

355
STM32H753xI
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
356/356 DS12117 Rev 7

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STM32H753xI

32-bit Arm® Cortex®-M7 480MHz MCUs, 2MB Flash,

Features FBGA FBGA

April 2019 DS12117 Rev 7 1/356

Interconnect matrix • Chrom-ART graphical hardware Accelerator™

4 DMA controllers to unload the CPU Up to 22 timers and watchdogs

• 2× dual-port DMAs with FIFO • 2× 32-bit timers with up to 4 IC/OC/PWM or

• SWPMI single-wire protocol master I/F Cryptographic acceleration

11 analog peripherals All packages are ECOPACK®2 compliant

2/356 DS12117 Rev 7

DS12117 Rev 7 3/356

3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4/356 DS12117 Rev 7

6 Electrical characteristics (rev Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

DS12117 Rev 7 5/356

6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

7 Electrical characteristics (rev V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

6/356 DS12117 Rev 7

7.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

DS12117 Rev 7 7/356

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

8/356 DS12117 Rev 7

Table 45. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

DS12117 Rev 7 9/356

Table 97. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

10/356 DS12117 Rev 7

Table 143. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

DS12117 Rev 7 11/356

Table 195. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

12/356 DS12117 Rev 7

Figure 1. STM32H753xI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DS12117 Rev 7 13/356

14/356 DS12117 Rev 7

Figure 101. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

DS12117 Rev 7 15/356

This document provides information on STM32H53xI microcontrollers, such as description,

16/356 DS12117 Rev 7

DS12117 Rev 7 17/356

18/356 DS12117 Rev 7

Table 2. STM32H753xI features and peripheral counts

Flash memory in Kbytes 2 x 1 Mbyte

DS12117 Rev 7 19/356

Table 2. STM32H753xI features and peripheral counts (continued)

SPI / I2S 6/3(1)

20/356 DS12117 Rev 7

DS12117 Rev 7 21/356

Figure 1. STM32H753xI block diagram

AXI/AHB12 (200MHz) 8 Stream 8 Stream DMA/ DMA/ DMA/

64-bit AXI BUS-MATRIX

Delay block AHB2 (200MHz) 16b

SD, SCK, FS, MCLK, D/CK[4:1] as SAI3

1 chan. (TIM17_CH1, BKIN as AF SDO, SDI, CK, WS, MCK, as AF

2 chan. (TIM_CH15[1:2], BKIN as AF Mux2 I2C2/SMBUS SCL, SDA, SMBAL as AF

MOSI, MISO, SCK, NSS as AF SPI4 AHB4

4 compl. chan. (TIM1_CH1[1:4]N), TIM1/PWM

PA..J[15:0] GPIO PORTA.. J