STM 32 F 423 CH

STM32F423xH
Arm®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, 1.5MB Flash,

320KB RAM, USB OTG FS, 1 ADC, 2 DACs, 2 DFSDMs, AES
Datasheet - production data
Features )%*$
• Dynamic Efficiency Line with eBAM (enhanced

Batch Acquisition Mode)
UFBGA100
– 1.7 V to 3.6 V power supply WLCSP81 LQFP64 (10x10mm)
UFQFPN48 (7x7mm)
(4.039x3.951 mm) LQFP100 (14x14mm) (7x7 mm) UFBGA144
– -40 °C to 85/105/125 °C temperature range LQFP144 (20x20mm) (10x10mm)
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART • Up to 18 timers: up to twelve 16-bit timers, two
Accelerator™) allowing 0-wait state execution 32-bit timers up to 100 MHz each with up to
from Flash memory, frequency up to 100 MHz, four IC/OC/PWM or pulse counter and
memory protection unit, 125 DMIPS/ quadrature (incremental) encoder input, two
1.25 DMIPS/MHz (Dhrystone 2.1), and DSP watchdog timers (independent and window),
instructions one SysTick timer, and a low-power timer
• Memories • Debug mode
– 1.5 Mbytes of Flash memory – Serial wire debug (SWD) & JTAG
– 320 Kbytes of SRAM – Cortex®-M4 Embedded Trace Macrocell™
– Flexible external static memory controller • Up to 114 I/O ports with interrupt capability
with up to 16-bit data bus: SRAM, PSRAM, – Up to 109 fast I/Os up to 100 MHz
NOR Flash memory – Up to 114 five V-tolerant I/Os
– Dual mode Quad-SPI interface • Up to 24 communication interfaces
• LCD parallel interface, 8080/6800 modes – Up to 4x I2C interfaces (SMBus/PMBus)
• Clock, reset and supply management – Up to 10 UARTS: 4 USARTs / 6 UARTs
– 1.7 to 3.6 V application supply and I/Os (2 x 12.5 Mbit/s, 2 x 6.25 Mbit/s), ISO 7816
– POR, PDR, PVD and BOR interface, LIN, IrDA, modem control)
– 4-to-26 MHz crystal oscillator – Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or
I2S audio protocol), out of which 2 muxed
– Internal 16 MHz factory-trimmed RC full-duplex I2S interfaces
– 32 kHz oscillator for RTC with calibration – SDIO interface (SD/MMC/eMMC)
– Internal 32 kHz RC with calibration – Advanced connectivity: USB 2.0 full-speed
• Power consumption device/host/OTG controller with PHY
– Run: 112 µA/MHz (peripheral off) – 3x CAN (2.0B Active)
– Stop (Flash in Stop mode, fast wakeup – 1xSAI
time): 42 µA Typ.; 80 µA max @25 °C • True random number generator
– Stop (Flash in Deep power down mode, • CRC calculation unit
slow wakeup time): 15 µA Typ.;
46 µA max @25 °C • 96-bit unique ID
– Standby without RTC: 1.1 µA Typ.; • RTC: subsecond accuracy, hardware calendar
14.7 µA max at @85 °C • 128/256-bit hardware encryption accelerator
– VBAT supply for RTC: 1 µA @25 °C (AES)
• 2x12-bit D/A converters • All packages are ECOPACK®2
• 1×12-bit, 2.4 MSPS ADC: up to 16 channels Table 1. Device summary
• 6x digital filters for sigma delta modulator, Reference Part number
12x PDM interfaces, with stereo microphone
and sound source localization support STM32F423xH
STM32F423CH STM32F423MH STM32F423RH
STM32F423VH STM32F423ZH
• General-purpose DMA: 16-stream DMA
September 2017 DocID029161 Rev 7 1/209

This is information on a product in full production. www.st.com
Contents STM32F423xH
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . . 19
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 19
3.3 Enhanced Batch Acquisition mode (eBAM) . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 20
3.7 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.10 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 22
3.11 Quad-SPI memory interface (QUAD-SPI) . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.17.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.17.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.18.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 31
3.19 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 31
3.20 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.22.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.22.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.24 Universal synchronous/asynchronous receiver transmitters (USART) . . 36
3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.26 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.27 Serial Audio interface (SAI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.28 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.29 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 39
3.30 Dynamic tuning of PDM delays for sound source localization . . . . . . . . . 39
3.31 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 40
3.32 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.33 Universal serial bus on-the-go full-speed (USB_OTG_FS) . . . . . . . . . . . 40
3.34 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.35 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 41
3.36 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.37 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.38 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.39 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.40 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.41 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.1 WLCSP81 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 UFQFPN48 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3 LQFP64 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.4 LQFP100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5 LQFP144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Contents STM32F423xH
4.6 UFBGA100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.7 UFBGA144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.8 Pins definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.9 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.2 VCAP_1/VCAP_2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.3 Operating conditions at power-up/power-down (regulator ON) . . . . . . . 86
6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 87
6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 87
6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 117
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 122
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.25 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.26 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.27 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics . . . 173
6.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.1 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.5 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.6 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
7.7 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Appendix A Recommendations when using the internal reset OFF . . . . . . . . 202
Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

B.1 Sensor Hub application example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
B.2 Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
B.3 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 205
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
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List of tables STM32F423xH
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F423xH features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Embedded bootloader interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 31
Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. DFSDM feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 10. STM32F423xH pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 11. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 12. STM32F423xH alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 13. STM32F423xH register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 18. Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 19. VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 20. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 86
Table 21. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 87
Table 22. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 23. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 89
accelerator disabled) running from SRAM - VDD = 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 25. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V . . . 91
(ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V . . 92
(ART accelerator disabled) running from Flash memory - VDD = 3.6 V. . . . . . . . . . . . . . . 93
(ART accelerator disabled) running from Flash memory - VDD = 1.7 V. . . . . . . . . . . . . . . 94
(ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V . . . . . 95
(ART accelerator enabled with prefetch) running from Flash memory - VDD = 1.7 V . . . . . 96
Table 31. Typical and maximum current consumption in Sleep mode - VDD = 3.6 V . . . . . . . . . . . . . 97
Table 32. Typical and maximum current consumption in Sleep mode - VDD = 1.7 V . . . . . . . . . . . . . 98
Table 33. Typical and maximum current consumptions in Stop mode - VDD = 1.7 V . . . . . . . . . . . . . 99
Table 34. Typical and maximum current consumption in Stop mode - VDD=3.6 V. . . . . . . . . . . . . . . 99
Table 35. Typical and maximum current consumption in Standby mode - VDD= 1.7 V . . . . . . . . . . . 99
Table 36. Typical and maximum current consumption in Standby mode - VDD= 3.6 V . . . . . . . . . . 100
Table 37. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 100
Table 38. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 39. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 40. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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STM32F423xH List of tables
Table 41. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 42. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 43. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 44. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 45. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 46. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 47. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 48. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 49. SSCG parameter constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 50. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 51. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 52. Flash memory programming with VPP voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 53. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 54. EMS characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 55. EMI characteristics for LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 56. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 57. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 58. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 59. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 60. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 61. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 62. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 63. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 64. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 65. SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 66. FMPI2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 67. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 68. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 69. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 70. QSPI dynamic characteristics in SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 71. QSPI dynamic characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 72. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 73. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 74. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 75. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 76. ADC accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 79. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 147
Table 80. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 147
Table 81. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 82. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 83. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 84. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 85. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 86. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 87. DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR -
read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -
NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 162
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List of tables STM32F423xH
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -

NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 92. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 164
Table 94. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 166
Table 96. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 97. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 99. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 100. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 101. eMMC characteristics VDD = 1.7 V to 1.9 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 102. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 103. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 104. WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 178
Table 105. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Table 106. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
Table 107. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 108. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 109. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 110. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 195
Table 111. UFBGA144 - 144-ball, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid
array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 112. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA) . . . . . . . . . . . . . . . . 198
Table 113. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 114. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 115. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
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STM32F423xH List of figures
List of figures
Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3. Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 4. STM32F423xH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6. VDDUSB connected to an external independent power supply . . . . . . . . . . . . . . . . . . . . . 26
Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 27
Figure 8. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Startup in regulator OFF: slow VDD slope
power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 10. Startup in regulator OFF mode: fast VDD slope
power-down reset risen before VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. STM32F423xH WLCSP81 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 12. STM32F423xH UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 13. STM32F423xH LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 14. STM32F423xH LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 15. STM32F423xH LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 16. STM32F423xH UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 17. STM32F423xH UFBGA144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 18. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 19. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 20. Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 21. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 23. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 24. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator
“low power” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
“high drive” mode selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 26. Low-power mode wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 27. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 28. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 29. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 30. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 31. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 32. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 33. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 34. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 35. FT/TC I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 36. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 37. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 38. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 39. FMPI2C timing diagram and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 40. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 41. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 43. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 44. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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List of figures STM32F423xH
Figure 45. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 46. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 47. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 144
Figure 48. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 49. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 150
Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 151
Figure 52. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 160
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 162
Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 57. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 58. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 60. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 61. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 62. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 63. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 64. WLCSP81- 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 65. WLCSP81 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 66. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 67. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 68. UFQFPN48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 69. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 183
Figure 70. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 71. LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 72. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 187
Figure 73. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 74. LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 75. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 190
Figure 76. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 77. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 78. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 80. UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
grid array recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 83. UFBGA144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 84. Sensor Hub application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 85. Display application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 86. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . 205
Figure 87. USB peripheral-only Full speed mode with direct connection
10/209 DocID029161 Rev 7

STM32F423xH List of figures
for VBUS sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 88. USB peripheral-only Full speed mode, VBUS detection using GPIO . . . . . . . . . . . . . . . . 206
Figure 89. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 206
DocID029161 Rev 7 11/209

11
Introduction STM32F423xH
1 Introduction
This datasheet provides the description of the STM32F423xH microcontrollers.

For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming
manual (PM0214) available from www.st.com.
12/209 DocID029161 Rev 7

STM32F423xH Description
2 Description
The STM32F423XH devices are based on the high-performance Arm® Cortex®-M4 32-bit
RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a
Floating point unit (FPU) single precision which supports all Arm single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F423XH devices belong to the STM32F423xH access product lines (with
products combining power efficiency, performance and integration) while adding a new
innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power
consumption during data batching.
The STM32F423XH devices incorporate high-speed embedded memories (1.5 Mbytes of
Flash memory, 320 Kbytes of SRAM), and an extensive range of enhanced I/Os and
peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus
matrix.
All devices offer a 12-bit ADC, two 12-bit DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timer for motor control, two general-purpose 32-bit timers
and a low power timer.
They also feature standard and advanced communication interfaces.
• Up to four I2Cs, including one I2C supporting Fast-Mode Plus
• Five SPIs
• Five I2Ss out of which two are full duplex. To achieve audio class accuracy, the I2S
peripherals can be clocked via a dedicate internal audio PLL or via an external clock to
allow synchronization.
• Four USARTs and six UARTs
• An SDIO/MMC interface
• An USB 2.0 OTG full-speed interface
• Three CANs
• An SAI.
In addition, the STM32F423xH devices embed advanced peripherals:
• A flexible static memory control interface (FSMC)
• A Quad-SPI memory interface
• Two digital filter for sigma modulator (DFSDM) supporting microphone MEMs and
sound source localization, one with two filters and up to four inputs, and the second
one with four filters and up to eight inputs
The STM32F423xH devices embed an AES hardware accelerator.
They are offered in 7 packages ranging from 48 to 144 pins. The set of available peripherals
depends on the selected package. The STM32F423xH operate in the – 40 to + 125 °C
temperature range from a 1.7 (PDR OFF) to 3.6 V power supply. A comprehensive set of
power-saving mode allows the design of low-power applications.
DocID029161 Rev 7 13/209

43
Description STM32F423xH
These features make the STM32F423xH microcontrollers suitable for a wide range of
applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
• Mobile phone sensor hub
• Wearable devices
• Connected objects
• Wifi modules
14/209 DocID029161 Rev 7

Table 2. STM32F423xH features and peripheral counts

Peripherals STM32F423xH
Flash memory (Kbyte) 1536

SRAM (Kbyte) System 320 (256 + 64)
FSMC memory controller - 1(1) 1(1) 1(1) 1
FSMC LCD parallel interface - 8 16
Data bus size
Quad-SPI memory interface - 1
General-purpose 10(2) 10 10 (3)
10
Advanced-control 2(4) 2
Timers
Basic 2
Low-power timer 1
Random number generator 1
AES 1
SPI/ I2S 5/5 (2 full duplex)
I2C 3
I2CFMP 1
USART/UART 3/3 4/3 4/6
Comm. interfaces SDIO/MMC 1
USB/OTG FS 1 1 1 1
Dual power rail No Yes No Yes
CAN 3
SAI 1
Number of digital Filtersfor Sigma- 6
delta modulator
Number of channels 7 11 12
GPIOs 36 50 60 81 114
12-bit ADC 1
Number of channels 10 16
12-bit DAC Yes
Number of channels 2
Maximum CPU frequency 100 MHz
Operating voltage 1.7 to 3.6 V
Ambient temperatures: – 40 to + 85 °C/– 40 to + 105 °C / – 40 to + 125 °C
Operating temperatures
Junction temperature: – 40 to + 130 °C
UFBGA100 UFBGA144
Package UFQFPN48 LQFP64 WLCSP81 LQFP100 LQFP144
1. 64 pins packages support only 8 bits multiplexed mode interface
81 pins packages support 1 external memory of up to 64KB in multiplexed mode
100 pins packages support 2 external memories of up to 64MB in multiplexed mode
Refer to Table 11: FSMC pin definition for more detailed information.
2. 48 pins packages: TIM3 and TIM4: ETR pin not available.
DocID029161 Rev 7 15/209

43
3. 81 pins packages: TIM4: ETR pin not available.

4. 48 pins packages: TIM8:CH1, CH2, CH3 and CH4 pins not available.
2.1 Compatibility with STM32F4 series

The STM32F423xH are fully software and feature compatible with the STM32F4 series
(STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407)
The STM32F423xH can be used as drop-in replacement of the other STM32F4 products but
some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package

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DocID029161 Rev 7 17/209

43
Figure 4. STM32F423xH block diagram
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1. The timers connected to APB2 are clocked from TIMxCLK up to 100 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 50 MHz.
18/209 DocID029161 Rev 7

STM32F423xH Functional overview
3 Functional overview
3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and
SRAM
The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an Arm core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F423xH devices are compatible with all Arm tools and software.
Figure 4 shows the general block diagram of the STM32F423xH.
Note: Cortex®-M4 with FPU is binary compatible with Cortex®-M3.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard Arm® Cortex®-M4 with FPU processors. It balances the inherent performance
advantage of the Arm® Cortex®-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 125 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART Accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 100 MHz.
3.3 Enhanced Batch Acquisition mode (eBAM)

The Batch acquisition mode allows enhanced power efficiency during data batching. It
enables data acquisition through any communication peripherals directly to memory using
the DMA in reduced power consumption as well as data processing while the rest of the
system is in low-power mode (including the Flash and ART). For example in an audio
system, a smart combination of PDM audio sample acquisition and processing from the
DFSDM directly to RAM (Flash and ART™ stopped) with the DMA using BAM followed by
some very short processing from Flash allows to drastically reduce the power consumption
of the application.
The BAM has been enhanced by adding SRAM2 that allows SRAM code to be executed
through the Ibus and Dbus, thus improving code execution performance.
DocID029161 Rev 7 19/209

43
Functional overview STM32F423xH
A dedicated application note (AN4515) describes how to implement the STM32F423xH

BAM to allow the best power efficiency.
3.4 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 byte and the whole 4 Gbyte of
addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.5 Embedded Flash memory

The devices embed 1.5 Mbytes of Flash memory available for storing programs and data,
plus 512 bytes of one-time programmable (OTP) memory organized in 16 blocks of
32 bytes, each which can be independently locked.
The user Flash memory area can be protected against read operations by an entrusted
code (read protection or RDP). Different protection levels are available. The user Flash
memory is divided into sectors, which can be individually protected against write operation.
Flash sectors can also be protected individually against D-bus read accesses by using the
proprietary readout protection (PCROP).
Refer to the product line reference manual for additional information on OTP area and
protection features.
To optimize the power consumption the Flash memory can also be switched off in Run or in
Sleep mode (see Section 3.20: Low-power modes).
Two modes are available: Flash in Stop mode or in DeepSleep mode (trade off between
power saving and startup time.
Before disabling the Flash, the code must be executed from the internal RAM.
3.6 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
20/209 DocID029161 Rev 7

3.7 Embedded SRAM

All devices embed 320 Kbytes of system SRAM which can be accessed (read/write) at CPU
clock speed with 0 wait states.
3.8 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
Figure 5. Multi-AHB matrix
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CPU can access SRAM1 memory via S-bus, when SRAM1 is mapped at the address range:
0x2000 0000 to 0x2003 FFFF.
CPU can access SRAM2 memory via S-bus, when SRAM2 is mapped at the address range:
0x2004 0000 to 0x2004 FFFF.
CPU can access SRAM1 memory via I-bus and D-bus, when SRAM1 is remapped at
address 0x0000 0000 either by booting from RAM memory or by the remap mode.
CPU can access SRAM2 memory via I-bus and D-bus, when SRAM2 is mapped at the
address range: 0x1000 0000 to 0x1000 FFFF.
Performance boosts up, when the CPU access SRAM memory via the I-bus.
DocID029161 Rev 7 21/209

43
3.9 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
• SPI and I2S
• I2C and I2CFMP
• USART
• General-purpose, basic and advanced-control timers TIMx
• SD/SDIO/MMC/eMMC host interface
• Quad-SPI
• ADC
• DAC
• Digital Filter for sigma-delta modulator (DFSDM) with a separate stream for each filter
• SAI.
3.10 Flexible static memory controller (FSMC)

The Flexible static memory controller (FSMC) includes a NOR/PSRAM memory controller. It
features four Chip Select outputs supporting the following modes: SRAM, PSRAM and NOR
Flash memory.
The main functions are:
• 8-,16-bit data bus width
• Write FIFO
• Maximum FSMC_CLK frequency for synchronous accesses is 90 MHz.
LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
22/209 DocID029161 Rev 7

3.11 Quad-SPI memory interface (QUAD-SPI)

All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting single, dual or quad-SPI Flash memories. It can work in direct mode
through registers, external Flash status register polling mode and memory mapped mode.
Up to 256 Mbyte of external Flash memory are mapped. They can be accessed in 8, 16 or
32-bit mode. Code execution is also supported. The opcode and the frame format are fully
programmable. Communication can be performed either in single data rate or dual data
rate.
3.12 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 102 maskable interrupt channels plus the 16 interrupt lines of the
Cortex®-M4 with FPU.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 24 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 114 GPIOs can be connected
to the 16 external interrupt lines.
3.14 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The
application can then select as system clock either the RC oscillator or an external 4-26 MHz
clock source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 100 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the three AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB
DocID029161 Rev 7 23/209

43
buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the
low-speed APB domain is 50 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
3.15 Boot modes

At startup, boot pins are used to select one out of three boot options:
• Boot from user Flash memory
• Boot from system memory
• Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using one of the interface listed in the Table 3 or the USB OTG FS in device mode through
DFU (device firmware upgrade).
Table 3. Embedded bootloader interfaces

SPI1 SPI3 SPI4
I2C
USART1 USART2 USART3 I2C1 I2C2 I2C3 PA4/ PA15/ PE11/ CAN2 USB
FMP1
Package PA9/ PD6/ PB11/ PB6/ PF0/ PA8/ PA5/ PC10/ PE12/ PB5/ PA11
PB14/
PA10 PD5 PB10 PB7 PF1 PB4 PA6/ PC11/ PE13/ PB13 /P12
PB15
PA7 PC12 PE14
UFQFPN48 Y - - Y - Y Y Y - - Y Y
LQFP64 Y - - Y - Y Y Y Y - Y Y
WLCSP81 Y - - Y - Y Y Y Y Y Y Y
LQFP100 Y Y - Y - Y Y Y Y Y Y Y
LQFP144 Y Y Y Y Y Y Y Y Y Y Y Y
UFBGA100 Y Y Y Y - Y Y Y Y Y Y Y
UFBGA144 Y Y Y Y Y Y Y Y Y Y Y Y
For more detailed information on the bootloader, refer to Application Note: AN2606,
STM32™ microcontroller system memory boot mode.
24/209 DocID029161 Rev 7

3.16 Power supply schemes

• VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
(POR/PDR) disabled, provided externally through VDD pins. Requires the use of an
external power supply supervisor connected to the VDD and NRST pins.
• VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with
decoupling technique.
Note: The VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply
supervisor (refer to Section 3.17.2: Internal reset OFF). Refer to Table 4: Regulator ON/OFF
and internal power supply supervisor availability to identify the packages supporting this
option.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
• VDDUSB can be connected either to VDD or an external independent power supply (3.0
to 3.6 V) for USB transceivers.
For example, when device is powered at 1.8 V, an independent power supply 3.3V can
be connected to VDDUSB. When the VDDUSB is connected to a separated power supply,
it is independent from VDD or VDDA but it must be the last supply to be provided and the
first to disappear.
The following conditions VDDUSB must be respected:
– During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
– During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than
VDD
– VDDUSB rising and falling time rate specifications must be respected.
– In operating mode phase, VDDUSB could be lower or higher than VDD:
– If USB is used, the associated GPIOs powered by VDDUSB are operating
between VDDUSB_MIN and VDDUSB_MAX.
– If USB is not used, the associated GPIOs powered by VDDUSB are operating
between VDD_MIN and VDD_MAX.
DocID029161 Rev 7 25/209

43
Figure 6. VDDUSB connected to an external independent power supply
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3.17 Power supply supervisor
3.17.1 Internal reset ON

This feature is available for VDD operating voltage range 1.8 V to 3.6 V.
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other package, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes.
The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or
VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
26/209 DocID029161 Rev 7

3.17.2 Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to
low.
An external power supply supervisor should monitor VDD and should set the device in reset
mode when VDD is below 1.7 V. NRST should be connected to this external power supply
supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset
OFF.
Figure 7. Power supply supervisor interconnection with internal reset OFF(1)
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A comprehensive set of power-saving mode allows to design low-power applications.

When the internal reset is OFF, the following integrated features are no longer supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
• The brownout reset (BOR) circuitry must be disabled.
• The embedded programmable voltage detector (PVD) is disabled.
• VBAT functionality is no more available and VBAT pin should be connected to VDD.
3.18 Voltage regulator

The regulator has three operating modes:
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
DocID029161 Rev 7 27/209

43
3.18.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
• MR is used in the nominal regulation mode (With different voltage scaling in Run mode)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
• LPR is used in the Stop mode
The LP regulator mode is configured by software when entering Stop mode.
• Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available on 100- and 144-pin
packages.
All packages have the regulator ON feature.
3.18.2 Regulator OFF

This feature is available only on UFBGA100 and UFBGA144 packages, which feature the
BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator
OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2
pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
28/209 DocID029161 Rev 7

Figure 8. Regulator OFF

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The following conditions must be respected:

• VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
• If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 9).
• Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 10).
• If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application.
DocID029161 Rev 7 29/209

43
Figure 9. Startup in regulator OFF: slow VDD slope

power-down reset risen after VCAP_1/VCAP_2 stabilization
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1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 10. Startup in regulator OFF mode: fast VDD slope

power-down reset risen before VCAP_1/VCAP_2 stabilization
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1. This figure is valid whatever the internal reset mode (ON or OFF).
30/209 DocID029161 Rev 7

3.18.3 Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal power supply supervisor availability

Power supply Power supply
Package Regulator ON Regulator OFF
supervisor ON supervisor OFF
UFQFPN48 Yes No Yes No

LQFP64 Yes No Yes No
Yes Yes Yes Yes
WLCSP81 BYPASS_REG BYPASS_REG PDR_ON PDR_ON
set to VSS set to VDD set to VDD set to VSS
LQFP100 Yes No Yes No
LQFP144 Yes No
Yes Yes
UFBGA100 BYPASS_REG BYPASS_REG Yes Yes
set to VSS set to VDD PDR_ON PDR_ON
set to VDD set to VSS
Yes Yes
UFBGA144 BYPASS_REG BYPASS_REG
set to VSS set to VDD
3.19 Real-time clock (RTC) and backup registers

The backup domain includes:
• The real-time clock (RTC)
• 20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC features a reference clock detection, a more precise
second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC
provides a programmable alarm and programmable periodic interrupts with wakeup from
Stop and Standby modes. The sub-seconds value is also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The backup registers are 32-bit registers used to store 80 byte of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 3.20: Low-power
modes).
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Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
The RTC and backup registers are supplied through a switch that is powered either from the
VDD supply when present or from the VBAT pin.
3.20 Low-power modes

The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
To further reduce the power consumption, the Flash memory can be switched off
before entering in Sleep mode. Note that this requires a code execution from the RAM.
• Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/
tamper/ time stamp events).
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on one of the WKUP pins, or an RTC alarm/ wakeup/ tamper/time stamp
event occurs.
Standby mode is not supported when the embedded voltage regulator is bypassed and
the 1.2 V domain is controlled by an external power.
3.21 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external
super-capacitor, or from VDD when no external battery and an external super-capacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC and the backup registers.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal
Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected
to VDD.
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3.22 Timers and watchdogs

The devices embed two advanced-control timer, ten general-purpose timers, two basic
timers, one low-power timer, two watchdog timers and a SysTick timer.
All timer counters can be frozen in debug mode.
Table 5 compares the features of the advanced-control and general-purpose timers.
Table 5. Timer feature comparison

Max. Max.
DMA Capture/
Timer Counter Counter Prescaler Complemen- interface timer
Timer request compare
type resolution type factor tary output clock clock
generation channels
(MHz) (MHz)
Any
Up, integer
Advance TIM1,
16-bit Down, between 1 Yes 4 Yes 100 100
d-control TIM8
Up/down and
65536
Any
Up, integer
TIM2,
32-bit Down, between 1 Yes 4 No 50 100
TIM5
Up/down and
65536
Any
Up, integer
TIM3,
16-bit Down, between 1 Yes 4 No 50 100
TIM4
Up/down and
65536
Any
integer
TIM9 16-bit Up between 1 No 2 No 100 100
and
General 65536
purpose Any
integer
TIM10,
16-bit Up between 1 No 1 No 100 100
TIM11
and
65536
Any
integer
TIM12 16-bit Up between 1 No 2 No 50 100
and
65536
Any
integer
TIM13,
16-bit Up between 1 No 1 No 50 100
TIM14
and
65536
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Table 5. Timer feature comparison (continued)

Max. Max.
DMA Capture/
Timer Counter Counter Prescaler Complemen- interface timer
Timer request compare
type resolution type factor tary output clock clock
generation channels
(MHz) (MHz)
Any
integer
Basic TIM6,
16-bit Up between 1 Yes 0 No 50 100
timers TIM7
and
65536
Low-
Between
power LPTIM1 16-bit Up No 2 No 50 100
1 and 128
timer
3.22.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1/8) can be seen as three-phase PWM generator
multiplexed on 4 independent channels. They have complementary PWM outputs with
programmable inserted dead times. They can also be considered as complete general-
purpose timers. Their 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge- or center-aligned modes)
• One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as a 16-bit PWM generator, they have full modulation capability
(0-100%).
The advanced-control timers can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.22.2 General-purpose timers (TIMx)

There are elven synchronizable general-purpose timers embedded in the STM32F423xH
(see Table 5 for differences).
• TIM2, TIM3, TIM4, TIM5
The STM32F423xH devices include 4 full-featured general-purpose timers: TIM2.
TIM3, TIM4 and TIM5. TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler while TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter plus a 16-bit prescaler. They all features four
34/209 DocID029161 Rev 7

independent channels for input capture/output compare, PWM or one-pulse mode

output. This gives up to 15 input capture/output compare/PWMs
TIM2. TIM3, TIM4 and TIM5 general-purpose timers can operate together or in
conjunction with the other general-purpose timers and TIM1 advanced-control timer via
the Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM output.
TIM2. TIM3, TIM4 and TIM5 channels have independent DMA request generation.
They are capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 4 hall-effect sensors.
• TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13 and TIM14 feature one independent channel, whereas TIM9 and
TIM12 have two independent channels for input capture/output compare, PWM or one-
pulse mode output. They can be synchronized with TIM2. TIM3, TIM4 and TIM5 full-
featured general-purpose timers or used as simple time bases.
3.22.3 Basic timer (TIM6, TIM7)

TIM6 and TIM7 timers are basic 16-bit timers. They support independent DMA request
generation.
3.22.4 Low-power timer (LPTIM1)

The low-power timer (LPTIM1) features an independent clock and runs in Stop mode if it is
clocked by LSE, LSI or by an external clock. LPTIM1 is able to wakeup the devices from
Stop mode.
The low-power timer main features are the following:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous / one shot mode
• Selectable software / hardware input trigger
• Selectable clock source
– Internal clock source: LSE, LSI, HSI or APB1 clock
– External clock source over LPTIM1 input (working even with no internal clock
source running, used by the pulse counter application)
• Programmable digital glitch filter
• Encoder mode
• Active in Stop mode.
3.22.5 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
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43
3.22.6 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.22.7 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
• A 24-bit downcounter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source.
3.23 Inter-integrated circuit interface (I2C)

The devices feature up to four I2C bus interfaces which can operate in multimaster and
slave modes:
• One I2C interface supports the Standard mode (up to 100 kHz), Fast-mode (up to
400 kHz) modes and Fast-mode plus (up to 1 MHz).
• Three I2C interfaces support the Standard mode (up to 100 KHz) and the Fast mode
(up to 400 KHz). Their frequency can be increased up to 1 MHz. For more details on
the complete solution, refer to the nearest STMicroelectronics sales office.
All I2C interfaces features 7/10-bit addressing mode and 7-bit addressing mode (as slave)
and embed a hardware CRC generation/verification.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 6).
Table 6. Comparison of I2C analog and digital filters

Analog filter Digital filter
Pulse width of
≥ 50 ns Programmable length from 1 to 15 I2C peripheral clocks
suppressed spikes
3.24 Universal synchronous/asynchronous receiver transmitters

(USART)
The devices embed four universal synchronous/asynchronous receiver transmitters
(USART1, USART2, USART3 and USART6) as well as six universal asynchronous receiver
transmitters (UART4, UART5, UART7, UART8, UART9 and UART10).
These ten interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. USART1, USART6, UART9 and UART10 can
communicate at speeds up to 12.5 Mbit/s. The other interfaces communicate at up to
6.25 bit/s.
36/209 DocID029161 Rev 7

USART1, USART2, USART3 and USART6 provide hardware management of the CTS and
RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
Table 7. USART feature comparison

Max. baud Max. baud
USART Standard Modem SPI Smartcard rate in Mbit/s rate in Mbit/s APB
LIN irDA
name features (RTS/CTS) master (ISO 7816) (oversampling (oversampling mapping
by 16) by 8)
APB2
USART1 X X X X X X 6.25 12.5 (max.
100 MHz)
APB1
50 MHz)
APB1
50 MHz)
APB1
UART4 X - X - X - 3.12 6.25 (max.
50 MHz)
APB1
UART5 X - X - X - 3.12 6.25 (max.
50 MHz)
APB2
100 MHz)
APB1
UART7 X - X - X - 3.12 6.25 (max.
50 MHz)
APB1
UART8 X - X - X - 3.12 6.25 (max.
50 MHz)
APB2
UART9 X - X - X - 6.25 12.5 (max.
100 MHz)
APB2
UART10 X - X - X - 6.25 12.5 (max.
100 MHz)
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43
3.25 Serial peripheral interface (SPI)

The devices feature five SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and
SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interfaces can be configured to operate in TI mode for communications in master
mode and slave mode.
3.26 Inter-integrated sound (I2S)

Five standard I2S interfaces (multiplexed with SPI1 to SPI5) are available. They can be
operated in master or slave mode, in simplex communication mode, and full duplex mode
for I2S2 and I2S3. All I2S interfaces can be configured to operate with a 16-/32-bit resolution
as an input or output channel. I2Sx audio sampling frequencies from 8 kHz up to 192 kHz
are supported. When either or both of the I2S interfaces is/are configured in master mode,
the master clock can be output to the external DAC/CODEC at 256 times the sampling
frequency.
All I2Sx interfaces can be served by the DMA controller.
3.27 Serial Audio interface (SAI1)

The serial audio interface (SAI1) is based on two independent audio sub-blocks which can
operate as transmitter or receiver with their FIFO. Many audio protocols are supported by
each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both sub-blocks
can be configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
SAI1 can be served by the DMA controller.
3.28 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
Different sources can be selected for the I2S master clock of the APB1 and the I2S master
clock of the APB2. This gives the flexibility to work with two different audio sampling
frequencies. The different possible sources are the main PLL, the PLLI2S, HSE or HSI
clocks or an external clock provided through a pin (external PLL or CODEC output)
38/209 DocID029161 Rev 7

Different sources can also be selected for the SAI. The different possible sources are the
main PLL, the PLLI2S, HSE or HSI clocks or an external clock provided through a pin
(external PLL or CODEC output).
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
3.29 Digital filter for sigma-delta modulators (DFSDM)

The device embeds two DFSDMs:
• DFSDM1 has 2 digital filters modules and 4 external input serial channels
(transceivers) or alternately 2 internal parallel inputs support.
• DFSDM2 features 4 digital filters modules and 8 external input serial channels
(transceivers) or alternately 4 internal parallel inputs support.
The amount of filters defines the number of conversions which can be performed
simultaneously.
The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on Σ∆ modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. It is also possible to introduce a programmable delay between different
microphones (beamforming feature). DFSDM features optional parallel data stream inputs
from microcontrollers memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various Σ∆
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
Table 8. DFSDM feature comparison

External input serial External input parallel
DFSDM instance Digital filters
channels channels
DFSDM1 4 2 2
DFSDM2 8 4 4
3.30 Dynamic tuning of PDM delays for sound source localization

A mechanism is implemented on top of the DFSDM allowing to dynamically tune PDM
delays of each microphone without the need to add external delay lines.
Audio application with several microphones require strong microphones placement
constraints, as the distance between the microphones must be a multiple of v/F where v is
the speed of the sound and F is the PCM sampling frequency.
The designed mechanism removes this constraint by programming delays for each digital
microphone with the granularity of the PDM clock rate prior to the conversion into PCM rate.
The tuning delay is performed by a clock skipping technique.
DocID029161 Rev 7 39/209

43
The strong benefits of such mechanism coupled with DFSDM are:

• Possibility to place the digital microphones close to each other
• No need for external delay lines
• The delay tuning is done in hardware, preventing the use of MIPs crunching algorithms
• Possibility to change the delay tuning on the fly
• The low power consumption and CPU time released due to the DFSDM hardware PDM
to PCM conversion
The impacted audio application are beam forming and sound source localization
3.31 Secure digital input/output interface (SDIO)

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC/eMMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.32 Controller area network (bxCAN)

The three CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for CAN1 and CAN2, and 512 bytes for
CAN3.
3.33 Universal serial bus on-the-go full-speed (USB_OTG_FS)

The devices embed a USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with USB 2.0 and OTG 1.0
specifications. It features software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock,
which is generated by a PLL connected to the HSE oscillator. The Battery Charging
Detection (BCD) can detect and identify the type of port it is connected to (standard USB or
charger). The charging type can also be detected: Dedicated Charging Port (DCP),
Charging Downstream Port (CDP) and Standard Downstream Port (SDP).
Some packages provide a dedicated USB power rail allowing to supply the USB from a
different voltage that the rest of the device. As an example, the device can be powered with
the minimum specified supply voltage while the USB runs at the level defined by the
standard.
40/209 DocID029161 Rev 7

The main USB OTG FS features are:

• Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
• Support of session request protocol (SRP) and host negotiation protocol (HNP)
• 6 bidirectional endpoints
• 12 host channels with periodic OUT support
• HNP/SNP/IP inside (no need for any external resistor)
• For OTG/Host modes, a power switch is needed when bus-powered devices are
connected
• Link Power Management (LPM)
• Battery Charging Detection (BCD) supporting DCP, CDP and SDP
3.34 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.35 Advanced encryption standard hardware accelerator (AES)

The devices embed an AES hardware accelerator can be used to both encipher and
decipher data using AES algorithm.
The AES peripheral supports:
• Encryption/Decryption using AES Rijndael Block Cipher algorithm
• NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm
• 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x
32-bit registers)
• Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois
Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher
Message Authentication Code mode (CMAC) supported.
• Key scheduler
• Key derivation for decryption
• 128-bit data block processing
• 128-bit, 256-bit key length
• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.
• Register access supporting 32-bit data width only.
• One 128-bit Register for the initialization vector when AES is configured in CBC mode
or for the 32-bit counter initialization when CTR mode is selected, GCM mode or
CMAC mode.
• Automatic data flow control with support of direct memory access (DMA) using 2
channels, one for incoming data, and one for outcoming data.
• Suspend a message if another message with a higher priority needs to be processed.
DocID029161 Rev 7 41/209

43
3.36 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 100 MHz.
3.37 Analog-to-digital converter (ADC)

One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4 or TIM5 timer.
3.38 Digital to analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This digital interface supports the following features:
• Two DAC output channels
• 8-bit or 12-bit output mode
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
• Input voltage reference (VREF+)
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA channels.
42/209 DocID029161 Rev 7

3.39 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the ADC_IN18 input channel which is used to convert the sensor output
voltage into a digital value. Refer to the reference manual for additional information.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.40 Serial wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.41 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F423xH through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using any high-speed
channel available. Real-time instruction and data flow activity can be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DocID029161 Rev 7 43/209

43
Pinouts and pin description STM32F423xH
4 Pinouts and pin description
4.1 WLCSP81 pinout description

Figure 11. STM32F423xH WLCSP81 pinout

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44/209 DocID029161 Rev 7

STM32F423xH Pinouts and pin description
4.2 UFQFPN48 pinout description

Figure 12. STM32F423xH UFQFPN48 pinout
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DocID029161 Rev 7 45/209

74
4.3 LQFP64 pinout description

Figure 13. STM32F423xH LQFP64 pinout
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46/209 DocID029161 Rev 7


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DocID029161 Rev 7 47/209

74

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48/209 DocID029161 Rev 7

4.6 UFBGA100 pinout description

Figure 16. STM32F423xH UFBGA100 pinout

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DocID029161 Rev 7 49/209

74
4.7 UFBGA144 pinout description

Figure 17. STM32F423xH UFBGA144 pinout

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4.8 Pins definition

Table 9. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/ output pin
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, I2C FM+ option
TC Standard 3.3 V I/O
I/O structure
TTa 3.3 V tolerant I/O directly connected to DAC
B Dedicated BOOT0 pin
NRST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
50/209 DocID029161 Rev 7

Table 9. Legend/abbreviations used in the pinout table (continued)

Name Abbreviation Definition
Alternate functions Functions selected through GPIOx_AFR registers

Additional functions Functions directly selected/enabled through peripheral registers
Table 10. STM32F423xH pin definition

Pin Number
Pin name
UFBGA100
UFBGA144
UFQFPN48
(function Pin I/O Additional

WLCSP81
LQFP100
LQFP144
LQFP64
Notes Alternate functions

after type structure functions
reset)(1)
TRACECLK,
SPI4_SCK/I2S4_CK,
SPI5_SCK/I2S5_CK,
(2) SAI1_MCLK_A,
- - NC 1 B2 A3 1 PE2 I/O FT -
QUADSPI_BK1_IO2,
UART10_RX,
FSMC_A23,
EVENTOUT
TRACED0, SAI1_SD_B,
(2) UART10_TX,
- - NC 2 A1 A2 2 PE3 I/O FT -
FSMC_A19,
EVENTOUT
TRACED1,
SPI4_NSS/I2S4_WS,
SPI5_NSS/I2S5_WS,
- - NC 3 B1 B2 3 PE4 I/O FT (2)(3) SAI1_SD_A, -
DFSDM1_DATIN3,
FSMC_A20,
EVENTOUT
TRACED2, TIM9_CH1,
SPI4_MISO,
SPI5_MISO,
(2)
- - NC 4 C2 B3 4 PE5 I/O FT SAI1_SCK_A, -
DFSDM1_CKIN3,
FSMC_A21,
EVENTOUT
TRACED3, TIM9_CH2,
SPI4_MOSI/I2S4_SD,
(2)(3) SPI5_MOSI/I2S5_SD,
- - NC 5 D2 B4 5 PE6 I/O FT -
SAI1_FS_A,
FSMC_A22,
EVENTOUT
1 1 B9 6 E2 C2 6 VBAT S - - - VBAT
PC13- (4)(5)
2 2 C8 7 C1 A1 7 I/O FT EVENTOUT TAMP_1
ANTI_TAMP
PC14- (4)(5)(6)
3 3 C9 8 D1 B1 8 I/O FT EVENTOUT OSC32_IN
OSC32_IN
DocID029161 Rev 7 51/209

74
Table 10. STM32F423xH pin definition (continued)

Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
PC15- (4)(6)
4 4 D9 9 E1 C1 9 I/O FT EVENTOUT OSC32_OUT
OSC32_OUT
I2C2_SDA, FSMC_A0,
- - - - - C3 10 PF0 I/O FT - -
EVENTOUT
I2C2_SCL, FSMC_A1,
- - - - - C4 11 PF1 I/O FT - -
EVENTOUT
I2C2_SMBA, FSMC_A2,
- - - - - D4 12 PF2 I/O FT - -
EVENTOUT
TIM5_CH1, FSMC_A3,
- - - - - E2 13 PF3 I/O FT - -
EVENTOUT
TIM5_CH2, FSMC_A4,
- - - - - E3 14 PF4 I/O FT - -
EVENTOUT
TIM5_CH3, FSMC_A5,
- - - - - E4 15 PF5 I/O FT - -
EVENTOUT
- - D8 10 F2 D2 16 VSS S - - - -
- - E8 11 G2 D3 17 VDD S - - - -
TRACED0, TIM10_CH1,
SAI1_SD_B,
- - - - - F3 18 PF6 I/O FT - UART7_Rx, -
QUADSPI_BK1_IO3,
EVENTOUT
TRACED1, TIM11_CH1,
SAI1_MCLK_B,
- - - - - F2 19 PF7 I/O FT - UART7_Tx, -
QUADSPI_BK1_IO2,
EVENTOUT
SAI1_SCK_B,
UART8_RX,
- - - - - G3 20 PF8 I/O FT - TIM13_CH1, -
QUADSPI_BK1_IO0,
EVENTOUT
SAI1_FS_B,
UART8_TX,
- - - - - G2 21 PF9 I/O FT - TIM14_CH1, -
QUADSPI_BK1_IO1,
EVENTOUT
TIM1_ETR, TIM5_CH4,
- - - - - G1 22 PF10 I/O FT - -
EVENTOUT
(6)
5 5 E9 12 F1 D1 23 PH0 - OSC_IN I/O FT EVENTOUT OSC_IN
PH1 - (6)
6 6 F9 13 G1 E1 24 I/O FT EVENTOUT OSC_OUT
OSC_OUT
52/209 DocID029161 Rev 7


Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
7 7 G9 14 H2 F1 25 NRST I/O RST - - NRST
LPTIM1_IN1,
DFSDM2_CKIN4, ADC1_IN10,
- 8 F8 15 H1 H1 26 PC0 I/O FT -
SAI1_MCLK_B, WKUP2
EVENTOUT
LPTIM1_OUT,
DFSDM2_DATIN4, ADC1_IN11,
- 9 C7 16 J2 H2 27 PC1 I/O FT -
SAI1_SD_B, WKUP3
EVENTOUT
LPTIM1_IN2,
DFSDM2_DATIN7,
SPI2_MISO,
I2S2ext_SD,
- 10 D7 17 J3 H3 28 PC2 I/O FT - ADC1_IN12
SAI1_SCK_B,
DFSDM1_CKOUT,
FSMC_NWE,
EVENTOUT
LPTIM1_ETR,
DFSDM2_CKIN7,
- 11 E7 18 K2 H4 29 PC3 I/O FT - SPI2_MOSI/I2S2_SD, ADC1_IN13
SAI1_FS_B, FSMC_A0,
EVENTOUT
- - - 19 - - 30 VDD S - - - -
8 12 H9 20 J1 J1 31 VSSA S - - - -
- - - - K1 K1 - VREF- S - - - -
- - G8 21 L1 L1 32 VREF+ S - - - -
9 13 F7 22 M1 M1 33 VDDA S - - - -
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR, ADC1_IN0,
10 14 G7 23 L2 J2 34 PA0 I/O FT -
USART2_CTS, WKUP1
UART4_TX, EVENTOUT
TIM2_CH2, TIM5_CH2,
SPI4_MOSI/I2S4_SD,
USART2_RTS,
11 15 H8 24 M2 K2 35 PA1 I/O FT - ADC1_IN1
UART4_RX,
QUADSPI_BK1_IO3,
EVENTOUT
TIM2_CH3, TIM5_CH3,
TIM9_CH1, I2S2_CKIN,
12 16 J9 25 K3 L2 36 PA2 I/O FT - USART2_TX, ADC1_IN2
FSMC_D4/FSMC_DA4,
EVENTOUT
DocID029161 Rev 7 53/209

74

Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
TIM2_CH4, TIM5_CH4,
TIM9_CH2, I2S2_MCK,
USART2_RX,
13 17 E6 26 L3 M2 37 PA3 I/O FT - ADC1_IN3
SAI1_SD_B,
FSMC_D5/FSMC_DA5,
EVENTOUT
- 18 H7 27 - - 38 VSS S - - - -
BYPASS_
- - F6 - E3 H5 - I FT - - -
REG
- 19 J8 28 - F4 39 VDD S - - - -
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, ADC1_IN4,
14 20 E5 29 M3 J3 40 PA4 I/O TTa -
DFSDM1_DATIN1, DAC_OUT1
FSMC_D6/FSMC_DA6,
EVENTOUT
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK, ADC1_IN5,
15 21 G6 30 K4 K3 41 PA5 I/O TTa -
DFSDM1_CKIN1, DAC_OUT2
FSMC_D7/FSMC_DA7,
EVENTOUT
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO, I2S2_MCK,
DFSDM2_CKIN1,
16 22 F5 31 L4 L3 42 PA6 I/O FT - ADC1_IN6
TIM13_CH1,
QUADSPI_BK2_IO0,
SDIO_CMD,
EVENTOUT
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
17 23 J7 32 M4 M3 43 PA7 I/O FT - ADC1_IN7
DFSDM2_DATIN1,
TIM14_CH1,
QUADSPI_BK2_IO1,
EVENTOUT
DFSDM2_CKIN2,
I2S1_MCK,
- 24 H6 33 K5 J4 44 PC4 I/O FT - QUADSPI_BK2_IO2, ADC1_IN14
FSMC_NE4,
EVENTOUT
54/209 DocID029161 Rev 7


Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
DFSDM2_DATIN2,
I2CFMP1_SMBA,
USART3_RX,
- 25 J6 34 L5 K4 45 PC5 I/O FT - ADC1_IN15
QUADSPI_BK2_IO3,
FSMC_NOE,
EVENTOUT
TIM1_CH2N,
TIM3_CH3,
18 26 E4 35 M5 L4 46 PB0 I/O FT - TIM8_CH2N, ADC1_IN8
SPI5_SCK/I2S5_CK,
EVENTOUT
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
19 27 G5 36 M6 M4 47 PB1 I/O FT - SPI5_NSS/I2S5_WS, ADC1_IN9
DFSDM1_DATIN0,
QUADSPI_CLK,
EVENTOUT
LPTIM1_OUT,
DFSDM1_CKIN0,
20 28 H5 37 L6 J5 48 PB2 I/O FT - BOOT1
QUADSPI_CLK,
EVENTOUT
- - - - - M5 49 PF11 I/O FT - TIM8_ETR, EVENTOUT -
TIM8_BKIN, FSMC_A6,
- - - - - L5 50 PF12 I/O FT - -
EVENTOUT
- - - - - G4 51 VSS S - - - -
- - - - - G5 52 VDD S - - - -
I2CFMP1_SMBA,
- - - - - K5 53 PF13 I/O FT - -
FSMC_A7, EVENTOUT
I2CFMP1_SCL,
- - - - - M6 54 PF14 I/O FTf - -
FSMC_A8, EVENTOUT
I2CFMP1_SDA,
- - - - - L6 55 PF15 I/O FTf - -
FSMC_A9, EVENTOUT
CAN1_RX, UART9_RX,
- - - - - K6 56 PG0 I/O FT - FSMC_A10, -
EVENTOUT
CAN1_TX, UART9_TX,
- - - - - J6 57 PG1 I/O FT - -
FSMC_A11, EVENTOUT
DocID029161 Rev 7 55/209

74

Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
TIM1_ETR,
DFSDM1_DATIN2,
(2) UART7_Rx,
- - NC 38 M7 M7 58 PE7 I/O FT -
QUADSPI_BK2_IO0,
FSMC_D4/FSMC_DA4,
EVENTOUT
TIM1_CH1N,
DFSDM1_CKIN2,
(2) UART7_Tx,
- - NC 39 L7 L7 59 PE8 I/O FT -
QUADSPI_BK2_IO1,
FSMC_D5/FSMC_DA5,
EVENTOUT
TIM1_CH1,
DFSDM1_CKOUT,
- - J5 40 M8 K7 60 PE9 I/O FT - QUADSPI_BK2_IO2, -
FSMC_D6/FSMC_DA6,
EVENTOUT
- - - - - H6 61 VSS S - - - -
- - - - - G6 62 VDD S - - - -
TIM1_CH2N,
DFSDM2_DATIN0,
- - G4 41 L8 J7 63 PE10 I/O FT - QUADSPI_BK2_IO3, -
FSMC_D7/FSMC_DA7,
EVENTOUT
TIM1_CH2,
DFSDM2_CKIN0,
SPI4_NSS/I2S4_WS,
- - H4 42 M9 H8 64 PE11 I/O FT - -
SPI5_NSS/I2S5_WS,
FSMC_D8/FSMC_DA8,
EVENTOUT
TIM1_CH3N,
DFSDM2_DATIN7,
SPI4_SCK/I2S4_CK,
- - J4 43 L9 J8 65 PE12 I/O FT - -
SPI5_SCK/I2S5_CK,
FSMC_D9/FSMC_DA9,
EVENTOUT
TIM1_CH3,
DFSDM2_CKIN7,
SPI4_MISO,
- - F4 44 M10 K8 66 PE13 I/O FT - -
SPI5_MISO,
FSMC_D10/FSMC_DA1
0, EVENTOUT
56/209 DocID029161 Rev 7


Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
TIM1_CH4,
SPI4_MOSI/I2S4_SD,
SPI5_MOSI/I2S5_SD,
- - G3 45 M11 L8 67 PE14 I/O FT - -
DFSDM2_DATIN1,
FSMC_D11/FSMC_DA1
1, EVENTOUT
TIM1_BKIN,
DFSDM2_CKIN1,
- - J3 46 M12 M8 68 PE15 I/O FT - -
FSMC_D12/FSMC_DA1
2, EVENTOUT
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
I2S3_MCK,
21 29 H3 47 L10 M9 69 PB10 I/O FTf - USART3_TX, -
I2CFMP1_SCL,
DFSDM2_CKOUT,
SDIO_D7, EVENTOUT
TIM2_CH4, I2C2_SDA,
I2S2_CKIN,
- - NC - K9 M10 70 PB11 I/O FT - -
USART3_RX,
EVENTOUT
22 30 H2 48 L11 H7 71 VCAP_1 S - - - -
23 31 J2 49 F12 - - VSS S - - - -
24 32 J1 50 G12 G7 72 VDD S - - - -
TIM1_BKIN,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
SPI4_NSS/I2S4_WS,
SPI3_SCK/I2S3_CK,
25 33 F3 51 L12 M11 73 PB12 I/O FT - USART3_CK, -
CAN2_RX,
DFSDM1_DATIN1,
UART5_RX,
FSMC_D13/FSMC_DA1
3, EVENTOUT
TIM1_CH1N,
I2CFMP1_SMBA,
SPI2_SCK/I2S2_CK,
SPI4_SCK/I2S4_CK,
26 34 G2 52 K12 M12 74 PB13 I/O FT - -
USART3_CTS,
CAN2_TX,
DFSDM1_CKIN1,
UART5_TX, EVENTOUT
DocID029161 Rev 7 57/209

74

Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
TIM1_CH2N,
TIM8_CH2N,
I2CFMP1_SDA,
SPI2_MISO,
I2S2ext_SD,
27 35 E3 53 K11 L11 75 PB14 I/O FTf - -
USART3_RTS,
DFSDM1_DATIN2,
TIM12_CH1,
FSMC_D0/FSMC_DA0,
SDIO_D6, EVENTOUT
RTC_REFIN,
TIM1_CH3N,
TIM8_CH3N,
I2CFMP1_SCL,
28 36 H1 54 K10 L12 76 PB15 I/O FTf - -
SPI2_MOSI/I2S2_SD,
DFSDM1_CKIN2,
TIM12_CH2, SDIO_CK,
EVENTOUT
USART3_TX,
- - NC 55 - L9 77 PD8 I/O FT (2) FSMC_D13/FSMC_DA1 -
3, EVENTOUT
USART3_RX,
- - F2 56 K8 K9 78 PD9 I/O FT - FSMC_D14/FSMC_DA1 -
4, EVENTOUT
USART3_CK,
(7) UART4_TX,
- - G1 57 J12 J9 79 PD10 I/O FT -
FSMC_D15/FSMC_DA1
5, EVENTOUT
DFSDM2_DATIN2,
I2CFMP1_SMBA,
(2) USART3_CTS,
- - NC 58 J11 H9 80 PD11 I/O FT -
QUADSPI_BK1_IO0,
FSMC_A16,
EVENTOUT
TIM4_CH1,
DFSDM2_CKIN2,
I2CFMP1_SCL,
- - NC 59 J10 L10 81 PD12 I/O FTf (2) USART3_RTS, -
QUADSPI_BK1_IO1,
FSMC_A17,
EVENTOUT
TIM4_CH2,
I2CFMP1_SDA,
- - NC 60 H12 K10 82 PD13 I/O FTf (2) QUADSPI_BK1_IO3, -
FSMC_A18,
EVENTOUT
- - - - - G8 83 VSS S - - - -
58/209 DocID029161 Rev 7


Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
- - - - - F8 84 VDD S - - - -
TIM4_CH3,
I2CFMP1_SCL,
(2) DFSDM2_CKIN0,
- - NC 61 H11 K11 85 PD14 I/O FTf -
UART9_RX,
FSMC_D0/FSMC_DA0,
EVENTOUT
TIM4_CH4,
I2CFMP1_SDA,
(2) DFSDM2_DATIN0,
- - NC 62 H10 K12 86 PD15 I/O FTf -
UART9_TX,
FSMC_D1/FSMC_DA1,
EVENTOUT
FSMC_A12,
- - - - - J12 87 PG2 I/O FT - -
EVENTOUT
FSMC_A13,
- - - - - J11 88 PG3 I/O FT - -
EVENTOUT
FSMC_A14,
- - - - - J10 89 PG4 I/O FT - -
EVENTOUT
FSMC_A15,
- - - - - H12 90 PG5 I/O FT - -
EVENTOUT
QUADSPI_BK1_NCS,
- - - - - H11 91 PG6 I/O FT - -
EVENTOUT
USART6_CK,
- - - - - H10 92 PG7 I/O FT - -
EVENTOUT
USART6_RTS,
- - - - - G11 93 PG8 I/O FT - -
EVENTOUT
- - - - - - 94 VSS S - - - -
- - - - - F10 - VDD S - - - -
- - F1 - - C11 95 VDDUSB S - - - -
TIM3_CH1, TIM8_CH1,
I2CFMP1_SCL,
I2S2_MCK,
DFSDM1_CKIN3,
- 37 D5 63 E12 G12 96 PC6 I/O FTf - -
DFSDM2_DATIN6,
USART6_TX,
FSMC_D1/FSMC_DA1,
SDIO_D6, EVENTOUT
DocID029161 Rev 7 59/209

74

Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
TIM3_CH2, TIM8_CH2,
I2CFMP1_SDA,
SPI2_SCK/I2S2_CK,
I2S3_MCK,
- 38 D4 64 E11 F12 97 PC7 I/O FTf - -
DFSDM2_CKIN6,
USART6_RX,
DFSDM1_DATIN3,
SDIO_D7, EVENTOUT
TIM3_CH3, TIM8_CH3,
DFSDM2_CKIN3,
- 39 E1 65 E10 F11 98 PC8 I/O FT - USART6_CK, -
QUADSPI_BK1_IO2,
SDIO_D0, EVENTOUT
MCO_2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S2_CKIN,
- 40 E2 66 D12 E11 99 PC9 I/O FT - -
DFSDM2_DATIN3,
QUADSPI_BK1_IO0,
SDIO_D1, EVENTOUT
MCO_1, TIM1_CH1,
I2C3_SCL,
DFSDM1_CKOUT,
USART1_CK,
29 41 D3 67 D11 E12 100 PA8 I/O FT - -
UART7_RX,
USB_FS_SOF,
CAN3_RX, SDIO_D1,
EVENTOUT
TIM1_CH2,
DFSDM2_CKIN3,
I2C3_SMBA,
30 42 D2 68 D10 D12 101 PA9 I/O FT - SPI2_SCK/I2S2_CK, -
USART1_TX,
USB_FS_VBUS,
SDIO_D2, EVENTOUT
TIM1_CH3,
DFSDM2_DATIN3,
SPI2_MOSI/I2S2_SD,
31 43 D1 69 C12 D11 102 PA10 I/O FT - SPI5_MOSI/I2S5_SD, -
USART1_RX,
USB_FS_ID,
EVENTOUT
60/209 DocID029161 Rev 7


Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
TIM1_CH4,
DFSDM2_CKIN5,
SPI2_NSS/I2S2_WS,
SPI4_MISO,
USART1_CTS,
32 44 C3 70 B12 C12 103 PA11 I/O FT - -
USART6_TX,
CAN1_RX,
USB_FS_DM,
UART4_RX,
EVENTOUT
TIM1_ETR,
DFSDM2_DATIN5,
SPI2_MISO,
SPI5_MISO,
33 45 B3 71 A12 B12 104 PA12 I/O FT - -
USART1_RTS,
USART6_RX,
CAN1_TX, USB_FS_DP,
UART4_TX, EVENTOUT
JTMS-SWDIO,
34 46 C2 72 A11 A12 105 PA13 I/O FT - -
EVENTOUT
- - C1 73 C11 G9 106 VCAP_2 S - - - -
35 47 B1 74 F11 G10 107 VSS S - - - -
- 48 - 75 G11 - - VDD S - - - -
36 - A1 - - F9 108 VDD S - - - -
JTCK-SWCLK,
37 49 B2 76 A10 A11 109 PA14 I/O FT - -
EVENTOUT
JTDI,
TIM2_CH1/TIM2_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
38 50 A3 77 A9 A10 110 PA15 I/O FT - -
USART1_TX,
UART7_TX,
SAI1_MCLK_A,
CAN3_TX, EVENTOUT
DFSDM2_CKIN5,
SPI3_SCK/I2S3_CK,
- 51 A2 78 B11 B11 111 PC10 I/O FT - USART3_TX, -
QUADSPI_BK1_IO1,
SDIO_D2, EVENTOUT
DocID029161 Rev 7 61/209

74

Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
DFSDM2_DATIN5,
I2S3ext_SD,
SPI3_MISO,
USART3_RX,
- 52 C4 79 C10 B10 112 PC11 I/O FT - -
UART4_RX,
QUADSPI_BK2_NCS,
FSMC_D2/FSMC_DA2,
SDIO_D3, EVENTOUT
SPI3_MOSI/I2S3_SD,
USART3_CK,
- 53 B4 80 B10 C10 113 PC12 I/O FT - UART5_TX, -
FSMC_D3/FSMC_DA3,
SDIO_CK, EVENTOUT
DFSDM2_CKIN6,
CAN1_RX, UART4_RX,
- - A4 81 C9 E10 114 PD0 I/O FT - -
FSMC_D2/FSMC_DA2,
EVENTOUT
DFSDM2_DATIN6,
(2) CAN1_TX, UART4_TX,
- - NC 82 B9 D10 115 PD1 I/O FT -
FSMC_D3/FSMC_DA3,
EVENTOUT
TIM3_ETR,
DFSDM2_CKOUT,
UART5_RX,
- 54 C5 83 C8 E9 116 PD2 I/O FT - -
FSMC_NWE,
SDIO_CMD,
EVENTOUT
TRACED1,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN0,
(2)
- - NC 84 B8 D9 117 PD3 I/O FT USART2_CTS, -
QUADSPI_CLK,
FSMC_CLK,
EVENTOUT
DFSDM1_CKIN0,
(2) USART2_RTS,
- - NC 85 B7 C9 118 PD4 I/O FT -
FSMC_NOE,
EVENTOUT
DFSDM2_CKOUT,
(2) USART2_TX,
- - NC 86 A6 B9 119 PD5 I/O FT -
FSMC_NWE,
EVENTOUT
- - - - - E7 120 VSS S - - - -
- - - - - F7 121 VDD S - - - -
62/209 DocID029161 Rev 7


Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
SPI3_MOSI/I2S3_SD,
DFSDM1_DATIN1,
(2)
- - NC 87 B6 A8 122 PD6 I/O FT USART2_RX, -
FSMC_NWAIT,
EVENTOUT
DFSDM1_CKIN1,
(2) USART2_CK,
- - NC 88 A5 A9 123 PD7 I/O FT -
FSMC_NE1,
EVENTOUT
USART6_RX,
QUADSPI_BK2_IO2,
- - - - - E8 124 PG9 I/O FT - -
FSMC_NE2,
EVENTOUT
FSMC_NE3,
- - - - - D8 125 PG10 I/O FT - -
EVENTOUT
CAN2_RX,
- - - - - C8 126 PG11 I/O FT - UART10_RX, -
EVENTOUT
USART6_RTS,
CAN2_TX, UART10_TX,
- - - - - B8 127 PG12 I/O FT - -
FSMC_NE4,
EVENTOUT
TRACED2,
USART6_CTS,
- - - - - D7 128 PG13 I/O FT - -
FSMC_A24,
EVENTOUT
TRACED3,
USART6_TX,
- - - - - C7 129 PG14 I/O FT - QUADSPI_BK2_IO3, -
FSMC_A25,
EVENTOUT
- - - - - - 130 VSS S - - - -
- - - - - F6 131 VDD S - - - -
USART6_CTS,
- - - - - B7 132 PG15 I/O FT - -
EVENTOUT
JTDO-SWO, TIM2_CH2,
I2CFMP1_SDA,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
39 55 A5 89 A8 A7 133 PB3 I/O FTf - -
USART1_RX,
UART7_RX, I2C2_SDA,
SAI1_SD_A, CAN3_RX,
EVENTOUT
DocID029161 Rev 7 63/209

74

Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
JTRST, TIM3_CH1,
SPI1_MISO,
SPI3_MISO,
I2S3ext_SD,
40 56 B5 90 A7 A6 134 PB4 I/O FT - -
UART7_TX, I2C3_SDA,
SAI1_SCK_A,
CAN3_TX, SDIO_D0,
EVENTOUT
LPTIM1_IN1,
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
41 57 A6 91 C5 B6 135 PB5 I/O FT - -
SPI3_MOSI/I2S3_SD,
CAN2_RX, SAI1_FS_A,
UART5_RX, SDIO_D3,
EVENTOUT
LPTIM1_ETR,
TIM4_CH1, I2C1_SCL,
DFSDM2_CKIN7,
42 58 B6 92 B5 C6 136 PB6 I/O FT - USART1_TX, CAN2_TX, -
QUADSPI_BK1_NCS,
UART5_TX, SDIO_D0,
EVENTOUT
LPTIM1_IN2,
TIM4_CH2, I2C1_SDA,
43 59 B7 93 B4 D6 137 PB7 I/O FT - DFSDM2_DATIN7, -
USART1_RX,
FSMC_NL, EVENTOUT
44 60 A7 94 A4 D5 138 BOOT0 I B - - VPP
LPTIM1_OUT,
TIM4_CH3, TIM10_CH1,
I2C1_SCL,
SPI5_MOSI/I2S5_SD,
45 61 C6 95 A3 C5 139 PB8 I/O FT - -
DFSDM2_CKIN1,
CAN1_RX, I2C3_SDA,
UART5_RX, SDIO_D4,
EVENTOUT
TIM4_CH4, TIM11_CH1,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
46 62 D6 96 B3 B5 140 PB9 I/O FT - DFSDM2_DATIN1, -
CAN1_TX, I2C2_SDA,
UART5_TX, SDIO_D5,
EVENTOUT
64/209 DocID029161 Rev 7


Pin Number
Pin name
UFQFPN48
UFBGA100
UFBGA144
WLCSP81
LQFP100
LQFP144
LQFP64

reset)(1)
TIM4_ETR,
DFSDM2_CKIN4,
(2)
- - NC 97 C3 A5 141 PE0 I/O FT UART8_Rx, -
FSMC_NBL0,
EVENTOUT
DFSDM2_DATIN4,
(2) UART8_Tx,
- - NC 98 A2 A4 142 PE1 I/O FT -
FSMC_NBL1,
EVENTOUT
47 63 A8 99 D3 E6 - VSS S - - - -
- - B8 - H3 E5 143 PDR_ON I FT - - -
48 64 A9 100 C4 F5 144 VDD S - - - -
1. Function availability depends on the chosen device.

2. NC (Not Connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the
output data register to avoid extra power consumption in low power mode.
3. Compatibility issue on alternate function pin PE4 SAI1_SD_A and PE6 SAI1_FS_A: Pins have been swapped versus other
MCUs supporting those alternate SAI functions on those pins
4. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
5. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F413/423 reference manual.
6. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
7. Incompatibility issue on alternate function with other MCUs supporting UART4: UART4_TX wrongly mapped to PD10
instead of PC10
Table 11. FSMC pin definition

FSMC
Pins NOR/PSRAM 64 pins 81 pins 100 pins 144 pins
LCD/NOR/
PSRAM/SRAM Mux
PE2 A23 A23 - - Yes Yes

PF0 A0 - - - - Yes
DocID029161 Rev 7 65/209

74
Table 11. FSMC pin definition (continued)

FSMC
LCD/NOR/
PSRAM/SRAM Mux
PF1 A1 - - - - Yes
PF2 A2 - - - - Yes
PF3 A3 - - - - Yes
PF4 A4 - - - - Yes
PF5 A5 - - - - Yes
PC2 NWE NWE Yes Yes Yes Yes
PC3 A0 - Yes Yes Yes Yes
PA2 D4 DA4 Yes Yes Yes Yes
PC4 NE4 NE4 Yes Yes Yes Yes
PC5 NOE NOE Yes Yes Yes Yes
PF12 A6 - - - - Yes
PF13 A7 - - - - Yes
PF14 A8 - - - - Yes
PF15 A9 - - - - Yes
PG0 A10 - - - - Yes
PG1 A11 - - - - Yes
PE7 D4 DA4 - - Yes Yes
PE8 D5 DA5 - - Yes Yes
PE9 D6 DA6 - Yes Yes Yes
PB12 D13 DA13 Yes Yes Yes Yes
PB14 D0 DA0 Yes Yes Yes Yes
PD8 D13 DA13 - - - Yes
PD9 D14 DA14 - Yes Yes Yes
66/209 DocID029161 Rev 7

Table 11. FSMC pin definition (continued)

FSMC
LCD/NOR/
PSRAM/SRAM Mux
PD11 A16 A16 - - Yes Yes

PD14 D0 DA0 - - Yes Yes
PG2 A12 - - - - Yes
PG3 A13 - - - - Yes
PG4 A14 - - - - Yes
PG5 A15 - - - - Yes
PC6 D1 DA1 Yes Yes Yes Yes
PD2 NWE NWE Yes Yes Yes Yes
PD3 CLK CLK - - Yes Yes
PD4 NOE NOE - - Yes Yes
PD5 NWE NWE - - Yes Yes
PD6 NWAIT NWAIT - - Yes Yes
PD7 NE1 NE1 - - Yes Yes
PG9 NE2 NE2 - - - Yes
PG13 A24 A24 - - - Yes
PG14 A25 A25 - - - Yes
PB7 NL NL Yes Yes Yes Yes
PE0 NBL0 NBL0 - - Yes Yes
PE1 NBL1 NBL1 - - Yes Yes
DocID029161 Rev 7 67/209

74
4.9 Alternate functions
68/209
Pinouts and pin description

Table 12. STM32F423xH alternate functions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SPI3/I2S3/ SAI1/
SPI2/I2S2/ I2C2/I2C3/ UART4/
Port SPI1/I2S1/ SAI1/ DFSDM1/ DFSDM1/
SPI3/I2S3/ I2CFMP1/ UART5/
SYS_ TIM1/2/ DFSDM2/ I2C1/2/3/ SPI2/I2S2/ DFSDM2/ USART3/4/ DFSDM2/ SYS_
TIM3/4/5 SPI4/I2S4/ CAN1/2/ UART9/ FSMC /SDIO - RNG
AF LPTIM1 TIM8/9/10/11 I2CFMP1 SPI3/I2S3/ USART1/ 5/6/7/8/ QUADSPI/ AF
SPI5/I2S5/ TIM12/13/14/ UART10
SPI4/I2S4 USART2/ CAN1 FSMC
DFSDM1/2 QUADSPI /CAN3
USART3 /OTG1_FS
TIM2_CH1/
TIM5_ USART2_ UART4_ EVENT
PA0 - TIM2_ TIM8_ETR - - - - - - - - -
CH1 CTS TX OUT
ETR
TIM5_ SPI4_MOSI/I USART2_ UART4_ QUADSPI_ EVENT
PA1 - TIM2_CH2 - - - - - - - -
CH2 2S4_SD RTS RX BK1_IO3 OUT
TIM5_ USART2_ FSMC_D4/ EVENT
PA2 - TIM2_CH3 TIM9_CH1 - I2S2_CKIN - - - - - - -
CH3 TX FSMC_DA4 OUT
TIM5_ USART2_ FSMC_D5/ EVENT
PA3 - TIM2_CH4 TIM9_CH2 - I2S2_MCK - - - SAI1_SD_B - - -
CH4 RX FSMC_DA5 OUT
DocID029161 Rev 7
SPI1_NSS/I2 SPI3_NSS/I USART2_ DFSDM1_ FSMC_D6/ EVENT

PA4 - - - - - - - - - -
S1_WS 2S3_WS CK DATIN1 FSMC_DA6 OUT
TIM2_CH1/
SPI1_SCK/I2 DFSDM1_ FSMC_D7/ EVENT
PA5 - TIM2_ - TIM8_CH1N - - - - - - - -
S1_CK CKIN1 FSMC_DA7 OUT
ETR
TIM1_ TIM3_ DFSDM2_ TIM13_ QUADSPI_B SDIO_ EVENT
PA6 - TIM8_BKIN - SPI1_MISO I2S2_MCK - - - -
BKIN CH1 CKIN1 CH1 K2_IO0 CMD OUT
TIM1_ TIM3_ TIM8_ SPI1_MOSI/I DFSDM2_ TIM14_ QUADSPI_B EVENT
PA7 - - - - - - - -
Port A
CH1N CH2 CH1N 2S1_SD DATIN1 CH1 K2_IO1 OUT

I2C3_ DFSDM1_ USART1_ UART7_ USB_FS_ CAN3_ SDIO_ EVENT
PA8 MCO_1 TIM1_CH1 - - - - - -
SCL CKOUT CK RX SOF RX D1 OUT
DFSDM2_ I2C3_ SPI2_SCK/I2 USART1_ USB_FS_ SDIO_ EVENT
PA9 - TIM1_CH2 - - - - - - -
CKIN3 SMBA S2_CK TX VBUS D2 OUT
DFSDM2_ SPI2_MOSI/I SPI5_MOSI/ USART1_ USB_FS_ EVENT
PA10 - TIM1_CH3 - - - - - - - -
DATIN3 2S2_SD I2S5_SD RX ID OUT
DFSDM2_ SPI2_NSS/I2 USART1_ USART6_ USB_FS_ UART4_ EVENT
PA11 - TIM1_CH4 - - SPI4_MISO CAN1_RX - - -
CKIN5 S2_WS CTS TX DM RX OUT
DFSDM2_ USART1_ USART6_ USB_FS_ UART4_ EVENT
PA12 - TIM1_ETR - - SPI2_MISO SPI5_MISO CAN1_TX - - -
DATIN5 RTS RX DP TX OUT
JTMS- EVENT
STM32F423xH
PA13 - - - - - - - - - - - - - -
SWDIO OUT
JTCK- EVENT
PA14 - - - - - - - - - - - - - -
SWCLK OUT
TIM2_CH1/
SPI1_NSS/ SPI3_NSS/ USART1_ UART7_ SAI1_ CAN3_ EVENT
PA15 JTDI TIM2_ - - - - - - -
I2S1_WS I2S3_WS TX TX MCLK_A TX OUT
ETR
Table 12. STM32F423xH alternate functions (continued)
STM32F423xH
SPI3/I2S3/ SAI1/
SPI1/I2S1/ SAI1/ DFSDM1/ DFSDM1/
Port SPI3/I2S3/ I2CFMP1/ UART5/
USART3 /OTG1_FS
TIM1_ TIM3_ TIM8_ SPI5_SCK/I EVENT

PB0 - - - - - - - - - - -
CH2N CH3 CH2N 2S5_CK OUT
TIM1_ TIM3_ TIM8_ SPI5_NSS/ DFSDM1_ QUADSPI_C EVENT
PB1 - - - - - - - - -
CH3N CH4 CH3N I2S5_WS DATIN0 LK OUT
LPTIM1_ DFSDM1_ QUADSPI_C EVENT
PB2 - - - - - - - - - - - -
OUT CKIN0 LK OUT
JTDO- I2CFMP1 SPI1_SCK/I2 SPI3_SCK/I USART1_ UART7_ CAN3_ EVENT
PB3 TIM2_CH2 - - I2C2_SDA SAI1_SD_A - - -
SWO _SDA S1_CK 2S3_CK RX RX RX OUT
TIM3_ I2S3ext_ UART7_ SAI1_SCK_ CAN3_ EVENT
PB4 JTRST - - - SPI1_MISO SPI3_MISO I2C3_SDA SDIO_D0 - -
CH1 SD TX A TX OUT
LPTIM1_ TIM3_ I2C1_ SPI1_MOSI/I SPI3_MOSI/ UART5_ EVENT
DocID029161 Rev 7
PB5 - - - - CAN2_RX SAI1_FS_A SDIO_D3 - -

IN1 CH2 SMBA 2S1_SD I2S3_SD RX OUT
LPTIM1_ TIM4_ DFSDM2_ USART1_ QUADSPI_ UART5_ EVENT
PB6 - - I2C1_SCL - - CAN2_TX SDIO_D0 - -
ETR CH1 CKIN7 TX BK1_NCS TX OUT
LPTIM1_ TIM4_ I2C1_ DFSDM2_ USART1_ EVENT
PB7 - - - - - - - FSMC_NL - -
IN2 CH2 SDA DATIN7 RX OUT
Port B
LPTIM1_ TIM4_ TIM10_ I2C1_ SPI5_MOSI/ DFSDM2_ UART5_ EVENT

PB8 - - CAN1_RX I2C3_SDA - SDIO_D4 - -
OUT CH3 CH1 SCL I2S5_SD CKIN1 RX OUT
TIM4_ TIM11_ I2C1_ SPI2_NSS/I2 DFSDM2_ UART5_ EVENT
PB9 - - - CAN1_TX I2C2_SDA - SDIO_D5 - -
CH4 CH1 SDA S2_WS DATIN1 TX OUT
I2C2_ SPI2_SCK/I2 USART3_ I2CFMP1_ DFSDM2_ EVENT
PB10 - TIM2_CH3 - - I2S3_MCK - - SDIO_D7 - -
SCL S2_CK TX SCL CKOUT OUT
I2C2_ USART3_ EVENT
PB11 - TIM2_CH4 - - I2S2_CKIN - - - - - - - -
SDA RX OUT

TIM1_ I2C2_ SPI2_NSS/I2 SPI4_NSS/ SPI3_SCK/ USART3_ DFSDM1_ UART5_ FSMC_D13/F EVENT
PB12 - - - CAN2_RX - -
BKIN SMBA S2_WS I2S4_WS I2S3_CK CK DATIN1 RX SMC_DA13 OUT
TIM1_ I2CFMP1 SPI2_SCK/I2 SPI4_SCK/ USART3_ DFSDM1_ UART5_ EVENT
PB13 - - - - CAN2_TX - - -
CH1N _SMBA S2_CK I2S4_CK CTS CKIN1 TX OUT
TIM1_ TIM8_ I2CFMP1 USART3_ DFSDM1_ FSMC_D0/ EVENT
PB14 - - SPI2_MISO I2S2ext_SD TIM12_CH1 - SDIO_D6 - -
CH2N CH2N _SDA RTS DATIN2 FSMC_DA0 OUT
RTC_ TIM1_ TIM8_ I2CFMP1 SPI2_MOSI/I DFSDM1_ EVENT
PB15 - - - TIM12_CH2 - - SDIO_CK - -
REFIN CH3N CH3N _SCL 2S2_SD CKIN2 OUT
69/209
70/209

SPI3/I2S3/ SAI1/
USART3 /OTG1_FS
LPTIM1_ DFSDM2_CK SAI1_ EVENT

PC0 - - - - - - - - - - - -
IN1 IN4 MCLK_B OUT
LPTIM1_ DFSDM2_DA EVENT
PC1 - - - - - SAI1_SD_B - - - - - - -
OUT TIN4 OUT
LPTIM1_IN DFSDM2_DA SAI1_SCK_ DFSDM1_ EVENT
PC2 - - - SPI2_MISO I2S2ext_SD - - - FSMC_NWE - -
2 TIN7 B CKOUT OUT
LPTIM1_ DFSDM2_CK SPI2_MOSI/I EVENT
PC3 - - - - SAI1_FS_B - - - - FSMC_A0 - -
ETR IN7 2S2_SD OUT
DFSDM2_CK QUADSPI_ EVENT
PC4 - - - - I2S1_MCK - - - - - FSMC_NE4 - -
IN2 BK2_IO2 OUT
DFSDM2_DA I2CFMP1 USART3_ QUADSPI_ EVENT
DocID029161 Rev 7
PC5 - - - - - - - - FSMC_NOE - -
TIN2 _SMBA RX BK2_IO3 OUT
TIM3_ I2CFMP1 DFSDM1_ DFSDM2_ USART6_ FSMC_D1/ EVENT
PC6 - - TIM8_CH1 I2S2_MCK - - SDIO_D6 - -
CH1 _SCL CKIN3 DATIN6 TX FSMC_DA1 OUT
TIM3_ I2CFMP1 SPI2_SCK/ DFSDM2_ USART6_ DFSDM1_ EVENT
PC7 - - TIM8_CH2 I2S3_MCK - - SDIO_D7 - -
CH2 _SDA I2S2_CK CKIN6 RX DATIN3 OUT
Port C
TIM3_ DFSDM2_ USART6_ QUADSPI_ EVENT

PC8 - - TIM8_CH3 - - - - - SDIO_D0 - -
CH3 CKIN3 CK BK1_IO2 OUT
TIM3_ I2C3_ DFSDM2_ QUADSPI_ EVENT
PC9 MCO_2 - TIM8_CH4 I2S2_CKIN - - - - SDIO_D1 - -
CH4 SDA DATIN3 BK1_IO0 OUT
DFSDM2_ SPI3_SCK/ USART3_ QUADSPI_ EVENT
PC10 - - - - - - - - SDIO_D2 - -
CKIN5 I2S3_CK TX BK1_IO1 OUT
DFSDM2_ USART3_ UART4_ QUADSPI_ FSMC_D2/ EVENT
PC11 - - - - I2S3ext_SD SPI3_MISO - SDIO_D3 - -
DATIN5 RX RX BK2_NCS FSMC_DA2 OUT
SPI3_MOSI/ USART3_ UART5_ FSMC_D3/F EVENT
PC12 - - - - - - - - SDIO_CK - -
I2S3_SD CK TX SMC_DA3 OUT
EVENT
PC13 - - - - - - - - - - - - - - -
OUT
EVENT
PC14 - - - - - - - - - - - - - - -
OUT
EVENT
STM32F423xH
PC15 - - - - - - - - - - - - - - -
OUT
STM32F423xH
SPI3/I2S3/ SAI1/
USART3 /OTG1_FS
DFSDM2_ UART4_ FSMC_D2/ EVENT

PD0 - - - - - - - - CAN1_RX - - -
CKIN6 RX FSMC_DA2 OUT
DFSDM2_ UART4_ FSMC_D3/ EVENT
PD1 - - - - - - - - CAN1_TX - - -
DATIN6 TX FSMC_DA3 OUT
TIM3_ DFSDM2_ UART5_ FSMC_ EVENT
PD2 - - - - - - - - SDIO_CMD - -
ETR CKOUT RX NWE OUT
TRACE SPI2_SCK/ DFSDM1_ USART2_ QUADSPI_ EVENT
PD3 - - - - - - - FSMC_CLK - -
D1 I2S2_CK DATIN0 CTS CLK OUT
DFSDM1_ USART2_ FSMC_ EVENT
PD4 - - - - - - - - - - - -
CKIN0 RTS NOE OUT
DFSDM2_ USART2_ FSMC_ EVENT
DocID029161 Rev 7
PD5 - - - - - - - - - - - -
CKOUT TX NWE OUT
SPI3_MOSI/ DFSDM1_ USART2_ FSMC_ EVENT
PD6 - - - - - - - - - - -
I2S3_SD DATIN1 RX NWAIT OUT
DFSDM1_ USART2_ EVENT
PD7 - - - - - - - - - - FSMC_NE1 - -
CKIN1 CK OUT
Port D
USART3_ FSMC_D13/F EVENT

PD8 - - - - - - - - - - - - -
TX SMC_DA13 OUT
USART3_ FSMC_D14/F EVENT
PD9 - - - - - - - - - - - - -
RX SMC_DA14 OUT
USART3_ UART4_ FSMC_D15/F EVENT
PD10 - - - - - - - - - - - -
CK TX SMC_DA15 OUT
DFSDM2_ I2CFMP1 USART3_ QUADSPI_ EVENT
PD11 - - - - - - - - FSMC_A16 - -
DATIN2 _SMBA CTS BK1_IO0 OUT

TIM4_ DFSDM2_ I2CFMP1 USART3_ QUADSPI_ EVENT
PD12 - - - - - - - FSMC_A17 - -
CH1 CKIN2 _SCL RTS BK1_IO1 OUT
TIM4_ I2CFMP1 QUADSPI_ EVENT
PD13 - - - - - - - - - FSMC_A18 - -
CH2 _SDA BK1_IO3 OUT
TIM4_ I2CFMP1 DFSDM2_ UART9_ FSMC_D0/ EVENT
PD14 - - - - - - - - - -
CH3 _SCL CKIN0 RX FSMC_DA0 OUT
TIM4_ I2CFMP1 DFSDM2_ UART9_ FSMC_D1/ EVENT
PD15 - - - - - - - - - -
CH4 _SDA DATIN0 TX FSMC_DA1 OUT
71/209
72/209

SPI3/I2S3/ SAI1/
USART3 /OTG1_FS
TIM4_ DFSDM2_ UART8_ FSMC_ EVENT

PE0 - - - - - - - - - - -
ETR CKIN4 Rx NBL0 OUT
DFSDM2_ UART8_ FSMC_ EVENT
PE1 - - - - - - - - - - - -
DATIN4 Tx NBL1 OUT
TRACE SPI4_SCK SPI5_SCK/ SAI1_ QUADSPI_ UART10 EVENT
PE2 - - - - - - FSMC_A23 - -
CLK /I2S4_CK I2S5_CK MCLK_A BK1_IO2 _RX OUT
TRACE UART10 EVENT
PE3 - - - - - - SAI1_SD_B - - - FSMC_A19 - -
D0 _TX OUT
TRACE SPI4_NSS/ SPI5_NSS/ DFSDM1_ EVENT
PE4 - - - - SAI1_SD_A - - - FSMC_A20 - -
D1 I2S4_WS I2S5_WS DATIN3 OUT
TRACE SAI1_SCK_ DFSDM1_ EVENT
DocID029161 Rev 7
PE5 - - TIM9_CH1 - SPI4_MISO SPI5_MISO - - - FSMC_A21 - -

D2 A CKIN3 OUT
TRACE SPI4_MOSI/I SPI5_MOSI/ EVENT
PE6 - - TIM9_CH2 - SAI1_FS_A - - - - FSMC_A22 - -
D3 2S4_SD I2S5_SD OUT
DFSDM1_ UART7_ QUADSPI_ FSMC_D4/ EVENT
PE7 - TIM1_ETR - - - - - - - - -
DATIN2 Rx BK2_IO0 FSMC_DA4 OUT
Port E
TIM1_ DFSDM1_ UART7_ QUADSPI_ FSMC_D5/ EVENT

PE8 - - - - - - - - - -
CH1N CKIN2 Tx BK2_IO1 FSMC_DA5 OUT
DFSDM1_ QUADSPI_ FSMC_D6/ EVENT
PE9 - TIM1_CH1 - - - - - - - - - -
CKOUT BK2_IO2 FSMC_DA6 OUT
TIM1_ DFSDM2_ QUADSPI_ FSMC_D7/ EVENT
PE10 - - - - - - - - - - -
CH2N DATIN0 BK2_IO3 FSMC_DA7 OUT
TIM1_ DFSDM2_ SPI4_NSS/ SPI5_NSS/ FSMC_D8/ EVENT
PE11 - - - - - - - - - -
CH2 CKIN0 I2S4_WS I2S5_WS FSMC_DA8 OUT
TIM1_ DFSDM2_ SPI4_SCK/ SPI5_SCK/ FSMC_D9/ EVENT
PE12 - - - - - - - - - -
CH3N DATIN7 I2S4_CK I2S5_CK FSMC_DA9 OUT
TIM1_ DFSDM2_ FSMC_D10/ EVENT
PE13 - - - SPI4_MISO SPI5_MISO - - - - - - -
CH3 CKIN7 FSMC_DA10 OUT
TIM1_ SPI4_MOSI/I SPI5_MOSI/ DFSDM2_ FSMC_D11/ EVENT
PE14 - - - - - - - - - -
CH4 2S4_SD I2S5_SD DATIN1 FSMC_DA11 OUT
TIM1_ DFSDM2_ FSMC_D12/F EVENT
STM32F423xH
PE15 - - - - - - - - - - - -
BKIN CKIN1 SMC_DA12 OUT
STM32F423xH
SPI3/I2S3/ SAI1/
USART3 /OTG1_FS
I2C2_ EVENT
PF0 - - - - - - - - - - - FSMC_A0 - -
SDA OUT
I2C2_ EVENT
PF1 - - - - - - - - - - - FSMC_A1 - -
SCL OUT
I2C2_ EVENT
PF2 - - - - - - - - - - - FSMC_A2 - -
SMBA OUT
TIM5_ EVENT
PF3 - - - - - - - - - - - FSMC_A3 - -
CH1 OUT
TIM5_ EVENT
PF4 - - - - - - - - - - - FSMC_A4 - -
CH2 OUT
TIM5_ EVENT
DocID029161 Rev 7
PF5 - - - - - - - - - - - FSMC_A5 - -
CH3 OUT
TRACE UART7_ QUADSPI_ EVENT
PF6 - - TIM10_CH1 - - - SAI1_SD_B - - - - -
D0 Rx BK1_IO3 OUT
TRACE SAI1_ UART7_ QUADSPI_ EVENT
PF7 - - TIM11_CH1 - - - - - - - -
D1 MCLK_B Tx BK1_IO2 OUT
Port F
SAI1_SCK_ QUADSPI_B EVENT

PF8 - - - - - - - UART8_RX TIM13_CH1 - - - -
B K1_IO0 OUT
UART8_ QUADSPI_B EVENT
PF9 - - - - - - - SAI1_FS_B TIM14_CH1 - - - -
TX K1_IO1 OUT
TIM5_ EVENT
PF10 - TIM1_ETR - - - - - - - - - - - -
CH4 OUT
EVENT
PF11 - - - TIM8_ETR - - - - - - - - - - -
OUT

EVENT
PF12 - - - TIM8_BKIN - - - - - - - - FSMC_A6 - -
OUT
I2CFMP1 EVENT
PF13 - - - - - - - - - - - FSMC_A7 - -
_SMBA OUT
I2CFMP1 EVENT
PF14 - - - - - - - - - - - FSMC_A8 - -
_SCL OUT
I2CFMP1 EVENT
PF15 - - - - - - - - - - - FSMC_A9 - -
_SDA OUT
73/209
74/209

SPI3/I2S3/ SAI1/
USART3 /OTG1_FS
UART9_ EVENT
PG0 - - - - - - - - - CAN1_RX - FSMC_A10 - -
RX OUT
UART9_ EVENT
PG1 - - - - - - - - - CAN1_TX - FSMC_A11 - -
TX OUT
EVENT
PG2 - - - - - - - - - - - - FSMC_A12 - -
OUT
EVENT
PG3 - - - - - - - - - - - - FSMC_A13 - -
OUT
EVENT
PG4 - - - - - - - - - - - - FSMC_A14 - -
OUT
EVENT
DocID029161 Rev 7
PG5 - - - - - - - - - - - - FSMC_A15 - -
OUT
QUADSPI_B EVENT
PG6 - - - - - - - - - - - - - -
K1_NCS OUT
USART6_ EVENT
PG7 - - - - - - - - - - - - - -
CK OUT
Port G
USART6_ EVENT
PG8 - - - - - - - - - - - - - -
RTS OUT
USART6_ QUADSPI_ EVENT
PG9 - - - - - - - - - - FSMC_NE2 - -
RX BK2_IO2 OUT
EVENT
PG10 - - - - - - - - - - - - FSMC_NE3 - -
OUT
UART10 EVENT
PG11 - - - - - - - - - CAN2_RX - - - -
_RX OUT
USART6_ UART10 EVENT
PG12 - - - - - - - - CAN2_TX - FSMC_NE4 - -
RTS _TX OUT
TRACE USART6_ EVENT
PG13 - - - - - - - - - - FSMC_A24 - -
D2 CTS OUT
TRACE USART6_ QUADSPI_ EVENT
PG14 - - - - - - - - - FSMC_A25 - -
D3 TX BK2_IO3 OUT
USART6_ EVENT
STM32F423xH
PG15 - - - - - - - - - - - - - -
CTS OUT
EVENT
PH0 - - - - - - - - - - - - - - -
OUT
PortH
EVENT
PH1 - - - - - - - - - - - - - - -
OUT
STM32F423xH Memory mapping
5 Memory mapping
The memory map is shown in Figure 18.
Figure 18. Memory map
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DocID029161 Rev 7 75/209

78
Memory mapping STM32F423xH
Table 13. STM32F423xH register boundary addresses

Bus Boundary address Peripheral
0xE010 0000 - 0xFFFF FFFF Reserved

®
Cortex -M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals
0xA000 2000 - 0xDFFF FFFF Reserved
0xA000 1000 - 0xA000 1FFF QuadSPI control register
0xA000 0000 - 0xA000 0FFF FSMC control register
AHB3
0x9000 0000 - 0x9FFF FFFF QUADSPI
0x7000 0000 - 0x08FFF FFFF Reserved
0x6000 0000 - 0x6FFF FFFF FSMC
0x5006 0C00 - 0x5FFF FFFF Reserved
0x5006 0800 0x5006 0BFF RNG
AHB2 0x5006 0400 - 0x5006 07FF Reserved
0x5006 0000 - 0x5006 03FF AES
0x5004 0000 - 0x5005 FFFF Reserved
0x5000 0000 - 0x5003 FFFF USB OTG FS
0x4002 6800 - 0x4FFF FFFF Reserved
0x4002 6400 - 0x4002 67FF DMA2
0x4002 6000 - 0x4002 63FF DMA1
0x4002 4000 - 0X4002 5FFF Reserved
0x4002 3C00 - 0x4002 3FFF Flash interface register
0x4002 3800 - 0x4002 3BFF RCC
0x4002 3400 - 0x4002 37FF Reserved
0x4002 3000 - 0x4002 33FF CRC
AHB1 0x4002 2000 - 0x4002 2FFF Reserved
0x4002 1C00 - 0x4002 1FFF GPIOH
0x4002 1800 - 0x4002 1BFF GPIOG
0x4002 1400 - 0x4002 17FF GPIOF
0x4002 1000 - 0x4002 13FF GPIOE
0x4002 0C00 - 0x4002 0FFF GPIOD
0x4002 0800 - 0x4002 0BFF GPIOC
0x4002 0400 - 0x4002 07FF GPIOB
0x4002 0000 - 0x4002 03FF GPIOA
76/209 DocID029161 Rev 7

STM32F423xH Memory mapping
Table 13. STM32F423xH register boundary addresses (continued)

0x4001 6800- 0x4001 FFFF Reserved

0x4001 6400 - 0x4001 67FF DFSDM2
0x4001 6000 - 0x4001 63FF DFSDM1
0x4001 5C00 - 0x4001 5FFF Reserved
0x4001 5800 - 0x4001 5BFF SAI1
0x4001 5400 - 0x4001 57FF Reserved
0x4001 5000 - 0x4001 53FF SPI5/I2S5
0x4001 4C00 - 0x4001 4FFF Reserved
0x4001 4800 - 0x4001 4BFF TIM11
0x4001 4400 - 0x4001 47FF TIM10
0x4001 4000 - 0x4001 43FF TIM9
0x4001 3C00 - 0x4001 3FFF EXTI
APB2 0x4001 3800 - 0x4001 3BFF SYSCFG
0x4001 3400 - 0x4001 37FF SPI4/I2S4
0x4001 3000 - 0x4001 33FF SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF SDIO
0x4001 2400 - 0x4001 2BFF Reserved
0x4001 2000 - 0x4001 23FF ADC1/2/3
0x4001 1C00 - 0x4001 1FFF UART10
0x4001 1800 - 0x4001 1BFF UART9
0x4001 1400 - 0x4001 17FF USART6
0x4001 1000 - 0x4001 13FF USART1
0x4001 0800 - 0x4001 0FFF Reserved
0x4001 0400 - 0x4001 07FF TIM8
0x4001 0000 - 0x4001 03FF TIM1
DocID029161 Rev 7 77/209

78
Memory mapping STM32F423xH
Table 13. STM32F423xH register boundary addresses (continued)

0x4000 8000 - 0x4000 FFFF Reserved

0x4000 7C00 - 0x4000 7FFF UART8
0x4000 7800 - 0x4000 7BFF UART7
0x4000 7400 - 0x4000 77FF DAC1
0x4000 7000 - 0x4000 73FF PWR
0x4000 6C00- 0x4000 6FFF CAN3
0x4000 6800- 0x4000 6BFF CAN2
0x4000 6400- 0x4000 67FF CAN1
0x4000 6000- 0x4000 63FF I2CFMP1
0x4000 5C00 - 0x4000 5FFF I2C3
0x4000 5800 - 0x4000 5BFF I2C2
0x4000 5400 - 0x4000 57FF I2C1
0x4000 5000 - 0x4000 53FF UART5
0x4000 4C00 - 0x4000 4FFF UART4
0x4000 4800 - 0x4000 4BFF USART3
0x4000 4400 - 0x4000 47FF USART2
APB1 0x4000 4000 - 0x4000 43FF I2S3ext
0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF SPI2 / I2S2
0x4000 3400 - 0x4000 37FF I2S2ext
0x4000 3000 - 0x4000 33FF IWDG
0x4000 2C00 - 0x4000 2FFF WWDG
0x4000 2800 - 0x4000 2BFF RTC & BKP Registers
0x4000 2400 - 0x4000 27FF LPTIM1
0x4000 2000 - 0x4000 23FF TIM14
0x4000 1C00 - 0x4000 1FFF TIM13
0x4000 1800 - 0x4000 1BFF TIM12
0x4000 1400 - 0x4000 17FF TIM7
0x4000 1000 - 0x4000 13FF TIM6
0x4000 0C00 - 0x4000 0FFF TIM5
0x4000 0800 - 0x4000 0BFF TIM4
0x4000 0400 - 0x4000 07FF TIM3
0x4000 0000 - 0x4000 03FF TIM2
78/209 DocID029161 Rev 7

STM32F423xH Electrical characteristics
6 Electrical characteristics
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3 σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V ≤ VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2 σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 19.
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 20.
Figure 19. Pin loading conditions Figure 20. Input voltage measurement
-#5 PIN -#5 PIN
# P& 6).
-36 -36
DocID029161 Rev 7 79/209

175
Electrical characteristics STM32F423xH
6.1.6 Power supply scheme
Figure 21. Power supply scheme

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1. To connect PDR_ON pin, refer to Section: Power supply supervisor.

2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VCAP_2 pad is only available on 100-pin and 144-pin packages.
4. VDDA=VDD and VSSA=VSS.
5. VDDUSB is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and
associated DP/DM GPIOs. VDDUSB value does not depend on the VDD and VDDA values, but it must be the
last supply to be provided and the first to disappear.
Caution: Each power supply pair (for example VDD/VSS, VDDA/VSSA) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure good operation of
the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
80/209 DocID029161 Rev 7

6.1.7 Current consumption measurement
Figure 22. Current consumption measurement scheme
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6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics, and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 14. Voltage characteristics

Symbol Ratings Min Max Unit
External main supply voltage (including VDDA, VDD,

VDD–VSS –0.3 4.0
VDDUSB and VBAT)(1)
Input voltage on FT and TC pins(2) VSS–0.3 VDD+4.0
V
Input voltage on TTa pins VSS–0.3 4.0
VIN
Input voltage on any other pin VSS–0.3 4.0
Input voltage for BOOT0 VSS 9.0
|ΔVDDx| Variations between different VDD power pins - 50
Variations between all the different ground pins mV
|VSSX −VSS| - 50
including VREF-
see Section 6.3.14:
Absolute maximum
VESD(HBM) Electrostatic discharge voltage (human body model)
ratings (electrical
sensitivity)
1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the
external power supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 15 for the values of the maximum allowed
injected current.
DocID029161 Rev 7 81/209

175
Table 15. Current characteristics

Symbol Ratings Max. Unit
ΣIVDD Total current into sum of all VDD_x power lines (source)(1) 180
(1)
Σ IVSS Total current out of sum of all VSS_x ground lines (sink) -180
Σ IVDDUSB Total current into VDDUSB power lines (source) 25
IVDD Maximum current into each VDD_x power line (source)(1) 100
(1)
IVSS Maximum current out of each VSS_x ground line (sink) -100
Output current sunk by any I/O and control pin 25
IIO
Output current sourced by any I/O and control pin -25
mA
Total output current sunk by sum of all I/O and control pins (2) 120
ΣIIO Total output current sunk by sum of all USB I/Os 25
Total output current sourced by sum of all I/Os and control pins(2) -120
(4)
Injected current on FT and TC pins
– 5/ + 0
IINJ(PIN) (3) Injected current on NRST and B pins (4)
Injected current on TTa pins(5) ±5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(6) ± 25
1. All main power (VDD, VDDA, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the external power supply,
in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. A positive injection is induced by VIN>VDDA in the same time a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 14 for the values of the maximum allowed input voltage.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 16. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150

TJ Maximum junction temperature 125
°C
Maximum lead temperature during soldering
(1)
TLEAD (WLCSP81, LQFP64/100/144, UFQFPN48, see note
UFBGA100/144)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS
directive 2011/65/EU, July 2011).
82/209 DocID029161 Rev 7

6.3 Operating conditions
6.3.1 General operating conditions
Table 17. General operating conditions

Symbol Parameter Conditions Min Typ Max Unit
Power Scale3: Regulator ON,

VOS[1:0] bits in PWR_CR 0 - 64
register = 0x01
Internal AHB clock
fHCLK VOS[1:0] bits in PWR_CR 0 - 84 MHz
frequency
register = 0x10
VOS[1:0] bits in PWR_CR 0 - 100
register = 0x11
Internal APB1 clock
fPCLK1 - 0 - 50 MHz
frequency
Internal APB2 clock
fPCLK2 - 0 - 100 MHz
frequency
VDD Standard operating voltage - 1.7(1) - 3.6 V
Analog operating voltage
(ADC limited to 1.2 M 1.7(1) - 2.4
samples)
VDDA(2)(3) Must be the same potential as VDD(4) V
Analog operating voltage
(ADC limited to 2.4 M 2.4 - 3.6
samples)
USB supply voltage USB not used 1.7 3.3 3.6
VDDUSB (supply voltage for PA11 and V
PA12 pins) USB used(5) 3.0 - 3.6
VBAT Backup operating voltage - 1.65 - 3.6 V

VOS[1:0] bits in PWR_CR
register = 0x01 1.08(6) 1.14 1.20(6)
Max frequency 64 MHz
Regulator ON: 1.2 V VOS[1:0] bits in PWR_CR
V12 internal voltage on register = 0x10 1.20(6) 1.26 1.32(6) V
VCAP_1/VCAP_2 pins Max frequency 84 MHz
VOS[1:0] bits in PWR_CR
register = 0x11 1.26 1.32 1.38
Max frequency 100 MHz
Regulator OFF: 1.2 V Max frequency 64 MHz 1.10 1.14 1.20
external voltage must be
V12 Max frequency 84 MHz 1.20 1.26 1.32 V
supplied on
VCAP_1/VCAP_2 pins Max frequency 100 MHz 1.26 1.32 1.38
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175
Table 17. General operating conditions (continued)

Input voltage on 2 V ≤ VDD ≤ 3.6 V –0.3 - 5.5

RST, FT and TC pins(7) VDD ≤ 2 V –0.3 - 5.2
VIN V
Input voltage on TTa pins - - 0.3 - VDDA + 0.3
Input voltage on BOOT0 pin - 0 - 9
UFQFPN48 - - 625
WLCSP81 - - 504
LQFP64 - - 426
Power dissipation at
TA = 85°C for range 6 or LQFP100 - - 465
TA = 105°C for range 7(8)
LQFP144 - 571
UFBGA100 - - 351
UFBGA144 - - 417
PD mW
UFQFPN48 - - 156
WLCSP81 - - 126
LQFP64 - - 106
Power dissipation at
LQFP100 - - 116
TA = 125°C for range 3(8)
LQFP144 - - 143
UFBGA100 - - 088
UFBGA144 - - 104
Ambient temperature for Maximum power dissipation –40 - 85

range 6 Low power dissipation(9) –40 - 105
Ambient temperature for Maximum power dissipation –40 - 105

TA
range 7 Low power dissipation(9) –40 - 125
Ambient temperature for Maximum power dissipation –40 - 125 °C

range 3 Low power dissipation (9) –40 - 130
Range 6 –40 - 105
TJ Junction temperature range Range 7 –40 - 125
Range 3 –40 - 130
1. VDD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.17.2: Internal
reset OFF).
2. When the ADC is used, refer to Table 75: ADC characteristics.
3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
5. Only the DM (PA11) and DP (PA12) pads are supplied through VDDUSB. For application where the VBUS (PA9) is directly
connected to the chip, a minimum VDD supply of 2.7V is required.
(some application examples are shown in appendix B)
6. Guaranteed by test in production
7. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
84/209 DocID029161 Rev 7

8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
Table 18. Features depending on the operating power supply range

Maximum
Flash
Operating memory Maximum Flash Possible
Clock output
power ADC access memory access Flash
I/O operation frequency on
supply operation frequency frequency with memory
I/O pins(3)
range with no wait wait states (1)(2) operations
states
(fFlashmax)
8-bit erase
Conversion
VDD =1.7 to 100 MHz with 6 – No I/O and program
time up to 16 MHz(5) up to 30 MHz
2.1 V(4) wait states compensation operations
1.2 Msps
only
Conversion 16-bit erase
VDD = 2.1 to 100 MHz with 5 – No I/O
time up to 18 MHz up to 30 MHz and program
2.4 V wait states compensation
1.2 Msps operations
Conversion – I/O 16-bit erase
VDD = 2.4 to 100 MHz with 4
time up to 20 MHz compensation up to 50 MHz and program
2.7 V wait states
2.4 Msps works operations
– up to
100 MHz
when VDD =
Conversion – I/O 32-bit erase
VDD = 2.7 to 100 MHz with 3 3.0 to 3.6 V
time up to 25 MHz compensation and program
3.6 V(6) wait states – up to
2.4 Msps works operations
50 MHz
when VDD =
2.7 to 3.0 V
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. Refer to Table 61: I/O AC characteristics for frequencies vs. external load.
4. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.17.2: Internal
reset OFF).
5. Prefetch available over the complete VDD supply range.
6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of
D- and D+ pins will be degraded between 2.7 and 3 V.
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175
6.3.2 VCAP_1/VCAP_2 external capacitors

Stabilization for the main regulator is achieved by connecting the external capacitor CEXT to
the VCAP_1 and VCAP_2 pins. For packages supporting only 1 VCAP pin, the 2 CEXT
capacitors are replaced by a single capacitor.
CEXT is specified in Table 19.
Figure 23. External capacitor CEXT
&
(65
5/HDN
069
1. Legend: ESR is the equivalent series resistance.
Table 19. VCAP_1/VCAP_2 operating conditions(1)

Symbol Parameter Conditions
Capacitance of external capacitor with the pins

CEXT 2.2 µF
VCAP_1 and VCAP_2 available
ESR of external capacitor with the pins VCAP_1 and
ESR <2Ω
VCAP_2 available
Capacitance of external capacitor with a single VCAP
CEXT 4.7 µF
pin available
ESR of external capacitor with a single VCAP pin
ESR <1Ω
available
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
6.3.3 Operating conditions at power-up/power-down (regulator ON)

Subject to general operating conditions for TA.
Table 20. Operating conditions at power-up / power-down (regulator ON)

Symbol Parameter Min Max Unit
VDD rise time rate 20 ∞

tVDD µs/V
VDD fall time rate 20 ∞
86/209 DocID029161 Rev 7

6.3.4 Operating conditions at power-up / power-down (regulator OFF)

Subject to general operating conditions for TA.
Table 21. Operating conditions at power-up / power-down (regulator OFF)(1)

Symbol Parameter Conditions Min Max Unit
VDD rise time rate Power-up 20 ∞

tVDD
VDD fall time rate Power-down 20 ∞
µs/V
VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞
tVCAP
VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
Note: This feature is only available for UFBGA100 and UFBGA144 packages.
6.3.5 Embedded reset and power control block characteristics

The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage @ 3.3V.
Table 22. Embedded reset and power control block characteristics

PLS[2:0]=000 (rising edge) 2.09 2.14 2.19

PLS[2:0]=000 (falling edge) 1.98 2.04 2.08
PLS[2:0]=001 (rising edge) 2.23 2.30 2.37
PLS[2:0]=001 (falling edge) 2.13 2.19 2.25
PLS[2:0]=010 (rising edge) 2.39 2.45 2.51
PLS[2:0]=010 (falling edge) 2.29 2.35 2.39
PLS[2:0]=011 (rising edge) 2.54 2.60 2.65
Programmable voltage PLS[2:0]=011 (falling edge) 2.44 2.51 2.56

VPVD V
detector level selection PLS[2:0]=100 (rising edge) 2.70 2.76 2.82
PLS[2:0]=100 (falling edge) 2.59 2.66 2.71
PLS[2:0]=101 (rising edge) 2.86 2.93 2.99
PLS[2:0]=101 (falling edge) 2.65 2.84 3.02
PLS[2:0]=110 (rising edge) 2.96 3.03 3.10
PLS[2:0]=110 (falling edge) 2.85 2.93 2.99
PLS[2:0]=111 (rising edge) 3.07 3.14 3.21
PLS[2:0]=111 (falling edge) 2.95 3.03 3.09
(2)
VPVDhyst PVD hysteresis - - 100 - mV
Power-on/power-down Falling edge 1.60(1) 1.68 1.76

VPOR/PDR V
reset threshold Rising edge 1.64 1.72 1.80
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175
Table 22. Embedded reset and power control block characteristics (continued)
VPDRhyst(2) PDR hysteresis - - 40 - mV
Brownout level 1 Falling edge 2.13 2.19 2.24

VBOR1
threshold Rising edge 2.23 2.29 2.33

VBOR2 V

VBOR3
(2)
VBORhyst BOR hysteresis - - 100 - mV
TRSTTEMPO
(2)(3) POR reset timing - 0.5 1.5 3.0 ms
In-Rush current on
voltage regulator power-
IRUSH(2) - - 160 200 mA
on (POR or wakeup from
Standby)
In-Rush energy on
(2) voltage regulator power- VDD = 1.7 V, TA = 125 °C,
ERUSH - - 5.4 µC
on (POR or wakeup from IRUSH = 171 mA for 31 µs
Standby)
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design.
3. The reset timing is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first
instruction is fetched by the user application code.
6.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 22: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
88/209 DocID029161 Rev 7

Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at VDD or VSS (no load).
• All peripherals are disabled except if it is explicitly mentioned.
• The Flash memory access time is adjusted to both fHCLK frequency and VDD ranges
(refer to Table 18: Features depending on the operating power supply range).
• The voltage scaling is adjusted to fHCLK frequency as follows:
– Scale 3 for fHCLK ≤ 64 MHz
– Scale 2 for 64 MHz < fHCLK ≤ 84 MHz
– Scale 1 for 84 MHz < fHCLK ≤ 100 MHz
• The system clock is HCLK, fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
• External clock is 4 MHz and PLL is ON except if it is explicitly mentioned.
• The maximum values are obtained for VDD = 3.6 V and a maximum ambient
temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless
otherwise specified.
accelerator disabled) running from SRAM - VDD = 1.7 V
Typ Max(1)
fHCLK
Symbol Parameter Conditions Unit
(MHz) T = 25 °C T = 25 °C T =85 °C T =105 °C T =125 °C
A A A A A
100 32.9 34.96 35.30 37.21 40.79

84 26.5 28.13 28.58 30.50 33.96
External clock,
PLL ON, 64 18.3 19.44 20.11 21.76 25.03
all peripherals 50 14.4 15.28 16.12 17.95 21.11
enabled(2)(3)
25 7.5 8.10 9.35 11.09 14.38
20 6.4 6.99 8.17 9.96 13.17
HSI, PLL off, all 16 4.6 5.17 6.42 8.28 11.46
peripherals
Supply enabled(2)(3) 1 0.7 1.28 2.64 4.30 7.66
IDD current in mA
Run mode 100 15.4 16.43 17.35 19.17 22.85
84 12.4 13.28 14.32 16.12 19.67
External clock,
PLL ON, all 64 8.7 9.36 10.38 12.06 15.31
peripherals 50 6.9 7.47 8.54 10.36 13.49
disabled(3)
25 3.7 4.27 5.47 7.17 10.45
20 3.2 3.72 5.01 6.67 10.02
HSI, PLL off, all 16 2.3 2.80 4.05 5.90 9.07
peripherals
disabled(3) 1 0.6 1.14 2.51 4.16 7.51
1. Guaranteed by characterization results.

2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered.
DocID029161 Rev 7 89/209

175
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
accelerator disabled) running from SRAM - VDD = 3.6 V
Typ Max(1)
fHCLK
(MHz) TA= TA= TA= TA= TA=
25 °C 25 °C 85 °C 105 °C 125 °C
100 33.3 35.32(3) 35.65 37.65 41.26(3)

84 26.8 28.45(3) 28.97 30.82 34.39(3)
External clock, 64 18.6 19.74(3) 20.35 22.11 25.35(3)
PLL ON,
all peripherals enabled(2) 50 14.6 15.57 16.41 18.21 21.46
25 7.8 8.37 9.64 11.32 14.68
20 6.7 7.25 8.40 10.25 13.45
HSI, PLL OFF(4), 16 4.6 4.96 6.39 8.20 11.54

Supply all peripherals enabled(2) 1 0.8 0.86 2.51 4.34 7.65
IDD current in mA
100 15.7 16.74(3) 17.62 19.50 23.16(3)
Run mode
84 12.7 13.57(3) 14.60 16.38 19.98(3)
External clock,
PLL ON, 64 9.0 9.62(3) 10.60 12.37 15.58(3)
all peripherals 50 7.1 7.69 8.79 10.63 13.79
disabled(2)
25 4.0 4.52 5.68 7.44 10.68
20 3.4 4.03 5.23 6.90 10.27
HSI, PLL OFF, 16 2.3 2.44 4.00 5.81 9.13
all peripherals
disabled(2) 1 0.6 0.70 2.35 4.18 7.49

2. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
3. Tested in production
4. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered
90/209 DocID029161 Rev 7

(ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V
Typ Max(1)
fHCLK
(MHz) TA = TA = TA = TA = TA = Unit
25 °C 25 °C 85 °C 105 °C 125 °C
100 30.2 32.03 32.71 34.69 38.46

84 24.3 25.77 26.58 28.47 32.16
External clock, 64 16.8 17.80 18.66 20.53 23.85
PLL ON,
all peripherals enabled(2)(3) 50 13.2 14.05 15.12 16.85 20.27
25 7.1 7.62 8.92 10.81 14.11
20 6.1 6.69 7.95 9.72 13.09
HSI, PLL OFF, 16 4.4 4.99 6.28 8.18 11.45

Supply all peripherals enabled(2) 1 0.9 1.50 2.88 4.58 8.00
IDD current in mA
Run mode 100 12.6 13.46 14.75 16.68 20.54
84 10.2 10.90 12.25 14.10 17.84
External clock, 64 7.2 7.70 8.95 10.81 14.14
PLL ON(4)
all peripherals disabled(2) 50 5.7 6.26 7.56 9.26 12.72
25 3.2 3.77 5.11 6.82 10.26
20 2.9 3.41 4.79 6.49 9.92
HSI, PLL OFF, all 16 2.1 2.63 3.91 5.80 9.06

peripherals disabled(2) 1 0.8 1.34 2.72 4.42 7.86
1. Guaranteed by characterization results..
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
4. Refer to Table 47 and RM0383 for the possible PLL VCO setting
DocID029161 Rev 7 91/209

175
(ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.6 V
Typ Max(1)
fHCLK
25 °C 25 °C 85 °C 105 °C 125 °C
100 30.7 32.85(4) 33.30 35.37 39.08

84 24.7 26.48 27.15 28.94 32.65
External clock, 64 17.2 18.36 19.14 20.88 24.29
PLL ON(2),
25 7.4 7.97 9.23 11.05 14.42
20 6.4 6.99 8.18 10.03 13.32
HSI, PLL OFF, all 16 4.5 5.04 6.32 8.23 11.50

peripherals enabled(3) 1 1.0 1.50 2.89 4.59 8.01
Supply current
IDD mA
in Run mode 100 13.1 14.36 15.33 17.25 20.98
84 10.7 11.67 12.73 14.56 18.21
External clock, PLL ON(2) 64 7.5 8.23 9.40 11.13 14.52

25 3.5 4.19 5.37 7.08 10.48
20 3.2 3.71 5.02 6.72 10.15
HSI, PLL OFF, all 16 2.1 2.67 3.95 5.84 9.10

4. Tested in production.
92/209 DocID029161 Rev 7

(ART accelerator disabled) running from Flash memory - VDD = 3.6 V
Typ Max(1)
fHCLK
25 °C 25 °C 85 °C 105 °C 125 °C
100 39.9 42.46 43.17 45.32 49.19

84 32.6 34.71 35.45 37.58 41.24
External clock, 64 24.2 25.86 26.73 28.47 31.96
PLL ON(2),
25 10.8 11.55 12.83 14.66 18.03
20 9.2 9.82 11.16 13.09 16.36
HSI, PLL OFF, all 16 6.8 7.33 8.77 10.69 14.00

peripherals enabled(3) 1 1.2 1.83 3.08 4.83 8.19
Supply current
IDD mA
in Run mode 100 22.3 24.11 25.26 27.35 31.11
84 18.5 20.00 21.15 23.20 26.87

25 7.0 7.52 8.95 10.84 14.19
20 6.0 6.58 7.95 9.74 13.07
HSI, PLL OFF, all 16 4.5 4.97 6.40 8.30 11.59

DocID029161 Rev 7 93/209

175
(ART accelerator disabled) running from Flash memory - VDD = 1.7 V
Typ Max(1)
fHCLK
25 °C 25 °C 85 °C 105 °C 125 °C
100 36.1 38.48 39.08 40.91 44.59

84 30.6 32.60 33.14 35.10 38.56
External clock,
PLL ON, 64 23.9 25.67 26.27 27.94 31.19
all peripherals 50 18.9 20.32 21.04 22.85 26.10
enabled(2)(3)
25 10.8 11.63 12.75 14.56 17.87
20 9.2 9.84 11.06 12.98 16.23
HSI, PLL OFF, 16 7.1 7.69 9.02 10.87 14.25
all peripherals
Supply current enabled(2)(3) 1 1.2 1.84 3.10 4.84 8.20
IDD mA
in Run mode
100 18.6 20.33 21.23 23.15 26.71
84 16.5 18.09 19.01 20.81 24.29

all peripherals disabled 50 11.5 12.57 13.53 15.33 18.49
25 7.0 7.67 8.90 10.76 14.05
20 6.0 6.68 7.87 9.65 12.96
HSI, PLL OFF, 16 4.8 5.33 6.66 8.49 11.86

analog part.
94/209 DocID029161 Rev 7

(ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.6 V
Typ Max(1)
fHCLK
25 °C 25 °C 85 °C 105 °C 125 °C
100 42.3 45.08 45.76 47.88 51.71

84 34.6 36.87 37.58 39.64 43.32
External clock, 64 25.5 27.18 27.93 29.90 33.23
PLL ON,
25 10.9 11.61 12.87 14.72 18.08
20 9.3 9.86 11.20 13.13 16.41
HSI, PLL OFF, 16 6.9 7.37 8.81 10.72 14.04

all peripherals enabled 1 1.2 1.83 3.09 4.83 8.19
Supply current
IDD mA
in Run mode 100 24.7 26.76 27.84 29.93 33.66
84 20.5 22.18 23.25 25.33 28.98
External clock, 64 15.9 17.13 18.23 20.18 23.46
PLL ON(2)
25 7.1 7.57 9.01 10.88 14.25
20 6.1 6.61 7.98 9.80 13.11
HSI, PLL OFF, 16 4.5 5.00 6.44 8.33 11.63

DocID029161 Rev 7 95/209

175
(ART accelerator enabled with prefetch) running from Flash memory - VDD = 1.7 V
Typ Max(1)
fHCLK
25 °C 25 °C 85 °C 105 °C 125 °C
100 42.9 45.86 45.76 47.88 51.71

84 35.4 37.90 38.16 40.01 43.26
External clock, 64 26.2 28.19 28.74 30.37 33.54
PLL ON,
25 11.1 11.87 12.87 14.72 18.08
20 9.4 10.05 11.26 13.16 16.46
HSI, PLL OFF, 16 7.1 7.72 9.06 10.90 14.29

Supply current
IDD mA
in Run mode 100 25.4 27.83 27.84 29.93 33.66
84 21.4 23.44 24.10 25.77 29.04
External clock, 64 16.6 18.31 19.17 20.72 23.86
PLL ON(2)
25 7.2 7.90 9.01 10.88 14.25
20 6.2 6.83 8.05 9.88 13.15
HSI, PLL OFF, 16 4.8 5.37 6.70 8.52 11.89

96/209 DocID029161 Rev 7

Table 31. Typical and maximum current consumption in Sleep mode - VDD = 3.6 V
Typ Max(1)
fHCLK
Symbol Parameter Conditions TA = TA = TA = TA = TA = Unit
(MHz)
25 °C 25 °C 85 °C 105 °C 125 °C
100 21.6 22.97(4) 23.91 25.99 29.72
84 17.4 18.50 19.59 21.42 25.09
All peripherals enabled(2)(3),
External clock, 64 12.0 12.81 13.87 15.73 19.00
PLL ON, 50 9.5 10.15 11.33 13.22 16.44
Flash deep power down
25 5.2 5.79 7.11 8.82 12.18
20 4.6 5.17 6.41 8.28 11.48
(2)(3)
All peripherals enabled , 16 3.0 3.24 4.78 6.60 9.94
HSI, PLL OFF,
1 0.7 0.76 2.41 4.23 7.55
100 22.0 23.42 24.45 26.41 30.24
84 17.7 18.91 19.98 21.85 25.56
All peripherals enabled(2)(3), 64 12.4 13.17 14.30 16.07 19.48
External clock,
PLL ON Flash ON 50 9.8 10.48 11.72 13.53 16.90
25 5.5 6.05 7.41 9.11 12.55
20 4.9 5.42 6.72 8.57 11.89
All peripherals enabled (2)(3), 16 3.3 3.51 5.06 6.91 10.30
Supply HSI, PLL ON, Flash ON 1 0.9 1.01 2.67 4.52 7.88
IDD current in mA
Sleep mode 100 3.5 4.17 5.56 7.54 11.23
84 2.9 3.48 4.94 6.76 10.40
All peripherals disabled,
External clock, 64 2.2 2.73 3.94 5.80 8.98
PLL ON(2), 50 1.8 2.38 3.57 5.42 8.60
25 1.3 1.86 3.11 4.82 8.12
20 1.3 1.90 3.13 4.85 8.15
All peripherals disabled, 16 0.6 0.68 2.33 4.16 7.47
HSI, PLL OFF(2),
1 0.5 0.59 2.24 4.07 7.38
100 4.0 4.54 5.97 8.09 11.74
84 3.3 3.87 5.32 7.19 10.84
External clock,
PLL ON(2), Flash ON 50 2.2 2.69 3.93 5.82 9.04
25 1.6 2.13 3.37 5.20 8.46
20 1.6 2.16 3.39 5.22 8.48
HSI, PLL OFF(2), Flash ON 1 0.7 0.85 2.50 4.36 7.71
analog part.
DocID029161 Rev 7 97/209

175
Table 32. Typical and maximum current consumption in Sleep mode - VDD = 1.7 V
Typ Max(1)
fHCLK
25 °C 25 °C 85 °C 105 °C 125 °C
100 21.2 22.64 23.56 25.66 29.30

84 17.1 18.20 19.27 21.14 24.75
External clock,
PLL ON, 64 11.8 12.53 13.59 15.47 18.66
Flash deep power down, 50 9.3 9.88 11.06 12.94 16.11
all peripherals enabled(2)
25 5.0 5.52 6.83 8.61 11.88
20 4.4 4.93 6.16 8.03 11.19
HSI, PLL OFF(2), 16 3.0 3.53 4.91 6.57 9.94
Flash deep power down,
100 21.7 23.10 24.09 26.12 29.90

84 17.4 18.61 19.72 21.55 25.27
all peripherals enabled,
Flash ON 50 9.6 10.20 11.43 13.32 16.62
25 5.2 5.80 7.19 8.91 12.33
20 4.6 5.18 6.47 8.37 11.63
(2),
HSI, PLL OFF all 16 3.2 3.79 5.17 6.88 10.32
peripherals enabled,
1 0.9 1.43 2.80 4.50 7.92
Supply current Flash ON
IDD mA
in Sleep mode 100 3.3 3.82 5.34 7.25 10.97
84 2.7 3.22 4.70 6.54 10.13
All peripherals disabled,
External clock, 64 1.9 2.48 3.70 5.55 8.71
PLL ON(2), 50 1.6 2.13 3.35 5.15 8.35
25 1.0 1.61 2.90 4.57 7.91
20 1.1 1.66 2.93 4.59 7.93
HSI, PLL OFF(2),
Flash deep power down 1 0.5 1.04 2.40 4.06 7.40
100 3.7 4.28 5.76 7.83 11.49

84 3.1 3.60 5.11 6.96 10.64
External clock, PLL
ON(2), Flash ON 50 1.9 2.44 3.70 5.59 8.82
25 1.3 1.89 3.18 4.94 8.27
20 1.4 1.92 3.20 4.97 8.29
HSI, PLL OFF(2), Flash
ON 1 0.7 1.25 2.65 4.34 7.77
98/209 DocID029161 Rev 7

Table 33. Typical and maximum current consumptions in Stop mode - VDD = 1.7 V
Typ(1) Max(1)
Symbol Conditions Parameter Unit
TA = TA = TA = TA = TA =
25 °C 25 °C 85 °C 105 °C 125 °C
Flash in Stop mode, Main regulator usage 111.7 157.9 713.7 1323.5 2315.1
all oscillators OFF, no
independent watchdog Low power regulator usage 42.3 80.1 594.1 1167.6 2097.6
IDD_STOP Flash in Deep power Main regulator usage 77.9 113.1 568.3 1073.6 1883.7 µA
down mode, all Low power regulator usage 19.7 55.8 561.3 1123.2 2026.0
oscillators OFF, no
Low power low voltage regulator
independent watchdog 15.3 46.3 490.8 991.3 1793.9
usage
Table 34. Typical and maximum current consumption in Stop mode - VDD=3.6 V
Typ Max(1)
Symbol Conditions Parameter Unit
TA = TA = TA = TA = TA =
25 °C 25 °C 85 °C 105 °C 125 °C
Flash in Stop mode, all Main regulator usage 114.4 161.6(2) 723.0 1339.0 2342.7(2)
oscillators OFF, no
independent watchdog Low power regulator usage 44.1 82.5(2) 600.6 1179.3 2119.1
IDD_STOP Flash in Deep power Main regulator usage 80.6 116.7 572.3 1079.2 1896.3 µA
down mode, all Low power regulator usage 21.4 58.9 567.9 1134.5 2049.6
oscillators OFF, no
Low power low voltage
independent watchdog 17.0 49.0(2) 497.4 1003.6 1817.0(2)
regulator usage
Table 35. Typical and maximum current consumption in Standby mode - VDD= 1.7 V
Typ(1) Max(2)
Symbol Parameter Conditions TA = Unit
TA = TA = TA = TA =
25 °C 25 °C 85 °C 105 °C 125 °C
Low-speed oscillator (LSE in low drive
2.3 3.7 15.9 32.5 76.8
mode) and RTC ON
Supply current in
IDD_STBY Low-speed oscillator (LSE in high drive µA
Standby mode 2.9 4.3 16.5 33.1 77.4
mode) and RTC ON
RTC and LSE OFF 1.1 2.5 14.7 31.3 75.6
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
DocID029161 Rev 7 99/209

175
Table 36. Typical and maximum current consumption in Standby mode - VDD= 3.6 V
Typ(1) Max(2)
Symbol Parameter Conditions TA = TA = TA = TA = TA = Unit
25 °C 25 °C 85 °C 105 °C 125 °C
Low-speed oscillator (LSE in low drive

3.7 5.2 20.6 40.5 82.7
mode) and RTC ON
Supply current in
IDD_STBY Low-speed oscillator (LSE in high drive µA
Standby mode 4.5 6.0 21.4 41.3 83.5
mode) and RTC ON
RTC and LSE OFF 2.5 4.0 19.4 39.3 81.5(3)
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Guaranteed by characterization, not tested in production unless otherwise specified.
Table 37. Typical and maximum current consumptions in VBAT mode

Typ Max(2)
TA = TA = TA =
TA = 25 °C
Symbol Parameter Conditions(1) 85 °C 105 °C 125 °C Unit
VBAT = VBAT= VBAT = VBAT =

VBAT = 3.6 V
1.7 V 2.4 V 3.3 V 3.6 V
Low-speed oscillator (LSE in

0.74 0.84 1.04 1.24 3.00 5.00 10.00
Backup low-drive mode) and RTC ON
domain
IDD_VBAT Low-speed oscillator (LSE in µA
supply 1.51 1.64 1.89 2.00 3.80 5.80 11.60
high-drive mode) and RTC ON
current
RTC and LSE OFF 0.03 0.03 0.04 0.04 2.00 4.00 8.00
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
100/209 DocID029161 Rev 7

“low power” mode selection)
06Y9
“high drive” mode selection)
06Y9
DocID029161 Rev 7 101/209

175
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 59: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 39: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
I SW = V DD × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
102/209 DocID029161 Rev 7

Table 38. Switching output I/O current consumption
I/O toggling
Symbol Parameter Conditions(1) Typ Unit
frequency (fSW)
2 MHz 0.05
8 MHz 0.15
25 MHz 0.45
VDD = 3.3 V
50 MHz 0.85
C = CINT
60 MHz 1.00
84 MHz 1.40
90 MHz 1.67
2 MHz 0.10
8 MHz 0.35
VDD = 3.3 V 25 MHz 1.05

CEXT = 0 pF 50 MHz 2.20
C = CINT + CEXT + CS 60 MHz 2.40
84 MHz 3.55
90 MHz 4.23
I/O switching 2 MHz 0.20

IDDIO mA
current 8 MHz 0.65
VDD = 3.3 V 25 MHz 1.85

CEXT =10 pF 50 MHz 2.45
84 MHz 8.80
90 MHz 10.47
2 MHz 0.25
VDD = 3.3 V 8 MHz 1.00

CEXT = 22 pF 25 MHz 3.45
60 MHz 11.55
2 MHz 0.32
VDD = 3.3 V
8 MHz 1.27
CEXT = 33 pF
25 MHz 3.88
C = CINT + CEXT + CS
50 MHz 12.34
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
DocID029161 Rev 7 103/209

175
On-chip peripheral current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• The ART accelerator is ON.
• Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V.
• HCLK is the system clock at 100 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off,
– with only one peripheral clocked on,
– scale 1 with fHCLK = 100 MHz,
– scale 2 with fHCLK = 84 MHz,
– scale 3 with fHCLK = 64 MHz.
• Ambient operating temperature is 25 °C and VDD=3.3 V.
Table 39. Peripheral current consumption

IDD (Typ)
Peripheral Unit
Scale 1 Scale 2 Scale 3
GPIOA 1.89 1.82 1.64

GPIOB 1.75 1.68 1.52
GPIOC 1.70 1.64 1.48
GPIOD 1.72 1.65 1.48
GPIOE 1.78 1.71 1.55
AHB1 GPIOF 1.68 1.62 1.45 µA/MHz
GPIOG 1.66 1.61 1.44
GPIOH 0.72 0.69 0.63
CRC 0.30 0.30 0.28
(1)
DMA1 1.75N + 3.14 1.66N + 3.00 1.49N + 2.70
(1)
DMA2 1.79N + 3.29 1.71N + 3.14 1.53N + 2.82
RNG 0.72 0.70 0.63
AHB2 USB_OTG_FS 19.26 18.37 16.47 µA/MHz
AES 2.75 2.63 2.36
FSMC 5.42 5.18 4.64
AHB3 µA/MHz
QSPI 10.33 9.86 8.84
104/209 DocID029161 Rev 7

Table 39. Peripheral current consumption (continued)

IDD (Typ)
Peripheral Unit
AHB-APB1 bridge 0.90 0.88 0.81

TIM2 13.08 12.48 11.16
TIM3 9.98 9.50 8.50
TIM4 9.88 9.43 8.44
TIM5 13.14 12.52 11.19
TIM6 1.94 1.86 1.66
TIM7 1.86 1.79 1.56
TIM12 5.56 5.29 4.72
TIM13 3.44 3.29 2.94
TIM14 3.66 3.48 3.09
LPTIM1 7.34 7.00 6.25
WWDG 0.64 0.62 0.53
SPI2/I2S2 3.02 2.88 2.56
SPI3/I2S3 3.06 2.90 2.59
APB1 USART2 3.30 3.14 2.81 µA/MHz
USART3 3.32 3.14 2.81
UART4 3.18 3.02 2.69
UART5 3.26 3.10 2.75
I2C1 3.20 3.05 2.72
I2C2 3.30 3.14 2.81
I2C3 3.26 3.10 2.78
I2CFMP1 5.22 4.98 4.44
CAN1 5.58 5.31 4.75
CAN2 5.14 4.88 4.38
CAN3 5.70 5.43 4.84
PWR 0.90 0.86 0.75
DAC1 2.14 2.05 1.81
UART7 3.08 2.93 2.59
UART8 3.10 2.95 2.63
DocID029161 Rev 7 105/209

175
Table 39. Peripheral current consumption (continued)

IDD (Typ)
Peripheral Unit
AHB-APB2 bridge 0.10 0.11 0.09

TIM1 6.78 6.46 5.80
TIM8 6.94 6.62 5.94
USART1 3.14 3.00 2.69
USART6 3.12 2.98 2.67
UART9 2.89 1.98 1.75
UART10 2.91 2.00 1.77
ADC1 3.45 3.29 2.95
SDIO 3.54 3.37 3.03
SPI1 1.52 1.46 1.31
APB2
SPI4 1.50 1.43 1.28 µA/MHz
SYSCFG 0.58 0.55 0.50
EXT1 0.91 0.86 0.78
TIM9 2.95 2.81 2.53
TIM10 1.88 1.79 1.61
TIM11 1.86 1.77 1.59
SPI5 1.50 1.43 1.30
SAI 2.89 2.75 2.47
DFSDM1 4.43 4.21 3.80
DFSDM2 7.08 6.76 6.05
Bus Matrix 4.06 3.87 3.45
1. N is the number of stream enable (1...8).
6.3.7 Wakeup time from low-power modes

The wakeup times given in Table 40 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PA0/PC0/PC1) pins are used to wakeup from Standby, Stop and Sleep modes.
106/209 DocID029161 Rev 7

Figure 26. Low-power mode wakeup
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All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
DocID029161 Rev 7 107/209

175
Table 40. Low-power mode wakeup timings(1)

Symbol Parameter Conditions Min(1) Typ(1) Max(1) Unit
clk
tWUSLEEP - - 4 6
cycles
Wakeup from Sleep mode
Flash memory in Deep
tWUSLEEPFDSM - - 50.0
power down mode
Main regulator - 12.7 15.0
Main regulator, Flash
memory in Deep power - 104.1 120.0
down mode
Wakeup from Stop mode,
regulator in low power - 20.9 28.0
Wakeup from STOP mode mode(2)
tWUSTOP
Code execution on Flash
Regulator in low power
mode, Flash memory in - 112.5 130.0
Deep power down mode(2)
Regulator in low power
mode low voltage, Flash
- 112.5 130.0 µs
memory in Deep power
down mode
Main regulator with Flash in
Stop mode or Deep power - 4.2 7.0
down(2)
Wakeup from STOP mode
tWUSTOP Wakeup from Stop mode,
code execution on RAM(3)
regulator in low power
- 12.6 20.0
mode and Flash in Stop
mode or Deep power down
Wakeup from Standby
tWUSTDBY - - 328.2 400.0
mode
From Flash_Stop mode - - 11.0
tWUFLASH Wakeup of Flash From Flash Deep power
- - 40.0
down mode
2. The specification is valid for wakeup from regulator in low power mode or low power low voltage mode, since the timing
difference is negligible.
3. For the faster wakeup time for code execution on RAM, the Flash must be in STOP or DeepPower Down mode (see
reference manual RM0430).
6.3.8 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 59. However, the recommended clock input
waveform is shown in Figure 27.
The characteristics given in Table 41 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
108/209 DocID029161 Rev 7

summarized in Table 17.
Table 41. High-speed external user clock characteristics

External user clock source

fHSE_ext 1 - 50 MHz
frequency(1)
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
tw(HSE)
OSC_IN high or low time(1) 5 - -
tw(HSE)
ns
tr(HSE)
OSC_IN rise or fall time(1) - - 10
tf(HSE)
Cin(HSE) OSC_IN input capacitance(1) - 5 - pF
DuCy(HSE) Duty cycle 45 - 55 %
IL OSC_IN Input leakage current VSS ≤VIN ≤VDD - - ±1 µA
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 59. However, the recommended clock input
waveform is shown in Figure 28.
The characteristics given in Table 42 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.
Table 42. Low-speed external user clock characteristics

User External clock source

fLSE_ext - 32.768 1000 kHz
frequency(1)
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage V
VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD
tw(LSE)
OSC32_IN high or low time(1) 450 - -
tf(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time(1) - - 50
tf(LSE)
Cin(LSE) OSC32_IN input capacitance(1) - 5 - pF
DuCy(LSE) Duty cycle 30 - 70 %
IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA
DocID029161 Rev 7 109/209

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Figure 27. High-speed external clock source AC timing diagram
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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 43. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
110/209 DocID029161 Rev 7

Table 43. HSE 4-26 MHz oscillator characteristics(1)

fOSC_IN Oscillator frequency 4 - 26 MHz

RF Feedback resistor - 200 - kΩ
VDD=3.3 V,
ESR= 30 Ω, - 450 -
CL=5 pF @25 MHz
IDD HSE current consumption µA
VDD=3.3 V,
ESR= 30 Ω, - 530 -
CL=10 pF @25 MHz
ACCHSE(2) HSE accuracy - -500 - 500 ppm
Gm_crit_max Maximum critical crystal gm Startup - - 1 mA/V
(3)
tSU(HSE) Startup time VDD is stabilized - 2 - ms
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 29). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 29. Typical application with an 8 MHz crystal
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Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 44. In
the application, the resonator and the load capacitors have to be placed as close as
DocID029161 Rev 7 111/209

175
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
The LSE high-power mode allows to cover a wider range of possible crystals but with a cost
of higher power consumption.
Table 44. LSE oscillator characteristics (fLSE = 32.768 kHz) (1)

RF Feedback resistor - - 18.4 - MΩ

Low-power mode
- - 1
IDD LSE current consumption (default) µA
High-drive mode - - 3
ACCLSE(2) LSE accuracy - -500 - 500 ppm
Startup, low-power
- - 0.56
mode
Gm_crit_max Maximum critical crystal gm µA/V
Startup, high-drive
- - 1.50
mode
tSU(LSE)(3) startup time VDD is stabilized - 2 - s
2. This parameter depends on the crystal used in the application. Refer to the application note AN2867.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is guaranteed by characterization and not tested in
production. It is measured for a standard crystal resonator and it can vary significantly with the crystal
manufacturer.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
For information about the LSE high-power mode, refer to the reference manual RM0383.
Figure 30. Typical application with a 32.768 kHz crystal
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112/209 DocID029161 Rev 7

6.3.9 Internal clock source characteristics

The parameters given in Table 45 and Table 46 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 17.
High-speed internal (HSI) RC oscillator
Table 45. HSI oscillator characteristics (1)

L
fHSI Frequency - - 16 - MHz

HSI user trimming step(2) - - - 1 %
(3)
TA = – 40 to 125 °C –8 - 6.75 %
ACCHSI TA = – 40 to 105 °C(3) –8 - 4.5 %
Accuracy of the HSI oscillator
TA = –10 to 85 °C(3) –4 - 4 %
TA = 25 °C(4) –1 - 1 %
tsu(HSI) (2) HSI oscillator startup time - - 2.2 4 µs
HSI oscillator power
IDD(HSI)(2) - - 60 80 µA
consumption
1. VDD = 3.3 V, TA = –40 to 125 °C unless otherwise specified.
2. Guaranteed by design
3. Based on characterization
4. Factory calibrated, parts not soldered.
Figure 31. ACCHSI versus temperature

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DocID029161 Rev 7 113/209

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Low-speed internal (LSI) RC oscillator
Table 46. LSI oscillator characteristics (1)

Symbol Parameter Min Typ Max Unit
fLSI(2) Frequency 16.1 32.0 47.0 kHz

(3)
tsu(LSI) LSI oscillator startup time - 15.0 40.0 µs
IDD(LSI)(3) LSI oscillator power consumption - 0.4 0.6 µA
1. VDD = 3 V, TA = –40 to 125 °C unless otherwise specified.
Figure 32. ACCLSI versus temperature
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114/209 DocID029161 Rev 7

6.3.10 PLL characteristics

The parameters given in Table 47 and Table 48 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 17.
Table 47. Main PLL characteristics

fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10

fPLLP_OUT PLLP multiplier output clock - 24 - 100
48 MHz PLLQ multiplier
fPLLQ_OUT - - 48 75
output clock MHz
PLLR multiplier output clock
fPLLR_OUT - - - 216
for I2S and SAI
fVCO_OUT PLL VCO output - 100 - 432
PLL lock time VCO freq = 100 MHz 75 - 200
tLOCK µs
VCO freq = 432 MHz 100 - 300
Cycle-to-cycle jitter RMS - 25 -
peak
to - ±150 -
System clock peak
Period Jitter 100 MHz RMS - 15 -
Jitter(3) ps
peak
to - ±200 -
peak
Cycle to cycle at 1 MHz
Bit Time CAN jitter - 330 -
on 1000 samples.
VCO freq = 100 MHz 0.15 0.40
IDD(PLL)(4) PLL power consumption on VDD -
VCO freq = 432 MHz 0.45 0.75
mA
PLL power consumption on VCO freq = 100 MHz 0.30 0.40
IDDA(PLL)(4) -
VDDA VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
3. The use of two PLLs in parallel could degraded the Jitter up to +30%.
DocID029161 Rev 7 115/209

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Table 48. PLLI2S (audio PLL) characteristics

fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10

48 MHz PLLI2SQ
fPLLI2SQ_OUT - - 48 75
multiplier output clock
MHz
PLLI2SR multiplier output clock
fPLLI2SR_OUT - - - 216
for I2S and SAI
fVCO_OUT PLLI2S VCO output - 100 - 432
VCO freq = 100 MHz 75 - 200
tLOCK PLLI2S lock time µs
VCO freq = 432 MHz 100 - 300
Cycle to cycle at RMS - 90 -

12.288 MHz on peak
48 kHz period, to - ±280 -
N=432, R=5 peak
Master I2S clock jitter
(3) Average frequency of
Jitter
12.288 MHz ps
- 90 -
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
WS I2S clock jitter - 400 -
on 1000 samples
PLLI2S power consumption on VCO freq = 100 MHz 0.15 0.40
IDD(PLLI2S)(4) -
VDD VCO freq = 432 MHz 0.45 0.75
mA
PLLI2S power consumption on VCO freq = 100 MHz 0.30 0.40
IDDA(PLLI2S)(4) -
VDDA VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
3. Value given with main PLL running.
116/209 DocID029161 Rev 7

6.3.11 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 55: EMI characteristics for LQFP144). It is available only on the
main PLL.
Table 49. SSCG parameter constraints

Symbol Parameter Min Typ Max(1) Unit
fMod Modulation frequency - - 10 kHz

md Peak modulation depth 0.25 - 2 %
MODEPER * INCSTEP (Modulation period) * (Increment Step) - - 215 -1 -
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round [ f PLL_IN ⁄ ( 4 × f Mod ) ]
fPLL_IN and fMod must be expressed in Hz.

As an example:
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
6 3
MODEPER = round [ 10 ⁄ ( 4 × 10 ) ] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
15
INCSTEP = round [ ( ( 2 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ]
fVCO_OUT must be expressed in MHz.

With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
15
INCSTEP = round [ ( ( 2 – 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
15
md quantized % = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2 – 1 ) × PLLN )
As a result:
15
md quantized % = ( 250 × 126 × 100 × 5 ) ⁄ ( ( 2 – 1 ) × 240 ) = 2.002%(peak)
DocID029161 Rev 7 117/209

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Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.
Figure 33. PLL output clock waveforms in center spread mode
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6.3.12 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 125 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 50. Flash memory characteristics

Write / Erase 8-bit mode, VDD = 1.7 V - 5 -

IDD Supply current Write / Erase 16-bit mode, VDD = 2.1 V - 8 - mA
Write / Erase 32-bit mode, VDD = 3.3 V - 12 -
118/209 DocID029161 Rev 7

Table 51. Flash memory programming

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Program/erase parallelism
tprog Word programming time - 16 100(2) µs
(PSIZE) = x 8/16/32
- 400 800
(PSIZE) = x 8
tERASE16KB Sector (16 KB) erase time - 300 600 ms
(PSIZE) = x 16
- 250 500
(PSIZE) = x 32
- 1200 2400
(PSIZE) = x 8
tERASE64KB Sector (64 KB) erase time - 700 1400 ms
(PSIZE) = x 16
- 550 1100
(PSIZE) = x 32
- 2 4
(PSIZE) = x 8
tERASE128KB Sector (128 KB) erase time - 1.3 2.6 s
(PSIZE) = x 16
- 1 2
(PSIZE) = x 32
- 24 48
(PSIZE) = x 8
tME Mass erase time - 15 30 s
(PSIZE) = x 16
- 11 22
(PSIZE) = x 32
32-bit program operation 2.7 - 3.6 V
Vprog Programming voltage 16-bit program operation 2.1 - 3.6 V
8-bit program operation 1.7 - 3.6 V
2. The maximum programming time is measured after 100K erase operations.
DocID029161 Rev 7 119/209

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Table 52. Flash memory programming with VPP voltage

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
tprog Double word programming - 16 100(2) µs

tERASE16KB Sector (16 KB) erase time TA = 0 to +40 °C - 230 -
tERASE64KB Sector (64 KB) erase time VDD = 3.3 V - 490 - ms
tERASE128KB Sector (128 KB) erase time VPP = 8.5 V - 875 -
tME Mass erase time - 9.8 - s
Vprog Programming voltage - 2.7 - 3.6 V
VPP VPP voltage range - 7 - 9 V
Minimum current sunk on
IPP - 10 - - mA
the VPP pin
Cumulative time during
tVPP(3) - - - 1 hour
which VPP is applied
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.
Table 53. Flash memory endurance and data retention

Value
Min(1)
TA = –40 to +85 °C (temp. range 6)

NEND Endurance TA = –40 to +105 °C (temp. range 7) 10 kcycles
TA = –40 to +125 °C (temp. range 3)
1 kcycle(2) at TA = 85 °C 30
1 kcycle(2) at TA = 105 °C 10
tRET Data retention Years
1 kcycle(2) at TA = 125 °C 3
10 kcycle(2) at TA = 55 °C 20
2. Cycling performed over the whole temperature range.
120/209 DocID029161 Rev 7

6.3.13 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 55. They are based on the EMS levels and classes
defined in application note AN1709.
Table 54. EMS characteristics for LQFP144 package

Level/
Class
VDD = 3.3 V, LQFP144

Voltage limits to be applied on any I/O pin
VFESD TA = +25 °C, fHCLK = 100 MHz, 1B
to induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, LQFP144

VEFTB applied through 100 pF on VDD and VSS TA = +25 °C, fHCLK = 100 MHz, 3B
pins to induce a functional disturbance conforms to IEC 61000-4-4
When the application is exposed to a noisy environment, it is recommended to avoid pin

exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1,
PA2, on LQFP144 packages and PDR_ON on WLCSP81.
As a consequence, it is recommended to add a serial resistor (1 kΩ maximum) located as
close as possible to the MCU to the pins exposed to noise (connected to tracks longer than
50 mm on PCB).
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
DocID029161 Rev 7 121/209

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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with IEC61967-2
standard which specifies the test board and the pin loading.
Table 55. EMI characteristics for LQFP144

Max vs.
Monitored [fHSE/fCPU]
frequency band
8/100 MHz
0.1 to 30 MHz 13
VDD = 3.6 V, TA = 25 °C, LQFP144 30 to 130 MHz 21
package, conforming to IEC 61967-2, dBµV
SEMI Peak level 130 MHz to 1 GHz 25
EEMBC, ART ON, all peripheral clocks
enabled, clock dithering disabled. 1 GHz to 2 GHz 19
EMI Level 4 -
6.3.14 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
122/209 DocID029161 Rev 7

Table 56. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum Unit

value(1)
Electrostatic
VESD(HBM) discharge voltage TA = +25 °C conforming to JESD22-A114 2 2000
(human body model)
TA = +25 °C conforming to ANSI/ESD STM5.3.1,
V
Electrostatic UFBGA144, UFBGA100, LQFP144, LQFP100, 3 250
VESD(CDM) discharge voltage WLCSP81, LQFP64
(charge device model) T = +25 °C conforming to ANSI/ESD STM5.3.1,
A 4 500
UFQFPN48
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
Table 57. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA = +125 °C conforming to JESD78A II level A
6.3.15 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins
(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator
frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 58.
DocID029161 Rev 7 123/209

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Table 58. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on BOOT0, PDR_ON, BYPASS_REG -0 0

Injected current on NRST -0 NA
Injected current on PE6, PC13, PC14, PC15, PF0, PF1,
IINJ -0 NA mA
PF2, PC0, PC1, PC2, PC3
Injected current on any other FT and FTf pins -5 NA
Injected current on any other pins -5 +5
1. NA = not applicable.
Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.16 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL
compliant.
Table 59. I/O static characteristics

FT, TTa, TC and NRST I/O input

1.7 V≤VDD≤3.6 V - - 0.3VDD(1)
low level voltage
1.75 V≤VDD ≤3.6 V,
VIL - - V
BOOT0 I/O input low level -40 °C≤TA ≤125 °C
0.1VDD+0.1(2)
voltage 1.7 V≤VDD ≤3.6 V,
- -
0 °C≤TA ≤125 °C
1.7 V≤VDD≤3.6 V 0.7VDD(1) - -
high level voltage(6)
1.75 V≤VDD ≤3.6 V,
VIH V
BOOT0 I/O input high level -40 °C≤TA ≤125 °C
0.17VDD+0.7(2) - -
voltage 1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤125 °C
1.7 V≤VDD≤3.6 V 10% VDD(2)(4) - -
hysteresis
1.75 V≤VDD ≤3.6 V,
VHYS(3) V
-40 °C≤TA ≤125 °C
BOOT0 I/O input hysteresis 0.1 - -
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤125 °C
124/209 DocID029161 Rev 7

Table 59. I/O static characteristics (continued)

(5)
I/O input leakage current VSS ≤VIN ≤VDD - - ±1
Ilkg I/O FT/TC input leakage current µA
(6) VIN = 5 V - - 3
All pins
except for
Weak pull-up VIN = VSS 30 40 50
PA10
RPU equivalent (OTG_FS_ID)
resistor(7)
PA10
- 7 10 14
(OTG_FS_ID)
kΩ
All pins
except for
Weak pull-down VIN = VDD 30 40 50
PA10
RPD equivalent (OTG_FS_ID)
resistor(8)
PA10
- 7 10 14
(OTG_FS_ID)
CIO I/O pin capacitance - - 5 - pF
1. Guaranteed by test in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
4. With a minimum of 200 mV.
5. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 58: I/O
current injection susceptibility
6. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 58: I/O current injection
susceptibility
7. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimum (~10% order).
8. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT and TC I/Os is shown in Figure 35.
DocID029161 Rev 7 125/209

175
Figure 35. FT/TC I/O input characteristics

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can
sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed
should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 15).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 15).
Output voltage levels

performed under ambient temperature and VDD supply voltage conditions summarized in
Table 17. All I/Os are CMOS and TTL compliant.
126/209 DocID029161 Rev 7

Table 60. Output voltage characteristics

VOL(1) Output low level voltage for an I/O pin CMOS port(2) - 0.4
IIO = +8 mA V
VOH(3) Output high level voltage for an I/O pin VDD–0.4 -
2.7 V ≤VDD ≤3.6 V
VOL (1) Output low level voltage for an I/O pin TTL port(2) - 0.4
IIO =+8 mA V
VOH (3) Output high level voltage for an I/O pin
2.7 V ≤VDD ≤3.6 V
2.4 -
VOL(1) Output low level voltage for an I/O pin IIO = + 20 mA - 1.3(4)
V
VOH(3) Output high level voltage for an I/O pin 2.7 V ≤VDD ≤3.6 V VDD–1.3(4) -
VOL(1) Output low level voltage for an I/O pin IIO = + 6 mA - 0.4(4)
V
VOL(1) Output low level voltage for an I/O pin IIO = +4 mA - 0.4(5)
V
Output low level voltage for an FTf I/O pin in IIO = + 20 mA

VOLFM(1) - 0.4 V
FM+ mode 2.7 V ≤ VDD ≤ 3.6 V
Output low level voltage for an FTf I/O pin in IIO = + 10 mA
VOLFM(1) - 0.4 V
FM+ mode 1.8 V ≤ VDD ≤ 3.6 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15. and the sum of
IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 15 and the sum
of IIO (I/O ports and control pins) must not exceed IVDD.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 36 and
Table 61, respectively.
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17.
DocID029161 Rev 7 127/209

175
Table 61. I/O AC characteristics(1)(2)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)
CL = 50 pF, VDD ≥ 2.70 V - - 4

CL = 50 pF, VDD≥ 1.7 V - - 2
fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD ≥ 2.70 V - - 8
00
CL = 10 pF, VDD ≥ 1.7 V - - 4
Output high to low level
tf(IO)out/
fall time and output low to CL = 50 pF, VDD = 1.7 V to 3.6 V - - 100 ns
tr(IO)out
high level rise time
CL = 50 pF, VDD ≥ 2.70 V - - 25
CL = 50 pF, VDD ≥ 1.7 V - - 12.5
CL = 10 pF, VDD ≥ 2.70 V - - 50
CL = 10 pF, VDD ≥ 1.7 V - - 20
01
CL = 50 pF, VDD ≥2.7 V - - 10
Output high to low level CL = 50 pF, VDD ≥ 1.7 V - - 20
tf(IO)out/
fall time and output low to ns
tr(IO)out CL = 10 pF, VDD ≥ 2.70 V - - 6
CL = 10 pF, VDD ≥ 1.7 V - - 10
CL = 40 pF, VDD ≥ 2.70 V - - 50(4)
CL = 40 pF, VDD ≥ 1.7 V - - 25
CL = 10 pF, VDD ≥ 2.70 V - - 100(4)
CL = 10 pF, VDD ≥ 1.7 V - - 50(4)
10
CL = 40 pF, VDD≥ 2.70 V - - 6
Output high to low level CL = 40 pF, VDD≥ 1.7 V - - 10
tf(IO)out/
tr(IO)out CL = 10 pF, VDD≥ 2.70 V - - 4
CL = 10 pF, VDD≥ 1.7 V - - 6
Fmax(IO)ou CL = 30 pF, VDD ≥ 2.70 V - - 100(4)

Maximum frequency(3) MHz
t CL = 30 pF, VDD ≥ 1.7 V - - 50(4)
CL = 30 pF, VDD ≥ 2.70 V - - 4
11
Output high to low level CL = 30 pF, VDD ≥ 1.7 V - - 6
tf(IO)out/
tr(IO)out CL = 10 pF, VDD≥ 2.70 V - - 2.5
CL = 10 pF, VDD≥ 1.7 V - - 4
Fmax Maximum frequency - - 1 MHz
FM+ Output high to low level CL = 50 pF, 1.6 ≤ VDD ≤ 3.6 V
Tf - - 5 ns
fall time
Pulse width of external
- tEXTIpw signals detected by the - 10 - - ns
EXTI controller
128/209 DocID029161 Rev 7


2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 36.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Figure 36. I/O AC characteristics definition

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6.3.17 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 59).
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 17. Refer to Table 59: I/O static characteristics for the values of VIH and VIL for
NRST pin.
Table 62. NRST pin characteristics

Weak pull-up equivalent

RPU VIN = VSS 30 40 50 kΩ
resistor(1)
VF(NRST)(2) NRST Input filtered pulse - - - 100 ns
VNF(NRST)(2) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns
Internal Reset
TNRST_OUT Generated reset pulse duration 20 - - µs
source
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
DocID029161 Rev 7 129/209

175
Figure 37. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 62. Otherwise the reset is not taken into account by the device.
6.3.18 TIM timer characteristics

The parameters given in Table 63 are guaranteed by design.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 63. TIMx characteristics(1)(2)

Symbol Parameter Conditions(3) Min Max Unit
AHB/APBx prescaler=1 1 - tTIMxCLK

or 2 or 4, fTIMxCLK =
100 MHz 11.9 - ns
tres(TIM) Timer resolution time
AHB/APBx prescaler>4, 1 - tTIMxCLK
fTIMxCLK = 100 MHz 11.9 - ns
Timer external clock 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 f
TIMxCLK = 100 MHz 0 50 MHz
ResTIM Timer resolution - 16/32 bit
16-bit counter clock
tCOUNTER period when internal clock fTIMxCLK = 100 MHz 0.0119 780 µs
is selected
65536 ×
- - tTIMxCLK
Maximum possible count 65536
tMAX_COUNT
with 32-bit counter
fTIMxCLK = 100 MHz - 51.1 S
1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.
3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE
bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise
TIMxCLK >= 4x PCLKx.
130/209 DocID029161 Rev 7

6.3.19 Communications interfaces

I2C interface characteristics
The I2C interface meets the requirements of the standard I2C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table 64. Refer also to Section 6.3.16: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
The I2C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400
kHz). The I2C bus frequency can be increased up to 1 MHz. For more details about the
complete solution, contact your local ST sales representative.
Table 64. I2C characteristics

Standard mode I2C(1)(2) Fast mode I2C(1)(2)
Symbol Parameter Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.70 - 1.30 -

tw(SCLH) SCL clock high time 4.0 - 0.60 -
tsu(SDA) SDA setup time 0.25 - 0.10 -
th(SDA) SDA data hold time 0 - 0 -
tv(SDA,ACK) SDA data hold time - 3.45(3) - 0.90(4)
tr(SDA)
SDA and SCL rise time - 0.100 - 0.30
tr(SCL)
tf(SDA)
SDA and SCL fall time - 0.30 - 0.30
tf(SCL) µs
th(STA) Start condition hold time 4 - 0.6 -
Repeated Start condition setup
tsu(STA) 4.7 - 0.6 -
time
tsu(STO) Stop condition setup time 4 - 0.60 -
Stop to Start condition time (bus
tw(STO:STA) 4.70 - 1.3 -
free)
Pulse width of the spikes that are
tSP suppressed by the analog filter - - 0.05 0.10(5)
for standard fast mode
Cb Capacitive load for each bus line - 400 - 400 pF
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode
I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock.
3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region
of the falling edge of SCL.
4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.
5. The minimum width of the spikes filtered by the analog filter is above tSP (max)
DocID029161 Rev 7 131/209

175
Figure 38. I2C bus AC waveforms and measurement circuit

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1. RS = series protection resistor.

2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
Table 65. SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400 0x8019
300 0x8021
200 0x8032
100 0x0096
50 0x012C
20 0x02EE
1. RP = External pull-up resistance, fSCL = I2 C speed
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external
components used to design the application.
132/209 DocID029161 Rev 7

FMPI2C characteristics
The following table presents FMPI2C characteristics.
Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output
function characteristics (SDA and SCL).
Table 66. FMPI2C characteristics(1)

Standard mode Fast mode Fast+ mode
Parameter Unit
Min Max Min Max Min Max
fFMPI2CC FMPI2CCLK frequency 2 - 8 - 18 -
tw(SCLL) SCL clock low time 4.7 - 1.3 - 0.5 -

tw(SCLH) SCL clock high time 4.0 - 0.6 - 0.26 -
tsu(SDA) SDA setup time 0.25 - 0.10 - 0.05 -
tH(SDA) SDA data hold time 0 - 0 - 0 -
tv(SDA,ACK) Data, ACK valid time - 3.45 - 0.9 - 0.45
tr(SDA)
SDA and SCL rise time - 1.0 - 0.30 - 0.12
tr(SCL)
tf(SDA)
SDA and SCL fall time - 0.30 - 0.30 -0 0.12 µs
tf(SCL)
th(STA) Start condition hold time 4 - 0.6 - 0.26 -
Repeated Start condition
tsu(STA) 4.7 - 0.6 - 0.26 -
setup time
tsu(STO) Stop condition setup time 4 - 0.6 - 0.26 -
Stop to Start condition time

tw(STO:STA) 4.7 - 1.3 - 0.5 -
(bus free)
Pulse width of the spikes that

are suppressed by the
tSP - - 0.05 0.1 0.05 0.1
analog filter for standard and
fast mode
Capacitive load for each bus
Cb - 400 - 400 - 550(2) pF
Line
1. Based on characterization results.
2. Can be limited. Maximum supported value can be retrieved by referring to the following formulas:
tr(SDA/SCL) = 0.8473 x Rp x Cload
Rp(min) = (VDD -VOL(max)) / IOL(max)
DocID029161 Rev 7 133/209

175
Figure 39. FMPI2C timing diagram and measurement circuit

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134/209 DocID029161 Rev 7

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 67 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 17, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 67. SPI dynamic characteristics(1)

Master mode,
SPI1,4,5 - - 50
3.0 V < VDD < 3.6 V
Master mode,
SPI1,4,5 - - 42
2.7 V < VDD < 3.6 V
Master mode
SPI1,4,5 - - 25
1.7 V < VDD < 3.6 V
Master transmitter mode
SPI1,4,5 - - 50
fSCK 1.71 V < VDD < 3.6 V
SPI clock frequency MHz
1/tc(SCK)
Slave receiver mode
SPI1,4,5 - - 50
1.71 V < VDD < 3.6 V
Slave mode transmitter/full duplex
SPI1,4,5 - - 40(2)
2.7 V < VDD < 3.6 V
Slave mode transmitter/full duplex
SPI1,4,5 - - 26
1.71 V < VDD < 3.6 V
Master & Slave mode,
SPI2/3 - - 25
1.71 V < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*TPCLK - - ns
th(NSS) NSS hold time Slave mode, SPI presc = 2 2*TPCLK - - ns
tw(SCKH)
SCK high and low time Master mode TPCLK - 2 TPCLK TPCLK +2 ns
tw(SCKL)
tsu(MI) Master mode 2.5 - -
Data input setup time ns
tsu(SI) Slave mode 4.5 - -
th(MI) Master mode 5 - -
Data input hold time ns
th(SI) Slave mode 2 - -
DocID029161 Rev 7 135/209

175
Table 67. SPI dynamic characteristics(1) (continued)

ta(SO) Data output access time Slave mode 7 - 21 ns

tdis(SO) Data output disable time Slave mode 5 - 12 ns
Slave mode (after enable edge),
- 7 12.5
2.7 V < VDD < 3.6 V
tv(SO)
Data output valid time Slave mode (after enable edge), ns
- 7 19
1.71 V < VDD < 3.6 V
tv(MO) Master mode - 2 3
Slave mode
th(SO) 6 - -
Data output hold time 1.71 V < VDD < 3.6 V ns
th(MO) Master mode 1.5 - -
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
Figure 40. SPI timing diagram - slave mode and CPHA = 0
136/209 DocID029161 Rev 7

Figure 41. SPI timing diagram - slave mode and CPHA = 1
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DocID029161 Rev 7 137/209

175
I2S interface characteristics

Unless otherwise specified, the parameters given in Table 68 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
function characteristics (CK, SD, WS).
Table 68. I2S dynamic characteristics(1)

fMCK I2S Main clock output - 256 * 8K 256 * Fs(2) MHz

Master data: 32 bits - 64 * Fs
fCK I2S clock frequency MHz
Slave data: 32 bits - 64 * Fs
DCK I2S clock frequency duty cycle Slave receiver 30 70 %
tv(WS) WS valid time Master mode - 3.5
th(WS) WS hold time Master mode 1.5 -
tsu(WS) WS setup time Slave mode 2.5 -
th(WS) WS hold time Slave mode 0.5 -
tsu(SD_MR) Master receiver 3 -
Data input setup time
tsu(SD_SR) Slave receiver 2.5 -
ns
th(SD_MR) Master receiver 5 -
Data input hold time
th(SD_SR) Slave receiver 1.5 -
tv(SD_ST) Slave transmitter (after enable edge) - 15
Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 6
th(SD_ST) Slave transmitter (after enable edge) 3.5 -
Data output hold time
th(SD_MT) Master transmitter (after enable edge) 1.5 -
2. The maximum value of 256xFs is 50 MHz (APB1 maximum frequency).
Note: Refer to the I2S section of RM0430 reference manual for more details on the sampling
frequency (FS).
fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these
parameters might be slightly impacted by the source clock precision. DCK depends mainly
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS
maximum value is supported for each mode/condition.
138/209 DocID029161 Rev 7

Figure 43. I2S slave timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 44. I2S master timing diagram (Philips protocol)
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
DocID029161 Rev 7 139/209

175
SAI characteristics
Unless otherwise specified, the parameters given in Table 69 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 17, with the following configuration:
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5VDD
function characteristics (SCK,SD,WS).
Table 69. SAI characteristics(1)

fMCKL SAI Main clock output - 256 * 8K 256 * Fs(2) MHz

Master data: 32 bits - 128 * Fs
FSCK SAI clock frequency MHz
Slave data: 32 bits - 128 * Fs
Master mode
- 19
2.7 V <= VDD <= 3.6 V
tv(FS) FS valid time
Master mode
- 28
1.71 V <= VDD <= 3.6 V
Master mode 13 -
th(FS) FS hold time
Slave mode 0 -
tsu(FS) FS setup time Slave mode 3 -
tsu(SD_ A_MR) Master receiver 0.5 -
tsu(SD_B_SR) Slave receiver 1.5 -
th(SD_ A_MR) Master receiver 5 -
th(SD_B_SR) Slave receiver 2.5 -
Slave transmitter (after enable edge)
- 15
2.7 V <= VDD <= 3.6 V
tv(SD_B_ST) Data output valid time
Slave transmitter (after enable edge)
- 28
1.71 V <= VDD <= 3.6 V
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 10 -
Master transmitter (after enable edge)
- 15
2.7 V <= VDD <= 3.6 V
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
- 29
1.71 V <= VDD <= 3.6 V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 13 -
2. 256 * Fs maximum corresponds to 45 MHz (APB2 maximum frequency)
140/209 DocID029161 Rev 7

Figure 45. SAI master timing waveforms

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Figure 46. SAI slave timing waveforms
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3!)?3#+?8
TW#+(?8 TW#+,?8 TH&3
3!)?&3?8
INPUT TSU&3 TV3$?34 TH3$?34
3!)?3$?8
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TRANSMIT
TSU3$?32 TH3$?32
3!)?3$?8 3LOT N
RECEIVE
-36
DocID029161 Rev 7 141/209

175
QSPI interface characteristics

Unless otherwise specified, the parameters given in the following tables for QSPI are
derived from tests performed under the ambient temperature, fAHB frequency and VDD
• Capacitive load C=20pF
function characteristics.
Table 70. QSPI dynamic characteristics in SDR mode(1)

2.7 V < VDD < 3.6 V

- - 100
fSCK Cload = 20 pF
QSPI clock frequency MHz
1/tc(SCK) 1.71 V < VDD < 3.6 V
- - 80
Cload = 15 pF
tw(CKH) t(CK) / 2 - 1 - t(CK) / 2
QSPI clock high and low -
tw(CKL) t(CK) / 2 - t(CK) / 2 + 1
ts(IN) Data input setup time - 1.5 - -
th(IN) Data input hold time - 3 - - ns
2.7 V < VDD < 3.6 V - 0.5 1
tv(OUT) Data output valid time
1.71 V < VDD < 3.6 V - 0.5 3
th(OUT) Data output hold time - 0 - 0
Table 71. QSPI dynamic characteristics in DDR mode(1)

2.7 V < VDD < 3.6 V

- - 80
fSCK Cload = 20 pF
QSPI clock frequency MHz
1/tc(SCK) 1.71 V< VDD < 3.6 V
- - 70
Cload = 15 pF
142/209 DocID029161 Rev 7

Table 71. QSPI dynamic characteristics in DDR mode(1) (continued)

tw(CKH) t(CK) / 2 - 1 - t(CK) / 2

QSPI clock high and low time -
tw(CKL) t(CK) / 2 - t(CK) / 2 + 1
tsr(IN), 2.7 V < VDD < 3.6 V 0.5 - -

tsf(IN) 1.71 V < VDD < 3.6 V 0.5 - -
thr(IN), 2.7 V<VDD<3.6 V 2 - -

thf(IN) 1.71 V<VDD<3.6 V 2 - -
tvr(OUT), 2.7 V<VDD<3.6 V - 8.5 9

Data output valid time
tvf(OUT) 1.71 V<VDD<3.6 V - 8.5 11.5
thr(OUT),
Data output hold time - 7.5 - -
thf(OUT)
USB OTG full speed (FS) characteristics

This interface is present in USB OTG FS controller.
Table 72. USB OTG FS startup time

Symbol Parameter Max Unit
tSTARTUP(1) USB OTG FS transceiver startup time 1 µs

Table 73. USB OTG FS DC electrical characteristics

Symbol Parameter Conditions Min.(1) Typ. Max.(1) Unit
USB OTG FS operating

VDD 3.0(2) - 3.6 V
voltage
VDI(3) Differential input sensitivity I(USB_FS_DP/DM) 0.2 - -
Input
levels Differential common mode
VCM(3) Includes VDI range 0.8 - 2.5
range V
Single ended receiver
VSE(3) 1.3 - 2.0
threshold
Output VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3
V
levels VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
PA11, PA12
17 21 24
RPD (USB_FS_DM/DP) VIN = VDD
PA9 (OTG_FS_VBUS) 0.65 1.1 2.0
kΩ
PA11, PA12
VIN = VSS 1.5 1.8 2.1
RPU (USB_FS_DM/DP)
PA9 (OTG_FS_VBUS) VIN = VSS 0.25 0.37 0.55
1. All the voltages are measured from the local ground potential.
DocID029161 Rev 7 143/209

175
2. The USB OTG FS functionality is ensured down to 2.7 V but not the full USB full speed electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
4. RL is the load connected on the USB OTG FS drivers.
Note: When VBUS sensing feature is enabled, PA9 should be left at their default state (floating
input), not as alternate function. A typical 200 µA current consumption of the embedded
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 when the feature is enabled.
Figure 47. USB OTG FS timings: definition of data signal rise and fall time
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Table 74. USB OTG FS electrical characteristics(1)

Driver characteristics
tr Rise time(2) CL = 50 pF 4 20 ns
tf Fall time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf 90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V
2. Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification -
Chapter 7 (version 2.0).
CAN (controller area network) interface

function characteristics (CANx_TX and CANx_RX).
144/209 DocID029161 Rev 7

6.3.20 12-bit ADC characteristics

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 17.
Table 75. ADC characteristics

VDDA (1)
Power supply 1.7 - 3.6
VDDA −VREF+ < 1.2 V
VREF+ Positive reference voltage 1.7(1) - VDDA V
VREF- Negative reference voltage - - 0 -
(1)
VDDA = 1.7 to 2.4 V 0.6 15 18 MHz
fADC ADC clock frequency
VDDA = 2.4 to 3.6 V 0.6 30 36 MHz
fADC = 30 MHz,
- - 1764 kHz
fTRIG(2) External trigger frequency 12-bit resolution
- - - 17 1/fADC
0 (VSSA or VREF-
VAIN Conversion voltage range(3) - - VREF+ V
tied to ground)
See Equation 1 for
RAIN(2) External input impedance - - 50 kΩ
details
RADC(2)(4) Sampling switch resistance - - - 6 kΩ
Internal sample and hold
CADC(2) - - 4 7 pF
capacitor
Injection trigger conversion fADC = 30 MHz - - 0.100 µs

tlat(2)
latency - - - 3(5) 1/fADC
Regular trigger conversion fADC = 30 MHz - - 0.067 µs

tlatr(2)
latency - - - 2(5) 1/fADC
fADC = 30 MHz 0.100 - 16 µs
tS(2) Sampling time
- 3 - 480 1/fADC
tSTAB(2) Power-up time - - 2 3 µs
fADC = 30 MHz
0.50 - 16.40 µs
12-bit resolution
fADC = 30 MHz
0.43 - 16.34 µs
10-bit resolution
Total conversion time (including fADC = 30 MHz
tCONV(2) 0.37 - 16.27 µs
sampling time) 8-bit resolution
fADC = 30 MHz
0.30 - 16.20 µs
6-bit resolution
9 to 492 (tS for sampling +n-bit resolution for successive
1/fADC
approximation)
DocID029161 Rev 7 145/209

175
Table 75. ADC characteristics (continued)

Sampling rate
12-bit resolution
fS(2) (fADC = 30 MHz, and - - 2 Msps
Single ADC
tS = 3 ADC cycles)
ADC VREF DC current

IVREF+(2) consumption in conversion - - 300 500 µA
mode
ADC VDDA DC current
IVDDA(2) consumption in conversion - - 1.6 1.8 mA
mode
1. VDDA minimum value of 1.7 V is possible with the use of an external power supply supervisor (refer to Section 3.17.2:
Internal reset OFF).
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 75.
Equation 1: RAIN max formula

( k – 0.5 )
R AIN - – R ADC
= ---------------------------------------------------------------
N+2
f ADC × C ADC × ln ( 2 )
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
Table 76. ADC accuracy at fADC = 18 MHz(1)

Symbol Parameter Test conditions Typ Max(2) Unit
ET Total unadjusted error ±3 ±4

fADC =18 MHz
EO Offset error ±2 ±3
VDDA = 1.7 to 3.6 V
LSB
EG Gain error VREF = 1.7 to 3.6 V ±1 ±3
ED Differential linearity error VDDA −VREF < 1.2 V ±1 ±2
EL Integral linearity error ±2 ±3
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
146/209 DocID029161 Rev 7



fADC = 30 MHz,
EO Offset error ±1.5 ±2.5
RAIN < 10 kΩ,
EG Gain error VDDA = 2.4 to 3.6 V, ±1.5 ±4 LSB
VREF = 1.7 to 3.6 V,
ED Differential linearity error ±1 ±2
VDDA −VREF < 1.2 V
EL Integral linearity error ±1.5 ±3


fADC =36 MHz,
EO Offset error ±2 ±3
VDDA = 2.4 to 3.6 V,
EG Gain error ±3 ±6 LSB
VREF = 1.7 to 3.6 V
ED Differential linearity error VDDA −VREF < 1.2 V ±2 ±3
EL Integral linearity error ±3 ±6
Table 79. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit
ENOB Effective number of bits 10.3 10.4 - bits

fADC =18 MHz
SINAD Signal-to-noise and distortion ratio VDDA = VREF+= 1.7 V 64 64.2 -
SNR Signal-to-noise ratio Input Frequency = 20 kHz 64 65 - dB
Temperature = 25 °C
THD Total harmonic distortion - -72 -67
Table 80. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit
ENOB Effective number of bits 10.6 10.8 - bits

fADC = 36 MHz
SINAD Signal-to noise and distortion ratio VDDA = VREF+ = 3.3 V 66 67 -
SNR Signal-to noise ratio Input Frequency = 20 kHz 64 68 - dB
Temperature = 25 °C
THD Total harmonic distortion - -72 -70
DocID029161 Rev 7 147/209

175
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.16 does not affect the ADC accuracy.
Figure 48. ADC accuracy characteristics
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1. See also Table 77.

2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
148/209 DocID029161 Rev 7

Figure 49. Typical connection diagram using the ADC
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1. Refer to Table 75 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
DocID029161 Rev 7 149/209

175
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 50 or Figure 51,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA)
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1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When
VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA.
150/209 DocID029161 Rev 7

Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA)
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1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When
VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA.
6.3.21 Temperature sensor characteristics
Table 81. Temperature sensor characteristics

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

(1)
Avg_Slope Average slope - 2.5 - mV/°C
V25(1) Voltage at 25 °C - 0.76 - V
tSTART(2) Startup time - 6 10 µs
TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs
Table 82. Temperature sensor calibration values

Symbol Parameter Memory address
TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D
TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F
DocID029161 Rev 7 151/209

175
6.3.22 VBAT monitoring characteristics
Table 83. VBAT monitoring characteristics

R Resistor bridge for VBAT - 50 - KΩ

Q Ratio on VBAT measurement - 4 -
(1)
Er Error on Q –1 - +1 %
ADC sampling time when reading the VBAT
TS_vbat(2)(2) 5 - - µs
1 mV accuracy
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.23 Embedded reference voltage

The parameters given in Table 84 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.
Table 84. Embedded internal reference voltage

VREFINT Internal reference voltage –40 °C < TA < +125 °C 1.18 1.21 1.24 V
ADC sampling time when reading the
TS_vrefint(1) - 10 - - µs
internal reference voltage
Internal reference voltage spread over the
VRERINT_s(2) VDD = 3V ± 10mV - 3 5 mV
temperature range
TCoeff(2) Temperature coefficient - - 30 50 ppm/°C
tSTART(2) Startup time - - 6 10 µs
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design
Table 85. Internal reference voltage calibration values

Symbol Parameter Memory address
Raw data acquired at temperature of

VREFIN_CAL 0x1FFF 7A2A - 0x1FFF 7A2B
30 °C VDDA = 3.3 V
152/209 DocID029161 Rev 7

6.3.24 DAC electrical characteristics
Table 86. DAC characteristics

Symbol Parameter Conditions Min Typ Max Unit Comments
Analog supply
VDDA - 1.7(1) - 3.6 V
voltage
Reference supply
VREF+ - 1.7(1) - 3.6 V VREF+ ≤VDDA
voltage
VSSA Ground - 0 - 0 V -
RLOAD
connected 5 - - kΩ -
DAC to VSSA
RLOAD(2) Resistive load output
buffer ON RLOAD
connected 25 - - kΩ -
to VDDA
When the buffer is OFF, the
Impedance output Minimum resistive load between
RO(2) - - - 15 kΩ
with buffer OFF DAC_OUT and VSS to have a 1%
accuracy is 1.5 MΩ
Maximum capacitive load at
CLOAD(2) Capacitive load - - - 50 pF DAC_OUT pin (when the buffer is
ON).
Lower DAC_OUT It gives the maximum output

DAC_OUT
voltage with buffer - 0.2 - - V excursion of the DAC.
min(2)
ON It corresponds to 12-bit input
Higher DAC_OUT code (0x0E0) to (0xF1C) at
DAC_OUT VDDA VREF+ = 3.6 V and (0x1C7) to
(2) voltage with buffer - - - V
max − 0.2 (0xE38) at VREF+ = 1.7 V
ON
Lower DAC_OUT
DAC_OUT
(2) voltage with buffer - - 0.5 - mV
min
OFF It gives the maximum output
Higher DAC_OUT VREF+ excursion of the DAC.
DAC_OUT
voltage with buffer - - - − V
max(2)
OFF 1LSB
With no load, worst code (0x800)
DAC DC VREF - - 170 240 at VREF+ = 3.6 V in terms of DC
current consumption on the inputs
IVREF+(4) consumption in µA
quiescent mode With no load, worst code (0xF1C)
(Standby mode) - - 50 75 at VREF+ = 3.6 V in terms of DC
consumption on the inputs
With no load, middle code
DAC DC VDDA - - 280 380 µA
(0x800) on the inputs
current
IDDA(4) With no load, worst code (0xF1C)
consumption in
quiescent mode(3) - - 475 625 µA at VREF+ = 3.6 V in terms of DC
consumption on the inputs
DocID029161 Rev 7 153/209

175
Table 86. DAC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit Comments
Differential non Given for the DAC in 10-bit

linearity Difference - - - ±0.5 LSB
configuration.
DNL(4) between two
consecutive code- Given for the DAC in 12-bit
1LSB) - - - ±2 LSB
configuration.
Integral non Given for the DAC in 10-bit
- - - ±1 LSB
linearity (difference configuration.
between measured
value at Code i and
INL(4) the value at Code i
on a line drawn Given for the DAC in 12-bit
- - - ±4 LSB
between Code 0 configuration.
and last Code
1023)
Given for the DAC in 12-bit
Offset error - - - ±10 mV
configuration
(difference between
(4) measured value at Given for the DAC in 10-bit at
Offset - - - ±3 LSB
Code (0x800) and VREF+ = 3.6 V
the ideal value =
Given for the DAC in 12-bit at
VREF+/2) - - - ±12 LSB
VREF+ = 3.6 V
Gain Given for the DAC in 12-bit
Gain error - - - ±0.5 %
error(4) configuration
Settling time (full
scale: for a 10-bit
input code transition
tSETTLING( between the lowest CLOAD ≤ 50 pF,
4) - - 3 6 µs
and the highest RLOAD ≥ 5 kΩ
input codes when
DAC_OUT reaches
final value ±4LSB
Total Harmonic
CLOAD ≤ 50 pF,
THD(4) Distortion - - - - dB
RLOAD ≥ 5 kΩ
Buffer ON
Max frequency for a
correct DAC_OUT
Update change when small CLOAD ≤ 50 pF,
- - - 1 MS/s
rate(2) variation in the input RLOAD ≥ 5 kΩ
code (from code i to
i+1LSB)
Wakeup time from
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
off state (Setting the
tWAKEUP(4) - - 6.5 10 µs input code between lowest and
ENx bit in the DAC
highest possible ones.
Control register)
Power supply
(2) rejection ratio (to
PSRR+ - - –67 –40 dB No RLOAD, CLOAD = 50 pF
VDDA) (static DC
measurement)
154/209 DocID029161 Rev 7

1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2:
Internal reset OFF).
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
Figure 52. 12-bit buffered /non-buffered DAC
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
DocID029161 Rev 7 155/209

175
6.3.25 DFSDM characteristics

Unless otherwise specified, the parameters given in Table 87 for DFSDM are derived from
tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage
conditions summarized in Table 17: General operating conditions.
• Measurement points are done at CMOS levels: 0.5 * VDD
function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM).
Table 87. DFSDM characteristics(1)

fDFSDMCLK DFSDM clock 1.71 < VDD < 3.6 V - - fSYSCLK

SPI mode
(SITP[1:0] = 0,1),
20
External clock mode - -
(fDFBDMCLK / 4
(SPICKSEL[1:0] = 0,
1.71 < VDD < 3.6 V
SPI mode
(SITP[1:0] = 0,1),
20
External clock mode - -
(fDFBDMCLK / 4
(SPICKSEL[1:0] = 0,
fCKIN Input clock 2.7 < VDD < 3.6 V
(1/TCKIN) frequency MHz
SPI mode
(SITP[1:0] = 0,1),
20
Internal clock mode - -
(fDFBDMCLK / 4
(SPICKSEL[1:0] ≠ 0,
1.71 < VDD < 3.6 V
SPI mode (SITP[1:0] = 0,1),
Internal clock mode 20
- -
(SPICKSEL[1:0] ≠ 0, (fDFBDMCLK / 4
2.7 < VDD < 3.6 V
Output clock
fCKOUT 1.71 < VDD < 3.6 V - - 20
frequency
Output clock
DuCyCKOUT frequency duty 1.71 < VDD < 3.6 V 45 50 55 %
cycle
156/209 DocID029161 Rev 7

Table 87. DFSDM characteristics(1) (continued)

SPI mode
(SITP[1:0] = 01),
twh(CKIN) Input clock high
External clock mode tCKIN / 2 - 0.5 tCKIN / 2 -
twl(CKIN) and low time
(SPICKSEL[1:0] = 0)
1.71 < VDD < 3.6 V
SPI mode
(SITP[1:0]=01),
Data input
tsu External clock mode 3.5 - -
setup time
(SPICKSEL[1:0] = 0)
1.71 < VDD < 3.6 V
ns
SPI mode
(SITP[1:0]=01),
Data input hold
th External clock mode 2.5 - -
time
(SPICKSEL[1:0] = 0)
1.71 < VDD < 3.6 V
Manchester mode
Manchester
(SITP[1:0] = 10 or 11),
data period (CKOUTDIV + 1) (2 * CKOUTDIV
TManchester Internal clock mode -
(recovered * tDFBDMCLK ) * tDFBDMCLK
(SPICKSEL[1:0] ≠ 0)
clock period)
1.71 < VDD < 3.6 V
1. Data based on characterization results.
DocID029161 Rev 7 157/209

175
Figure 16: DFSDM timing diagram

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158/209 DocID029161 Rev 7

6.3.26 FSMC characteristics

Unless otherwise specified, the parameters given in Table 88 to Table 95 for the FSMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 16, with the following configuration:
• Capacitance load C = 30 pF
• Measurement points are done at CMOS levels: 0.5.VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
Asynchronous waveforms and timings

Figure 53 through Figure 56 represent asynchronous waveforms and Table 88 through
Table 95 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
In all timing tables, the THCLK is the HCLK clock period.
DocID029161 Rev 7 159/209

175
Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

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160/209 DocID029161 Rev 7

Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR -

read timings(1)(2)
tw(NE) FSMC_NE low time 2 * tHCLK - 1 2 * tHCLK + 1

tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0 0.5
tw(NOE) FSMC_NOE low time 2 * tHCLK - 1 2 * tHCLK + 1
FSMC_NOE high to FSMC_NE high hold
th(NE_NOE) 0 -
time
tv(A_NE) FSMC_NEx low to FSMC_A valid - 0.5
th(A_NOE) Address hold time after FSMC_NOE high 0 -
tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns
th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 -
tsu(Data_NE) Data to FSMC_NEx high setup time tHCLK - 2 -
tsu(Data_NOE) Data to FSMC_NOEx high setup time tHCLK - 2 -
th(Data_NOE) Data hold time after FSMC_NOE high 0 -
th(Data_NE) Data hold time after FSMC_NEx high 0 -
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 0
tw(NADV) FSMC_NADV low time - tHCLK + 1
1. CL = 30 pF.
2. Based on characterization.
Table 89. Asynchronous non-multiplexed SRAM/PSRAM/NOR read -

NWAIT timings(1)(2)
tw(NE) FSMC_NE low time 7 * tHCLK + 1 7 * tHCLK + 1
tw(NOE) FSMC_NWE low time 5 * tHCLK - 1 5 * tHCLK + 1

tw(NWAIT) FSMC_NWAIT low time tHCLK - 0.5 - ns
FSMC_NWAIT valid before FSMC_NEx
tsu(NWAIT_NE) 5 * tHCLK + 1.5 -
high
FSMC_NEx hold time after
th(NE_NWAIT) 4 * tHCLK + 1 -
FSMC_NWAIT invalid
1. CL = 30 pF.
DocID029161 Rev 7 161/209

175
Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
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Table 90. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)

tw(NE) FSMC_NE low time 3 * tHclk - 1 3 * tHclk - 1
tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tHCLK - 1 tHCLK + 0.5
tw(NWE) FSMC_NWE low time tHCLK - 1.5 tHCLK + 0.5
th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tHCLK -
tv(A_NE) FSMC_NEx low to FSMC_A valid - 0
th(A_NWE) Address hold time after FSMC_NWE high tHCLK - 0.5 -
ns
tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5
th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tHCLK - 0.5 -
tv(Data_NE) Data to FSMC_NEx low to Data valid - tHCLK + 2.5
th(Data_NWE) Data hold time after FSMC_NWE high tHCLK -
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 0
tw(NADV) FSMC_NADV low time - tHCLK + 1
162/209 DocID029161 Rev 7

1. CL = 30 pF.
Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -

NWAIT timings(1)(2)
tw(NWE) FSMC_NWE low time 6 * tHCLK - 1.5 6 * tHCLK + 0.5

ns
tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 6 * tHCLK - 1 -
FSMC_NEx hold time after FSMC_NWAIT
invalid
1. CL = 30 pF.
Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms

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DocID029161 Rev 7 163/209

175
Table 92. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)


tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 2 * tHCLK 2 * tHCLK + 0.5
tw(NOE) FSMC_NOE low time tHCLK - 1 tHCLK + 1
FSMC_NOE high to FSMC_NE high hold
th(NE_NOE) 0 -
time
tv(A_NE) FSMC_NEx low to FSMC_A valid - 0.5
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 0 0.5
tw(NADV) FSMC_NADV low time tHCLK - 0.5 tHCLK + 1
FSMC_AD(address) valid hold time after ns
th(AD_NADV) tHCLK + 0.5 -
FSMC_NADV high)
th(A_NOE) Address hold time after FSMC_NOE high tHCLK - 0.5 -
th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 -
tsu(Data_NE) Data to FSMC_NEx high setup time tHCLK - 2 -
tsu(Data_NOE) Data to FSMC_NOE high setup time tHCLK - 2 -
th(Data_NE) Data hold time after FSMC_NEx high 0 -
th(Data_NOE) Data hold time after FSMC_NOE high 0 -
1. CL = 30 pF.
Table 93. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)(2)

8 * tHCLK + 1
tw(NE) FSMC_NE low time 8 * tHCLK - 1
tw(NOE) FSMC_NWE low time 5 * tHCLK - 1.5 5 * tHCLK + 0.5

ns
FSMC_NWAIT valid before FSMC_NEx
tsu(NWAIT_NE) 5 * tHCLK + 1.5 -
high
FSMC_NEx hold time after
FSMC_NWAIT invalid
1. CL = 30 pF.
164/209 DocID029161 Rev 7

Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms

WZ 1(
)60&B1([
)60&B12(
WY 1:(B1( WZ 1:( WK 1(B1:(
)60&B1:(
TV!?.% WK $B1:(
)60&B$>@ $GGUHVV
TV",?.% WK %/B1:(
)60&B1%/>@ 1%/
WY $B1( WY 'DWDB1$'9 WK 'DWDB1:(
)60&B$'>@ $GGUHVV 'DWD
W Y 1$'9B1( TH!$?.!$6
WZ 1$'9
)60&B1$'9
)60&B1:$,7
WK 1(B1:$,7
WVX 1:$,7B1(
06Y9
DocID029161 Rev 7 165/209

175
Table 94. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)

tw(NE) FSMC_NE low time 4 * THCLK - 1 4 * THCLK + 1

tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK - 1 THCLK + 0.5
tw(NWE) FSMC_NWE low time 2 * THCLK - 0.5 2 * THCLK - 0.5
th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK - 0.5 -
tv(A_NE) FSMC_NEx low to FSMC_A valid - 0
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 0 0.5
tw(NADV) FSMC_NADV low time THCLK THCLK + 1
ns
FSMC_AD (address) valid hold time after FSMC_NADV
th(AD_NADV) THCLK + 0.5 -
high)
th(A_NWE) Address hold time after FSMC_NWE high THCLK + 0.5 -
th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK - 0.5 -
tv(Data_NADV) FSMC_NADV high to Data valid - THCLK + 2.5
th(Data_NWE) Data hold time after FSMC_NWE high THCLK -
1. CL = 30 pF.
Table 95. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)

tw(NE) FSMC_NE low time 9 * THCLK - 1 9 * THCLK + 1
tw(NWE) FSMC_NWE low time 7 * THCLK - 0.5 7 * THCLK + 0.5 ns
tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 6 * THCLK + 2 -

th(NE_NWAIT) FSMC_NEx hold time after FSMC_NWAIT invalid 4 * THCLK - 1 -
1. CL = 30 pF.
Synchronous waveforms and timings

Figure 57 through Figure 60 represent synchronous waveforms and Table 96 through
Table 99 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
• BurstAccessMode = FSMC_BurstAccessMode_Enable;
• MemoryType = FSMC_MemoryType_CRAM;
• WriteBurst = FSMC_WriteBurst_Enable;
• CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390)
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
166/209 DocID029161 Rev 7

In all timing tables, the THCLK is the HCLK clock period (with maximum
FSMC_CLK = 90 MHz).
Figure 57. Synchronous multiplexed NOR/PSRAM read timings

WZ &/. WZ &/. %867851
)60&B&/.
'DWDODWHQF\
WG &/./1([/ WG &/.+1([+
)60&B1([
WG &/./1$'9/ WG &/./1$'9+
)60&B1$'9
WG &/./$9 WG &/.+$,9
)60&B$>@
WG &/./12(/ WG &/.+12(+
)60&B12(
WG &/./$',9 WK &/.+$'9
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)60&B$'>@ $'>@ ' '
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)60&B1:$,7
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WVX 1:$,79&/.+ WK &/.+1:$,79
)60&B1:$,7
:$,7&)* E:$,732/E
WVX 1:$,79&/.+ WK &/.+1:$,79
06Y9
DocID029161 Rev 7 167/209

175
Table 96. Synchronous multiplexed NOR/PSRAM read timings(1)(2)

tw(CLK) FSMC_CLK period 2 * THCLK - 0.5 -

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 2
td(CLKH_NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2) THCLK + 0.5 -
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 -
td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 2.5
td(CLKH-AIV) FSMC_CLK high to FSMC_Ax invalid (x=16…25) THCLK -
td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 1.5 ns
td(CLKH-NOEH) FSMC_CLK high to FSMC_NOE high THCLK - 0.5 -
td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 3
td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 -
tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 1.5 -
th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 3.5 -
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 2.5 -
th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 3.5 -
1. CL = 30 pF.
168/209 DocID029161 Rev 7

Figure 58. Synchronous multiplexed PSRAM write timings
WZ &/. WZ &/. %867851
)60&B&/.
'DWDODWHQF\
WG &/./1([/ WG &/.+1([+
)60&B1([
WG &/./1$'9/ WG &/./1$'9+
)60&B1$'9
WG &/./$9 WG &/.+$,9
)60&B$>@
WG &/./1:(/ WG &/.+1:(+
)60&B1:(
WG &/./$',9 WG &/./'DWD
WG &/./$'9 WG &/./'DWD
)60&B$'>@ $'>@ ' '
)60&B1:$,7
:$,7&)* E:$,732/E
WVX 1:$,79&/.+ WK &/.+1:$,79
WG &/.+1%/+
)60&B1%/
06Y9
DocID029161 Rev 7 169/209

175
Table 97. Synchronous multiplexed PSRAM write timings(1)(2)

tw(CLK) FSMC_CLK period, VDD range= 2.7 to 3.6 V 2 * THCLK - 0.5 -

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x= 0...2) - 2
td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2) THCLK + 0.5 -
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1.5
ns
t(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high THCLK + 0.5 -
td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 3
td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 4
td(CLKL-NBLL) FSMC_CLK low to FSMC_NBL low 0 2
td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high THCLK + 0.5 -
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 2 -
1. CL = 30 pF.
170/209 DocID029161 Rev 7

Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings

WZ &/. WZ &/.
)60&B&/.
WG &/./1([/ WG &/.+1([+
'DWDODWHQF\
)60&B1([
WG &/./1$'9/ WG &/./1$'9+
)60&B1$'9
WG &/./$9 WG &/.+$,9
)60&B$>@
WG &/./12(/ WG &/.+12(+
)60&B12(
WVX '9&/.+ WK &/.+'9
WVX '9&/.+ WK &/.+'9
)60&B'>@ ' '

WVX 1:$,79&/.+ WK &/.+1:$,79
)60&B1:$,7
:$,7&)* E
:$,732/E WVX 1:$,79&/.+ WK &/.+1:$,79
)60&B1:$,7
:$,7&)* E
:$,732/E
WVX 1:$,79&/.+ WK &/.+1:$,79
06Y9
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)

tw(CLK) FSMC_CLK period 2THCLK – 0.5 -

t(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2) THCLK +0.5 -
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0.5
td(CLKH-AIV) FSMC_CLK high to FSMC_Ax invalid (x=16…25) THCLK - ns
td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 1.5
td(CLKH-NOEH) FSMC_CLK high to FSMC_NOE high THCLK - 0.5 -
tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 1.5 -
th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 3.5 -
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 2.5 -
1. CL = 30 pF.
DocID029161 Rev 7 171/209

175
Figure 60. Synchronous non-multiplexed PSRAM write timings

WZ &/. WZ &/.
)60&B&/.
WG &/./1([/ WG &/.+1([+
'DWDODWHQF\
)60&B1([
WG &/./1$'9/ WG &/./1$'9+
)60&B1$'9
WG &/./$9 WG &/.+$,9
)60&B$>@
WG &/./1:(/ WG &/.+1:(+
)60&B1:(
WG &/./'DWD WG &/./'DWD
)60&B'>@ ' '
)60&B1:$,7
:$,7&)* E WVX 1:$,79&/.+ WG &/.+1%/+
:$,732/E
WK &/.+1:$,79
)60&B1%/
06Y9
Table 99. Synchronous non-multiplexed PSRAM write timings(1)(2)

tw(CLK) FSMC_CLK period 2 * THCLK - 0.5 -

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2) THCLK + 0.5 -
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0.5
ns
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1.5
td(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high THCLK + 1 -
td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 4
td(CLKL-NBLL) FSMC_CLK low to FSMC_NBL low - 2
td(CLKH-NBLH) FSMC_CLK high to FSMC_NBL high THCLK + 1 -
tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 2 -
1. CL = 30 pF.
172/209 DocID029161 Rev 7

6.3.27 SD/SDIO MMC/eMMC card host interface (SDIO) characteristics

Unless otherwise specified, the parameters given in Table 100 for the SDIO are derived
from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply
voltage conditions summarized in Table 17, with the following configuration:
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output
characteristics.
Figure 61. SDIO high-speed mode

WI WU
W&
W: &.+ W: &./
&.
W29 W2+
'&0' RXWSXW
W,68 W,+
'&0' LQSXW
DL
Figure 62. SD default mode
DocID029161 Rev 7 173/209

175
Table 100. SD / MMC characteristics(1)(2)

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp =50MHz 9.5 10.5 -
ns
tW(CKH) Clock high time fpp =50MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU Input setup time HS fpp =50MHz 5 - -

ns
tIH Input hold time HS fpp =50MHz 1 - -
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV Output valid time HS fpp =50MHz - 12 13.5

ns
tOH Output hold time HS fpp =50MHz 10.5 - -
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD fpp =25MHz 5 - -

ns
tIHD Input hold time SD fpp =25MHz 1 - -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD fpp =25 MHz - 2 3

ns
tOHD Output hold default time SD fpp =25 MHz 1 - -

2. VDD = 2.7 to 3.6 V.
Table 101. eMMC characteristics VDD = 1.7 V to 1.9 V(1)(2)

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp =50MHz 9.5 10.5 -
ns
tW(CKH) Clock high time fpp =50MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS fpp =50MHz 3 - -

ns
tIH Input hold time HS fpp =50MHz 2.5 - -
CMD, D outputs (referenced to CK) in eMMC mode
tOV Output valid time HS fpp =50MHz - 15 15.5

ns
tOH Output hold time HS fpp =50MHz 13 - -
2. CLOAD = 20 pF.
174/209 DocID029161 Rev 7

6.3.28 RTC characteristics
Table 102. RTC characteristics

Symbol Parameter Conditions Min Max
Any read/write operation

- fPCLK1/RTCCLK frequency ratio 4 -
from/to an RTC register
DocID029161 Rev 7 175/209

175
Package information STM32F423xH
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1 WLCSP81 package information

Figure 63. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package outline
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GGG 0 =
6,'(9,(: '(7$,/$
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1. Drawing is not to scale.
176/209 DocID029161 Rev 7

STM32F423xH Package information
Table 103. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A 0.525 0.555 0.585 0.0207 0.0219 0.0230
A1 - 0.175 - - 0.0069 -
A2 - 0.380 - - 0.0150 -
(2)
A3 - 0.025 - - 0.0010 -
Ø b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 4.004 4.039 4.074 0.1576 0.1590 0.1604
E 3.916 3.951 3.986 0.1542 0.1556 0.1569
e - 0.400 - - 0.0157 -
e1 - 3.200 - - 0.1260 -
e2 - 3.200 - - 0.1260 -
F - 0.4195 - - 0.0165 -
G - 0.3755 - - 0.0148 -
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
DocID029161 Rev 7 177/209

206
Figure 64. WLCSP81- 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint
'SDG
'VP
:/&63B$%B)3B9
Table 104. WLCSP81 recommended PCB design rules (0.4 mm pitch)

Dimension Recommended values
Pitch 0.4 mm
Dpad 0.225 mm
0.290 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm
178/209 DocID029161 Rev 7

Device marking for WLCSP81

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 65. WLCSP81 marking example (package top view)

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1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DocID029161 Rev 7 179/209

206
7.2 UFQFPN48 package information

Figure 66. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline
3LQLGHQWLILHU
ODVHUPDUNLQJDUHD
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7 6HDWLQJ
SODQH
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DUHD '

/

&[
SLQFRUQHU 5W\S
( 'HWDLO=

=
$%B0(B9

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
180/209 DocID029161 Rev 7

Table 105. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Symbol
Min. Typ. Max. Min. Typ. Max.
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
Figure 67. UFQFPN48 recommended footprint

!"?&0?6
1. Dimensions are in millimeters.
DocID029161 Rev 7 181/209

206
Device marking for UFQFPN48

location.
Figure 68. UFQFPN48 marking example (package top view)
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182/209 DocID029161 Rev 7

7.3 LQFP64 package information

Figure 69. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
6($7,1*3/$1(
&
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' /

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DocID029161 Rev 7 183/209

206
Table 106. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
Κ 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
184/209 DocID029161 Rev 7

Figure 70. LQFP64 recommended footprint

AIC
DocID029161 Rev 7 185/209

206
Device marking for LQFP64

location.
Figure 71. LQFP64 marking example (package top view)
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186/209 DocID029161 Rev 7


3%!4).' 0,!.%
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1. Drawing is not to scale. Dimensions are in millimeters.

mechanical data
Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
DocID029161 Rev 7 187/209

206

mechanical data (continued)
Symbol
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
Figure 73. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat

recommended footprint

AIC
188/209 DocID029161 Rev 7


location.
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DocID029161 Rev 7 189/209

206

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190/209 DocID029161 Rev 7

Table 108. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package

mechanical data
Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.6890 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
DocID029161 Rev 7 191/209

206
Figure 76. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package

recommended footprint

DLH
1. Dimensions are expressed in millimeters.
192/209 DocID029161 Rev 7


location.
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670)=+7
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DocID029161 Rev 7 193/209

206
7.6 UFBGA100 package information

grid array package outline
= 6HDWLQJSODQH
GGG =
$ $ $ $ $
( ;
$EDOO $EDOO
LGHQWLILHU LQGH[DUHD (
H =
$
=
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H
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0

%277209,(: E EDOOV 7239,(:
HHH 0 = < ;
III 0 =
$&B0(B9
grid array package mechanical data
Symbol
A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 0.0094
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 6.850 7.000 7.150 0.2697 0.2756 0.2815
D1 - 5.500 - - 0.2165 -
E 6.850 7.000 7.150 0.2697 0.2756 0.2815
E1 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
Z - 0.750 - - 0.0295 -
194/209 DocID029161 Rev 7

grid array package mechanical data (continued)
Symbol
ddd - - 0.080 - - 0.0031

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
grid array package recommended footprint
'SDG
'VP
$&B)3B9
Table 110. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Pitch 0.5
Dpad 0.280 mm
Dsm
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
DocID029161 Rev 7 195/209

206
Device marking for UFBGA100

The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 80. UFBGA100 marking example (package top view)
WƌŽĚƵĐƚŝĚĞŶƚŝĨŝĐĂƚŝŽŶ;ϭͿ
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$
06Y9
196/209 DocID029161 Rev 7

7.7 UFBGA144 package information

grid array package outline
& 6HDWLQJSODQH
GGG =
$ $ $ $ $
( $EDOO $EDOO $
LGHQWLILHU LQGH[DUHD (
H )
$
)
' '
H
%
0

%277209,(: E EDOOV 7239,(:
HHH 0 & $ %
III 0 & $<B0(B9
array package mechanical data
Symbol
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.360 0.400 0.440 0.0091 0.0110 0.0130
D 9.950 10.000 10.050 0.2736 0.2756 0.2776
D1 8.750 8.800 8.850 0.2343 0.2362 0.2382
E 9.950 10.000 10.050 0.2736 0.2756 0.2776
E1 8.750 8.800 8.850 0.2343 0.2362 0.2382
e 0.750 0.800 0.850 - 0.0197 -
DocID029161 Rev 7 197/209

206
array package mechanical data (continued)
Symbol
F 0.550 0.600 0.650 0.0177 0.0197 0.0217

ddd - - 0.080 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0020
grid array recommended footprint
'SDG
'VP
ϬϮzͺ&Wͺsϭ
Table 112. UFBGA144 recommended PCB design rules (0.80 mm pitch BGA)
Pitch 0.80 mm
Dpad 0.400 mm
Dsm
Note: Non solder mask defined (NSMD) pads are recommended.

4 to 6 mils solder paste screen printing process.
Stencil opening is 0.400 mm.
Stencil thickness is between 0.100 mm and 0.125 mm.
Pad trace width is 0.120 mm.
198/209 DocID029161 Rev 7

Device marking for UFBGA144

The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 83. UFBGA144 marking example (package top view)
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670)
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%DOO$
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DocID029161 Rev 7 199/209

206
7.8 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 17: General operating conditions.
The maximum chip-junction temperature, TJ max., in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 113. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

35
LQFP144 - 20 x 20 mm
43
LQFP100 - 14 x 14 mm
47
LQFP64 - 10 x 10 mm
ΘJA 48 °C/W
UFBGA144 - 10 x 10 mm / 0.8 mm pitch
57
UFBGA100 - 7 x 7 mm
39.7
WLCSP81 - 4.039 x 3.951 mm
32
UFQFPN48 - 7 x 7 mm
7.8.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
200/209 DocID029161 Rev 7

STM32F423xH Ordering information
8 Ordering information
Table 114. Ordering information scheme

Example: STM32 F 423 C H T 6 TR
Device family
STM32 = Arm®-based 32-bit microcontroller
Product type
F = General-purpose
Device subfamily
423 = 423 line with AES
Pin count
C = 48 pins
R = 64 pins
M = 81 pins
V = 100 pins
Z = 144 pins
Flash memory size

H = 1536 Kbytes of Flash memory
Package
H = UFBGA 7 x 7 mm
J = UFBGA 10 x 10 mm
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = Industrial temperature range, – 40 to 85 °C
3 = Industrial temperature range, – 40 to 125 °C
Packing
TR = tape and reel
No character = tray or tube
DocID029161 Rev 7 201/209

206
Recommendations when using the internal reset OFF STM32F423xH
Appendix A Recommendations when using the internal

reset OFF
When the internal reset is OFF, the following integrated features are no longer supported:
• The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled.
• The brownout reset (BOR) circuitry must be disabled. By default BOR is OFF.
• The embedded programmable voltage detector (PVD) is disabled.
• VBAT functionality is no more available and VBAT pin should be connected to VDD.
202/209 DocID029161 Rev 7

STM32F423xH Application block diagrams
Appendix B Application block diagrams
B.1 Sensor Hub application example

Figure 84. Sensor Hub application example
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*\URVFRSH
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,6
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6:2
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1567 3$ 026,
26& N
3&
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3&
8SWR$'&LQSXWV
06Y9
DocID029161 Rev 7 203/209

206
Application block diagrams STM32F423xH
B.2 Display application example

Figure 85. Display application example
670)[[
SLQSDFNDJH
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7,0BFK 3&
FRQWURO
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Note: 16 bit displays interfaces can be addressed with 100 and 144 pins packages.
MSv40843
204/209 DocID029161 Rev 7

STM32F423xH Application block diagrams
B.3 USB OTG full speed (FS) interface solutions

Figure 86. USB controller configured as peripheral-only and used in Full speed mode
9'' 9''86%
9WR9''86%
9ROWDJHUHJXODWRU
670)[[
670)[[
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1. External voltage regulator only needed when building a VBUS powered device.
Figure 87. USB peripheral-only Full speed mode with direct connection
for VBUS sense
9''!9 9''86%
670)[[
670)[[
SLQVSDFNDJHV
SLQVSDFNDJHV
9%86
86%6WG%FRQQHFWRU
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26&B287
966
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DocID029161 Rev 7 205/209

206
Application block diagrams STM32F423xH
Figure 88. USB peripheral-only Full speed mode, VBUS detection using GPIO
99''9 9''86%
670)[[
SLQVSDFNDJHV
*3,2 9%86
86%6WG%FRQQHFWRU
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Figure 89. USB controller configured as host-only and used in full speed mode
9''
670)[[
(1
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2. The current limiter is required only if the application has to support a VBUS powered device. A basic power
switch can be used if 5 V are available on the application board.
206/209 DocID029161 Rev 7

STM32F423xH Revision history
Revision history
Table 115. Document revision history

Date Revision Changes
02-Sep-2016 1 Initial release.

Updated Figure 65: WLCSP81 marking example
24-Oct-2016 2
(package top view)
Updated:
– Table 55: EMI characteristics for LQFP144
– Table 56: ESD absolute maximum ratings
– Table 70: QSPI dynamic characteristics in SDR mode
13-Dec-2016 3 – Table 111: UFBGA144 - 144-ball, 10 x 10 mm,
0.80 mm pitch, ultra fine pitch ball grid array package
mechanical data
– Figure 81: UFBGA144 - 144-pin, 10 x 10 mm,
0.80 mm pitch, ultra fine pitch ball grid array package
outline
Added:
12-Jan-2017 4
– Table 1: Device summary
Updated:
– Table 2: STM32F423xH features and peripheral
counts
07-Mar-2017 5
– Table 12: STM32F423xH alternate functions
Added:
– Table 11: FSMC pin definition
DocID029161 Rev 7 207/209

208
Revision history STM32F423xH
Table 115. Document revision history

Date Revision Changes
Added:
– Section 4.1: WLCSP81 pinout description
– Section 4.2: UFQFPN48 pinout description
– Section 4.3: LQFP64 pinout description
– Section 4.6: UFBGA100 pinout description
– Section 4.7: UFBGA144 pinout description
19-Jun-2017 6 – Section 4.8: Pins definition
– Section 4.9: Alternate functions
Updated:
– Table 10: STM32F423xH pin definition
– Table 11: FSMC pin definition
– Figure 38: I2C bus AC waveforms and measurement
circuit
– Figure 39: FMPI2C timing diagram and measurement
circuit
Updated:
– Section 3.29: Digital filter for sigma-delta modulators
(DFSDM)
15-Sep-2017 7
– Table 53: Flash memory endurance and data retention
– Table 59: I/O static characteristics
– Table 75: ADC characteristics
208/209 DocID029161 Rev 7

STM32F423xH
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
DocID029161 Rev 7 209/209

209

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STM32F423xH

Arm®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, 1.5MB Flash,

• Dynamic Efficiency Line with eBAM (enhanced

September 2017 DocID029161 Rev 7 1/209

2/209 DocID029161 Rev 7

3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

DocID029161 Rev 7 3/209

4.6 UFBGA100 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4/209 DocID029161 Rev 7

6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

Appendix A Recommendations when using the internal reset OFF . . . . . . . . 202

Appendix B Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

DocID029161 Rev 7 5/209

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

6/209 DocID029161 Rev 7

Table 41. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

DocID029161 Rev 7 7/209

Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write -

8/209 DocID029161 Rev 7

Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DocID029161 Rev 7 9/209

Figure 45. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10/209 DocID029161 Rev 7

for VBUS sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

DocID029161 Rev 7 11/209

This datasheet provides the description of the STM32F423xH microcontrollers.

12/209 DocID029161 Rev 7

DocID029161 Rev 7 13/209

14/209 DocID029161 Rev 7

Table 2. STM32F423xH features and peripheral counts

Flash memory (Kbyte) 1536

DocID029161 Rev 7 15/209

3. 81 pins packages: TIM4: ETR pin not available.

2.1 Compatibility with STM32F4 series

Figure 1. Compatible board design for LQFP100 package

966 9'' 966 9''

16/209 DocID029161 Rev 7

Figure 2. Compatible board design for LQFP64 package

966 9'' 9 6 6 9 ''

Figure 3. Compatible board design for LQFP144 package

 9''  9''

DocID029161 Rev 7 17/209

Figure 4. STM32F423xH block diagram

6WUHDPV $+%0+] 9'' 3RZHUPDQDJPW

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DQDORJLQSXWV $'& ,) '$& &$1 7;5;

18/209 DocID029161 Rev 7

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

9'' 9''

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