STM 32 L 412 KB

STM32L412xx
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,

up to 128KB flash, 40KB SRAM, analog, ext. SMPS
Datasheet - production data
Features
Includes ST state-of-the-art patented
LQFP32 (7x7 mm) UFBGA64 (5x5 mm) UFQFPN32 (5x5 mm) WLCSP36
technology LQFP48 (7x7 mm) UFQFPN48 (7x7 mm) (2.6x3.1 mm)
LQFP64 (10x10 mm)
• Ultra-low-power with FlexPowerControl
– 1.71 V to 3.6 V power supply – Internal multispeed 100 kHz to 48 MHz
– -40 °C to 85/125 °C temperature range oscillator, auto-trimmed by LSE (better than
– 300 nA in VBAT mode: supply for RTC and ±0.25 % accuracy)
32x32-bit backup registers – Internal 48 MHz with clock recovery
– 16 nA Shutdown mode (4 wakeup pins) – PLL for system clock
– 32 nA Standby mode (4 wakeup pins) • Up to 52 fast I/Os, most 5 V-tolerant
– 245 nA Standby mode with RTC • RTC with HW calendar, alarms and calibration
– 0.7 µA Stop 2 mode, 0.95 µA with RTC • Up to 12 capacitive sensing channels: support
– 79 µA/MHz run mode (LDO Mode) touchkey, linear and rotary touch sensors
– 28 μA/MHz run mode (@3.3 V SMPS • 10x timers: 1x 16-bit advanced motor-control,
Mode) 1x 32-bit and 2x 16-bit general purpose, 1x 16-
– Batch acquisition mode (BAM) bit basic, 2x low-power 16-bit timers (available
– 4 µs wakeup from Stop mode in Stop mode), 2x watchdogs, SysTick timer
– Brown out reset (BOR) • Memories
– Interconnect matrix – 128 KB single bank flash, proprietary code
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, readout protection
Adaptive real-time accelerator (ART – 40 KB of SRAM including 8 KB with
Accelerator™) allowing 0-wait-state execution hardware parity check
from flash memory, frequency up to 80 MHz, – Quad SPI memory interface with XIP
MPU, 100DMIPS and DSP instructions capability
• Performance benchmark • Rich analog peripherals (independent supply)
– 1.25 DMIPS/MHz (Drystone 2.1) – 2x 12-bit ADC 5 Msps, up to 16-bit with
– 273.55 CoreMark® (3.42 CoreMark/MHz @ hardware oversampling, 200 µA/Msps
80 MHz) – 1x operational amplifier with built-in PGA
• Energy benchmark – 1x ultra-low-power comparator
– 442 ULPMark-CP® • 12x communication interfaces
– 165 ULPMark-PP® – USB 2.0 full-speed crystal less solution
• Clock Sources with LPM and BCD
– 4 to 48 MHz crystal oscillator – 3x I2C FM+(1 Mbit/s), SMBus/PMBus
– 32 kHz crystal oscillator for RTC (LSE) – 3x USARTs (ISO 7816, LIN, IrDA, modem)
– Internal 16 MHz factory-trimmed RC (±1%) – 1x LPUART (Stop 2 wake-up)
– Internal low-power 32 kHz RC (±5%) – 2x SPIs (and 1x Quad SPI)
– IRTIM (Infrared interface)
December 2022 DS12469 Rev 9 1/198

This is information on a product in full production. www.st.com
STM32L412xx
• 14-channel DMA controller • Development support: serial wire debug

• True random number generator (SWD), JTAG, Embedded Trace Macrocell™
• CRC calculation unit, 96-bit unique ID • All packages are ECOPACK2 compliant
Table 1. Device summary
Reference Part numbers
STM32L412CB, STM32L412KB, STM32L412RB, STM32L412TB

STM32L412xx
STM32L412C8, STM32L412K8, STM32L412R8, STM32L412T8
2/198 DS12469 Rev 9

STM32L412xx Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 16
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 19
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 37
3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 37
3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.16 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Contents STM32L412xx
3.17 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.18 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.19 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20.2 General-purpose timers (TIM2, TIM15, TIM16) . . . . . . . . . . . . . . . . . . . 42
3.20.3 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.20.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 42
3.20.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.20.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.20.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.20.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.21 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 44
3.22 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.23 Universal synchronous/asynchronous receiver transmitter (USART) . . . 46
3.24 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47
3.25 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.26 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.27 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.28 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.29 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.29.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.29.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
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STM32L412xx Contents
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 80
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 80
6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 138
6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 139
6.3.19 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.20 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.24 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 158
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

7.1 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
7.2 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
7.4 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.5 WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.6 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
DS12469 Rev 9 5/198

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Contents STM32L412xx

7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 191
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6/198 DS12469 Rev 9

STM32L412xx List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32L412xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 17
Table 4. STM32L412xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6. STM32L412xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 11. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. STM32L412xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 14. STM32L412xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 15. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 16. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 17. STM32L412xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 72
Table 18. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 19. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 20. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 21. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 22. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 23. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 24. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 25. Current consumption in Run and Low-power run modes, code with data processing
running from flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 26. Current consumption in Run modes, code with data processing running from flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
running from flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . . 89
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 30. Current consumption in Run, code with data processing running from
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . 91
Table 31. Typical current consumption in Run and Low-power run modes, with different codes
running from flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 32. Typical current consumption in Run, with different codes running from flash,
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
(VDD12 = 1.00 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
running from flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 35. Typical current consumption in Run modes, with different codes running from
DS12469 Rev 9 7/198

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List of tables STM32L412xx
flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . 94
Table 36. Typical current consumption in Run modes, with different codesrunning from
flash, ART disable and power supplied by external SMPS (VDD12 = 1.00 V) . . . . . . . . . 95
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 38. Typical current consumption in Run, with different codes running from
Table 40. Current consumption in Sleep and Low-power sleep modes, flash ON . . . . . . . . . . . . . . . 97
Table 41. Current consumption in Sleep, flash ON and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 42. Current consumption in Low-power sleep modes, flash in power-down. . . . . . . . . . . . . . . 98
Table 43. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 44. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 45. Current consumption in Stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 46. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 47. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 48. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 49. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 50. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 51. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 52. Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 53. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 54. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 55. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 56. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 57. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 58. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Table 59. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 60. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 61. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 62. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 63. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 64. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 65. EMI characteristics for fHSE = 8 MHz and fHCLK = 64 MHz . . . . . . . . . . . . . . . . . . . . . 130
Table 66. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 67. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 68. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 69. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 70. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 71. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 72. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 73. EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 74. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 75. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 76. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 77. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 81. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
8/198 DS12469 Rev 9

STM32L412xx List of tables
Table 82. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Table 83. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 84. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 85. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 86. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 87. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 88. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 89. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 90. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 91. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 92. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 93. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 94. LQFP64 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 95. UFBGA64 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 96. UFBGA64 - Recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . 172
Table 98. UFQFPN48 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 99. WLCSP36 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 100. WLCSP36 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 101. UFQFPN32 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 103. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 104. STM32L412xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 105. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
DS12469 Rev 9 9/198

9
List of figures STM32L412xx
List of figures
Figure 1. STM32L412xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3. Power supply overview, external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 6. STM32L412Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7. STM32L412Rx, external SMPS, LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 8. STM32L412Rx UFBGA64 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 9. STM32L412Rx UFBGA64, external SMPS, ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. STM32L412Cx LQFP48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11. STM32L412Cx LQFP48, external SMPS, pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 12. STM32L412Cx UFQFPN48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 13. STM32L412Cx UFQFPN48, external SMPS, pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 14. STM32L412Tx WLCSP36 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 15. STM32L412Tx, external SMPS, WLCSP36 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 16. STM32L412Kx LQFP32 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 17. STM32L412Kx UFQFPN32 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 18. STM32L412xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 19. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 21. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 22. Current consumption measurement scheme with and without external
SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 23. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 24. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 25. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 26. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 27. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 28. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 29. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 30. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 31. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 32. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 33. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 34. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 35. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 36. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 37. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 38. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 39. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 40. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 41. LQFP64 - Outline(15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 42. LQFP64 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 43. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 44. LQFP64 (external SMPS device) marking (package top view). . . . . . . . . . . . . . . . . . . . . 170
Figure 45. UFBGA64 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 46. UFBGA64 – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
10/198 DS12469 Rev 9

STM32L412xx List of figures
Figure 47. UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 51. UFQFPN48 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 52. UFQFPN48 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 53. UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 54. WLCSP36 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 55. WLCSP36 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 56. WLCSP36 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 57. UFQFPN32 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 58. UFQFPN32 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 59. UFQFPN32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
DS12469 Rev 9 11/198

11
Introduction STM32L412xx
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L412xx microcontrollers.
This document should be read in conjunction with the STM32L41x, STM32L42x,
STM32L43x, STM32L44x, STM32L45x, STM32L46x reference manual (RM0394), available
from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M4 core, refer to the Cortex®-M4 Technical
Reference Manual, available from the www.arm.com website.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32L412xx errata sheet (ES0456), available on the STMicroelectronics
website www.st.com.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
12/198 DS12469 Rev 9

STM32L412xx Description
2 Description
The STM32L412xx devices are ultra-low-power microcontrollers based on the

high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to
80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision that
supports all Arm® single-precision data-processing instructions and data types. It also
implements a full set of DSP instructions and a memory protection unit (MPU) which
enhances application security.
The STM32L412xx devices embed high-speed memories (flash memory up to 128 Kbyte,
40 Kbyte of SRAM), a Quad SPI flash memories interface (available on all packages) and
an extensive range of enhanced I/Os and peripherals connected to two APB buses, two
AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L412xx devices embed several protection mechanisms for embedded flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and Firewall.
The devices offer two fast 12-bit ADC (5 Msps), two comparators, one operational amplifier,
a low-power RTC, one general-purpose 32-bit timer, one 16-bit PWM timer dedicated to
motor control, four general-purpose 16-bit timers, and two 16-bit low-power timers.
In addition, up to 12 capacitive sensing channels are available.
They also feature standard and advanced communication interfaces, namely three I2Cs,
two SPIs, three USARTs and one Low-Power UART, one USB full-speed device crystal
less.
The STM32L412xx operates in the -40 to +85 °C (+105 °C junction) and -40 to +125 °C
(+130 °C junction) temperature ranges from a 1.71 to 3.6 V VDD power supply when using
internal LDO regulator and a 1.00 to 1.32V VDD12 power supply when using external SMPS
supply. A comprehensive set of power-saving modes makes possible the design of low-
power applications.
Some independent power supplies are supported: analog independent supply input for
ADC, OPAMP and comparator. A VBAT input makes it possible to backup the RTC and
backup registers. Dedicated VDD12 power supplies can be used to bypass the internal LDO
regulator when connected to an external SMPS.
The STM32L412xx family offers six packages from 32 to 64-pin packages.
Table 2. STM32L412xx family device features and peripheral counts

STM32L412RB
STM32L412CB
STM32L412KB
STM32L412TB
STM32L412R8
STM32L412C8
STM32L412K8
STM32L412T8
Peripheral
Flash memory 128KB 64KB 128KB 64KB 128KB 64KB 128KB 64KB
SRAM 40KB
Quad SPI Yes
DS12469 Rev 9 13/198

50
Description STM32L412xx
Table 2. STM32L412xx family device features and peripheral counts (continued)
STM32L412RB
STM32L412CB
STM32L412KB
STM32L412TB
STM32L412R8
STM32L412C8
STM32L412K8
STM32L412T8
Peripheral
Advanced
1 (16-bit)
control
General 2 (16-bit)
purpose 1 (32-bit)
Basic 1 (16-bit)
Timers Low -power 2 (16-bit)
SysTick timer 1
Watchdog
timers
2
(independent,
window)
SPI 2 1
2C
Comm. I 3 2
interfac USART 3 2
es LPUART 1 1
USB FS Yes
RTC Yes
Tamper pins 2 2 1
Random generator Yes
GPIOs(1) 52 38 30 26
Wakeup pins 4 3 2 2
Capacitive sensing
12 6 2
Number of channels
12-bit ADC 2 2 2 2
Number of channels 16 10 10 10
Internal voltage
No
reference buffer
Analog comparator 1
Operational amplifiers 1
Max. CPU frequency 80 MHz
Operating voltage (VDD) 1.71 to 3.6 V
Operating voltage
1.00 to 1.32 V
(VDD12)
Ambient operating temperature: -40 to 85 °C / -40 to 125 °C
Operating temperature
Junction temperature: -40 to 105 °C / -40 to 130 °C
LQFP64 LQFP48 UFQFPN32
Packages WLCSP36
UFBGA64 UFQFPN48 LQFP32
1. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS
power supplies hence reducing the number of available GPIO's by 2.
14/198 DS12469 Rev 9

STM32L412xx Description
Figure 1. STM32L412xx block diagram
D0[3:0],
NJTRST, JTDI, D1[3:0],
JTCK/SWCLK JTAG & SW Quad SPI memory interface CLK0,
MPU
CLK1
JTDO/SWD, JTDO
ETM NVIC CS
TRACECLK
TRACED[3:0] D-BUS
ARM Cortex-M4
80 MHz
I-BUS
FPU RNG
ACCEL/
CACHE
Flash
ART
S-BUS up to
128 KB
AHB bus-matrix
SRAM2 8 KB
SRAM1 32 KB
VDD Power management

DMA2 AHB2 80 MHz
Voltage VDD = 1.71 to 3.6 V
regulator
VSS
3.3 to 1.2 V
DMA1
@ VDD @ VDD
Supply
MSI reset
supervision
7 Groups of VDDUSB
Touch sensing controller RC HSI Int
4 channels max as AF BOR
VDDA, VSSA
RC LSI VDD, VSS, NRST
PA[15:0] GPIO PORT A PVD, PVM
PLL 1&2
PB[15:0] GPIO PORT B AHB1 80 MHz HSI48 @VDD
XTAL OSC OSC_IN

PC[15:0] GPIO PORT C 4- 16MHz OSC_OUT
IWDG
VBAT = 1.55 to 3.6 V
PD2 GPIO PORT D
Standby
PH[1:0],
GPIO PORT H interface
PH[3] Reset & clock
M AN AGT
control @VBAT
OSC32_IN
XTAL 32 kHz
OSC32_OUT
@ VDD
RTC
RTC_TS
FCLK
PCLKx
U STemperature
AR T 2 M sensor
Bps AWU
HCLKx
RTC_TAMPx
Backup register
RTC_OUT
TIM2 32b 4 channels, ETR as AF

CRC
@ VDDA @ VDDUSB
DP
16 external analog inputs ADC1
FIFO
PHY DM
USB FS
ITF NOE
16 external analog inputs ADC2

CRS CRS_SYNC
@ VDDA
smcard
VREF+ USART2 RX, TX, CK, CTS, RTS as AF
VREF Buffer AHB/APB2 AHB/APB1 IrDA
smcard RX, TX, CK, CTS, RTS as AF

USART3
83 AF EXT IT. WKUP IrDA
3 compl. channels (TIM1_CH[1:3]N),

4 channels (TIM1_CH[1:4]), TIM1 / PWM 16b
ETR, BKIN, BKIN2 as AF
SPI2 MOSI, MISO, SCK, NSS as AF
WWDG
I2C1/SMBUS SCL, SDA, SMBA as AF
2 channels, 16b
TIM15
1 compl. channel, BKIN as AF
APB2 80MHz
1 channel,
TIM16 16b
1 compl. channel, BKIN as AF
1 3 0 M Hz
smcard
A P B(max)
RX, TX, CK,CTS, USART1

RTS as AF IrDA TIM6 16b
APB1 80 MHz
MOSI, MISO,
SPI1
SCK, NSS as AF
@VDDA
OpAmp1 VOUT, VINM, VINP

B Hz
60PM
A 2
LPUART1 RX, TX, CTS, RTS as AF

@ VDDA
INP, INM, OUT COMP1
LPTIM1 IN1, IN2, OUT, ETR as AF
FIREWALL
LPTIM2 IN1, OUT, ETR as AF
MSv45999V2
Note: AF: alternate function on I/O pins.
DS12469 Rev 9 15/198

50
Functional overview STM32L412xx
3 Functional overview
3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems, developed to provide a low-cost platform that meets the needs of MCU
implementation with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an Arm® core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions enabling efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded Arm® core, the STM32L412xx family is compatible with all Arm® tools
and software.
Figure 1 shows the general block diagram of the STM32L412xx family devices.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator optimized for STM32 industry-standard
Arm® Cortex®-M4 processors. It balances the inherent performance advantage of the Arm®
Cortex®-M4 over flash memory technologies, which normally requires the processor to wait
for the flash memory at higher frequencies.
To release the processor near 100 DMIPS performance at 80 MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from flash memory at a CPU frequency up to 80 MHz.
3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole
4 Gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
16/198 DS12469 Rev 9

STM32L412xx Functional overview
3.4 Embedded flash memory

STM32L412xx devices feature 128Kbyte of embedded flash memory available for storing
programs and data in single bank architecture.The flash memory contains 64 pages of 2
Kbyte
Flexible protections can be configured thanks to option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial
wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
Table 3. Access status versus readout protection level and execution modes
Debug, boot from RAM or boot
User execution
Protection from system memory (loader)
Area
level
Read Write Erase Read Write Erase
Main 1 Yes Yes Yes No No No

memory 2 Yes Yes Yes N/A N/A N/A
System 1 Yes No No Yes No No

memory 2 Yes No No N/A N/A N/A
Option 1 Yes Yes Yes Yes Yes Yes

bytes 2 Yes No No N/A N/A N/A
(1)
Backup 1 Yes Yes N/A No No N/A(1)
registers 2 Yes Yes N/A N/A N/A N/A
1 Yes Yes Yes(1) No No No(1)
SRAM2
2 Yes Yes Yes N/A N/A N/A
1. Erased when RDP change from Level 1 to Level 0.
• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 2-Kbyte granularity.
• Proprietary code readout protection (PCROP): a part of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP)
allows the user to select if the PCROP area is erased or not when the RDP protection
is changed from Level 1 to Level 0.
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• single error detection and correction
• double error detection.
DS12469 Rev 9 17/198

50
The address of the ECC fail can be read in the ECC register.
3.5 Embedded SRAM

STM32L412xx devices feature 40 Kbyte of embedded SRAM, split into two blocks:
• 32 Kbyte mapped at address 0x2000 0000 (SRAM1)
• 8 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2000 8000, offering a contiguous address
space with the SRAM1 (8 Kbyte aliased by bit band)
This block is accessed through the ICode/DCode buses for maximum performance.
These 8 Kbyte SRAM can also be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.6 Firewall
The device embeds a Firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
The Firewall main features are the following:
• Three segments can be protected and defined thanks to the Firewall registers:
– Code segment (located in flash or SRAM1 if defined as executable protected
area)
– Non-volatile data segment (located in flash)
– Volatile data segment (located in SRAM1)
• The start address and the length of each segments are configurable:
– Code segment: up to 1024 Kbyte with granularity of 256 bytes
– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes
– Volatile data segment: up to 128 Kbyte with a granularity of 64 bytes
• Specific mechanism implemented to open the Firewall to get access to the protected
areas (call gate entry sequence)
• Volatile data segment can be shared or not with the non-protected code
• Volatile data segment can be executed or not depending on the Firewall configuration
The flash readout protection must be set to level 2 in order to reach the expected level of
protection.
3.7 Boot modes

At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select
one of three boot options:
• Boot from user flash memory
• Boot from system memory
• Boot from embedded SRAM
18/198 DS12469 Rev 9

The boot loader is located in system memory. It is used to reprogram the flash memory by
using USART, I2C, SPI or USB FS in Device mode through DFU (device firmware upgrade).
BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the
value of a user option bit to free the GPIO pad if needed.
An empty check mechanism is implemented to force the boot from system flash if the first
memory location is not programmed and if the boot selection is configured to boot from main
flash. If the boot selection uses BOOT0 pin to boot from the main flash memory, but the first
flash memory location is found empty, the flash empty check mechanism forces boot from
the system memory (containing embedded bootloader). Then due to bootloader activation,
some of the GPIOs are reconfigured from the High-Z state. Please refer to AN2606 for more
details concerning the bootloader and GPIOs configuration in system memory boot mode.
It is possible to disable this feature by configuring the option bytes (instead of BOOT0 pin) to
force boot from the main flash memory (nSWBOOT0 = 0, nBOOT0 = 1).
3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.9 Power supply management
3.9.1 Power supply schemes

• VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and
the system analog such as reset, power management and internal clocks. It is provided
externally through VDD pins.
• VDD12 = 1.00 to 1.32 V: external power supply bypassing internal regulator when
connected to an external SMPS. It is provided externally through VDD12 pins and only
available on packages with the external SMPS supply option. VDD12 does not require
any external decoupling capacitance and cannot support any external load.
• VDDA = 1.62 V (ADC/COMP) / 1.8 (OPAMP) to 3.6 V: external analog power supply for
ADC, OPAMP, Comparator. The VDDA voltage level is independent from the VDD
voltage.
• VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage.
• VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: When the functions supplied by VDDA are not used, this supply should preferably be shorted
to VDD.
Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V
tolerant.
DS12469 Rev 9 19/198

50
Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with
VDDIO1 = VDD.
Figure 2. Power supply overview
VDDA domain
A/D converters
VDDA Comparators
VSSA Operational amplifiers
Voltage reference buffer
VDDUSB
USB transceivers
VSS
VDD domain
VDDIO1
VDD I/O ring
Reset block
Temp. sensor
PLL, HSI, MSI, HSI48
VSS
Standby circuitry
(Wakeup logic, IWDG)
VCORE domain
VCORE Core
Voltage regulator Memories
Digital peripherals
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
VBAT RCC BDCR register
RTC
MS51448V1
20/198 DS12469 Rev 9

Figure 3. Power supply overview, external SMPS
VDDA domain
A/D converters
VDDA Comparators
VSSA Operational amplifiers
Voltage reference buffer
VDDUSB
USB transceivers
VSS
VDD domain
VDDIO1
VDD I/O ring
Reset block
Temp. sensor
PLL, HSI, MSI, HSI48
VSS
Standby circuitry
(Wakeup logic, IWDG)
VCORE domain
VCORE Core
Voltage regulator Memories
Digital peripherals
VDD12
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
VBAT RCC BDCR register
RTC
MS49685V1
During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDAVDDUSB) must remain below VDD +
300 mV.
• When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1 mJ; this allows external decoupling
capacitors to be discharged with different time constants during the power-down transient
phase.
DS12469 Rev 9 21/198

50
Figure 4. Power-up/down sequence

V
3.6
VDDX(1)
VDD
VBOR0
0.3
Power-on Operating mode Power-down time
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDUSB.
3.9.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
except Shutdown and ensuring proper operation after power-on and during power down.
The device remains in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a Peripheral Voltage Monitor which compares the
independent supply voltage VDDA with a fixed threshold in order to ensure that the
peripheral is in its functional supply range.
22/198 DS12469 Rev 9

3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
• The MR is used in the Run and Sleep modes and in the Stop 0 mode.
• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 8 Kbyte SRAM2 in Standby with SRAM2 retention.
• Both regulators are in power-down in Standby and Shutdown modes: the regulator
output is in high impedance, and the kernel circuitry is powered down thus inducing
zero consumption.
The ultralow-power STM32L412xx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the Main Regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
There are two power consumption ranges:
• Range 1 with the CPU running at up to 80 MHz.
• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by HSI16.
3.9.4 Low-power modes

The ultra-low-power STM32L412xx supports seven low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources.
DS12469 Rev 9 23/198

50
24/198
Functional overview
Table 4. STM32L412xx modes overview
Mode Regulator(1) CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source Consumption(3) Wakeup time
MR range 1 91 µA/MHz
All
SMPS range 2 high 34 µA/MHz
Run Yes ON(4) ON Any N/A N/A
MR range2 79 µA/MHz
All except USB_FS, RNG
SMPS range 2 low 28 µA/MHz
Any to Range 1: 4 µs
LPRun LPR Yes ON(4) ON except All except USB_FS, RNG N/A 83 µA/MHz
to Range 2: 64 µs
PLL
MR range 1 21 µA/MHz
All
SMPS range 2 high Any interrupt or 7.5 µA/MHz
Sleep No ON(4) ON(5) Any 6 cycles
MR range2 event 20 µA/MHz
All except USB_FS, RNG
DS12469 Rev 9
SMPS range 2 low 7 µA/MHz

Any
Any interrupt or
LPSleep LPR No ON(4) ON(5) except All except USB_FS, RNG 83 µA/MHz 6 cycles
event
PLL
BOR, PVD, PVM

Reset pin, all I/Os
MR Range 1 RTC, IWDG
BOR, PVD, PVM
COMP1, OPAMP1
RTC, IWDG
USARTx (x=1...3)(6)
COMP1
LSE LPUART1(6) 2.47 µs in SRAM
Stop 0 No OFF ON USARTx (x=1...3)(6) 105 µA
LSI I2Cx (x=1...3)(7) 4.1 µs in flash
LPUART1(6)
LPTIMx (x=1,2)
I2Cx (x=1...3)(7)
***
LPTIMx (x=1,2)
All other peripherals are
STM32L412xx
MR Range 2
USB_FS(8)
frozen.
Table 4. STM32L412xx modes overview (continued)
STM32L412xx
(1)
Mode Regulator CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source Consumption(3) Wakeup time
BOR, PVD, PVM

Reset pin, all I/Os
RTC, IWDG
BOR, PVD, PVM
COMP1, OPAMP1
RTC, IWDG
USARTx (x=1...3)(6)
COMP1
LSE LPUART1(6) 3.25 µA w/o RTC 5.7 µs in SRAM
Stop 1 LPR No Off ON USARTx (x=1...3)(6)
LSI I2Cx (x=1...3)(7) 3.65 µA w RTC 7 µs in flash
LPUART1(6)
LPTIMx (x=1,2)
I2Cx (x=1...3)(7)
***
LPTIMx (x=1,2)
All other peripherals are
USB_FS(8)
frozen.
BOR, PVD, PVM
RTC, IWDG Reset pin, all I/Os
COMP1 BOR, PVD, PVM
DS12469 Rev 9
I2C3(7) RTC, IWDG

LSE 710 nA w/o RTC 5.8 µs in SRAM
Stop 2 LPR No Off ON LPUART1(6) COMP1
950 nA w RTC
LSI 8.3 µs in flash
LPTIMx (x = 1, 2) I2C3(7)
*** LPUART1(6)
All other peripherals are LPTIMx (x = 1, 2)
frozen.
Functional overview
25/198
Table 4. STM32L412xx modes overview (continued)
26/198
Functional overview
(1)
Mode Regulator CPU Flash SRAM Clocks DMA and Peripherals(2) Wakeup source Consumption(3) Wakeup time
SRAM BOR, RTC, IWDG

LPR 195 nA
2 ON ***
All other peripherals are Reset pin
Power LSE
Standby Off Power powered off. 5 I/Os (WKUPx)(9) 16.1 µs
ed Off LSI
OFF ed *** BOR, RTC, IWDG 105 nA
Off I/O configuration can be
floating, pull-up or pull-down
RTC
***
Power All other peripherals are Reset pin
Power powered off.
Shutdown OFF Off ed LSE 5 I/Os (WKUPx)(9) 18 nA 256 µs
ed Off ***
Off RTC
I/O configuration can be
DS12469 Rev 9
floating, pull-up or pull-

down(10)
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in
LPRun/LPSleep.
4. The flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
5. The SRAM1 and SRAM2 clocks can be gated on or off independently.
6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. USB_FS wakeup by resume from suspend and attach detection protocol event.
9. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PA2, PC5.
10. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
STM32L412xx
By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize the
regulator's operating current. The code can be executed from SRAM or from flash, and
the CPU frequency is limited to 2 MHz. The peripherals with independent clock can be
clocked by HSI16.
• Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the low-
power run mode.
• Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode
to detect their wakeup condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
• Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL, the
MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in
Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention
mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
DS12469 Rev 9 27/198

50
• Shutdown mode
The Shutdown mode permits to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16,
the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
28/198 DS12469 Rev 9

Table 5. Functionalities depending on the working mode(1)

Stop 0/1 Stop 2 Standby Shutdown
Wakeup capability
Wakeup capability
Wakeup capability
Wakeup capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -
CPU Y - Y - - - - - - - - - -
Flash memory (up to
O(2) O(2) O(2) O(2) - - - - - - - - -
128 KB)
SRAM1 (32 KB) Y Y(3) Y Y(3) Y - Y - - - - - -
SRAM2 (8 KB) Y Y(3) Y Y(3) Y - Y - O(4) - - - -
Quad SPI O O O O - - - - - - - - -
Backup registers Y Y Y Y Y - Y - Y - Y - Y
Brown-out reset
Y Y Y Y Y Y Y Y Y Y - - -
(BOR)
Programmable
voltage detector O O O O O O O O - - - - -
(PVD)
Peripheral voltage
monitor (PVMx; O O O O O O O O - - - - -
x=1,3,4)
DMA O O O O - - - - - - - - -
High speed Internal (5) (5)
O O O O - - - - - - -
(HSI16)
Oscillator RC48 O O - - - - - - - - - - -
High speed external
O O O O - - - - - - - - -
(HSE)
Low speed internal
O O O O O - O - O - - - -
(LSI)
Low speed external
O O O O O - O - O - O - O
(LSE)
Multi-Speed internal
O O O O - - - - - - - - -
(MSI)
Clock security
O O O O - - - - - - - - -
system (CSS)
Clock security
O O O O O O O O O O - - -
system on LSE
RTC / Auto wakeup O O O O O O O O O O O O O
Number of RTC
2 2 2 2 2 O 2 O 2 O 2 O 2
Tamper pins
USARTx (x=1,2,3) O O O O O(6) O(6) - - - - - - -
DS12469 Rev 9 29/198

50
Table 5. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Standby Shutdown
Wakeup capability
Wakeup capability
Wakeup capability
Wakeup capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -
Low-power UART
O O O O O(6) O(6) O(6) O(6) - - - - -
(LPUART)
I2Cx (x=1,2) O O O O O(7) O(7) - - - - - - -
I2C3 O O O O O(7) O(7) O(7) O(7) - - - - -
SPIx (x=1,2) O O O O - - - - - - - - -
ADCx (x=1,2) O O O O - - - - - - - - -
OPAMPx (x=1) O O O O O - - - - - - - -
COMP1 O O O O O O O O - - - - -
Temperature sensor O O O O - - - - - - - - -
Timers (TIMx) O O O O - - - - - - - - -
Low-power timer 1
O O O O O O O O - - - - -
(LPTIM1)
Low-power timer 2
O O O O O O O O - - - - -
(LPTIM2)
Independent
O O O O O O O O O O - - -
watchdog (IWDG)
Window watchdog
O O O O - - - - - - - - -
(WWDG)
SysTick timer O O O O - - - - - - - - -
Touch sensing
O O O O - - - - - - - - -
controller (TSC)
Random number
O(8) O(8) - - - - - - - - - - -
generator (RNG)
CRC calculation unit O O O O - - - - - - - - -
4 4
(9) (11)
GPIOs O O O O O O O O pins pins -
(10) (10)
1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.
2. The flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame
event.
30/198 DS12469 Rev 9

7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling Range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
3.9.5 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.9.6 VBAT operation

The VBAT pin permits to power the device VBAT domain from an external battery, an
external supercapacitor, or from VDD when no external battery and an external
supercapacitor are present. The VBAT pin supplies the RTC with LSE and the backup
registers. Two anti-tamper detection pins are available in VBAT mode.
VBAT operation is automatically activated when VDD is not present.
An internal VBAT battery charging circuit is embedded and can be activated when VDD is
present.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
3.10 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run
and sleep, Stop 0, Stop 1 and Stop 2 modes.
Table 6. STM32L412xx peripherals interconnect matrix

Low-power sleep
Low-power run
Stop 0 / Stop 1
Stop 2
Sleep
Interconnect
Run
Interconnect source Interconnect action

destination
TIMx Timers synchronization or chaining Y Y Y Y - -
ADCx
Conversion triggers Y Y Y Y - -
TIMx
DMA Memory to memory transfer trigger Y Y Y Y - -

COMPx Comparator output blanking Y Y Y Y - -
DS12469 Rev 9 31/198

50
Table 6. STM32L412xx peripherals interconnect matrix (continued)
Low-power sleep
Low-power run
Stop 0 / Stop 1
Stop 2
Sleep
Interconnect
Run
Interconnect source Interconnect action
destination
TIM15/TIM16 IRTIM Infrared interface output generation Y Y Y Y - -

TIM1 Timer input channel, trigger, break from
Y Y Y Y - -
TIM2 analog signals comparison
COMPx
Low-power timer triggered by analog
LPTIMERx Y Y Y Y Y Y
signals comparison
ADCx TIM1 Timer triggered by analog watchdog Y Y Y Y - -

TIM16 Timer input channel from RTC events Y Y Y Y - -
RTC Low-power timer triggered by RTC alarms
LPTIMERx Y Y Y Y Y Y
or tampers
All clocks sources (internal TIM2 Clock source used as input channel for
Y Y Y Y - -
and external) TIM15, 16 RC measurement and trimming
CSS
CPU (hard fault)
RAM (parity error) TIM1
Timer break Y Y Y Y - -
Flash memory (ECC error) TIM15,16
COMPx
PVD
TIMx External trigger Y Y Y Y - -

LPTIMERx External trigger Y Y Y Y Y Y
GPIO
ADCx Conversion external trigger Y Y Y Y - -
32/198 DS12469 Rev 9

3.11 Clocks and startup

The clock controller (see Figure 5) distributes the clocks coming from different oscillators to
the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply
a PLL. The HSE can also be configured in bypass mode for an external clock.
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.
– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 80 MHz.
• RC48 with clock recovery system (HSI48): internal RC48 MHz clock source can be
used to drive the USB or the RNG peripherals. This clock can be output on the MCO.
• Auxiliary clock source: two ultralow-power clock sources that can be used to drive
the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy.
• Peripheral clock sources: Several peripherals (RNG, USARTs, I2Cs, LPTimers) have
their own independent clock whatever the system clock. PLL having three independent
outputs allowing the highest flexibility, can generate independent clocks for the RNG.
• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
DS12469 Rev 9 33/198

50
interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
• Clock-out capability:
– MCO: microcontroller clock output: it outputs one of the internal clocks for
external use by the application. Low frequency clocks (LSI, LSE) are available
down to Stop 1 low power state.
– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes
down to Standby mode. LSE can also be output on LSCO in Shutdown mode.
LSCO is not available in VBAT mode.
Several prescalers permit to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 80 MHz.
34/198 DS12469 Rev 9

Figure 5. Clock tree

to IWDG
LSI RC 32 kHz
LSCO
to RTC
OSC32_OUT
LSE OSC
/32
32.768 kHz
OSC32_IN
LSE
LSI
MCO HSE
ĺ to PWR
SYSCLK
HSI16 to AHB bus, core, memory and DMA
Clock
HSI48 source
MSI control AHB PRESC HCLK FCLK Cortex free running clock
OSC_OUT HSE OSC
PLLCLK / 1,2,..512
4-48 MHz to Cortex system timer
HSE
/8
OSC_IN Clock MSI
detector SYSCLK PCLK1
HSI16 APB1 PRESC
/ 1,2,4,8,16 to APB1 peripherals
HSI RC x1 or x2
to TIMx
16 MHz x=2,6,7
LSE
HSI16
SYSCLK to USARTx
x=2..3
to LPUART1
MSI RC HSI16
SYSCLK to I2Cx
100 kHz – 48 MHz x=1,2,3
LSI
LSE to LPTIMx
HSI16 x=1,2
MSI PCLK2
HSI16
PLL /M HSE APB2 PRESC
to APB2 peripherals
/P / 1,2,4,8,16
/Q PLL48M1CLK x1 or x2
to TIMx
/R PLLCLK
x=1,15,16
LSE
HSI16 to
SYSCLK USART1
MSI
48 MHz clock to USB, RNG
HSI RC
48 MHz to ADCx, x=1,2
SYSCLK
CRS
MSv46900V3
DS12469 Rev 9 35/198

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3.12 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.13 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 7: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 14 channels in total, each dedicated to managing memory
access requests from one or more peripherals. Each has an arbiter for handling the priority
between DMA requests.
The DMA supports:
• 14 independently configurable channels (requests)
• Each channel is connected to dedicated hardware DMA requests, software trigger is
also supported on each channel. This configuration is done by software.
• Priorities between requests from channels of one DMA are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(example: request 1 has priority over request 2)
• Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
• Support for circular buffer management
• 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
• Memory-to-memory transfer
• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
• Access to flash, SRAM, APB and AHB peripherals as source and destination
• Programmable number of data to be transferred: up to 65536.
Table 7. DMA implementation

DMA features DMA1 DMA2
Number of regular channels 7 7
36/198 DS12469 Rev 9

3.14 Interrupts and events
3.14.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4.
The NVIC benefits are the following:
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 37 edge detector lines used to generate
interrupt/event requests and wake-up the system from Stop mode. Each external line can be
independently configured to select the trigger event (rising edge, falling edge, both) and can
be masked independently. A pending register maintains the status of the interrupt requests.
The internal lines are connected to peripherals with wakeup from Stop mode capability. The
EXTI can detect an external line with a pulse width shorter than the internal clock period. Up
to 52 GPIOs can be connected to the 16 external interrupt lines.
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3.15 Analog to digital converter (ADC)

The device embeds 2 successive approximation analog-to-digital converter with the
following features:
• 12-bit native resolution, with built-in calibration
• 5.33 Msps maximum conversion rate with full resolution
– Down to 18.75 ns sampling time
– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
• Up to 16 external channels, some of them shared between ADC1 and ADC2.
• 3 internal channels: internal reference voltage, temperature sensor, VBAT/3.
• One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
• Single-ended and differential mode inputs
• Low-power design
– Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
• Highly versatile digital interface
– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
– Handles two ADC converters for dual mode operation (simultaneous or
interleaved sampling modes)
– Each ADC supports multiple trigger inputs for synchronization with on-chip timers
and external signals
– Results stored into 2 data register or in RAM with DMA controller support
– Data pre-processing: left/right alignment and per channel offset compensation
– Built-in oversampling unit for enhanced SNR
– Channel-wise programmable sampling time
– Three analog watchdog for automatic voltage monitoring, generating interrupts
and trigger for selected timers
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching
3.15.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
38/198 DS12469 Rev 9

Table 8. Temperature sensor calibration values

Calibration value name Description Memory address
TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF 75A8 - 0x1FFF 75A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 130 °C (± 5 °C), 0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.15.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Table 9. Internal voltage reference calibration values

Calibration value name Description Memory address
Raw data acquired at a

VREFINT temperature of 30 °C (± 5 °C), 0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.15.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC1_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 3. As a consequence, the converted digital value is one third the VBAT voltage.
3.16 Comparators (COMP)

The STM32L412xx devices embed one rail-to-rail comparator with programmable reference
voltage (internal or external), hysteresis and speed (low speed for low-power) and with
selectable output polarity.
The reference voltage can be one of the following:
• External I/O
• Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can be also combined into a window comparator.
3.17 Operational amplifier (OPAMP)

The STM32L412xx embeds one operational amplifier with external or internal follower
routing and PGA capability.
DS12469 Rev 9 39/198

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The operational amplifier features:

• Low input bias current
• Low offset voltage
• Low-power mode
• Rail-to-rail input
3.18 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode which is protected from direct touch by a dielectric (such as
glass or plastic). The capacitive variation introduced by the finger (or any conductive object)
is measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
The main features of the touch sensing controller are the following:
• Proven and robust surface charge transfer acquisition principle
• Supports up to 12 capacitive sensing channels
• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
3.19 True random number generator (RNG)

The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
40/198 DS12469 Rev 9

3.20 Timers and watchdogs

The STM32L412xx includes one advanced control timers, up to five general-purpose timers,
two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table
below compares the features of the advanced control, general purpose and basic timers.
Table 10. Timer feature comparison

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Any integer
Advanced Up, down,
TIM1 16-bit between 1 Yes 4 3
control Up/down
and 65536
Any integer
General- Up, down,
TIM2 32-bit between 1 Yes 4 No
purpose Up/down
and 65536
Any integer
General-
TIM15 16-bit Up between 1 Yes 2 1
purpose
and 65536
Any integer
General-
TIM16 16-bit Up between 1 Yes 1 1
purpose
and 65536
Any integer
Basic TIM6 16-bit Up between 1 Yes 0 No
and 65536
3.20.1 Advanced-control timer (TIM1)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers. The 4 independent
channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.20.2) using the same architecture, so the advanced-control timer can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
DS12469 Rev 9 41/198

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3.20.2 General-purpose timers (TIM2, TIM15, TIM16)

There are up to three synchronizable general-purpose timers embedded in the
STM32L412xx (see Table 10 for differences). Each general-purpose timer can be used to
generate PWM outputs, or act as a simple time base.
• TIM2
It is a full-featured general-purpose timers:
– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.
This timers feature 4 independent channels for input capture/output compare, PWM or
one-pulse mode output. They can work with the other general-purpose timers via the
Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoder.
• TIM15 and 16
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has 2 channels and 1 complementary channel
– TIM16 has 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.20.3 Basic timer (TIM6)

The basic timer can be used as generic 16-bit timebase.
3.20.4 Low-power timer (LPTIM1 and LPTIM2)

The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wakeup the system from Stop mode.
Both LPTIM1 and LPTIM2 are active in Stop 0, Stop 1 and Stop 2 modes.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/ one shot mode
• Selectable software/hardware input trigger
• Selectable clock source
– Internal clock sources: LSE, LSI, HSI16 or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
• Programmable digital glitch filter
• Encoder mode (LPTIM1 only)
42/198 DS12469 Rev 9

3.20.5 Infrared interface (IRTIM)

The STM32L412xx includes one infrared interface (IRTIM), which can be used with an
infrared LED to perform remote control functions. It uses TIM15 and TIM16 output channels
to generate output signal waveforms on IR_OUT pin.
3.20.6 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.20.7 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.20.8 SysTick timer

This timer is dedicated to real-time operating systems, but can also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source
DS12469 Rev 9 43/198

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3.21 Real-time clock (RTC) and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Two anti-tamper detection pins with programmable filter.
• Timestamp feature, which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
44/198 DS12469 Rev 9

3.22 Inter-integrated circuit interface (I2C)

The device embeds three I2C. Refer to Table 11: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 5: Clock tree.
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 11. I2C implementation

I2C features(1) I2C1 I2C2 I2C3
Standard-mode (up to 100 kbit/s) X X X

Fast-mode (up to 400 kbit/s) X X X
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X
Programmable analog and digital noise filters X X X
SMBus/PMBus hardware support X X X
Independent clock X X X
Wakeup from Stop 1 mode on address match X X X
Wakeup from Stop 2 mode on address match - - X
1. X: supported
DS12469 Rev 9 45/198

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3.23 Universal synchronous/asynchronous receiver transmitter

(USART)
The STM32L412xx devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable, and are able to communicate at speeds of up to
10 Mbit/s.
USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and
SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake
up events from Stop mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 12. STM32L412xx USART/UART/LPUART features

USART modes/features(1) USART1 USART2 USART3 LPUART1
Hardware flow control for modem X X X X

Continuous communication using DMA X X X X
Multiprocessor communication X X X X
Synchronous mode X X X -
Smartcard mode X X X -
Single-wire half-duplex communication X X X X
IrDA SIR ENDEC block X X X -
LIN mode X X X -
Dual clock domain X X X X
Wakeup from Stop 0 / Stop 1 modes X X X X
Wakeup from Stop 2 mode - - - X
Receiver timeout interrupt X X X -
Modbus communication X X X -
Auto baud rate detection X (4 modes) -
Driver Enable X X X X
LPUART/USART data length 7, 8 and 9 bits
1. X = supported.
46/198 DS12469 Rev 9

3.24 Low-power universal asynchronous receiver transmitter

(LPUART)
The device embeds one Low-Power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.
DS12469 Rev 9 47/198

50
3.25 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 40 Mbits/s in master and slave modes, in
half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI interfaces
support NSS pulse mode, TI mode and Hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
3.26 Universal serial bus (USB)

The STM32L412xx devices embed a full-speed USB device peripheral compliant with the
USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has software-
configurable endpoint setting with packet memory up-to 1 KB and suspend/resume support.
It requires a precise 48 MHz clock which can be generated from the internal main PLL (the
clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in
automatic trimming mode. The synchronization for this oscillator can be taken from the USB
data stream itself (SOF signalization) which allows crystal less operation.
3.27 Clock recovery system (CRS)

The STM32L412xx devices embed a special block which allows automatic trimming of the
internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device
operational range. This automatic trimming is based on the external synchronization signal,
which could be either derived from LSE oscillator, from an external signal on CRS_SYNC
pin or generated by user software. For faster lock-in during startup it is also possible to
combine automatic trimming with manual trimming action.
3.28 Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI
flash memories. It can operate in any of the three following modes:
• Indirect mode: all the operations are performed using the QUADSPI registers
• Status polling mode: the external flash memory status register is periodically read and
an interrupt can be generated in case of flag setting
• Memory-mapped mode: the external flash is memory mapped and is seen by the
system as if it were an internal memory
48/198 DS12469 Rev 9

The Quad SPI interface supports:

• Three functional modes: indirect, status-polling, and memory-mapped
• Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two
flash memories in parallel.
• SDR and DDR support
• Fully programmable opcode for both indirect and memory mapped mode
• Fully programmable frame format for both indirect and memory mapped mode
• Each of the five following phases can be configured independently (enable, length,
single/dual/quad communication)
– Instruction phase
– Address phase
– Alternate bytes phase
– Dummy cycles phase
– Data phase
• Integrated FIFO for reception and transmission
• 8, 16, and 32-bit data accesses are allowed
• DMA channel for indirect mode operations
• Programmable masking for external flash flag management
• Timeout management
• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
DS12469 Rev 9 49/198

50
3.29 Development support
3.29.1 Serial wire JTAG debug port (SWJ-DP)

The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins
can be reused as GPIO with alternate function): the JTAG TMS and TCK pins are shared
with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.29.2 Embedded Trace Macrocell™

The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L412xx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell™ operates with third party debugger software tools.
50/198 DS12469 Rev 9

STM32L412xx Pinouts and pin description
4 Pinouts and pin description
Figure 6. STM32L412Rx LQFP64 pinout(1)
PH3-BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD2
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
LQFP64
PC1 9 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
VDDA/VREF+ 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD
PC4
PC5
PB0
PB1
PB2
VSS
PB10
VDD
PA3
PA4
PA5
PA6
PA7
PB11
MSv46920V1
1. The above figure shows the package top view.
Figure 7. STM32L412Rx, external SMPS, LQFP64 pinout(1)

PH3-BOOT0
VDD12
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD
PC4
PB0
PB1
PB2
PB10
VDD12
VSS
VDD
PA3
PA4
PA5
PA6
PA7
PB11
MS46959V1
DS12469 Rev 9 51/198

74
Pinouts and pin description STM32L412xx
Figure 8. STM32L412Rx UFBGA64 ballout(1)

1 2 3 4 5 6 7 8
PC14-
A PC13 PB9 PB4 PB3 PA15 PA14 PA13
OSC32_IN
PC15-
B VBAT PB8 PH3-BOOT0 PD2 PC11 PC10 PA12
OSC32_OUT
C PH0-OSC_IN VSS PB7 PB5 PC12 PA10 PA9 PA11
PH1-
D VDD PB6 VSS VSS VSS PA8 PC9
OSC_OUT
E NRST PC1 PC0 VDD VDDUSB VDD PC7 PC8
F VSSA/VREF- PC2 PA2 PA5 PB0 PC6 PB15 PB14
G PC3 PA0 PA3 PA6 PB1 PB2 PB10 PB13
H VDDA/VREF+ PA1 PA4 PA7 PC4 PC5 PB11 PB12
MSv46919V1
Figure 9. STM32L412Rx UFBGA64, external SMPS, ballout(1)

1 2 3 4 5 6 7 8
PC14-
A PC13 PB9 PB4 PB3 PA15 PA14 PA13
OSC32_IN
PC15-
B VBAT PB8 PH3-BOOT0 VDD12 PC11 PC10 PA12
OSC32_OUT
C PH0-OSC_IN VSS PB7 PB5 PC12 PA10 PA9 PA11
PH1-
D VDD PB6 VSS VSS VSS PA8 PC9
OSC_OUT
E NRST PC1 PC0 VDD VDDUSB VDD PC7 PC8
F VSSA/VREF- PC2 PA2 PA5 PB0 PC6 PB15 PB14
G PC3 PA0 PA3 PA6 PB1 PB2 PB10 PB13
H VDDA/VREF+ PA1 PA4 PA7 PC4 VDD12 PB11 PB12
MS53656V1
52/198 DS12469 Rev 9

Figure 10. STM32L412Cx LQFP48 pinout(1)
PH3/BOOT0
PA15
PA14
VDD
VSS
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDDUSB
PC13 2 35 VSS
PC14/OSC32_IN 3 34 PA13
PC15/OSC32_OUT 4 33 PA12
PH0/OSC_IN 5 32 PA11
PH1/OSC_OUT 6 31 PA10
LQFP48
NRST 7 30 PA9
VSSA 8 29 PA8
VDDA 9 28 PB15
PA0/CK_IN 10 27 PB14
PA1 11 26 PB13
PA2 12 13 25 PB12
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
VSS
PB10
VDD
PA3
PA4
PA5
PA6
PA7
PB11
MSv46916V1
Figure 11. STM32L412Cx LQFP48, external SMPS, pinout(1)

PH3-BOOT0
VDD12
PA15
PA14
VDD
VSS
PB9
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDDUSB
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
NRST 7
LQFP48 30 PA9
VSSA/VREF- 8 29 PA8
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10
VDD12
VSS
VDD
PA3
PA4
PA5
PA6
PA7
MSv71417V1
DS12469 Rev 9 53/198

74
Figure 12. STM32L412Cx UFQFPN48 pinout(1)
PH3-BOOT0
PA15
PA14
VDD
VSS
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDDUSB
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
NRST 7
UFQFPN48 30 PA9
VSSA/VREF- 8 29 PA8
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10
VSS
VDD
PA3
PA4
PA5
PA6
PA7
PB11
MSv46917V2
Figure 13. STM32L412Cx UFQFPN48, external SMPS, pinout(1)

PH3-BOOT0
VDD12
PA15
PA14
VDD
VSS
PB9
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDDUSB
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
NRST 7
UFQFPN48 30 PA9
VSSA/VREF- 8 29 PA8
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
PB10
VDD12
VSS
VDD
PA3
PA4
PA5
PA6
PA7
MSv71418V1
54/198 DS12469 Rev 9

Figure 14. STM32L412Tx WLCSP36 ballout(1)

1 2 3 4 5 6
A PA12 PA14 PB4 PB7 VSS VDD
B PA11 PA13 PB3 PB6 PB8 PC14
PH3
C PA9 PA10 PA15 PB5
BOOT0
PC15
D PA8 PB1 PA6 PA1 PA0 NRST
E VDD PB2 PA7 PA5 PA2 VREF+
F VSS PB10 PB0 PA4 PA3 VDDA
MS49688V1
Figure 15. STM32L412Tx, external SMPS, WLCSP36 ballout(1)
1 2 3 4 5 6
A PA12 PA14 PB4 PB7 VSS VDD
B PA11 PA13 PB3 PB6 VDD12 PC14
C PA9 PA10 PA15 PB5 PH3 PC15
D PA8 PB1 PA6 PA2 PA1 NRST
VDDA/
E VDD PB10 PB0 PA5 PA3
VREF+
F VSS VDD12 PB2 PA7 PA4 PA0
MS51459V1
DS12469 Rev 9 55/198

74
Figure 16. STM32L412Kx LQFP32 pinout(1)
PH3-BOOT0
PA15
VSS
PB7
PB6
PB5
PB4
PB3
32
31
30
29
28
27
26
25
VDD 1 24 PA14
PC14-OSC32_IN 2 23 PA13
NRST 4 21 PA11
LQFP32
VDDA/VREF+ 5 20 PA10
PA0-CK_IN 6 19 PA9
PA1 7 18 PA8
PA2 8 17 VDD
10
12
13
14
15
16
11
9
PB0
PB1
VSS
PA3
PA4
PA5
PA6
PA7
MSv46914V1
Figure 17. STM32L412Kx UFQFPN32 pinout(1)

PH3-BOOT0
PA15
VSS
PB7
PB6
PB5
PB4
PB3
32
31
30
29
28
27
26
25
VDD 1 24 PA14
PC14-OSC32_IN 2 23 PA13
NRST 4 21 PA11
VDDA/VREF+ 5
UFQFPN32 20 PA10
PA0-CK_IN 6 19 PA9
PA1 7 18 PA8
PA2 8 17 VDD
10
12
13
14
15
16
11
9
PB0
PB1
VSS
PA3
PA4
PA5
PA6
PA7
MSv46915V2
56/198 DS12469 Rev 9

Table 13. Legend/abbreviations used in the pinout table

Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
RST Bidirectional reset pin with embedded weak pull-up resistor
I/O structure Option for TT or FT I/Os
_f (1) I/O, Fm+ capable

_u (2)
I/O, with USB function supplied by VDDUSB
(3)
_a I/O, with Analog switch function supplied by VDDA
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 14 are: FT_f, FT_fa.
2. The related I/O structures in Table 14 are: FT_u, FT_fu.
3. The related I/O structures in Table 14 are: FT_a, FT_fa, TT_a.
Note: FT_a and FT_fa pins can be connected to analog peripherals inputs. When analog
peripheral is not connected to this FT_a or FT_fa pins (analog switch from GPIO to
peripheral is not closed, for example ADC not uses given pin as ADC input), then GPIO can
accept VDD + 3.6 V (5 V tolerant I/O). However, once the I/O input is connected to the
analog peripheral (for example ADC selects as input channel from this pin), the parasitic
diode from this I/O pin to VDDA and/or VREF+ does not allow to use higher voltage on given
I/O pin than VDDA or VREF+ and pin is no more 5 V-tolerant I/O.
DS12469 Rev 9 57/198

74
58/198
Pinouts and pin description

Table 14. STM32L412xx pin definitions
Pin Number
UFQFPN48 SMPS
I/O structure
WLCSP36 SMPS
UFBGA64 SMPS
LQFP48 SMPS
LQFP64 SMPS
Pin name
Pin type
UFQFPN32
UFQFPN48
Notes
WLCSP36
UFBGA64
LQFP32
LQFP48
LQFP64
(function after Alternate functions Additional functions
reset)
- - - - 1 1 1 1 1 1 B2 B2 VBAT S - - - -
(1)
RTC_TAMP1/RTC_TS/RT
- - - - 2 2 2 2 2 2 A2 A2 PC13 I/O FT (2) EVENTOUT
C_OUT1/WKUP2
(1)
PC14-OSC32_IN
2 2 B6 B6 3 3 3 3 3 3 A1 A1 I/O FT (2) EVENTOUT OSC32_IN
(PC14)
PC15- (1)
3 3 C6 C6 4 4 4 4 4 4 B1 B1 OSC32_OUT I/O FT EVENTOUT OSC32_OUT
DS12469 Rev 9
(2)
(PC15)
PH0-OSC_IN
- - - - 5 5 5 5 5 5 C1 C1 I/O FT - EVENTOUT OSC_IN
(PH0)
PH1-OSC_OUT
- - - - 6 6 6 6 6 6 D1 D1 I/O FT - EVENTOUT OSC_OUT
(PH1)
4 4 D6 D6 7 7 7 7 7 7 E1 E1 NRST I/O RST - - -
TRACECK, LPTIM1_IN1,
- - - - - - - - 8 8 E3 E3 PC0 I/O FT_fa - I2C3_SCL, LPUART1_RX, ADC12_IN1
LPTIM2_IN1, EVENTOUT
TRACED0, LPTIM1_OUT,
- - - - - - - - 9 9 E2 E2 PC1 I/O FT_fa - I2C3_SDA, LPUART1_TX, ADC12_IN2
EVENTOUT
LPTIM1_IN2, SPI2_MISO,
- - - - - - - - 10 10 F2 F2 PC2 I/O FT_a - ADC12_IN3
EVENTOUT
LPTIM1_ETR, SPI2_MOSI,
STM32L412xx
- - - - - - - - 11 11 G1 G1 PC3 I/O FT_a - ADC12_IN4
LPTIM2_ETR, EVENTOUT
- - - - 8 8 8 8 12 12 F1 F1 VSSA/VREF- S - - - -
- - - E6 - - - - - - - - VREF+ S - - - -
Table 14. STM32L412xx pin definitions (continued)
STM32L412xx
Pin Number
UFQFPN48 SMPS
I/O structure
WLCSP36 SMPS
UFBGA64 SMPS
LQFP48 SMPS
LQFP64 SMPS
Pin name
Pin type
UFQFPN32
UFQFPN48
Notes
WLCSP36
UFBGA64
LQFP32
LQFP48
LQFP64
reset)
- - - F6 - - - - - - - - VDDA S - - - -
5 5 E6 - 9 9 9 9 13 13 H1 H1 VDDA/VREF+ S - - - -
TIM2_CH1, USART2_CTS, OPAMP1_VINP,
- - - - 10 10 10 10 14 14 G2 G2 PA0 I/O FT_a - COMP1_OUT, TIM2_ETR, COMP1_INM, ADC1_IN5,
EVENTOUT RTC_TAMP2/WKUP1
OPAMP1_VINP,
TIM2_CH1, USART2_CTS,
COMP1_INM, ADC1_IN5,
6 6 F6 D5 - - - - - - - - PA0-CK_IN I/O FT_a - COMP1_OUT, TIM2_ETR,
DS12469 Rev 9
RTC_TAMP2/WKUP1,
EVENTOUT
CK_IN
TIM2_CH2, I2C1_SMBA,
SPI1_SCK, OPAMP1_VINM,
7 7 D5 D4 11 11 11 11 15 15 H2 H2 PA1 I/O FT_a -
USART2_RTS_DE, COMP1_INP, ADC1_IN6
TIM15_CH1N, EVENTOUT
TIM2_CH3, USART2_TX,
LPUART1_TX, ADC12_IN7,
8 8 D4 E5 12 12 12 12 16 16 F3 F3 PA2 I/O FT_a -
QUADSPI_BK1_NCS, WKUP4/LSCO
TIM15_CH1, EVENTOUT
TIM2_CH4, USART2_RX,

LPUART1_RX, OPAMP1_VOUT,
9 9 E5 F5 13 13 13 13 17 17 G3 G3 PA3 I/O TT_a -
QUADSPI_CLK, ADC12_IN8
TIM15_CH2, EVENTOUT
- - - - - - - - 18 18 C2 C2 VSS S - - - -
- - - - - - - - 19 19 D2 D2 VDD S - - - -
SPI1_NSS, USART2_CK,
10 10 F5 F4 14 14 14 14 20 20 H3 H3 PA4 I/O TT_a - COMP1_INM, ADC12_IN9
LPTIM2_OUT, EVENTOUT
59/198
60/198

Pin Number
UFQFPN48 SMPS
I/O structure
WLCSP36 SMPS
UFBGA64 SMPS
LQFP48 SMPS
LQFP64 SMPS
Pin name
Pin type
UFQFPN32
UFQFPN48
Notes
WLCSP36
UFBGA64
LQFP32
LQFP48
LQFP64
reset)
TIM2_CH1, TIM2_ETR,
COMP1_INM,
11 11 E4 E4 15 15 15 15 21 21 F4 F4 PA5 I/O TT_a - SPI1_SCK, LPTIM2_ETR,
ADC12_IN10
EVENTOUT
TIM1_BKIN, SPI1_MISO,
COMP1_OUT,
USART3_CTS,
12 12 D3 D3 16 16 16 16 22 22 G4 G4 PA6 I/O FT_a - ADC12_IN11
LPUART1_CTS,
QUADSPI_BK1_IO3,
DS12469 Rev 9
TIM16_CH1, EVENTOUT
TIM1_CH1N, I2C3_SCL,
SPI1_MOSI,
13 13 F4 E3 17 17 17 17 23 23 H4 H4 PA7 I/O FT_fa - ADC12_IN12
QUADSPI_BK1_IO2,
EVENTOUT
COMP1_INM,
- - - - - - - - 24 24 H5 H5 PC4 I/O FT_a - USART3_TX, EVENTOUT
ADC12_IN13
- - - - - - - - - 25 - H6 PC5 I/O FT_a - USART3_RX, EVENTOUT COMP1_INP, ADC12_IN14
TRACED0, TIM1_CH2N,
14 14 E3 F3 18 18 18 18 25 26 F5 F5 PB0 I/O FT_a - ADC12_IN15
QUADSPI_BK1_IO1,
COMP1_OUT, EVENTOUT
TRACED1, TIM1_CH3N,
USART3_RTS_DE,
COMP1_INM,
15 15 D2 D2 19 19 19 19 26 27 G5 G5 PB1 I/O FT_a - LPUART1_RTS_DE,
ADC12_IN16
QUADSPI_BK1_IO0,
STM32L412xx
LPTIM2_IN1, EVENTOUT
LPTIM1_OUT, I2C3_SMBA,
- - F3 E2 20 20 20 20 27 28 G6 G6 PB2 I/O FT_a - RTC_OUT2, COMP1_INP
EVENTOUT
STM32L412xx
Pin Number
UFQFPN48 SMPS
I/O structure
WLCSP36 SMPS
UFBGA64 SMPS
LQFP48 SMPS
LQFP64 SMPS
Pin name
Pin type
UFQFPN32
UFQFPN48
Notes
WLCSP36
UFBGA64
LQFP32
LQFP48
LQFP64
reset)
TIM2_CH3, I2C2_SCL,
SPI2_SCK, USART3_TX,
- - E2 F2 21 21 21 21 28 29 G7 G7 PB10 I/O FT_f - LPUART1_RX, TSC_SYNC, -
QUADSPI_CLK,
COMP1_OUT, EVENTOUT
TIM2_CH4, I2C2_SDA,
USART3_RX, LPUART1_TX,
- - - - - 22 - 22 29 30 H7 H7 PB11 I/O FT_f - -
QUADSPI_BK1_NCS,
DS12469 Rev 9
EVENTOUT
- - F2 - 22 - 22 - 30 - H6 - VDD12 S - - - -
16 16 F1 F1 23 23 23 23 31 31 D6 D6 VSS S - - - -
17 17 E1 E1 24 24 24 24 32 32 E6 E6 VDD S - - - -
TIM1_BKIN, I2C2_SMBA,
- - - - 25 25 25 25 33 33 H8 H8 PB12 I/O FT - LPUART1_RTS_DE, -
TSC_G1_IO1, TIM15_BKIN,
EVENTOUT
TIM1_CH1N, I2C2_SCL,

SPI2_SCK, USART3_CTS,
- - - - 26 26 26 26 34 34 G8 G8 PB13 I/O FT_f - LPUART1_CTS, -
TSC_G1_IO2, TIM15_CH1N,
EVENTOUT
TIM1_CH2N, I2C2_SDA,
SPI2_MISO,
- - - - 27 27 27 27 35 35 F8 F8 PB14 I/O FT_f - USART3_RTS_DE, -
TSC_G1_IO3, TIM15_CH1,
EVENTOUT
61/198
62/198

Pin Number
UFQFPN48 SMPS
I/O structure
WLCSP36 SMPS
UFBGA64 SMPS
LQFP48 SMPS
LQFP64 SMPS
Pin name
Pin type
UFQFPN32
UFQFPN48
Notes
WLCSP36
UFBGA64
LQFP32
LQFP48
LQFP64
reset)
RTC_REFIN, TIM1_CH3N,
- - - - 28 28 28 28 36 36 F7 F7 PB15 I/O FT - SPI2_MOSI, TSC_G1_IO4, -
TIM15_CH2, EVENTOUT
- - - - - - - - 37 37 F6 F6 PC6 I/O FT - TSC_G4_IO1, EVENTOUT -
- - - - - - - - 38 38 E7 E7 PC7 I/O FT - TSC_G4_IO2, EVENTOUT -
- - - - - - - - 39 39 E8 E8 PC8 I/O FT - TSC_G4_IO3, EVENTOUT -
TSC_G4_IO4, USB_NOE,
- - - - - - - - 40 40 D8 D8 PC9 I/O FT - -
DS12469 Rev 9
EVENTOUT
MCO, TIM1_CH1,
18 18 D1 D1 29 29 29 29 41 41 D7 D7 PA8 I/O FT - USART1_CK, LPTIM2_OUT, -
EVENTOUT
TIM1_CH2, I2C1_SCL,
19 19 C1 C1 30 30 30 30 42 42 C7 C7 PA9 I/O FT_f - USART1_TX, TIM15_BKIN, -
EVENTOUT
TIM1_CH3, I2C1_SDA,
USART1_RX,
20 20 C2 C2 31 31 31 31 43 43 C6 C6 PA10 I/O FT_f - -
USB_CRS_SYNC,
EVENTOUT
TIM1_CH4, TIM1_BKIN2,
SPI1_MISO, COMP1_OUT,
21 21 B1 B1 32 32 32 32 44 44 C8 C8 PA11 I/O FT_u - USART1_CTS, USB_DM, -
TIM1_BKIN2_COMP1,
EVENTOUT
STM32L412xx
TIM1_ETR, SPI1_MOSI,
22 22 A1 A1 33 33 33 33 45 45 B8 B8 PA12 I/O FT_u - USART1_RTS_DE, -
USB_DP, EVENTOUT
STM32L412xx
Pin Number
UFQFPN48 SMPS
I/O structure
WLCSP36 SMPS
UFBGA64 SMPS
LQFP48 SMPS
LQFP64 SMPS
Pin name
Pin type
UFQFPN32
UFQFPN48
Notes
WLCSP36
UFBGA64
LQFP32
LQFP48
LQFP64
reset)
PA13 JTMS/SWDIO, IR_OUT,

23 23 B2 B2 34 34 34 34 46 46 A8 A8 I/O FT - -
(JTMS/SWDIO) USB_NOE, EVENTOUT
- - - - 35 35 35 35 47 47 D5 D5 VSS S - - - -
- - - - 36 36 36 36 48 48 E5 E5 VDDUSB S - - - -
JTCK/SWCLK,
PA14
24 24 A2 A2 37 37 37 37 49 49 A7 A7 I/O FT - LPTIM1_OUT, I2C1_SMBA, -
(JTCK/SWCLK)
EVENTOUT
DS12469 Rev 9
JTDI, TIM2_CH1,
TIM2_ETR, USART2_RX,
25 25 C3 C3 38 38 38 38 50 50 A6 A6 PA15 (JTDI) I/O FT - SPI1_NSS, -
USART3_RTS_DE,
TSC_G3_IO1, EVENTOUT
TRACED1, USART3_TX,
- - - - - - - - 51 51 B7 B7 PC10 I/O FT - -
USART3_RX, TSC_G3_IO3,
- - - - - - - - 52 52 B6 B6 PC11 I/O FT - -
EVENTOUT
TRACED3, USART3_CK,
- - - - - - - - 53 53 C5 C5 PC12 I/O FT - -

TRACED2,
- - - - - - - - - 54 - B5 PD2 I/O FT - USART3_RTS_DE, -
TSC_SYNC, EVENTOUT
JTDO/TRACESWO,
PB3
TIM2_CH2, SPI1_SCK,
26 26 B3 B3 39 39 39 39 54 55 A5 A5 (JTDO/TRACESW I/O FT_a - -
USART1_RTS_DE,
O)
EVENTOUT
63/198
64/198

Pin Number
UFQFPN48 SMPS
I/O structure
WLCSP36 SMPS
UFBGA64 SMPS
LQFP48 SMPS
LQFP64 SMPS
Pin name
Pin type
UFQFPN32
UFQFPN48
Notes
WLCSP36
UFBGA64
LQFP32
LQFP48
LQFP64
reset)
NJTRST, I2C3_SDA,
27 27 A3 A3 40 40 40 40 55 56 A4 A4 PB4 (NJTRST) I/O FT_fa - SPI1_MISO, USART1_CTS, -
TRACED2, LPTIM1_IN1,
I2C1_SMBA, SPI1_MOSI,
28 28 C4 C4 41 41 41 41 56 57 C4 C4 PB5 I/O FT - -
USART1_CK, TSC_G2_IO2,
TIM16_BKIN, EVENTOUT
TRACED3, LPTIM1_ETR,
DS12469 Rev 9
I2C1_SCL, USART1_TX,
29 29 B4 B4 42 42 42 42 57 58 D3 D3 PB6 I/O FT_fa - -
TSC_G2_IO3, TIM16_CH1N,
EVENTOUT
TRACECK, LPTIM1_IN2,
30 30 A4 A4 43 43 43 43 58 59 C3 C3 PB7 I/O FT_fa - I2C1_SDA, USART1_RX, PVD_IN
PH3-BOOT0
31 31 C5 C5 44 44 44 44 59 60 B4 B4 I/O FT - EVENTOUT -
(BOOT0)
I2C1_SCL, TIM16_CH1,
- - - B5 - 45 - 45 60 61 B3 B3 PB8 I/O FT_f - -
EVENTOUT
IR_OUT, I2C1_SDA,
- - - - 45 46 45 46 61 62 A3 A3 PB9 I/O FT_f - -
SPI2_NSS, EVENTOUT
- - B5 - 46 - 46 - 62 - B5 - VDD12 S - - - -
32 32 A5 A5 47 47 47 47 63 63 D4 D4 VSS S - - - -
1 1 A6 A6 48 48 48 48 64 64 E4 E4 VDD S - - - -
STM32L412xx
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output
mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (for example to drive a LED).
STM32L412xx
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers which are not reset by the
system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC register descriptions in RM0394 reference manual.
Table 15. Alternate function AF0 to AF7(1)

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Port
TIM1/TIM2/LPT USART1/USA
SYS_AF TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 COMP1
IM1 RT2/USART3
PA0 - TIM2_CH1 - - - - - USART2_CTS

USART2_RTS_
PA1 - TIM2_CH2 - - I2C1_SMBA SPI1_SCK -
DE
PA2 - TIM2_CH3 - - - - - USART2_TX
PA3 - TIM2_CH4 - - - - - USART2_RX
PA4 - - - - - SPI1_NSS - USART2_CK
DS12469 Rev 9
PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - -

PA6 - TIM1_BKIN - - - SPI1_MISO COMP1_OUT USART3_CTS
PA7 - TIM1_CH1N - - I2C3_SCL SPI1_MOSI - -
Port A PA8 MCO TIM1_CH1 - - - - - USART1_CK
PA9 - TIM1_CH2 - - I2C1_SCL - - USART1_TX
PA10 - TIM1_CH3 - - I2C1_SDA - - USART1_RX
PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO COMP1_OUT USART1_CTS
USART1_RTS_

PA12 - TIM1_ETR - - - SPI1_MOSI -
DE
PA13 JTMS/SWDIO IR_OUT - - - - - -
PA14 JTCK/SWCLK LPTIM1_OUT - - I2C1_SMBA - - -
USART3_RTS_
PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS -
DE
65/198
Table 15. Alternate function AF0 to AF7(1) (continued)
66/198

Port
IM1 RT2/USART3
PB0 TRACED0 TIM1_CH2N - - - SPI1_NSS - USART3_CK

USART3_RTS_
PB1 TRACED1 TIM1_CH3N - - - - -
DE
PB2 - LPTIM1_OUT - - I2C3_SMBA - - -
JTDO/TRACES USART1_RTS_
PB3 TIM2_CH2 - - - SPI1_SCK -
WO DE
PB4 NJTRST - - - I2C3_SDA SPI1_MISO - USART1_CTS
PB5 TRACED2 LPTIM1_IN1 - - I2C1_SMBA SPI1_MOSI - USART1_CK
PB6 TRACED3 LPTIM1_ETR - - I2C1_SCL - - USART1_TX
DS12469 Rev 9
Port B PB7 TRACECK LPTIM1_IN2 - - I2C1_SDA - - USART1_RX

PB8 - - - - I2C1_SCL - - -
PB9 - IR_OUT - - I2C1_SDA SPI2_NSS - -
PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK - USART3_TX
PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX
PB12 - TIM1_BKIN - - I2C2_SMBA SPI2_NSS - USART3_CK
PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK - USART3_CTS
USART3_RTS_
PB14 - TIM1_CH2N - - I2C2_SDA SPI2_MISO -
DE
PB15 RTC_REFIN TIM1_CH3N - - - SPI2_MOSI - -
STM32L412xx
STM32L412xx
Port
IM1 RT2/USART3
PC0 TRACECK LPTIM1_IN1 - - I2C3_SCL - - -

PC1 TRACED0 LPTIM1_OUT - - I2C3_SDA - - -
PC2 - LPTIM1_IN2 - - - SPI2_MISO - -
PC3 - LPTIM1_ETR - - - SPI2_MOSI - -
PC4 - - - - - - - USART3_TX
PC5 - - - - - - - USART3_RX
PC6 - - - - - - - -
PC7 - - - - - - - -
Port C
DS12469 Rev 9
PC8 - - - - - - - -
PC9 - - - - - - - -
PC10 TRACED1 - - - - - - USART3_TX
PC11 - - - - - - - USART3_RX
PC12 TRACED3 - - - - - - USART3_CK
PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -

USART3_RTS_
Port D PD2 TRACED2 - - - - - -
DE
PH0 - - - - - - - -
Port H PH1 - - - - - - - -
PH3 - - - - - - - -
1. Refer to Table 16 for AF8 to AF15.
67/198
Table 16. Alternate function AF8 to AF15(1)
68/198

Port
TIM2/TIM15/
LPUART1 TSC QUADSPI - COMP1 - EVENOUT
TIM16/LPTIM2
PA0 - - - - COMP1_OUT - TIM2_ETR EVENTOUT

PA1 - - - - - - TIM15_CH1N EVENTOUT
QUADSPI_BK1
PA2 LPUART1_TX - - - - TIM15_CH1 EVENTOUT
_NCS
PA3 LPUART1_RX - QUADSPI_CLK - - - TIM15_CH2 EVENTOUT
PA4 - - - - - - LPTIM2_OUT EVENTOUT
PA5 - - - - - - LPTIM2_ETR EVENTOUT
QUADSPI_BK1
PA6 LPUART1_CTS - - - - TIM16_CH1 EVENTOUT
_IO3
DS12469 Rev 9
QUADSPI_BK1
PA7 - - - - - - EVENTOUT
Port A _IO2
PA8 - - - - - - LPTIM2_OUT EVENTOUT
PA9 - - - - - - TIM15_BKIN EVENTOUT
USB_CRS_SY
PA10 - - - - - - EVENTOUT
NC
TIM1_BKIN2_C
PA11 - - USB_DM - - - EVENTOUT
OMP1
PA12 - - USB_DP - - - - EVENTOUT
PA13 - - USB_NOE - - - - EVENTOUT
PA14 - - - - - - - EVENTOUT
PA15 - TSC_G3_IO1 - - - - - EVENTOUT
STM32L412xx
STM32L412xx
Port
TIM2/TIM15/
TIM16/LPTIM2
QUADSPI_BK1
PB0 - - - COMP1_OUT - - EVENTOUT
_IO1
LPUART1_RTS QUADSPI_BK1
PB1 - - - - LPTIM2_IN1 EVENTOUT
_DE _IO0
PB2 - - - - - - - EVENTOUT
PB3 - - - - - - - EVENTOUT
PB4 - TSC_G2_IO1 - - - - - EVENTOUT
PB5 - TSC_G2_IO2 - - - - TIM16_BKIN EVENTOUT
PB6 - TSC_G2_IO3 - - - - TIM16_CH1N EVENTOUT
DS12469 Rev 9
PB7 - TSC_G2_IO4 - - - - - EVENTOUT

Port B
PB8 - - - - - - TIM16_CH1 EVENTOUT
PB9 - - - - - - - EVENTOUT
PB10 LPUART1_RX TSC_SYNC QUADSPI_CLK - COMP1_OUT - - EVENTOUT
QUADSPI_BK1
PB11 LPUART1_TX - - - - - EVENTOUT
_NCS
LPUART1_RTS
PB12 TSC_G1_IO1 - - - - TIM15_BKIN EVENTOUT
_DE

PB13 LPUART1_CTS TSC_G1_IO2 - - - - TIM15_CH1N EVENTOUT
PB14 - TSC_G1_IO3 - - - - TIM15_CH1 EVENTOUT
PB15 - TSC_G1_IO4 - - - - TIM15_CH2 EVENTOUT
69/198
70/198

Port
TIM2/TIM15/
TIM16/LPTIM2
PC0 LPUART1_RX - - - - - LPTIM2_IN1 EVENTOUT

PC1 LPUART1_TX - - - - - - EVENTOUT
PC2 - - - - - - - EVENTOUT
PC3 - - - - - - LPTIM2_ETR EVENTOUT
PC4 - - - - - - - EVENTOUT
PC5 - - - - - - - EVENTOUT
PC6 - TSC_G4_IO1 - - - - - EVENTOUT
Port C
DS12469 Rev 9

PC9 - TSC_G4_IO4 USB_NOE - - - - EVENTOUT
PC13 - - - - - - - EVENTOUT
PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT
Port D PD2 - TSC_SYNC - - - - - EVENTOUT
PH0 - - - - - - - EVENTOUT
Port H PH1 - - - - - - - EVENTOUT
PH3 - - - - - - - EVENTOUT
STM32L412xx
1. Refer to Table 15 for AF0 to AF7.
STM32L412xx Memory mapping
5 Memory mapping
Figure 18. STM32L412xx memory map
0xFFFF FFFF 0xBFFF FFFF

Cortex™-M4 Reserved
0xA000 1400
with FPU
7 QUADSPI registers
Internal
Peripherals 0xA000 1000
0xE000 0000
0x5FFF FFFF
Reserved
6
0x5006 0C00
AHB2
0x4800 0000
0xC000 0000 Reserved
0x4002 4400
QUADSPI AHB1
registers
5 0x4002 0000
Reserved
0xA000 1000
0x4001 5800
0xA000 0000 APB2
QUADSPI flash 0x4001 0000
bank Reserved
0x4000 9800
4 0x9000 0000
APB1
0x4000 0000
0x8000 0000 0x1FFF FFFF
3
Reserved
0x6000 0000
0x1FFF 7810
Options Bytes
2
0x1FFF 7800
Reserved
0x1FFF 7400
Peripherals OTP area
0x4000 0000
0x1FFF 7000
System memory
1 0x2000 A000 0x1FFF 0000
SRAM2 Reserved
0x2000 8000
0x1000 2000
SRAM1
0x2000 0000 SRAM2
0x1000 0000
Reserved
0 0x0802 0000
CODE
Flash memory
0x0800 0000
Reserved
0x0000 0000
0x0002 0000 Flash, system memory
or SRAM, depending on
0x0000 0000 BOOT configuration
Reserved
MSv45997V1
DS12469 Rev 9 71/198

74
Memory mapping STM32L412xx
Table 17. STM32L412xx memory map and peripheral register boundary addresses(1)
Bus Boundary address Size(bytes) Peripheral
0x5006 0800 - 0x5006 0BFF 1 KB RNG

0x5006 0400 - 0x5006 07FF 1 KB Reserved
0x5004 0400 - 5006 07FF 128 KB Reserved
0x5004 0000 - 0x5004 03FF 1 KB ADC
0x5000 0000 - 0x5003 FFFF 16 KB Reserved
0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved
AHB2 0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH
0x4800 1000 - 0x4800 1BFF 3 KB Reserved
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
- 0x4002 4400 - 0x47FF FFFF ~127 MB Reserved
0x4002 4000 - 0x4002 43FF 1 KB TSC
0x4002 3400 - 0x4002 3FFF 1 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
0x4002 2000 - 0x4002 23FF 1 KB FLASH registers
AHB1
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0400 - 0x4002 07FF 1 KB DMA2
0x4002 0000 - 0x4002 03FF 1 KB DMA1
72/198 DS12469 Rev 9

STM32L412xx Memory mapping
(continued)

0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 4000 - 0x4001 43FF 1 KB TIM15
0x4001 3C00 - 0x4001 3FFF 1 KB Reserved
0x4001 3800 - 0x4001 3BFF 1 KB USART1
0x4001 3400 - 0x4001 37FF 1 KB Reserved
0x4001 3000 - 0x4001 33FF 1 KB SPI1
APB2 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
0x4001 2000 - 0x4001 2BFF 3 KB Reserved
0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL
0x4001 0800- 0x4001 1BFF 5 KB Reserved
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0200 - 0x4001 03FF 1 KB COMP
0x4001 0030 - 0x4001 01FF 1 KB Reserved
0x4001 0000 - 0x4001 002F 1 KB SYSCFG
0x4000 9400 - 0x4000 97FF 1 KB LPTIM2
0x4000 8400 - 0x4000 93FF 4 KB Reserved
0x4000 8000 - 0x4000 83FF 1 KB LPUART1
0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1
0x4000 7800 - 0x4000 7BFF 1 KB OPAMP
0x4000 7400 - 0x4000 77FF 1 KB Reserved
0x4000 7000 - 0x4000 73FF 1 KB PWR
0x4000 6C00 - 0x4000 6FFF 1 KB USB SRAM
APB1 0x4000 6800 - 0x4000 6BFF 1 KB USB FS
0x4000 6400 - 0x4000 67FF 1 KB Reserved
0x4000 6000 - 0x4000 63FF 1 KB CRS
0x4000 5C00- 0x4000 5FFF 1 KB I2C3
0x4000 5800 - 0x4000 5BFF 1 KB I2C2
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 4C00 - 0x4000 53FF 2 KB Reserved
0x4000 4800 - 0x4000 4BFF 1 KB USART3
0x4000 4400 - 0x4000 47FF 1 KB USART2
0x4000 4000 - 0x4000 43FF 1 KB Reserved
DS12469 Rev 9 73/198

74
Memory mapping STM32L412xx
(continued)
0x4000 3C00 - 0x4000 3FFF 1 KB SPI3

0x4000 3800 - 0x4000 3BFF 1 KB SPI2
0x4000 3400 - 0x4000 37FF 1 KB Reserved
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
APB1
0x4000 2800 - 0x4000 2BFF 1 KB RTC
0x4000 1400 - 0x4000 27FF 5 KB Reserved
0x4000 1000 - 0x4000 13FF 1 KB TIM6
0x4000 0400- 0x4000 0FFF 3 KB Reserved
0x4000 0000 - 0x4000 03FF 1 KB TIM2
1. The gray color is used for reserved boundary addresses.
74/198 DS12469 Rev 9

STM32L412xx Electrical characteristics
6 Electrical characteristics
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 19.
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 20.
Figure 19. Pin loading conditions Figure 20. Pin input voltage
MCU pin MCU pin

C = 50 pF VIN
MS19210V1 MS19211V1
DS12469 Rev 9 75/198

165
Electrical characteristics STM32L412xx
6.1.6 Power supply scheme
Figure 21. Power supply scheme
VBAT
Backup circuitry
1.55 – 3.6 V (LSE, RTC,
Backup registers)
Power switch
VDD VCORE
n x VDD
Regulator
VDDIO1
OUT
Level shifter
Kernel logic
n x 100 nF IO (CPU, Digital
GPIOs logic
+1 x 4.7 μF IN & Memories)
n x VSS
VDDA
VDDA
VREF
10 nF VREF+ ADCs/
+1 μF OPAMPs/
100 nF +1 μF VREF- COMPs/
VSSA
MS49692V1
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
76/198 DS12469 Rev 9

6.1.7 Current consumption measurement
Figure 22. Current consumption measurement scheme with and without external
SMPS power supply
IDD_USB
VDDUSB
IDD_USB
VDDUSB
IDD_VBAT
VBAT
IDD_VBAT
VBAT
IDD
VDD12
SMPS
IDD
VDD VDD
IDDA IDDA
VDDA VDDA
MSv45729V1
The IDD_ALL parameters given in Table 25 to Table 47 represent the total MCU consumption
including the current supplying VDD, VDDA, VDDUSB and VBAT.
6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
Table 18. Voltage characteristics(1)

Symbol Ratings Min Max Unit
External main supply voltage (including VDD,

VDDX - VSS -0.3 4.0 V
VDDA, VDDUSB, VBAT, VREF+)
VDD12 - VSS External SMPS supply voltage -0.3 1.32 V
min (VDD, VDDA, VDDUSB)
Input voltage on FT_xxx pins VSS-0.3
+ 4.0(3)(4)
VIN(2) V
Input voltage on TT_xx pins VSS-0.3 4.0
Input voltage on any other pins VSS-0.3 4.0
Variations between different VDDX power pins of
|∆VDDx| - 50 mV
the same domain
DS12469 Rev 9 77/198

165
Table 18. Voltage characteristics(1) (continued)

Symbol Ratings Min Max Unit
|VSSx-VSS| (5)
Variations between all the different ground pins - 50 mV
VREF+ - VDDA Allowed voltage difference for VREF+ > VDDA - 0.4 V
1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected
current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 19. Current characteristics

Symbol Ratings Max Unit
∑IVDD Total current into sum of all VDD power lines (source)(1)(2) 140
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 140
IVDD(PIN) Maximum current into each VDD power pin (source) (1)
100
IVSS(PIN) Maximum current out of each VSS ground pin (sink) (1)
100
Output current sunk by any I/O and control pin except FT_f 20
IIO(PIN) Output current sunk by any FT_f pin 20
Output current sourced by any I/O and control pin 20 mA
Total output current sunk by sum of all I/Os and control pins(3) 100
∑IIO(PIN)
(3)
Total output current sourced by sum of all I/Os and control pins 100
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,
-5/+0(5)
IINJ(PIN)(4) PA5
Injected current on PA4, PA5 -5/0
∑|IINJ(PIN)| (6)
Total injected current (sum of all I/Os and control pins) 25
1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power
supplies, in the permitted range.
2. Valid also for VDD12 on SMPS packages.
3. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
4. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
5. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage
characteristics for the maximum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
Table 20. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C
78/198 DS12469 Rev 9

6.3 Operating conditions
6.3.1 General operating conditions
Table 21. General operating conditions

Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 80

fPCLK1 Internal APB1 clock frequency - 0 80 MHz
fPCLK2 Internal APB2 clock frequency - 0 80
1.71
VDD Standard operating voltage - (1) 3.6 V
ADC or COMP used 1.62

VDDA Analog supply voltage OPAMP used 1.8 3.6 V
ADC, OPAMP, COMP not used 0
Full frequency range 1.08
VDD12 Standard operating voltage 1.32 V
Up to 26 MHz 1.00
VBAT Backup operating voltage - 1.55 3.6 V
USB used 3.0 3.6
VDDUSB USB supply voltage V
USB not used 0 3.6
TT_xx I/O -0.3 VDDIOx+0.3
VIN I/O input voltage Min(Min(VDD, VDDA, V

All I/O except TT_xx -0.3 VDDUSB)+3.6 V,
5.5 V)(2)(3)
LQFP64 - 303
UFBGA64 - 317
Power dissipation at LQFP48 - 294
TA = 85 °C for suffix 6
PD UFQFPN48 - 667 mW
or
TA = 105 °C for suffix 7(4) WLCSP36 235
LQFP32 294
UFQFPN32 541
LQFP64 - 76
UFBGA64 - 79
LQFP48 - 75
Power dissipation at
PD UFQFPN48 - 167 mW
TA = 125 °C for suffix 3(4)
WLCSP36 - 59
LQFP32 - 75
UFQFPN32 - 135
DS12469 Rev 9 79/198

165
Table 21. General operating conditions (continued)

Ambient temperature for the Maximum power dissipation –40 85

suffix 6 version Low-power dissipation(5) –40 105
TA °C
Ambient temperature for the Maximum power dissipation –40 125
suffix 3 version Low-power dissipation(5) –40 130
Suffix 6 version –40 105
TJ Junction temperature range °C
Suffix 3 version –40 130
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, VDDUSB)+3.6 V and 5.5V.
3. For operation with voltage higher than Min (VDD, VDDA, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must
be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.8: Thermal characteristics).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8:
Thermal characteristics).
6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
Table 22. Operating conditions at power-up / power-down

VDD rise time rate - 0 ∞

µs/V
tVDD ULPEN = 0 10 ∞
VDD fall time rate
ULPEN = 1 100 ∞ ms/V
VDDA rise time rate 0 ∞
tVDDA -
VDDA fall time rate 10 ∞
µs/V
VDDUSB rise time rate 0 ∞
tVDDUSB -
VDDUSB fall time rate 10 ∞
6.3.3 Embedded reset and power control block characteristics

temperature conditions summarized in Table 21: General operating conditions.
Table 23. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit
Reset temporization after

tRSTTEMPO(2) VDD rising - 250 400 μs
BOR0 is detected
Rising edge 1.62 1.66 1.7
VBOR0(2) Brown-out reset threshold 0 V
Falling edge 1.6 1.64 1.69
80/198 DS12469 Rev 9

Table 23. Embedded reset and power control block characteristics (continued)
Rising edge 2.06 2.1 2.14

VBOR1 Brown-out reset threshold 1 V
Falling edge 1.96 2 2.04
Rising edge 2.26 2.31 2.35
Rising edge 2.56 2.61 2.66
Rising edge 2.85 2.90 2.95
Programmable voltage Rising edge 2.1 2.15 2.19

VPVD0 V
detector threshold 0 Falling edge 2 2.05 2.1
Rising edge 2.26 2.31 2.36
VPVD1 PVD threshold 1 V
Rising edge 2.41 2.46 2.51
Rising edge 2.56 2.61 2.66
Rising edge 2.69 2.74 2.79
Rising edge 2.85 2.91 2.96
Rising edge 2.92 2.98 3.04
Hysteresis in
continuous - 20 -
Vhyst_BORH0 Hysteresis voltage of BORH0 mode mV
Hysteresis in
- 30 -
other mode
Hysteresis voltage of BORH
Vhyst_BOR_PVD - - 100 - mV
(except BORH0) and PVD
BOR(3) (except BOR0) and
- - 1.1 1.6 µA
PVD consumption from VDD
IDD
(3)
(BOR_PVD)(2) BOR (except BOR0) and
PVD average consumption - - 55 1000 nA
from VDD with ENULP = 1
VDDUSB peripheral voltage
VPVM1 - 1.18 1.22 1.26 V
monitoring
VDDA peripheral voltage Rising edge 1.61 1.65 1.69

VPVM3 V
monitoring Falling edge 1.6 1.64 1.68
DS12469 Rev 9 81/198

165
Table 23. Embedded reset and power control block characteristics (continued)
VDDA peripheral voltage Rising edge 1.78 1.82 1.86

VPVM4 V
monitoring Falling edge 1.77 1.81 1.85
Vhyst_PVM3 PVM3 hysteresis - - 10 - mV
Vhyst_PVM4 PVM4 hysteresis - - 10 - mV
IDD (PVM1)
(2) PVM1 consumption from VDD - - 0.2 - µA
IDD
PVM3 and PVM4
(PVM3/PVM4) - - 2 - µA
(2) consumption from VDD
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
82/198 DS12469 Rev 9

6.3.4 Embedded voltage reference

temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 24. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +130 °C 1.182 1.212 1.232 V
ADC sampling time when
tS_vrefint (1) reading the internal reference - 4(2) - - µs
voltage
Start time of reference voltage
tstart_vrefint - - 8 12(2) µs
buffer when ADC is enable
VREFINT buffer consumption
from VDD when converted by - - 12.5 20(2) µA
IDD(VREFINTBUF)
ADC
Internal reference voltage
∆VREFINT spread over the temperature VDD = 3 V - 5 7.5(2) mV
range
TCoeff Temperature coefficient –40°C < TA < +130°C - 30 50(2) ppm/°C
ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm
VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage 24 25 26
%
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
DS12469 Rev 9 83/198

165
Figure 23. VREFINT versus temperature
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv40169V1
84/198 DS12469 Rev 9

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 22: Current consumption
measurement scheme with and without external SMPS power supply.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0394 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 25 to Table 48 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
DS12469 Rev 9 85/198

165
86/198
Electrical characteristics
running from flash, ART enable (Cache ON Prefetch OFF)
Conditions TYP MAX(1)
Symbol Parameter Unit
- Voltage fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
scaling
26 MHz 2.05 2.10 2.10 2.20 2.35 2.20 2.25 2.30 2.40 2.60
16 MHz 1.30 1.35 1.40 1.45 1.60 1.40 1.45 1.50 1.60 1.80
8 MHz 0.715 0.730 0.780 0.855 1.00 0.76 0.78 0.84 0.96 1.25
Range 2 4 MHz 0.415 0.430 0.475 0.555 0.710 0.45 0.50 0.55 0.70 0.90
2 MHz 0.265 0.28 0.325 0.400 0.555 0.30 0.30 0.40 0.50 0.80
fHCLK = fHSE up to 1 MHz 0.190 0.205 0.250 0.325 0.480 0.20 0.25 0.30 0.44 0.70
48MHz included,
Supply 100 kHz 0.120 0.135 0.180 0.255 0.410 0.15 0.20 0.25 0.40 0.60
IDD_ALL bypass mode
current in mA
DS12469 Rev 9
(Run) PLL ON above 80 MHz 7.30 7.35 7.40 7.55 7.70 7.75 7.80 7.80 7.90 8.10
Run mode
48 MHz all
peripherals disable 72 MHz 6.60 6.65 6.70 6.80 7.00 7.00 7.00 7.10 7.20 7.40
64 MHz 5.90 5.90 6.00 6.10 6.30 6.25 6.30 6.35 6.40 6.65
Range 1 48 MHz 4.40 4.40 4.50 4.60 4.80 4.70 4.75 4.80 4.90 5.10
32 MHz 3.00 3.00 3.05 3.15 3.35 3.20 3.25 3.30 3.40 3.60
24 MHz 2.30 2.30 2.35 2.45 2.65 2.40 2.40 2.50 2.60 2.90
16 MHz 1.55 1.60 1.65 1.75 1.90 1.70 1.75 1.80 1.90 2.20
2 MHz 190 205 255 335 505 235 230 315 455 725
Supply
IDD_ALL current in fHCLK = fMSI 1 MHz 110 120 165 250 415 135 145 230 370 645
µA
(LPRun) Low-power all peripherals disable 400 kHz 55.0 65.5 115 195 360 75.0 90.5 180 325 590
run mode
100 kHz 26.0 40.0 87.5 170 335 45.0 65.5 160 290 550
1. Guaranteed by characterization results, unless otherwise specified.
STM32L412xx
STM32L412xx
(VDD12 = 1.10 V)
Conditions(1) TYP
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C
80 MHz 2.62 2.64 2.66 2.71 2.77

72 MHz 2.37 2.39 2.41 2.44 2.52
64 MHz 2.12 2.12 2.16 2.19 2.26
48 MHz 1.58 1.58 1.62 1.65 1.73
32 MHz 1.08 1.08 1.10 1.13 1.20
fHCLK = fHSE up to 48MHz included, bypass mode 24 MHz 0.83 0.83 0.84 0.88 0.95
Supply current in Run
IDD_ALL(Run) PLL ON above mA
mode 16 MHz 0.56 0.58 0.59 0.63 0.68
48 MHz all peripherals disable
DS12469 Rev 9
8 MHz 0.26 0.26 0.28 0.31 0.36

4 MHz 0.15 0.15 0.17 0.20 0.26
2 MHz 9.53 0.10 0.12 0.14 0.20
1 MHz 0.07 0.07 0.09 0.12 0.17
100 kHz 0.01 0.01 0.03 0.06 0.12
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS input = 3.3 V, SMPS efficiency = 85%,
VDD12 = 1.10 V
87/198
88/198
running from flash, ART disable
Voltage
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
scaling
26 MHz 2.40 2.45 2.50 2.55 2.75 2.60 2.65 2.70 2.80 3.00
16 MHz 1.70 1.75 1.80 1.85 2.05 1.85 1.90 1.95 2.05 2.30
8 MHz 0.970 0.985 1.05 1.10 1.25 1.05 1.10 1.15 1.25 1.50
Range 2 4 MHz 0.570 0.585 0.630 0.710 0.865 0.61 0.63 0.70 0.80 1.10
2 MHz 0.340 0.355 0.400 0.475 0.635 0.40 0.40 0.50 0.60 0.80
fHCLK = fHSE up to
48MHz included, 1 MHz 0.230 0.240 0.285 0.365 0.52 0.25 0.30 0.34 0.50 0.70
Supply
IDD_ALL bypass mode 100 kHz 0.125 0.140 0.185 0.260 0.415 0.14 0.20 0.25 0.40 0.60
current in mA
Run mode
48 MHz all
72 MHz 6.95 6.95 7.05 7.15 7.35 7.40 7.45 7.50 7.60 7.80
peripherals disable
DS12469 Rev 9
64 MHz 6.90 6.95 7.05 7.20 7.40 7.40 7.45 7.50 7.60 7.80
Range 1 48 MHz 5.85 5.90 6.00 6.15 6.35 6.30 6.35 6.50 6.65 6.90
32 MHz 4.20 4.20 4.30 4.45 4.65 4.50 4.55 4.70 4.80 5.10
24 MHz 3.15 3.20 3.25 3.35 3.55 3.40 3.40 3.50 3.60 3.90
16 MHz 2.25 2.30 2.35 2.50 2.65 2.50 2.50 2.60 2.70 3.00
2 MHz 275 290 340 425 590 325 360 425 565 840
Supply
IDD_ALL current in fHCLK = fMSI 1 MHz 155 165 210 295 460 185 195 275 420 690
µA
(LPRun) Low-power all peripherals disable 400 kHz 69.0 83.0 130 215 280 90.5 108 195 340 600
run
100 kHz 32.0 45.5 92.0 175 340 48.0 69 155 300 570
STM32L412xx
STM32L412xx
ART disable and power supplied by external SMPS (VDD12 = 1.10 V)
Conditions(1) TYP
Uni
Symbol Parameter
t
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C
80 MHz 2.75 2.77 2.82 2.88 2.95

72 MHz 2.50 2.50 2.53 2.57 2.64
64 MHz 2.48 2.50 2.53 2.59 2.66
48 MHz 2.10 2.12 2.16 2.21 2.28
32 MHz 1.51 1.51 1.55 1.60 1.67
Supply current in Run fHCLK = fHSE up to 48MHz included, bypass mode 24 MHz 1.13 1.15 1.17 1.20 1.28
IDD_ALL(Run) mA
mode PLL ON above 48 MHz all peripherals disable 16 MHz 0.81 0.83 0.84 0.90 0.95
8 MHz 0.35 0.35 0.38 0.40 0.45
DS12469 Rev 9
4 MHz 0.20 0.21 0.23 0.26 0.31

2 MHz 12.22 0.13 0.14 0.17 0.23
1 MHz 0.08 0.09 0.10 0.13 0.19
100 kHz 0.01 0.02 0.03 0.06 0.12
VDD12 = 1.10 V
89/198
90/198
running from SRAM1
Voltage 105 125 105 125
- fHCLK 25 °C 55 °C 85 °C 25 °C 55 °C 85 °C
scaling °C °C °C °C
26 MHz 2.00 2.05 2.10 2.15 2.35 2.20 2.20 2.25 2.35 2.55
16 MHz 1.30 1.30 1.35 1.45 1.60 1.40 1.45 1.45 1.55 1.80
8 MHz 0.705 0.720 0.765 0.845 1.00 0.75 0.77 0.83 0.94 1.20
Range 2 4 MHz 0.410 0.425 0.470 0.550 0.700 0.44 0.46 0.52 0.64 0.90
2 MHz 0.265 0.275 0.320 0.395 0.555 0.28 0.30 0.37 0.49 0.75
fHCLK = fHSE up to
48MHz included, 1 MHz 0.190 0.200 0.245 0.325 0.475 0.21 0.22 0.29 0.42 0.67
Supply
IDD_ALL bypass mode 100 kHz 0.120 0.135 0.180 0.255 0.410 0.14 0.15 0.23 0.35 0.61
current in mA
Run mode
48 MHz all
72 MHz 6.45 6.50 6.55 6.75 6.85 6.90 6.95 7.00 7.05 7.25
peripherals disable
DS12469 Rev 9
64 MHz 5.75 5.80 5.85 6.05 6.15 6.15 6.20 6.25 6.30 6.50
Range 1 48 MHz 4.20 4.35 4.40 4.50 7.70 4.65 4.65 4.70 4.80 5.00
32 MHz 2.95 2.95 3.00 3.10 3.30 3.15 3.15 3.20 3.30 3.55
24 MHz 2.25 2.25 2.30 2.40 2.60 2.40 2.40 2.50 2.60 2.85
16 MHz 1.55 1.55 1.60 1.70 1.85 1.65 1.70 1.75 1.85 2.10
2 MHz 180 190 240 320 485 215 225 300 450 720
Supply
fHCLK = fMSI 1 MHz 90.5 110 155 235 400 120 135 220 360 640
IDD_ALL current in
all peripherals disable µA
(LPRun) low-power 400 kHz 40.5 56.0 105 185 350 60.0 76.5 165 315 565
FLASH in power-down
run mode
100 kHz 17.5 32.0 78.5 160 325 33.5 53.5 140 285 555
STM32L412xx
Table 30. Current consumption in Run, code with data processing running from
STM32L412xx
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V)
Conditions(1) TYP
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C
80 MHz 2.57 2.59 2.61 2.68 2.71

72 MHz 2.32 2.34 2.35 2.43 2.46
64 MHz 2.07 2.08 2.10 2.17 2.21
48 MHz 1.55 1.56 1.58 1.62 1.69
32 MHz 1.06 1.06 1.08 1.11 1.19
fHCLK = fHSE up to 48MHz included, bypass mode 24 MHz 0.81 0.81 0.83 0.86 0.93
IDD_ALL(Run) Supply current in Run mode PLL ON above mA
48 MHz all peripherals disable 16 MHz 0.56 0.56 0.58 0.61 0.67
8 MHz 0.25 0.26 0.28 0.30 0.36
DS12469 Rev 9
4 MHz 0.15 0.15 0.17 0.20 0.25

2 MHz 9.53 0.10 0.12 0.15 0.20
1 MHz 0.07 0.07 0.09 0.14 0.17
100 kHz 0.01 0.01 0.03 0.06 0.12
VDD12 = 1.10 V
91/198
running from flash, ART enable (Cache ON Prefetch OFF)
Conditions TYP TYP
Symbol Parameter Unit Unit
Voltage
- Code 25 °C 25 °C
scaling
Reduced code(1) 2.05 79
fHCLK = 26 MHz
Coremark 2.30 88
Range 2
Dhrystone 2.1 2.35 mA 90 µA/MHz
fHCLK = fHSE up
to 48 MHz Fibonacci 2.25 87
Supply included, bypass While(1) 1.95 75
IDD_ALL
current in mode PLL ON
(Run) Reduced code (1)
7.30 91
Run mode above 48 MHz fHCLK = 80 MHz
all peripherals Coremark 8.15 102
Range 1
disable
Dhrystone 2.1 8.35 mA 104 µA/MHz
Fibonacci 8.10 101
While(1) 7.20 90
(1)
Reduced code 190 95
Supply Coremark 205 103
IDD_ALL current in fHCLK = fMSI = 2 MHz
Dhrystone 2.1 220 µA 110 µA/MHz
(LPRun) Low-power all peripherals disable
run Fibonacci 205 103
While(1) 225 113
1. Reduced code used for characterization results provided in Table 25, Table 27, Table 29.
(VDD12 = 1.10 V)
Conditions(1) TYP TYP
Symbol Parameter Voltage Unit Unit
- Code 25 °C 25 °C
scaling
fHCLK = 26 MHz
Coremark 0.99 38
Dhrystone 2.1 1.01 39
fHCLK = fHSE up to
48 MHz included, Fibonacci 0.97 37
Supply bypass mode PLL While(1) 0.84 32
IDD_ALL
current in ON above mA µA/MHz
(Run) Reduced code(2) 3.15 39
Run mode 48 MHz
fHCLK = 80 MHz

disable Dhrystone 2.1 3.60 45
Fibonacci 3.49 44
While(1) 3.11 39
92/198 DS12469 Rev 9

1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:
SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V
(VDD12 = 1.00 V)
- Code 25 °C 25 °C
scaling
fHCLK = fHSE up to Reduced code(2) 0.73 28
fHCLK = 26 MHz
48 MHz included, Coremark 0.82 32
Supply bypass mode PLL
IDD_ALL Dhrystone 2.1 0.84 32
current in ON above mA µA/MHz
(Run)
Run mode 48 MHz Fibonacci 0.80 31
all peripherals
disable While(1) 0.70 27
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters:
SMPS input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.00 V
DS12469 Rev 9 93/198

165
running from flash, ART disable
Conditions TYP TYP
Voltage
- Code 25 °C 25 °C
scaling
fHCLK = 80 MHz fHCLK = 26 MHz

Coremark 2.15 83
Range 2
fHCLK = fHSE up to Dhrystone 2.1 2.20 mA 85 µA/MHz
Supply bypass mode
IDD_ALL While(1) 1.90 73
current in PLL ON above
(Run) Reduced code (1)
7.65 96
Run mode 48 MHz
all peripherals Range 1 Coremark 6.95 87
disable Dhrystone 2.1 7.00 mA 88 µA/MHz
Fibonacci 6.60 83
While(1) 6.85 86
Reduced code(1) 275 138
While(1) 385 193
Table 35. Typical current consumption in Run modes, with different codes running from
flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V)
- Code 25 °C 25 °C
scaling
Coremark 0.93 36
fHCLK = fHSE up to Dhrystone 2.1 0.95 37
Supply bypass mode While(1) 0.82 32
IDD_ALL
current in PLL ON above mA µA/MHz
Run mode 48 MHz
disable Dhrystone 2.1 3.02 38
Fibonacci 2.85 36
While(1) 2.95 37
1. All values are obtained by calculation based on measurements done without SMPS and using following parameters: SMPS
input = 3.3 V, SMPS efficiency = 85%, VDD12 = 1.10 V
94/198 DS12469 Rev 9

Table 36. Typical current consumption in Run modes, with different codesrunning from
flash, ART disable and power supplied by external SMPS (VDD12 = 1.00 V)
- Code 25 °C 25 °C
scaling
fHCLK = 26 MHz
Supply
IDD_ALL bypass mode
current in Dhrystone 2.1 0.78 mA 30 µA/MHz
(Run) PLL ON above
Run mode Fibonacci 0.73 28
48 MHz
all peripherals While(1) 0.68 26
running from SRAM1
Conditions TYP TYP
Voltage
- Code 25 °C 25 °C
scaling

Coremark 2.00 77
Range 2
fHCLK = fHSE up to Dhrystone 2.1 2.05 mA 79 µA/MHz

Supply bypass mode
IDD_ALL While(1) 1.85 71
current in PLL ON above
Run mode 48 MHz all
peripherals Coremark 7.00 88
Range 1
disable Dhrystone 2.1 7.15 mA 89 µA/MHz

Fibonacci 7.10 89
While(1) 6.60 83
Reduced code(1) 180 90
While(1) 170 85
DS12469 Rev 9 95/198

165
- Code 25 °C 25 °C
scaling

Coremark 0.86 33
fHCLK = fHSE up to
Supply While(1) 0.80 31
IDD_ALL bypass mode
current in mA µA/MHz
(Run) PLL ON above Reduced code(2) 3.08 39
Run mode
48 MHz all
Coremark 3.02 38
peripherals disable
Fibonacci 3.06 38
While(1) 2.85 36
- Code 25 °C 25 °C
scaling
fHCLK = 26 MHz

Supply
IDD_ALL bypass mode
current in Dhrystone 2.1 0.73 mA 28 µA/MHz
(Run) PLL ON above
Run mode Fibonacci 0.71 27
48 MHz all
peripherals disable While(1) 0.66 25
96/198 DS12469 Rev 9

STM32L412xx
Table 40. Current consumption in Sleep and Low-power sleep modes, flash ON
Voltage
scaling
26 MHz 0.535 0.550 0.600 0.680 0.835 0.58 0.60 0.66 0.79 1.05
16 MHz 0.375 0.390 0.435 0.515 0.670 0.41 0.43 0.50 0.62 0.88
8 MHz 0.245 0.260 0.305 0.385 0.540 0.27 0.29 0.36 0.49 0.74
Range 2 4 MHz 0.180 0.195 0.240 0.315 0.470 0.20 0.22 0.29 0.42 0.67
fHCLK = fHSE up 2 MHz 0.150 0.160 0.205 0.285 0.435 0.17 0.18 0.25 0.38 0.63
to 48 MHz
Supply included, bypass 1 MHz 0.130 0.145 0.190 0.265 0.420 0.15 0.16 0.24 0.36 0.62
IDD_ALL current in mode 100 kHz 0.115 0.130 0.175 0.250 0.405 0.13 0.15 0.22 0.35 0.60
mA
(Sleep) sleep pll ON above 80 MHz 1.65 1.70 1.75 1.85 2.00 1.80 1.80 1.85 1.95 2.25
mode, 48 MHz all
72 MHz 1.50 1.55 1.60 1.70 1.85 1.60 1.65 1.70 1.80 2.10
peripherals
DS12469 Rev 9
disable 64 MHz 1.35 1.40 1.45 1.55 1.70 1.45 1.50 1.55 1.65 1.95
Range 1 48 MHz 1.00 1.05 1.10 1.2 1.35 1.10 1.15 1.20 1.35 1.65
32 MHz 0.725 0.740 0.795 0.885 1.05 0.78 0.80 0.87 1.05 1.35
24 MHz 0.575 0.595 0.650 0.740 0.910 0.62 0.64 0.72 0.86 1.15
16 MHz 0.425 0.440 0.495 0.585 0.760 0.47 0.48 0.56 0.71 1.00
Supply 2 MHz 52.5 66.5 115 195 360 71.0 91.5 175 315 600
current in 1 MHz 37.0 51.5 97.5 180 345 55.0 73.0 165 295 575
IDD_ALL f =f
low-power HCLK MSI µA
(LPSleep) all peripherals disable 400 kHz 25.5 39.0 85.0 170 330 41.0 63.0 150 280 565
sleep
mode 100 kHz 18.5 33.5 80.5 165 325 36.0 57.5 145 280 560
97/198
Table 41. Current consumption in Sleep, flash ON and power supplied by external SMPS
98/198
(VDD12 = 1.10 V)
Conditions(1) TYP
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C
80 MHz 0.59 0.61 0.63 0.67 0.72

72 MHz 0.54 0.56 0.58 0.61 0.67
64 MHz 0.49 0.50 0.52 0.56 0.61
48 MHz 0.36 0.38 0.40 0.43 0.49
fHCLK = fHSE up to 48 MHz included, bypass 32 MHz 0.26 0.27 0.29 0.32 0.38
mode 24 MHz 0.21 0.21 0.23 0.27 0.33
IDD_ALL(Sleep) Supply current in sleep mode, mA
pll ON above 16 MHz 0.15 0.16 0.18 0.21 0.27
48 MHz all peripherals disable
8 MHz 0.09 0.09 0.11 0.14 0.19
4 MHz 0.06 0.07 0.09 0.11 0.17
2 MHz 5.39 0.06 0.07 0.10 0.15
DS12469 Rev 9
1 MHz 0.05 0.05 0.07 0.10 0.15

100 kHz 0.01 0.01 0.03 0.06 0.12
VDD12 = 1.10 V
Table 42. Current consumption in Low-power sleep modes, flash in power-down

Voltage
scaling
2 MHz 50 60 105 185 350 63 83 170 300 585

Supply current
IDD_ALL fHCLK = fMSI 1 MHz 35 45 89.0 170 335 46 65 150 285 570
in low-power µA
(LPSleep) all peripherals disable 400 kHz 20 32 76.5 155 320 32 51 135 270 560
sleep mode
100 kHz 15 25 71.5 150 315 25 46 135 270 555
STM32L412xx
Table 43. Current consumption in Stop 2 mode
STM32L412xx
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 0.77 2.35 8.60 20.5 46.0 2.0 5.6 21.5 51.0 115
2.4 V 0.78 2.35 8.75 21.0 47.0 2.1 5.8 22.0 52.5 120
-
3V 0.79 2.40 9.00 21.5 49.0 2.1 5.9 22.5 54.0 125
Supply current in 3.6 V 0.84 2.55 9.40 22.5 51.5 2.3 6.1 23.0 56.0 130
IDD_ALL
Stop 2 mode, µA
(Stop 2) 1.8 V 0.72 2.35 9.35 21.0 46.5 - - - - -
RTC disabled
2.4 V 0.74 2.35 9.65 22.0 48.0 - - - - -
ENULP = 1
3V 0.75 2.65 10.0 22.5 50.0 - - - - -
3.6 V 0.79 2.90 10.5 24.0 52.5 - - - - -
1.8 V 1.05 2.70 9.00 21.0 46.0 2.5 6.2 22.0 51.5 120
2.4 V 1.10 2.90 9.30 21.5 47.5 2.8 6.4 22.5 53.0 120
RTC clocked by LSI
DS12469 Rev 9
3V 1.20 3.10 9.65 22.5 49.5 3.0 6.8 23.0 54.5 125
3.6 V 1.30 3.35 10.0 23.5 52.0 3.3 7.2 24.5 57.0 130
1.8 V 1.00 2.65 9.55 21.5 46.5 - - - - -
IDD_ALL Supply current in RTC clocked by LSI 2.4 V 1.05 2.90 10.0 22.0 48.5 - - - - -
(Stop 2 with Stop 2 mode, ENULP = 1 µA
RTC) RTC enabled LPCAL = 1 3V 1.10 3.15 10.5 23.0 50.5 - - - - -
3.6 V 1.20 3.55 11.5 24.5 53.0 - - - - -
1.8 V 0.86 2.45 9.35 21.5 46.5 - - - - -
RTC clocked by LSI
ENULP = 1 2.4 V 0.88 2.60 9.70 22.0 48.0 - - - - -
LPCAL = 1 3V 0.93 2.75 10.0 23.0 50.0 - - - - -
LSIPREDIV = 1
3.6 V 0.98 3.05 11.0 24.0 52.5 - - - - -
99/198
Table 43. Current consumption in Stop 2 mode (continued)
100/198
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 1.35 2.85 9.15 21.0 46.0 - - - - -
RTC clocked by LSE 2.4 V 1.60 3.15 9.60 22.0 48.0 - - - - -
bypassed at 32768 Hz 3V 2.00 3.85 11.0 24.0 51.5 - - - - -
3.6 V 3.90 6.60 15.0 29.5 58.5 - - - - -
1.8 V 1.20 2.80 9.70 21.5 46.5 - - - - -
RTC clocked by LSE
bypassed at 32768 Hz, 2.4 V 1.35 3.10 10.5 22.5 48.5 - - - - -
ENULP = 1, 3V 1.80 3.90 11.5 25.0 52.5 - - - - -
IDD_ALL Supply current in LPCAL = 1 3.6 V 3.65 6.75 16.0 30.5 59.5 - - - - -
(Stop 2 with Stop 2 mode, µA
RTC) RTC enabled 1.8 V 1.20 2.65 8.85 20.5 47.5 - - - - -
RTC clocked by LSE 2.4 V 1.25 2.75 9.10 21.0 49.0 - - - - -
quartz in low drive
DS12469 Rev 9
mode 3V 1.35 2.90 9.45 22.0 51.0 - - - - -

3.6 V 1.50 3.10 9.95 23.0 53.0 - - - - -
1.8 V 1.00 2.55 9.50 21.0 48.0 - - - - -
RTC clocked by LSE
quartz(2) in low drive 2.4 V 1.10 2.75 9.90 22.0 49.5 - - - - -
mode, ENULP = 1, 3V 1.15 3.00 10.5 23.0 52.0 - - - - -
LPCAL = 1
3.6 V 1.25 3.25 11.0 25.0 54.5 - - - - -
Wakeup clock is
MSI = 48 MHz,
3V 1.85 - - - - - - - - -
voltage Range 1.
See (3).
Supply current Wakeup clock is
IDD_ALL MSI = 4 MHz,
during wakeup
(wakeup from voltage Range 2. 3V 1.55 - - - - - - - - - mA
from Stop 2
Stop2)
mode See (3).
Wakeup clock is
STM32L412xx
HSI16 = 16 MHz,
voltage Range 1. 3V 1.52 - - - - - - - - -
See (3).
STM32L412xx
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
DS12469 Rev 9 3. Wakeup with code execution from flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings.
101/198
Table 44. Current consumption in Stop 1 mode
102/198
- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Supply current 1.8 V 3.95 13.0 47.5 110 230 7.40 24.5 87.0 190 395 µA
IDD_ALL in Stop 1 2.4 V 3.95 13.0 48.0 110 230 7.50 24.5 86.0 190 395
-
(Stop 1) mode, 3V 4.00 13.5 48.0 110 235 7.30 24.5 87.0 195 400
RTC disabled
3.6 V 4.10 13.5 48.5 110 240 7.85 25.0 90.0 195 405
1.8 V 4.40 13.5 48.0 110 230 8.05 24.5 86.5 190 395
2.4 V 4.60 14.0 48.5 110 235 8.10 25.0 90.0 195 395
RTC clocked by LSI
3V 4.75 14.0 48.5 110 235 8.20 25.5 89.0 195 400
3.6 V 5.05 14.5 49.5 115 240 8.55 27.0 89.5 195 405
Supply current 1.8 V 4.50 13.5 48.5 110 230 11.5 26.5 86.0 190 395
IDD_ALL 2.4 V 4.70 14.0 49.0 110 230 29.0 31.5 90.0 190 395
in stop 1 RTC clocked by LSE
(Stop 1 with µA
mode, bypassed at 32768 Hz 3V 5.35 14.5 50.0 115 240 36.0 31.5 87.5 195 400
RTC)
DS12469 Rev 9
RTC enabled
3.6 V 7.20 17.5 54.5 120 245 26.0 28.0 88.0 195 405
1.8 V 4.25 13.5 47.5 110 - - - - - -
RTC clocked by LSE quartz(2) 2.4 V 4.35 13.5 48.0 110 - - - - - -
in low drive mode 3V 4.40 13.5 48.0 110 - - - - - -
3.6 V 4.50 14.0 49.0 125 - - - - - -
Wakeup clock MSI = 48 MHz,
voltage Range 1. 3V 1.15 - - - - - - - - -
See (3).
Supply current Wakeup clock MSI = 4 MHz,
IDD_ALL
during voltage Range 2. 3V 1.25 - - - - - - - - -
(wakeup mA
wakeup from See (3).
from Stop1)
Stop 1
Wakeup clock
HSI16 = 16 MHz,
3V 1.20 - - - - - - - - -
voltage Range 1.
See (3).
STM32L412xx
3. Wakeup with code execution from flash. Average value given for a typical wakeup time as specified in Table 50: Low-power mode wakeup timings.
Table 45. Current consumption in Stop 0
STM32L412xx
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 110 125 165 240 380 130 145 215 340 585
Supply current 2.4 V 110 125 170 240 385 130 145 215 340 585
IDD_ALL
in Stop 0 mode, µA
(Stop 0) 3V 115 125 170 245 385 130 145 220 345 590
RTC disabled
3.6 V 115 130 175 250 390 135 150 220 345 595
DS12469 Rev 9
103/198
Table 46. Current consumption in Standby mode
104/198
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 95 255 1150 3200 8350 115 405 2750 7150 19500
2.4 V 105 290 1300 3600 9500 175 540 3250 8350 23000
No independent watchdog
3V 120 354 1550 4350 11500 215 650 3750 9600 26000
3.6 V 150 410 1850 5050 13000 280 835 4450 11500 29500
1.8 V 32 225 1400 3850 9000 115 405 2750 7250 19500
No independent watchdog 2.4 V 46 315 1800 4500 10500 175 540 3250 8350 23000
Supply current ENULP = 1 3V 66 430 2400 5450 12500 215 650 3750 9600 26000
in Standby
IDD_ALL mode (backup 3.6 V 115 570 3050 6350 14500 280 835 4450 11500 29500
nA
(Standby) registers 1.8 V 295 450 1300 3250 8250 - - - - -
retained),
With independent 2.4 V 350 530 1500 3750 9450 - - - - -
RTC disabled
DS12469 Rev 9
watchdog 3V 415 635 1800 4450 11500 - - - - -

3.6 V 505 775 2200 5350 13500 - - - - -
1.8 V 230 415 1450 3900 8850 - - - - -
With independent 2.4 V 290 540 1950 4600 10550 - - - - -
watchdog
ENULP = 1 3V 365 710 2550 5500 12500 - - - - -
3.6 V 460 915 3300 6600 14500 - - - - -
STM32L412xx
Table 46. Current consumption in Standby mode (continued)
STM32L412xx
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 480 635 1500 3450 8400 560 900 3180 7500 19500
RTC clocked by LSI, no 2.4 V 615 800 1800 4050 9700 770 1200 3850 880 23000
independent watchdog 3V 775 995 2150 4850 11500 975 1450 4450 10500 26000
3.6 V 970 1250 2650 5850 14000 1250 1850 5300 12000 29500
1.8 V 330 515 1600 4000 9000 560 900 3180 7500 19500
RTC clocked by LSI, no 2.4 V 435 690 2100 4750 10500 770 1200 3850 8800 23000
Supply current independent watchdog
ENULP = 1 3V 565 915 2750 5750 12500 975 1450 4450 10500 26000
in Standby
IDD_ALL 3.6 V 725 1200 3600 6900 1500 1250 1850 5300 12000 29500
mode (backup
(Standby nA
registers 1.8 V 530 680 1550 3500 8450 - - - - -
with RTC)
retained),
RTC clocked by LSI, with 2.4 V 675 855 1850 4100 9850 - - - - -
RTC enabled
independent watchdog
DS12469 Rev 9
3V 850 1050 2250 4900 11500 - - - - -

3.6 V 1050 1350 2750 4900 11500 - - - - -
1.8 V 370 560 1600 4050 9050 - - - - -
RTC clocked by LSI, with 2.4 V 495 755 2150 4800 10500 - - - - -
independent watchdog
ENULP = 1 3V 645 985 2850 5800 12500 - - - - -
3.6 V 825 1300 3700 6950 15000 - - - - -
105/198
Table 46. Current consumption in Standby mode (continued)
106/198
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 480 640 1500 3450 8100 - - - - -
RTC clocked by LSE 2.4 V 615 800 1800 4000 9300 - - - - -
bypassed at 32768 Hz 3V 775 995 2150 4800 11000 - - - - -
3.6 V 960 1250 2650 5800 13000 - - - - -
1.8 V 330 510 1600 4000 8800 - - - - -
Supply current bypassed at 32768 Hz
in Standby ENULP = 1 3V 565 910 2750 5700 12000 - - - - -
IDD_ALL
mode (backup 3.6 V 730 1200 3600 6900 14500 - - - - -
(Standby
registers nA
with RTC) 1.8 V 415 575 1450 3400 - - - - - -
retained),
(cont.)
RTC enabled RTC clocked by LSE 2.4 V 485 670 1650 3900 - - - - - -
(cont.) quartz (2) in low drive mode
DS12469 Rev 9
3V 550 800 1950 4600 - - - - - -

3.6 V 690 985 2400 - - - - - - -
1.8 V 245 450 1600 4000 - - - - - -
RTC clocked by LSE
(2) in low drive mode 2.4 V 290 565 2050 4650 - - - - - -
quartz
ENULP = 1 3V 355 705 2650 5500 - - - - - -
LPCAL = 1
3.6 V 450 915 3400 - - - - - - -
Supply current 1.8 V 100 230 750 1600 3500 - - - - -
IDD_ALL to be added in 2.4 V 100 230 750 1650 3500 - - - - -
Standby mode - nA
(SRAM2)(3) 3V 100 235 750 1700 3500 - - - - -
when SRAM2
is retained 3.6 V 100 240 750 1700 3500 - - - - -
IDD_ALL Supply current Wakeup clock is
(wakeup during wakeup MSI = 4 MHz. 3V 1.25 - - - - - - - - - mA
from from Standby
See (4).
Standby) mode
STM32L412xx
3. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD_ALL(Standby
+ RTC) + IDD_ALL(SRAM2).
Table 47. Current consumption in Shutdown mode
STM32L412xx
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Supply current 1.8 V 16 100 600 1850 5450 56 310 1200 3350 9550
in Shutdown 2.4 V 22 120 705 2150 6250 65 365 1350 3800 11000
mode
IDD_ALL 3V 31 155 870 2650 7700 97 600 1700 4750 12500
(backup - nA
(Shutdown)
registers
retained) RTC 3.6 V 52 220 1150 3350 9350 95 440 1850 5050 14500
disabled
1.8 V 210 300 820 2050 5750 - - - - -
bypassed at 32768 Hz 3V 625 1000 2200 44000 10000 - - - - -
3.6 V 820 1650 3500 5600 14500 - - - - -
1.8 V 210 300 820 2050 5750 - - - - -
DS12469 Rev 9

Supply current bypassed at 32768 Hz
in Shutdown ENULP = 1 3V 625 1000 2200 44000 10000 - - - - -
IDD_ALL mode 3.6 V 820 1650 3500 5600 14500 - - - - -
(Shutdown (backup nA
with RTC) registers 1.8 V 325 425 930 2200 - - - - - -
retained) RTC RTC clocked by LSE 2.4 V 400 515 1100 2550 - - - - - -
enabled quartz (2) in low drive
mode 3V 475 630 1350 3100 - - - - - -
3.6 V 595 795 1750 - - - - - - -
1.8 V 230 325 830 2050 - - - - - -
RTC clocked by LSE 2.4 V 270 380 975 2400 - - - - - -
quartz (2) in low drive
3V 320 455 1200 1950 - - - - - -
mode ENULP = 1
3.6 V 400 575 1500 - - - - - - -
Supply current
IDD_ALL Wakeup clock is
during wakeup
(wakeup from MSI = 4 MHz. 3V 0.78 - - - - - - - - - mA
from Shutdown
Shutdown) See (3).
mode
107/198
108/198
Table 48. Current consumption in VBAT mode

- VBAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 2 12 66 195 540 - - - - -
2.4 V 3 14 73 215 600 - - - - -
RTC disabled
3V 5 16 92 265 730 - - - - -
IDD_VBAT Backup domain 3.6 V 6 30 161 460 1250 - - - - -
nA
(VBAT) supply current 1.8 V 300 455 460 990 1750 - - - - -
RTC enabled and 2.4 V 380 515 575 1050 1950 - - - - -
clocked by LSE
quartz(2) 3V 445 550 595 1200 2550 - - - - -
3.6 V 495 630 820 1500 2950 - - - - -
DS12469 Rev 9
STM32L412xx
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 69: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 49: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DS12469 Rev 9 109/198

165
On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 49. The MCU is placed
under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in
Table 49. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 49. Peripheral current consumption

Low-power run
Peripheral Range 1 Range 2 Unit
and sleep
Bus Matrix(1) 3.0 2.9 2.8

ADC clock domain 2.2 1.8 1.8
CRC 0.5 0.3 0.2
DMA1 1.3 1.2 1.1
DMA2 1.3 1.2 1.1
FLASH 5.9 4.9 5.6
(2)
GPIOA 1.6 1.5 1.3
GPIOB(2)) 1.5 1.4 1.3
AHB GPIOC(2) 1.7 1.6 1.5
(2)
GPIOH 0.6 0.5 0.6
QSPI 6.9 7.0 5.6
RNG independent clock domain 2.2 NA NA µA/MHz
RNG clock domain 0.5 NA NA

SRAM1 0.7 0.6 0.7
SRAM2 0.9 0.7 0.8
TSC 1.5 1.3 1.3
All AHB Peripherals 21.9 19.2 20.5
AHB to APB1 bridge(3) 0.8 0.6 0.8
RTCA 1.7 1.1 2.1
CRS 0.3 0.3 0.5
APB1
USB FS independent clock
2.8 NA NA
domain
USB FS clock domain 2.2 NA NA
110/198 DS12469 Rev 9

Table 49. Peripheral current consumption (continued)

Low-power run
and sleep
I2C1 independent clock domain 3.4 2.8 3.3

I2C1 clock domain 1.0 0.9 0.9
LPUART1 independent clock
1.8 1.6 1.7
domain
LPUART1 clock domain 0.6 0.6 1.7
LPTIM1 independent clock
2.8 2.3 2.7
domain
LPTIM1 clock domain 0.8 0.4 0.7
LPTIM2 independent clock
2.9 2.6 3.8
domain
APB1 LPTIM2 clock domain 0.8 0.7 0.8 µA/MHz

OPAMP 0.4 0.2 0.4
PWR 0.4 0.1 0.4
SPI2 1.7 1.5 1.5
SPI3 1.7 1.4 1.5
TIM2 6.2 5.0 5.8
TIM6 1.0 0.6 0.9
USART2 independent clock
4.0 3.5 3.7
domain
USART2 clock domain 1.3 0.8 1.1
4.2 3.4 4.1
domain
WWDG 0.5 0.5 0.5
All APB1 on 41.4 28.5 38.9
DS12469 Rev 9 111/198

165
Table 49. Peripheral current consumption (continued)

Low-power run
and sleep
AHB to APB2(4) 1.0 0.9 0.9

FW 0.2 0.2 0.2
SPI1 1.7 1.6 1.7
SYSCFG/COMP 0.6 0.5 0.6
TIM1 8.1 6.4 7.6
APB2 TIM15 3.7 3.0 3.4 µA/MHz
TIM16 2.6 2.1 2.5

4.1 4.1 4.4
domain
All APB2 on 19.2 16.1 17.8
ALL 82.5 63.8 77.2
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when
the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current
consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog
mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).
3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.
4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.
The consumption for the peripherals when using SMPS can be found using STM32CubeMX
PCC tool.
6.3.6 Wakeup time from low-power modes and voltage scaling

transition times
The wakeup times given in Table 50 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
Table 50. Low-power mode wakeup timings(1)

Symbol Parameter Conditions Typ Max Unit
Wakeup time from Sleep

tWUSLEEP - 6 6
mode to Run mode
Nb of
CPU
Wakeup time from Low- Wakeup in flash with flash in power-down during cycles
tWULPSLEEP power sleep mode to Low- low-power sleep mode (SLEEP_PD=1 in 6 8.3
power run mode FLASH_ACR) and with clock MSI = 2 MHz
112/198 DS12469 Rev 9

Table 50. Low-power mode wakeup timings(1) (continued)

Wakeup clock MSI = 48 MHz 3.8 5.7

Range 1
Wakeup clock HSI16 = 16 MHz 4.1 6.9
Wake up time from Stop 0
mode to Run mode in flash
Range 2 Wakeup clock HSI16 = 16 MHz 4.1 6.8
tWUSTOP0 µs
Range 1
mode to Run mode in Wakeup clock MSI = 24 MHz 2.4 3.48
SRAM1
Range 1
mode to Run in flash
Range 1
tWUSTOP1 mode to Run mode in Wakeup clock MSI = 24 MHz 5.4 6.51 µs
SRAM1

mode to Low-power run 16.4 17.73
Regulator in
mode in flash
low-power
Wakeup clock MSI = 2 MHz
mode (LPR=1
in PWR_CR1)
mode to Low-power run 17.3 18.82
mode in SRAM1
DS12469 Rev 9 113/198

165
Table 50. Low-power mode wakeup timings(1) (continued)


Range 1
mode to Run mode in flash
tWUSTOP2 µs
Range 1
mode to Run mode in Wakeup clock MSI = 24 MHz 6.3 7.36
SRAM1
Wakeup time from Standby Wakeup clock MSI = 8 MHz 12.2 18.35
tWUSTBY Range 1 µs
mode to Run mode Wakeup clock MSI = 4 MHz 19.14 25.8
tWUSTBY Wakeup time from Standby Wakeup clock MSI = 8 MHz 12.1 18.3
Range 1 µs
SRAM2 with SRAM2 to Run mode Wakeup clock MSI = 4 MHz 19.2 25.87
Wakeup time from
tWUSHDN Shutdown mode to Run Range 1 Wakeup clock MSI = 4 MHz 261.5 315.7 µs
mode
1. Guaranteed by characterization results.
Table 51. Regulator modes transition times(1)

Wakeup time from Low-power run mode to

tWULPRUN Code run with MSI 2 MHz 5 7
Run mode(2)
µs
Regulator transition time from Range 2 to
tVOST Code run with MSI 24 MHz 20 40
Range 1 or Range 1 to Range 2(3)
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.
Table 52. Wakeup time using USART/LPUART(1)

Wakeup time needed to calculate the Stop 0 mode - 1.7

tWUUSART maximum USART/LPUART baudrate
allowing to wakeup up from stop mode Stop 1 mode and Stop 2 µs
tWULPUART - 8.5
when USART/LPUART clock source is mode
HSI
114/198 DS12469 Rev 9

6.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 24: High-speed external clock
source AC timing diagram.
Table 53. High-speed external user clock characteristics(1)

Voltage scaling
- 8 48
Range 1
fHSE_ext User external clock source frequency MHz
Voltage scaling
- 8 26
Range 2
VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx
V
VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx
Voltage scaling
7 - -
tw(HSEH) Range 1
OSC_IN high or low time ns
tw(HSEL) Voltage scaling
18 - -
Range 2
Figure 24. High-speed external clock source AC timing diagram
tw(HSEH)
VHSEH
90%
10%
VHSEL
tr(HSE) t
tf(HSE) tw(HSEL)
THSE
MS19214V2
DS12469 Rev 9 115/198

165
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 25.
Table 54. Low-speed external user clock characteristics(1)

fLSE_ext User external clock source frequency - - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx
V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
Figure 25. Low-speed external clock source AC timing diagram
tw(LSEH)
VLSEH
90%
10%
VLSEL
tr(LSE) t
tf(LSE) tw(LSEL)
TLSE
MS19215V2
116/198 DS12469 Rev 9

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 55. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 55. HSE oscillator characteristics(1)

fOSC_IN Oscillator frequency - 4 8 48 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 5.5
VDD = 3 V,
Rm = 30 Ω, - 0.44 -
CL = 10 pF@8 MHz
VDD = 3 V,
Rm = 45 Ω, - 0.45 -
CL = 10 pF@8 MHz
IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 30 Ω, - 0.68 -
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 0.94 -
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 1.77 -
CL = 20 pF@48 MHz
Maximum critical crystal
Gm Startup - - 1.5 mA/V
transconductance
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 26). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
DS12469 Rev 9 117/198

165
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 26. Typical application with an 8 MHz crystal
Resonator with integrated

capacitors
CL1
OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain
REXT (1) OSC_OUT

CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 56. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 56. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

LSEDRV[1:0] = 00
- 250 -
Low drive capability
LSEDRV[1:0] = 01
- 315 -
Medium low drive capability
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10
- 500 -
Medium high drive capability
LSEDRV[1:0] = 11
- 630 -
High drive capability
LSEDRV[1:0] = 00
- - 0.5
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Maximum critical crystal Medium low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
118/198 DS12469 Rev 9

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 27. Typical application with a 32.768 kHz crystal
Resonator with integrated

capacitors
CL1
OSC32_IN fLSE
32.768 kHz Drive

resonator programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DS12469 Rev 9 119/198

165
6.3.8 Internal clock source characteristics

The parameters given in Table 57 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 57. HSI16 oscillator characteristics(1)

fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

Trimming code is not a
0.2 0.3 0.4
multiple of 64
TRIM HSI16 user trimming step %
Trimming code is a
-4 -6 -8
multiple of 64
DuCy(HSI16)(2) Duty Cycle - 45 - 55 %
HSI16 oscillator frequency TA= 0 to 85 °C -1 - 1 %

∆Temp(HSI16)
drift over temperature TA= -40 to 125 °C -2 - 1.5 %
HSI16 oscillator frequency
∆VDD(HSI16) VDD=1.62 V to 3.6 V -0.1 - 0.05 %
drift over VDD
HSI16 oscillator start-up
tsu(HSI16)(2) - - 0.8 1.2 μs
time
HSI16 oscillator
tstab(HSI16)(2) - - 3 5 μs
stabilization time
HSI16 oscillator power
IDD(HSI16)(2) - - 155 190 μA
consumption
120/198 DS12469 Rev 9

Figure 28. HSI16 frequency versus temperature
MHz
16.4
+2%
16.3
+1.5%
16.2 +1%
16.1
16
15.9
-1%
15.8
-1.5%
15.7
-2%
15.6
-40 -20 0 20 40 60 80 100 120 °C
min mean max
MSv39299V1
DS12469 Rev 9 121/198

165
Multi-speed internal (MSI) RC oscillator
Table 58. MSI oscillator characteristics(1)

Range 0 98.7 100 101.3

Range 1 197.4 200 202.6
kHz
Range 2 394.8 400 405.2
Range 3 789.6 800 810.4
Range 4 0.987 1 1.013
Range 5 1.974 2 2.026
MSI mode
Range 6 3.948 4 4.052
Range 7 7.896 8 8.104
MHz
Range 8 15.79 16 16.21
Range 9 23.69 24 24.31
MSI frequency Range 10 31.58 32 32.42

after factory Range 11 47.38 48 48.62
fMSI calibration, done
at VDD=3 V and Range 0 - 98.304 -
TA=30 °C Range 1 - 196.608 -
kHz
Range 2 - 393.216 -
Range 3 - 786.432 -
Range 4 - 1.016 -
PLL mode Range 5 - 1.999 -
XTAL=
32.768 kHz Range 6 - 3.998 -
Range 7 - 7.995 -
MHz
Range 8 - 15.991 -
Range 9 - 23.986 -
Range 10 - 32.014 -
Range 11 - 48.005 -
MSI oscillator TA= -0 to 85 °C -3.5 - 3
∆TEMP(MSI)(2) frequency drift MSI mode %
over temperature TA= -40 to 125 °C -8 - 6
122/198 DS12469 Rev 9

Table 58. MSI oscillator characteristics(1) (continued)

VDD=1.62 V
-1.2 -
to 3.6 V
Range 0 to 3 0.5
VDD=2.4 V
-0.5 -
to 3.6 V
MSI oscillator VDD=1.62 V

-2.5 -
frequency drift to 3.6 V
(2)
∆VDD(MSI) MSI mode Range 4 to 7 0.7 %
over VDD VDD=2.4 V
(reference is 3 V) -0.8 -
to 3.6 V
VDD=1.62 V
-5 -
to 3.6 V
Range 8 to 11 1.2
VDD=2.4 V
-1.6 -
to 3.6 V
Frequency TA= -40 to 85 °C - 1 2
∆FSAMPLING
variation in MSI mode %
(MSI)(2)(6) TA= -40 to 125 °C - 2 4
sampling mode(3)
for next
- - - 3.458
P_USB Period jitter for PLL mode transition
ns
Jitter(MSI)(6) USB clock(4) Range 11 for paired
- - - 3.916
transition
for next
- - - 2
MT_USB Medium term jitter PLL mode transition
ns
Jitter(MSI)(6) for USB clock(5) Range 11 for paired
- - - 1
transition
RMS cycle-to-
CC jitter(MSI)(6) PLL mode Range 11 - - 60 - ps
cycle jitter
P jitter(MSI)(6) RMS Period jitter PLL mode Range 11 - - 50 - ps
Range 0 - - 10 20
Range 1 - - 5 10
MSI oscillator Range 2 - - 4 8

tSU(MSI)(6) us
start-up time Range 3 - - 3 7
Range 4 to 7 - - 3 6
Range 8 to 11 - - 2.5 6
10 % of final
- - 0.25 0.5
frequency
MSI oscillator PLL mode 5 % of final
tSTAB(MSI)(6) - - 0.5 1.25 ms
stabilization time Range 11 frequency
1 % of final
- - - 2.5
frequency
DS12469 Rev 9 123/198

165
Table 58. MSI oscillator characteristics(1) (continued)

Range 0 - - 0.6 1
Range 1 - - 0.8 1.2
Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
MSI oscillator Range 5 - - 6.5 9
MSI and
IDD(MSI)(6) power µA
PLL mode Range 6 - - 11 15
consumption
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter
of MSI @48 MHz clock.
5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.
For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28
cycles.
For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over
56 cycles.
124/198 DS12469 Rev 9

Figure 29. Typical current consumption versus MSI frequency
High-speed internal 48 MHz (HSI48) RC oscillator
Table 59. HSI48 oscillator characteristics(1)

fHSI48 HSI48 Frequency VDD=3.0V, TA=30°C - 48 - MHz

TRIM HSI48 user trimming step - - 0.11(2) 0.18(2) %
USER TRIM
HSI48 user trimming coverage ±32 steps ±3(3) ±3.5(3) - %
COVERAGE
DuCy(HSI48) Duty Cycle - 45(2) - 55(2) %
VDD = 3.0 V to 3.6 V,
Accuracy of the HSI48 oscillator - - ±3(3)
TA = –15 to 85 °C
ACCHSI48_REL over temperature (factory %
calibrated) VDD = 1.65 V to 3.6 V,
- - ±4.5(3)
TA = –40 to 125 °C
HSI48 oscillator frequency drift VDD = 3 V to 3.6 V - 0.025(3) 0.05(3)

DVDD(HSI48) %
with VDD VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3)
tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs
HSI48 oscillator power
IDD(HSI48) - - 340(2) 380(2) μA
consumption
DS12469 Rev 9 125/198

165
Table 59. HSI48 oscillator characteristics(1) (continued)

Next transition jitter

NT jitter - - +/-0.15(2) - ns
Accumulated jitter on 28 cycles(4)
Paired transition jitter
PT jitter - - +/-0.25(2) - ns
Accumulated jitter on 56 cycles(4)
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
4. Jitter measurement are performed without clock source activated in parallel.
Figure 30. HSI48 frequency versus temperature

%
6
-2
-4
-6
-50 -30 -10 10 30 50 70 90 110 130
°C
Avg min max
MSv40989V1
Low-speed internal (LSI) RC oscillator
Table 60. LSI oscillator characteristics(1)

VDD = 3.0 V, TA = 30 °C 31.04 - 32.96

fLSI LSI Frequency kHz
VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34
LSI oscillator start-
tSU(LSI)(2) - - 80 130 μs
up time
LSI oscillator
tSTAB(LSI)(2) 5% of final frequency - 125 180 μs
stabilization time
LSI oscillator power
IDD(LSI)(2) - - 110 180 nA
consumption
126/198 DS12469 Rev 9

6.3.9 PLL characteristics

The parameters given in Table 61 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 21: General operating conditions.
Table 61. PLL characteristics(1)

PLL input clock(2) - 4 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 45 - 55 %
Voltage scaling Range 1 3.0968 - 80
fPLL_P_OUT PLL multiplier output clock P MHz
Voltage scaling Range 2 3.0968 - 26
Voltage scaling Range 1 12 - 80
fPLL_Q_OUT PLL multiplier output clock Q MHz
fPLL_R_OUT PLL multiplier output clock R MHz
fVCO_OUT PLL VCO output MHz
tLOCK PLL lock time - - 15 40 μs
RMS cycle-to-cycle jitter - 40 -
Jitter System clock 80 MHz ±ps
RMS period jitter - 30 -
VCO freq = 96 MHz - 200 260
PLL power consumption on
IDD(PLL) VCO freq = 192 MHz - 300 380 μA
VDD(1)
VCO freq = 344 MHz - 520 650
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the 2 PLLs.
DS12469 Rev 9 127/198

165
6.3.10 Flash memory characteristics
Table 62. Flash memory characteristics(1)

tprog 64-bit programming time - 81.69 90.76 µs
one row (32 double normal programming 2.61 2.90

tprog_row
word) programming time fast programming 1.91 2.12
one page (2 Kbyte) normal programming 20.91 23.24 ms

tprog_page
programming time fast programming 15.29 16.98
tERASE Page (2 KB) erase time - 22.02 24.47
one bank (512 Kbyte) normal programming 5.35 5.95

tprog_bank s
programming time fast programming 3.91 4.35
Mass erase time
tME - 22.13 24.59 ms
(one or two banks)
Average consumption Write mode 3.4 -

from VDD Erase mode 3.4 -
IDD mA
Write mode 7 (for 2 μs) -
Maximum current (peak)
Erase mode 7 (for 41 μs) -
Table 63. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
NEND Endurance TA = –40 to +105 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30
(2)
1 kcycle at TA = 105 °C 15
(2)
1 kcycle at TA = 125 °C 7
tRET Data retention Years
(2)
10 kcycles at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
(2)
10 kcycles at TA = 105 °C 10
2. Cycling performed over the whole temperature range.
128/198 DS12469 Rev 9

6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 64. They are based on the EMS levels and classes
defined in application note AN1709.
Table 64. EMS characteristics

Level/
Symbol Parameter Conditions
Class
VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin
VFESD fHCLK = 80 MHz, 2B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 80 MHz, 5A
pins to induce a functional disturbance conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
DS12469 Rev 9 129/198

165
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 65. EMI characteristics for fHSE = 8 MHz and fHCLK = 64 MHz
Symbol Parameter Conditions Monitored frequency band Value Unit
0.1 MHz to 30 MHz 3

30 MHz to 130 MHz 3
Peak(1) VDD = 3.6 V, TA = 25 °C, dBµV
SEMI LQFP64 package 130 MHz to 1 GHz 4
compliant with IEC 61967-2
1 GHz to 2 GHz 8
Level(2) 0.1 MHz to 2 GHz 2.5 -
1. Refer to AN1709 “EMI radiated test” section.
2. Refer to AN1709 “EMI level classification” section.
6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 66. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Package Class Unit
value(1)
T = +25 °C, conforming

Electrostatic discharge voltage A
VESD(HBM) to ANSI/ESDA/JEDEC All 2 2000
(human body model)
JS-001
V
T = +25 °C, BGA64 C2a 500
Electrostatic discharge voltage A
VESD conforming to
(charge device model) All others C1 250
ANSI/ESDA/JEDEC-002
130/198 DS12469 Rev 9

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 67. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II
6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 68.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 68. I/O current injection susceptibility(1)

Functional
susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on all pins except PA4, PA5 -5 N/A(2)

IINJ mA
Injected current on PA4, PA5 pins -5 0
2. Injection is not possible.
DS12469 Rev 9 131/198

165
6.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 69 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Note: For information on GPIO configuration, refer to the application note AN4899 “STM32 GPIO
configuration for hardware settings and low-power consumption” available from the ST
website www.st.com.
Table 69. I/O static characteristics

I/O input low level

1.62 V<VDDIOx<3.6 V - - 0.3xVDDIOx (2)
voltage
I/O input low level
VIL(1) 1.62 V<VDDIOx<3.6 V - - 0.39xVDDIOx-0.06 (3) V
voltage
I/O input low level
1.08 V<VDDIOx<1.62 V - - 0.43xVDDIOx-0.1 (3)
voltage
I/O input high level
1.62 V<VDDIOx<3.6 V 0.7xVDDIOx (2) - -
voltage
VIH(1) 1.62 V<VDDIOx<3.6 V 0.49xVDDIOX+0.26 (3) - - V
voltage
1.08 V<VDDIOx<1.62 V 0.61xVDDIOX+0.05 (3) - -
voltage
TT_xx, FT_xxx and
Vhys(3) NRST I/O input 1.62 V<VDDIOx<3.6 V - 200 - mV
hysteresis
VIN ≤
- - ±100
Max(VDDXXX)(6)(7)
FT_xx input leakage Max(VDDXXX) ≤ VIN ≤
- - 650
current(3)(5) Max(VDDXXX)+1 V(6)(7)
Max(VDDXXX)+1 V <
- - 200
VIN ≤ 5.5 V(6)(7)
VIN ≤
- - ±150
Ilkg(4) Max(VDDXXX)(6)(7) nA
Max(VDDXXX) ≤ VIN ≤
FT_u and PC3 I/O - - 2500(3)
Max(VDDXXX)+1 V(6)(7)
Max(VDDXXX)+1 V <
- - 250
VIN ≤ 5.5 V(6)(7)
VIN ≤ Max(VDDXXX)(6) - - ±150
TT_xx input leakage
current Max(VDDXXX) ≤ VIN <
- - 2000(3)
3.6 V(6)
Weak pull-up
RPU V = VSS 25 40 55 kΩ
equivalent resistor (8) IN
132/198 DS12469 Rev 9

Table 69. I/O static characteristics (continued)

Weak pull-down
RPD VIN = VDDIOx 25 40 55 kΩ
equivalent resistor(8)
CIO I/O pin capacitance - - 5 - pF
1. Refer to Figure 31: I/O input characteristics.
2. Tested in production.
4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] ₓ Ilkg(Max).
5. All FT_xx GPIOs except FT_u and PC3 I/O.
6. Max(VDDXXX) is the maximum value of all the I/O supplies. Refer to Table: Legend/Abbreviations used in the pinout table.
7. To sustain a voltage higher than Min(VDD, VDDA, VDDUSB) +0.3 V, the internal Pull-up and Pull-Down resistors must be
disabled.
8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 31 for standard I/Os, and in Figure 31 for
5 V tolerant I/Os.
Figure 31. I/O input characteristics
TTL requirement Vih min = 2V
2
DIO
x
>1.6
0. 7xV D V DDIOx
in = 6 for
m +0.2
Vih xV DDIO
x
ent 0.49
quir
em 2 or
<1.6 >1.62
S re V DD IOx
r VDDIOx
MO .08< .06 fo
tion
C or 1 -0
c +0.05 f xV D DIOx
rodu IOx r 0.39
d in p 0.6 1xV DD x<
1.62 o
Teste min = 1.08<
V DD IO
n Vih -0.1 fo
r
ulatio VDDIOx
do n sim ax = 0.43x TTL requirement Vil max = 0.8V
Base n Vil m xVdd
ulatio ax = 0.3
on sim nt Vil m
Based OS re quireme
ction CM
in produ
Tested
MSv37613V1
Current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH).
DS12469 Rev 9 133/198

165
GPIOs PC13, PC14 and PC15 are supplied through the power switch, limiting source
capability up to 3 mA only.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 18: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 18: Voltage characteristics).
Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT or TT
unless otherwise specified).
Table 70. Output voltage characteristics(1)

VOL Output low level voltage for an I/O pin CMOS port(2) - 0.4
|IIO| = 8 mA(3)
VOH Output high level voltage for an I/O pin V VDDIOx-0.4 -
DDIOx ≥ 2.7 V
VOL(4) Output low level voltage for an I/O pin TTL port(2) - 0.4
|IIO| = 8 mA(5)
VOH(4) Output high level voltage for an I/O pin V 2.4 -
DDIOx ≥ 2.7 V
VOL(4) Output low level voltage for an I/O pin PC13, PC14 and PC15 - 0.07
|IIO| = 3 mA
VOH(4) Output high level voltage for an I/O pin V VDDIOx-0.35 -
DDIOx ≥ 2.7 V
VOL(4) Output low level voltage for an I/O pin |IIO| = 20 mA(5) - 1.3
VOH (4) Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx-1.3 -
V
VOL(4) Output low level voltage for an I/O pin |IIO| = 4 mA(3) - 0.45
VOH(4) Output high level voltage for an I/O pin VDDIOx ≥ 1.62 V VDDIOx-0.45 -
VOL (4) Output low level voltage for an I/O pin - 0.35ₓVDDIOx
|IIO| = 2 mA
VOH (4)
Output high level voltage for an I/O pin 1.62 V ≥ VDDIOx ≥ 1.08 V 0.65ₓVDDIOx -
|IIO| = 20 mA
- 0.4
VDDIOx ≥ 2.7 V
Output low level voltage for an FT I/O
VOLFM+ |IIO| = 10 mA
(4) pin in FM+ mode (FT I/O with "f" - 0.4
VDDIOx ≥ 1.62 V
option)
|IIO| = 2 mA
- 0.4
1.62 V ≥ VDDIOx ≥ 1.08 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. PC13, PC14 and PC15 are tested/characterized at their maximum current of 3 mA.
134/198 DS12469 Rev 9

5. Not applicable to PC13, PC14 and PC15.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 32 and
Table 71, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
Table 71. I/O AC characteristics(1)(2)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1
Fmax Maximum frequency MHz
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1
00
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 52
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 140
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 17
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 110
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 10
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 1
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 50
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 15
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 1
01
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 9
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 16
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 40
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 4.5
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 9
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 21
DS12469 Rev 9 135/198

165
Table 71. I/O AC characteristics(1)(2) (continued)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3)
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 5
10
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5.8
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 11
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 28
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 2.5
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 12
C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 120(3)
C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 50
C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 10
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 180(3)
11 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 75
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 10
C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 3.3
Tr/Tf Output rise and fall time C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 6 ns
C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 16
Fmax Maximum frequency - 1 MHz
Fm+ C=50 pF, 1.6 V≤VDDIOx≤3.6 V
(4)
Tf Output fall time - 5 ns
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0394 reference manual for a description of GPIO Port configuration register.
3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
136/198 DS12469 Rev 9

Figure 32. I/O AC characteristics definition(1)
90% 10%
50% 50%
10% 90%
t r(IO)out t f(IO)out
Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.
MS32132V4
1. Refer to Table 71: I/O AC characteristics.
6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions.
Table 72. NRST pin characteristics(1)

NRST input low level

VIL(NRST) - - - 0.3ₓVDDIOx
voltage
V
NRST input high level
VIH(NRST) - 0.7ₓVDDIOx - -
voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up
RPU VIN = VSS 25 40 55 kΩ
equivalent resistor(2)
NRST input filtered
VF(NRST) - - - 70 ns
pulse
NRST input not filtered
VNF(NRST) 1.71 V ≤ VDD ≤ 3.6 V 350 - - ns
pulse
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
DS12469 Rev 9 137/198

165
Figure 33. Recommended NRST pin protection
External
reset circuit(1) VDD
RPU
NRST(2) Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 72: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
6.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 73. EXTI Input Characteristics(1)

Pulse length to event

PLEC - 20 - - ns
controller
6.3.17 Analog switches booster
Table 74. Analog switches booster characteristics(1)

Symbol Parameter Min Typ Max Unit
VDD Supply voltage 1.62 - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs
Booster consumption for
- - 250
1.62 V ≤ VDD ≤ 2.0 V
IDD(BOOST) - - 500 µA
2.0 V ≤ VDD ≤ 2.7 V
- - 900
2.7 V ≤ VDD ≤ 3.6 V
138/198 DS12469 Rev 9

6.3.18 Analog-to-Digital converter characteristics

Unless otherwise specified, the parameters given in Table 75 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 21: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 75. ADC characteristics(1) (2)

VDDA Analog supply voltage - 1.62 - 3.6 V

VDDA ≥ 2 V 2 - VDDA V
VREF+ Positive reference voltage
VDDA < 2 V VDDA V
Negative reference
VREF- - VSSA V
voltage
Range 1 0.14 - 80
fADC ADC clock frequency MHz
Range 2 0.14 - 26
Resolution = 12 bits - - 5.33
Sampling rate for FAST Resolution = 10 bits - - 6.15

channels Resolution = 8 bits - - 7.27
fs Msps
Sampling rate for SLOW Resolution = 10 bits - - 4.71

channels Resolution = 8 bits - - 5.33
fADC = 80 MHz
- - 5.33 MHz
fTRIG External trigger frequency Resolution = 12 bits
Resolution = 12 bits - - 15 1/fADC
(VREF++ (VREF++
(VREF++
VCMIN Input common mode Differential mode VREF-)/2 VREF-)/2 V
VREF-)/2
- 0.18 + 0.18
Conversion voltage
VAIN (3) - 0 - VREF+ V
range(2)
RAIN External input impedance - - - 50 kΩ
Internal sample and hold
CADC - - 5 - pF
capacitor
conversion
tSTAB Power-up time - 1
cycle
fADC = 80 MHz 1.45 µs
tCAL Calibration time
- 116 1/fADC
DS12469 Rev 9 139/198

165
Table 75. ADC characteristics(1) (2) (continued)

CKMODE = 00 1.5 2 2.5

Trigger conversion
latency Regular and CKMODE = 01 - - 2.0
tLATR 1/fADC
injected channels without CKMODE = 10 - - 2.25
conversion abort
CKMODE = 11 - - 2.125
CKMODE = 00 2.5 3 3.5
Trigger conversion
latency Injected channels CKMODE = 01 - - 3.0
tLATRINJ 1/fADC
aborting a regular CKMODE = 10 - - 3.25
conversion
CKMODE = 11 - - 3.125
fADC = 80 MHz 0.03125 - 8.00625 µs
ts Sampling time
- 2.5 - 640.5 1/fADC
ADC voltage regulator
tADCVREG_STUP start-up time - - - 20 µs
fADC = 80 MHz
0.1875 - 8.1625 µs
Resolution = 12 bits
Total conversion time
tCONV ts + 12.5 cycles for
(including sampling time)
Resolution = 12 bits successive approximation 1/fADC
= 15 to 653
fs = 5 Msps - 730 830
ADC consumption from
IDDA(ADC) fs = 1 Msps - 160 220 µA
the VDDA supply
fs = 10 ksps - 16 50
fs = 5 Msps - 130 160
IDDV_S(ADC) the VREF+ single ended fs = 1 Msps - 30 40 µA
mode
fs = 10 ksps - 0.6 2
fs = 5 Msps - 260 310
IDDV_D(ADC) the VREF+ differential fs = 1 Msps - 60 70 µA
mode
fs = 10 ksps - 1.3 3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pinouts and pin description for further details.
The maximum value of RAIN can be found in Table 76: Maximum ADC RAIN.
140/198 DS12469 Rev 9

Table 76. Maximum ADC RAIN(1)(2)

RAIN max (Ω)
Sampling cycle Sampling time [ns]
Resolution
@80 MHz @80 MHz
Fast channels(3) Slow channels(4)
2.5 31.25 100 N/A

6.5 81.25 330 100
12.5 156.25 680 470
24.5 306.25 1500 1200
12 bits
47.5 593.75 2200 1800
92.5 1156.25 4700 3900
247.5 3093.75 12000 10000
640.5 8006.75 39000 33000
2.5 31.25 120 N/A
6.5 81.25 390 180
12.5 156.25 820 560
24.5 306.25 1500 1200
10 bits
47.5 593.75 2200 1800
92.5 1156.25 5600 4700
247.5 3093.75 12000 10000
640.5 8006.75 47000 39000
2.5 31.25 180 N/A
6.5 81.25 470 270
12.5 156.25 1000 680
24.5 306.25 1800 1500
8 bits
47.5 593.75 2700 2200
92.5 1156.25 6800 5600
247.5 3093.75 15000 12000
640.5 8006.75 50000 50000
2.5 31.25 220 N/A
6.5 81.25 560 330
12.5 156.25 1200 1000
24.5 306.25 2700 2200
6 bits
47.5 593.75 3900 3300
92.5 1156.25 8200 6800
247.5 3093.75 18000 15000
640.5 8006.75 50000 50000
DS12469 Rev 9 141/198

165
VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. Fast channels are available by access pins: PC0, PC1, PC2, PC3, PA0, PA1.
4. Slow channels are: all ADC inputs except the fast channels.
142/198 DS12469 Rev 9

Table 77. ADC accuracy - limited test conditions 1(1)(2)(3)(4)

Sym-
Parameter Conditions(5) Min Typ Max Unit
bol
Single Fast channel (max speed) - 4 5

Total ended Slow channel (max speed) - 4 5
ET unadjusted
error Fast channel (max speed) - 3.5 4.5
Differential
Slow channel (max speed) - 3.5 4.5
Single Fast channel (max speed) - 1 2.5

ended Slow channel (max speed) - 1 2.5
Offset
EO
Differential
Single Fast channel (max speed) - 2.5 4.5

ended Slow channel (max speed) - 2.5 4.5
EG Gain error LSB
Fast channel (max speed) - 2.5 3.5
Differential

Differential ended Slow channel (max speed) - 1 1.5
ED linearity
error ADC clock frequency ≤ Fast channel (max speed) - 1 1.2
80 MHz, Differential
Slow channel (max speed) - 1 1.2
Sampling rate ≤ 5.33 Msps,
VDDA = VREF+ = 3 V, Single Fast channel (max speed) - 1.5 2.5
Integral TA = 25 °C ended Slow channel (max speed) - 1.5 2.5
EL linearity
error Fast channel (max speed) - 1 2
Differential
Slow channel (max speed) - 1 2
Single Fast channel (max speed) 10.4 10.5 -

Effective ended Slow channel (max speed) 10.4 10.5 -
ENOB number of bits
bits Fast channel (max speed) 10.8 10.9 -
Differential
Slow channel (max speed) 10.8 10.9 -
Single Fast channel (max speed) 64.4 65 -

Signal-to-
ended Slow channel (max speed) 64.4 65 -
noise and
SINAD
distortion Fast channel (max speed) 66.8 67.4 -
ratio Differential
dB
Single Fast channel (max speed) 65 66 -
ended Slow channel (max speed) 65 66 -
Signal-to-
SNR
noise ratio Fast channel (max speed) 67 68 -
Differential
Slow channel (max speed) 67 68 -
DS12469 Rev 9 143/198

165
Table 77. ADC accuracy - limited test conditions 1(1)(2)(3)(4) (continued)

Sym-
bol
ADC clock frequency ≤ Single Fast channel (max speed) - -74 -73
Total 80 MHz, ended Slow channel (max speed) - -74 -73
THD harmonic Sampling rate ≤ 5.33 Msps, dB
distortion VDDA = VREF+ = 3 V, Fast channel (max speed) - -79 -76
Differential
TA = 25 °C Slow channel (max speed) - -79 -76
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
4. The above table gives the ADC performance in 12-bit mode.
VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
144/198 DS12469 Rev 9


Sym-
bol

Total ended Slow channel (max speed) - 4 6.5
ET unadjusted
Differential

ended Slow channel (max speed) - 1 5
Offset
EO
error Fast channel (max speed) - 1.5 3
Differential
Slow channel (max speed) - 1.5 3
Single Fast channel (max speed) - 2.5 6

ended Slow channel (max speed) - 2.5 6
EG Gain error LSB
Fast channel (max speed) - 2.5 3.5
Differential

ED linearity
error Fast channel (max speed) - 1 1.2
ADC clock frequency ≤ Differential
80 MHz, Slow channel (max speed) - 1 1.2
Sampling rate ≤ 5.33 Msps, Fast channel (max speed) - 1.5 3.5
Single
2 V ≤ VDDA ended
Integral Slow channel (max speed) - 1.5 3.5
EL linearity
Differential
Single Fast channel (max speed) 10 10.5 -

Effective ended Slow channel (max speed) 10 10.5 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 66 67.4 -
ratio Differential
Slow channel (max speed) 66 67.4 -
dB
Signal-to-
SNR
noise ratio Fast channel (max speed) 66.5 68 -
Differential
Slow channel (max speed) 66.5 68 -
DS12469 Rev 9 145/198

165

Sym-
bol
Single Fast channel (max speed) - -74 -65

ADC clock frequency ≤
THD harmonic dB
Sampling rate ≤ 5.33 Msps, Fast channel (max speed) - -79 -70
distortion
2 V ≤ VDDA Differential
Slow channel (max speed) - -79 -71
146/198 DS12469 Rev 9


Sym-
bol

Total ended Slow channel (max speed) - 4.5 6.5
ET unadjusted
Differential

Offset
EO
Differential
Single Fast channel (max speed) - 4.5 7

EG Gain error LSB
Fast channel (max speed) - 3.5 4
Differential

Differential ended Slow channel (max speed) - 1.2 1.5
ED linearity ADC clock frequency ≤
Sampling rate ≤ 5.33 Msps, Slow channel (max speed) - 1 1.2
1.65 V ≤ VDDA = VREF+ ≤ Fast channel (max speed) - 3 3.5
Single
3.6 V,
Integral ended Slow channel (max speed) - 2.5 3.5
EL linearity Voltage scaling Range 1
Differential
Single Fast channel (max speed) 10 10.4 -

Effective ended Slow channel (max speed) 10 10.4 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 65 66 -
ratio Differential
dB
Signal-to-
SNR
Differential
DS12469 Rev 9 147/198

165

Sym-
bol
80 MHz, ended
Total Slow channel (max speed) - -71 -67
Sampling rate ≤ 5.33 Msps,
THD harmonic Fast channel (max speed) - -72 -71 dB
1.65 V ≤ VDDA = VREF+ ≤
distortion
3.6 V, Differential
Slow channel (max speed) - -72 -71
Voltage scaling Range 1
148/198 DS12469 Rev 9


Sym-
bol

Total ended Slow channel (max speed) - 4 5
ET unadjusted
Differential

ended Slow channel (max speed) - 2 4
Offset
EO
Differential

ended Slow channel (max speed) - 4 4.5
EG Gain error LSB
Fast channel (max speed) - 3 4
Differential
Slow channel (max speed) - 3 4

ED linearity
error ADC clock frequency ≤ Fast channel (max speed) - 1 1.2
1.65 V ≤ VDDA = VREF+ ≤
3.6 V, Single Fast channel (max speed) - 2.5 3
Integral Voltage scaling Range 2 ended Slow channel (max speed) - 2.5 3
EL linearity
Differential
Single Fast channel (max speed) 10.2 10.5 -

Effective ended Slow channel (max speed) 10.2 10.5 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 65 66 -
ratio Differential
dB
Signal-to-
SNR
Differential
DS12469 Rev 9 149/198

165

Sym-
bol
THD harmonic 1.65 V ≤ VDDA = VREF+ ≤ dB
distortion 3.6 V, Fast channel (max speed) - -73 -72
Differential
Voltage scaling Range 2 Slow channel (max speed) - -73 -72
Figure 34. ADC accuracy characteristics
VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA
MSv19880V6
150/198 DS12469 Rev 9

Figure 35. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function
VDDA(4) VREF+(4)
I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
(2)
Cparasitic Ilkg(3) CADC
VAIN Sampling
switch with
multiplexing
VSS VSS VSSA
MSv67871V3
1. Refer to Table 75: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 69: I/O static characteristics). A high Cparasitic value will downgrade
conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 69: I/O static characteristics for the values of Ilkg.
4. Refer to Figure 21: Power supply scheme.
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 21: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
DS12469 Rev 9 151/198

165
6.3.19 Comparator characteristics
Table 81. COMP characteristics(1)

VDDA Analog supply voltage - 1.62 - 3.6

Comparator input voltage
VIN - 0 - VDDA V
range
VBG(2) Scaler input voltage - VREFINT
VSC Scaler offset voltage - - ±5 ±10 mV
Scaler static consumption BRG_EN=0 (bridge disable) - 200 300 nA

IDDA(SCALER)
from VDDA BRG_EN=1 (bridge enable) - 0.8 1 µA
tSTART_SCALER Scaler startup time - - 100 200 µs
High-speed VDDA ≥ 2.7 V - - 5

mode VDDA < 2.7 V - - 7
Comparator startup time to
tSTART reach propagation delay VDDA ≥ 2.7 V - - 15 µs
specification Medium mode
VDDA < 2.7 V - - 25
Ultra-low-power mode - - 40
High-speed VDDA ≥ 2.7 V - 55 80

ns
mode VDDA < 2.7 V - 65 100
(3) Propagation delay with
tD
100 mV overdrive Medium mode - 0.55 0.9
µs
Ultra-low-power mode - 4 7
Full common
Voffset Comparator offset error - - ±5 ±20 mV
mode range
No hysteresis - 0 -
Low hysteresis 4 8 16
Vhys Comparator hysteresis mV
Medium hysteresis 8 15 30
High hysteresis 15 27 52
152/198 DS12469 Rev 9

Table 81. COMP characteristics(1) (continued)

Static - 400 600

Ultra-low- With 50 kHz nA
power mode ±100 mV overdrive - 1200 -
square signal
Static - 5 7
Comparator consumption
IDDA(COMP) Medium mode With 50 kHz
from VDDA ±100 mV overdrive - 6 -
square signal
µA
Static - 70 100
High-speed With 50 kHz
mode ±100 mV overdrive - 75 -
square signal
Comparator input bias - - - -(4)

Ibias nA
current
1. Guaranteed by design, unless otherwise specified.
2. Refer to Table 24: Embedded internal voltage reference.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 69: I/O static characteristics.
6.3.20 Operational amplifiers characteristics
Table 82. OPAMP characteristics(1)

Analog supply
VDDA - 1.8 - 3.6 V
voltage(2)
Common mode
CMIR - 0 - VDDA V
input range
Input offset 25 °C, No Load on output. - - ±1.5

VIOFFSET mV
voltage All voltage/Temp. - - ±3
Input offset Normal mode - ±5 -

∆VIOFFSET μV/°C
voltage drift Low-power mode - ±10 -
Offset trim step
TRIMOFFSETP at low common
- - 0.8 1.1
TRIMLPOFFSETP input voltage
(0.1 ₓ VDDA)
mV
Offset trim step
TRIMOFFSETN at high common
- - 1 1.35
TRIMLPOFFSETN input voltage
(0.9 ₓ VDDA)
DS12469 Rev 9 153/198

165
Table 82. OPAMP characteristics(1) (continued)

Normal mode - - 500

ILOAD Drive current VDDA ≥ 2 V
Low-power mode - - 100
µA
Drive current in Normal mode - - 450
ILOAD_PGA VDDA ≥ 2 V
PGA mode Low-power mode - - 50
Resistive load Normal mode 4 - -

(connected to
RLOAD VDDA < 2 V
VSSA or to
VDDA) Low-power mode 20 - -
kΩ
Resistive load
Normal mode 4.5 - -
in PGA mode
RLOAD_PGA (connected to VDDA < 2 V
VSSA or to
Low-power mode 40 - -
VDDA)
CLOAD Capacitive load - - - 50 pF
Common mode Normal mode - -85 -

CMRR dB
rejection ratio Low-power mode - -90 -
CLOAD ≤ 50 pf,
Normal mode 70 85 -
Power supply RLOAD ≥ 4 kΩ DC
PSRR dB
rejection ratio CLOAD ≤ 50 pf,
Low-power mode 72 90 -
RLOAD ≥ 20 kΩ DC
Normal mode VDDA ≥ 2.4 V 550 1600 2200
(OPA_RANGE = 1)
Gain Bandwidth Low-power mode 100 420 600
GBW kHz
Product Normal mode 250 700 950
VDDA < 2.4 V
Low-power mode (OPA_RANGE = 0) 40 180 280
Normal mode - 700 -
Slew rate VDDA ≥ 2.4 V
(from 10 and Low-power mode - 180 -
SR(3) V/ms
90% of output Normal mode - 300 -
voltage) VDDA < 2.4 V
Low-power mode - 80 -
Normal mode 55 110 -
AO Open loop gain dB
Low-power mode 45 110 -
VDDA -
Normal mode - -
High saturation Iload = max or Rload = 100
VOHSAT(3)
voltage min Input at VDDA. VDDA -
Low-power mode - - mV
50
Low saturation Normal mode Iload = max or Rload = - - 100

VOLSAT(3)
voltage Low-power mode min Input at 0. - - 50
Normal mode - 74 -
φm Phase margin °
154/198 DS12469 Rev 9


Normal mode - 13 -
GM Gain margin dB
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
Normal mode - 5 10
follower
Wake up time configuration
tWAKEUP µs
from OFF state. CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ
Low-power mode - 10 30
follower
configuration
OPAMP input
Ibias General purpose input - - -(4) nA
bias current
- 2 -
Non inverting - 4 -
PGA gain(3) - -
gain value - 8 -
- 16 -
PGA Gain = 2 - 80/80 -
120/
R2/R1 internal PGA Gain = 4 - -
40
resistance
Rnetwork 140/ kΩ/kΩ
values in PGA PGA Gain = 8 - -
mode(5) 20
150/
PGA Gain = 16 - -
10
Resistance
Delta R variation (R1 or - -15 - 15 %
R2)
PGA gain error PGA gain error - -1 - 1 %
GBW/
Gain = 2 - - -
2
GBW/
PGA bandwidth Gain = 4 - -
4
-
PGA BW for different non MHz
inverting gain GBW/
Gain = 8 - - -
8
GBW/
Gain = 16 - - -
16
DS12469 Rev 9 155/198

165

at 1 kHz, Output
Normal mode - 500 -
loaded with 4 kΩ
at 1 kHz, Output
Voltage noise loaded with 20 kΩ
en nV/√Hz
density at 10 kHz, Output
Normal mode - 180 -
loaded with 4 kΩ
at 10 kHz, Output
loaded with 20 kΩ
OPAMP Normal mode - 120 260
no Load, quiescent
IDDA(OPAMP)(3) consumption µA
Low-power mode mode - 45 100
from VDDA
1. Guaranteed by design, unless otherwise specified.
2. The temperature range is limited to 0 °C-125 °C when VDDA is below 2 V
4. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 69: I/O static characteristics.
5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
6.3.21 Temperature sensor characteristics
Table 83. TS characteristics

TL(1) VTS linearity with temperature - ±1 ±2 °C

(2)
Avg_Slope Average slope 2.3 2.5 2.7 mV/°C
V30 Voltage at 30°C (±5 °C)(3) 0.742 0.76 0.785 V
tSTART
Sensor Buffer Start-up time in continuous mode(4) - 8 15 µs
(TS_BUF)(1)
tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs
tS_temp(1) ADC sampling time when reading the temperature 5 - - µs
Temperature sensor consumption from VDD, when

IDD(TS)(1) - 4.7 7 µA
selected by ADC
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 8:
Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
156/198 DS12469 Rev 9

6.3.22 VBAT monitoring characteristics
Table 84. VBAT monitoring characteristics

R Resistor bridge for VBAT - 3×39 - kΩ

Q Ratio on VBAT measurement - 3 - -
(1)
Er Error on Q -10 - 10 %
(1)
tS_vbat ADC sampling time when reading the VBAT 12 - - µs
Table 85. VBAT charging characteristics

Battery VBRS = 0 - 5 -
RBC charging kΩ
resistor VBRS = 1 - 1.5 -
6.3.23 Timer characteristics

The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 86. TIMx(1) characteristics

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 80 MHz 12.5 - ns
Timer external clock - 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 f
TIMxCLK = 80 MHz 0 40 MHz
TIMx (except
- 16
ResTIM Timer resolution TIM2) bit
TIM2 - 32
16-bit counter clock - 1 65536 tTIMxCLK

tCOUNTER
period fTIMxCLK = 80 MHz 0.0125 819.2 µs
Maximum possible count - - 65536 × 65536 tTIMxCLK

tMAX_COUNT
with 32-bit counter fTIMxCLK = 80 MHz - 53.68 s
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
DS12469 Rev 9 157/198

165
Table 87. IWDG min/max timeout period at 32 kHz (LSI)(1)

Min timeout RL[11:0]= Max timeout RL[11:0]=
Prescaler divider PR[2:0] bits Unit
0x000 0xFFF
/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
Table 88. WWDG min/max timeout value at 80 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0512 3.2768
2 1 0.1024 6.5536
ms
4 2 0.2048 13.1072
8 3 0.4096 26.2144
6.3.24 Communication interfaces characteristics

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0394 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
158/198 DS12469 Rev 9

Table 89. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit
Maximum pulse width of spikes

tAF that are suppressed by the analog 50(2) 260(3) ns
filter
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
DS12469 Rev 9 159/198

165
SPI characteristics
Unless otherwise specified, the parameters given in Table 90 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 21: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 90. SPI characteristics(1)

Master mode receiver/full duplex

2.7 < VDD < 3.6 V 40
Voltage Range 1
Master mode receiver/full duplex
1.71 < VDD < 3.6 V 16
Voltage Range 1
Master mode transmitter
1.71 < VDD < 3.6 V 40
Voltage Range 1
fSCK
SPI clock frequency Slave mode receiver - - MHz
1/tc(SCK)
1.71 < VDD < 3.6 V 40
Voltage Range 1
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V 37(2)
Voltage Range 1
Slave mode transmitter/full duplex
1.71 < VDD < 3.6 V 20(2)
Voltage Range 1
Voltage Range 2 13
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4ₓTPCLK - - ns
th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2ₓTPCLK - - ns
tw(SCKH)
SCK high and low time Master mode TPCLK-2 TPCLK TPCLK+2 ns
tw(SCKL)
tsu(MI) Master mode 4 - -
Data input setup time ns
tsu(SI) Slave mode 1.5 - -
th(MI) Master mode 6.5 - -
Data input hold time ns
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time Slave mode 9 - 36 ns
tdis(SO) Data output disable time Slave mode 9 - 16 ns
160/198 DS12469 Rev 9

Table 90. SPI characteristics(1) (continued)

Slave mode 2.7 < VDD < 3.6 V

- 12.5 13.5
Voltage Range 1
tv(SO) - 12.5 24
Data output valid time Voltage Range 1 ns
- 12.5 33
Voltage Range 2
tv(MO) Master mode - 4.5 6
th(SO) Slave mode 7 - -
Data output hold time ns
th(MO) Master mode 0 - -
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.
Figure 36. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
DS12469 Rev 9 161/198

165
Figure 37. SPI timing diagram - slave mode and CPHA = 1

NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 38. SPI timing diagram - master mode

High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI)
tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
MSB OUT BIT1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136d
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
162/198 DS12469 Rev 9

Quad SPI characteristics

Unless otherwise specified, the parameters given in Table 91 and Table 92 for Quad SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 21: General operating conditions, with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 15 or 20 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 91. Quad SPI characteristics in SDR mode(1)

1.71 < VDD< 3.6 V, CLOAD = 20 pF

- - 40
Voltage Range 1
1.71 < VDD< 3.6 V, CLOAD = 15 pF
- - 48
FCK Voltage Range 1
Quad SPI clock frequency MHz
1/t(CK) 2.7 < VDD< 3.6 V, CLOAD = 15 pF
- - 60
Voltage Range 1
1.71 < VDD < 3.6 V CLOAD = 20 pF
- - 26
Voltage Range 2
tw(CKH) Quad SPI clock high and t(CK)/2-2 - t(CK)/2
fAHBCLK= 48 MHz, presc=0
tw(CKL) low time t(CK)/2 - t(CK)/2+2
Voltage Range 1 2 - -
ts(IN) Data input setup time
Voltage Range 2 3.5 - -
th(IN) Data input hold time ns
Voltage Range 2 6.5 - -
Voltage Range 1 - 1 5
tv(OUT) Data output valid time
Voltage Range 2 - 3 5
th(OUT) Data output hold time
DS12469 Rev 9 163/198

165
Table 92. QUADSPI characteristics in DDR mode(1)

1.71 < VDD < 3.6 V, CLOAD = 20 pF

- - 40
Voltage Range 1
2 < VDD < 3.6 V, CLOAD = 20 pF
- - 48
FCK Quad SPI clock Voltage Range 1
MHz
1/t(CK) frequency 1.71 < VDD < 3.6 V, CLOAD = 15 pF
- - 48
Voltage Range 1
1.71 < VDD < 3.6 V CLOAD = 20 pF
- - 26
Voltage Range 2
tw(CKH) Quad SPI clock high t(CK)/2-2 - t(CK)/2
fAHBCLK = 48 MHz, presc=0
tw(CKL) and low time t(CK)/2 - t(CK)/2+2
Data input setup time Voltage Range 1 1

tsr(IN) - -
on rising edge Voltage Range 2 3.5
Data input setup time Voltage Range 1 1

tsf(IN) - -
on falling edge Voltage Range 2 1.5
Data input hold time Voltage Range 1 6

thr(IN) - -
on rising edge Voltage Range 2 6.5
Data input hold time Voltage Range 1 5.5

thf(IN) - - ns
on falling edge Voltage Range 2 5.5
Data output valid time Voltage Range 1 5 5.5

tvr(OUT) -
on rising edge Voltage Range 2 9.5 14
Data output valid time Voltage Range 1 5 8.5

tvf(OUT) -
on falling edge Voltage Range 2 15 19
Data output hold time Voltage Range 1 3.5 -

thr(OUT) -
on rising edge Voltage Range 2 8 -
Data output hold time Voltage Range 1 3.5 -

thf(OUT) -
on falling edge Voltage Range 2 13 -
164/198 DS12469 Rev 9

Figure 39. Quad SPI timing diagram - SDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V1
Figure 40. Quad SPI timing diagram - DDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output IO0 IO1 IO2 IO3 IO4 IO5
tsf(IN) thf(IN) tsr(IN) thr(IN)
Data input IO0 IO1 IO2 IO3 IO4 IO5

MSv36879V3
USB characteristics
The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF
certified (for Full-speed device operation).
Table 93. USB electrical characteristics(1)

VDDUSB USB transceiver operating voltage 3.0(2) - 3.6 V

Tcrystal_less USB crystal less operation temperature -15 - 85 °C
tSTARTUP(3) USB transceiver startup time - - 1.0 μs

RPUI Embedded USB_DP pull-up value during idle 900 1250 1600
Embedded USB_DP pull-up value during Ω
RPUR 1400 2300 3200
reception
Driving high
ZDRV(3) Output driver impedance(4) 28 36 44 Ω
and low
1. TA = -40 to 125 °C unless otherwise specified.
2. The STM32L412xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics
which are degraded in the 2.7-to-3.0 V voltage range.
4. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
DS12469 Rev 9 165/198

165
Package information STM32L412xx
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
166/198 DS12469 Rev 9

STM32L412xx Package information
7.1 LQFP64 package information

This LQFP is 64-pin, 10 x 10 mm low-profile quad flat package.
Note: See list of notes in the notes section.
Figure 41. LQFP64 - Outline(15)

BOTTOM VIEW
2 1
(2)
R1
H
R2
B
B-
N
O
TI
C
SE
B GAUGE PLANE
D 1/4
0.25
(6)
S
B
L
4x N/4 TIPS
E 1/4 3
(L1)
aaa C A-B D (1) (11)
bbb H A-B D 4x
SECTION A-A
(13) (N – 4)x e
C
A
0.05
A2 A1 (12)
b
ddd C A-B D ccc C
D (4)
(5) (2) D1 (9) (11)
(10)
D (3) b WITH PLATING
N (4)
1 E 1/4 (11) (11)

2
3 c c1
(3) A (6) B (3) (5)
D 1/4 (2)
E1 E b1 BASE METAL
(11)
A A SECTION B-B
(Section A-A)
TOP VIEW 5W_LQFP64_ME_V1
DS12469 Rev 9 167/198

193
Table 94. LQFP64 - Mechanical data

millimeters inches(14)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
A1(12) 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0570
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 12.00 BSC 0.4724 BSC
(2)(5)
D1 10.00 BSC 0.3937 BSC
E(4) 12.00 BSC 0.4724 BSC
(2)(5)
E1 10.00 BSC 0.3937 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 64
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
(1)
aaa 0.20 0.0079
(1)
bbb 0.20 0.0079
(1)
ccc 0.08 0.0031
ddd(1) 0.08 0.0031
168/198 DS12469 Rev 9

Notes:
1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
2. The Top package body size may be smaller than the bottom package size by as much
as 0.15 mm.
3. Datums A-B and D to be determined at datum plane H.
4. To be determined at seating datum plane C.
5. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash
or protrusions is “0.25 mm” per side. D1 and E1 are Maximum plastic body size
dimensions including mold mismatch.
6. Details of pin 1 identifier are optional but must be located within the zone indicated.
7. All Dimensions are in millimeters.
8. No intrusion allowed inwards the leads.
9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall
not cause the lead width to exceed the maximum “b” dimension by more than 0.08 mm.
Dambar cannot be located on the lower radius or the foot. Minimum space between
protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
10. Exact shape of each corner is optional.
11. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm
from the lead tip.
12. A1 is defined as the distance from the seating plane to the lowest point on the package
body.
13. “N” is the number of terminal positions for the specified body size.
14. Values in inches are converted from mm and rounded to 4 decimal digits.
15. Drawing is not to scale.
Figure 42. LQFP64 - Recommended footprint
48 33
0.30
49 0.5 32
12.70
10.30
10.30
64 17
1.20
1 16
7.80
12.70
5W_LQFP64_FP_V2
1. Dimensions are expressed in millimeters.
DS12469 Rev 9 169/198

193
Device marking
The following figure shows the locations and orientation of the marking areas versus pin 1. It
also gives an example of topside marking.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 43. LQFP64 marking (package top view)
Revision code
Product identification(1) A
STM32L412
RBT6
Y WW Date code
Pin 1 identifier
MS49693V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
Figure 44. LQFP64 (external SMPS device) marking (package top view)
Revision code
Product identification(1) A
STM32L412
RBT6P
Y WW Date code
Pin 1 identifier
MS49694V1
170/198 DS12469 Rev 9

7.2 UFBGA64 package information

This UFBGA is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
package
Figure 45. UFBGA64 – Outline
Z Seating plane
ddd Z
A4
A3 A2 A1 A
E1 A1 ball A1 ball X
identifier index area E
e F
A
F
D1 D
e
H Y
8 1
BOTTOM VIEW Øb (64 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z A019_ME_V1
Table 95. UFBGA64 – Mechanical data

Symbol
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 0.080 0.130 0.180 0.0031 0.0051 0.0071
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.170 0.280 0.330 0.0067 0.0110 0.0130
D 4.850 5.000 5.150 0.1909 0.1969 0.2028
D1 3.450 3.500 3.550 0.1358 0.1378 0.1398
E 4.850 5.000 5.150 0.1909 0.1969 0.2028
DS12469 Rev 9 171/198

193
Table 95. UFBGA64 – Mechanical data (continued)

Symbol
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

E1 3.450 3.500 3.550 0.1358 0.1378 0.1398
e - 0.500 - - 0.0197 -
F 0.700 0.750 0.800 0.0276 0.0295 0.0315
ddd - - 0.080 - - 0.0031
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
Figure 46. UFBGA64 – Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 96. UFBGA64 - Recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch 0.5
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
172/198 DS12469 Rev 9


Figure 47. UFBGA64 marking (package top view)
Product identification(1) L412RBI6
Y WW Date code
A
Pin 1 identifier
MS49695V1
DS12469 Rev 9 173/198

193

This LQFP is a 48-pin, 7 x 7 mm low-profile quad flat package

BOTTOM VIEW
4x N/4 TIPS
aaa C A-B D
2 1
(2)
R1
H
R2
B
B-
D 1/4
N
O
(6)
TI
C
SE
B GAUGE PLANE
E 1/4
0.25
S
B
bbb H A-B D 4x
L
3
(13) (L1)
0.05 (N – 4)x e (1) (11)
A A2 C SECTION A-A
(12) ccc C
A1 ddd C A-B D
b
D (4)
(2) (5)
D1
(10) D (3) (9) (11)
N b WITH PLATING
1
2 E 1/4
(3) A 3
(6) B (3)
D 1/4 c c1
E1 E (11) (11)
(2) (4)
(5)
A A b1 BASE METAL
(Section A-A) (11)
SECTION B-B
TOP VIEW
5B_LQFP48_ME_V1
174/198 DS12469 Rev 9


Symbol
A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
(11)
b1 0.17 0.20 0.23 0.0067 0.0079 0.0090
c(11) 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 9.00 BSC 0.3543 BSC
D1(2)(5) 7.00 BSC 0.2756 BSC
(4)
E 9.00 BSC 0.3543 BSC
E1(2)(5) 7.00 BSC 0.2756 BSC
e 0.50 BSC 0.1970 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 48
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
(1)(7)
bbb 0.20 0.0079
(1)(7)
ccc 0.08 0.0031
ddd(1)(7) 0.08 0.0031
DS12469 Rev 9 175/198

193
Notes:
as 0.15 mm.
from the lead tip.
body.

0.50
1.20
36 25
37 24 0.30
0.20
9.70 7.30
48 13
1 12
5.80
9.70
5B_LQFP48_FP_V1
176/198 DS12469 Rev 9

Device marking
STM32L412
(1)
Product identification
CBT6
Y WW Date code
Pin 1 identifier
A Revision code
MS49696V1
DS12469 Rev 9 177/198

193
7.4 UFQFPN48 package information

This UFQFPN is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package
Figure 51. UFQFPN48 - Outline

Pin 1 identifier
laser marking area
D
A
E E
T Seating
plane
ddd A1
e b
Detail Y
D
Y
Exposed pad
area D2
1
L
48
C 0.500x45°
pin1 corner R 0.125 typ.
E2 Detail Z
48
Z
A0B9_UFQFPN48_ME_V3

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN48 package. It is recommended to connect
and solder this back-side pad to PCB ground.
178/198 DS12469 Rev 9

Table 98. UFQFPN48 - Mechanical data

Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
(2)
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
D1 5.400 5.500 5.600 0.2126 0.2165 0.2205
D2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
(2)
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
E1 5.400 5.500 5.600 0.2126 0.2165 0.2205
E2(3) 5.500 5.600 5.700 0.2165 0.2205 0.2244
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
ddd - - 0.080 - - 0.0031
2. Dimensions D and E do not include mold protusion, not exceed 0.15 mm.
3. Dimensions D2 and E2 are not in accordance with JEDEC.
Figure 52. UFQFPN48 - Recommended footprint
7.30
6.20
48 37
1 36
0.20 5.60
7.30
5.80
6.20
5.60
0.30
12 25
13 24
0.50 0.75
0.55
5.80 A0B9_UFQFPN48_FP_V3
DS12469 Rev 9 179/198

193
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 53. UFQFPN48 marking (package top view)
STM32L412
(1)
Product identification
CBU6
Y WW Date code
Pin 1 identifier
A Revision code
MS49697V1
180/198 DS12469 Rev 9

7.5 WLCSP36 package information

This WLCSP - 36 balls, 2.58 x 3.07 mm, 0.4 mm pitch, wafer level chip scale package.
Figure 54. WLCSP36 - Outline

bbb Z
F A1 ball location
A1
e1
G
A6 A5 A4 A3 A2 A1
B6 B5 B4 B3 B2 B1 DETAIL A
C6 C5 C4 C3 C2 C1
e2 E
D6 D5 D4 D3 D2 D1
E6 E5 E4 E3 E2 E1
e
F6 F5 F4 F3 F2 F1
e A
D
aaa A2
BOTTOM VIEW (4X) TOP VIEW SIDE VIEW
A3
BUMP
FRONT VIEW
eee Z
Z
b(36x)
ccc Z XY
ddd Z DETAIL A SEATING PLANE
ROTATED 90
B03P_WLCSP36_DIE464_ME_V1

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
Table 99. WLCSP36 - Mechanical data

Symbol
A(2) - - 0.59 - - 0.023

A1 - 0.18 - - 0.007 -
A2 - 0.38 - - 0.015 -
A3(3) - 0.025 - - 0.001 -
DS12469 Rev 9 181/198

193
Table 99. WLCSP36 - Mechanical data (continued)

Symbol
b 0.22 0.25 0.28 0.009 0.010 0.011

D 2.55 2.58 2.61 0.100 0.102 0.103
E 3.04 3.07 3.10 0.120 0.121 0.122
e - 0.40 - - 0.016 -
e1 - 2.00 - - 0.079 -
e2 - 2.00 - - 0.079 -
(4)
F - 0.290 - - 0.0114 -
G(4) - 0.535 - - 0.0211 -
aaa - 0.10 - - 0.004 -
bbb - 0.10 - - 0.004 -
ccc - 0.10 - - 0.004 -
ddd - 0.05 - - 0.002 -
eee - 0.05 - - 0.002 -
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Calculated dimensions are rounded to the 3rd decimal place
Figure 55. WLCSP36 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
182/198 DS12469 Rev 9

Table 100. WLCSP36 - Recommended PCB design rules

Dimension Recommended values
Pitch 0.4 mm
Dpad 0,225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.100 mm
Device marking
The following figure gives an example of topside marking orientation versus ball 1 identifier
location.
Figure 56. WLCSP36 marking (package top view)
Ball A1 identifier
Product identification(1) L412B6
A Revision code
Y WW Date code
MS51421V1
DS12469 Rev 9 183/198

193
7.6 UFQFPN32 package information

This UFQFPN is a 32 pins, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package.
Figure 57. UFQFPN32 - Outline
ddd C
e A1
C
A3
SEATINGPLANE
D1
b
E2 b
E1 E
1
L
32
D2 L
PIN 1 Identifier
A0B8_ME_V3
184/198 DS12469 Rev 9

Table 101. UFQFPN32 - Mechanical data

Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.000 0.0007 0.0020
A3 - 0.152 - - 0.0060 -
b 0.180 0.230 0.280 0.0071 0.0091 0.0110
(2)
D 4.900 5.000 5.100 0.1929 0.1969 0.2008
D1 3.400 3.500 3.600 0.1339 0.1378 0.1417
D2 3.400 3.500 3.600 0.1339 0.1378 0.1417
(2)
E 4.900 5.000 5.100 0.1929 0.1969 0.2008
E1 3.400 3.500 3.600 0.1339 0.1378 0.1417
E2 3.400 3.500 3.600 0.1339 0.1378 0.1417
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
2. Dimensions D and E do not include mold protrusion, not to exceed 0,15mm.
Figure 58. UFQFPN32 - Recommended footprint
5.30
3.80
0.60
32 25
1 24
3.45
5.30 3.80
3.45
0.50
0.30 8 17
9 16 0.75
3.80
A0B8_FP_V2
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
DS12469 Rev 9 185/198

193

Figure 59. UFQFPN32 marking (package top view)
Product identification(1) L412KB6
Y WW A Revision code
Date code
Pin 1 identifier
MS49698V1
186/198 DS12469 Rev 9


This LQFP is a 32-pin, 7 x 7 mm low-profile quad flat package.
BOTTOM VIEW
2 1
(2)
(6) R1
D 1/4 H
R2
B
B-
N
O
TI
E 1/4
C
SE
B GAUGE PLANE
4x N/4 TIPS
0.25
aaa C A-B D bbb H A-B D 4x S
N B
L
3
(L1)
(1) (11)
SECTION A-A
(N – 4)x e (13)
C
A
A2 A1 b ddd C A-B D
0.05 (12) ccc C
D (4)
(9) (11)
(2) (5)
b WITH PLATING
D1
D (3)
(10)
(11) c
1
c1(11)
2 E 1/4
(3) A B
3
D 1/4
E1 E b1 BASE METAL
(6) (2) (4) (11)
(3) (5)
A A SECTION B-B
(Section A-A)
TOP VIEW 5V_LQFP32_ME_V1
DS12469 Rev 9 187/198

193

Symbol
A - - 1.60 - - 0.0630
(12)
A1 0.05 - 0.15 0.002 - 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
(9)(11)
b 0.30 0.37 0.45 0.0118 0.0146 0.0177
(11)
b1 0.30 0.35 0.40 0.0118 0.0128 0.0157
(11)
c 0.09 - 0.20 0.0035 - 0.0079
c1(11) 0.09 - 0.16 0.0035 - 0.0063
(4)
D 9.00 BSC 0.3543 BSC
(2)(5)
D1 7.00 BSC 0.2756 BSC
E(4) 9.00 BSC 0.3543 BSC
E1(2)(5) 7.00 BSC 0.2756 BSC
e 0.80 BSC 0.0315 BSC
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 REF 0.0394 REF
N(13) 32
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 11° 12° 13° 11° 12° 13°
θ3 11° 12° 13° 11° 12° 13°
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
aaa(1)(7) 0.20 0.0079
bbb(1)(7) 0.20 0.0079
(1)(7)
ccc 0.10 0.0039
(1)(7)
ddd 0.20 0.0079
188/198 DS12469 Rev 9

Notes:
as 0.15 mm.
from the lead tip.
body.

0.80
24 17
25 16 0.50
0.30
9.70
7.30
32 9
1 8
1.20
6.10
9.70
5V_LQFP32_FP_V3
DS12469 Rev 9 189/198

193
Device marking
670/
3URGXFWLGHQWLILFDWLRQ
.%7
< :: 'DWHFRGH
3LQLGHQWLILHU
$ 5HYLVLRQFRGH
069
190/198 DS12469 Rev 9

7.8 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of all IDDXXX and VDDXXX, expressed in Watts. This is the
maximum chip internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 103. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

66
LQFP64 - 10 × 10 mm / 0.5 mm pitch
63
UFBGA64 - 5 × 5 mm / 0.5 mm pitch
30
UFQFPN48 - 7 × 7 mm / 0.5 mm pitch
ΘJA 68 °C/W
LQFP48 - 7 × 7 mm / 0.5 mm pitch
85
WLCSP36 - 2.58 x 3.07 mm / 0.4 mm pitch
68
LQFP32 - 7 x 7 / 0.8 mm pitch
37
UFQFPN32- 5 × 5 mm / 0.5 mm pitch
7.8.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
7.8.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
DS12469 Rev 9 191/198

193
As applications do not commonly use the STM32L412xx at maximum dissipation, it is useful

to calculate the exact power consumption and junction temperature to determine which
temperature range is best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 72 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL = 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V = 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 103 TJmax is calculated as follows:
– For LQFP64, 66 °C/W
TJmax = 72 °C + (66 °C/W × 447 mW) = 72 °C + 29.502 °C = 101.502 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Section 8:
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see Part
numbering).
Note: With this given PDmax user can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 37).
Suffix 6: TAmax = TJmax - (66°C/W × 447 mW) = 105-29.502 = 75.498 °C
Suffix 3: TAmax = TJmax - (46°C/W × 447 mW) = 130-29.502 = 100.498 °C
Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL = 0.4 V
PINTmax = 20 mA × 3.5 V = 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
192/198 DS12469 Rev 9

Using the values obtained in Table 103 TJmax is calculated as follows:

– For LQFP64, 66 °C/W
TJmax = 100 °C + (66 °C/W × 134 mW) = 100 °C + 8.844 °C = 108.844 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 3 (see
Section 8: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
DS12469 Rev 9 193/198

193
Ordering information STM32L412xx
8 Ordering information
Table 104. STM32L412xx ordering information scheme

Example: STM32 L 412 R B T 6 P TR
Device family
STM32 = Arm® based 32-bit microcontroller
Product type
L = ultra-low-power
Device subfamily
412 = STM32L412xx
Pin count
K = 32 pins
T = 36 pins
C = 48 pins
R = 64 pins
Flash memory size

B = 128 KB of flash memory
8 = 64 KB of flash memory
Package
T = LQFP ECOPACK2
U = QFN ECOPACK2
I = UFBGA ECOPACK2
Y = CSP ECOPACK2
Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
3 = Industrial temperature range, -40 to 125 °C (130 °C junction)
Option
Blank = Standard production with integrated LDO
P = Dedicated pinout supporting external SMPS
Packing
TR = tape and reel
xxx = programmed parts
For a list of available options (such as speed, package) or for further information on any
aspect of this device contact the nearest ST sales office.
194/198 DS12469 Rev 9

STM32L412xx Important security notice
9 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
DS12469 Rev 9 195/198

195
Revision history STM32L412xx
10 Revision history
Table 105. Document revision history

Date Revision Changes
02-Oct-2018 1 Initial release.

Updated:
– Features
– Table 25: Current consumption in Run and Low-power
run modes, code with data processing running from
flash, ART enable (Cache ON Prefetch OFF),
Table 27: Current consumption in Run and Low-power
run modes, code with data processing running from
18-Oct-2018 2 flash, ART disable, Table 29: Current consumption in
Run and Low-power run modes, code with data
processing running from SRAM1, Table 40: Current
consumption in Sleep and Low-power sleep modes,
flash ON, Table 42: Current consumption in Low-
power sleep modes, flash in power-down, Table 43:
Current consumption in Stop 2 mode, Table 48:
Current consumption in VBAT mode, Table 49:
Peripheral current consumption
Updated Table 46: Current consumption in Standby
mode, Table 22: Operating conditions at power-up /
power-down, Table 23: Embedded reset and power
03-Dec-2018 3 control block characteristics, Table 65: EMI
characteristics for fHSE = 8 MHz and fHCLK = 64 MHz.
Removed Figure 5: STM32L412Vx, external SMPS
device, LQFP100 pinout
18-Dec-2018 4 Updated Table 99: WLCSP36 - Mechanical data.
Added Figure 15: STM32L412Tx, external SMPS,
11-Feb-2019 5 WLCSP36 ballout(1).
Updated Table 14: STM32L412xx pin definitions.
03-Jun-2019 6 Updated Table 16: Alternate function AF8 to AF15
Updated Table 2: STM32L412xx family device features
26-Sep-2019 7
and peripheral counts
Updated Table 16: Alternate function AF8 to AF15
Added UFBGA64 SMPS in Table 14: STM32L412xx pin
03-Nov-2020 8
definitions, Figure 9: STM32L412Rx UFBGA64, external
SMPS, ballout(1)
Updated Rich analog peripherals (independent supply)
on cover page.
Updated Section 1: Introduction.
23-Dec-2022 9 Updated Section 3.7: Boot modes.
Added Figure 2: Power supply overview.
Updated Section 3.15.3: VBAT battery voltage
monitoring.
196/198 DS12469 Rev 9

STM32L412xx Revision history
Table 105. Document revision history (continued)

Date Revision Changes
Updated Section 3.19: True random number generator

(RNG).
Updated Section 3.25: Serial peripheral interface (SPI).
Updated Section 3.28: Quad SPI memory interface
(QUADSPI).
Added Figure 11: STM32L412Cx LQFP48, external
SMPS, pinout(1).
Updated Figure 12: STM32L412Cx UFQFPN48
pinout(1).
Added Figure 13: STM32L412Cx UFQFPN48, external
SMPS, pinout(1).
Updated Figure 17: STM32L412Kx UFQFPN32
pinout(1).
Added Note:.
Updated Table 14: STM32L412xx pin definitions.
Updated Table 15: Alternate function AF0 to AF7.
Updated Table 16: Alternate function AF8 to AF15.
Updated Table 18: Voltage characteristics.
Updated Table 58: MSI oscillator characteristics.
Updated Table 65: EMI characteristics for fHSE = 8
MHz and fHCLK = 64 MHz.
9 Added Note: in Section 6.3.14: I/O port characteristics.
23-Dec-2022
(continued) Updated Section 6.3.14: I/O port characteristics.
Updated Table 70: Output voltage characteristics.
Updated Figure 32: I/O AC characteristics definition(1).
Updated footnote in Table 76: Maximum ADC RAIN.
Updated Section 6.3.18: Analog-to-Digital converter
characteristics
Added footnote in Table 77: ADC accuracy - limited test
conditions 1.
conditions 2.
conditions 3.
conditions 4.
Updated Figure 34: ADC accuracy characteristics.
Updated Figure 35: Typical connection diagram when
using the ADC with FT/TT pins featuring analog switch
function.
Updated Table 81: COMP characteristics.
Updated Table 84: VBAT monitoring characteristics.
Updated Section 7: Package information.
Added Section 9: Important security notice.
DS12469 Rev 9 197/198

197
STM32L412xx
IMPORTANT NOTICE – READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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© 2022 STMicroelectronics – All rights reserved
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STM32L412xx

Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,

December 2022 DS12469 Rev 9 1/198

• 14-channel DMA controller • Development support: serial wire debug

STM32L412CB, STM32L412KB, STM32L412RB, STM32L412TB

2/198 DS12469 Rev 9

DS12469 Rev 9 3/198

3.17 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4/198 DS12469 Rev 9

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

DS12469 Rev 9 5/198

7.7 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

6/198 DS12469 Rev 9

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DS12469 Rev 9 7/198

8/198 DS12469 Rev 9

Table 82. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

DS12469 Rev 9 9/198

Figure 1. STM32L412xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

10/198 DS12469 Rev 9

Figure 47. UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

DS12469 Rev 9 11/198

12/198 DS12469 Rev 9

The STM32L412xx devices are ultra-low-power microcontrollers based on the

Table 2. STM32L412xx family device features and peripheral counts

DS12469 Rev 9 13/198

Table 2. STM32L412xx family device features and peripheral counts (continued)

14/198 DS12469 Rev 9

Figure 1. STM32L412xx block diagram

VDD Power management

PB[15:0] GPIO PORT B AHB1 80 MHz HSI48 @VDD

XTAL OSC OSC_IN

TIM2 32b 4 channels, ETR as AF

16 external analog inputs ADC2

smcard RX, TX, CK, CTS, RTS as AF

3 compl. channels (TIM1_CH[1:3]N),

SPI2 MOSI, MISO, SCK, NSS as AF

RX, TX, CK,CTS, USART1

OpAmp1 VOUT, VINM, VINP

LPUART1 RX, TX, CTS, RTS as AF

INP, INM, OUT COMP1

LPTIM1 IN1, IN2, OUT, ETR as AF

Note: AF: alternate function on I/O pins.

DS12469 Rev 9 15/198

3.1 Arm® Cortex®-M4 core with FPU

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

3.3 Memory protection unit

16/198 DS12469 Rev 9

3.4 Embedded flash memory

Main 1 Yes Yes Yes No No No

System 1 Yes No No Yes No No

Option 1 Yes Yes Yes Yes Yes Yes

DS12469 Rev 9 17/198

3.5 Embedded SRAM