STM32L443

STM32L443CC STM32L443RC
STM32L443VC
Ultra-low-power Arm® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,
256KB Flash, 64KB SRAM, USB FS, LCD, analog, audio, AES
Datasheet - production data
Features
• Ultra-low-power with FlexPowerControl
LQFP48
– 1.71 V to 3.6 V power supply (7 x 7 mm) UFQFPN48 UFBGA64 THIN WLCSP49
LQFP64 (7 x 7 mm) (5 x 5 mm) (3.14 x 3.15 x 0.20 mm)
– -40 °C to 85/105/125 °C temperature range (10 x 10 mm) UFBGA100 STANDARD WLCSP49
LQFP100 (7 x 7 mm) (3.141 x 3.127 x 0.38 mm)
– 200 nA in VBAT mode: supply for RTC and (14 x 14 mm) STANDARD WLCSP64
32x32-bit backup registers (3.141 x3.127 x 0.38 mm)
– 8 nA Shutdown mode (5 wakeup pins)
• Up to 83 fast I/Os, most 5 V-tolerant
– 28 nA Standby mode (5 wakeup pins)
• RTC with HW calendar, alarms and calibration
– 280 nA Standby mode with RTC
– 1.0 µA Stop 2 mode, 1.28 µA with RTC • LCD 8× 40 or 4× 44 with step-up converter
– 84 µA/MHz run mode • Up to 21 capacitive sensing channels: support
– Batch acquisition mode (BAM) touchkey, linear and rotary touch sensors
– 4 µs wakeup from Stop mode • 11x timers: 1x 16-bit advanced motor-control,
– Brown out reset (BOR) 1x 32-bit and 2x 16-bit general purpose, 2x 16-
bit basic, 2x low-power 16-bit timers (available
– Interconnect matrix
in Stop mode), 2x watchdogs, SysTick timer
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
• Memories
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait-state execution – 256 KB single bank Flash, proprietary code
from Flash memory, frequency up to 80 MHz, readout protection
MPU, 100DMIPS and DSP instructions – 64 KB of SRAM including 16 KB with
hardware parity check
• Performance benchmark
– Quad SPI memory interface
– 1.25 DMIPS/MHz (Drystone 2.1)
– 273.55 CoreMark® (3.42 CoreMark/MHz @ • Rich analog peripherals (independent supply)
80 MHz) – 1x 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
• Energy benchmark
– 2x 12-bit DAC output channels, low-power
– 347 ULPMark™ CP score
sample and hold
– 121 ULPMark™ PP score
– 1x operational amplifier with built-in PGA
• Clock Sources
– 2x ultra-low-power comparators
– 4 to 48 MHz crystal oscillator
• AES: 128/256-bit key encryption hardware
– 32 kHz crystal oscillator for RTC (LSE) accelerator
– Internal 16 MHz factory-trimmed RC (±1%)
• 17x communication interfaces
– Internal low-power 32 kHz RC (±5%)
– USB 2.0 full-speed crystal less solution
– Internal multispeed 100 kHz to 48 MHz with LPM and BCD
oscillator, auto-trimmed by LSE (better than
– 1x SAI (serial audio interface)
±0.25 % accuracy)
– 3x I2C FM+(1 Mbit/s), SMBus/PMBus
– Internal 48 MHz with clock recovery
– 4x USARTs (ISO 7816, LIN, IrDA, modem)
– 2 PLLs for system clock, USB, audio, ADC
– 1x LPUART (Stop 2 wake-up)
October 2019 DS11421 Rev 5 1/220

This is information on a product in full production. www.st.com
STM32L443CC STM32L443RC STM32L443VC
– 3x SPIs (and 1x Quad SPI) • True random number generator

– CAN (2.0B Active) and SDMMC interface • CRC calculation unit, 96-bit unique ID
– SWPMI single wire protocol master I/F • Development support: serial wire debug
– IRTIM (Infrared interface) (SWD), JTAG, Embedded Trace Macrocell™
• 14-channel DMA controller • All packages are ECOPACK2® compliant
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STM32L443CC STM32L443RC STM32L443VC Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 17
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 20
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 38
3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 38
3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.16 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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Contents STM32L443CC STM32L443RC STM32L443VC
3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.21 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.22 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.23 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 43
3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.24.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.24.2 General-purpose timers (TIM2, TIM15, TIM16) . . . . . . . . . . . . . . . . . . . 46
3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.24.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 46
3.24.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.24.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.24.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.24.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 48
3.26 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.27 Universal synchronous/asynchronous receiver transmitter (USART) . . . 50
3.28 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 51
3.29 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.30 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.31 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 53
3.32 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.33 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 54
3.34 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.35 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.36 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.37 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.37.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.37.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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STM32L443CC STM32L443RC STM32L443VC Contents
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 93
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 93
6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 144
6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 145
6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 158
6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 163
6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
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Contents STM32L443CC STM32L443RC STM32L443VC
6.3.26 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

6.3.27 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 173
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

7.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
7.2 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.3 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.4 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.5 STANDARD WLCSP64 package information . . . . . . . . . . . . . . . . . . . . . 198
7.6 STANDARD WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . 201
7.7 THIN WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.8 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
7.9 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
7.10 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.10.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.10.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 215
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
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STM32L443CC STM32L443RC STM32L443VC List of tables
List of tables
Table 1. STM32L443xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 14

Table 2. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 18
Table 3. STM32L443xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5. STM32L443xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 6. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 8. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 10. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 11. STM32L443xx USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 12. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 14. STM32L443xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 15. Alternate function AF0 to AF7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 16. Alternate function AF8 to AF15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 17. STM32L443xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 84
Table 18. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 19. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 20. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 21. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 22. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 23. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 24. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 25. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . . 99
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 28. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 102
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 31. Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . 104
Table 32. Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 105
Table 33. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 34. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 35. Current consumption in Stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 36. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 37. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 38. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 39. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 40. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 41. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 42. Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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List of tables STM32L443CC STM32L443RC STM32L443VC
Table 43. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 44. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 45. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 46. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 47. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 48. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table 49. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 50. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 51. PLL, PLLSAI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 52. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 53. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 54. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 55. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 56. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 57. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 58. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 59. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 60. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 61. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 62. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 63. EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 64. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 65. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 66. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 67. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 71. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 72. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 73. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 74. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 75. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 76. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 77. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 78. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 79. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 80. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 81. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 82. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 83. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Table 84. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 85. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 86. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 87. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 88. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 89. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 90. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 91. SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 92. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 93. UFBGA - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
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array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 94. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 191
Table 95. LQFP - 64 pins, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 96. UFBGA – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
Table 97. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . 197
Table 98. STANDARD WLCSP - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level
chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 99. STANDARD WLCSP64 recommended PCB design rules
(0.35 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 101. STANDARD WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . 203
Table 102. THIN WLCSP - 49 balls, 3.14x 3.15 mm, 0.4 mm pitch, wafer level chip scale
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 103. THIN WLCSP49 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 105. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Table 106. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 107. STM32L443xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 108. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
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List of figures STM32L443CC STM32L443RC STM32L443VC
List of figures
Figure 1. STM32L443xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 5. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6. STM32L443Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 7. STM32L443Vx UFBGA100 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 8. STM32L443Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 9. STM32L443Rx UFBGA64 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10. STM32L443Rx WLCSP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 11. STM32L443Cx WLCSP49 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 12. STM32L443Cx LQFP48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 13. STM32L443Cx UFQFPN48 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 14. STM32L443xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 15. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 16. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 17. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 18. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 19. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 21. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 24. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 25. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 26. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 27. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 28. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 29. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 30. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 31. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 32. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 33. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 34. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 35. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 36. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 37. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 38. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 39. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 40. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 41. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 42. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . 186
Figure 43. LQFP - 100 pins, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 44. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 45. UFBGA - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 46. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
10/220 DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC List of figures
array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

Figure 47. UFBGA100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 48. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . 193
Figure 49. LQFP - 64 pins, 10 x 10 mm low-profile quad flat package
Figure 50. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 51. UFBGA – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 52. UFBGA64 – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 53. UFBGA64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 54. STANDARD WLCSP - 64-ball, 3.141 x 3.127 mm, 0.35 mm pitch wafer level
chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 56. STANDARD WLCSP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 59. STANDARD WLCSP49 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 60. WLCSP - 49 balls, 3.14x 3.15 mm, 0.4 mm pitch, wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 61. THIN WLCSP - 49 balls, 3.14x 3.15 mm, 0.4 mm pitch, wafer level chip scale
Figure 62. THIN WLCSP49 marking (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 63. LQFP - 48 pins, 7 x 7 mm low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . 207
Figure 65. LQFP48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 66. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 68. UFQFPN48 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 69. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
DS11421 Rev 5 11/220

11
Introduction STM32L443CC STM32L443RC STM32L443VC
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L443xx microcontrollers.
This document should be read in conjunction with the STM32L41x, STM32L42x,
STM32L43x, STM32L44x, STM32L45x, STM32L46x reference manual (RM0394). The
reference manual is available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M4 core, please refer to the Cortex®-M4 Technical
Reference Manual, available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
12/220 DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC Description
2 Description
The STM32L443xx devices are the ultra-low-power microcontrollers based on the high-
performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz.
The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all
Arm® single-precision data-processing instructions and data types. It also implements a full
set of DSP instructions and a memory protection unit (MPU) which enhances application
security.
The STM32L443xx devices embed high-speed memories (256 Kbyte of Flash memory,
64 Kbyte of SRAM), a Quad SPI flash memories interface (available on all packages) and
an extensive range of enhanced I/Os and peripherals connected to two APB buses, two
AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L443xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and Firewall.
The devices offer a fast 12-bit ADC (5 Msps), two comparators, one operational amplifier,
two DAC channels, an internal voltage reference buffer, a low-power RTC, one general-
purpose 32-bit timer, one 16-bit PWM timer dedicated to motor control, four general-purpose
16-bit timers, and two 16-bit low-power timers.
In addition, up to 21 capacitive sensing channels are available. The devices also embed an
integrated LCD driver 8x40 or 4x44, with internal step-up converter.
They also feature standard and advanced communication interfaces.
• Three I2Cs
• Three SPIs
• Three USARTs and one Low-Power UART.
• One SAI (Serial Audio Interfaces)
• One SDMMC
• One CAN
• One USB full-speed device crystal less
• One SWPMI (Single Wire Protocol Master Interface)
The STM32L443xx devices embed AES hardware accelerator.
The STM32L443xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C
(+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to
3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-
power applications.
Some independent power supplies are supported: analog independent supply input for
ADC, DAC, OPAMP and comparators, and 3.3 V dedicated supply input for USB. A VBAT
input allows to backup the RTC and backup registers.
The STM32L443xx family offers eight packages from 48 to 100-pin packages.
DS11421 Rev 5 13/220

56
Description STM32L443CC STM32L443RC STM32L443VC
Table 1. STM32L443xx family device features and peripheral counts

Peripheral STM32L443Vx STM32L443Rx STM32L443Cx
Flash memory 256KB

SRAM 64KB
Quad SPI Yes
Advanced control 1 (16-bit)
2 (16-bit)
General purpose
1 (32-bit)
Basic 2 (16-bit)
Timers Low -power 2 (16-bit)
SysTick timer 1
Watchdog timers
(independent, 2
window)
SPI 3
2C
I 3
USART 3
LPUART 1
Comm. SAI 1
interfaces
CAN 1
USB FS Yes
SDMMC Yes No
SWPMI Yes
RTC Yes
Tamper pins 3 2 2
LCD Yes Yes Yes
COM x SEG 8x40 or 4x44 8x28 or 4x32 4x19
Random generator Yes
AES Yes
GPIOs 83 52 38 or 39(1)
Wakeup pins 5 4 3
Capacitive sensing
21 12 6
Number of channels
12-bit ADC 1 1 1
Number of channels 16 16 10
12-bit DAC channels 2
Internal voltage reference buffer Yes No
Analog comparator 2
Operational amplifiers 1
14/220 DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC Description
Table 1. STM32L443xx family device features and peripheral counts (continued)

Peripheral STM32L443Vx STM32L443Rx STM32L443Cx
Max. CPU frequency 80 MHz

Operating voltage 1.71 to 3.6 V
Ambient operating temperature:
-40 to 85 °C / -40 to 105 °C / -40 to 125 °C
Operating temperature
Junction temperature:
-40 to 105 °C / -40 to 125 °C / -40 to 130 °C
WLCSP64 WLCSP49
LQFP100
Packages LQFP64 LQFP48
UFBGA100
UFBGA64 UFQFPN48
1. For WLCSP49 package.
DS11421 Rev 5 15/220

56
Description STM32L443CC STM32L443RC STM32L443VC
Figure 1. STM32L443xx block diagram
D0[3:0],
NJTRST, JTDI, D1[3:0],
JTCK/SWCLK JTAG & SW Quad SPI memory interface CLK0,
MPU
CLK1
JTDO/SWD, JTDO
ETM NVIC CS
TRACECLK
TRACED[3:0] D-BUS
ARM Cortex-M4
80 MHz
FPU I-BUS
RNG
ACCEL/
CACHE
Flash
ART
S-BUS up to
AES
256 KB
AHB bus-matrix
SRAM 48 KB
SRAM 16 KB
VDD Power management

DMA2 AHB2 80 MHz
Voltage VDD = 1.71 to 3.6 V
regulator
3.3 to 1.2 V VSS
DMA1
@ VDD @ VDD
Supply
MSI reset
supervision
7 Groups of VDDUSB
Touch sensing controller RC HSI Int
3 channels max as AF BOR
VDDA, VSSA
RC LSI VDD, VSS, NRST
PA[15:0] GPIO PORT A PVD, PVM
PLL 1&2
AHB1 80 MHz
PB[15:0] GPIO PORT B HSI48 @VDD
XTAL OSC OSC_IN

PC[15:0] GPIO PORT C 4- 16MHz OSC_OUT
IWDG
VBAT = 1.55 to 3.6 V
PD[15:0] GPIO PORT D
Standby
PE[15:0] GPIO PORT E interface
Reset & clock
M AN AGT
control @VBAT
PH[1:0], OSC32_IN
PH[3] GPIO PORT H XTAL 32 kHz
OSC32_OUT
RTC
RTC_TS
FCLK
PCLKx
AWU
HCLKx
RTC_TAMPx
Backup register
RTC_OUT
@ VDD
U STemperature
AR T 2 M sensor
Bps TIM2 32b 4 channels, ETR as AF
CRC
@ VDDUSB
DP
@ VDDA
FIFO
PHY DM
USB FS
NOE
16 external analog inputs ADC1 ITF
CRS CRS_SYNC
@ VDDA
VREF+
VREF Buffer AHB/APB2 AHB/APB1
smcard
USART2 RX, TX, CK, CTS, RTS as AF
IrDA
83 AF EXT IT. WKUP
smcard RX, TX, CK, CTS, RTS as AF
USART3
D[7:0] IrDA
FIFO
CMD, CK as AF SDIO / MMC

SPI2 MOSI, MISO, SCK, NSS as AF
3 compl. channels (TIM1_CH[1:3]N),
4 channels (TIM1_CH[1:4]), TIM1 / PWM 16b SPI3 MOSI, MISO, SCK, NSS as AF
ETR, BKIN, BKIN2 as AF
I2C1/SMBUS SCL, SDA, SMBA as AF
WWDG
I2C2/SMBUS SCL, SDA, SMBA as AF
2 channels, 16b
TIM15
1 compl. channel, BKIN as AF I2C3/SMBUS SCL, SDA, SMBA as AF
APB2 80MHz
1 channel,
FIFO
TIM16 16b
1 compl. channel, BKIN as AF bxCAN1 TX, RX as AF
@VDDA
1 3 0 M Hz
OpAmp1 VOUT, VINM, VINP

smcard
A P B(max)
RX, TX, CK,CTS, USART1

RTS as AF IrDA TIM6 16b
APB1 80 MHz
MOSI, MISO,
SPI1
SCK, NSS as AF TIM7 16b
MCLK_A, SD_A, FS_A, SCK_A, EXTCLK LCD Booster
VLCD
SAI1 VLCD = 2.5V to 3.6V

MCLK_B, SD_B, FS_B, SCK_B as AF
B Hz
60PM 2
LCD 8x40 SEGx, COMx as AF

A
@ VDDA @ VDDA LPUART1 RX, TX, CTS, RTS as AF
INP, INM, OUT COMP1 IO

DAC1 SWPMI1
ITF RX, TX, SUSPEND as AF
INP, INM, OUT COMP2 DAC2
LPTIM1 IN1, IN2, OUT, ETR as AF
FIREWALL
LPTIM2 IN1, OUT, ETR as AF
OUT1 OUT2 MSv39219V2
Note: AF: alternate function on I/O pins.
16/220 DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC Functional overview
3 Functional overview
3.1 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm® processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an Arm® core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded Arm® core, the STM32L443xx family is compatible with all Arm® tools
and software.
Figure 1 shows the general block diagram of the STM32L443xx family devices.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard Arm® Cortex®-M4 processors. It balances the inherent performance advantage of
the Arm® Cortex®-M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
To release the processor near 100 DMIPS performance at 80MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 80 MHz.
3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
DS11421 Rev 5 17/220

56
Functional overview STM32L443CC STM32L443RC STM32L443VC
3.4 Embedded Flash memory

STM32L443xx devices feature 256 Kbyte of embedded Flash memory available for storing
programs and data in single bank architecture. The Flash memory contains 128 pages of 2
Kbyte.
Flexible protections can be configured thanks to option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial
wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
Table 2. Access status versus readout protection level and execution modes
Debug, boot from RAM or boot
User execution
Protection from system memory (loader)
Area
level
Read Write Erase Read Write Erase
Main 1 Yes Yes Yes No No No

memory 2 Yes Yes Yes N/A N/A N/A
System 1 Yes No No Yes No No

memory 2 Yes No No N/A N/A N/A
Option 1 Yes Yes Yes Yes Yes Yes

bytes 2 Yes No No N/A N/A N/A
(1)
Backup 1 Yes Yes N/A No No N/A(1)
registers 2 Yes Yes N/A N/A N/A N/A
1 Yes Yes Yes(1) No No No(1)
SRAM2
2 Yes Yes Yes N/A N/A N/A
1. Erased when RDP change from Level 1 to Level 0.
• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 2-Kbyte granularity.
• Proprietary code readout protection (PCROP): a part of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
The PCROP area granularity is 64-bit wide. An additional option bit (PCROP_RDP)
allows to select if the PCROP area is erased or not when the RDP protection is
changed from Level 1 to Level 0.
18/220 DS11421 Rev 5

The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
• single error detection and correction
• double error detection.
• The address of the ECC fail can be read in the ECC register
3.5 Embedded SRAM

STM32L443xx devices feature 64 Kbyte of embedded SRAM. This SRAM is split into two
blocks:
• 48 Kbyte mapped at address 0x2000 0000 (SRAM1)
• 16 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
This memory is also mapped at address 0x2000 C000, offering a contiguous address
space with the SRAM1 (16 Kbyte aliased by bit band)
This block is accessed through the ICode/DCode buses for maximum performance.
These 16 Kbyte SRAM can also be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.6 Firewall
The device embeds a Firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
The Firewall main features are the following:
• Three segments can be protected and defined thanks to the Firewall registers:
– Code segment (located in Flash or SRAM1 if defined as executable protected
area)
– Non-volatile data segment (located in Flash)
– Volatile data segment (located in SRAM1)
• The start address and the length of each segments are configurable:
– Code segment: up to 1024 Kbyte with granularity of 256 bytes
– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes
– Volatile data segment: up to 48 Kbyte with a granularity of 64 bytes
• Specific mechanism implemented to open the Firewall to get access to the protected
areas (call gate entry sequence)
• Volatile data segment can be shared or not with the non-protected code
• Volatile data segment can be executed or not depending on the Firewall configuration
The Flash readout protection must be set to level 2 in order to reach the expected level of
protection.
DS11421 Rev 5 19/220

56
3.7 Boot modes

At startup, BOOT0 pin or nSWBOOT0 option bit, and BOOT1 option bit are used to select
one of three boot options:
• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM
BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on the
value of a user option bit to free the GPIO pad if needed.
A Flash empty check mechanism is implemented to force the boot from system flash if the
first flash memory location is not programmed and if the boot selection is configured to boot
from main flash.
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART, I2C, SPI, CAN or USB FS in Device mode through DFU (device firmware
upgrade).
3.8 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.9 Power supply management
3.9.1 Power supply schemes

• VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and
the system analog such as reset, power management and internal clocks. It is provided
externally through VDD pins.
• VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DAC/OPAMP) to 3.6 V: external analog power
supply for ADCs, DAC, OPAMPs, Comparators and Voltage reference buffer. The VDDA
voltage level is independent from the VDD voltage.
• VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage.
• VLCD = 2.5 to 3.6 V: the LCD controller can be powered either externally through VLCD
pin, or internally from an internal voltage generated by the embedded step-up
converter.
• VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: When the functions supplied by VDDA or VDDUSB are not used, these supplies should
preferably be shorted to VDD.
20/220 DS11421 Rev 5

Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V
tolerant (refer to Table 18: Voltage characteristics).
Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1, with
VDDIO1 = VDD.
Figure 2. Power supply overview
VDDA domain
A/D converters
VDDA Comparators
D/A converters
VSSA Operational amplifiers
Voltage reference buffer
VLCD LCD
VDDUSB
USB transceivers
VSS
VDD domain
VDDIO1
VDD I/O ring
Reset block
Temp. sensor
PLL, HSI, MSI, HSI48
VSS
Standby circuitry
(Wakeup logic, IWDG)
VCORE domain
VCORE Core
Voltage regulator Memories
Digital peripherals
Low voltage detector
Backup domain
LSE crystal 32 K osc
BKP registers
VBAT RCC BDCR register
RTC
MSv45724V1
During power-up and power-down phases, the following power sequence requirements
must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDUSB, VLCD) must remain
below VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1 mJ; this allows external decoupling
capacitors to be discharged with different time constants during the power-down transient
phase.
DS11421 Rev 5 21/220

56
Figure 3. Power-up/down sequence
3.6
VDDX(1)
VDD
VBOR0
0.3
Power-on Operating mode Power-down time
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1
1. VDDX refers to any power supply among VDDA, VDDUSB, VLCD.
3.9.2 Power supply supervisor

The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
except Shutdown and ensuring proper operation after power-on and during power down.
The device remains in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a Peripheral Voltage Monitor which compares the
independent supply voltages VDDA, VDDUSB with a fixed threshold in order to ensure that the
peripheral is in its functional supply range.
22/220 DS11421 Rev 5

3.9.3 Voltage regulator

Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
• The MR is used in the Run and Sleep modes and in the Stop 0 mode.
• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 16 Kbyte SRAM2 in Standby with SRAM2 retention.
• Both regulators are in power-down in Standby and Shutdown modes: the regulator
output is in high impedance, and the kernel circuitry is powered down thus inducing
zero consumption.
The ultralow-power STM32L443xx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the Main Regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
There are two power consumption ranges:
• Range 1 with the CPU running at up to 80 MHz.
• Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
• Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by HSI16.
3.9.4 Low-power modes

The ultra-low-power STM32L443xx supports seven low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources.
DS11421 Rev 5 23/220

56
24/220
Functional overview
Table 3. STM32L443xx modes overview
Mode Regulator(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
MR range 1 All 97 µA/MHz

Run Yes ON(4) ON Any N/A N/A
MR range2 All except USB_FS, RNG 84 µA/MHz
Any to Range 1: 4 µs
LPRun LPR Yes ON(4) ON except All except USB_FS, RNG N/A 94 µA/MHz
to Range 2: 64 µs
PLL
MR range 1 All Any interrupt or 28 µA/MHz
Sleep No ON(4) ON(5) Any 6 cycles
MR range2 All except USB_FS, RNG event 26 µA/MHz
Any
Any interrupt or
LPSleep LPR No ON(4) ON(5) except All except USB_FS, RNG 29 µA/MHz 6 cycles
event
PLL
DS11421 Rev 5
BOR, PVD, PVM

RTC, LCD, IWDG Reset pin, all I/Os
MR Range 1 COMPx (x=1,2) BOR, PVD, PVM 108 µA
RTC, LCD, IWDG

DAC1
OPAMPx (x=1) COMPx (x=1..2)
LSE USARTx (x=1...3)(6) USARTx (x=1...3)(6) 2.4 µs in SRAM
Stop 0 No OFF ON
LSI LPUART1(6) LPUART1(6) 4.1 µs in Flash
I2Cx (x=1...3)(7) I2Cx (x=1...3)(7)
LPTIMx (x=1,2) LPTIMx (x=1,2)
MR Range 2 *** USB_FS(8) 108 µA
All other peripherals are SWPMI1(9)
frozen.
Table 3. STM32L443xx modes overview (continued)

(1)
Mode Regulator CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
BOR, PVD, PVM

COMPx (x=1,2) BOR, PVD, PVM
DAC1 RTC, LCD, IWDG
OPAMPx (x=1) COMPx (x=1..2)
LSE USARTx (x=1...3)(6) USARTx (x=1...3)(6) 4.34 µA w/o RTC 6.3 µs in SRAM
Stop 1 LPR No Off ON
LSI LPUART1(6) LPUART1(6) 4.63 µA w RTC 7.8 µs in Flash
I2Cx (x=1...3)(7) I2Cx (x=1...3)(7)
LPTIMx (x=1,2) LPTIMx (x=1,2)
*** USB_FS(8)
All other peripherals are SWPMI1(9)
frozen.
BOR, PVD, PVM
DS11421 Rev 5

COMPx (x=1..2) BOR, PVD, PVM
I2C3(7) RTC, LCD, IWDG
LSE 1.3 µA w/o RTC 6.8 µs in SRAM
Stop 2 LPR No Off ON LPUART1(6) COMPx (x=1..2)
LSI 1.4 µA w/RTC 8.2 µs in Flash
LPTIM1 I2C3(7)
*** LPUART1(6)
All other peripherals are LPTIM1
frozen.
Functional overview
25/220
Table 3. STM32L443xx modes overview (continued)
26/220
Functional overview
(1)
Mode Regulator CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
SRAM BOR, RTC, IWDG 0.20 µA w/o RTC

LPR
2 ON *** 0.46 µA w/ RTC
All other peripherals are Reset pin
Power LSE
Standby Off Power powered off. 5 I/Os (WKUPx)(10) 12.2 µs
ed Off LSI 0.03 µA w/o RTC
OFF ed *** BOR, RTC, IWDG
I/O configuration can be 0.29 µA w/ RTC
Off
floating, pull-up or pull-down
RTC
***
Power All other peripherals are Reset pin
Power powered off. 0.01 µA w/o RTC
Shutdown OFF Off ed LSE 5 I/Os (WKUPx)(10) 262 µs
ed Off *** 0.20 µA w/ RTC
Off RTC
I/O configuration can be
DS11421 Rev 5
floating, pull-up or pull-

down(11)
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.

3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in
LPRun/LPSleep.
4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
5. The SRAM1 and SRAM2 clocks can be gated on or off independently.
6. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. USB_FS wakeup by resume from suspend and attach detection protocol event.
9. SWPMI1 wakeup by resume from suspend.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.
By default, the microcontroller is in Run mode after a system or a power Reset. It is up to the
user to select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Low-power run mode
This mode is achieved with VCORE supplied by the low-power regulator to minimize the
regulator's operating current. The code can be executed from SRAM or from Flash,
and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can
be clocked by HSI16.
• Low-power sleep mode
This mode is entered from the low-power run mode. Only the CPU clock is stopped.
When wakeup is triggered by an event or an interrupt, the system reverts to the low-
power run mode.
• Stop 0, Stop 1 and Stop 2 modes
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the VCORE domain are stopped, the PLL, the MSI
RC, the HSI16 RC and the HSE crystal oscillators are disabled. The LSE or LSI is still
running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode
to detect their wakeup condition.
Three Stop modes are available: Stop 0, Stop 1 and Stop 2 modes. In Stop 2 mode,
most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, allowing a very fast wakeup time but with much higher consumption.
The system clock when exiting from Stop 0, Stop 1 or Stop 2 modes can be either MSI
up to 48 MHz or HSI16, depending on software configuration.
• Standby mode
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off. The PLL, the
MSI RC, the HSI16 RC and the HSE crystal oscillators are also switched off.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1 and register contents are lost except for registers
in the Backup domain and Standby circuitry. Optionally, SRAM2 can be retained in
Standby mode, supplied by the low-power Regulator (Standby with SRAM2 retention
mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wakeup, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wakeup is MSI up to 8 MHz.
DS11421 Rev 5 27/220

56
• Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off so that the VCORE domain is powered off. The PLL, the HSI16,
the MSI, the LSI and the HSE oscillators are also switched off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup
domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wakeup, timestamp, tamper).
The system clock after wakeup is MSI at 4 MHz.
28/220 DS11421 Rev 5

Table 4. Functionalities depending on the working mode(1)

Stop 0/1 Stop 2 Standby Shutdown
Wakeup capability
Wakeup capability
Wakeup capability
Wakeup capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -
CPU Y - Y - - - - - - - - - -
Flash memory
O(2) O(2) O(2) O(2) - - - - - - - - -
(256 KB)
SRAM1 (48 KB) Y Y(3) Y Y(3) Y - Y - - - - - -
SRAM2 (16 KB) Y Y(3) Y Y(3) Y - Y - O(4) - - - -
Quad SPI O O O O - - - - - - - - -
Backup Registers Y Y Y Y Y - Y - Y - Y - Y
Brown-out reset
Y Y Y Y Y Y Y Y Y Y - - -
(BOR)
Programmable
Voltage Detector O O O O O O O O - - - - -
(PVD)
Peripheral Voltage
Monitor (PVMx; O O O O O O O O - - - - -
x=1,3,4)
DMA O O O O - - - - - - - - -
High Speed Internal (5) (5)
O O O O - - - - - - -
(HSI16)
Oscillator RC48 O O - - - - - - - - - - -
High Speed External
O O O O - - - - - - - - -
(HSE)
Low Speed Internal
O O O O O - O - O - - - -
(LSI)
Low Speed External
O O O O O - O - O - O - O
(LSE)
Multi-Speed Internal
O O O O - - - - - - - - -
(MSI)
Clock Security
O O O O - - - - - - - - -
System (CSS)
Clock Security
O O O O O O O O O O - - -
System on LSE
RTC / Auto wakeup O O O O O O O O O O O O O
Number of RTC
3 3 3 3 3 O 3 O 3 O 3 O 3
Tamper pins
LCD O O O O O O O O - - - - -
DS11421 Rev 5 29/220

56
Table 4. Functionalities depending on the working mode(1) (continued)

Wakeup capability
Wakeup capability
Wakeup capability
Wakeup capability
Low- Low-
run sleep - - - -
USB FS O(8) O(8) - - - O - - - - - - -

(6) (6)
USARTx (x=1,2,3) O O O O O O - - - - - - -
Low-power UART
O O O O O(6) O(6) O(6) O(6) - - - - -
(LPUART)
I2Cx (x=1,2) O O O O O(7) O(7) - - - - - - -
(7)
I2C3 O O O O O O(7) O(7) O(7) - - - - -
SPIx (x=1,2,3) O O O O - - - - - - - - -
CAN O O O O - - - - - - - - -
SDMMC1 O O O O - - - - - - - - -
SWPMI1 O O O O - O - - - - - - -
SAIx (x=1) O O O O - - - - - - - - -
ADCx (x=1) O O O O - - - - - - - - -
DAC1 O O O O O - - - - - - - -
VREFBUF O O O O O - - - - - - - -
OPAMPx (x=1) O O O O O - - - - - - - -
COMPx (x=1,2) O O O O O O O O - - - - -
Temperature sensor O O O O - - - - - - - - -
Timers (TIMx) O O O O - - - - - - - - -
Low-power timer 1
O O O O O O O O - - - - -
(LPTIM1)
Low-power timer 2
O O O O O O - - - - - - -
(LPTIM2)
Independent
O O O O O O O O O O - - -
watchdog (IWDG)
Window watchdog
O O O O - - - - - - - - -
(WWDG)
SysTick timer O O O O - - - - - - - - -
Touch sensing
O O O O - - - - - - - - -
controller (TSC)
Random number
O(8) O(8) - - - - - - - - - - -
generator (RNG)
AES hardware
O O O O - - - - - - - - -
accelerator
30/220 DS11421 Rev 5

Table 4. Functionalities depending on the working mode(1) (continued)

Wakeup capability
Wakeup capability
Wakeup capability
Wakeup capability
Low- Low-
run sleep - - - -
CRC calculation unit O O O O - - - - - - - - -

5 5
(9) (11)
GPIOs O O O O O O O O pins pins -
(10) (10)
1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available.
2. The Flash can be configured in power-down mode. By default, it is not in power-down mode.
3. The SRAM clock can be gated on or off.
4. SRAM2 content is preserved when the bit RRS is set in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling Range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
3.9.5 Reset mode

In order to improve the consumption under reset, the I/Os state under and after reset is
“analog state” (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is
deactivated when the reset source is internal.
3.9.6 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present. The VBAT pin supplies the RTC with LSE and the backup registers. Three anti-
tamper detection pins are available in VBAT mode.
VBAT operation is automatically activated when VDD is not present.
An internal VBAT battery charging circuit is embedded and can be activated when VDD is
present.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
DS11421 Rev 5 31/220

56
3.10 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, low-power run
and sleep, Stop 0, Stop 1 and Stop 2 modes.
Table 5. STM32L443xx peripherals interconnect matrix
Low-power sleep
Low-power run
Stop 0 / Stop 1
Stop 2
Sleep
Interconnect
Run
Interconnect source Interconnect action
destination
TIMx Timers synchronization or chaining Y Y Y Y - -
ADCx
Conversion triggers Y Y Y Y - -
TIMx DAC1
DMA Memory to memory transfer trigger Y Y Y Y - -

COMPx Comparator output blanking Y Y Y Y - -
TIM15/TIM16 IRTIM Infrared interface output generation Y Y Y Y - -
TIM1 Timer input channel, trigger, break from
Y Y Y Y - -
TIM2 analog signals comparison
COMPx
Low-power timer triggered by analog Y
LPTIMERx Y Y Y Y Y (1)
signals comparison
ADCx TIM1 Timer triggered by analog watchdog Y Y Y Y - -

TIM16 Timer input channel from RTC events Y Y Y Y - -
RTC Low-power timer triggered by RTC alarms Y
LPTIMERx Y Y Y Y Y (1)
or tampers
All clocks sources (internal TIM2 Clock source used as input channel for
Y Y Y Y - -
and external) TIM15, 16 RC measurement and trimming
USB TIM2 Timer triggered by USB SOF Y Y - - - -
CSS
CPU (hard fault)
RAM (parity error) TIM1
Timer break Y Y Y Y - -
Flash memory (ECC error) TIM15,16
COMPx
PVD
32/220 DS11421 Rev 5

Table 5. STM32L443xx peripherals interconnect matrix (continued)
Low-power sleep
Low-power run
Stop 0 / Stop 1
Stop 2
Sleep
Interconnect
Run
Interconnect source Interconnect action
destination
TIMx External trigger Y Y Y Y - -

Y
LPTIMERx External trigger Y Y Y Y Y (1)
GPIO
ADCx
Conversion external trigger Y Y Y Y - -
DAC1
1. LPTIM1 only.
DS11421 Rev 5 33/220

56
3.11 Clocks and startup

The clock controller (see Figure 4) distributes the clocks coming from different oscillators to
the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 4-48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply
a PLL. The HSE can also be configured in bypass mode for an external clock.
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. In this mode the MSI can feed the
USB device. The MSI can supply a PLL.
– System PLL which can be fed by HSE, HSI16 or MSI, with a maximum frequency
at 80 MHz.
• RC48 with clock recovery system (HSI48): internal RC48 MHz clock source can be
used to drive the USB, the SDMMC or the RNG peripherals. This clock can be output
on the MCO.
• Auxiliary clock source: two ultralow-power clock sources that can be used to drive
the LCD controller and the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5% accuracy.
• Peripheral clock sources: Several peripherals (USB, SDMMC, RNG, SAI, USARTs,
I2Cs, LPTimers, ADC, SWPMI) have their own independent clock whatever the system
clock. Two PLLs, each having three independent outputs allowing the highest flexibility,
can generate independent clocks for the ADC, the USB/SDMMC/RNG and the SAI.
• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
• Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI16 and a software
34/220 DS11421 Rev 5

interrupt is generated if enabled. LSE failure can also be detected and generated an
interrupt.
• Clock-out capability:
– MCO: microcontroller clock output: it outputs one of the internal clocks for
external use by the application. Low frequency clocks (LSI, LSE) are available
down to Stop 1 low power state.
– LSCO: low speed clock output: it outputs LSI or LSE in all low-power modes
down to Standby mode. LSE can also be output on LSCO in Shutdown mode.
LSCO is not available in VBAT mode.
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB
domains is 80 MHz.
DS11421 Rev 5 35/220

56
Figure 4. Clock tree

to IWDG
LSI RC 32 kHz
LSCO
to RTC and LCD

OSC32_OUT
LSE OSC
/32
32.768 kHz
OSC32_IN
LSE
LSI
HSE
SYSCLK to PWR
MCO
/ 1→16
MSI
HSI16 to AHB bus, core, memory and DMA
Clock
HSI48 source
AHB HCLK FCLK Cortex free running clock
PLLCLK control
OSC_OUT HSE OSC PRESC
4-48 MHz / 1,2,..512
HSE to Cortex system timer
/8
OSC_IN Clock MSI
detector SYSCLK APB1 PCLK1
HSI16 PRESC
/ 1,2,4,8,16 to APB1 peripherals
HSI RC x1 or x2
to TIMx
16 MHz x=2,6,7
LSE
HSI16 to USARTx
SYSCLK x=2..3
to LPUART1
MSI RC HSI16
SYSCLK to I2Cx
100 kHz – 48 MHz x=1,2,3
LSI
LSE to LPTIMx
HSI16 x=1,2
HSI16
to SWPMI
MSI PCLK2
HSI16 APB2
PLL /M HSE PRESC to APB2 peripherals
VCO FVCO / P PLLSAI1CLK
/ 1,2,4,8,16
/Q PLL48M1CLK x1 or x2
to TIMx
/R PLLCLK
x=1,15,16
LSE
PLLSAI1 HSI16 to USART1
SYSCLK
VCO FVCO / P PLLSAI2CLK
/Q PLL48M2CLK
/R PLLADC1CLK
SYSCLK to ADC
HSI RC
48 MHz
HSI16 MSI
CRS
48 MHz clock to USB, RNG, SDMMC
HSI16
to SAI1
SAI1_EXTCLK
MSv36868V3
36/220 DS11421 Rev 5

3.12 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
3.13 Direct memory access controller (DMA)

The device embeds 2 DMAs. Refer to Table 6: DMA implementation for the features
implementation.
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 14 channels in total, each dedicated to managing memory
access requests from one or more peripherals. Each has an arbiter for handling the priority
between DMA requests.
The DMA supports:
• 14 independently configurable channels (requests)
• Each channel is connected to dedicated hardware DMA requests, software trigger is
also supported on each channel. This configuration is done by software.
• Priorities between requests from channels of one DMA are software programmable (4
levels consisting of very high, high, medium, low) or hardware in case of equality
(request 1 has priority over request 2, etc.)
• Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
• Support for circular buffer management
• 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
• Memory-to-memory transfer
• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
• Access to Flash, SRAM, APB and AHB peripherals as source and destination
• Programmable number of data to be transferred: up to 65536.
Table 6. DMA implementation

DMA features DMA1 DMA2
Number of regular channels 7 7
DS11421 Rev 5 37/220

56
3.14 Interrupts and events
3.14.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 67 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-
M4.
The NVIC benefits are the following:
• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved on interrupt entry, and restored on interrupt exit,
with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
3.14.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 37 edge detector lines used to generate
interrupt/event requests and wake-up the system from Stop mode. Each external line can be
independently configured to select the trigger event (rising edge, falling edge, both) and can
be masked independently. A pending register maintains the status of the interrupt requests.
The internal lines are connected to peripherals with wakeup from Stop mode capability. The
EXTI can detect an external line with a pulse width shorter than the internal clock period. Up
to 83 GPIOs can be connected to the 16 external interrupt lines.
38/220 DS11421 Rev 5

3.15 Analog to digital converter (ADC)

The device embeds a successive approximation analog-to-digital converter with the
following features:
• 12-bit native resolution, with built-in calibration
• 5.33 Msps maximum conversion rate with full resolution
– Down to 18.75 ns sampling time
– Increased conversion rate for lower resolution (up to 8.88 Msps for 6-bit
resolution)
• Up to 16 external channels.
• 5 internal channels: internal reference voltage, temperature sensor, VBAT/3,
DAC1_OUT1 and DAC1_OUT2.
• One external reference pin is available on some package, allowing the input voltage
range to be independent from the power supply
• Single-ended and differential mode inputs
• Low-power design
– Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
– Dual clock domain architecture: ADC speed independent from CPU frequency
• Highly versatile digital interface
– Single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
– ADC supports multiple trigger inputs for synchronization with on-chip timers and
external signals
– Results stored into data register or in RAM with DMA controller support
– Data pre-processing: left/right alignment and per channel offset compensation
– Built-in oversampling unit for enhanced SNR
– Channel-wise programmable sampling time
– Three analog watchdog for automatic voltage monitoring, generating interrupts
and trigger for selected timers
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching
3.15.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
DS11421 Rev 5 39/220

56
Table 7. Temperature sensor calibration values

Calibration value name Description Memory address
TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF 75A8 - 0x1FFF 75A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 130 °C (± 5 °C), 0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.15.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC and Comparators. VREFINT is internally connected to the ADC1_IN0 input
channel. The precise voltage of VREFINT is individually measured for each part by ST
during production test and stored in the system memory area. It is accessible in read-only
mode.
Table 8. Internal voltage reference calibration values

Calibration value name Description Memory address
Raw data acquired at a

VREFINT temperature of 30 °C (± 5 °C), 0x1FFF 75AA - 0x1FFF 75AB
VDDA = VREF+ = 3.0 V (± 10 mV)
3.15.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC1_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 3. As a consequence, the converted digital value is one third the VBAT voltage.
3.16 Digital to analog converter (DAC)

Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage
signal outputs. The chosen design structure is composed of integrated resistor strings and
an amplifier in inverting configuration.
40/220 DS11421 Rev 5

This digital interface supports the following features:

• Up to two DAC output channels
• 8-bit or 12-bit output mode
• Buffer offset calibration (factory and user trimming)
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
• Sample and hold low-power mode, with internal or external capacitor
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.17 Voltage reference buffer (VREFBUF)

The STM32L443xx devices embed an voltage reference buffer which can be used as
voltage reference for ADCs, DAC and also as voltage reference for external components
through the VREF+ pin.
The internal voltage reference buffer supports two voltages:
• 2.048 V
• 2.5 V
An external voltage reference can be provided through the VREF+ pin when the internal
voltage reference buffer is off.
The VREF+ pin is double-bonded with VDDA on some packages. In these packages the
internal voltage reference buffer is not available.
Figure 5. Voltage reference buffer
VREFBUF
VDDA DAC, ADC
Bandgap + VREF+
Low frequency
100 nF
cut-off capacitor
MSv40197V1
DS11421 Rev 5 41/220

56
3.18 Comparators (COMP)

The STM32L443xx devices embed two rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low-power) and
with selectable output polarity.
The reference voltage can be one of the following:
• External I/O
• DAC output channels
• Internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers
and can be also combined into a window comparator.
3.19 Operational amplifier (OPAMP)

The STM32L443xx embeds one operational amplifier with external or internal follower
routing and PGA capability.
The operational amplifier features:
• Low input bias current
• Low offset voltage
• Low-power mode
• Rail-to-rail input
3.20 Touch sensing controller (TSC)

The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode which is protected from direct touch by a dielectric (glass,
plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
42/220 DS11421 Rev 5

The main features of the touch sensing controller are the following:
• Proven and robust surface charge transfer acquisition principle
• Supports up to 21 capacitive sensing channels
• Up to 3 capacitive sensing channels can be acquired in parallel offering a very good
response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to I/O availability.
3.21 Liquid crystal display controller (LCD)

The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
• Internal step-up converter to guarantee functionality and contrast control irrespective of
VDD. This converter can be deactivated, in which case the VLCD pin is used to provide
the voltage to the LCD
• Supports static, 1/2, 1/3, 1/4 and 1/8 duty
• Supports static, 1/2, 1/3 and 1/4 bias
• Phase inversion to reduce power consumption and EMI
• Integrated voltage output buffers for higher LCD driving capability
• Up to 8 pixels can be programmed to blink
• Unneeded segments and common pins can be used as general I/O pins
• LCD RAM can be updated at any time owing to a double-buffer
• The LCD controller can operate in Stop mode
3.22 Random number generator (RNG)

All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
3.23 Advanced encryption standard hardware accelerator (AES)

The devices embed an AES hardware accelerator can be used to both encipher and
DS11421 Rev 5 43/220

56
decipher data using AES algorithm.

The AES peripheral supports:
• Encryption/Decryption using AES Rijndael Block Cipher algorithm
• NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm
• 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x
32-bit registers)
• Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois
Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher
Message Authentication Code mode (CMAC) supported.
• Key scheduler
• Key derivation for decryption
• 128-bit data block processing
• 128-bit, 256-bit key length
• 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer.
• Register access supporting 32-bit data width only.
• One 128-bit Register for the initialization vector when AES is configured in CBC mode
or for the 32-bit counter initialization when CTR mode is selected, GCM mode or
CMAC mode.
• Automatic data flow control with support of direct memory access (DMA) using 2
channels, one for incoming data, and one for outcoming data.
• Suspend a message if another message with a higher priority needs to be processed
3.24 Timers and watchdogs

The STM32L443xx includes one advanced control timers, up to five general-purpose timers,
two basic timers, two low-power timers, two watchdog timers and a SysTick timer. The table
below compares the features of the advanced control, general purpose and basic timers.
Table 9. Timer feature comparison

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Any integer
Advanced Up, down,
TIM1 16-bit between 1 Yes 4 3
control Up/down
and 65536
Any integer
General- Up, down,
TIM2 32-bit between 1 Yes 4 No
purpose Up/down
and 65536
Any integer
General-
TIM15 16-bit Up between 1 Yes 2 1
purpose
and 65536
44/220 DS11421 Rev 5

Table 9. Timer feature comparison (continued)

DMA Capture/
Counter Counter Prescaler Complementary
Timer type Timer request compare
resolution type factor outputs
generation channels
Any integer
General-
TIM16 16-bit Up between 1 Yes 1 1
purpose
and 65536
Any integer
Basic TIM6, TIM7 16-bit Up between 1 Yes 0 No
and 65536
3.24.1 Advanced-control timer (TIM1)

The advanced-control timer can each be seen as a three-phase PWM multiplexed on 6
channels. They have complementary PWM outputs with programmable inserted dead-
times. They can also be seen as complete general-purpose timers. The 4 independent
channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.24.2) using the same architecture, so the advanced-control timer can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
DS11421 Rev 5 45/220

56
3.24.2 General-purpose timers (TIM2, TIM15, TIM16)

There are up to three synchronizable general-purpose timers embedded in the
STM32L443xx (see Table 9 for differences). Each general-purpose timer can be used to
generate PWM outputs, or act as a simple time base.
• TIM2
It is a full-featured general-purpose timer:
TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler.
This timer features 4 independent channels for input capture/output compare, PWM or
one-pulse mode output. It can work with the other general-purpose timers via the Timer
Link feature for synchronization or event chaining.
The counter can be frozen in debug mode.
It has independent DMA request generation and support quadrature encoder.
• TIM15 and 16
They are general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
– TIM15 has 2 channels and 1 complementary channel
– TIM16 has 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.24.3 Basic timers (TIM6 and TIM7)

The basic timers are mainly used for DAC trigger generation. They can also be used as
generic 16-bit timebases.
3.24.4 Low-power timer (LPTIM1 and LPTIM2)

The devices embed two low-power timers. These timers have an independent clock and are
running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to
wakeup the system from Stop mode.
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 mode.
46/220 DS11421 Rev 5

This low-power timer supports the following features:

• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/ one shot mode
• Selectable software/hardware input trigger
• Selectable clock source
– Internal clock sources: LSE, LSI, HSI16 or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application).
• Programmable digital glitch filter
• Encoder mode (LPTIM1 only)
3.24.5 Infrared interface (IRTIM)

The STM32L443xx includes one infrared interface (IRTIM). It can be used with an infrared
LED to perform remote control functions. It uses TIM15 and TIM16 output channels to
generate output signal waveforms on IR_OUT pin.
3.24.6 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.
3.24.7 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.24.8 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
• A 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0.
• Programmable clock source
DS11421 Rev 5 47/220

56
3.25 Real-time clock (RTC) and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Three anti-tamper detection pins with programmable filter.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
• A 32.768 kHz external crystal (LSE)
• An external resonator or oscillator (LSE)
• The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
• The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes except Shutdown mode.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
48/220 DS11421 Rev 5

3.26 Inter-integrated circuit interface (I2C)

The device embeds three I2C. Refer to Table 10: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (Packet Error Checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 4: Clock tree.
• Wakeup from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 10. I2C implementation

I2C features(1) I2C1 I2C2 I2C3
Standard-mode (up to 100 kbit/s) X X X

Fast-mode (up to 400 kbit/s) X X X
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X
Programmable analog and digital noise filters X X X
SMBus/PMBus hardware support X X X
Independent clock X X X
Wakeup from Stop 0 / Stop 1 mode on address match X X X
Wakeup from Stop 2 mode on address match - - X
1. X: supported
DS11421 Rev 5 49/220

56
3.27 Universal synchronous/asynchronous receiver transmitter

(USART)
The STM32L443xx devices have three embedded universal synchronous receiver
transmitters (USART1, USART2 and USART3).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
10Mbit/s.
USART1, USART2 and USART3 also provide Smart Card mode (ISO 7816 compliant) and
SPI-like communication capability.
All USART have a clock domain independent from the CPU clock, allowing the USARTx
(x=1,2,3) to wake up the MCU from Stop mode using baudrates up to 204 Kbaud. The wake
up events from Stop mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 11. STM32L443xx USART/LPUART features

USART modes/features(1) USART1 USART2 USART3 LPUART1
Hardware flow control for modem X X X X

Continuous communication using DMA X X X X
Multiprocessor communication X X X X
Synchronous mode X X X -
Smartcard mode X X X -
Single-wire half-duplex communication X X X X
IrDA SIR ENDEC block X X X -
LIN mode X X X -
Dual clock domain X X X X
Wakeup from Stop 0 / Stop 1 modes X X X X
Wakeup from Stop 2 mode - - - X
Receiver timeout interrupt X X X -
Modbus communication X X X -
Auto baud rate detection X (4 modes) -
Driver Enable X X X X
LPUART/USART data length 7, 8 and 9 bits
1. X = supported.
50/220 DS11421 Rev 5

3.28 Low-power universal asynchronous receiver transmitter

(LPUART)
The device embeds one Low-Power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop
mode are programmable and can be:
• Start bit detection
• Any received data frame
• A specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.
DS11421 Rev 5 51/220

56
3.29 Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to 40 Mbits/s in master and up to 24 Mbits/s
slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8
master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI
interfaces support NSS pulse mode, TI mode and Hardware CRC calculation.
All SPI interfaces can be served by the DMA controller.
3.30 Serial audio interfaces (SAI)

The device embeds 1 SAI. Refer to Table 12: SAI implementation for the features
implementation. The SAI bus interface handles communications between the
microcontroller and the serial audio protocol.
The SAI peripheral supports:
• Two independent audio sub-blocks which can be transmitters or receivers with their
respective FIFO.
• 8-word integrated FIFOs for each audio sub-block.
• Synchronous or asynchronous mode between the audio sub-blocks.
• Master or slave configuration independent for both audio sub-blocks.
• Clock generator for each audio block to target independent audio frequency sampling
when both audio sub-blocks are configured in master mode.
• Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.
• Peripheral with large configurability and flexibility allowing to target as example the
following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF
out.
• Up to 16 slots available with configurable size and with the possibility to select which
ones are active in the audio frame.
• Number of bits by frame may be configurable.
• Frame synchronization active level configurable (offset, bit length, level).
• First active bit position in the slot is configurable.
• LSB first or MSB first for data transfer.
• Mute mode.
• Stereo/Mono audio frame capability.
• Communication clock strobing edge configurable (SCK).
• Error flags with associated interrupts if enabled respectively.
– Overrun and underrun detection.
– Anticipated frame synchronization signal detection in slave mode.
– Late frame synchronization signal detection in slave mode.
– Codec not ready for the AC’97 mode in reception.
• Interruption sources when enabled:
– Errors.
– FIFO requests.
• DMA interface with 2 dedicated channels to handle access to the dedicated integrated
FIFO of each SAI audio sub-block.
52/220 DS11421 Rev 5

Table 12. SAI implementation

SAI features Support(1)
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 X

Mute mode X
Stereo/Mono audio frame capability. X
16 slots X
Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit X
FIFO Size X (8 Word)
SPDIF X
1. X: supported
3.31 Single wire protocol master interface (SWPMI)

The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
• full-duplex communication mode
• automatic SWP bus state management (active, suspend, resume)
• configurable bitrate up to 2 Mbit/s
• automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
3.32 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
DS11421 Rev 5 53/220

56
The CAN peripheral supports:

• Supports CAN protocol version 2.0 A, B Active
• Bit rates up to 1 Mbit/s
• Transmission
– Three transmit mailboxes
– Configurable transmit priority
• Reception
– Two receive FIFOs with three stages
– 14 Scalable filter banks
– Identifier list feature
– Configurable FIFO overrun
• Time-triggered communication option
– Disable automatic retransmission mode
– 16-bit free running timer
– Time Stamp sent in last two data bytes
• Management
– Maskable interrupts
– Software-efficient mailbox mapping at a unique address space
3.33 Secure digital input/output and MultiMediaCards Interface

(SDMMC)
The card host interface (SDMMC) provides an interface between the APB peripheral bus
and MultiMediaCards (MMCs), SD memory cards and SDIO cards.
The SDMMC features include the following:
• Full compliance with MultiMediaCard System Specification Version 4.2. Card support
for three different databus modes: 1-bit (default), 4-bit and 8-bit
• Full compatibility with previous versions of MultiMediaCards (forward compatibility)
• Full compliance with SD Memory Card Specifications Version 2.0
• Full compliance with SD I/O Card Specification Version 2.0: card support for two
different databus modes: 1-bit (default) and 4-bit
• Data transfer up to 48 MHz for the 8 bit mode
• Data write and read with DMA capability
3.34 Universal serial bus (USB)

The STM32L443xx devices embed a full-speed USB device peripheral compliant with the
USB specification version 2.0. The internal USB PHY supports USB FS signaling,
embedded DP pull-up and also battery charging detection according to Battery Charging
Specification Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function
interface with added support for USB 2.0 Link Power Management. It has software-
configurable endpoint setting with packet memory up-to 1 KB and suspend/resume support.
It requires a precise 48 MHz clock which can be generated from the internal main PLL (the
clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in
54/220 DS11421 Rev 5

automatic trimming mode. The synchronization for this oscillator can be taken from the USB
data stream itself (SOF signalization) which allows crystal less operation.
3.35 Clock recovery system (CRS)

The STM32L443xx devices embed a special block which allows automatic trimming of the
internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device
operational range. This automatic trimming is based on the external synchronization signal,
which could be either derived from USB SOF signalization, from LSE oscillator, from an
external signal on CRS_SYNC pin or generated by user software. For faster lock-in during
startup it is also possible to combine automatic trimming with manual trimming action.
3.36 Quad SPI memory interface (QUADSPI)

The Quad SPI is a specialized communication interface targeting single, dual or quad SPI
flash memories. It can operate in any of the three following modes:
• Indirect mode: all the operations are performed using the QUADSPI registers
• Status polling mode: the external flash status register is periodically read and an
interrupt can be generated in case of flag setting
• Memory-mapped mode: the external Flash is memory mapped and is seen by the
system as if it were an internal memory
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
Quad SPI flash memories are accessed simultaneously.
The Quad SPI interface supports:
• Three functional modes: indirect, status-polling, and memory-mapped
• Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two
flash memories in parallel.
• SDR and DDR support
• Fully programmable opcode for both indirect and memory mapped mode
• Fully programmable frame format for both indirect and memory mapped mode
• Each of the 5 following phases can be configured independently (enable, length,
single/dual/quad communication)
– Instruction phase
– Address phase
– Alternate bytes phase
– Dummy cycles phase
– Data phase
• Integrated FIFO for reception and transmission
• 8, 16, and 32-bit data accesses are allowed
• DMA channel for indirect mode operations
• Programmable masking for external flash flag management
• Timeout management
• Interrupt generation on FIFO threshold, timeout, status match, operation complete, and
access error
DS11421 Rev 5 55/220

56
3.37 Development support
3.37.1 Serial wire JTAG debug port (SWJ-DP)

The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.37.2 Embedded Trace Macrocell™

The Arm® Embedded Trace Macrocell™ provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L443xx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. Real-time instruction and data flow activity be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell™ operates with third party debugger software tools.
56/220 DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC Pinouts and pin description
4 Pinouts and pin description
Figure 6. STM32L443Vx LQFP100 pinout(1)
PH3-BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VDDUSB
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF- 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
VSS
PE10
PE12
PE13
PE14
PE15
PB10
VDD
PA3
PA4
PA5
PA6
PA7
PE11
PB11
MSv36893V3
1. The above figure shows the package top view.
DS11421 Rev 5 57/220

86
Pinouts and pin description STM32L443CC STM32L443RC STM32L443VC
Figure 7. STM32L443Vx UFBGA100 ballout(1)

1 2 3 4 5 6 7 8 9 10 11 12
A PE3 PE1 PB8 PH3-BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PA13 PA12
B PE4 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11
C PC13 PE5 PE0 VDD PB5 PD2 PD0 PC11 VDDUSB PA10
PC14-
D PE6 VSS PA9 PA8 PC9
OSC32_IN
PC15-
E VBAT VSS PC8 PC7 PC6
OSC32_OUT
F PH0-OSC_IN VSS VSS VSS
PH1-
UFBGA100
G VDD VDD VDD
OSC_OUT
H PC0 NRST VDD PD15 PD14 PD13
J VSSA PC1 PC2 PD12 PD11 PD10
K VREF- PC3 PA2 PA5 PC4 PD9 PD8 PB15 PB14 PB13
L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 PE10 PE12 PB10 PB11 PB12
M VDDA PA1 PA4 PA7 PB0 PB1 PE7 PE9 PE11 PE13 PE14 PE15
MSv36894V3
Figure 8. STM32L443Rx LQFP64 pinout(1)

PH3-BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD2
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDDUSB
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA/VREF- 12 37 PC6
VDDA/VREF+ 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD
PC4
PC5
PB0
PB1
PB2
VSS
PB10
VDD
PA3
PA4
PA5
PA6
PA7
PB11
MSv36895V3
58/220 DS11421 Rev 5

Figure 9. STM32L443Rx UFBGA64 ballout(1)

1 2 3 4 5 6 7 8
PC14-
A PC13 PB9 PB4 PB3 PA15 PA14 PA13
OSC32_IN
PC15-
B VBAT PB8 PH3-BOOT0 PD2 PC11 PC10 PA12
OSC32_OUT
C PH0-OSC_IN VSS PB7 PB5 PC12 PA10 PA9 PA11
PH1-
D VDD PB6 VSS VSS VSS PA8 PC9
OSC_OUT
E NRST PC1 PC0 VDD VDDUSB VDD PC7 PC8
F VSSA/VREF- PC2 PA2 PA5 PB0 PC6 PB15 PB14
G PC3 PA0 PA3 PA6 PB1 PB2 PB10 PB13
H VDDA/VREF+ PA1 PA4 PA7 PC4 PC5 PB11 PB12
MSv36896V3
Figure 10. STM32L443Rx WLCSP64 pinout(1)

1 2 3 4 5 6 7 8
A VDDUSB PA15 PC12 PD2 PB3 PB7 VSS VDD
B VSS PA14 PC11 PB4 PB6 PB9 VBAT PC13
PC15- PC14-
C PA12 PA13 PC10 PB5 PH3-BOOT0 PB8
OSC32_OUT OSC32_IN
PH1-
D PA9 PA10 PA11 PC4 PC0 NRST PH0-OSC_IN
OSC_OUT
E PC7 PC9 PA8 PC5 PA4 PC3 PC2 PC1
F PC6 PB15 PC8 PB0 PA5 PA2 PA0 VSSA/VREF-
G PB14 PB13 PB12 PB2 PA6 PA3 PA1 VDDA/VREF+
H VDD VSS PB11 PB10 PB1 PA7 VDD VSS
MSv38084V3
Figure 11. STM32L443Cx WLCSP49 pinout(1)

1 2 3 4 5 6 7
A VDDUSB PA14 PB3 PB4 PH3-BOOT0 VSS VDD
B VSS PA13 PA15 PB5 PB8 VBAT PC13
PC15- PC14-
C PA11 PA10 PA12 PB6 PB9
OSC32_OUT OSC32_IN
PH1-
D PA8 PA9 PB15 PB7 NRST PH0-OSC_IN
OSC_OUT
E PB14 PB13 PB10 PA3 PA2 PC3 VSSA/VREF-
F PB12 PB11 PA7 PA6 PA5 PA0 VDDA/VREF+
G VDD VSS PB2 PB1 PB0 PA4 PA1
MSv38085V3
DS11421 Rev 5 59/220

86
Figure 12. STM32L443Cx LQFP48 pinout(1)
PH3-BOOT0
PA15
PA14
VDD
VSS
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDDUSB
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
NRST 7
LQFP48 30 PA9
VSSA/VREF- 8 29 PA8
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
VSS
PB10
VDD
PA3
PA4
PA5
PA6
PA7
PB11
MSv36897V3
Figure 13. STM32L443Cx UFQFPN48 pinout(1)

PH3-BOOT0
PA15
PA14
VDD
VSS
PB9
PB8
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 VDDUSB
PC13 2 35 VSS
PC14-OSC32_IN 3 34 PA13
NRST 7
UFQFPN48 30 PA9
VSSA/VREF- 8 29 PA8
PA0 10 27 PB14
PA1 11 26 PB13
PA2 12 25 PB12
13
14
15
16
17
18
19
20
21
22
23
24
PB0
PB1
PB2
VSS
PB10
VDD
PA3
PA4
PA5
PA6
PA7
PB11
MSv38086V3
60/220 DS11421 Rev 5

Table 13. Legend/abbreviations used in the pinout table

Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
RST Bidirectional reset pin with embedded weak pull-up resistor
Option for TT or FT I/Os

I/O structure
_f (1) I/O, Fm+ capable
_l (2)
I/O, with LCD function supplied by VLCD
(3)
_u I/O, with USB function supplied by VDDUSB
(4)
_a I/O, with Analog switch function supplied by VDDA
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 14 are: FT_f, FT_fa, FT_fl, FT_fla.
2. The related I/O structures in Table 14 are: FT_l, FT_fl, FT_lu.
3. The related I/O structures in Table 14 are: FT_u, FT_lu.
4. The related I/O structures in Table 14 are: FT_a, FT_la, FT_fa, FT_fla, TT_a, TT_la.
Table 14. STM32L443xx pin definitions

Pin Number Pin functions
(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48
LQFP64
Alternate functions
functions
Notes
TRACECK, TSC_G7_IO1,
LCD_SEG38,
- - - - - - 1 B2 PE2 I/O FT_l - -
SAI1_MCLK_A,
EVENTOUT
TRACED0, TSC_G7_IO2,
- - - - - - 2 A1 PE3 I/O FT_l - LCD_SEG39, SAI1_SD_B, -
EVENTOUT
- - - - - - 3 B1 PE4 I/O FT - -
SAI1_FS_A, EVENTOUT
DS11421 Rev 5 61/220

86
Table 14. STM32L443xx pin definitions (continued)

(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48
LQFP64 Alternate functions

functions
Notes
- - - - - - 4 C2 PE5 I/O FT - -
SAI1_SCK_A, EVENTOUT
TRACED3, SAI1_SD_A, RTC_TAMP3/
- - - - - - 5 D2 PE6 I/O FT -
EVENTOUT WKUP3
1 1 B6 B7 1 B2 6 E2 VBAT S - - - -
RTC_TAMP1/
(1)
RTC_TS/
2 2 B7 B8 2 A2 7 C1 PC13 I/O FT (2) EVENTOUT
RTC_OUT/
WKUP2
PC14- (1)
3 3 C7 C8 3 A1 8 D1 OSC32_I I/O FT (2) EVENTOUT OSC32_IN
N (PC14)
PC15-
(1)
OSC32_
4 4 C6 C7 4 B1 9 E1 I/O FT (2) EVENTOUT OSC32_OUT
OUT
(PC15)
- - - - - - 10 F2 VSS S - - - -
- - - - - - 11 G2 VDD S - - - -
PH0-
5 5 D7 D8 5 C1 12 F1 OSC_ I/O FT - EVENTOUT OSC_IN
IN (PH0)
PH1-
6 6 D6 D7 6 D1 13 G1 OSC_OU I/O FT - EVENTOUT OSC_OUT
T (PH1)
7 7 D5 D6 7 E1 14 H2 NRST I/O RST - - -
LPTIM1_IN1, I2C3_SCL,
LPUART1_RX,
- - - D5 8 E3 15 H1 PC0 I/O FT_fla - ADC1_IN1
LCD_SEG18,
LPTIM2_IN1, EVENTOUT
LPTIM1_OUT, I2C3_SDA,
- - - E8 9 E2 16 J2 PC1 I/O FT_fla - LPUART1_TX, ADC1_IN2
LCD_SEG19, EVENTOUT
LPTIM1_IN2, SPI2_MISO,
- - - E7 10 F2 17 J3 PC2 I/O FT_la - ADC1_IN3
LCD_SEG20, EVENTOUT
LPTIM1_ETR,
SPI2_MOSI, LCD_VLCD,
- - E6 E6 11 G1 18 K2 PC3 I/O FT_a - SAI1_SD_A, ADC1_IN4
LPTIM2_ETR,
EVENTOUT
- - - - - - 19 J1 VSSA S - - - -
62/220 DS11421 Rev 5


(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48

functions
Notes
- - - - - - 20 K1 VREF- S - - - -
VSSA/
8 8 E7 F8 12 F1 - - S - - - -
VREF-
- - - - - - 21 L1 VREF+ S - - - VREFBUF_OUT
- - - - - - 22 M1 VDDA S - - - -
VDDA/
9 9 F7 G8 13 H1 - - S - - - -
VREF+
TIM2_CH1, OPAMP1_VINP,
USART2_CTS, COMP1_INM,
10 10 F6 F7 14 G2 23 L2 PA0 I/O FT_a - COMP1_OUT, ADC1_IN5,
SAI1_EXTCLK, RTC_TAMP2/
TIM2_ETR, EVENTOUT WKUP1
TIM2_CH2, I2C1_SMBA,
SPI1_SCK,
OPAMP1_VINM,
USART2_RTS_DE,
11 11 G7 G7 15 H2 24 M2 PA1 I/O FT_la - COMP1_INP,
LCD_SEG0,
ADC1_IN6
TIM15_CH1N,
EVENTOUT
TIM2_CH3, USART2_TX,
LPUART1_TX,
COMP2_INM,
QUADSPI_BK1_NCS,
12 12 E5 F6 16 F3 25 K3 PA2 I/O FT_la - ADC1_IN7,
LCD_SEG1,
WKUP4/LSCO
COMP2_OUT,
TIM15_CH1, EVENTOUT
TIM2_CH4, USART2_RX,
LPUART1_RX,
OPAMP1_VOUT,
QUADSPI_CLK,
13 13 E4 G6 17 G3 26 L3 PA3 I/O TT_la - COMP2_INP,
LCD_SEG2,
ADC1_IN8
SAI1_MCLK_A,
TIM15_CH2, EVENTOUT
- - - H8 18 C2 27 E3 VSS S - - - -
- - - H7 19 D2 28 H3 VDD S - - - -
SPI1_NSS, SPI3_NSS, COMP1_INM,
USART2_CK, SAI1_FS_B, COMP2_INM,
14 14 G6 E5 20 H3 29 M3 PA4 I/O TT_a -
LPTIM2_OUT, ADC1_IN9,
EVENTOUT DAC1_OUT1
COMP1_INM,
TIM2_CH1, TIM2_ETR,
COMP2_INM,
15 15 F5 F5 21 F4 30 K4 PA5 I/O TT_a - SPI1_SCK, LPTIM2_ETR,
ADC1_IN10,
EVENTOUT
DAC1_OUT2
DS11421 Rev 5 63/220

86

(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48

functions
Notes
TIM1_BKIN, SPI1_MISO,
USART3_CTS,
LPUART1_CTS,
QUADSPI_BK1_IO3,
16 16 F4 G5 22 G4 31 L4 PA6 I/O FT_la - ADC1_IN11
LCD_SEG3,
COMP1_OUT/TIM1_BKIN
_COMP2, TIM16_CH1,
EVENTOUT
TIM1_CH1N, I2C3_SCL,
SPI1_MOSI,
QUADSPI_BK1_IO2,
17 17 F3 H6 23 H4 32 M4 PA7 I/O FT_fla - ADC1_IN12
LCD_SEG4,
COMP2_OUT,
EVENTOUT
USART3_TX, COMP1_INM,
- - - D4 24 H5 33 K5 PC4 I/O FT_la -
LCD_SEG22, EVENTOUT ADC1_IN13
COMP1_INP,
USART3_RX,
- - - E4 25 H6 34 L5 PC5 I/O FT_la - ADC1_IN14,
LCD_SEG23, EVENTOUT
WKUP5
TIM1_CH2N, SPI1_NSS,
USART3_CK,
QUADSPI_BK1_IO1,
18 18 G5 F4 26 F5 35 M5 PB0 I/O FT_la - LCD_SEG5, ADC1_IN15
COMP1_OUT,
SAI1_EXTCLK,
EVENTOUT
TIM1_CH3N,
USART3_RTS_DE,
LPUART1_RTS_DE, COMP1_INM,
19 19 G4 H5 27 G5 36 M6 PB1 I/O FT_la -
QUADSPI_BK1_IO0, ADC1_IN16
LCD_SEG6, LPTIM2_IN1,
EVENTOUT
RTC_OUT, LPTIM1_OUT,
20 20 G3 G4 28 G6 37 L6 PB2 I/O FT_a - I2C3_SMBA, LCD_VLCD, COMP1_INP
EVENTOUT
TIM1_ETR, SAI1_SD_B,
- - - - - - 38 M7 PE7 I/O FT - -
EVENTOUT
TIM1_CH1N,
- - - - - - 39 L7 PE8 I/O FT - -
SAI1_SCK_B, EVENTOUT
TIM1_CH1, SAI1_FS_B,
- - - - - - 40 M8 PE9 I/O FT - -
EVENTOUT
64/220 DS11421 Rev 5


(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48

functions
Notes
TIM1_CH2N,
TSC_G5_IO1,
- - - - - - 41 L8 PE10 I/O FT - QUADSPI_CLK, -
SAI1_MCLK_B,
EVENTOUT
TIM1_CH2, TSC_G5_IO2,
- - - - - - 42 M9 PE11 I/O FT - QUADSPI_BK1_NCS, -
EVENTOUT
TIM1_CH3N, SPI1_NSS,
TSC_G5_IO3,
- - - - - - 43 L9 PE12 I/O FT - -
QUADSPI_BK1_IO0,
EVENTOUT
TIM1_CH3, SPI1_SCK,
TSC_G5_IO4,
- - - - - - 44 M10 PE13 I/O FT - -
QUADSPI_BK1_IO1,
EVENTOUT
TIM1_CH4, TIM1_BKIN2,
TIM1_BKIN2_COMP2,
- - - - - - 45 M11 PE14 I/O FT - SPI1_MISO, -
QUADSPI_BK1_IO2,
EVENTOUT
TIM1_BKIN,
TIM1_BKIN_COMP1,
- - - - - - 46 M12 PE15 I/O FT - SPI1_MOSI, -
QUADSPI_BK1_IO3,
EVENTOUT
TIM2_CH3, I2C2_SCL,
SPI2_SCK, USART3_TX,
LPUART1_RX,
TSC_SYNC,
21 21 E3 H4 29 G7 47 L10 PB10 I/O FT_fl - -
QUADSPI_CLK,
LCD_SEG10,
COMP1_OUT,
SAI1_SCK_A, EVENTOUT
TIM2_CH4, I2C2_SDA,
USART3_RX,
LPUART1_TX,
22 22 F2 H3 30 H7 48 L11 PB11 I/O FT_fl - QUADSPI_BK1_NCS, -
LCD_SEG11,
COMP2_OUT,
EVENTOUT
23 23 G2 H2 31 D6 49 F12 VSS S - - - -
24 24 G1 H1 32 E6 50 G12 VDD S - - - -
DS11421 Rev 5 65/220

86

(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48

functions
Notes
TIM1_BKIN,
TIM1_BKIN_COMP2,
I2C2_SMBA, SPI2_NSS,
USART3_CK,
25 25 F1 G3 33 H8 51 L12 PB12 I/O FT_l - LPUART1_RTS_DE, -
TSC_G1_IO1,
LCD_SEG12,
SWPMI1_IO, SAI1_FS_A,
TIM15_BKIN, EVENTOUT
TIM1_CH1N, I2C2_SCL,
SPI2_SCK,
USART3_CTS,
LPUART1_CTS,
TSC_G1_IO2,
26 26 E2 G2 34 G8 52 K12 PB13 I/O FT_fl - -
LCD_SEG13,
SWPMI1_TX,
SAI1_SCK_A,
TIM15_CH1N,
EVENTOUT
TIM1_CH2N, I2C2_SDA,
SPI2_MISO,
USART3_RTS_DE,
TSC_G1_IO3,
27 27 E1 G1 35 F8 53 K11 PB14 I/O FT_fl - -
LCD_SEG14,
SWPMI1_RX,
SAI1_MCLK_A,
TIM15_CH1, EVENTOUT
RTC_REFIN, TIM1_CH3N,
SPI2_MOSI,
TSC_G1_IO4,
28 28 D3 F2 36 F7 54 K10 PB15 I/O FT_l - LCD_SEG15, -
SWPMI1_SUSPEND,
SAI1_SD_A, TIM15_CH2,
EVENTOUT
USART3_TX,
- - - - - - 55 K9 PD8 I/O FT_l - -
LCD_SEG28, EVENTOUT
USART3_RX,
- - - - - - 56 K8 PD9 I/O FT_l - -
LCD_SEG29, EVENTOUT
USART3_CK,
- - - - - - 57 J12 PD10 I/O FT_l - TSC_G6_IO1, -
LCD_SEG30, EVENTOUT
66/220 DS11421 Rev 5


(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48

functions
Notes
USART3_CTS,
TSC_G6_IO2,
- - - - - - 58 J11 PD11 I/O FT_l - LCD_SEG31, -
LPTIM2_ETR,
EVENTOUT
USART3_RTS_DE,
TSC_G6_IO3,
- - - - - - 59 J10 PD12 I/O FT_l - -
LCD_SEG32,
LPTIM2_IN1, EVENTOUT
TSC_G6_IO4,
LCD_SEG33,
- - - - - - 60 H12 PD13 I/O FT_l - -
LPTIM2_OUT,
EVENTOUT
- - - - - - 61 H11 PD14 I/O FT_l - LCD_SEG34, EVENTOUT -
- - - - - - 62 H10 PD15 I/O FT_l - LCD_SEG35, EVENTOUT -
TSC_G4_IO1,
LCD_SEG24,
- - - F1 37 F6 63 E12 PC6 I/O FT_l - -
SDMMC1_D6,
EVENTOUT
TSC_G4_IO2,
LCD_SEG25,
- - - E1 38 E7 64 E11 PC7 I/O FT_l - -
SDMMC1_D7,
EVENTOUT
TSC_G4_IO3,
LCD_SEG26,
- - - F3 39 E8 65 E10 PC8 I/O FT_l - -
SDMMC1_D0,
EVENTOUT
TSC_G4_IO4, USB_NOE,
LCD_SEG27,
- - - E2 40 D8 66 D12 PC9 I/O FT_l - -
SDMMC1_D1,
EVENTOUT
MCO, TIM1_CH1,
USART1_CK,
LCD_COM0, SWPMI1_IO,
29 29 D1 E3 41 D7 67 D11 PA8 I/O FT_l - -
SAI1_SCK_A,
LPTIM2_OUT,
EVENTOUT
TIM1_CH2, I2C1_SCL,
USART1_TX,
30 30 D2 D1 42 C7 68 D10 PA9 I/O FT_fl - -
LCD_COM1, SAI1_FS_A,
TIM15_BKIN, EVENTOUT
DS11421 Rev 5 67/220

86

(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48

functions
Notes
TIM1_CH3, I2C1_SDA,
USART1_RX,
31 31 C2 D2 43 C6 69 C12 PA10 I/O FT_fl - USB_CRS_SYNC, -
LCD_COM2, SAI1_SD_A,
EVENTOUT
TIM1_CH4, TIM1_BKIN2,
SPI1_MISO,
USART1_CTS, CAN1_RX,
32 32 C1 D3 44 C8 70 B12 PA11 I/O FT_u - COMP1_OUT
USB_DM,
TIM1_BKIN2_COMP1,
EVENTOUT
TIM1_ETR, SPI1_MOSI,
USART1_RTS_DE,
33 33 C3 C1 45 B8 71 A12 PA12 I/O FT_u - -
CAN1_TX, USB_DP,
EVENTOUT
PA13 JTMS-SWDIO, IR_OUT,
(3)
34 34 B2 C2 46 A8 72 A11 (JTMS- I/O FT USB_NOE, SWPMI1_TX, -
SWDIO) SAI1_SD_B, EVENTOUT
35 35 B1 B1 47 D5 - - VSS S - - - -
VDD
36 36 A1 A1 48 E5 73 C11 S - - - -
USB
- - - - - - 74 F11 VSS S - - - -
- - - - - - 75 G11 VDD S - - - -
JTCK-SWCLK,
PA14 LPTIM1_OUT,
37 37 A2 B2 49 A7 76 A10 (JTCK- I/O FT (3)
I2C1_SMBA, -
SWCLK) SWPMI1_RX, SAI1_FS_B,
EVENTOUT
JTDI, TIM2_CH1,
TIM2_ETR, USART2_RX,
SPI1_NSS, SPI3_NSS,
PA15 (3) USART3_RTS_DE,
38 38 B3 A2 50 A6 77 A9 I/O FT_l -
(JTDI) TSC_G3_IO1,
LCD_SEG17,
SWPMI1_SUSPEND,
EVENTOUT
SPI3_SCK, USART3_TX,
TSC_G3_IO2,
LCD_COM4/LCD_SEG28/
- - - C3 51 B7 78 B11 PC10 I/O FT_l - -
LCD_SEG40,
SDMMC1_D2,
EVENTOUT
68/220 DS11421 Rev 5


(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48

functions
Notes
SPI3_MISO, USART3_RX,
TSC_G3_IO3,
LCD_COM5/LCD_SEG29/
- - - B3 52 B6 79 C10 PC11 I/O FT_l - -
LCD_SEG41,
SDMMC1_D3,
EVENTOUT
SPI3_MOSI, USART3_CK,
TSC_G3_IO4,
LCD_COM6/LCD_SEG30/
- - - A3 53 C5 80 B10 PC12 I/O FT_l - -
LCD_SEG42,
SDMMC1_CK,
EVENTOUT
SPI2_NSS, CAN1_RX,
- - - - - - 81 C9 PD0 I/O FT - -
EVENTOUT
SPI2_SCK, CAN1_TX,
- - - - - - 82 B9 PD1 I/O FT - -
EVENTOUT
USART3_RTS_DE,
TSC_SYNC,
LCD_COM7/LCD_SEG31/
- - - A4 54 B5 83 C8 PD2 I/O FT_l - -
LCD_SEG43,
SDMMC1_CMD,
EVENTOUT
SPI2_MISO,
USART2_CTS,
- - - - - - 84 B8 PD3 I/O FT - -
QUADSPI_BK2_NCS,
EVENTOUT
SPI2_MOSI,
USART2_RTS_DE,
- - - - - - 85 B7 PD4 I/O FT - -
QUADSPI_BK2_IO0,
EVENTOUT
USART2_TX,
- - - - - - 86 A6 PD5 I/O FT - QUADSPI_BK2_IO1, -
EVENTOUT
USART2_RX,
- - - - - - 87 B6 PD6 I/O FT - QUADSPI_BK2_IO2, -
SAI1_SD_A, EVENTOUT
USART2_CK,
- - - - - - 88 A5 PD7 I/O FT - QUADSPI_BK2_IO3, -
EVENTOUT
DS11421 Rev 5 69/220

86

(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48

functions
Notes
JTDO-TRACESWO,
PB3 TIM2_CH2, SPI1_SCK,
(JTDO- SPI3_SCK,
39 39 A3 A5 55 A5 89 A8 I/O FT_la (3) COMP2_INM
TRACE USART1_RTS_DE,
SWO) LCD_SEG7,
SAI1_SCK_B, EVENTOUT
NJTRST, I2C3_SDA,
SPI1_MISO, SPI3_MISO,
USART1_CTS,
PB4
40 40 A4 B4 56 A4 90 A7 I/O FT_fla (3) TSC_G2_IO1, COMP2_INP
(NJTRST)
LCD_SEG8,
SAI1_MCLK_B,
EVENTOUT
LPTIM1_IN1, I2C1_SMBA,
SPI1_MOSI, SPI3_MOSI,
USART1_CK,
TSC_G2_IO2,
41 41 B4 C4 57 C4 91 C5 PB5 I/O FT_l - -
LCD_SEG9,
COMP2_OUT,
SAI1_SD_B, TIM16_BKIN,
EVENTOUT
LPTIM1_ETR, I2C1_SCL,
USART1_TX,
TSC_G2_IO3,
42 42 C4 B5 58 D3 92 B5 PB6 I/O FT_fa - COMP2_INP
SAI1_FS_B,
TIM16_CH1N,
EVENTOUT
LPTIM1_IN2, I2C1_SDA,
USART1_RX, COMP2_INM,
43 43 D4 A6 59 C3 93 B4 PB7 I/O FT_fla -
TSC_G2_IO4, PVD_IN
LCD_SEG21, EVENTOUT
PH3/
44 44 A5 C5 60 B4 94 A4 I/O FT - EVENTOUT BOOT0
BOOT0
I2C1_SCL, CAN1_RX,
LCD_SEG16,
45 45 B5 C6 61 B3 95 A3 PB8 I/O FT_fl - SDMMC1_D4, -
SAI1_MCLK_A,
TIM16_CH1, EVENTOUT
IR_OUT, I2C1_SDA,
SPI2_NSS, CAN1_TX,
46 46 C5 B6 62 A3 96 B3 PB9 I/O FT_fl - LCD_COM3, -
SDMMC1_D5,
SAI1_FS_A, EVENTOUT
70/220 DS11421 Rev 5


(function after
Pin name
I/O structure
UFQFPN48
UFBGA100
reset)
WLCSP49
WLCSP64
UFBGA64
LQFP100
Additional
Pin type
LQFP48

functions
Notes
LCD_SEG36, TIM16_CH1,
- - - - - - 97 C3 PE0 I/O FT_l - -
EVENTOUT
- - - - - - 98 A2 PE1 I/O FT_l - LCD_SEG37, EVENTOUT -
47 47 A6 A7 63 D4 99 D3 VSS S - - - -
48 48 A7 A8 64 E4 100 C4 VDD S - - - -
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After a Backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of
the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
domain and RTC register descriptions in the RM0394 reference manual.
3. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13, PB4
pins and the internal pull-down on PA14 pin are activated.
DS11421 Rev 5 71/220

86
72/220
Pinouts and pin description

Table 15. Alternate function AF0 to AF7(1)
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Port USART1/
TIM1/TIM2/
SYS_AF TIM1/TIM2 USART2 I2C1/I2C2/I2C3 SPI1/SPI2 SPI3 USART2/
LPTIM1
USART3
PA0 - TIM2_CH1 - - - - - USART2_CTS

USART2_RTS_
PA1 - TIM2_CH2 - - I2C1_SMBA SPI1_SCK -
DE
PA2 - TIM2_CH3 - - - - - USART2_TX
PA3 - TIM2_CH4 - - - - - USART2_RX
PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK
PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - -
DS11421 Rev 5
PA6 - TIM1_BKIN - - - SPI1_MISO COMP1_OUT USART3_CTS

PA7 - TIM1_CH1N - - I2C3_SCL SPI1_MOSI - -
Port A PA8 MCO TIM1_CH1 - - - - - USART1_CK

PA9 - TIM1_CH2 - - I2C1_SCL - - USART1_TX
PA10 - TIM1_CH3 - - I2C1_SDA - - USART1_RX
PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO COMP1_OUT USART1_CTS
USART1_RTS_
PA12 - TIM1_ETR - - - SPI1_MOSI -
DE
PA13 JTMS-SWDIO IR_OUT - - - - - -
PA14 JTCK-SWCLK LPTIM1_OUT - - I2C1_SMBA - - -
USART3_RTS_
PA15 JTDI TIM2_CH1 TIM2_ETR USART2_RX - SPI1_NSS SPI3_NSS
DE
Table 15. Alternate function AF0 to AF7(1) (continued)

Port USART1/
TIM1/TIM2/
LPTIM1
USART3
PB0 - TIM1_CH2N - - - SPI1_NSS - USART3_CK

USART3_RTS_
PB1 - TIM1_CH3N - - - - -
DE
Port B PB2 RTC_OUT LPTIM1_OUT - - I2C3_SMBA - - -
JTDO- USART1_RTS_
PB3 TIM2_CH2 - - - SPI1_SCK SPI3_SCK
TRACESWO DE
PB4 NJTRST - - - I2C3_SDA SPI1_MISO SPI3_MISO USART1_CTS
PB5 - LPTIM1_IN1 - - I2C1_SMBA SPI1_MOSI SPI3_MOSI USART1_CK
DS11421 Rev 5
PB6 - LPTIM1_ETR - - I2C1_SCL - - USART1_TX

PB7 - LPTIM1_IN2 - - I2C1_SDA - - USART1_RX
PB8 - - - - I2C1_SCL - - -
PB9 - IR_OUT - - I2C1_SDA SPI2_NSS - -
PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK - USART3_TX
Port B
PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX
TIM1_BKIN_
PB12 - TIM1_BKIN - I2C2_SMBA SPI2_NSS - USART3_CK
COMP2

PB13 - TIM1_CH1N - - I2C2_SCL SPI2_SCK - USART3_CTS
USART3_RTS_
PB14 - TIM1_CH2N - - I2C2_SDA SPI2_MISO -
DE
PB15 RTC_REFIN TIM1_CH3N - - - SPI2_MOSI - -
73/220
74/220

Port USART1/
TIM1/TIM2/
LPTIM1
USART3
PC0 - LPTIM1_IN1 - - I2C3_SCL - - -

PC1 - LPTIM1_OUT - - I2C3_SDA - - -
PC2 - LPTIM1_IN2 - - - SPI2_MISO - -
PC3 - LPTIM1_ETR - - - SPI2_MOSI - -
PC4 - - - - - - - USART3_TX
Port C PC5 - - - - - - - USART3_RX
PC6 - - - - - - - -
PC7 - - - - - - - -
DS11421 Rev 5
PC8 - - - - - - - -
PC9 - - - - - - - -

PC10 - - - - - - SPI3_SCK USART3_TX
PC11 - - - - - - SPI3_MISO USART3_RX
PC12 - - - - - - SPI3_MOSI USART3_CK
Port C PC13 - - - - - - - -
PC14 - - - - - - - -
PC15 - - - - - - - -

Port USART1/
TIM1/TIM2/
LPTIM1
USART3
PD0 - - - - - SPI2_NSS - -
PD1 - - - - - SPI2_SCK - -
USART3_RTS_
PD2 - - - - - - -
DE
PD3 - - - - - SPI2_MISO - USART2_CTS
USART2_RTS_
PD4 - - - - - SPI2_MOSI -
DE
PD5 - - - - - - - USART2_TX
DS11421 Rev 5
PD6 - - - - - - - USART2_RX
Port D PD7 - - - - - - - USART2_CK

PD8 - - - - - - - USART3_TX
PD9 - - - - - - - USART3_RX
PD10 - - - - - - - USART3_CK
PD11 - - - - - - - USART3_CTS
USART3_RTS_
PD12 - - - - - - -
DE

PD13 - - - - - - - -
PD14 - - - - - - - -
PD15 - - - - - - - -
Port E PE0 - - - - - - - -
75/220
76/220

Port USART1/
TIM1/TIM2/
LPTIM1
USART3
PE1 - - - - - - - -
PE2 TRACECK - - - - - - -
PE3 TRACED0 - - - - - - -
PE4 TRACED1 - - - - - - -
PE5 TRACED2 - - - - - - -
PE6 TRACED3 - - - - - - -
PE7 - TIM1_ETR - - - - - -
PE8 - TIM1_CH1N - - - - - -
DS11421 Rev 5
Port E
PE9 - TIM1_CH1 - - - - - -
PE10 - TIM1_CH2N - - - - - -

PE11 - TIM1_CH2 - - - - - -
PE12 - TIM1_CH3N - - - SPI1_NSS - -
PE13 - TIM1_CH3 - - - SPI1_SCK - -
TIM1_BKIN2_
PE14 - TIM1_CH4 TIM1_BKIN2 - SPI1_MISO - -
COMP2
TIM1_BKIN_
PE15 - TIM1_BKIN - - SPI1_MOSI - -
COMP1
PH0 - - - - - - - -
Port H PH1 - - - - - - - -
PH3 - - - - - - - -
1. Please refer to Table 16 for AF8 to AF15.
Table 16. Alternate function AF8 to AF15(1)

SDMMC1/
Port
COMP1/ TIM2/TIM15/
LPUART1 CAN1/TSC USB/QUADSPI LCD SAI1 EVENTOUT
COMP2/ TIM16/LPTIM2
SWPMI1
PA0 - - - - COMP1_OUT SAI1_EXTCLK TIM2_ETR EVENTOUT

PA1 - - - LCD_SEG0 - - TIM15_CH1N EVENTOUT
QUADSPI_
PA2 LPUART1_TX - LCD_SEG1 COMP2_OUT - TIM15_CH1 EVENTOUT
BK1_NCS
PA3 LPUART1_RX - QUADSPI_CLK LCD_SEG2 - SAI1_MCLK_A TIM15_CH2 EVENTOUT
PA4 - - - - - SAI1_FS_B LPTIM2_OUT EVENTOUT
PA5 - - - - - - LPTIM2_ETR EVENTOUT
DS11421 Rev 5
QUADSPI_ TIM1_BKIN_
PA6 LPUART1_CTS - LCD_SEG3 - TIM16_CH1 EVENTOUT
BK1_IO3 COMP2
QUADSPI_
PA7 - - LCD_SEG4 COMP2_OUT - - EVENTOUT
BK1_IO2
Port A
PA8 - - - LCD_COM0 SWPMI1_IO SAI1_SCK_A LPTIM2_OUT EVENTOUT
PA9 - - - LCD_COM1 - SAI1_FS_A TIM15_BKIN EVENTOUT
USB_CRS_
PA10 - - LCD_COM2 - SAI1_SD_A - EVENTOUT
SYNC
TIM1_BKIN2_
PA11 - CAN1_RX USB_DM - - - EVENTOUT

COMP1
PA12 - CAN1_TX USB_DP - - - - EVENTOUT
PA13 - - USB_NOE - SWPMI1_TX SAI1_SD_B - EVENTOUT
PA14 - - - - SWPMI1_RX SAI1_FS_B - EVENTOUT
SWPMI1_
PA15 - TSC_G3_IO1 - LCD_SEG17 - - EVENTOUT
SUSPEND
77/220
78/220

SDMMC1/
Port
COMP1/ TIM2/TIM15/
COMP2/ TIM16/LPTIM2
SWPMI1
QUADSPI_
PB0 - - LCD_SEG5 COMP1_OUT SAI1_EXTCLK - EVENTOUT
BK1_IO1
LPUART1_RTS QUADSPI_
PB1 - LCD_SEG6 - - LPTIM2_IN1 EVENTOUT
_DE BK1_IO0
PB2 - - - LCD_VLCD - - - EVENTOUT
PB3 - - - LCD_SEG7 - SAI1_SCK_B - EVENTOUT
PB4 - TSC_G2_IO1 - LCD_SEG8 - SAI1_MCLK_B - EVENTOUT
PB5 - TSC_G2_IO2 - LCD_SEG9 COMP2_OUT SAI1_SD_B TIM16_BKIN EVENTOUT
DS11421 Rev 5
PB6 - TSC_G2_IO3 - - - SAI1_FS_B TIM16_CH1N EVENTOUT

PB7 - TSC_G2_IO4 - LCD_SEG21 - - - EVENTOUT
Port B PB8 - CAN1_RX - LCD_SEG16 SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT

PB9 - CAN1_TX - LCD_COM3 SDMMC1_D5 SAI1_FS_A - EVENTOUT
PB10 LPUART1_RX TSC_SYNC QUADSPI_CLK LCD_SEG10 COMP1_OUT SAI1_SCK_A - EVENTOUT
QUADSPI_
PB11 LPUART1_TX - LCD_SEG11 COMP2_OUT - - EVENTOUT
BK1_NCS
LPUART1_RTS
PB12 TSC_G1_IO1 - LCD_SEG12 SWPMI1_IO SAI1_FS_A TIM15_BKIN EVENTOUT
_DE
PB13 LPUART1_CTS TSC_G1_IO2 - LCD_SEG13 SWPMI1_TX SAI1_SCK_A TIM15_CH1N EVENTOUT
PB14 - TSC_G1_IO3 - LCD_SEG14 SWPMI1_RX SAI1_MCLK_A TIM15_CH1 EVENTOUT
SWPMI1_
PB15 - TSC_G1_IO4 - LCD_SEG15 SAI1_SD_A TIM15_CH2 EVENTOUT
SUSPEND

SDMMC1/
Port
COMP1/ TIM2/TIM15/
COMP2/ TIM16/LPTIM2
SWPMI1
PC0 LPUART1_RX - - LCD_SEG18 - - LPTIM2_IN1 EVENTOUT

Port C PC1 LPUART1_TX - - LCD_SEG19 - - - EVENTOUT
PC2 - - - LCD_SEG20 - - - EVENTOUT
PC3 - - - LCD_VLCD - SAI1_SD_A LPTIM2_ETR EVENTOUT
PC6 - TSC_G4_IO1 - LCD_SEG24 SDMMC1_D6 - - EVENTOUT
DS11421 Rev 5

PC9 - TSC_G4_IO4 USB_NOE LCD_SEG27 SDMMC1_D1 - - EVENTOUT
LCD_COM4/
PC10 - TSC_G3_IO2 - LCD_SEG28/ SDMMC1_D2 - - EVENTOUT
Port C
LCD_SEG40
LCD_COM5/
PC11 - TSC_G3_IO3 - LCD_SEG29/ SDMMC1_D3 - - EVENTOUT
LCD_SEG41

LCD_COM6/
PC12 - TSC_G3_IO4 - LCD_SEG30/ SDMMC1_CK - - EVENTOUT
LCD_SEG42
PC13 - - - - - - - EVENTOUT
PC14 - - - - - - - EVENTOUT
PC15 - - - - - - - EVENTOUT
79/220
80/220

SDMMC1/
Port
COMP1/ TIM2/TIM15/
COMP2/ TIM16/LPTIM2
SWPMI1
PD0 - CAN1_RX - - - - - EVENTOUT

PD1 - CAN1_TX - - - - - EVENTOUT
Port D
LCD_COM7/
SDMMC1_
PD2 - TSC_SYNC - LCD_SEG31/ - - EVENTOUT
CMD
LCD_SEG43
QUADSPI_BK2
PD3 - - - - - - EVENTOUT
_NCS
QUADSPI_BK2
DS11421 Rev 5
_IO0
QUADSPI_BK2
_IO1
QUADSPI_BK2

PD6 - - - - SAI1_SD_A - EVENTOUT
_IO2
QUADSPI_BK2
_IO3
Port D
PD8 - - - LCD_SEG28 - - - EVENTOUT
PD10 - TSC_G6_IO1 - LCD_SEG30 - - - EVENTOUT
PD11 - TSC_G6_IO2 - LCD_SEG31 - - LPTIM2_ETR EVENTOUT
PD12 - TSC_G6_IO3 - LCD_SEG32 - - LPTIM2_IN1 EVENTOUT
PD13 - TSC_G6_IO4 - LCD_SEG33 - - LPTIM2_OUT EVENTOUT

SDMMC1/
Port
COMP1/ TIM2/TIM15/
COMP2/ TIM16/LPTIM2
SWPMI1
PE0 - - - LCD_SEG36 - - TIM16_CH1 EVENTOUT

PE1 - - - LCD_SEG37 - - - EVENTOUT
Port E PE2 - TSC_G7_IO1 - LCD_SEG38 - SAI1_MCLK_A - EVENTOUT
PE3 - TSC_G7_IO2 - LCD_SEG39 - SAI1_SD_B - EVENTOUT
PE4 - TSC_G7_IO3 - - - SAI1_FS_A - EVENTOUT
PE5 - TSC_G7_IO4 - - - SAI1_SCK_A - EVENTOUT
PE6 - - - - - SAI1_SD_A - EVENTOUT
DS11421 Rev 5
PE7 - - - - - SAI1_SD_B - EVENTOUT

PE8 - - - - - SAI1_SCK_B - EVENTOUT
PE9 - - - - - SAI1_FS_B - EVENTOUT
PE10 - TSC_G5_IO1 QUADSPI_CLK - - SAI1_MCLK_B - EVENTOUT
QUADSPI_BK1
PE11 - TSC_G5_IO2 - - - - EVENTOUT
Port E _NCS
QUADSPI_BK1
_IO0

QUADSPI_BK1
_IO1
QUADSPI_BK1
PE14 - - - - - - EVENTOUT
_IO2
QUADSPI_BK1
PE15 - - - - - - EVENTOUT
_IO3
81/220
82/220

SDMMC1/
Port
COMP1/ TIM2/TIM15/
COMP2/ TIM16/LPTIM2
SWPMI1
PH0 - - - - - - - EVENTOUT
Port H PH1 - - - - - - - EVENTOUT
PH3 - - - - - - - EVENTOUT
1. Please refer to Table 15 for AF0 to AF7.
DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC Memory mapping
5 Memory mapping
Figure 14. STM32L443xx memory map
0xFFFF FFFF 0xBFFF FFFF

Cortex™-M4 Reserved
0xA000 1400
with FPU
7 QUADSPI registers
Internal
Peripherals 0xA000 1000
0xE000 0000
0x5FFF FFFF
Reserved
6
0x5006 0C00
AHB2
0x4800 0000
0xC000 0000 Reserved
0x4002 4400
QUADSPI AHB1
registers
5 0x4002 0000
Reserved
0xA000 1000
0x4001 5800
0xA000 0000 APB2
QUADSPI Flash 0x4001 0000
bank Reserved
0x4000 9800
4 0x9000 0000
APB1
0x4000 0000
0x8000 0000 0x1FFF FFFF
3
Reserved
0x6000 0000
0x1FFF 7810
Options Bytes
2
0x1FFF 7800
Reserved
0x1FFF 7400
Peripherals OTP area
0x4000 0000
0x1FFF 7000
System memory
1 0x1FFF 0000
SRAM2 Reserved
0x2000 C000
0x1000 4000
SRAM1
0x2000 0000 SRAM2
0x1000 0000
Reserved
0 0x0804 0000
CODE
Flash memory
0x0800 0000
Reserved
0x0000 0000
0x0004 0000 Flash, system memory
or SRAM, depending on
0x0000 0000 BOOT configuration
Reserved
MSv36892V2
DS11421 Rev 5 83/220

86
Memory mapping STM32L443CC STM32L443RC STM32L443VC
Table 17. STM32L443xx memory map and peripheral register boundary addresses(1)
Bus Boundary address Size(bytes) Peripheral
0x5006 0800 - 0x5006 0BFF 1 KB RNG

0x5006 0400 - 0x5006 07FF 158 KB Reserved
0x5006 0000 - 0x5006 03FF 1 KB AES
0x5004 0400 - 0x5005 FFFF 158 KB Reserved
0x5004 0000 - 0x5004 03FF 1 KB ADC
0x4800 2000 - 0x4FFF FFFF ~127 MB Reserved
AHB2
0x4800 1C00 - 0x4800 1FFF 1 KB GPIOH
0x4800 1400 - 0x4800 1BFF 2 KB Reserved
0x4800 1000 - 0x4800 13FF 1 KB GPIOE
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
- 0x4002 4400 - 0x47FF FFFF ~127 MB Reserved
0x4002 4000 - 0x4002 43FF 1 KB TSC
0x4002 3400 - 0x4002 3FFF 1 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
0x4002 2000 - 0x4002 23FF 1 KB FLASH registers
AHB1
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0400 - 0x4002 07FF 1 KB DMA2
0x4002 0000 - 0x4002 03FF 1 KB DMA1
84/220 DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC Memory mapping
(continued)

0x4001 5400 - 0x4000 57FF 1 KB SAI1
0x4001 4800 - 0x4000 53FF 3 KB Reserved
0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 4000 - 0x4001 43FF 1 KB TIM15
APB2
0x4001 3C00 - 0x4001 3FFF 1 KB Reserved
0x4001 3800 - 0x4001 3BFF 1 KB USART1
0x4001 3400 - 0x4001 37FF 1 KB Reserved
0x4001 3000 - 0x4001 33FF 1 KB SPI1
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
0x4001 2800 - 0x4001 2BFF 1 KB SDMMC1
0x4001 2000 - 0x4001 27FF 2 KB Reserved
0x4001 1C00 - 0x4001 1FFF 1 KB FIREWALL
0x4001 0800- 0x4001 1BFF 5 KB Reserved
APB2
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0200 - 0x4001 03FF COMP
0x4001 0030 - 0x4001 01FF 1 KB VREFBUF
0x4001 0000 - 0x4001 002F SYSCFG
DS11421 Rev 5 85/220

86
Memory mapping STM32L443CC STM32L443RC STM32L443VC
(continued)

0x4000 9400 - 0x4000 97FF 1 KB LPTIM2
0x4000 8C00 - 0x4000 93FF 2 KB Reserved
0x4000 8800 - 0x4000 8BFF 1 KB SWPMI1
0x4000 8400 - 0x4000 87FF 1 KB Reserved
0x4000 8000 - 0x4000 83FF 1 KB LPUART1
0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1
0x4000 7800 - 0x4000 7BFF 1 KB OPAMP
0x4000 7400 - 0x4000 77FF 1 KB DAC1
0x4000 7000 - 0x4000 73FF 1 KB PWR
0x4000 6C00 - 0x4000 6FFF 1 KB USB SRAM
0x4000 6800 - 0x4000 6BFF 1 KB USB FS
0x4000 6400 - 0x4000 67FF 1 KB CAN1
APB1 0x4000 6000 - 0x4000 63FF 1 KB CRS
0x4000 5C00- 0x4000 5FFF 1 KB I2C3
0x4000 5800 - 0x4000 5BFF 1 KB I2C2
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 4C00 - 0x4000 53FF 2 KB Reserved
0x4000 4800 - 0x4000 4BFF 1 KB USART3
0x4000 4400 - 0x4000 47FF 1 KB USART2
0x4000 4000 - 0x4000 43FF 1 KB Reserved
0x4000 3C00 - 0x4000 3FFF 1 KB SPI3
0x4000 3800 - 0x4000 3BFF 1 KB SPI2
0x4000 3400 - 0x4000 37FF 1 KB Reserved
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
0x4000 2800 - 0x4000 2BFF 1 KB RTC
0x4000 2400 - 0x4000 27FF 1 KB LCD
0x4000 1800 - 0x4000 23FF 3 KB Reserved
0x4000 1400 - 0x4000 17FF 1 KB TIM7
APB1
0x4000 1000 - 0x4000 13FF 1 KB TIM6
0x4000 0400- 0x4000 0FFF 3 KB Reserved
0x4000 0000 - 0x4000 03FF 1 KB TIM2
1. The gray color is used for reserved boundary addresses.
86/220 DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC Electrical characteristics
6 Electrical characteristics
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 15.
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 16.
Figure 15. Pin loading conditions Figure 16. Pin input voltage
MCU pin MCU pin

C = 50 pF VIN
MS19210V1 MS19211V1
DS11421 Rev 5 87/220

185
Electrical characteristics STM32L443CC STM32L443RC STM32L443VC
6.1.6 Power supply scheme
Figure 17. Power supply scheme
VBAT
Backup circuitry
1.55 – 3.6 V (LSE, RTC,
Backup registers)
Power switch
VDD VCORE
n x VDD
Regulator
VDDIO1
OUT
Level shifter
Kernel logic
n x 100 nF IO (CPU, Digital
GPIOs logic
+1 x 4.7 μF IN & Memories)
n x VSS
VDDA
VDDA
VREF
ADCs/
10 nF VREF+ DACs/
+1 μF OPAMPs/
100 nF +1 μF VREF- COMPs/
VREFBUF
VSSA
MSv41628V1
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
88/220 DS11421 Rev 5

6.1.7 Current consumption measurement
Figure 18. Current consumption measurement scheme

IDD_USB
VDDUSB
IDD_VBAT
VBAT
IDD
VDD
IDDA
VDDA
MS35002V2
The IDD_ALL parameters given in Table 25 to Table 37 represent the total MCU consumption
including the current supplying VDD, VDDA, VDDUSB and VBAT.
6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 qualification standard, extended mission profiles are
available on demand.
Table 18. Voltage characteristics(1)

Symbol Ratings Min Max Unit
External main supply voltage (including

VDDX - VSS -0.3 4.0 V
VDD, VDDA, VDDUSB, VLCD, VBAT)
min (VDD, VDDA, VDDUSB, VLCD)
Input voltage on FT_xxx pins VSS-0.3
+ 4.0(3)(4)
VIN(2) V
Input voltage on TT_xx pins VSS-0.3 4.0
Input voltage on any other pins VSS-0.3 4.0
DS11421 Rev 5 89/220

185
Table 18. Voltage characteristics(1) (continued)

Symbol Ratings Min Max Unit
Variations between different VDDX power

|∆VDDx| - 50 mV
pins of the same domain
Variations between all the different ground
|VSSx-VSS| - 50 mV
pins(5)
1. All main power (VDD, VDDA, VDDUSB, VLCD, VBAT) and ground (VSS, VSSA) pins must always be connected to the external
power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum allowed injected
current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
5. Include VREF- pin.
Table 19. Current characteristics

Symbol Ratings Max Unit
∑IVDD Total current into sum of all VDD power lines (source)(1) 140
∑IVSS Total current out of sum of all VSS ground lines (sink) (1)
140
IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk by any I/O and control pin except FT_f 20
IIO(PIN) Output current sunk by any FT_f pin 20
Output current sourced by any I/O and control pin 20 mA
Total output current sunk by sum of all I/Os and control pins(2) 100
∑IIO(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 100
Injected current on FT_xxx, TT_xx, RST and B pins, except PA4,
-5/+0(4)
IINJ(PIN)(3) PA5
Injected current on PA4, PA5 -5/0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) 25
1. All main power (VDD, VDDA, VDDUSB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power
supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 18: Voltage
characteristics for the maximum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
90/220 DS11421 Rev 5

Table 20. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C
DS11421 Rev 5 91/220

185
6.3 Operating conditions
6.3.1 General operating conditions
Table 21. General operating conditions

Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 80

fPCLK1 Internal APB1 clock frequency - 0 80 MHz
fPCLK2 Internal APB2 clock frequency - 0 80
1.71
VDD Standard operating voltage - (1) 3.6 V
ADC or COMP used 1.62

DAC or OPAMP used 1.8
VDDA Analog supply voltage VREFBUF used 2.4 3.6 V
ADC, DAC, OPAMP, COMP,

0
VREFBUF not used
VBAT Backup operating voltage - 1.55 3.6 V
USB used 3.0 3.6
VDDUSB USB supply voltage V
USB not used 0 3.6
TT_xx I/O -0.3 VDDIOx+0.3
VIN I/O input voltage Min(Min(VDD, VDDA, V

All I/O except TT_xx -0.3 VDDUSB, VLCD)+3.6 V,
5.5 V)(2)(3)
LQFP100 - 476
LQFP64 - 444
LQFP48 - 350
Power dissipation at
TA = 85 °C for suffix 6 UFBGA100 - 350
PD mW
or UFBGA64 - 307
TA = 105 °C for suffix 7(4)
UFQFPN48 - 606
WLCSP64 - 434
WLCSP49 - 416
LQFP100 - 119
LQFP64 - 111
LQFP48 - 88
Power dissipation at UFBGA100 - 88

PD mW
TA = 125 °C for suffix 3(4) UFBGA64 - 77
UFQFPN48 - 151
WLCSP64 - 109
WLCSP49 - 104
92/220 DS11421 Rev 5

Table 21. General operating conditions (continued)

Ambient temperature for the Maximum power dissipation –40 85

suffix 6 version Low-power dissipation(5) –40 105

TA °C
suffix 7 version Low-power dissipation (5)
–40 125

suffix 3 version Low-power dissipation(5) –40 130
Suffix 6 version –40 105
TJ Junction temperature range Suffix 7 version –40 125 °C
Suffix 3 version –40 130
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between Min(VDD, VDDA, VDDUSB, VLCD)+3.6 V and 5.5V.
3. For operation with voltage higher than Min (VDD, VDDA, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down resistors
must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.10: Thermal
characteristics).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.10:
Thermal characteristics).
6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
Table 22. Operating conditions at power-up / power-down

VDD rise time rate 0 ∞

tVDD -
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
tVDDA - µs/V
VDDA fall time rate 10 ∞
VDDUSB rise time rate 0 ∞
tVDDUSB -
VDDUSB fall time rate 10 ∞
The requirements for power-up/down sequence specified in Section 3.9.1: Power supply
schemes must be respected.
6.3.3 Embedded reset and power control block characteristics

temperature conditions summarized in Table 21: General operating conditions.
DS11421 Rev 5 93/220

185
Table 23. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit
Reset temporization after

tRSTTEMPO(2) VDD rising - 250 400 μs
BOR0 is detected
Rising edge 1.62 1.66 1.7
VBOR0(2) Brown-out reset threshold 0 V
Falling edge 1.6 1.64 1.69
Rising edge 2.06 2.1 2.14
VBOR1 Brown-out reset threshold 1 V
Falling edge 1.96 2 2.04
Rising edge 2.26 2.31 2.35
Rising edge 2.56 2.61 2.66
Rising edge 2.85 2.90 2.95
Programmable voltage Rising edge 2.1 2.15 2.19

VPVD0 V
detector threshold 0 Falling edge 2 2.05 2.1
Rising edge 2.26 2.31 2.36
VPVD1 PVD threshold 1 V
Rising edge 2.41 2.46 2.51
Rising edge 2.56 2.61 2.66
Rising edge 2.69 2.74 2.79
Rising edge 2.85 2.91 2.96
Rising edge 2.92 2.98 3.04
Hysteresis in
continuous - 20 -
Vhyst_BORH0 Hysteresis voltage of BORH0 mode mV
Hysteresis in
- 30 -
other mode
Hysteresis voltage of BORH
Vhyst_BOR_PVD - - 100 - mV
(except BORH0) and PVD
IDD BOR(3) (except BOR0) and
- - 1.1 1.6 µA
(BOR_PVD)(2) PVD consumption from VDD
VDDUSB peripheral voltage
VPVM1 - 1.18 1.22 1.26 V
monitoring
94/220 DS11421 Rev 5

Table 23. Embedded reset and power control block characteristics (continued)
VDDA peripheral voltage Rising edge 1.61 1.65 1.69

VPVM3 V
monitoring Falling edge 1.6 1.64 1.68
VDDA peripheral voltage Rising edge 1.78 1.82 1.86

VPVM4 V
monitoring Falling edge 1.77 1.81 1.85
Vhyst_PVM3 PVM3 hysteresis - - 10 - mV
Vhyst_PVM4 PVM4 hysteresis - - 10 - mV
IDD (PVM1)
(2) PVM1 consumption from VDD - - 0.2 - µA
IDD
PVM3 and PVM4
(PVM3/PVM4) - - 2 - µA
(2) consumption from VDD
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power
sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply
current characteristics tables.
DS11421 Rev 5 95/220

185
6.3.4 Embedded voltage reference

temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 24. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +130 °C 1.182 1.212 1.232 V
ADC sampling time when
tS_vrefint (1) reading the internal reference - 4(2) - - µs
voltage
Start time of reference voltage
tstart_vrefint - - 8 12(2) µs
buffer when ADC is enable
VREFINT buffer consumption
from VDD when converted by - - 12.5 20(2) µA
IDD(VREFINTBUF)
ADC
Internal reference voltage
∆VREFINT spread over the temperature VDD = 3 V - 5 7.5(2) mV
range
TCoeff Temperature coefficient –40°C < TA < +130°C - 30 50(2) ppm/°C
ACoeff Long term stability 1000 hours, T = 25°C - 300 1000(2) ppm
VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage 24 25 26
%
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
96/220 DS11421 Rev 5

Figure 19. VREFINT versus temperature
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv40169V1
DS11421 Rev 5 97/220

185
6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 18: Current consumption
measurement scheme.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0394 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 25 to Table 38 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
98/220 DS11421 Rev 5

running from Flash, ART enable (Cache ON Prefetch OFF)
Conditions TYP MAX(1)
Symbol Parameter Unit
- Voltage fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
scaling
26 MHz 2.37 2.38 2.44 2.52 2.66 2.7 2.7 2.8 2.9 3.2
16 MHz 1.5 1.52 1.57 1.64 1.79 1.7 1.7 1.8 2.0 2.3
8 MHz 0.81 0.82 0.87 0.94 1.08 0.9 0.9 1.0 1.2 1.5
Range 2 4 MHz 0.46 0.47 0.52 0.59 0.73 0.5 0.6 0.6 0.8 1.1
2 MHz 0.29 0.3 0.34 0.41 0.55 0.3 0.4 0.4 0.6 0.9
fHCLK = fHSE up to 1 MHz 0.2 0.21 0.25 0.32 0.46 0.2 0.3 0.3 0.5 0.8
48MHz included,
Supply 100 kHz 0.12 0.13 0.17 0.24 0.38 0.1 0.2 0.2 0.4 0.7
IDD_ALL bypass mode
current in mA
DS11421 Rev 5
(Run) PLL ON above 80 MHz 8.53 8.56 8.64 8.74 8.92 9.5 9.6 9.7 9.9 10.3
Run mode
48 MHz all
peripherals disable 72 MHz 7.7 7.73 7.8 7.9 8.08 8.6 8.6 8.7 8.9 9.3
64 MHz 6.86 6.9 6.97 7.06 7.23 7.7 7.7 7.8 8.0 8.3
Range 1 48 MHz 5.13 5.16 5.23 5.32 5.49 5.8 5.8 6.0 6.1 6.5
32 MHz 3.46 3.48 3.55 3.64 3.8 3.9 4.0 4.1 4.2 4.6
24 MHz 2.63 2.64 2.71 2.79 2.96 3.0 3.0 3.1 3.3 3.6
16 MHz 1.8 1.81 1.87 1.96 2.12 2.0 2.1 2.2 2.3 2.7
2 MHz 211 230 280 355 506 273.8 301.1 360.4 502.7 815.9
Supply
1 MHz 117 134 179 254 404 154.7 184.6 249.6 398.4 712.4
Electrical characteristics
IDD_ALL current in fHCLK = fMSI
µA
(LPRun) Low-power all peripherals disable 400 kHz 58.5 70.4 116 189 338 80.2 111.5 179.7 330.8 643.4
run mode
100 kHz 30 41.1 85.2 159 308 46.5 76.6 147.1 299.1 611.2
1. Guaranteed by characterization results, unless otherwise specified.
99/220
100/220
running from Flash, ART disable
Voltage
- fHCLK 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
scaling
26 MHz 2.66 2.68 2.73 2.81 2.96 3.0 3.1 3.2 3.3 3.6
16 MHz 1.88 1.9 1.94 2.02 2.17 2.1 2.2 2.3 2.4 2.7
8 MHz 1.05 1.06 1.11 1.18 1.33 1.2 1.2 1.3 1.4 1.7
Range 2 4 MHz 0.6 0.62 0.66 0.73 0.87 0.7 0.7 0.8 0.9 1.2
2 MHz 0.36 0.37 0.34 0.48 0.62 0.4 0.4 0.5 0.6 0.9
fHCLK = fHSE up to
48MHz included, 1 MHz 0.23 0.25 0.25 0.36 0.5 0.3 0.3 0.4 0.5 0.8
Supply
IDD_ALL bypass mode 100 kHz 0.12 0.14 0.17 0.25 0.39 0.1 0.2 0.2 0.4 0.7
current in mA
Run mode
48 MHz all
72 MHz 7.74 7.79 7.86 7.96 8.14 8.7 8.7 8.8 9.0 9.4
peripherals disable
DS11421 Rev 5
64 MHz 7.63 7.68 7.75 7.85 8.04 8.6 8.6 8.7 8.9 9.3
Range 1 48 MHz 6.36 6.4 6.48 6.58 6.76 7.2 7.3 7.4 7.6 7.9
32 MHz 4.56 4.6 4.66 4.76 4.93 5.2 5.2 5.3 5.5 5.8

24 MHz 3.45 3.48 3.54 3.64 3.8 3.9 4.0 4.1 4.2 4.6
16 MHz 2.48 2.51 2.56 2.65 2.82 2.8 2.9 3.0 3.1 3.5
2 MHz 310 317 364 440 593 375.3 400.9 456.7 595.3 909.6
Supply
IDD_ALL current in fHCLK = fMSI 1 MHz 157 173 226 296 448 204.8 234.2 298.2 445.8 758.9
µA
(LPRun) Low-power all peripherals disable 400 kHz 72.6 89 130 206 356 99.7 131.2 199.7 349.3 663.7
run
100 kHz 32.3 46 89.7 164 314 52.4 82.1 153.3 301.2 616.9

running from SRAM1
Voltage 105 125 105 125
- fHCLK 25 °C 55 °C 85 °C 25 °C 55 °C 85 °C
scaling °C °C °C °C
26 MHz 2.42 2.43 2.49 2.56 2.71 2.7 2.7 2.8 3.0 3.3
16 MHz 1.54 1.55 1.6 1.67 1.82 1.7 1.7 1.8 2.0 2.3
8 MHz 0.82 0.84 0.88 0.95 1.1 0.9 1.0 1.0 1.2 1.5
Range 2 4 MHz 0.47 0.48 0.52 0.59 0.73 0.5 0.6 0.6 0.8 1.1
2 MHz 0.29 0.3 0.34 0.41 0.55 0.3 0.4 0.4 0.6 0.9
fHCLK = fHSE up to
48MHz included, 1 MHz 0.2 0.21 0.25 0.32 0.46 0.2 0.3 0.3 0.5 0.8
Supply
IDD_ALL bypass mode 100 kHz 0.12 0.13 0.17 0.24 0.38 0.1 0.2 0.2 0.4 0.7
current in mA
Run mode
48 MHz all
72 MHz 7.79 7.83 7.9 7.99 8.17 8.6 8.6 8.8 8.9 9.3
peripherals disable
DS11421 Rev 5
64 MHz 6.95 6.99 7.05 7.15 7.32 7.7 7.7 7.9 8.0 8.4
Range 1 48 MHz 5.19 5.22 5.29 5.38 5.55 5.8 5.8 5.9 6.1 6.5
32 MHz 3.51 3.53 3.6 3.68 3.85 3.9 4.0 4.1 4.2 4.6
24 MHz 2.66 2.68 2.74 2.83 2.99 3.0 3.0 3.1 3.3 3.6
16 MHz 1.82 1.84 1.89 1.98 2.14 2.0 2.1 2.2 2.3 2.7
2 MHz 205 228 275 352 501 276.5 302.3 358.4 502.5 816.4
Supply
fHCLK = fMSI 1 MHz 111 126 175 248 397 151.3 180.9 245.3 390.7 703.4
IDD_ALL current in
all peripherals disable µA
(LPRun) low-power 400 kHz 49.2 62.7 108 181 330 73.3 104.0 170.8 321.0 632.4
FLASH in power-down
run mode
100 kHz 21.5 33.3 76.6 151 299 36.4 67.7 137.2 287.8 600.8
101/220
running from Flash, ART enable (Cache ON Prefetch OFF)
Conditions TYP TYP
Symbol Parameter Unit Unit
Voltage
- Code 25 °C 25 °C
scaling
Reduced code(1) 2.37 91
fHCLK = 26 MHz
Coremark 2.69 103
Range 2
Dhrystone 2.1 2.74 mA 105 µA/MHz
fHCLK = fHSE up
to 48 MHz Fibonacci 2.58 99
Supply included, bypass While(1) 2.30 88
IDD_ALL
current in mode PLL ON
(Run) Reduced code (1)
8.53 107
Run mode above 48 MHz fHCLK = 80 MHz
all peripherals Coremark 9.68 121
Range 1
disable
Dhrystone 2.1 9.76 mA 122 µA/MHz
Fibonacci 9.27 116
While(1) 8.20 103
(1)
Reduced code 211 106
Supply Coremark 251 126
IDD_ALL current in fHCLK = fMSI = 2 MHz
Dhrystone 2.1 269 µA 135 µA/MHz
(LPRun) Low-power all peripherals disable
run Fibonacci 230 115
While(1) 286 143
1. Reduced code used for characterization results provided in Table 25, Table 26, Table 27.
102/220 DS11421 Rev 5

running from Flash, ART disable
Conditions TYP TYP
Voltage
- Code 25 °C 25 °C
scaling
fHCLK = 80 MHz fHCLK = 26 MHz

Coremark 2.44 94
Range 2
fHCLK = fHSE up to Dhrystone 2.1 2.46 mA 95 µA/MHz
48 MHz included, Fibonacci 2.27 87
Supply bypass mode
IDD_ALL While(1) 2.20 84.6
current in PLL ON above
(Run) Reduced code(1) 8.56 107
Run mode 48 MHz
all peripherals Range 1 Coremark 8.00 100
disable Dhrystone 2.1 7.98 mA 100 µA/MHz
Fibonacci 7.41 93
While(1) 7.83 98
Reduced code(1) 310 155
While(1) 384 192
running from SRAM1
Conditions TYP TYP
Voltage
- Code 25 °C 25 °C
scaling

fHCLK = 80 MHz fHCLK = 26 MHz
Coremark 2.18 84
Range 2
fHCLK = fHSE up to Dhrystone 2.1 2.40 mA 92 µA/MHz

48 MHz included, Fibonacci 2.40 92
Supply bypass mode
IDD_ALL While(1) 2.29 88
current in PLL ON above
(Run) Reduced code(1) 8.63 108
Run mode 48 MHz all
peripherals Coremark 7.76 97
Range 1
disable Dhrystone 2.1 8.55 mA 107 µA/MHz

Fibonacci 8.56 107
While(1) 8.12 102
Reduced code(1) 205 103
While(1) 211 106
DS11421 Rev 5 103/220

185
104/220
Table 31. Current consumption in Sleep and Low-power sleep modes, Flash ON
Voltage
scaling
26 MHz 0.68 0.69 0.74 0.81 0.95 0.8 0.8 0.9 1.0 1.3
16 MHz 0.46 0.48 0.52 0.59 0.73 0.5 0.6 0.6 0.8 1.1
8 MHz 0.29 0.30 0.34 0.41 0.55 0.3 0.4 0.4 0.6 0.9
Range 2 4 MHz 0.20 0.21 0.25 0.32 0.46 0.2 0.3 0.3 0.5 0.8
fHCLK = fHSE up 2 MHz 0.16 0.17 0.21 0.28 0.42 0.2 0.2 0.3 0.4 0.7
to 48 MHz
Supply included, bypass 1 MHz 0.13 0.15 0.19 0.26 0.40 0.1 0.2 0.3 0.4 0.7
IDD_ALL current in mode 100 kHz 0.11 0.13 0.17 0.24 0.38 0.1 0.2 0.2 0.4 0.7
mA
(Sleep) sleep pll ON above 80 MHz 2.23 2.25 2.30 2.38 2.54 2.5 2.5 2.6 2.8 3.1
mode, 48 MHz all
72 MHz 2.02 2.04 2.10 2.18 2.34 2.2 2.3 2.4 2.5 2.9
peripherals
DS11421 Rev 5
disable 64 MHz 1.82 1.84 1.89 1.98 2.14 2.0 2.1 2.1 2.3 2.6
Range 1 48 MHz 1.34 1.36 1.42 1.50 1.66 1.5 1.6 1.7 1.8 2.2
32 MHz 0.93 0.95 1.01 1.09 1.25 1.1 1.1 1.2 1.4 1.7
24 MHz 0.73 0.75 0.80 0.88 1.04 0.8 0.9 1.0 1.1 1.4

16 MHz 0.53 0.55 0.60 0.68 0.84 0.6 0.6 0.7 0.9 1.2
Supply 2 MHz 71.8 80.7 125 200 350 91.1 122.7 191.3 341.5 653.5
current in 1 MHz 45.0 57.3 101 176 325 63.2 95.4 165.4 316.5 628.7
IDD_ALL f =f
low-power HCLK MSI µA
(LPSleep) all peripherals disable 400 kHz 27.0 40.7 84.6 158 308 43.9 75.8 147.2 297.6 609.2
sleep
mode 100 kHz 22.8 30.9 63.3 113.2 207.7 35.2 67.9 140.9 290.8 602.4
Table 32. Current consumption in Low-power sleep modes, Flash in power-down

Voltage
scaling
2 MHz 58.7 70.7 103.2 153.7 248.5 80 113 180 330 641
Supply current
IDD_ALL fHCLK = fMSI 1 MHz 39.4 47.2 79.3 129.6 224.8 53 86 154 304 616
in low-power µA
(LPSleep) all peripherals disable 400 kHz 20.8 30.8 62.1 112.5 207.8 35 67 137 286 597
sleep mode
100 kHz 14.3 23.1 55.1 105.7 201.5 27 58 130 279 590
Table 33. Current consumption in Stop 2 mode

- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
DS11421 Rev 5
1.8 V 1 2.54 8.74 19.8 43.4 2.0 5.6 21.1 50.8 116.0
2.4 V 1.02 2.59 8.89 20.2 44.3 2.1 5.8 21.6 52.3 119.6
LCD disabled
3V 1.06 2.67 9.11 20.7 45.5 2.1 5.9 22.2 53.7 123.2
Supply current in 3.6 V 1.23 2.88 9.56 21.6 47.3 2.3 6.1 23.0 55.8 127.9
IDD_ALL
Stop 2 mode, µA
(Stop 2) 1.8 V 1.31 2.87 9.03 20 43.1 2.6 6.3 21.9 51.8 117.5
RTC disabled
LCD enabled(2) 2.4 V 1.36 2.96 9.22 20.4 44.1 2.8 6.5 22.5 53.3 121.1
clocked by LSI 3V 1.45 3.08 9.24 20.4 45.5 2.9 6.8 23.2 54.9 124.8
3.6 V 1.69 3.4 10.1 22.1 47.9 3.1 7.1 24.2 57.1 129.6
105/220
Table 33. Current consumption in Stop 2 mode (continued)
106/220
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 1.3 2.82 9.02 20.1 43.6 2.5 6.2 21.6 51.3 116.3
RTC clocked by LSI, 2.4 V 1.39 2.95 9.24 20.5 44.6 2.8 6.4 22.3 52.8 120.0
LCD disabled 3V 1.5 3.11 9.55 21.1 45.8 3.0 6.8 23.0 54.5 123.8
3.6 V 1.76 3.42 10.1 22.1 47.8 3.3 7.2 24.1 56.7 128.7
1.8 V 1.41 2.96 9.13 20.1 43.3 2.8 6.4 22.1 52.0 117.6
2.4 V 1.49 3.08 9.35 20.5 44.2 3.0 6.7 22.8 53.5 121.2
RTC clocked by LSI,
LCD enabled(2) 3V 1.61 3.25 9.41 20.5 45.6 3.2 7.1 23.5 55.2 125.1
IDD_ALL Supply current in 130.0
3.6 V 1.91 3.63 10.3 22.3 48.1 3.5 7.5 24.6 57.5 (3)
(Stop 2 with Stop 2 mode, µA
RTC) RTC enabled 1.8 V 1.36 2.9 9.1 20.1 43.7 - - - - -
RTC clocked by LSE 2.4 V 1.48 3.09 9.44 20.8 45 - - - - -
DS11421 Rev 5
bypassed at
32768Hz,LCD disabled 3 V 1.83 3.67 10.4 22.3 47.3 - - - - -
3.6 V 3.58 6.17 13.9 26.6 53 - - - - -
1.8 V 1.28 2.81 9.13 20.8 - - - - - -
RTC clocked by LSE

quartz(4) 2.4 V 1.39 2.93 9.34 21.3 - - - - - -
in low drive mode, 3V 1.59 3.1 9.64 21.8 - - - - - -
LCD disabled
3.6 V 1.86 3.45 10.2 22.8 - - - - - -
Wakeup clock is
MSI = 48 MHz,
3V 1.85 - - - - - - - - -
voltage Range 1.
See (5).
Supply current Wakeup clock is
IDD_ALL MSI = 4 MHz,
during wakeup
(wakeup from voltage Range 2. 3V 1.52 - - - - - - - - - mA
from Stop 2
Stop2)
mode See (5).
Wakeup clock is
HSI16 = 16 MHz,
3V 1.54 - - - - - - - - -
voltage Range 1.
See (5).
2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD.
3. Guaranteed by test in production.
4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors.
5. Wakeup with code execution from Flash. Average value given for a typical wakeup time as specified in Table 40: Low-power mode wakeup timings.
DS11421 Rev 5
107/220
Table 34. Current consumption in Stop 1 mode
108/220
- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 4.34 12.4 43.6 96.4 204 9.3 27.4 98.9 198.7 397.5
LCD 2.4 V 4.35 12.5 43.8 97 205 9.4 27.6 99.5 199.0 398.0
-
disabled 3V 4.41 12.6 44.1 97.7 207 9.5 27.8 100.3 200.4 400.8
Supply current
IDD_ALL in Stop 1 3.6 V 4.56 12.9 44.8 98.9 210 9.7 28.3 101.7 202.1 404.2
µA
(Stop 1) mode, 1.8 V 4.68 12.7 43.9 96.7 204 9.1 27.2 99.1 198.9 397.7
LCD
RTC disabled
enabled(2) 2.4 V 4.7 12.8 44.2 97.3 205 9.7 27.7 99.9 199.5 399.0
-
clocked by 3V 4.88 12.6 44.5 98 206 10.2 28.4 101.0 200.9 401.8
LSI
3.6 V 5.1 13.4 45.3 99.6 270 10.6 29.2 102.7 203.2 406.4
1.8 V 4.63 12.7 43.9 96.8 205 9.9 28.0 99.5 198.9 397.8
LCD 2.4 V 4.78 12.8 44.2 97.4 206 10.1 28.3 100.3 199.5 399.0
disabled 3V 4.93 13 44.6 98.1 207 10.4 28.7 101.2 200.9 401.9
DS11421 Rev 5
RTC clocked by 3.6 V 5.05 13.4 45.3 99.5 210 10.8 29.4 102.8 202.5 405.0
LSI 1.8 V 4.82 12.9 44 96.8 204 10.2 28.4 99.9 199.6 399.1
LCD 2.4 V 4.93 13 44.3 97.4 205 10.4 28.7 100.7 200.3 400.6
enabled(2)

Supply current 3V 5.05 12.7 44.7 98.1 206 10.7 29.2 101.7 201.8 403.6
IDD_ALL 3.6 V 5.31 13.7 45.6 99.9 210 11.1 29.8 103.4 202.9 405.8
in stop 1
(Stop 1 with µA
mode, 1.8 V 4.7 12.8 44 96.9 205 - - - - -
RTC)
RTC enabled RTC clocked by
LCD 2.4 V 4.95 13 44.4 97.6 206 - - - - -
LSE bypassed
disabled 3V 5.33 13.6 45.4 99.1 209 - - - - -
at 32768 Hz
3.6 V 6.91 16.1 48.8 103 216 - - - - -
1.8 V 4.76 12.3 43.7 99.1 - - - - - -
RTC clocked by 2.4 V 4.95 12.4 43.8 99.3 - - - - - -
LCD
LSE quartz(3) in
disabled 3V 5.1 12.6 44.1 99.6 - - - - - -
low drive mode
3.6 V 5.65 13 44.8 101 - - - - - -
Table 34. Current consumption in Stop 1 mode (continued)

- - VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Wakeup clock MSI = 48 MHz,
voltage Range 1. 3V 1.14 - - - - - - - - -
See (4).
Supply current Wakeup clock MSI = 4 MHz,
IDD_ALL
during voltage Range 2. 3V 1.22 - - - - - - - - -
(wakeup mA
wakeup from See (4).
from Stop1)
Stop 1
Wakeup clock
HSI16 = 16 MHz,
3V 1.20 - - - - - - - - -
voltage Range 1.
See (4).
2. LCD enabled with external voltage source. Consumption from VLCD excluded. Refer to LCD controller characteristics for IVLCD.
DS11421 Rev 5
109/220
Table 35. Current consumption in Stop 0
110/220
VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 108 119 158 221 347 133 158 244 395 704
Supply
IDD_ALL current in 2.4 V 110 121 160 223 349 136 161 248 399 710
µA
(Stop 0) Stop 0 mode, 3V 111 123 161 224 352 139 164 251 403 716
RTC disabled
3.6 V 114 125 163 227 355 142 167 254 408 722(2)
DS11421 Rev 5

Table 36. Current consumption in Standby mode

- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 27.7 144 758 2 072 5 425 119 425 2866 7524 20510
2.4 V 50.9 187 892 2 408 6 247 183 564 3383 8778 23768
Supply current no independent watchdog
3V 90.2 253 1 090 2 884 7 409 225 681 3912 10071 26976
in Standby
IDD_ALL mode (backup 3.6 V 253 459 1 474 3 575 8 836 292 877 4638 11659 30758
nA
(Standby) registers 1.8 V 216 - - - - - - - - -
retained),
with independent 2.4 V 342 - - - - - - - - -
RTC disabled
watchdog 3V 416 - - - - - - - - -
3.6 V 551 - - - - - - - - -
1.8 V 287 407 989 2 230 5 396 585 944 3344 7866 20504
2.4 V 386 526 1 201 2 638 6 274 811 1230 4007 9246 23824
RTC clocked by LSI, no
DS11421 Rev 5
independent watchdog 3V 513 679 1 478 3 167 7 414 1022 1521 4683 10671 27124
30954
3.6 V 771 978 1 963 3 992 9 039 1284 1924 5577 12383 (2)
nA
1.8 V 342 - - - - - - - - -
RTC clocked by LSI, with 2.4 V 521 - - - - - - - - -
Supply current
in Standby independent watchdog 3V 655 - - - - - - - - -
IDD_ALL
mode (backup 3.6 V 865 - - - - - - - - -
(Standby
registers
with RTC) 1.8 V 142 126 865 2 220 5 650 - - - - -
retained),
RTC enabled RTC clocked by LSE 2.4 V 249 219 1 090 2 660 6 600 - - - - -
bypassed at 32768Hz 3V 404 364 1 410 3 260 7 850 - - - - -
3.6 V 742 670 2 000 4 230 9 700 - - - - -
nA
1.8 V 281 423 1 046 2 410 5 700 - - - - -
RTC clocked by LSE 2.4 V 388 548 1 268 2 847 6 564 - - - - -
quartz (3) in low drive mode 3 V 535 715 1 565 3 420 7 694 - - - - -
3.6 V 836 1 048 2 081 4 311 9 338 - - - - -
111/220
Table 36. Current consumption in Standby mode (continued)
112/220
- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Supply current 1.8 V 173 349 1 009 2 158 4 542 249 527 1604 3402 6908
IDD_ALL to be added in 2.4 V 174 345 1 015 2 163 4 535 271 589 1623 3438 6924
Standby mode - nA
(SRAM2)(4) 3V 178 350 1 019 2 148 4 419 277 594 1628 3467 6935
when SRAM2
is retained 3.6 V 184 352 1 033 2 208 4 610 293 611 1631 3480 6948
IDD_ALL Supply current Wakeup clock is
(wakeup during wakeup MSI = 4 MHz. 3V 1.23 - - - - - - - - - mA
from from Standby
See (5).
Standby) mode
4. The supply current in Standby with SRAM2 mode is: IDD_ALL(Standby) + IDD_ALL(SRAM2). The supply current in Standby with RTC with SRAM2 mode is: IDD_ALL(Standby
DS11421 Rev 5
+ RTC) + IDD_ALL(SRAM2).
Table 37. Current consumption in Shutdown mode

- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
Supply current 1.8 V 7.82 190 386 1 286 3 854 25.0 255 1721 5052 15543
in Shutdown 2.4 V 23 229 485 1 517 4 431 34.9 270 2085 5878 17639
mode
IDD_ALL 3V 44.3 290 634 1 878 5 310 70.1 345 2454 6755 19984
(backup - nA
(Shutdown)
registers
retained) RTC 3.6 V 212 397 977 2 516 6 656 119.1 496 2992 7939 22860
disabled
Table 37. Current consumption in Shutdown mode (continued)

- VDD 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 63 133 522 1 490 4 270 - - - - -
Supply current RTC clocked by LSE 2.4 V 165 253 710 1 830 4 980 - - - - -
in Shutdown bypassed at 32768 Hz 3V 316 423 990 2 340 6 050 - - - - -
IDD_ALL mode 3.6 V 649 787 1 530 3 220 7 710 - - - - -
(Shutdown (backup nA
with RTC) registers 1.8 V 203 293 700 1 675 - - - - - -
retained) RTC RTC clocked by LSE 2.4 V 303 411 880 2 001 - - - - - -
enabled quartz (2) in low drive
mode 3V 448 567 1 136 2 479 - - - - - -
3.6 V 744 887 1 609 3 256 - - - - - -
Supply current Wakeup clock is
IDD_ALL
during wakeup
(wakeup from MSI = 4 MHz. 3V 0.780 - - - - - - - - - mA
from Shutdown
Shutdown) See (3).
DS11421 Rev 5
mode
113/220
Table 38. Current consumption in VBAT mode
114/220
- VBAT 25 °C 55 °C 85 °C 105 °C 125 °C 25 °C 55 °C 85 °C 105 °C 125 °C
1.8 V 2 12 66 193 540 5 30 165 482 1350
2.4 V 1 12 73 217 600 6 30 182 542 1500
RTC disabled
3V 5 16 92 266 731 12.5 40 230 665 1928
3.6 V 6 30 161 459 1 269 15 75 402 1147 3173
1.8 V 154 175 247 430 - - - - - -
RTC enabled and 2.4 V 228 246 335 542 - - - - - -
IDD_VBAT Backup domain
clocked by LSE nA
(VBAT) supply current 3V 316 340 459 714 - - - - - -
bypassed at 32768 Hz
3.6 V 419 462 684 1 140 - - - - - -
1.8 V 256 297 385 558 823 - - - - -
RTC enabled and 2.4 V 345 381 477 673 906 - - - - -
clocked by LSE
DS11421 Rev 5
quartz(2) 3V 455 495 603 836 1 085 - - - - -

3.6 V 591 642 824 1 207 1 733 - - - - -

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 59: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 39: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
DS11421 Rev 5 115/220

185
On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 39. The MCU is placed
under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in
Table 39. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 39. Peripheral current consumption

Low-power run
Peripheral Range 1 Range 2 Unit
and sleep
Bus Matrix(1) 3.2 2.9 3.1

ADC independent clock domain 0.4 0.1 0.2
ADC clock domain 2.1 1.9 1.9
AES 1.7 1.5 1.6
CRC 0.4 0.2 0.3
DMA1 1.4 1.3 1.4
DMA2 1.5 1.3 1.4
FLASH 6.2 5.2 5.8
GPIOA(2) 1.7 1.4 1.6
(2))
GPIOB 1.6 1.3 1.6
AHB GPIOC(2) 1.7 1.5 1.6
(2)
GPIOD 1.8 1.6 1.7 µA/MHz
GPIOE(2) 1.7 1.6 1.6
GPIOH(2) 0.6 0.6 0.5
QSPI 7.0 5.8 7.3
RNG independent clock domain 2.2 N/A N/A
RNG clock domain 0.5 N/A N/A
SRAM1 0.8 0.9 0.7
SRAM2 1.0 0.8 0.8
TSC 1.6 1.3 1.3
All AHB Peripherals 25.2 21.7 23.6
(3)
AHB to APB1 bridge 0.9 0.7 0.9
APB1
CAN1 4.1 3.2 3.9
116/220 DS11421 Rev 5

Table 39. Peripheral current consumption (continued)

Low-power run
and sleep
DAC1 2.4 1.8 2.2

RTCA 1.7 1.1 2.1
CRS 0.3 0.3 0.6
USB FS independent clock
2.9 N/A N/A
domain
USB FS clock domain 2.3 N/A N/A
I2C1 independent clock domain 3.5 2.8 3.4
I2C1 clock domain 1.1 0.9 1.0
LCD 0.9 0.6 0.8
LPUART1 independent clock
1.9 1.6 1.8
domain
LPUART1 clock domain 0.6 0.6 0.6
LPTIM1 independent clock
2.9 2.4 2.8
APB1 domain µA/MHz
LPTIM1 clock domain 0.8 0.4 0.7
LPTIM2 independent clock
3.1 2.7 3.9
domain
LPTIM2 clock domain 0.8 0.7 0.8
OPAMP 0.4 0.2 0.4
PWR 0.4 0.1 0.4
SPI2 1.8 1.6 1.6
SPI3 1.7 1.3 1.6
SWPMI1 independent clock
1.9 1.6 1.9
domain
SWPMI1 clock domain 0.9 0.7 0.8
TIM2 6.2 5.0 5.9
TIM6 1.0 0.6 0.9
TIM7 1.0 0.6 0.6
USART2 independent clock
4.1 3.6 3.8
domain
USART2 clock domain 1.3 0.9 1.1
DS11421 Rev 5 117/220

185
Table 39. Peripheral current consumption (continued)

Low-power run
and sleep

4.3 3.5 4.2
domain
APB1 USART3 clock domain 1.5 1.1 1.3

WWDG 0.5 0.5 0.5
All APB1 on 51.5 35.5 48.6
AHB to APB2(4) 1.0 0.9 0.9
FW 0.2 0.2 0.2
SAI1 independent clock domain 2.3 1.8 1.9
SAI1 clock domain 2.1 1.8 2.0
SDMMC1 independent clock
4.7 3.9 3.9
domain
µA/MHz
SDMMC1 clock domain 2.5 1.9 1.9
SPI1 1.8 1.6 1.7
APB2
SYSCFG/VREFBUF/COMP 0.6 0.5 0.6
TIM1 8.1 6.5 7.6
TIM15 3.7 3.0 3.4
TIM16 2.7 2.1 2.6
4.8 4.2 4.6
domain
USART1 clock domain 1.5 1.3 1.7
All APB2 on 24.2 19.9 22.6
ALL 100.9 77.1 94.8
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The GPIOx (x= A…H) dynamic current consumption is approximately divided by a factor two versus this table values when
the GPIO port is locked thanks to LCKK and LCKy bits in the GPIOx_LCKR register. In order to save the full GPIOx current
consumption, the GPIOx clock should be disabled in the RCC when all port I/Os are used in alternate function or analog
mode (clock is only required to read or write into GPIO registers, and is not used in AF or analog modes).
3. The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1.
4. The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2.
6.3.6 Wakeup time from low-power modes and voltage scaling

transition times
The wakeup times given in Table 40 are the latency between the event and the execution of
the first user instruction.
The device goes in low-power mode after the WFE (Wait For Event) instruction.
118/220 DS11421 Rev 5

Table 40. Low-power mode wakeup timings(1)

Symbol Parameter Conditions Typ Max Unit
Wakeup time from Sleep

tWUSLEEP - 6 6
mode to Run mode
Nb of
CPU
Wakeup time from Low- Wakeup in Flash with Flash in power-down cycles
tWULPSLEEP power sleep mode to Low- during low-power sleep mode (SLEEP_PD=1 in 6 8.3
power run mode FLASH_ACR) and with clock MSI = 2 MHz
Wakeup clock MSI = 48 MHz 3.8 5.7

Range 1
Wakeup clock HSI16 = 16 MHz 4.1 6.9
Wake up time from Stop 0
mode to Run mode in Wakeup clock MSI = 24 MHz 4.07 6.2
Flash
Range 2 Wakeup clock HSI16 = 16 MHz 4.1 6.8
tWUSTOP0 µs
Range 1
SRAM1
Range 1
mode to Run in Flash
Range 1
tWUSTOP1 mode to Run mode in Wakeup clock MSI = 24 MHz 5.4 6.51 µs
SRAM1

mode to Low-power run 16.4 17.73
Regulator in
mode in Flash
low-power
Wakeup clock MSI = 2 MHz
mode (LPR=1
in PWR_CR1)
mode to Low-power run 17.3 18.82
mode in SRAM1
DS11421 Rev 5 119/220

185
Table 40. Low-power mode wakeup timings(1) (continued)


Range 1
Flash
tWUSTOP2 µs
Range 1
SRAM1
Wakeup time from Standby Wakeup clock MSI = 8 MHz 12.2 18.35
tWUSTBY Range 1 µs
mode to Run mode Wakeup clock MSI = 4 MHz 19.14 25.8
tWUSTBY Wakeup time from Standby Wakeup clock MSI = 8 MHz 12.1 18.3
Range 1 µs
SRAM2 with SRAM2 to Run mode Wakeup clock MSI = 4 MHz 19.2 25.87
Wakeup time from
tWUSHDN Shutdown mode to Run Range 1 Wakeup clock MSI = 4 MHz 261.5 315.7 µs
mode
1. Guaranteed by characterization results.
Table 41. Regulator modes transition times(1)

Wakeup time from Low-power run mode to

tWULPRUN Code run with MSI 2 MHz 5 7
Run mode(2)
µs
Regulator transition time from Range 2 to
tVOST Code run with MSI 24 MHz 20 40
Range 1 or Range 1 to Range 2(3)
2. Time until REGLPF flag is cleared in PWR_SR2.
3. Time until VOSF flag is cleared in PWR_SR2.
Table 42. Wakeup time using USART/LPUART(1)

Wakeup time needed to calculate the Stop 0 mode - 1.7

tWUUSART maximum USART/LPUART baudrate
allowing to wakeup up from stop mode Stop 1 mode and Stop 2 µs
tWULPUART - 8.5
when USART/LPUART clock source is mode
HSI16
120/220 DS11421 Rev 5

6.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 20: High-speed external clock
source AC timing diagram.
Table 43. High-speed external user clock characteristics(1)

Voltage scaling
- 8 48
Range 1
fHSE_ext User external clock source frequency MHz
Voltage scaling
- 8 26
Range 2
VHSEH OSC_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx
V
VHSEL OSC_IN input pin low level voltage - VSS - 0.3 VDDIOx
Voltage scaling
7 - -
tw(HSEH) Range 1
OSC_IN high or low time ns
tw(HSEL) Voltage scaling
18 - -
Range 2
Figure 20. High-speed external clock source AC timing diagram
tw(HSEH)
VHSEH
90%
10%
VHSEL
tr(HSE) t
tf(HSE) tw(HSEL)
THSE
MS19214V2
DS11421 Rev 5 121/220

185
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 21.
Table 44. Low-speed external user clock characteristics(1)

fLSE_ext User external clock source frequency - - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage - 0.7 VDDIOx - VDDIOx
V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
Figure 21. Low-speed external clock source AC timing diagram
tw(LSEH)
VLSEH
90%
10%
VLSEL
tr(LSE) t
tf(LSE) tw(LSEL)
TLSE
MS19215V2
122/220 DS11421 Rev 5

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 45. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 45. HSE oscillator characteristics(1)

fOSC_IN Oscillator frequency - 4 8 48 MHz

RF Feedback resistor - - 200 - kΩ
(3)
During startup - - 5.5
VDD = 3 V,
Rm = 30 Ω, - 0.44 -
CL = 10 pF@8 MHz
VDD = 3 V,
Rm = 45 Ω, - 0.45 -
CL = 10 pF@8 MHz
IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 30 Ω, - 0.68 -
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 0.94 -
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 1.77 -
CL = 20 pF@48 MHz
Maximum critical crystal
Gm Startup - - 1.5 mA/V
transconductance
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 22). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
DS11421 Rev 5 123/220

185
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 22. Typical application with an 8 MHz crystal
Resonator with integrated

capacitors
CL1
OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain
REXT (1) OSC_OUT

CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 46. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 46. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

LSEDRV[1:0] = 00
- 250 -
Low drive capability
LSEDRV[1:0] = 01
- 315 -
Medium low drive capability
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10
- 500 -
Medium high drive capability
LSEDRV[1:0] = 11
- 630 -
High drive capability
LSEDRV[1:0] = 00
- - 0.5
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Maximum critical crystal Medium low drive capability
Gmcritmax µA/V
gm LSEDRV[1:0] = 10
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
124/220 DS11421 Rev 5

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 23. Typical application with a 32.768 kHz crystal
Resonator with integrated

capacitors
CL1
OSC32_IN fLSE
32.768 kHz Drive

resonator programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DS11421 Rev 5 125/220

185
6.3.8 Internal clock source characteristics

The parameters given in Table 47 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI16) RC oscillator
Table 47. HSI16 oscillator characteristics(1)

fHSI16 HSI16 Frequency VDD=3.0 V, TA=30 °C 15.88 - 16.08 MHz

Trimming code is not a
0.2 0.3 0.4
multiple of 64
TRIM HSI16 user trimming step %
Trimming code is a
-4 -6 -8
multiple of 64
DuCy(HSI16)(2) Duty Cycle - 45 - 55 %
HSI16 oscillator frequency TA= 0 to 85 °C -1 - 1 %

∆Temp(HSI16)
drift over temperature TA= -40 to 125 °C -2 - 1.5 %
HSI16 oscillator frequency
∆VDD(HSI16) VDD=1.62 V to 3.6 V -0.1 - 0.05 %
drift over VDD
HSI16 oscillator start-up
tsu(HSI16)(2) - - 0.8 1.2 μs
time
HSI16 oscillator
tstab(HSI16)(2) - - 3 5 μs
stabilization time
HSI16 oscillator power
IDD(HSI16)(2) - - 155 190 μA
consumption
126/220 DS11421 Rev 5

Figure 24. HSI16 frequency versus temperature

MHz
16.4
+2%
16.3
+1.5%
16.2 +1%
16.1
16
15.9
-1%
15.8
-1.5%
15.7
-2%
15.6
-40 -20 0 20 40 60 80 100 120 °C
min mean max
MSv39299V1
DS11421 Rev 5 127/220

185
Multi-speed internal (MSI) RC oscillator
Table 48. MSI oscillator characteristics(1)

Range 0 98.7 100 101.3

Range 1 197.4 200 202.6
kHz
Range 2 394.8 400 405.2
Range 3 789.6 800 810.4
Range 4 0.987 1 1.013
Range 5 1.974 2 2.026
MSI mode
Range 6 3.948 4 4.052
Range 7 7.896 8 8.104
MHz
Range 8 15.79 16 16.21
Range 9 23.69 24 24.31
MSI frequency Range 10 31.58 32 32.42

after factory Range 11 47.38 48 48.62
fMSI calibration, done
at VDD=3 V and Range 0 - 98.304 -
TA=30 °C Range 1 - 196.608 -
kHz
Range 2 - 393.216 -
Range 3 - 786.432 -
Range 4 - 1.016 -
PLL mode Range 5 - 1.999 -
XTAL=
32.768 kHz Range 6 - 3.998 -
Range 7 - 7.995 -
MHz
Range 8 - 15.991 -
Range 9 - 23.986 -
Range 10 - 32.014 -
Range 11 - 48.005 -
MSI oscillator TA= -0 to 85 °C -3.5 - 3
∆TEMP(MSI)(2) frequency drift MSI mode %
over temperature TA= -40 to 125 °C -8 - 6
128/220 DS11421 Rev 5

Table 48. MSI oscillator characteristics(1) (continued)

VDD=1.62 V
-1.2 -
to 3.6 V
Range 0 to 3 0.5
VDD=2.4 V
-0.5 -
to 3.6 V
MSI oscillator VDD=1.62 V

-2.5 -
frequency drift to 3.6 V
(2)
∆VDD(MSI) MSI mode Range 4 to 7 0.7 %
over VDD VDD=2.4 V
(reference is 3 V) -0.8 -
to 3.6 V
VDD=1.62 V
-5 -
to 3.6 V
Range 8 to 11 1
VDD=2.4 V
-1.6 -
to 3.6 V
Frequency TA= -40 to 85 °C - 1 2
∆FSAMPLING
variation in MSI mode %
(MSI)(2)(6) TA= -40 to 125 °C - 2 4
sampling mode(3)
for next
- - - 3.458
P_USB Period jitter for PLL mode transition
ns
Jitter(MSI)(6) USB clock(4) Range 11 for paired
- - - 3.916
transition
for next
- - - 2
MT_USB Medium term jitter PLL mode transition
ns
Jitter(MSI)(6) for USB clock(5) Range 11 for paired
- - - 1
transition
RMS cycle-to-
CC jitter(MSI)(6) PLL mode Range 11 - - 60 - ps
cycle jitter
P jitter(MSI)(6) RMS Period jitter PLL mode Range 11 - - 50 - ps
Range 0 - - 10 20
Range 1 - - 5 10
MSI oscillator Range 2 - - 4 8

tSU(MSI)(6) us
start-up time Range 3 - - 3 7
Range 4 to 7 - - 3 6
Range 8 to 11 - - 2.5 6
10 % of final
- - 0.25 0.5
frequency
MSI oscillator PLL mode 5 % of final
tSTAB(MSI)(6) - - 0.5 1.25 ms
stabilization time Range 11 frequency
1 % of final
- - - 2.5
frequency
DS11421 Rev 5 129/220

185
Table 48. MSI oscillator characteristics(1) (continued)

Range 0 - - 0.6 1
Range 1 - - 0.8 1.2
Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
MSI oscillator Range 5 - - 6.5 9
MSI and
IDD(MSI)(6) power µA
PLL mode Range 6 - - 11 15
consumption
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Average period of MSI @48 MHz is compared to a real 48 MHz clock over 28 cycles. It includes frequency tolerance + jitter
of MSI @48 MHz clock.
5. Only accumulated jitter of MSI @48 MHz is extracted over 28 cycles.
For next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of the MSI @48 MHz, for 1000 captures over 28
cycles.
For paired transitions: min. and max. jitter of 2 consecutive frame of 56 cycles of the MSI @48 MHz, for 1000 captures over
56 cycles.
130/220 DS11421 Rev 5

Figure 25. Typical current consumption versus MSI frequency
High-speed internal 48 MHz (HSI48) RC oscillator
Table 49. HSI48 oscillator characteristics(1)

fHSI48 HSI48 Frequency VDD=3.0V, TA=30°C - 48 - MHz

TRIM HSI48 user trimming step - - 0.11(2) 0.18(2) %
USER TRIM
HSI48 user trimming coverage ±32 steps ±3(3) ±3.5(3) - %
COVERAGE
DuCy(HSI48) Duty Cycle - 45(2) - 55(2) %
VDD = 3.0 V to 3.6 V,
Accuracy of the HSI48 oscillator - - ±3(3)
TA = –15 to 85 °C
ACCHSI48_REL over temperature (factory %
calibrated) VDD = 1.65 V to 3.6 V,
- - ±4.5(3)
TA = –40 to 125 °C
HSI48 oscillator frequency drift VDD = 3 V to 3.6 V - 0.025(3) 0.05(3)

DVDD(HSI48) %
with VDD VDD = 1.65 V to 3.6 V - 0.05(3) 0.1(3)
tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs
HSI48 oscillator power
IDD(HSI48) - - 340(2) 380(2) μA
consumption
DS11421 Rev 5 131/220

185
Table 49. HSI48 oscillator characteristics(1) (continued)

Next transition jitter

NT jitter - - +/-0.15(2) - ns
Accumulated jitter on 28 cycles(4)
Paired transition jitter
PT jitter - - +/-0.25(2) - ns
Accumulated jitter on 56 cycles(4)
1. VDD = 3 V, TA = –40 to 125°C unless otherwise specified.
4. Jitter measurement are performed without clock source activated in parallel.
Figure 26. HSI48 frequency versus temperature

%
6
-2
-4
-6
-50 -30 -10 10 30 50 70 90 110 130
°C
Avg min max
MSv40989V1
Low-speed internal (LSI) RC oscillator
Table 50. LSI oscillator characteristics(1)

VDD = 3.0 V, TA = 30 °C 31.04 - 32.96

fLSI LSI Frequency kHz
VDD = 1.62 to 3.6 V, TA = -40 to 125 °C 29.5 - 34
LSI oscillator start-
tSU(LSI)(2) - - 80 130 μs
up time
LSI oscillator
tSTAB(LSI)(2) 5% of final frequency - 125 180 μs
stabilization time
LSI oscillator power
IDD(LSI)(2) - - 110 180 nA
consumption
132/220 DS11421 Rev 5

6.3.9 PLL characteristics

The parameters given in Table 51 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 21: General operating conditions.
Table 51. PLL, PLLSAI1 characteristics(1)

PLL input clock(2) - 4 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 45 - 55 %
Voltage scaling Range 1 3.0968 - 80
fPLL_P_OUT PLL multiplier output clock P MHz
Voltage scaling Range 2 3.0968 - 26
Voltage scaling Range 1 12 - 80
fPLL_Q_OUT PLL multiplier output clock Q MHz
fPLL_R_OUT PLL multiplier output clock R MHz
fVCO_OUT PLL VCO output MHz
tLOCK PLL lock time - - 15 40 μs
RMS cycle-to-cycle jitter - 40 -
Jitter System clock 80 MHz ±ps
RMS period jitter - 30 -
VCO freq = 96 MHz - 200 260
PLL power consumption on
IDD(PLL) VCO freq = 192 MHz - 300 380 μA
VDD(1)
VCO freq = 344 MHz - 520 650
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the 2 PLLs.
DS11421 Rev 5 133/220

185
6.3.10 Flash memory characteristics
Table 52. Flash memory characteristics(1)

tprog 64-bit programming time - 81.69 90.76 µs
one row (32 double normal programming 2.61 2.90

tprog_row
word) programming time fast programming 1.91 2.12
one page (2 Kbyte) normal programming 20.91 23.24 ms

tprog_page
programming time fast programming 15.29 16.98
tERASE Page (2 KB) erase time - 22.02 24.47
one bank (512 Kbyte) normal programming 5.35 5.95

tprog_bank s
programming time fast programming 3.91 4.35
Mass erase time
tME - 22.13 24.59 ms
(one or two banks)
Average consumption Write mode 3.4 -

from VDD Erase mode 3.4 -
IDD mA
Write mode 7 (for 2 μs) -
Maximum current (peak)
Erase mode 7 (for 41 μs) -
Table 53. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
NEND Endurance TA = –40 to +105 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30
(2)
1 kcycle at TA = 105 °C 15
(2)
1 kcycle at TA = 125 °C 7
tRET Data retention Years
(2)
10 kcycles at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
(2)
10 kcycles at TA = 105 °C 10
2. Cycling performed over the whole temperature range.
134/220 DS11421 Rev 5

6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 54. They are based on the EMS levels and classes
defined in application note AN1709.
Table 54. EMS characteristics

Level/
Symbol Parameter Conditions
Class
VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin
VFESD fHCLK = 80 MHz, 3B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 80 MHz, 5A
pins to induce a functional disturbance conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
DS11421 Rev 5 135/220

185
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 55. EMI characteristics

Max vs.
Monitored [fHSE/fHCLK]
Symbol Parameter Conditions Unit
frequency band
8 MHz/ 80 MHz
0.1 MHz to 30 MHz -8

VDD = 3.6 V, TA = 25 °C, 30 MHz to 130 MHz 2
LQFP100 package dBµV
SEMI Peak level 130 MHz to 1 GHz 5
compliant with IEC
61967-2 1 GHz to 2 GHz 8
EMI Level 2.5 -
6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 56. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)
TA = +25 °C, conforming

Electrostatic discharge
VESD(HBM) to ANSI/ESDA/JEDEC 2 2000
voltage (human body model)
JS-001
V
Electrostatic discharge TA = +25 °C,
VESD(CDM) voltage (charge device conforming to ANSI/ESD C3 250
model) STM5.3.1
136/220 DS11421 Rev 5

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 57. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II
6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 58.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 58. I/O current injection susceptibility(1)

Functional
susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on all pins except PA4, PA5, PE8, PE9,

-5 N/A(2)
PE10, PE11, PE12
IINJ mA
Injected current on PE8, PE9, PE10, PE11, PE12 -0 N/A(2)
Injected current on PA4, PA5 pins -5 0
2. Injection is not possible.
DS11421 Rev 5 137/220

185
6.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 59. I/O static characteristics

I/O input low level

1.62 V<VDDIOx<3.6 V - - 0.3xVDDIOx (2)
voltage
I/O input low level
VIL(1) 1.62 V<VDDIOx<3.6 V - - 0.39xVDDIOx-0.06 (3) V
voltage
I/O input low level
1.08 V<VDDIOx<1.62 V - - 0.43xVDDIOx-0.1 (3)
voltage
I/O input high level
1.62 V<VDDIOx<3.6 V 0.7xVDDIOx (2) - -
voltage
VIH(1) 1.62 V<VDDIOx<3.6 V 0.49xVDDIOX+0.26 (3) - - V
voltage
1.08 V<VDDIOx<1.62 V 0.61xVDDIOX+0.05 (3) - -
voltage
TT_xx, FT_xxx and
Vhys(3) NRST I/O input 1.62 V<VDDIOx<3.6 V - 200 - mV
hysteresis
VIN ≤
- - ±100
Max(VDDXXX)(6)(7)
FT_xx input leakage Max(VDDXXX) ≤ VIN ≤
- - 650
current(3)(5) Max(VDDXXX)+1 V(6)(7)
Max(VDDXXX)+1 V <
- - 200
VIN ≤ 5.5 V(6)(7)
VIN ≤
- - ±150
Ilkg(4) Max(VDDXXX)(6)(7) nA
Max(VDDXXX) ≤ VIN ≤
FT_u and PC3 I/Os - - 2500(3)
Max(VDDXXX)+1 V(6)(7)
Max(VDDXXX)+1 V <
- - 250
VIN ≤ 5.5 V(6)(7)
VIN ≤ Max(VDDXXX)(6) - - ±150
TT_xx input leakage
current Max(VDDXXX) ≤ VIN <
- - 2000(3)
3.6 V(6)
Weak pull-up
RPU V = VSS 25 40 55 kΩ
equivalent resistor (8) IN
Weak pull-down
RPD VIN = VDDIOx 25 40 55 kΩ
equivalent resistor(8)
CIO I/O pin capacitance - - 5 - pF
138/220 DS11421 Rev 5

1. Refer to Figure 27: I/O input characteristics.

2. Tested in production.
4. This value represents the pad leakage of the IO itself. The total product pad leakage is provided by this formula:
ITotal_Ileak_max = 10 µA + [number of IOs where VIN is applied on the pad] ₓ Ilkg(Max).
5. All FT_xx GPIOs except FT_u and PC3 I/Os.
6. Max(VDDXXX) is the maximum value of all the I/O supplies.
7. To sustain a voltage higher than Min(VDD, VDDA, VDDUSB, VLCD) +0.3 V, the internal Pull-up and Pull-Down resistors must
be disabled.
8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 27 for standard I/Os, and in Figure 27 for
5 V tolerant I/Os.
Figure 27. I/O input characteristics
TTL requirement Vih min = 2V
V DDIO
x
x>
1.62
= 0.7x 6 for
V DDIO
min +0.2
Vih 9xV DD
IOx
em ent r 0.4
quir 2o
re x <1.6 x>1
.62
OS <V DDIO for VDDIO
on CM for 1.08 -0.06
rod ucti x+
0.05 9 xVDDIOx
in p DDIO or 0.3
ted =0 .61xV VDDIOx
<1.62
Tes ih min r 1.08<
nV -0.1 fo
ulatio xVDDIOx
n sim ax =0
.43
Ba sed o n Vil m xVdd
TTL requirement Vil max = 0.8V
tio .3
on simula ent Vil max = 0
Based OS requirem
ction CM
in produ
Tested
MSv37613V1
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL/VOH).
DS11421 Rev 5 139/220

185
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
• The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 18: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 18: Voltage characteristics).
Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
Table 60. Output voltage characteristics(1)

VOL Output low level voltage for an I/O pin CMOS port(2) - 0.4
|IIO| = 8 mA
VOH Output high level voltage for an I/O pin V VDDIOx-0.4 -
DDIOx ≥ 2.7 V
VOL(3) Output low level voltage for an I/O pin TTL port(2) - 0.4
|IIO| = 8 mA
VOH(3) Output high level voltage for an I/O pin V 2.4 -
DDIOx ≥ 2.7 V
VOL(3) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3
VOH (3) Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx-1.3 -
(3)
VOL Output low level voltage for an I/O pin |IIO| = 4 mA - 0.45
V
VOH(3) Output high level voltage for an I/O pin VDDIOx ≥ 1.62 V VDDIOx-0.45 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 2 mA - 0.35ₓVDDIOx
VOH (3)
Output high level voltage for an I/O pin 1.62 V ≥ VDDIOx ≥ 1.08 V 0.65ₓVDDIOx -
|IIO| = 20 mA
- 0.4
VDDIOx ≥ 2.7 V
Output low level voltage for an FT I/O
VOLFM+ |IIO| = 10 mA
(3) pin in FM+ mode (FT I/O with "f" - 0.4
VDDIOx ≥ 1.62 V
option)
|IIO| = 2 mA
- 0.4
1.62 V ≥ VDDIOx ≥ 1.08 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 28 and
Table 61, respectively.
140/220 DS11421 Rev 5

Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
Table 61. I/O AC characteristics(1)(2)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 1
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1
Fmax Maximum frequency MHz
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 10
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 1.5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 0.1
00
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 52
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 140
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 17
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 110
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 25
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 10
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 1
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 50
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 15
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 1
01
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 9
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 16
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 40
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 4.5
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 9
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 21
DS11421 Rev 5 141/220

185
Table 61. I/O AC characteristics(1)(2) (continued)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 50

C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 25
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 5
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 100(3)
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 37.5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 5
10
C=50 pF, 2.7 V≤VDDIOx≤3.6 V - 5.8
C=50 pF, 1.62 V≤VDDIOx≤2.7 V - 11
C=50 pF, 1.08 V≤VDDIOx≤1.62 V - 28
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 2.5
C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 5
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 12
C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 120(3)
C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 50
C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 10
C=10 pF, 2.7 V≤VDDIOx≤3.6 V - 180(3)
11 C=10 pF, 1.62 V≤VDDIOx≤2.7 V - 75
C=10 pF, 1.08 V≤VDDIOx≤1.62 V - 10
C=30 pF, 2.7 V≤VDDIOx≤3.6 V - 3.3
Tr/Tf Output rise and fall time C=30 pF, 1.62 V≤VDDIOx≤2.7 V - 6 ns
C=30 pF, 1.08 V≤VDDIOx≤1.62 V - 16
Fmax Maximum frequency - 1 MHz
Fm+ C=50 pF, 1.6 V≤VDDIOx≤3.6 V
(4)
Tf Output fall time - 5 ns
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0394 reference manual for a description of GPIO Port configuration register.
3. This value represents the I/O capability but the maximum system frequency is limited to 80 MHz.
4. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.
142/220 DS11421 Rev 5

Figure 28. I/O AC characteristics definition(1)

90% 10%
50% 50%
10% 90%
t r(IO)out t f(IO)out
Maximum frequency is achieved if (t r + t f (≤ 2/3)T and if the duty cycle is (45-55%)

when loaded by the specified capacitance.
MS32132V2
1. Refer to Table 61: I/O AC characteristics.
6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions.
Table 62. NRST pin characteristics(1)

NRST input low level

VIL(NRST) - - - 0.3ₓVDDIOx
voltage
V
NRST input high level
VIH(NRST) - 0.7ₓVDDIOx - -
voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up
RPU VIN = VSS 25 40 55 kΩ
equivalent resistor(2)
NRST input filtered
VF(NRST) - - - 70 ns
pulse
NRST input not filtered
VNF(NRST) 1.71 V ≤ VDD ≤ 3.6 V 350 - - ns
pulse
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
DS11421 Rev 5 143/220

185
Figure 29. Recommended NRST pin protection
External
reset circuit(1) VDD
RPU
NRST(2) Internal reset
Filter
0.1 μF
MS19878V3
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 62: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
6.3.16 Extended interrupt and event controller input (EXTI) characteristics

The pulse on the interrupt input must have a minimal length in order to guarantee that it is
detected by the event controller.
Table 63. EXTI Input Characteristics(1)

Pulse length to event

PLEC - 20 - - ns
controller
6.3.17 Analog switches booster
Table 64. Analog switches booster characteristics(1)

Symbol Parameter Min Typ Max Unit
VDD Supply voltage 1.62 - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs
Booster consumption for
- - 250
1.62 V ≤ VDD ≤ 2.0 V
IDD(BOOST) - - 500 µA
2.0 V ≤ VDD ≤ 2.7 V
- - 900
2.7 V ≤ VDD ≤ 3.6 V
144/220 DS11421 Rev 5

6.3.18 Analog-to-Digital converter characteristics

Unless otherwise specified, the parameters given in Table 65 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 21: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 65. ADC characteristics(1) (2)

VDDA Analog supply voltage - 1.62 - 3.6 V

VDDA ≥ 2 V 2 - VDDA V
VREF+ Positive reference voltage
VDDA < 2 V VDDA V
Negative reference
VREF- - VSSA V
voltage
Range 1 0.14 - 80
fADC ADC clock frequency MHz
Range 2 0.14 - 26
Resolution = 12 bits - - 5.33
Sampling rate for FAST Resolution = 10 bits - - 6.15

channels Resolution = 8 bits - - 7.27
fs Msps
Sampling rate for SLOW Resolution = 10 bits - - 4.71

channels Resolution = 8 bits - - 5.33
fADC = 80 MHz
- - 5.33 MHz
fTRIG External trigger frequency Resolution = 12 bits
Resolution = 12 bits - - 15 1/fADC
(VREF++ (VREF++
(VREF++
VCMIN Input common mode Differential mode VREF-)/2 VREF-)/2 V
VREF-)/2
- 0.18 + 0.18
Conversion voltage
VAIN (3) - 0 - VREF+ V
range(2)
RAIN External input impedance - - - 50 kΩ
Internal sample and hold
CADC - - 5 - pF
capacitor
conversion
tSTAB Power-up time - 1
cycle
fADC = 80 MHz 1.45 µs
tCAL Calibration time
- 116 1/fADC
DS11421 Rev 5 145/220

185
Table 65. ADC characteristics(1) (2) (continued)

CKMODE = 00 1.5 2 2.5

Trigger conversion
latency Regular and CKMODE = 01 - - 2.0
tLATR 1/fADC
injected channels without CKMODE = 10 - - 2.25
conversion abort
CKMODE = 11 - - 2.125
CKMODE = 00 2.5 3 3.5
Trigger conversion
latency Injected channels CKMODE = 01 - - 3.0
tLATRINJ 1/fADC
aborting a regular CKMODE = 10 - - 3.25
conversion
CKMODE = 11 - - 3.125
fADC = 80 MHz 0.03125 - 8.00625 µs
ts Sampling time
- 2.5 - 640.5 1/fADC
ADC voltage regulator
tADCVREG_STUP start-up time - - - 20 µs
fADC = 80 MHz
0.1875 - 8.1625 µs
Resolution = 12 bits
Total conversion time
tCONV ts + 12.5 cycles for
(including sampling time)
Resolution = 12 bits successive approximation 1/fADC
= 15 to 653
fs = 5 Msps - 730 830
ADC consumption from
IDDA(ADC) fs = 1 Msps - 160 220 µA
the VDDA supply
fs = 10 ksps - 16 50
fs = 5 Msps - 130 160
IDDV_S(ADC) the VREF+ single ended fs = 1 Msps - 30 40 µA
mode
fs = 10 ksps - 0.6 2
fs = 5 Msps - 260 310
IDDV_D(ADC) the VREF+ differential fs = 1 Msps - 60 70 µA
mode
fs = 10 ksps - 1.3 3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enable when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pinouts and pin description for further details.
The maximum value of RAIN can be found in Table 66: Maximum ADC RAIN.
146/220 DS11421 Rev 5

Table 66. Maximum ADC RAIN(1)(2)

RAIN max (Ω)
Sampling cycle Sampling time [ns]
Resolution
@80 MHz @80 MHz
Fast channels(3) Slow channels(4)
2.5 31.25 100 N/A

6.5 81.25 330 100
12.5 156.25 680 470
24.5 306.25 1500 1200
12 bits
47.5 593.75 2200 1800
92.5 1156.25 4700 3900
247.5 3093.75 12000 10000
640.5 8006.75 39000 33000
2.5 31.25 120 N/A
6.5 81.25 390 180
12.5 156.25 820 560
24.5 306.25 1500 1200
10 bits
47.5 593.75 2200 1800
92.5 1156.25 5600 4700
247.5 3093.75 12000 10000
640.5 8006.75 47000 39000
2.5 31.25 180 N/A
6.5 81.25 470 270
12.5 156.25 1000 680
24.5 306.25 1800 1500
8 bits
47.5 593.75 2700 2200
92.5 1156.25 6800 5600
247.5 3093.75 15000 12000
640.5 8006.75 50000 50000
2.5 31.25 220 N/A
6.5 81.25 560 330
12.5 156.25 1200 1000
24.5 306.25 2700 2200
6 bits
47.5 593.75 3900 3300
92.5 1156.25 8200 6800
247.5 3093.75 18000 15000
640.5 8006.75 50000 50000
DS11421 Rev 5 147/220

185
VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. Fast channels are: PC0, PC1, PC2, PC3, PA0, PA1.
4. Slow channels are: all ADC inputs except the fast channels.
148/220 DS11421 Rev 5

Table 67. ADC accuracy - limited test conditions 1(1)(2)(3)

Sym-
Parameter Conditions(4) Min Typ Max Unit
bol
Single Fast channel (max speed) - 4 5

Total ended Slow channel (max speed) - 4 5
ET unadjusted
error Fast channel (max speed) - 3.5 4.5
Differential
Slow channel (max speed) - 3.5 4.5
Single Fast channel (max speed) - 1 2.5

ended Slow channel (max speed) - 1 2.5
Offset
EO
Differential
Single Fast channel (max speed) - 2.5 4.5

ended Slow channel (max speed) - 2.5 4.5
EG Gain error LSB
Fast channel (max speed) - 2.5 3.5
Differential

Differential ended Slow channel (max speed) - 1 1.5
ED linearity
error ADC clock frequency ≤ Fast channel (max speed) - 1 1.2
80 MHz, Differential
Slow channel (max speed) - 1 1.2
Sampling rate ≤ 5.33 Msps,
VDDA = VREF+ = 3 V, Single Fast channel (max speed) - 1.5 2.5
Integral TA = 25 °C ended Slow channel (max speed) - 1.5 2.5
EL linearity
error Fast channel (max speed) - 1 2
Differential
Slow channel (max speed) - 1 2
Single Fast channel (max speed) 10.4 10.5 -

Effective ended Slow channel (max speed) 10.4 10.5 -
ENOB number of bits
bits Fast channel (max speed) 10.8 10.9 -
Differential
Slow channel (max speed) 10.8 10.9 -
Single Fast channel (max speed) 64.4 65 -

Signal-to-
ended Slow channel (max speed) 64.4 65 -
noise and
SINAD
distortion Fast channel (max speed) 66.8 67.4 -
ratio Differential
dB
Single Fast channel (max speed) 65 66 -
ended Slow channel (max speed) 65 66 -
Signal-to-
SNR
noise ratio Fast channel (max speed) 67 68 -
Differential
Slow channel (max speed) 67 68 -
DS11421 Rev 5 149/220

185
Table 67. ADC accuracy - limited test conditions 1(1)(2)(3) (continued)

Sym-
bol
ADC clock frequency ≤ Single Fast channel (max speed) - -74 -73
Total 80 MHz, ended Slow channel (max speed) - -74 -73
THD harmonic Sampling rate ≤ 5.33 Msps, dB
distortion VDDA = VREF+ = 3 V, Fast channel (max speed) - -79 -76
Differential
TA = 25 °C Slow channel (max speed) - -79 -76
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
VDDA < 2.4 V). It is disable when VDDA ≥ 2.4 V. No oversampling.
150/220 DS11421 Rev 5


Sym-
bol

Total ended Slow channel (max speed) - 4 6.5
ET unadjusted
Differential

ended Slow channel (max speed) - 1 5
Offset
EO
error Fast channel (max speed) - 1.5 3
Differential
Slow channel (max speed) - 1.5 3
Single Fast channel (max speed) - 2.5 6

ended Slow channel (max speed) - 2.5 6
EG Gain error LSB
Fast channel (max speed) - 2.5 3.5
Differential

ED linearity
error Fast channel (max speed) - 1 1.2
ADC clock frequency ≤ Differential
80 MHz, Slow channel (max speed) - 1 1.2
Sampling rate ≤ 5.33 Msps, Fast channel (max speed) - 1.5 3.5
Single
2 V ≤ VDDA ended
Integral Slow channel (max speed) - 1.5 3.5
EL linearity
Differential
Single Fast channel (max speed) 10 10.5 -

Effective ended Slow channel (max speed) 10 10.5 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 66 67.4 -
ratio Differential
Slow channel (max speed) 66 67.4 -
dB
Signal-to-
SNR
noise ratio Fast channel (max speed) 66.5 68 -
Differential
Slow channel (max speed) 66.5 68 -
DS11421 Rev 5 151/220

185

Sym-
bol
Single Fast channel (max speed) - -74 -65

ADC clock frequency ≤
THD harmonic dB
Sampling rate ≤ 5.33 Msps, Fast channel (max speed) - -79 -70
distortion
2 V ≤ VDDA Differential
Slow channel (max speed) - -79 -71
152/220 DS11421 Rev 5


Sym-
bol

Total ended Slow channel (max speed) - 4.5 6.5
ET unadjusted
Differential

Offset
EO
Differential
Single Fast channel (max speed) - 4.5 7

EG Gain error LSB
Fast channel (max speed) - 3.5 4
Differential

Differential ended Slow channel (max speed) - 1.2 1.5
ED linearity ADC clock frequency ≤
Sampling rate ≤ 5.33 Msps, Slow channel (max speed) - 1 1.2
1.65 V ≤ VDDA = VREF+ ≤ Fast channel (max speed) - 3 3.5
Single
3.6 V,
Integral ended Slow channel (max speed) - 2.5 3.5
EL linearity Voltage scaling Range 1
Differential
Single Fast channel (max speed) 10 10.4 -

Effective ended Slow channel (max speed) 10 10.4 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 65 66 -
ratio Differential
dB
Signal-to-
SNR
Differential
DS11421 Rev 5 153/220

185

Sym-
bol
80 MHz, ended
Total Slow channel (max speed) - -71 -67
Sampling rate ≤ 5.33 Msps,
THD harmonic Fast channel (max speed) - -72 -71 dB
1.65 V ≤ VDDA = VREF+ ≤
distortion
3.6 V, Differential
Slow channel (max speed) - -72 -71
Voltage scaling Range 1
154/220 DS11421 Rev 5


Sym-
bol

Total ended Slow channel (max speed) - 4 5
ET unadjusted
Differential

ended Slow channel (max speed) - 2 4
Offset
EO
Differential

ended Slow channel (max speed) - 4 4.5
EG Gain error LSB
Fast channel (max speed) - 3 4
Differential
Slow channel (max speed) - 3 4

ED linearity
error ADC clock frequency ≤ Fast channel (max speed) - 1 1.2
1.65 V ≤ VDDA = VREF+ ≤
3.6 V, Single Fast channel (max speed) - 2.5 3
Integral Voltage scaling Range 2 ended Slow channel (max speed) - 2.5 3
EL linearity
Differential
Single Fast channel (max speed) 10.2 10.5 -

Effective ended Slow channel (max speed) 10.2 10.5 -
ENOB number of bits
Differential

Signal-to-
noise and
SINAD
distortion Fast channel (max speed) 65 66 -
ratio Differential
dB
Signal-to-
SNR
Differential
DS11421 Rev 5 155/220

185

Sym-
bol
THD harmonic 1.65 V ≤ VDDA = VREF+ ≤ dB
distortion 3.6 V, Fast channel (max speed) - -73 -72
Differential
Voltage scaling Range 2 Slow channel (max speed) - -73 -72
Figure 30. ADC accuracy characteristics
VSSA EG (1) Example of an actual transfer curve

4095
(2) The ideal transfer curve
4094 (3) End point correlation line
4093
(2)
ET = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
ET EO = offset error: maximum deviation
(3)
7 between the first actual transition and
(1)
6 the first ideal one.
EG = gain error: deviation between the last
5
EO EL
ideal transition and the last actual one.
4 ED = differential linearity error: maximum
3 deviation between actual steps and the ideal ones.
ED
EL = integral linearity error: maximum deviation
2
between any actual transition and the end point
1 LSB IDEAL
1 correlation line.
0
1 2 3 4 5 6 7 4093 4094 4095 4096 VDDA
MS19880V2
156/220 DS11421 Rev 5

Figure 31. Typical connection diagram using the ADC
VDDA
VT Sample and hold ADC converter
RAIN(1) AINx RADC

12-bit
converter
Cparasitic(2) VT Ilkg (3) CADC
VAIN
MS33900V5
1. Refer to Table 65: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 59: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 59: I/O static characteristics for the values of Ilkg.
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 17: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
DS11421 Rev 5 157/220

185
6.3.19 Digital-to-Analog converter characteristics
Table 71. DAC characteristics(1)

DAC output buffer OFF (no resistive

load on DAC1_OUTx pin or internal 1.71 -
Analog supply voltage for
VDDA connection) 3.6
DAC ON
Other modes 1.80 -
DAC output buffer OFF (no resistive

V
load on DAC1_OUTx pin or internal 1.71 -
VREF+ Positive reference voltage connection) VDDA
Other modes 1.80 -
Negative reference
VREF- - VSSA
voltage
DAC output connected to VSSA 5 - -

RL Resistive load kΩ
buffer ON connected to VDDA 25 - -
RO Output Impedance DAC output buffer OFF 9.6 11.7 13.8 kΩ
Output impedance sample VDD = 2.7 V - - 2
RBON and hold mode, output kΩ
buffer ON VDD = 2.0 V - - 3.5
Output impedance sample VDD = 2.7 V - - 16.5

RBOFF and hold mode, output kΩ
buffer OFF VDD = 2.0 V - - 18.0
CL DAC output buffer ON - - 50 pF

Capacitive load
CSH Sample and hold mode - 0.1 1 µF
VREF+
Voltage on DAC1_OUTx DAC output buffer ON 0.2 -
VDAC_OUT – 0.2 V
output
DAC output buffer OFF 0 - VREF+
±0.5 LSB - 1.7 3
Settling time (full scale: for Normal mode
a 12-bit code transition ±1 LSB - 1.6 2.9
DAC output
between the lowest and buffer ON ±2 LSB - 1.55 2.85
the highest input codes CL ≤ 50 pF,
tSETTLING ±4 LSB - 1.48 2.8 µs
when DAC1_OUTx RL ≥ 5 kΩ
reaches final value ±8 LSB - 1.4 2.75
±0.5LSB, ±1 LSB, ±2 LSB,
±4 LSB, ±8 LSB) Normal mode DAC output buffer
- 2 2.5
OFF, ±1LSB, CL = 10 pF
Wakeup time from off state Normal mode DAC output buffer ON
- 4.2 7.5
(setting the ENx bit in the CL ≤ 50 pF, RL ≥ 5 kΩ
tWAKEUP(2) µs
DAC Control register) until Normal mode DAC output buffer
final value ±1 LSB - 2 5
OFF, CL ≤ 10 pF
Normal mode DAC output buffer ON
PSRR VDDA supply rejection ratio - -80 -28 dB
CL ≤ 50 pF, RL = 5 kΩ, DC
158/220 DS11421 Rev 5

Table 71. DAC characteristics(1) (continued)

Minimal time between two

consecutive writes into the
DAC_DORx register to
guarantee a correct
DAC1_OUTx for a small
TW_to_W variation of the input code - - µs
(1 LSB)
DAC_MCR:MODEx[2:0] =
000 or 001 CL ≤ 50 pF, RL ≥ 5 kΩ 1
DAC_MCR:MODEx[2:0] =
010 or 011 CL ≤ 10 pF 1.4
DAC output buffer
- 0.7 3.5
DAC1_OUTx ON, CSH = 100 nF
Sampling time in sample ms
pin connected DAC output buffer
and hold mode (code - 10.5 18
OFF, CSH = 100 nF
transition between the
tSAMP lowest input code and the DAC1_OUTx
highest input code when pin not
DAC1_OUTx reaches final connected DAC output buffer
- 2 3.5 µs
value ±1LSB) (internal OFF
connection
only)
Sample and hold mode,
Ileak Output leakage current - - -(3) nA
DAC1_OUTx pin connected
Internal sample and hold
CIint - 5.2 7 8.8 pF
capacitor
Middle code offset trim
tTRIM DAC output buffer ON 50 - - µs
time
Middle code offset for 1 VREF+ = 3.6 V - 1500 -

Voffset µV
trim code step VREF+ = 1.8 V - 750 -
No load, middle
- 315 500
DAC output code (0x800)
buffer ON No load, worst code
- 450 670
(0xF1C)
DAC consumption from DAC output No load, middle
IDDA(DAC) - - 0.2 µA
VDDA buffer OFF code (0x800)
315 ₓ 670 ₓ
Sample and hold mode, CSH = Ton/(Ton Ton/(Ton
-
100 nF +Toff) +Toff)
(4) (4)
DS11421 Rev 5 159/220

185
Table 71. DAC characteristics(1) (continued)

No load, middle
- 185 240
DAC output code (0x800)
buffer ON No load, worst code
- 340 400
(0xF1C)
DAC output No load, middle
- 155 205
buffer OFF code (0x800)
DAC consumption from
IDDV(DAC) 185 ₓ 400 ₓ µA
VREF+
Sample and hold mode, buffer ON, Ton/(Ton Ton/(Ton
-
CSH = 100 nF, worst case +Toff) +Toff)
(4) (4)
155 ₓ 205 ₓ
Sample and hold mode, buffer OFF, Ton/(Ton Ton/(Ton
-
CSH = 100 nF, worst case +Toff) +Toff)
(4) (4)
2. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
3. Refer to Table 59: I/O static characteristics.
4. Ton is the Refresh phase duration. Toff is the Hold phase duration. Refer to RM0394 reference manual for more details.
Figure 32. 12-bit buffered / non-buffered DAC
Buffered/non-buffered DAC
(1)
Buffer
RLOAD
12-bit
DACx_OUT
digital to
analog
converter
CLOAD
ai17157d
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
160/220 DS11421 Rev 5

Table 72. DAC accuracy(1)

.
Differential non DAC output buffer ON - - ±2

DNL
linearity (2) DAC output buffer OFF - - ±2
- monotonicity 10 bits guaranteed
DAC output buffer ON
- - ±4
Integral non CL ≤ 50 pF, RL ≥ 5 kΩ
INL
linearity(3) DAC output buffer OFF
- - ±4
CL ≤ 50 pF, no RL
VREF+ = 3.6 V - - ±12

CL ≤ 50 pF, RL ≥ 5 kΩ LSB
Offset error at
Offset VREF+ = 1.8 V - - ±25
code 0x800(3)
DAC output buffer OFF
- - ±8
CL ≤ 50 pF, no RL
Offset error at DAC output buffer OFF
Offset1 - - ±5
code 0x001(4) CL ≤ 50 pF, no RL
Offset Error at VREF+ = 3.6 V - - ±5

OffsetCal code 0x800
CL ≤ 50 pF, RL ≥ 5 kΩ
after calibration VREF+ = 1.8 V - - ±7

- - ±0.5
CL ≤ 50 pF, RL ≥ 5 kΩ
(5)
Gain Gain error %
DAC output buffer OFF
- - ±0.5
CL ≤ 50 pF, no RL
Total - - ±30
CL ≤ 50 pF, RL ≥ 5 kΩ
TUE unadjusted LSB
error DAC output buffer OFF
- - ±12
CL ≤ 50 pF, no RL
Total
unadjusted DAC output buffer ON
TUECal - - ±23 LSB
error after CL ≤ 50 pF, RL ≥ 5 kΩ
calibration
CL ≤ 50 pF, RL ≥ 5 kΩ - 71.2 -
Signal-to-noise 1 kHz, BW 500 kHz
SNR dB
ratio DAC output buffer OFF
CL ≤ 50 pF, no RL, 1 kHz - 71.6 -
BW 500 kHz
- -78 -
Total harmonic CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
THD dB
distortion DAC output buffer OFF
- -79 -
CL ≤ 50 pF, no RL, 1 kHz
DS11421 Rev 5 161/220

185
Table 72. DAC accuracy(1) (continued)


Signal-to-noise - 70.4 -
CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
SINAD and distortion dB
ratio DAC output buffer OFF
- 71 -
- 11.4 -
Effective CL ≤ 50 pF, RL ≥ 5 kΩ, 1 kHz
ENOB bits
number of bits DAC output buffer OFF
- 11.5 -
2. Difference between two consecutive codes - 1 LSB.
3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
4. Difference between the value measured at Code (0x001) and the ideal value.
5. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VREF+ – 0.2) V when buffer is ON.
162/220 DS11421 Rev 5

6.3.20 Voltage reference buffer characteristics
Table 73. VREFBUF characteristics(1)

VRS = 0 2.4 - 3.6

Normal mode
Analog supply VRS = 1 2.8 - 3.6
VDDA
voltage VRS = 0 1.65 - 2.4
Degraded mode(2)
VRS = 1 1.65 - 2.8
V
(3)
VRS = 0 2.046 2.048 2.049(3)
Normal mode
Voltage VRS = 1 2.498(3) 2.5 2.502(3)
VREFBUF_
reference
OUT output VRS = 0 VDDA-150 mV - VDDA
Degraded mode(2)
VRS = 1 VDDA-150 mV - VDDA
Trim step
TRIM - - - ±0.05 ±0.1 %
resolution
CL Load capacitor - - 0.5 1 1.5 µF
Equivalent
esr Serial Resistor - - - - 2 Ω
of Cload
Static load
Iload - - - - 4 mA
current
Iload = 500 µA - 200 1000
Iline_reg Line regulation 2.8 V ≤ VDDA ≤ 3.6 V ppm/V
Iload = 4 mA - 100 500
Load
Iload_reg 500 μA ≤ Iload ≤4 mA Normal mode - 50 500 ppm/mA
regulation
Tcoeff_
-40 °C < TJ < +125 °C - - vrefint +
Temperature 50
TCoeff ppm/ °C
coefficient Tcoeff_
0 °C < TJ < +50 °C - - vrefint +
50
Power supply DC 40 60 -
PSRR dB
rejection 100 kHz 25 40 -
CL = 0.5 µF(4) - 300 350
tSTART Start-up time CL = 1.1 µF(4) - 500 650 µs
(4)
CL = 1.5 µF - 650 800
Control of
maximum DC
current drive
IINRUSH on VREFBUF_ - - - 8 - mA
OUT during
start-up phase
(5)
DS11421 Rev 5 163/220

185
Table 73. VREFBUF characteristics(1) (continued)

Iload = 0 µA - 16 25
VREFBUF
IDDA(VREF
consumption Iload = 500 µA - 18 30 µA
BUF)
from VDDA
Iload = 4 mA - 35 50
1. Guaranteed by design, unless otherwise specified.
2. In degraded mode, the voltage reference buffer can not maintain accurately the output voltage which will follow (VDDA -
drop voltage).
4. The capacitive load must include a 100 nF capacitor in order to cut-off the high frequency noise.
5. To correctly control the VREFBUF inrush current during start-up phase and scaling change, the VDDA voltage should be in
the range [2.4 V to 3.6 V] and [2.8 V to 3.6 V] respectively for VRS = 0 and VRS = 1.
164/220 DS11421 Rev 5

6.3.21 Comparator characteristics
Table 74. COMP characteristics(1)

VDDA Analog supply voltage - 1.62 - 3.6

Comparator input voltage
VIN - 0 - VDDA V
range
VBG(2) Scaler input voltage - VREFINT
VSC Scaler offset voltage - - ±5 ±10 mV
Scaler static consumption BRG_EN=0 (bridge disable) - 200 300 nA

IDDA(SCALER)
from VDDA BRG_EN=1 (bridge enable) - 0.8 1 µA
tSTART_SCALER Scaler startup time - - 100 200 µs
High-speed VDDA ≥ 2.7 V - - 5

mode VDDA < 2.7 V - - 7
Comparator startup time to
tSTART reach propagation delay VDDA ≥ 2.7 V - - 15 µs
specification Medium mode
VDDA < 2.7 V - - 25
Ultra-low-power mode - - 40
High-speed VDDA ≥ 2.7 V - 55 80

ns
mode VDDA < 2.7 V - 65 100
(3) Propagation delay with
tD
100 mV overdrive Medium mode - 0.55 0.9
µs
Ultra-low-power mode - 4 7
Full common
Voffset Comparator offset error - - ±5 ±20 mV
mode range
No hysteresis - 0 -
Low hysteresis - 8 -
Vhys Comparator hysteresis mV
Medium hysteresis - 15 -
High hysteresis - 27 -
DS11421 Rev 5 165/220

185
Table 74. COMP characteristics(1) (continued)

Static - 400 600

Ultra-low- With 50 kHz nA
power mode ±100 mV overdrive - 1200 -
square signal
Static - 5 7
Comparator consumption
IDDA(COMP) Medium mode With 50 kHz
from VDDA ±100 mV overdrive - 6 -
square signal
µA
Static - 70 100
High-speed With 50 kHz
mode ±100 mV overdrive - 75 -
square signal
Comparator input bias - - - -(4)

Ibias nA
current
2. Refer to Table 24: Embedded internal voltage reference.
4. Mostly I/O leakage when used in analog mode. Refer to Ilkg parameter in Table 59: I/O static characteristics.
6.3.22 Operational amplifiers characteristics
Table 75. OPAMP characteristics(1)

Analog supply
VDDA - 1.8 - 3.6 V
voltage(2)
Common mode
CMIR - 0 - VDDA V
input range
Input offset 25 °C, No Load on output. - - ±1.5

VIOFFSET mV
voltage All voltage/Temp. - - ±3
Input offset Normal mode - ±5 -

∆VIOFFSET μV/°C
voltage drift Low-power mode - ±10 -
Offset trim step
TRIMOFFSETP at low common
- - 0.8 1.1
TRIMLPOFFSETP input voltage
(0.1 ₓ VDDA)
mV
Offset trim step
TRIMOFFSETN at high common
- - 1 1.35
TRIMLPOFFSETN input voltage
(0.9 ₓ VDDA)
166/220 DS11421 Rev 5

Table 75. OPAMP characteristics(1) (continued)

Normal mode - - 500

ILOAD Drive current VDDA ≥ 2 V
Low-power mode - - 100
µA
Drive current in Normal mode - - 450
ILOAD_PGA VDDA ≥ 2 V
PGA mode Low-power mode - - 50
Resistive load Normal mode 4 - -

(connected to
RLOAD VDDA < 2 V
VSSA or to
VDDA) Low-power mode 20 - -
kΩ
Resistive load
Normal mode 4.5 - -
in PGA mode
RLOAD_PGA (connected to VDDA < 2 V
VSSA or to
Low-power mode 40 - -
VDDA)
CLOAD Capacitive load - - - 50 pF
Common mode Normal mode - -85 -

CMRR dB
rejection ratio Low-power mode - -90 -
CLOAD ≤ 50 pf,
Normal mode 70 85 -
Power supply RLOAD ≥ 4 kΩ DC
PSRR dB
rejection ratio CLOAD ≤ 50 pf,
Low-power mode 72 90 -
RLOAD ≥ 20 kΩ DC
Normal mode VDDA ≥ 2.4 V 550 1600 2200
(OPA_RANGE = 1)
Gain Bandwidth Low-power mode 100 420 600
GBW kHz
Product Normal mode 250 700 950
VDDA < 2.4 V
Low-power mode (OPA_RANGE = 0) 40 180 280
Normal mode - 700 -
Slew rate VDDA ≥ 2.4 V
(from 10 and Low-power mode - 180 -
SR(3) V/ms
90% of output Normal mode - 300 -
voltage) VDDA < 2.4 V
Low-power mode - 80 -
Normal mode 55 110 -
AO Open loop gain dB
Low-power mode 45 110 -
VDDA -
Normal mode - -
High saturation Iload = max or Rload = 100
VOHSAT(3)
voltage min Input at VDDA. VDDA -
Low-power mode - - mV
50
Low saturation Normal mode Iload = max or Rload = - - 100

VOLSAT(3)
voltage Low-power mode min Input at 0. - - 50
Normal mode - 74 -
φm Phase margin °
DS11421 Rev 5 167/220

185

Normal mode - 13 -
GM Gain margin dB
CLOAD ≤ 50 pf,
RLOAD ≥ 4 kΩ
Normal mode - 5 10
follower
Wake up time configuration
tWAKEUP µs
from OFF state. CLOAD ≤ 50 pf,
RLOAD ≥ 20 kΩ
Low-power mode - 10 30
follower
configuration
OPAMP input
Ibias General purpose input - - -(4) nA
bias current
- 2 -
Non inverting - 4 -
PGA gain(3) - -
gain value - 8 -
- 16 -
PGA Gain = 2 - 80/80 -
120/
R2/R1 internal PGA Gain = 4 - -
40
resistance
Rnetwork 140/ kΩ/kΩ
values in PGA PGA Gain = 8 - -
mode(5) 20
150/
PGA Gain = 16 - -
10
Resistance
Delta R variation (R1 or - -15 - 15 %
R2)
PGA gain error PGA gain error - -1 - 1 %
GBW/
Gain = 2 - - -
2
GBW/
PGA bandwidth Gain = 4 - -
4
-
PGA BW for different non MHz
inverting gain GBW/
Gain = 8 - - -
8
GBW/
Gain = 16 - - -
16
168/220 DS11421 Rev 5


at 1 kHz, Output
Normal mode - 500 -
loaded with 4 kΩ
at 1 kHz, Output
Voltage noise loaded with 20 kΩ
en nV/√Hz
density at 10 kHz, Output
Normal mode - 180 -
loaded with 4 kΩ
at 10 kHz, Output
loaded with 20 kΩ
OPAMP Normal mode - 120 260
no Load, quiescent
IDDA(OPAMP)(3) consumption µA
Low-power mode mode - 45 100
from VDDA
2. The temperature range is limited to 0 °C-125 °C when VDDA is below 2 V
4. Mostly I/O leakage, when used in analog mode. Refer to Ilkg parameter in Table 59: I/O static characteristics.
5. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between
OPAMP inverting input and ground. The PGA gain =1+R2/R1
6.3.23 Temperature sensor characteristics
Table 76. TS characteristics

TL(1) VTS linearity with temperature - ±1 ±2 °C

(2)
Avg_Slope Average slope 2.3 2.5 2.7 mV/°C
V30 Voltage at 30°C (±5 °C)(3) 0.742 0.76 0.785 V
tSTART
Sensor Buffer Start-up time in continuous mode(4) - 8 15 µs
(TS_BUF)(1)
tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs
tS_temp(1) ADC sampling time when reading the temperature 5 - - µs
Temperature sensor consumption from VDD, when

IDD(TS)(1) - 4.7 7 µA
selected by ADC
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 7:
Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
DS11421 Rev 5 169/220

185
6.3.24 VBAT monitoring characteristics
Table 77. VBAT monitoring characteristics

R Resistor bridge for VBAT - 39 - kΩ

Q Ratio on VBAT measurement - 3 - -
(1)
Er Error on Q -10 - 10 %
(1)
tS_vbat ADC sampling time when reading the VBAT 12 - - µs
Table 78. VBAT charging characteristics

Battery VBRS = 0 - 5 -
RBC charging kΩ
resistor VBRS = 1 - 1.5 -
170/220 DS11421 Rev 5

6.3.25 LCD controller characteristics

The devices embed a built-in step-up converter to provide a constant LCD reference voltage
independently from the VDD voltage. An external capacitor Cext must be connected to the
VLCD pin to decouple this converter.
Table 79. LCD controller characteristics(1)
VLCD LCD external voltage - - 3.6

VLCD0 LCD internal reference voltage 0 - 2.62 -
VLCD3 LCD internal reference voltage 3 - 3.04 - V
Buffer OFF
0.2 - 2
(BUFEN=0 is LCD_CR register)
Cext VLCD external capacitance μF
Buffer ON
1 - 2
(BUFEN=1 is LCD_CR register)
Supply current from VDD at Buffer OFF
- 3 -
VDD = 2.2 V (BUFEN=0 is LCD_CR register)
(2)
ILCD μA
Supply current from VDD at Buffer OFF
- 1.5 -
VDD = 3.0 V (BUFEN=0 is LCD_CR register)
Buffer OFF
- 0.5 -
(BUFFEN = 0, PON = 0)
Buffer ON
- 0.6 -
Supply current from VLCD (BUFFEN = 1, 1/2 Bias)
IVLCD μA
(VLCD = 3 V) Buffer ON
- 0.8 -
(BUFFEN = 1, 1/3 Bias)
Buffer ON
- 1 -
(BUFFEN = 1, 1/4 Bias)
RHN Total High Resistor value for Low drive resistive network - 5.5 - MΩ
RLN Total Low Resistor value for High drive resistive network - 240 - kΩ
V44 Segment/Common highest level voltage - VLCD -
V34 Segment/Common 3/4 level voltage - 3/4 VLCD -
V12 Segment/Common 1/2 level voltage - 1/2 VLCD - V
V0 Segment/Common lowest level voltage - 0 -
DS11421 Rev 5 171/220

185
2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected.
6.3.26 Timer characteristics

The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 80. TIMx(1) characteristics

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 80 MHz 12.5 - ns
Timer external clock - 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 f
TIMxCLK = 80 MHz 0 40 MHz
TIMx (except
- 16
ResTIM Timer resolution TIM2) bit
TIM2 - 32
16-bit counter clock - 1 65536 tTIMxCLK

tCOUNTER
period fTIMxCLK = 80 MHz 0.0125 819.2 µs
Maximum possible count - - 65536 × 65536 tTIMxCLK

tMAX_COUNT
with 32-bit counter fTIMxCLK = 80 MHz - 53.68 s
1. TIMx, is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17.
Table 81. IWDG min/max timeout period at 32 kHz (LSI)(1)

Min timeout RL[11:0]= Max timeout RL[11:0]=
Prescaler divider PR[2:0] bits Unit
0x000 0xFFF
/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
172/220 DS11421 Rev 5

Table 82. WWDG min/max timeout value at 80 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0512 3.2768
2 1 0.1024 6.5536
ms
4 2 0.2048 13.1072
8 3 0.4096 26.2144
6.3.27 Communication interfaces characteristics

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0394 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 83. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit
Maximum pulse width of spikes

tAF that are suppressed by the analog 50(2) 260(3) ns
filter
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
DS11421 Rev 5 173/220

185
SPI characteristics
Unless otherwise specified, the parameters given in Table 84 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 21: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 84. SPI characteristics(1)

Master mode receiver/full duplex

2.7 < VDD < 3.6 V 40
Voltage Range 1
Master mode receiver/full duplex
1.71 < VDD < 3.6 V 16
Voltage Range 1
Master mode transmitter
1.71 < VDD < 3.6 V 40
Voltage Range 1
fSCK
SPI clock frequency Slave mode receiver - - MHz
1/tc(SCK)
1.71 < VDD < 3.6 V 40
Voltage Range 1
Slave mode transmitter/full duplex
2.7 < VDD < 3.6 V 37(2)
Voltage Range 1
Slave mode transmitter/full duplex
1.71 < VDD < 3.6 V 20(2)
Voltage Range 1
Voltage Range 2 13
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4ₓTPCLK - - ns
th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2ₓTPCLK - - ns
tw(SCKH)
SCK high and low time Master mode TPCLK-2 TPCLK TPCLK+2 ns
tw(SCKL)
tsu(MI) Master mode 4 - -
Data input setup time ns
tsu(SI) Slave mode 1.5 - -
th(MI) Master mode 6.5 - -
Data input hold time ns
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time Slave mode 9 - 36 ns
tdis(SO) Data output disable time Slave mode 9 - 16 ns
174/220 DS11421 Rev 5

Table 84. SPI characteristics(1) (continued)

Slave mode 2.7 < VDD < 3.6 V

- 12.5 13.5
Voltage Range 1
tv(SO) - 12.5 24
Data output valid time Voltage Range 1 ns
- 12.5 33
Voltage Range 2
tv(MO) Master mode - 4.5 6
th(SO) Slave mode 7 - -
Data output hold time ns
th(MO) Master mode 0 - -
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.
Figure 33. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
DS11421 Rev 5 175/220

185
Figure 34. SPI timing diagram - slave mode and CPHA = 1

NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V1
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Figure 35. SPI timing diagram - master mode
High
NSS input
tc(SCK)
SCK Output
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
MSB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136c
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
176/220 DS11421 Rev 5

Quad SPI characteristics

Unless otherwise specified, the parameters given in Table 85 and Table 86 for Quad SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 21: General operating conditions, with the
following configuration:
• Capacitive load C = 15 or 20 pF
function characteristics.
Table 85. Quad SPI characteristics in SDR mode(1)

1.71 < VDD< 3.6 V, CLOAD = 20 pF

- - 40
Voltage Range 1
1.71 < VDD< 3.6 V, CLOAD = 15 pF
- - 48
FCK Voltage Range 1
Quad SPI clock frequency MHz
1/t(CK) 2.7 < VDD< 3.6 V, CLOAD = 15 pF
- - 60
Voltage Range 1
1.71 < VDD < 3.6 V CLOAD = 20 pF
- - 26
Voltage Range 2
tw(CKH) Quad SPI clock high and t(CK)/2-2 - t(CK)/2
fAHBCLK= 48 MHz, presc=0
tw(CKL) low time t(CK)/2 - t(CK)/2+2
Voltage Range 1 2 - -
ts(IN) Data input setup time
Voltage Range 2 3.5 - -
th(IN) Data input hold time ns
Voltage Range 2 6.5 - -
Voltage Range 1 - 1 5
tv(OUT) Data output valid time
Voltage Range 2 - 3 5
th(OUT) Data output hold time
DS11421 Rev 5 177/220

185
Table 86. QUADSPI characteristics in DDR mode(1)

1.71 < VDD < 3.6 V, CLOAD = 20 pF

- - 40
Voltage Range 1
2 < VDD < 3.6 V, CLOAD = 20 pF
- - 48
FCK Quad SPI clock Voltage Range 1
MHz
1/t(CK) frequency 1.71 < VDD < 3.6 V, CLOAD = 15 pF
- - 48
Voltage Range 1
1.71 < VDD < 3.6 V CLOAD = 20 pF
- - 26
Voltage Range 2
tw(CKH) Quad SPI clock high t(CK)/2-2 - t(CK)/2
fAHBCLK = 48 MHz, presc=0
tw(CKL) and low time t(CK)/2 - t(CK)/2+2
Data input setup time Voltage Range 1 1

tsr(IN) - -
on rising edge Voltage Range 2 3.5
Data input setup time Voltage Range 1 1

tsf(IN) - -
on falling edge Voltage Range 2 1.5
Data input hold time Voltage Range 1 6

thr(IN) - -
on rising edge Voltage Range 2 6.5
Data input hold time Voltage Range 1 5.5

thf(IN) - - ns
on falling edge Voltage Range 2 5.5
Data output valid time Voltage Range 1 5 5.5

tvr(OUT) -
on rising edge Voltage Range 2 9.5 14
Data output valid time Voltage Range 1 5 8.5

tvf(OUT) -
on falling edge Voltage Range 2 15 19
Data output hold time Voltage Range 1 3.5 -

thr(OUT) -
on rising edge Voltage Range 2 8 -
Data output hold time Voltage Range 1 3.5 -

thf(OUT) -
on falling edge Voltage Range 2 13 -
178/220 DS11421 Rev 5

Figure 36. Quad SPI timing diagram - SDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V1
Figure 37. Quad SPI timing diagram - DDR mode

tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output IO0 IO1 IO2 IO3 IO4 IO5
tsf(IN) thf(IN) tsr(IN) thr(IN)
Data input IO0 IO1 IO2 IO3 IO4 IO5

MSv36879V3
DS11421 Rev 5 179/220

185
SAI characteristics
Unless otherwise specified, the parameters given in Table 87 for SAI are derived
from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized inTable 21: General operating conditions, with
the following configuration:
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output
alternate function characteristics (CK,SD,FS).
Table 87. SAI characteristics(1)

fMCLK SAI Main clock output - - 50 MHz

Master transmitter
2.7 ≤ VDD ≤ 3.6 - 18.5
Voltage Range 1
Master transmitter
1.71 ≤ VDD ≤ 3.6 - 12.5
Voltage Range 1
Master receiver
- 25
Voltage Range 1
fCK SAI clock frequency(2) Slave transmitter MHz
2.7 ≤ VDD ≤ 3.6 - 22.5
Voltage Range 1
Slave transmitter
1.71 ≤ VDD ≤ 3.6 - 14.5
Voltage Range 1
Slave receiver
- 25
Voltage Range 1
Voltage Range 2 - 12.5
Master mode
- 22
2.7 ≤ VDD ≤ 3.6
tv(FS) FS valid time ns
Master mode
- 40
1.71 ≤ VDD ≤ 3.6
th(FS) FS hold time Master mode 10 - ns
tsu(FS) FS setup time Slave mode 1 - ns
th(FS) FS hold time Slave mode 2 - ns
tsu(SD_A_MR) Master receiver 2 -
Data input setup time ns
tsu(SD_B_SR) Slave receiver 1.5 -
th(SD_A_MR) Master receiver 5 -
Data input hold time ns
th(SD_B_SR) Slave receiver 2.5 -
180/220 DS11421 Rev 5

Table 87. SAI characteristics(1) (continued)

Slave transmitter (after enable edge)

- 22
2.7 ≤ VDD ≤ 3.6
tv(SD_B_ST) Data output valid time ns
Slave transmitter (after enable edge)
- 34
1.71 ≤ VDD ≤ 3.6
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 10 - ns
Master transmitter (after enable edge)
- 27
2.7 ≤ VDD ≤ 3.6
tv(SD_A_MT) Data output valid time ns
Master transmitter (after enable edge)
- 40
1.71 ≤ VDD ≤ 3.6
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 10 - ns
2. APB clock frequency must be at least twice SAI clock frequency.
Figure 38. SAI master timing waveforms

1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)
SAI_SD_X Slot n
(receive)
MS32771V1
DS11421 Rev 5 181/220

185
Figure 39. SAI slave timing waveforms
1/fSCK
SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X Slot n
(receive)
MS32772V1
SDMMC characteristics
Unless otherwise specified, the parameters given in Table 88 for SDIO are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 21: General operating conditions, with the following
configuration:
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output
characteristics.
Table 88. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1)

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 4/3 -
tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns
tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU Input setup time HS fPP = 50 MHz 3.5 - - ns
tIH Input hold time HS fPP = 50 MHz 2.5 - - ns
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV Output valid time HS fPP = 50 MHz - 12 13 ns
tOH Output hold time HS fPP = 50 MHz 10 - - ns
CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD fPP = 50 MHz 3.5 - - ns
tIHD Input hold time SD fPP = 50 MHz 3 - - ns
182/220 DS11421 Rev 5

Table 88. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V(1) (continued)

CMD, D outputs (referenced to CK) in SD default mode

tOVD Output valid default time SD fPP = 50 MHz - 2 3 ns
tOHD Output hold default time SD fPP = 50 MHz 0 - - ns
Table 89. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V(1)(2)

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDIO_CK/fPCLK2 frequency ratio - - - 4/3 -
tW(CKL) Clock low time fPP = 50 MHz 8 10 - ns
tW(CKH) Clock high time fPP = 50 MHz 8 10 - ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS fPP = 50 MHz 0 - - ns
tIH Input hold time HS fPP = 50 MHz 1.5 - - ns
CMD, D outputs (referenced to CK) in eMMC mode
tOV Output valid time HS fPP = 50 MHz - 13.5 15 ns
tOH Output hold time HS fPP = 50 MHz 9 - - ns
2. CLOAD = 20pF.
Figure 40. SDIO high-speed mode
DS11421 Rev 5 183/220

185
Figure 41. SD default mode
CK
tOVD tOHD
D, CMD
(output)
ai14888
USB characteristics
The STM32L443xx USB interface is fully compliant with the USB specification version 2.0
and is USB-IF certified (for Full-speed device operation).
Table 90. USB electrical characteristics(1)

VDDUSB USB transceiver operating voltage 3.0(2) - 3.6 V

Tcrystal_less USB crystal less operation temperature -15 - 85 °C
tSTARTUP(3) USB transceiver startup time - - 1.0 µs

RPUI Embedded USB_DP pull-up value during idle 900 1250 1600
Embedded USB_DP pull-up value during Ω
RPUR 1400 2300 3200
reception
Driving high
ZDRV(3) Output driver impedance(4) 28 36 44 Ω
and low
1. TA = -40 to 125 °C unless otherwise specified.
2. The STM32L443xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics
which are degraded in the 2.7-to-3.0 V voltage range.
4. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
CAN (controller area network) interface

function characteristics (CAN_TX and CAN_RX).
184/220 DS11421 Rev 5

SWPMI characteristics
The Single Wire Protocol Master Interface (SWPMI) and the associated SWPMI_IO
transceiver are compliant with the ETSI TS 102 613 technical specification.
Table 91. SWPMI electrical characteristics

SWP Class B
tSWPSTART SWPMI regulator startup time - - 300 μs
2.7 V ≤ VDD ≤ 3,3V
VCORE voltage range 1 500 - -
tSWPBIT SWP bit duration ns
VCORE voltage range 2 620 - -
DS11421 Rev 5 185/220

185
Package information STM32L443CC STM32L443RC STM32L443VC
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1 LQFP100 package information

Figure 42. LQFP - 100 pins, 14 x 14 mm low-profile quad flat package outline
SEATING PLANE
C
0.25 mm
A2
A
A1
c
GAUGE PLANE
ccc C
A1
K
L
D1
L1
D3
75 51
76 50
b
E1
E3
100 26
PIN 1 1 25
IDENTIFICATION
e 1L_ME_V5
1. Drawing is not to scale.
186/220 DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC Package information

mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DS11421 Rev 5 187/220

216
Figure 43. LQFP - 100 pins, 14 x 14 mm low-profile quad flat

recommended footprint
75 51
76 50
0.5
0.3
16.7 14.3
100 26
1.2
1 25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
188/220 DS11421 Rev 5

Figure 44. LQFP100 marking (package top view)
Product identification(1)
STM32L443 Optional gate mark
VCT6 A Revision code
Date code
Y WW
Pin 1
indentifier
MSv40126V1
1. Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS11421 Rev 5 189/220

216
7.2 UFBGA100 package information

Figure 45. UFBGA - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package outline
Z Seating plane
ddd Z
A4 A3 A2 A1 A
E1 X
A1 ball A1 ball
identifier index area E
e Z
A
Z
D1 D
e
Y
M
12 1
BOTTOM VIEW Øb (100 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z
A0C2_ME_V5
array package mechanical data
Symbol
Min. Typ. Max. Min. Typ. Max.
A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 0.0094
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 6.850 7.000 7.150 0.2697 0.2756 0.2815
D1 - 5.500 - - 0.2165 -
E 6.850 7.000 7.150 0.2697 0.2756 0.2815
E1 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
Z - 0.750 - - 0.0295 -
190/220 DS11421 Rev 5

array package mechanical data (continued)
Symbol
Min. Typ. Max. Min. Typ. Max.
ddd - - 0.080 - - 0.0031

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
Figure 46. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid
array package recommended footprint
Dpad
Dsm
A0C2_FP_V1
Table 94. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA)
Dimension Recommended values
Pitch 0.5
Dpad 0.280 mm
0.370 mm typ. (depends on the solder mask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
DS11421 Rev 5 191/220

216
Figure 47. UFBGA100 marking (package top view)
STM32L
443VCI6
Y WW Date code
Pin 1 identifier
A
MSv40917V1
192/220 DS11421 Rev 5


SEATING PLANE
C
A2
A
0.25 mm
GAUGE PLANE
A1
c
ccc C
A1
D K
D1 L
D3 L1
48 33
32
49
E1
E3
E
64 17
PIN 1 1 16
IDENTIFICATION e
5W_ME_V3

package mechanical data
Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -
DS11421 Rev 5 193/220

216

package mechanical data (continued)
Symbol
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031

48 33
0.3
49 0.5 32
12.7
10.3
10.3
64 17
1.2
1 16
7.8
12.7
ai14909c
Device marking
location.
194/220 DS11421 Rev 5

Revision code
Product identification(1) A
STM32L
443RCT6
Y WW Date code
Pin 1 identifier
MSv40131V1
7.4 UFBGA64 package information

Figure 51. UFBGA – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package outline
Z Seating plane
ddd Z
A4
A3 A2 A1 A
E1 A1 ball A1 ball X
identifier index area E
e F
A
F
D1 D
e
H Y
8 1
BOTTOM VIEW Øb (64 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z A019_ME_V1
DS11421 Rev 5 195/220

216
Table 96. UFBGA – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array
Symbol
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 0.080 0.130 0.180 0.0031 0.0051 0.0071
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.170 0.280 0.330 0.0067 0.0110 0.0130
D 4.850 5.000 5.150 0.1909 0.1969 0.2028
D1 3.450 3.500 3.550 0.1358 0.1378 0.1398
E 4.850 5.000 5.150 0.1909 0.1969 0.2028
E1 3.450 3.500 3.550 0.1358 0.1378 0.1398
e - 0.500 - - 0.0197 -
F 0.700 0.750 0.800 0.0276 0.0295 0.0315
ddd - - 0.080 - - 0.0031
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
Figure 52. UFBGA64 – 64 balls, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid
array package recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
196/220 DS11421 Rev 5

Table 97. UFBGA64 recommended PCB design rules (0.5 mm pitch BGA)
Pitch 0.5
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask
Dsm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Device marking
location.
Figure 53. UFBGA64 marking (package top view)
Product identification(1) 32L443C6
Y WW Date code
A
Pin 1 identifier
MSv40920V1
DS11421 Rev 5 197/220

216
7.5 STANDARD WLCSP64 package information

chip scale package outline
e1 bbb Z
F
G 8 1
A
Detail A
e2
e
H
G
A
e F A2
A3
Bump side Side view
Bump
A1
eee Z
E
A1 Orientation
b
reference Z
ccc Z X Y
ddd Z Seating plane
aaa
(4x)
Wafer back side Detail A

(rotated 90°)
WLCSP64_A064_ME_V1
chip scale package mechanical data
Symbol
A 0.516 0.546 0.576 0.0203 0.0215 0.0227
A1 - 0.166 - - 0.0065 -
A2 - 0.380 - - 0.0150 -
(2)
A3 - 0.025 - - 0.0010 -
198/220 DS11421 Rev 5

chip scale package mechanical data (continued)
Symbol
(3)
b 0.190 0.220 0.250 0.0075 0.0087 0.0098
D 3.106 3.141 3.176 0.1223 0.1237 0.1250
E 3.092 3.127 3.162 0.1217 0.1231 0.1245
e - 0.350 - - 0.0138 -
e1 - 2.450 - - 0.0965 -
e2 - 2.450 - - 0.0965 -
F - 0.3455 - - 0.0136 -
G - 0.3385 - - 0.0133 -
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
chip scale package recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
DS11421 Rev 5 199/220

216
Table 99. STANDARD WLCSP64 recommended PCB design rules

(0.35 mm pitch)
Pitch 0.35 mm
Dpad 0.210 mm
Dsm
Stencil thickness 0.100 mm
Device marking
location.
Figure 56. STANDARD WLCSP64 marking (package top view)
Pin 1 identifier
Product identification(1) L443RC6
Y WW A Revision code
Date code
MSv40134V1
200/220 DS11421 Rev 5

7.6 STANDARD WLCSP49 package information

chip scale package outline
e1 bbb Z
F
A1 ball location A1
G
Detail A
e2 E
e
e
A
D
A2
Bottom view
Bump side Side view
A3 A2
b
Bump
Front view
A1
eee Z
Z
b
E ccc ZXY
ddd Z
A1 Orientation Detail A Seating plane
reference (rotated 90°)
aaa
D (4x)
Top view
Wafer back side
WLCSP49_A04Z_ME_V1
DS11421 Rev 5 201/220

216
chip scale package mechanical data
Symbol
A 0.525 0.555 0.585 0.0207 0.0219 0.0230
A1 - 0.175 - - 0.0069 -
A2 - 0.380 - - 0.0150 -
(2)
A3 - 0.025 - - 0.0010 -
b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 3.106 3.141 3.176 0.1223 0.1237 0.1250
E 3.092 3.127 3.162 0.1217 0.1231 0.1245
e - 0.400 - - 0.0157 -
e1 - 2.400 - - 0.0945 -
e2 - 2.400 - - 0.0945 -
F - 0.3705 - - 0.0146 -
G - 0.3635 - - 0.0143 -
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
2. Back side coating
chip scale package recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
202/220 DS11421 Rev 5

Table 101. STANDARD WLCSP49 recommended PCB design rules (0.4 mm pitch)
Pitch 0.4
Dpad 0.225 mm
Dsm
Device marking
location.
Figure 59. STANDARD WLCSP49 marking (package top view)
Pin 1 identifier
Product identification(1) L443CCY
Y WW A Revision code
Date code
MSv40138V1
DS11421 Rev 5 203/220

216
7.7 THIN WLCSP49 package information

Figure 60. WLCSP - 49 balls, 3.14x 3.15 mm, 0.4 mm pitch, wafer level chip scale
package outline
A1 ORIENTATION REFERENCE
G
F bbb Z
e1 D
A1
DETAIL A
e2 E
e
A
e aaa
(4x) A2
BOTTOM VIEW TOP VIEW SIDE VIEW
BUMP
A3 A2
A1
b eee Z
FRONT VIEW
b(Nx) Z
ccc Z X Y
ddd Z
SEATING PLANE
DETAIL A
ROTATED 90
B06U_WLCSP49_DIE435_ME_V1

3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
mechanical data
Symbol
A(2) - - 0.33 - - 0.013

A1 - 0.09 - - 0.004 -
A2 - 0.20 - - 0.008 -
(3)
A3 - 0.025 - - 0.001 -
(4)
b 0.16 0.19 0.22 0.006 0.007 0.009
D 3.13 3.15 3.17 0.123 0.124 0.125
204/220 DS11421 Rev 5

mechanical data (continued)
Symbol
E 3.12 3.14 3.16 0.123 0.124 0.124

e - 0.40 - - 0.016 -
e1 - 2.40 - - 0.094 -
e2 - 2.40 - - 0.094 -
F(5) - 0.375 - - 0.015 -
(5)
G - 0.370 - - 0.015 -
aaa - 0.10 - - 0.004 -
bbb - 0.10 - - 0.004 -
ccc - 0.10 - - 0.004 -
ddd - 0.05 - - 0.002 -
eee - 0.05 - - 0.002 -
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
5. Calculated dimensions are rounded to the 3rd decimal place
Figure 61. THIN WLCSP - 49 balls, 3.14x 3.15 mm, 0.4 mm pitch, wafer level chip scale
Dpad
Dsm
BGA_WLCSP_FT_V1
DS11421 Rev 5 205/220

216
Table 103. THIN WLCSP49 recommended PCB design rules

Pitch 0.4 mm
Dpad 0,225 mm
Dsm 0.290 mm typ. (depends on soldermask registration tolerance)
Device marking
location.
Figure 62. THIN WLCSP49 marking (package top view)
Pin 1 identifier
Product identification(1) L443CF6
Y WW Z Revision code
Date code
MSv64419V1
206/220 DS11421 Rev 5


SEATING
PLANE
C
A2
A
A1
c
0.25 mm
GAUGE PLANE
ccc C
D K
A1
L
D1 L1
D3
36 25
37 24
E1
E3
E
48 13
PIN 1
IDENTIFICATION 1 12
e 5B_ME_V2
DS11421 Rev 5 207/220

216

mechanical data
Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
208/220 DS11421 Rev 5


0.50
1.20
0.30
36 25
37 24
0.20
7.30
9.70 5.80
7.30
48 13
1 12
1.20
5.80
9.70
ai14911d
Device marking
location.
DS11421 Rev 5 209/220

216
STM32L
443CCT6
Y WW Date code
Pin 1 identifier
A Revision code
MSv40142V1
210/220 DS11421 Rev 5

7.9 UFQFPN48 package information

package outline
Pin 1 identifier
laser marking area
D
A
E E
T Seating
plane
ddd A1
e b
Detail Y
D
Y
Exposed pad
area D2
1
L
48
C 0.500x45°
pin1 corner R 0.125 typ.
E2 Detail Z
48
Z
A0B9_ME_V3

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
DS11421 Rev 5 211/220

216
Table 105. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
package recommended footprint
7.30
6.20
48 37
1 36
0.20 5.60
7.30
5.80
6.20
5.60
0.30
12 25
13 24
0.50 0.75
0.55
5.80
A0B9_FP_V2
212/220 DS11421 Rev 5

Device marking
location.
Figure 68. UFQFPN48 marking (package top view)
STM32L
443CCU6
Y WW Date code
Pin 1 identifier
A Revision code
MSv40146V1
DS11421 Rev 5 213/220

216
7.10 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 21: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of all IDDXXX and VDDXXX, expressed in Watts. This is the
maximum chip internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ ((VDDIOx – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 106. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

33
UFQFPN48 - 7 × 7 mm / 0.5 mm pitch
57
LQFP48 - 7 × 7 mm / 0.5 mm pitch
48
WLCSP49 3.141 x 3.127 / 0.4 mm pitch
45
LQFP64 - 10 × 10 mm / 0.5 mm pitch
ΘJA °C/W
65
UFBGA64 - 5 × 5 mm / 0.5 mm pitch
46
WLCSP64 3.141 x 3.127 / 0.35 mm pitch
42
LQFP100 - 14 × 14 mm / 0.5 mm pitch
57
UFBGA100 - 7 × 7 mm / 0.5 mm pitch
7.10.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
214/220 DS11421 Rev 5

7.10.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32L443xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 106 TJmax is calculated as follows:
– For LQFP64, 46 °C/W
TJmax = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.562 °C = 102.562 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C) see Section 8:
Ordering information.
In this case, parts must be ordered at least with the temperature range suffix 6 (see Part
numbering).
Note: With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (46°C/W × 447 mW) = 105-20.562 = 84.438 °C
Suffix 7: TAmax = TJmax - (46°C/W × 447 mW) = 125-20.562 = 104.438 °C
Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
DS11421 Rev 5 215/220

216
Assuming the following application conditions:

Maximum ambient temperature TAmax = 100 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
Using the values obtained in Table 106 TJmax is calculated as follows:
– For LQFP64, 46 °C/W
TJmax = 100 °C + (46 °C/W × 134 mW) = 100 °C + 6.164 °C = 106.164 °C
This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
Refer to Figure 69 to select the required temperature range (suffix 6 or 7) according to your
ambient temperature or power requirements.
Figure 69. LQFP64 PD max vs. TA

700
600
500
PD (mW)
400 Suffix 6
300
Suffix 7
200
100
0
65 75 85 95 105 115 125 135
TA (°C) MSv32143V1
216/220 DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC Ordering information
8 Ordering information
Table 107. STM32L443xx ordering information scheme

Example: STM32 L 443 C C T 6 TR
Device family
STM32 = Arm® based 32-bit microcontroller
Product type
L = ultra-low-power
Device subfamily
443: STM32L443xx
Pin count
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size

C = 256 KB of Flash memory
Package
T = LQFP ECOPACK®2
U = QFN ECOPACK®2
I = UFBGA ECOPACK®2
Y = STANDARD WLCSP ECOPACK®2
F = THIN WLCSP ECOPACK®2
Temperature range
6 = Industrial temperature range, -40 to 85 °C (105 °C junction)
Packing
TR = tape and reel
xxx = programmed parts
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
DS11421 Rev 5 217/220

219
Revision history STM32L443CC STM32L443RC STM32L443VC
9 Revision history
Table 108. Document revision history

Date Revision Changes
08-Feb-2016 1 Initial release.

Updated document title.
Updated Table 1: STM32L443xx family device features
and peripheral counts.
Updated Section 3.15.3: VBAT battery voltage
monitoring.
Updated Section 3.27: Universal
synchronous/asynchronous receiver transmitter
(USART).
Updated Table 14: STM32L443xx pin definitions.
Updated Table 16: Alternate function AF8 to AF15.
Updated Table 18: Voltage characteristics.
Updated Table 21: General operating conditions.
Added Figure 19: VREFINT versus temperature.
Updated Table 23: Embedded reset and power control
block characteristics.
Updated Table 25 to Table 27 and Table 31 to Table 40.
Updated Table 40: Low-power mode wakeup timings.
23-May-2016 2
Added Table 42: Wakeup time using USART/LPUART.
Updated Table 48: MSI oscillator characteristics.
Added Table 49: HSI48 oscillator characteristics.
Added Figure 26: HSI48 frequency versus temperature.
Updated Table 51: PLL, PLLSAI1 characteristics.
Updated introduction of Section 6.3.14: I/O port
characteristics.
Added note to Figure 29: Recommended NRST pin
protection.
Updated Table 64: Analog switches booster
characteristics.
Updated Table 65: ADC characteristics.
Updated Table 73: VREFBUF characteristics.
Updated Table 74: COMP characteristics.
Updated Table 90: USB electrical characteristics.
Added Section : SWPMI characteristics.
Updated Table 106: Package thermal characteristics.
Added 1x LPUART on cover page.
Updated Reference Manual title when referring to
RM0394.
12-Jun-2017 3 Added Table 3: STM32L443xx modes overview.
Updated Table 5: STM32L443xx peripherals
interconnect matrix.
Added Section 3.24.5: Infrared interface (IRTIM).
218/220 DS11421 Rev 5

STM32L443CC STM32L443RC STM32L443VC Revision history
Table 108. Document revision history (continued)

Date Revision Changes
Updated baudrate in Section 3.27: Universal

synchronous/asynchronous receiver transmitter
(USART).
Updated Section 6.1.7: Current consumption
measurement.
Added footnote to Table 58: I/O current injection
susceptibility.
3
12-Jun-2017 Updated Table 59: I/O static characteristics.
(continued)
Updated Section 6.3.18: Analog-to-Digital converter
characteristics.
Added FADC min in Table 65: ADC characteristics.
Updated Table 71: DAC characteristics.
Added Ibias parameter in Table 74: COMP
characteristics.
Updated Section 7: Package information.
Updated DAC terminology in all the document for
clarification: single DAC instance (= DAC1) with 2 output
channels.
Added ECOPACK2® information in Features.
Updated Section 3.9.1: Power supply schemes.
Added Figure 3: Power-up/down sequence.
Updated Clock-out capability in Section 3.11: Clocks
and startup.
Updated Figure 4: Clock tree.
22-May-2018 4 Updated Section 3.14.1: Nested vectored interrupt
controller (NVIC).
Updated Section 6.3.2: Operating conditions at power-
up / power-down.
Updated ACoeff in Table 24: Embedded internal voltage
reference.
Updated Table 59: I/O static characteristics.
Added Section 6.3.16: Extended interrupt and event
controller input (EXTI) characteristics.
Updated Table 71: DAC characteristics.
Added THIN WLCSP in Features.
Updated Table 90: USB electrical characteristics
Updated Section 7.5: STANDARD WLCSP64 package
information.
29-Oct-2019 5 Updated Section 7.6: STANDARD WLCSP49 package
information.
Added Section 7.7: THIN WLCSP49 package
information.
updated Section 8: Ordering information.
DS11421 Rev 5 219/220

219
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
220/220 DS11421 Rev 5

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October 2019 DS11421 Rev 5 1/220

– 3x SPIs (and 1x Quad SPI) • True random number generator

2/220 DS11421 Rev 5

DS11421 Rev 5 3/220

3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4/220 DS11421 Rev 5

DS11421 Rev 5 5/220

6.3.26 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

6/220 DS11421 Rev 5

Table 1. STM32L443xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 14

DS11421 Rev 5 7/220

Table 43. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

8/220 DS11421 Rev 5

array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

DS11421 Rev 5 9/220

Figure 1. STM32L443xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10/220 DS11421 Rev 5

array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

DS11421 Rev 5 11/220

12/220 DS11421 Rev 5

DS11421 Rev 5 13/220

Table 1. STM32L443xx family device features and peripheral counts

Flash memory 256KB

14/220 DS11421 Rev 5

Table 1. STM32L443xx family device features and peripheral counts (continued)

Max. CPU frequency 80 MHz

DS11421 Rev 5 15/220

Figure 1. STM32L443xx block diagram

VDD Power management

XTAL OSC OSC_IN

CMD, CK as AF SDIO / MMC

OpAmp1 VOUT, VINM, VINP

RX, TX, CK,CTS, USART1

SAI1 VLCD = 2.5V to 3.6V

LCD 8x40 SEGx, COMx as AF

@ VDDA @ VDDA LPUART1 RX, TX, CTS, RTS as AF

INP, INM, OUT COMP1 IO

OUT1 OUT2 MSv39219V2

Note: AF: alternate function on I/O pins.

16/220 DS11421 Rev 5

3.1 Arm® Cortex®-M4 core with FPU

3.2 Adaptive real-time memory accelerator (ART Accelerator™)

3.3 Memory protection unit

DS11421 Rev 5 17/220

3.4 Embedded Flash memory

Main 1 Yes Yes Yes No No No

System 1 Yes No No Yes No No

Option 1 Yes Yes Yes Yes Yes Yes

18/220 DS11421 Rev 5

3.5 Embedded SRAM

DS11421 Rev 5 19/220

3.7 Boot modes

3.8 Cyclic redundancy check calculation unit (CRC)

3.9 Power supply management

3.9.1 Power supply schemes