STM 32 F 722 Re

STM32F722xx
STM32F723xx
Arm® Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 512KB Flash
256+16+4KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF
Datasheet - production data
Features
• Core: Arm® 32-bit Cortex®-M7 CPU with FPU,
adaptive real-time accelerator (ART
Accelerator) and L1-cache: 8 Kbytes of data
cache and 8 Kbytes of instruction cache, LQFP64 (10 × 10 mm) UFBGA144 (7 x 7 mm) WLCSP100
allowing 0-wait state execution from embedded LQFP100 (14 × 14 mm)
UFBGA176 (10 x 10 mm)
(0.4 mm pitch)
Flash memory and external memories, LQFP144 (20 × 20 mm)
frequency up to 216 MHz, MPU, LQFP176 (24 x 24 mm)
462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1)
and DSP instructions. – VBAT supply for RTC, 32×32 bit backup
• Memories registers + 4 Kbytes of backup SRAM
– Up to 512 Kbytes of Flash memory with • 3×12-bit, 2.4 MSPS ADC: up to 24 channels
protection mechanisms (read and write and 7.2 MSPS in triple interleaved mode
protections, proprietary code readout
• 2×12-bit D/A converters
protection (PCROP))
– 528 bytes of OTP memory • Up to 18 timers: up to thirteen 16-bit (1x low-
power 16-bit timer available in Stop mode) and
– SRAM: 256 Kbytes (including 64 Kbytes of
two 32-bit timers, each with up to 4
data TCM RAM for critical real-time data) +
IC/OC/PWMs or pulse counter and quadrature
16 Kbytes of instruction TCM RAM (for
(incremental) encoder inputs. All 15 timers
critical real-time routines) + 4 Kbytes of
running up to 216 MHz. 2x watchdogs, SysTick
backup SRAM (available in the lowest
timer
power modes)
– Flexible external memory controller with up • General-purpose DMA: 16-stream DMA
to 32-bit data bus: SRAM, PSRAM, controller with FIFOs and burst support
SDRAM/LPSDR SDRAM, NOR/NAND • Debug mode
memories – SWD and JTAG interfaces
• Dual mode Quad-SPI – Cortex®-M7 Trace Macrocell™
• Clock, reset and supply management • Up to 140 I/O ports with interrupt capability
– 1.7 V to 3.6 V application supply and I/Os – Up to 136 fast I/Os up to 108 MHz
– POR, PDR, PVD and BOR – Up to 138 5 V-tolerant I/Os
– Dedicated USB power • Up to 21 communication interfaces
– 4-to-26 MHz crystal oscillator – Up to 3× I2C interfaces (SMBus/PMBus)
– Internal 16 MHz factory-trimmed RC (1% – Up to 4 USARTs/4 UARTs (27 Mbit/s,
accuracy) ISO7816 interface, LIN, IrDA, modem
– 32 kHz oscillator for RTC with calibration control)
– Internal 32 kHz RC with calibration – Up to 5 SPIs (up to 54 Mbit/s), 3 with
• Low-power muxed simplex I2Ss for audio class
accuracy via internal audio PLL or external
– Sleep, Stop and Standby modes
clock
– 2 x SAIs (serial audio interface)
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This is information on a product in full production. www.st.com
STM32F722xx STM32F723xx
– 1 x CAN (2.0B active) • CRC calculation unit

– 2 x SDMMCs • RTC: subsecond accuracy, hardware
• Advanced connectivity calendar
– USB 2.0 full-speed device/host/OTG • 96-bit unique ID
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with
dedicated DMA, on-chip full-speed
PHY and on-chip Hi-speed PHY or
ULPI depending on the part number
• True random number generator
Table 1. Device summary
Reference Part number
STM32F722IC, STM32F722IE, STM32F722RC, STM32F722RE, STM32F722VC,

STM32F722xx STM32F722VE, STM32F722ZC, STM32F722ZE
STM32F723IC, STM32F723IE, STM32F723VC, STM32F723VE, STM32F723ZC,
STM32F723xx STM32F723ZE
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STM32F722xx STM32F723xx Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 STM32F723xx versus STM32F722xx LQFP100/ LQFP144/
LQFP176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 Arm Cortex-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 23
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 26
3.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.15.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.15.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.16.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.16.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35
3.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35
3.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Contents STM32F722xx STM32F723xx
3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.20.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.20.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.20.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.20.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.21 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.22 Universal synchronous/asynchronous receiver transmitters (USART) . . 41
3.23 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 42
3.24 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.25 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.26 Audio PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.27 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 43
3.28 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 44
3.30 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 44
3.31 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.32 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.33 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.34 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.35 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.36 Serial-wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.37 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.3 Operating conditions at power-up/power-down (regulator ON) . . . . . . 105
6.3.4 Operating conditions at power-up/power-down (regulator OFF) . . . . . 105
6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . 106
6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 130
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 135
6.3.13 USB OTG HS PHY PLLs characteristics (on STM32F723xx devices) 136
6.3.14 USB OTG HS PHY regulator characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.15 USB HS PHY external resistor characteristics
(on STM32F723xx devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 141
6.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
6.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
6.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
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Contents STM32F722xx STM32F723xx
6.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

6.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.3.32 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 194
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

7.1 LQFP64 – 10 x 10 mm, low-profile quad flat package information . . . . . 197
7.2 LQFP100, 14 x 14 mm low-profile quad flat package information . . . . . 200
7.3 LQFP144, 20 x 20 mm low-profile quad flat package information . . . . . 203
7.4 LQFP176 24 x 24 mm low-profile quad flat package information . . . . . . 206
7.5 UFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.6 UFBGA176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid
array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.7 WLCSP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 222

A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
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STM32F722xx STM32F723xx List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. STM32F722xx and STM32F723xx features and peripheral counts . . . . . . . . . . . . . . . . . . 15
Table 3. Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5. Voltage regulator modes in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 9. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 10. STM32F722xx and STM32F723xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 11. FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 12. STM32F722xx and STM32F723xx alternate function mapping. . . . . . . . . . . . . . . . . . . . . 84
Table 13. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 14. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 15. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 16. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 17. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 103
Table 18. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 19. VCAP1 operating conditions in the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 20. Operating conditions at power-up/power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 105
Table 21. Operating conditions at power-up/power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 105
Table 22. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 23. Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 24. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON . . . . . 110
running from Flash memory on ITCM interface (ART disabled), regulator ON . . . . . . . . 111
or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 29. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 113
Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 113
Table 31. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 114
Table 32. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 115
Table 33. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 116
Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 36. USB OTG HS and USB OTG PHY HS current consumption . . . . . . . . . . . . . . . . . . . . . . 125
Table 37. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 38. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 39. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 40. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Table 42. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 43. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 44. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 45. PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 46. PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 47. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 48. USB OTG HS PLL1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 49. USB OTG HS PLL2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 50. USB OTG HS PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 51. USB HS PHY external resistor characteristics (on STM32F723xx devices). . . . . . . . . . . 138
Table 52. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 53. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 54. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 55. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 56. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 57. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 58. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 59. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 60. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 61. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 62. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 63. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 64. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 65. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 66. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 67. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 68. ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 71. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 153
Table 72. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 153
Table 73. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 74. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 75. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 76. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 77. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 78. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 79. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 80. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 81. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 82. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 83. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 84. USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 85. USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 86. USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 87. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 88. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 89. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 90. USB OTG high speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 91. USB OTG high speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 92. USB FS PHY BCD electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 174
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Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 174

Table 95. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 175
Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 176
Table 97. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 98. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 177
Table 99. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 179
Table 101. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 102. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 103. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 104. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 105. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 106. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 107. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 108. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 109. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 110. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 111. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 112. Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 195
Table 114. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 196
Table 115. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 116. LQPF100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 117. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 118. LQFP176 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 119. UFBGA144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 120. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA) . . . . . . . . . . . . . . . . 211
Table 121. UFBGA(176+25) - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 122. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . 214
Table 123. WLCSP100 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 124. WLCSP100 - Recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 125. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 126. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 127. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 222
Table 128. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
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List of figures STM32F722xx STM32F723xx
List of figures
Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 2. Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. STM32F722xx and STM32F723xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . . 24
Figure 8. VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30
Figure 11. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 34
Figure 15. STM32F722xx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 16. STM32F722xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 18. STM32F723xx WLCSP100 ballout (with OTG PHY HS) . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 19. STM32F722xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 20. STM32F723xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 21. STM32F723xx UFBGA144 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 24. STM32F723xx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 25. STM32F723xx UFBGA176 ballout (with OTG PHY HS). . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 26. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 27. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 28. STM32F722xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 29. STM32F723xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 30. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 31. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 32. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and
LSE in low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LSE in medium low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LSE in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LSE in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LSE in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 37. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 38. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 39. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 40. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 41. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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Figure 42. LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 43. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 44. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 45. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 46. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 47. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 48. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 49. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 155
Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 155
Figure 52. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 53. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 54. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 55. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 56. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 57. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 58. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 59. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 60. USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 169
Figure 61. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 173
Figure 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 175
Figure 64. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 66. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 67. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 69. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 70. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 71. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 72. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 187
Figure 73. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 188
Figure 74. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 75. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 76. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 77. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 78. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 79. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 80. LQFP64 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 81. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 82. LQFP64 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 83. LQFP100 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 84. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 85. LQFP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 86. LQFP144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 87. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 88. LQFP144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 89. LQFP176 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 90. LQFP176 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 91. LQFP176 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 92. UFBGA144 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 93. UFBGA144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
DS11853 Rev 9 11/226

12
List of figures STM32F722xx STM32F723xx
Figure 94. UFBGA144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

Figure 95. UFBGA(176+25) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 96. UFBGA(176+25) - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Figure 97. UFBGA176 top view example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 98. WLCSP100 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 99. WLCSP100 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 100. WLCSP100 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
12/226 DS11853 Rev 9

STM32F722xx STM32F723xx Introduction
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F722xx and STM32F723xx microcontrollers.
This document should be ready in conjunction with the STM32F72xxx and STM32F73xxx
advanced Arm®-based 32-bit MCUs reference manual (RM0431). The reference manual is
available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, refer to the Cortex®-M7 technical
reference manual available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS11853 Rev 9 13/226

47
Description STM32F722xx STM32F723xx
2 Description
The STM32F722xx and STM32F723xx devices are based on the high-performance Arm®
Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core
features a single floating point unit (SFPU) precision which supports Arm® single-precision
data-processing instructions and data types. It also implements a full set of DSP instructions
and a memory protection unit (MPU) which enhances the application security.
The STM32F722xx and STM32F723xx devices incorporate high-speed embedded
memories with a Flash memory up to 512 Kbytes, 256 Kbytes of SRAM (including
64 Kbytes of data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM
(for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power
modes, and an extensive range of enhanced I/Os and peripherals connected to two APB
buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect
supporting internal and external memories access.
All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen general-
purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-
bit timers, a true random number generator (RNG). They also feature standard and
advanced communication interfaces.
• Up to three I2Cs
• Five SPIs, three I2Ss in half duplex mode. To achieve the audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL or via an external clock
to allow synchronization.
• Four USARTs plus four UARTs
• An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI or with the integrated HS PHY depending on the part number)
• One CAN
• Two SAI serial audio interfaces
• Two SDMMC host interfaces
Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory interface.
The STM32F722xx and STM32F723xx devices operate in the –40 to +105 °C temperature
range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for the USB (OTG_FS and
OTG_HS) and the SDMMC2 (clock, command and 4-bit data) are available on all the
packages except LQFP100 and LQFP64 for a greater power supply choice.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A
comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F722xx and STM32F723xx devices offer devices in 7 packages ranging from 64
pins to 176 pins. The set of included peripherals changes with the device chosen.
14/226 DS11853 Rev 9

STM32F722xx STM32F723xx Description
These features make the STM32F722xx and STM32F723xx microcontrollers suitable for a
wide range of applications:
• Motor drive and application control,
• Medical equipment,
• Industrial applications: PLC, inverters, circuit breakers,
• Printers, and scanners,
• Alarm systems, video intercom, and HVAC,
• Home audio appliances,
• Mobile applications, Internet of Things,
• Wearable devices: smart watches.
The following table lists the peripherals available on each part number.
Table 2. STM32F722xx and STM32F723xx features and peripheral counts

Peripherals STM32F72xRx STM32F72xVx STM32F72xZx STM32F72xIx
Flash memory in Kbytes 256 512 256 512 256 512 256 512
System 256(176+16+64)
SRAM in Kbytes Instruction 16
Backup 4
FMC memory controller No Yes(1)
QUADSPI Yes
General-purpose 10(2)
Advanced-control 2
Timers
Basic 2
Low-power No 1
Random number generator Yes
SPI/I2S 3/3 (simplex)(3) 4/3 (simplex)(3) 5/3 (simplex)(3)
I2C 3
USART/UART 4/2 4/4
USB OTG FS Yes
USB OTG HS(4) Yes
Communication USB OTG PHY
interfaces HS controller No Yes(10)
(USBPHYC)
CAN 1
SAI 2
SDMMC1 Yes
SDMMC2 No Yes(5)(6)
DS11853 Rev 9 15/226

47
Table 2. STM32F722xx and STM32F723xx features and peripheral counts (continued)

Peripherals STM32F72xRx STM32F72xVx STM32F72xZx STM32F72xIx
82 in 114 in 140 in
STM32F722xx STM32F722xx STM32F722xx
GPIOs 50
79 in 112 in 138 in
STM32F723xx STM32F723xx STM32F723xx
12-bit ADC 3
Number of channels 16 24
12-bit DAC Yes
Number of channels 2
Maximum CPU frequency 216 MHz(7)
Operating voltage 1.7 to 3.6 V(8)
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Operating temperatures
Junction temperature: –40 to + 125 °C
LQFP100 LQFP144 UFBGA176
Package LQFP64(9)
WLCSP100(10) UFBGA144(10) LQFP176
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 Chip Select.
2. On the STM32F723xx device packages, except the 176-pin ones, the TIM12 is not available, so there are 9 general-
purpose timers.
3. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
4. USB OTG HS with the ULPI on the STM32F722xx devices and with integrated HS PHY on the STM32F723xx devices.
5. The SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144
pin package.
6. The SDMMC2 is not available on the STM32F723Vx devices.
7. 216 MHz maximum frequency for - 40°C to + 85°C ambient temperature range (200 MHz maximum frequency for - 40°C to
+ 105°C ambient temperature range).
8. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.15.2: Internal reset OFF).
9. Available only on the STM32F722xx devices.
2.1 Full compatibility throughout the family

The STM32F722xx devices are fully pin-to-pin, compatible with the STM32F7x5xx,
STM32F7x6xx, STM32F7x7xx devices.
The STM32F722xx devices are partially pin-to-pin, compatible with the STM32F4xxxx
devices, allowing the user to try different peripherals, and reaching higher performances
(higher frequency) for a greater degree of freedom during the development cycle.
Figure 1 and Figure 2 give compatible board designs between the STM32F722xx, with
LQFP64 and LQFP100 packages, and STM32F4xx families.
16/226 DS11853 Rev 9

Figure 1. Compatible board design for LQFP100 package
STM32F427xx / STM32F437xx
PC3 18 STM32F405xx / STM32F407xx
VDD 19
VSSA 20
VREF+ 21
VDDA 22
PA0-WKUP 23
PA1 24
PA2 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PE12
VCAP1
PE13
PE14
PB10
PE15
PE11
VDD
PB11
VSS
VDD
PA3
PC4
PC5
PB1
PB2
PE7
PA4
PA5
PB0
PE10
PA7
PE8
PA6
PE9
PC3 18 STM32F72xxx
VSSA 19
VREF+ 20
VDDA 21
PA0-WKUP 22
PA1 23 Pins 19 to 49 are not compatible
PA2 24
PA3 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VCAP1
PE12
PE13
PB11
PE10
PE14
PB10
PE11
PE15
VDD
VSS
VDD
PA4
VSS
PC4
PC5
PB1
PE7
PE9
PB2
PE8
PA5
PB0
PA7
PA6
MSv41001V2
DS11853 Rev 9 17/226

47
PC12
PC10
PC12
PC10
PC11
PC11
PA15
PA14
PA15
PA14
53 52 51 50 49 53 52 51 50 49
48 VDD VDD 48 VDD VDD
47 VCAP_2 47 VSS
46 PA13 46 PA13
45 PA12 45 PA12
44 PA11 44 PA11
43 PA10 43 PA10
42 PA9 42 PA9
VSS VSS
41 PA8 41 PA8
STM32F405/
40 PC9 STM32F4x1 40 PC9
STM32F415 line 39 PC8
39 PC8
38 PC7 38 PC7
37 PC6 37 PC6
PB11 not available anymore
36 PB15 36 PB15
35 PB14 Replaced by V CAP_1 35 PB14
34 PB13 34 PB13
33 PB12 33 PB12
28 29 30 31 32 28 29 30 31 32
PB10
PB10
VDD
VDD
VSS
PB2
PB2
PB11
VCAP_1
VCAP_1
V CAP increased to 4.7 μf
ESR 1 ohm or below 1 ohm
VSS VDD
VSS VDD
PC 11
PC12
PC10
PA15
PA14
PD2
PB5
PB4
PB3
57 56 55 54 53 52 51 50 49
48 VDD VDD
47 VSS
46 PA13
45 PA12
44 PA11
43 PA10
PA9 VSS
42
STM32F722xx 41 PA8
40 PC9
39 PC8
38 PC7
37 PC6
PC5 not available anymore 36 PB15
Replaced by VCAP_1 35 PB14
34 PB13
33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCAP_1
VSS
VDD
PB0
PB1
PB2
PC4
VSS
VDD
PB11
PB10
PA3
PA5
PA4
PA6
PA7
Not compatible STM32F722xx pins with either

STM32F4x1 or STM32F405/F415 or both
VCAP increased to 4.7 μf
ESR between 0.1 ohm and 0.2 ohm
VSS VDD
MSv41007V3
The STM32F722xx LQFP144, UFBGA176 and LQFP176 packages are fully pin to pin
compatible with the STM32F4xx devices.
18/226 DS11853 Rev 9

2.2 STM32F723xx versus STM32F722xx LQFP100/ LQFP144/

LQFP176 packages
58 PD11
58 PD11 57 PB15
STM32F722xx 57 PD10 STM32F723xx 56 PB14
56 PD9 55 VDD12OTGHS
55 PD8 54 VDDPHYHS
54 PB15 53 OTG_HS_REXT
53 PB14 52 PB13
52 PB13 51 PB12
51 PB12 50
50
VDD
VDD
Not compatible pins

MSv63473V1
93 PG8
93 PG8 92 PG5
92 PG7 91 PG4
91 PG6 90 PG3
90 PG5 89 PG2
89 PG4 88 PD15
88 PG3 87 PD14
87 PG2 86 VDD
86 PD15 85 VSS
85 PD14 84 PD13
84 VDD 83 PD12
83 VSS 82 PD11
82 PD13 81 PD10
81 PD12 80 PD9
80 PD11 79 PD8
STM32F722xx 79 PD10 STM32F723xx 78 PB15
78 PD9 77 PB14
77 PD8 76 VDD12OTGHS
75 PB14 74 PB13
74 PB13 73 PB12
73 PB12 72
72
VDD
VDD
PG6, PG7 removed on the STM32F723xx
Not compatible pins

MSv41098V1
DS11853 Rev 9 19/226

47
112 PG8 112 PG8

111 PG7 111 PG5
110 PG6 110 PG4
109 PG5 109 PG3
108 PG4 108 PG2
107 PG3 107 PD15
106 PG2 106 PD14
105 PD15 105 VDD
104 PD14 104 VSS
103 VDD 103 PD13
102 VSS 102 PD12
101 PD13 101 PD11
100 PD12 100 PD10
99 PD11 99 PD9
98 PD10 98 PD8
97 PD9 97 PB15
96 PD8 96 PB14
STM32F722xx 95 PB15 STM32F723xx 95 VDD12OTGHS
93 PB13 93 PB13
92 PB12 92 PB12
91 VDD 91 VDD
90 VSS 90 VSS
89 PH12 89 PH12
88 88
PH11
PH11
PG6, PG7 removed on the STM32F723xx
Not compatible pins

MSv41099V1
Figure 6 shows the general block diagram of the device family.
20/226 DS11853 Rev 9

Figure 6. STM32F722xx and STM32F723xx block diagram

JTRST, JTDI, JTAG & SW MPU FPU
JTCK/SWCLK ETM NVIC
JTDO/SWD, JTDO DTCM RAM 64KB
DTCM
TRACECK Arm CPU ICTM ITCM RAM 16KB
TRACED[3:0]
AHB2AXI
Cortex-M7
I-Cache AXIM
8KB ACCEL/ FLASH 512KB
CACHE
216MHz D-Cache RNG
AHBP
8KB
11S8M 8S7M
AHBS
DP
FIFO
SRAM1 176KB USB DM
PHY
SCL, SDA, INT, ID, VBUS
AHB bus-matrix
SRAM2 16KB OTG FS
(2) LDO CLK, NE [3:0], A[23:0],
PLL1
USB HS AHB2 216 MHz D[31:0], NOEN, NWEN,
AHB BUS-MATRIX
PHY NBL[3:0], SDCLKE[1:0]
BGR PLL2 EXT MEM CTL (FMC)
SDNE[1:0], SDNWE, NL
SRAM, SDRAM, NOR-Flash, NRAS, NCAS, NADV
NAND-Flash, SDRAM NWAIT, INTN
USB OTG HS
FS PHY
DP, DM DMA/ Quad-SPI CLK, CS,D[7:0]

ULPI:CK, D[7:0], DIR, STP, NXT FIFO @VDDA
PLL LDO AHB1 216 MHz POR
SCL/SDA, INT, ID, VBUS SUPPLY
reset SUPERVISION
POR/PDR
GP-DMA2 8 Streams Int
FIFO BOR VDDA, VSSA
PVD NRESET
@VDDA
8 Streams WKUP[4:0]
GP-DMA1 FIFO RC HS @VDD33 (3)
VDD12 BBgen + POWER MNGT
VDDPHYHS = 3.0 to 3.6V
RC LS VDDMMC33 = 3.0 to 3.6V
PA[15:0] GPIO PORT A
VOLT. REG VDDUSB33 = 3.0 to 3.6 V
PWRCTRL
PLL1+PLL2+PLL3
PB[15:0] 3.3V TO 1.2V VDD = 1.8 to 3.6 V
GPIO PORT B
VSS
PC[15:0] @VDD33 VCAP1
GPIO PORT C
XTAL OSC OSC_IN
PD[15:0] GPIO PORT D 4- 16MHz OSC_OUT
PE[15:0] RCC WDG32K
GPIO PORT E Reset
M & control
GT
GPIO PORT F Standby VBAT = 1.8 to 3.6 V
PF[15:0]
interface
PG[15:0] AHB1PCLK @VSW
APBP1CLK
GPIO PORT G
APBP2CLK
AHB2PCLK
OSC32_IN
HCLK
FCLK
XTAL 32 kHz OSC32_OUT
LS
PH[15:0] GPIO PORT H
RTC RTC_TS
PI[11:0] GPIO PORT I AWU RTC_TAMPx
Backup register RTC_OUT
LS
CRC 4 KB BKPRAM
168 AF EXT IT. WKUP
D[7:0] TIM2 4 channels, ETR as AF
FIFO FIFO
32b
CMD, CK as AF SDMMC1
TIM3 16b 4 channels, ETR as AF
D[7:0] SDMMC2
CMD, CK as AF GPDMA1
GPDMA2 TIM4 16b 4 channels, ETR as AF
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF TIM1 / PWM 16b AHB/
AHB/APB2 TIM5 32b 4 channels
4 compl. chan.(TIM8_CH1[1:4]N), APB1
TIM8 / PWM 16b
4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF TIM12 16b 2 channels as AF
2 channels as AF TIM9 16b
TIM13 16b 1 channel as AF
1 channel as AF TIM10 16b
APB2 108 MHz (max)
1 channel as AF TIM11 16b TIM14 16b 1 channel as AF
RX, TX, SCK, smcard USART1 smcard RX, TX, SCK

CTS, RTS as AF USART2 irDA CTS, RTS as AF
irDA
RX, TX, SCK, smcard WWDG smcard RX, TX, SCK
CTS, RTS as AF USART6 USART3
irDA irDA CTS, RTS as AF
MOSI, MISO, UART4 RX, TX as AF
SCK, NSS as AF
SPI1/I2S1 16b
LPTIM1 UART5 RX, TX as AF
MOSI, MISO,
3Hz
(max)
SPI4 RX, TX as AF
SCK, NSS as AF UART7
APB10M
MOSI, MISO, SPI5 UART8 RX, TX as AF

APB1 54 MHz
SCK, NSS as AF
TIM6 16b SPI2/I2S2 MOSI, MISO, SCK
FIFO FIFO
SD, SCK, FS, MCLK as AF SAI1 NSS as AF

TIM7 16b SPI3/I2S3 MOSI, MISO, SCK
SD, SCK, FS, MCLK as AF SAI2 NSS as AF
Digital filter
I2C1/SMBUS SCL, SDA, SMBAL as AF
ULPI:CK, D[7:0], DIR, STP, NXT (2) I2C2/SMBUS SCL, SDA, SMBAL as AF
OTG HS PHY
SCL, SDA, INT, ID, VBUS CONTROLLER SYSCFG
I2C3/SMBUS SCL, SDA, SMBAL as AF
@VDDA
VDDREF_ADC AR T 2 M B sensor
U STemperature ps
FIFO
bxCAN1 TX, RX
8 analog inputs common
to the 3 ADCs ADC1 @VDDA
8 analog inputs common ADC2 DAC1
to the ADC1 & 2 IF ITF
8 analog inputs for ADC3
ADC3 DAC2
DAC1 DAC2
as AF as AF MSv41012V4
1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
3. Available only on the STM32F723xx LQFP100 package.
DS11853 Rev 9 21/226

47
Functional overview STM32F722xx STM32F723xx
3 Functional overview
3.1 Arm Cortex-M7 with FPU

The Arm Cortex-M7 with FPU processor is the latest generation of Arm processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and low interrupt latency.
The Cortex-M7 processor is a highly efficient high-performance featuring:
• Six-stage dual-issue pipeline
• Dynamic branch prediction
• Harvard caches (8 Kbytes of I-cache and 8 Kbytes of D-cache)
• 64-bit AXI4 interface
• 64-bit ITCM interface
• 2x32-bit DTCM interfaces
The processor supports the following memory interfaces:
• tightly-coupled memory (TCM) interface
• Harvard instruction and data caches and AXI master (AXIM) interface
• dedicated low-latency AHB-Lite peripheral (AHBP) interface
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It supports single precision FPU (floating point unit), speeds up software development by
using metalanguage development tools, while avoiding saturation.
Figure 6 shows the general block diagram of the STM32F722xx and STM32F723xx family.
Note: Cortex-M7 with FPU core is binary compatible with the Cortex-M4 core.
3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to eight protected areas that can in turn be
divided up into eight subareas. The protection area sizes are between 32 bytes and the
whole 4 Gbytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS
(real-time operating system). If a program accesses a memory location that is prohibited by
the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
22/226 DS11853 Rev 9

STM32F722xx STM32F723xx Functional overview
3.3 Embedded Flash memory

The STM32F722xx and STM32F723xx devices embed a Flash memory of up to 512 Kbytes
available for storing programs and data.
The flexible protections can be configured thanks to option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: no access (read, erase, program) to the Flash memory or backup SRAM
can be performed while the debug feature is connected or while booting from RAM
or system memory bootloader.
– Level 2: debug/chip read protection disabled
• Write protection (WRP): the protected area is protected against erasing and
programming.
• Proprietary code readout protection (PCROP): Flash memory user sectors (0 to 7) can
be protected against D-bus read accesses by using the proprietary readout protection
(PCROP). The protected area is execute-only.
3.4 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
link-time and stored at a given memory location.
3.5 Embedded SRAM

All the devices feature:
• System SRAM up to 256 Kbytes:
– SRAM1 on AHB bus Matrix: 176 Kbytes
– SRAM2 on AHB bus Matrix: 16 Kbytes
– DTCM-RAM on TCM interface: 64 Kbytes for critical real-time data
• Instruction RAM (ITCM-RAM) 16 Kbytes:
– It is mapped on TCM interface and reserved only for CPU execution/instruction
useful for critical real-time routines.
The data TCM RAM is accessible by the GP-DMAs and peripheral DMAs through the
specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is
accessed at CPU clock speed with 0 wait states.
• 4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
DS11853 Rev 9 23/226

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3.6 AXI-AHB bus matrix

The STM32F722xx and STM32F723xx system architecture is based on two subsystems:
• an AXI-to-multi-AHB bridge converting AXI4 protocol to AHB-Lite protocol:
– 3x AXI-to-32-bit-AHB bridges connected to AHB bus matrix
– 1x AXI-to-64-bit-AHB bridge connected to the embedded Flash memory
• a multi-AHB bus matrix
– The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs,
USB HS) and the slaves (Flash memory, RAM, FMC, QUADSPI, AHB and APB
peripherals), and ensures a seamless and efficient operation even when several
high-speed peripherals work simultaneously.
Figure 7. STM32F722xx and STM32F723xx AXI-AHB bus matrix architecture(1)

DTCM
ITCM
AHBS
GP GP USB OTG
Arm Cortex-M7 DMA1 DMA2 HS
USB_HS_M
DMA_MEM2
DMA_P2
DMA_MEM1
DMA_PI
8KB DTCM RAM

I/D Cache 64KB
AXIM
AHBP
ITCM RAM
16KB
AXI to
multi-AHB
ITCM
ART
FLASH
64-bit AHB 512KB
64-bit BuS Matrix
SRAM1
176KB
SRAM2
16KB
AHB
Periph1 APB1
AHB
periph2
FMC external APB2
MemCtl
Quad-SPI
32-bit Bus Matrix - S
MSv41005V1
1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus.
24/226 DS11853 Rev 9

3.7 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with eight
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support a circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. The configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
• SPI and I2S
• I2C
• USART
• General-purpose, basic and advanced-control timers TIMx
• DAC
• SDMMC
• ADC
• SAI
• QUADSPI
3.8 Flexible memory controller (FMC)

The flexible memory controller (FMC) includes three memory controllers:
• NOR/PSRAM memory controller
• NAND/memory controller
• synchronous DRAM (SDRAM/mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/oneNAND Flash memory
– PSRAM (four memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-, 16-, 32-bit data bus width
• Independent chip select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• Read FIFO for SDRAM controller
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• HCLK/2 maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses
LCD parallel interface

The FMC can be configured to interface seamlessly with most graphic LCD controllers.
It supports Intel® 8080 and Motorola® 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build
cost-effective graphic applications using LCD modules, with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.9 Quad-SPI memory interface (QUADSPI)

All the devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting single, dual or quad-SPI Flash memories. It can work in:
• Direct mode through registers
• External Flash status register polling mode
• Memory-mapped mode
Up to 256 Mbytes of external Flash are memory mapped, supporting 8-, 16-, and 32-bit
access. The code execution is supported.
The opcode and the frame format are fully programmable. The communication can be either
in single-data rate or dual-data rate.
3.10 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 110 maskable interrupt channels, plus the 16 interrupt lines of the
Cortex-M7 with FPU core.
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with a minimum
interrupt latency.
3.11 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 24 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs in the
STM32F722xx devices (138 GPIOs in the STM32F723xx devices) can be connected to the
16 external interrupt lines.
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3.12 Clocks and startup

On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock.
The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application
can then select as system clock either the RC oscillator or an external 4-26 MHz clock
source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 216 MHz. Similarly, a full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2), and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 216 MHz, while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.
The devices embed two dedicated PLLs (PLLI2S and PLLSAI) which allow audio class
performance to be achieved. In this case, the I2S and SAI master clock can generate all
standard sampling frequencies from 8 kHz to 192 kHz.
The STM32F723xx devices embed two PLLs inside the PHY HS controller: PLL1 and PLL2.
The PLL1 allows an output of 60 MHz used as an input for PLL2 which itself allows the
generation of 480 Mbps in the USB OTG High Speed mode.
The PLL1 has as input HSE clock.
3.13 Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing any boot memory address to be programmed from 0x0000 0000 to
0x3FFF FFFF, which includes:
• all Flash address space mapped on ITCM or AXIM interface
• all RAM address space: ITCM, DTCM RAMs, and SRAMs mapped on AXIM interface
• system memory bootloader
The bootloader is located in system memory. It is used to reprogram the Flash memory
through a serial interface.
3.14 Power supply schemes

• VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
• VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: The VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 3.15.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode
versus device operating mode to identify the packages supporting this option.
• The VDDSDMMC can be connected either to VDD or to an external independent power
supply (1.8 to 3.6 V) for the SDMMC2 pins (clock, command, and 4-bit data).
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47
For example, when the device is powered at 1.8 V, an independent power supply 2.7 V
can be connected to VDDSDMMC.When the VDDSDMMC is connected to a separated
power supply, it is independent from VDD or VDDA, but it must be the last supply to be
provided, and the first to disappear. The following conditions VDDSDMMC must be
respected:
– During the power-on phase (VDD < VDD_MIN), VDDSDMMC must be always lower
than VDD.
– During the power-down phase (VDD < VDD_MIN), VDDSDMMC must be always lower
than VDD.
– The VDDSDMMC rising and falling time rate specifications must be respected.
– In the operating mode phase, VDDSDMMC can be lower or higher than VDD:
All associated GPIOs powered by VDDSDMMC are operating between
VDDSDMMC_MIN and VDDSDMMC_MAX.
• The VDDUSB can be connected either to VDD or to an external independent power
supply (3.0 to 3.6 V) for USB transceivers (refer to Figure 8 and Figure 9).
For example, when the device is powered at 1.8 V, an independent power supply 3.3 V
can be connected to the VDDUSB. When the VDDUSB is connected to a separated power
supply, it is independent from VDD or VDDA, but it must be the last supply to be
provided, and the first to disappear. The following conditions VDDUSB must be
respected:
– During the power-on phase (VDD < VDD_MIN), VDDUSB must be always lower
than VDD.
– During the power-down phase (VDD < VDD_MIN), VDDUSB must be always lower
than VDD.
– The VDDUSB rising and falling time rate specifications must be respected.
– In the operating mode phase, VDDUSB can be lower or higher than VDD:
- If the USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered
by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
- The VDDUSB supplies both USB transceiver (USB OTG_HS and USB OTG_FS).
If only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied by VDDUSB.
- If the USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered
by VDDUSB are operating between VDD_MIN and VDD_MAX.
28/226 DS11853 Rev 9

Figure 8. VDDUSB connected to VDD power supply

VDD
VDD_MAX
VDD= VDDA = VDDUSB
VDD_MIN
Power-down time
Power-on Operating mode
MS37591V1
Figure 9. VDDUSB connected to external power supply
VDDUSB_MAX
USB functional area
VDDUSB
VDDUSB_MIN
USB non USB non
functional VDD = VDDA functional
area area
VDD_MIN
Power-down time
Power-on Operating mode
MS37590V1
On the STM32F7x3xx devices, the USB OTG HS subsystem uses one or two additional
power supply pins depending on the package:
• The VDD12OTGHS pin is the output of PHY HS regulator (1.2 V). An external
capacitor of 2.2 µF must be connected on the VDD12OTGHS pin.
• On the LQFP100 only, a second power pin VDDPHYHS is used to supply the USB
OTG PHY HS and associated GPIOs.The VDDPHYHS follows the same rules provided
for the VDDUSB power pin.
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47
3.15 Power supply supervisor
3.15.1 Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled
by holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry
coupled with a brownout reset (BOR) circuitry. At power-on, POR/PDR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply, and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold, and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.15.2 Internal reset OFF

This feature is available only on packages featuring the PDR_ON pin. The internal
POR/PDR circuitry is disabled through the PDR_ON pin.
An external power supply supervisor monitors VDD and NRST, and maintains the device in
reset mode as long as VDD is below a specified threshold. PDR_ON must be connected
to VSS (see the figure below).
Figure 10. Power supply supervisor interconnection with internal reset OFF
VDD
External VDD power supply supervisor
Ext. reset controller active when

VDD < 1.7 V
Application reset
NRST signal
PDR_ON
VDD
VSS
MS31383V4
The VDD specified threshold, below which the device must be maintained under reset,
is 1.7 V (see Figure 11).
A comprehensive set of power-saving mode allows design low-power applications.
30/226 DS11853 Rev 9

When the internal reset is OFF, the following integrated features are no more supported:
• The integrated POR/PDR circuitry is disabled.
• The BOR circuitry must be disabled.
• The embedded PVD is disabled.
• VBAT functionality is no more available, and VBAT pin must be connected to VDD.
All packages, except the LQFP100, disables the internal reset through the PDR_ON signal
when connected to VSS.
Figure 11. PDR_ON control with internal reset OFF

V DD
PDR = 1.7 V
time
Reset by other source than

power supply supervisor
NRST
PDR_ON PDR_ON time
MS19009V7
3.16 Voltage regulator

The regulator has four operating modes:
• Regulator ON
– main regulator mode (MR)
– low-power regulator (LPR)
– power-down
• Regulator OFF
3.16.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
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47
There are three power modes configured by software when the regulator is ON:
• MR mode used in Run/Sleep modes, or in Stop modes:
– In Run/Sleep modes
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). A different voltage scaling is provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
for a given voltage scaling.
– In Stop modes
The MR can be configured in two ways during stop mode:
- MR operates in normal mode (default mode of MR in Stop mode).
- MR operates in under-drive mode (reduced leakage mode).
• LPR is used in Stop mode:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
– LPR operates in normal mode (default mode when LPR is ON).
– LPR operates in under-drive mode (reduced leakage mode).
• Power-down is used in Standby mode.
The power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance, and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
VCAP_1 and VCAP_2 pins must be connected to 2 × 2.2 µF, ESR < 2 Ω (or 1 × 4.7 µF, ESR
between 0.1 Ω and 0.2 Ω if only the VCAP_1 pin is provided (on LQFP64 package)).
All the packages have the regulator ON feature.
Table 3. Voltage regulator configuration mode versus device operating mode(1)

Voltage regulator
Run mode Sleep mode Stop mode Standby mode
configuration
Normal mode MR MR MR or LPR -

Over-drive mode(2) MR MR - -
Under-drive mode - - MR or LPR -
Power-down mode - - - Yes
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
3.16.2 Regulator OFF

This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode supplies externally a V12
voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.The two 2.2 µF ceramic capacitors must
be replaced by two 100 nF decoupling capacitors.
32/226 DS11853 Rev 9

When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor can be used to monitor the V12 of the logic power domain. The PA0 pin
can be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it is used to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset.
As a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
• The over-drive and under-drive modes are not available.
• The Standby mode is not available.
Figure 12. Regulator OFF

V12
External VCAP_1/2 power
supply supervisor Application reset
Ext. reset controller active signal (optional)
when VCAP_1/2 < Min V12
VDD
PA0 NRST
VDD
BYPASS_REG
V12
VCAP_1
VCAP_2
ai18498V3
The following conditions must be respected:

• VDD must always be higher than VCAP_1 and VCAP_2 to avoid current injection between
power domains.
• If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time
for VDD to reach 1.7 V, then PA0 must be kept low to cover both conditions: until
VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V
(see Figure 13).
• Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 can be asserted low externally
(see Figure 14).
• If VCAP_1 and VCAP_2 go below V12 minimum value, and VDD is higher than 1.7 V, then
a reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application.
On the LQFP64 pin package, the VCAP_2 is not available.
DS11853 Rev 9 33/226

47
Figure 13. Startup in regulator OFF: slow VDD slope

- power-down reset risen after VCAP_1/VCAP_2 stabilization
VDD
PDR = 1.7 V or 1.8 V VCAP_1 / VCAP_2

V12
Min V12
time
NRST
time
ai18491f
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 14. Startup in regulator OFF mode: fast VDD slope

- power-down reset risen before VCAP_1/VCAP_2 stabilization
VDD
PDR = 1.7 V or 1.8 V
VCAP_1 / VCAP_2
V12
Min V12
time
NRST
PA0 asserted externally
time
ai18492e
1. This figure is valid whatever the internal reset mode (ON or OFF).
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3.16.3 Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability

Package Regulator ON Regulator OFF Internal reset ON Internal reset OFF
LQFP64,
Yes No
LQFP100
Yes No
LQFP144
Yes Yes
LQFP176, Yes Yes PDR_ON set to VDD PDR_ON set to VSS
UFBGA144, BYPASS_REG set BYPASS_REG set
UFBGA176 to VSS to VDD
3.17 Real-time clock (RTC), backup SRAM and backup registers

The RTC is an independent BCD timer/counter. It supports the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Two programmable alarms
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• Three anti-tamper detection pins with programmable filter
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch
to VBAT mode.
• 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when
the device wakes up from Standby mode.
The RTC clock sources can be:
• a 32.768 kHz external crystal (LSE)
• an external resonator or oscillator (LSE)
• the internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
• the high-speed external clock (HSE) divided by 32
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
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47
All the RTC events (alarm, wakeup timer, timestamp, or tamper) can generate an interrupt,
and wake up the device from the low-power modes.
3.18 Low-power modes

The devices support three low-power modes to achieve the best compromise between
low-power consumption, short startup time, and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate, and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in Stop mode):
– normal mode (default mode when MR or LPR is enabled)
– under-drive mode
The device can be woken up from the Stop mode by any of the EXTI lines (the EXTI
line source can be one of the 16 external lines, the PVD output, the RTC alarm,
wakeup, tamper, time stamp events, the USB OTG FS/HS wake up, and the LPTIM1
asynchronous interrupt).
Table 5. Voltage regulator modes in Stop mode

Voltage regulator
Main regulator (MR) Low-power regulator (LPR)
configuration
Normal mode MR ON LPR ON

Under-drive mode MR in under-drive mode LPR in under-drive mode
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off, so that the entire 1.2 V domain is powered off.
The PLL, the HSI RC, and the HSE crystal oscillators are also switched off.
After entering Standby mode, the SRAM and register contents are lost except for
registers in the backup domain, and the backup SRAM when selected.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
a rising or falling edge on one of the six WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11),
or an RTC alarm, wakeup, tamper, time stamp event occurs.
The Standby mode is not supported when the embedded voltage regulator is
bypassed, and the 1.2 V domain is controlled by an external power.
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3.19 VBAT operation

The VBAT pin is used to power the device VBAT domain from an external battery, an external
super-capacitor, or from VDD when no external battery and an external super-capacitor
are present.
The VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers, and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When the PDR_ON pin is connected to VSS (internal reset OFF), the VBAT functionality is no
more available, and the VBAT pin must be connected to VDD.
3.20 Timers and watchdogs

The devices include two advanced-control timers, eight general-purpose timers, two basic
timers, and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
Table 6. Timer feature comparison

Max Max
DMA Capture/ Complem
Timer Counter Counter Prescaler interface timer
Timer request compare entary
type resolution type factor clock clock
generation channels output
(MHz) (MHz)(1)
Any
Up,
Advanced TIM1, integer
16-bit Down, Yes 4 Yes 108 216
-control TIM8 between 1
Up/down
and 65536
DS11853 Rev 9 37/226

47
Table 6. Timer feature comparison (continued)

Max Max
DMA Capture/ Complem
Timer Counter Counter Prescaler interface timer
Timer request compare entary
type resolution type factor clock clock
generation channels output
(MHz) (MHz)(1)
Any
Up,
TIM2, integer
32-bit Down, Yes 4 No 54 108/216
TIM5 between 1
Up/down
and 65536
Any
Up,
TIM3, integer
16-bit Down, Yes 4 No 54 108/216
TIM4 between 1
Up/down
and 65536
Any
integer
TIM9 16-bit Up No 2 No 108 216
between 1
General and 65536
purpose Any
TIM10, integer
16-bit Up No 1 No 108 216
TIM11 between 1
and 65536
Any
integer
TIM12 16-bit Up No 2 No 54 108/216
between 1
and 65536
Any
TIM13, integer
16-bit Up No 1 No 54 108/216
TIM14 between 1
and 65536
Any
TIM6, integer
Basic 16-bit Up Yes 0 No 54 108/216
TIM7 between 1
and 65536
1. The maximum timer clock is either 108 or 216 MHz, depending on TIMPRE bit configuration in the RCC_DCKCFGR
register.
3.20.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on six channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their four independent channels can be used for:
• input capture
• output compare
• PWM generation (edge- or center-aligned modes)
• one-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability
(0-100%).
38/226 DS11853 Rev 9

The advanced-control timer can work together with the TIMx timers via the timer Link
feature for synchronization or event chaining.
The TIM1 and TIM8 support independent DMA request generation.
3.20.2 General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32F722xx and
STM32F723xx devices (see Table 6 for differences).
• TIM2, TIM3, TIM4, TIM5
The STM32F722xx and STM32F723xx include four full-featured general-purpose
timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit
auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are
based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4
independent channels for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input capture/output compare/PWM on the largest
packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
timer link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
• TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
3.20.3 Basic timers TIM6 and TIM7

These timers are mainly used for the DAC trigger and waveform generation. They can also
be used as a generic 16-bit time base.
The TIM6 and TIM7 support independent DMA request generation.
3.20.4 Low-power timer (LPTIM1)

The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• configurable output: pulse, PWM
• continuous/one-shot mode
• selectable software/hardware input trigger
• selectable clock source:
DS11853 Rev 9 39/226

47
• internal clock source: LSE, LSI, HSI, or APB clock

• external clock source over LPTIM input (working even with no internal clock source
running, used by the pulse-counter application)
• programmable digital glitch filter
• encoder mode
3.20.5 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.20.6 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.20.7 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
• a 24-bit downcounter
• auto-reload capability
• maskable system interrupt generation when the counter reaches 0
• programmable clock source
3.21 Inter-integrated circuit interface (I2C)

The devices embed three I2Cs. Refer to Table 7: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
40/226 DS11853 Rev 9

• System management bus (SMBus) specification rev 2.0 compatibility:

– Hardware PEC (packet error checking) generation and verification
with ACK control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBusTM) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 7. I2C implementation

I2C features(1) I2C1 I2C2 I2C3
Standard-mode (up to 100 kbit/s) X X X

Fast-mode (up to 400 kbit/s) X X X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X
Programmable analog and digital noise filters X X X
SMBus/PMBus hardware support X X X
Independent clock X X X
1. X: supported.
3.22 Universal synchronous/asynchronous receiver transmitters

(USART)
The devices embed USARTs. Refer to Table 8: USART implementation for the features
implementation.
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format.
The USART peripheral supports:
• Full-duplex asynchronous communications
• Configurable oversampling method by 16 or 8 to give flexibility between speed and
clock tolerance
• Dual clock domain allowing convenient baud rate programming independent from the
PCLK reprogramming
• A common programmable transmit and receive baud rate of up to 27 Mbit/s when
USART clock source is system clock frequency (max is 216 MHz) and oversampling
by eight is used.
• Auto baud rate detection
• Programmable data word length (7 or 8 or 9 bits) word length
• Programmable data order with MSB-first or LSB-first shifting
• Programmable parity (odd, even, no parity)
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47
• Configurable stop bits (1, 1.5, or 2 stop bits)

• Synchronous mode and clock output for synchronous communications
• Single-wire half-duplex communications
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Multiprocessor communications
• LIN master synchronous break send capability and LIN slave break detection capability
• IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode
• Smartcard mode (T = 0 and T = 1 asynchronous protocols for Smartcards as defined in
the ISO/IEC 7816-3 standard)
• Support for Modbus communication
Table 8 summarizes the implementation of all U(S)ARTs instances
Table 8. USART implementation

Features(1) USART1/2/3/6 UART4/5/7/8
Data length 7, 8 and 9 bits

Hardware flow control for modem X X
Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X -
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X X
LIN mode X X
Dual clock domain X X
Receiver timeout interrupt X X
Modbus communication X X
Auto baud rate detection X X
Driver enable X X
1. X: supported.
3.23 Serial peripheral interface (SPI)/inter- integrated sound

interfaces (I2S)
The devices feature up to five SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, and SPI5 can communicate at up to 50 Mbit/s, SPI2
and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces support the
NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be served by
the DMA controller.
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Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in master or slave mode, in simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
3.24 Serial audio interface (SAI)

The devices embed two serial audio interfaces.
The serial audio interface is based on two independent audio subblocks which can operate
as transmitter or receiver with their FIFO. Many audio protocols are supported by each
block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output,
supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be
configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two subblocks can be configured in synchronous mode when full-duplex mode
is required.
SAI1 and SAI2 can be served by the DMA controller.
3.25 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
the achievement of an error-free I2S sampling clock accuracy without compromising on the
CPU performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU and USB interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 kHz to 192 lHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or codec output).
3.26 Audio PLL (PLLSAI)

An additional PLL dedicated to audio is used for the SAI1 peripheral in case the PLLI2S is
programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz)
and the audio application requires both sampling frequencies simultaneously.
3.27 SD/SDIO/MMC card host interface (SDMMC)

SDMMC host interfaces are available, that support MultiMediaCard System Specification
Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
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47
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDMMC Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a
stack of MMC4.1 or previous.
The SDMMC can be served by the DMA controller
3.28 Controller area network (bxCAN)

The CAN is compliant with the 2.0A and B (active) specifications with a bit rate
up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive
FIFOs with three stages and 28 shared scalable filter banks (all of them can be used even if
one CAN is used). 256 bytes of SRAM are allocated to the CAN.
3.29 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
• Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
• 12 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• Internal FS OTG PHY support
• HNP/SNP/IP inside (no need for any external resistor)
• BCD support
For the OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.30 Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. The USB OTG HS supports both full-speed and high-speed operations. It
integrates the transceivers for full-speed operation (12 Mbit/s).
The STM32F722xx devices feature a UTMI low-pin interface (ULPI) for high-speed
operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device
connected to the ULPI is required.
44/226 DS11853 Rev 9

The STM32F723xx devices feature an integrated PHY HS.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has a software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
• Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 8 bidirectional endpoints
• 16 host channels with periodic OUT support
• Software configurable to OTG1.3 and OTG2.0 modes of operation
• USB 2.0 LPM (Link Power Management) support
• For STM32F722xx devices: External HS or HS OTG operation supporting ULPI in
SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12
signals. It can be clocked using the 60 MHz output.
• For STM32F723xx devices: Internal HS OTG PHY support
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Universal serial-bus controller on-the-go high-speed PHY controller

(USBPHYC) only on STM32F723xx devices.
The USB HS PHY controller:
• Sets the PHYPLL1/2 values for the PHY HS.
• Sets the other controls on the PHY HS.
• Controls and monitors the USB PHY LDO.
3.31 Random number generator (RNG)

All the devices embed an RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.
3.32 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
A fast I/O handling allows a maximum I/O toggling up to 108 MHz.
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47
3.33 Analog-to-digital converters (ADCs)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up
to 16 external channels, performing conversions in the single-shot or scan mode. In the
scan mode, an automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs can be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
3.34 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with the temperature.
The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part must be used.
3.35 Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
• Two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
• Input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
46/226 DS11853 Rev 9

3.36 Serial-wire JTAG debug port (SWJ-DP)

The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial-wire debug
port that enables either a serial-wire debug, or a JTAG probe to be connected to the target.
The debug is performed using two pins only instead of five required by the JTAG (JTAG pins
can be reused as GPIO with alternate function): JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.37 Embedded Trace Macrocell™

The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F722xx and STM32F723xx device through a small number of ETM pins to an
external hardware trace port analyser (TPA). The TPA is connected to a host computer
using the USB or any other high-speed channel. The real-time instruction and data flow
activity can be recorded and then formatted for display on the host computer that runs the
debugger software. The TPA hardware is commercially available from common
development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
DS11853 Rev 9 47/226

47
Pinouts and pin description STM32F722xx STM32F723xx
4 Pinouts and pin description
Figure 15. STM32F722xx LQFP64 pinout
BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD2
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT 1 48 VDD
PC13 2 47 VSS
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0-WKUP 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCAP_1
PA3
PA4
PA5
PA6
PA7
VSS
VDD
PC4
PB0
PB1
PB2
PB10
PB11
VSS
VDD
MS40455V3
1. The above figure shows the package top view.
48/226 DS11853 Rev 9

STM32F722xx STM32F723xx Pinouts and pin description
BOOT0
PA15
PA14
PC12
PC11
PC10
VDD
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PE1
PE0
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VCAP_2
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0-WKUP 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCAP_1
PE11
PE10
PB10
PB11
PE12
PE14
PE15
PE13
VDD
VDD
VSS
PB2
PB1
PA7
PC5
PA4
PB0
PE7
PE8
PE9
PA5
PA6
PC4
VSS
MSv40457V1
DS11853 Rev 9 49/226

94
BOOT0
PA15
PA14
PC12
PC11
PC10
VDD
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PE1
PE0
VSS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VCAP_2
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
V SSA 19 57 PB15
VREF+ 20 56 PB14
VDDA 21 55 VDD12OTGHS
PA0-WKUP 22 54 VDDPHYHS
PA1 23 53 OTG_HS_REXT
PA2 24 52 PB13
PA3 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCAP_1
PE11
PE10
PB10
PB11
PE12
PE14
PE15
PE13
VDD
VDD
VSS
PB2
PB1
PA7
PC5
PA4
PB0
PE7
PE8
PE9
PA5
PA6
PC4
VSS
MSv63474V1
50/226 DS11853 Rev 9

Figure 18. STM32F723xx WLCSP100 ballout (with OTG PHY HS)
1 2 3 4 5 6 7 8 9 10
A VDD VSS PC10 PD1 PD5 PB3 BOOT0 VSS VDD PE3
B PA13 PA12 VCAP_2 PA15 PD0 PD4 PB4 PB7 PE1 PE6
C PA11 PA10 PA9 PA14 PC11 PD3 PB5 PB8 PE2 VBAT
D PC9 PC8 PA8 PC7 PC12 PD6 PB6 PB9 PE4 PC13
E PC6 PD15 PD13 PE10 PD2 PD7 PE0 PE5 PC14 PC15
F PD14 PD12 PD11 PE15 PB0 PA5 PC3 PC0 VSS VDD
G VDD12 OTG_HS
PB10 PE11 PB1 PA6 PA4 PA0 NRST PH0
OTGHS _REXT
H PB15 PB13 PB11 PE12 PE8 PC4 PA3 PA2 PC1 PH1
J PB14 PB12 VCAP_1 PE13 PE7 PC5 VDD PA1 VREF+ PC2
K VDD VDD PE14 PB2

VSS PE9 PA7 VSS VDDA VSSA
USB
MSv42002V2
DS11853 Rev 9 51/226

94
VDDSDMMC
PDR_ON
BOOT0
PG15
PG14
PG13
PG12
PG11
PG10
PC12
PC11
PC10
PA15
PA14
PG9
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
VDD
VDD
VSS
VSS
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
109
120
119
118
117
116
115
114
113
112
110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VCAP_2
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14 8 101 PA9
PC15 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDUSB
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0 23 86 PD15
PH1 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
72
61
62
63
64
65
66
67
68
69
70
71
VCAP_1
VDD
VSS
PA3
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VDD
VDD
VDD
VSS
VSS
MS39132V1
52/226 DS11853 Rev 9

VDDSDMMC
PDR_ON
BOOT0
PG15
PG14
PG13
PG12
PG11
PG10
PC12
PC11
PC10
PA15
PA14
PG9
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
VDD
VDD
VSS
VSS
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
109
120
119
118
117
116
115
114
113
112
110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VCAP_2
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14 8 101 PA9
PC15 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDDUSB
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG5
PF6 18 91 PG4
PF7 19 LQFP144 90 PG3
PF8 20 with HS PHY 89 PG2
PF9 21 88 PD15
PF10 22 87 PD14
PH0 23 86 VDD
PH1 24 85 VSS
NRST 25 84 PD13
PC0 26 83 PD12
PC1 27 82 PD11
PC2 28 81 PD10
PC3 29 80 PD9
VDD 30 79 PD8
VSSA 31 78 PB15
VREF+ 32 77 PB14
VDDA 33 76 VDD12OTGHS
PA0 34 75 OTG_HS_REXT
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
72
61
62
63
64
65
66
67
68
69
70
71
VCAP_1
VDD
VSS
PA3
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VDD
VDD
VDD
VSS
VSS
MS41014V1
DS11853 Rev 9 53/226

94
Figure 21. STM32F723xx UFBGA144 ballout (with OTG PHY HS)
1 2 3 4 5 6 7 8 9 10 11 12
A PC13 PE3 PE2 PE1 PE0 PB4 PB3 PD6 PD7 PA15 PA14 PA13
PC14-
B OSC32_IN
PE4 PE5 PE6 PB9 PB5 PG15 PG12 PD5 PC11 PC10 PA12
PC15-
C OSC32_OUT
VBAT PF0 PF1 PB8 PB6 PG14 PG11 PD4 PC12 VDDUSB PA11
PH0 -
D OSC_IN
VSS VDD PF2 BOOT0 PB7 PG13 PG10 PD3 PD1 PA10 PA9
PH1 -
E OSC_OUT
PF3 PF4 PF5 PDR_ON VSS VSS PG9 PD2 PD0 PC9 PA8
F NRST PF7 PF6 VDD VDD VDD VDD VDD VDD VDD PC8 PC7
G PF10 PF9 PF8 VSS VDD VDD VDD VSS VCAP_2 VSS PG8 PC6
BYPASS_ VDD12OTG OTG_HS

H PC0 PC1 PC2 PC3
REG
VSS VCAP_1 PE11 PD11
HS _REXT
PG5
J VSSA PA0 PA4 PC4 PB2 PG1 PE10 PE12 PD10 PG4 PG3 PG2
K VREF- PA1 PA5 PC5 PF13 PG0 PE9 PE13 PD9 PD13 PD14 PD15
L VREF+ PA2 PA6 PB0 PF12 PF15 PE8 PE14 PD8 PD12 PB14 PB15
M VDDA PA3 PA7 PB1 PF11 PF14 PE7 PE15 PB10 PB11 PB12 PB13
MSv42000V1
54/226 DS11853 Rev 9

VDDSDMMC
PDR_ON
BOOT0
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
PG9
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
VDD
VDD
VSS
VSS
VSS
DD
PI7
PI6
PI5
PI4
PI3
PI2
V
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
141
140
152
151
150
149
148
147
146
145
144
143
142
139
138
137
136
135
134
133
PE2 1 132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8 7 126 VSS
PC13 8 125 VCAP_2
PC14 9 124 PA13
PC15 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDDUSB
PF4 20 113 VSS
PF5 21 112 PG8
22
LQFP176 111
VSS PG7
VDD 23 110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
PF10 28 105 PD15
PH0 29 104 PD14
PH1 30 103 VDD
NRST 31 102 VSS
PC0 32 101 PD13
PC1 33 100 PD12
PC2 34 99 PD11
PC3 35 98 PD10
VDD 36 97 PD9
VSSA 37 96 PD8
VREF+ 38 95 PB15
VDDA 39 94 PB14
PA0 40 93 PB13
PA1 41 92 PB12
PA2 42 91 VDD
PH2 43 90 VSS
PH3 44 89 PH12
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
80
69
70
71
72
73
74
75
76
77
78
79
88
81
82
83
84
85
86
87
VCAP_1
PC4
PC5
PF12
PF13
PF14
PF15
PH10
PG0
PG1
PH4
PH5
BYPASS_REG
PE10
PE12
PE13
PE14
PE15
PB10
PH6
PH7
PH8
PH9
PB0
PB1
PB2
PE7
PE8
PE9
VDD
VDD
VDD
VSS
VSS
PH11
PF11
PE11
PB11
PA3
PA4
PA5
PA6
PA7
VDD
MS41015V1
DS11853 Rev 9 55/226

94
VDDSDMMC
PDR_ON
BOOT0
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
PG9
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
VDD
VDD
VSS
VSS
VSS
DD
PI7
PI6
PI5
PI4
PI3
PI2
V
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
141
140
152
151
150
149
148
147
146
145
144
143
142
139
138
137
136
135
134
133
PE2 1 132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8 7 126 VSS
PC13 8 125 VCAP_2
PC14 9 124 PA13
PC15 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDDUSB
PF4 20 113 VSS
PF5 21 112 PG8
22
LQFP176 111
VSS PG5
VDD 23 with HS PHY 110 PG4
PF6 24 109 PG3
PF7 25 108 PG2
PF8 26 107 PD15
PF9 27 106 PD14
PF10 28 105 VDD
PH0 29 104 VSS
PH1 30 103 PD13
NRST 31 102 PD12
PC0 32 101 PD11
PC1 33 100 PD10
PC2 34 99 PD9
PC3 35 98 PD8
VDD 36 97 PB15
VSSA 37 96 PB14
VREF+ 38 95 VDD12OTGHS
VDDA 39 94 OTG_HS_REXT
PA0 40 93 PB13
PA1 41 92 PB12
PA2 42 91 VDD
PH2 43 90 VSS
PH3 44 89 PH12
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
80
69
70
71
72
73
74
75
76
77
78
79
88
81
82
83
84
85
86
87
VCAP_1
PC4
PC5
PF12
PF13
PF14
PF15
PH10
PG0
PG1
PH4
PH5
BYPASS_REG
PE10
PE12
PE13
PE14
PE15
PB10
PH6
PH7
PH8
PH9
PB0
PB1
PB2
PE7
PE8
PE9
VDD
VDD
VDD
VSS
VSS
PH11
PF11
PE11
PB11
PA3
PA4
PA5
PA6
PA7
VDD
MS41082V1
56/226 DS11853 Rev 9

Figure 24. STM32F723xx UFBGA176 ballout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
B PE4 PE5
PI7 PI6 PI5 VDD PDR_ON VDD VDD

C VBAT VDD PG9 PD5 PD1 PI3 PI2 PA11
SDMMC
D PC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10
PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9

E
F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP2 PC9 PA8
PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
G
H PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDDUSB PG8 PC6
PH1
J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6
K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
BYPASS_
L PF10 PF9 PF8 PH11 PH10 PD15 PG2
REG
M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13
N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10
P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15

R VDDA PA3 PA7 PB1 PB0 PF11
MS39130V1
DS11853 Rev 9 57/226

94
Figure 25. STM32F723xx UFBGA176 ballout (with OTG PHY HS)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
B PE4 PE5
PI7 PI6 PI5 VDD PDR_ON VDD VDD

C VBAT VDD PG9 PD5 PD1 PI3 PI2 PA11
SDMMC
D PC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10
PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9

E
F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP2 PC9 PA8
PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
G
H PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDDUSB PG8 PC6
PH1
VDD12 OTG_HS
J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD OTGHS _REXT
K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
BYPASS_
L PF10 PF9 PF8 PH11 PH10 PD15 PG2
REG
M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13
N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10
P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15

R VDDA PA3 PA7 PB1 PB0 PF11
MS42001V1
58/226 DS11853 Rev 9

Table 9. Legend/abbreviations used in the pinout table

Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
FTf 5V tolerant I/O, I2C Fm+ option.
I/O structure TTa 3.3 V tolerant I/O directly connected to ADC
B Dedicated BOOT pin
RST Bidirectional reset pin with weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Additional
Functions directly selected/enabled through peripheral registers
functions
DS11853 Rev 9 59/226

94
60/226
Pinouts and pin description

Table 10. STM32F722xx and STM32F723xx pin and ball definition
Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
(function after Alternate functions
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
reset)(1)
LQFP64
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
- 1 1 A2 1 1 C9 A2 A3 1 1 PE2 I/O FT - -
QUADSPI_BK1_IO2, FMC_A23,
EVENTOUT
TRACED0, SAI1_SD_B, FMC_A19,

- 2 2 A1 2 2 A10 A1 A2 2 2 PE3 I/O FT - -
EVENTOUT
DS11853 Rev 9
TRACED1, SPI4_NSS,
- 3 3 B1 3 3 D9 B1 B2 3 3 PE4 I/O FT - SAI1_FS_A, FMC_A20, -
EVENTOUT
TRACED2, TIM9_CH1,
- 4 4 B2 4 4 E8 B2 B3 4 4 PE5 I/O FT - SPI4_MISO, SAI1_SCK_A, -
FMC_A21, EVENTOUT
TRACED3, TIM1_BKIN2,
TIM9_CH2, SPI4_MOSI,
- 5 5 B3 5 5 B10 B3 B4 5 5 PE6 I/O FT - -
SAI1_SD_A, SAI2_MCK_B,
FMC_A22, EVENTOUT
1 6 6 C1 6 6 C10 C1 C2 6 6 VBAT S - - - -
(2) RTC_TAMP2/
- - - D2 7 - - D2 - - 7 PI8 I/O FT (3) EVENTOUT RTC_TS,
WKUP5
Table 10. STM32F722xx and STM32F723xx pin and ball definition (continued)
Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
RTC_TAMP1/
(2)
RTC_TS/
2 7 7 D1 8 7 D10 D1 A1 7 8 PC13 I/O FT (3) EVENTOUT
RTC_OUT,
WKUP4
(2)
PC14-
(3)
3 8 8 E1 9 8 E9 E1 B1 8 9 OSC32_IN I/O FT EVENTOUT OSC32_IN
(5)
(PC14)
PC15- (2)
DS11853 Rev 9
4 9 9 F1 10 9 E10 F1 C1 9 10 OSC32_OUT(P I/O FT (3)

EVENTOUT OSC32_OUT
C15) (5)
UART4_RX, CAN1_RX, FMC_D30,

- - - D3 11 - - D3 - - 11 PI9 I/O FT - -
EVENTOUT
- - - E3 12 - - E3 - - 12 PI10 I/O FT - FMC_D31, EVENTOUT -
(4)
- - - E4 13 - - E4 - - 13 PI11 I/O FT OTG_HS_ULPI_DIR, EVENTOUT WKUP6
- - - F2 14 - - F2 - - 14 VSS S - - - -

- - - F3 15 - - F3 - - 15 VDD S - - - -
- - 10 E2 16 - - E2 C3 10 16 PF0 I/O FTf - I2C2_SDA, FMC_A0, EVENTOUT -
- - 11 H3 17 - - H3 C4 11 17 PF1 I/O FTf - I2C2_SCL, FMC_A1, EVENTOUT -
I2C2_SMBA, FMC_A2,
- - 12 H2 18 - - H2 D4 12 18 PF2 I/O FT - -
EVENTOUT
- - 13 J2 19 - - J2 E2 13 19 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9
61/226
- - 14 J3 20 - - J3 E3 14 20 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14

62/226

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
- - 15 K3 21 - - K3 E4 15 21 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15

- 10 16 G2 22 10 F9 G2 D2 16 22 VSS S - - - -
- 11 17 G3 23 11 F10 G3 D3 17 23 VDD S - - - -
TIM10_CH1, SPI5_NSS,
- - 18 K2 24 - - K2 F3 18 24 PF6 I/O FT - SAI1_SD_B, UART7_RX, ADC3_IN4
QUADSPI_BK1_IO3, EVENTOUT
DS11853 Rev 9
TIM11_CH1, SPI5_SCK,
- - 19 K1 25 - - K1 F2 19 25 PF7 I/O FT - SAI1_MCLK_B, UART7_TX, ADC3_IN5
SPI5_MISO, SAI1_SCK_B,
- - 20 L3 26 - - L3 G3 20 26 PF8 I/O FT - UART7_RTS, TIM13_CH1, ADC3_IN6
SPI5_MOSI, SAI1_FS_B,
- - 21 L2 27 - - L2 G2 21 27 PF9 I/O FT - UART7_CTS, TIM14_CH1, ADC3_IN7
- - 22 L1 28 - - L1 G1 22 28 PF10 I/O FT - EVENTOUT ADC3_IN8

(5)
5 12 23 G1 29 12 G10 G1 D1 23 29 PH0-OSC_IN I/O FT EVENTOUT OSC_IN
Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
6 13 24 H1 30 13 H10 H1 E1 24 30 PH1-OSC_OUT I/O FT (5) EVENTOUT OSC_OUT

RS
7 14 25 J1 31 14 G9 J1 F1 25 31 NRST I/O - - -
T
ADC1_IN10,
(4) SAI2_FS_B, OTG_HS_ULPI_STP,
8 15 26 M2 32 15 F8 M2 H1 26 32 PC0 I/O FT ADC2_IN10,
FMC_SDNWE, EVENTOUT
ADC3_IN10
ADC1_IN11,
ADC2_IN11,
DS11853 Rev 9
TRACED0, SPI2_MOSI/I2S2_SD,
9 16 27 M3 33 16 H9 M3 H2 27 33 PC1 I/O FT - ADC3_IN11,
SAI1_SD_A, EVENTOUT
RTC_TAMP3,
WKUP3
ADC1_IN12,
(4) SPI2_MISO, OTG_HS_ULPI_DIR,
10 17 28 M4 34 17 J10 M4 H3 28 34 PC2 I/O FT ADC2_IN12,
FMC_SDNE0, EVENTOUT
ADC3_IN12
SPI2_MOSI/I2S2_SD, ADC1_IN13,

(4)
11 18 29 M5 35 18 F7 M5 H4 29 35 PC3 I/O FT OTG_HS_ULPI_NXT, ADC2_IN13,
FMC_SDCKE0, EVENTOUT ADC3_IN13
- - 30 - 36 - J7 - F10 30 36 VDD S - - - -
12 19 31 M1 37 19 K10 M1 J1 31 37 VSSA S - - - -
- - - N1 - - - N1 K1 - - VREF- S - - - -
13 20 32 P1 38 20 J9 P1 L1 32 38 VREF+ S - - - -
63/226
- 21 33 R1 39 21 K9 R1 M1 33 39 VDDA S - - - -
64/226

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
TIM2_CH1/TIM2_ETR, TIM5_CH1, ADC1_IN0,

(5) TIM8_ETR, USART2_CTS, ADC2_IN0,
14 22 34 N3 40 22 G8 N3 J2 34 40 PA0-WKUP I/O FT
UART4_TX, SAI2_SD_B, ADC3_IN0,
EVENTOUT WKUP1
TIM2_CH2, TIM5_CH2,
ADC1_IN1,
DS11853 Rev 9
USART2_RTS, UART4_RX,
15 23 35 N2 41 23 J8 N2 K2 35 41 PA1 I/O FT - ADC2_IN1,
QUADSPI_BK1_IO3,
ADC3_IN1
SAI2_MCK_B, EVENTOUT
ADC1_IN2,
TIM2_CH3, TIM5_CH3, TIM9_CH1,
ADC2_IN2,
16 24 36 P2 42 24 H8 P2 L2 36 42 PA2 I/O FT - USART2_TX, SAI2_SCK_B,
ADC3_IN2,
EVENTOUT
WKUP2
LPTIM1_IN2, QUADSPI_BK2_IO0,
- - - F4 43 - - F4 - - 43 PH2 I/O FT - SAI2_SCK_B, FMC_SDCKE0, -
EVENTOUT
QUADSPI_BK2_IO1,
- - - G4 44 - - G4 - - 44 PH3 I/O FT - SAI2_MCK_B, FMC_SDNE0, -
EVENTOUT
(4) I2C2_SCL, OTG_HS_ULPI_NXT,

- - - H4 45 - - H4 - - 45 PH4 I/O FTf -
EVENTOUT
I2C2_SDA, SPI5_NSS,
- - - J4 46 - - J4 - - 46 PH5 I/O FTf - -
FMC_SDNWE, EVENTOUT
Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
TIM2_CH4, TIM5_CH4, TIM9_CH2, ADC1_IN3,

17 25 37 R2 47 25 H7 R2 M2 37 47 PA3 I/O FT (4)
USART2_RX, OTG_HS_ULPI_D0, ADC2_IN3,
EVENTOUT ADC3_IN3
18 26 38 - - 26 K8 - G4 38 - VSS S - - - -
- - - L4 48 - - L4 H5 - 48 BYPASS_REG I FT - - -
19 27 39 K4 49 27 - K4 F4 39 49 VDD S - - - -
SPI1_NSS/I2S1_WS,
ADC1_IN4,
DS11853 Rev 9
SPI3_NSS/I2S3_WS,
20 28 40 N4 50 28 G7 N4 J3 40 50 PA4 I/O TTa - ADC2_IN4,
USART2_CK, OTG_HS_SOF,
DAC_OUT1
EVENTOUT
TIM2_CH1/TIM2_ETR, ADC1_IN5,
21 29 41 P4 51 29 F6 P4 K3 41 51 PA5 I/O TTa (4) TIM8_CH1N, SPI1_SCK/I2S1_CK, ADC2_IN5,
OTG_HS_ULPI_CK, EVENTOUT DAC_OUT2
TIM1_BKIN, TIM3_CH1,
ADC1_IN6,
22 30 42 P3 52 30 G6 P3 L3 42 52 PA6 I/O FT - TIM8_BKIN, SPI1_MISO,
ADC2_IN6
TIM13_CH1, EVENTOUT

TIM1_CH1N, TIM3_CH2,
TIM8_CH1N, ADC1_IN7,
23 31 43 R3 53 31 K7 R3 M3 43 53 PA7 I/O FT -
SPI1_MOSI/I2S1_SD, TIM14_CH1, ADC2_IN7
FMC_SDNWE, EVENTOUT
I2S1_MCK, FMC_SDNE0, ADC1_IN14,

24 32 44 N5 54 32 H6 N5 J4 44 54 PC4 I/O FT -
EVENTOUT ADC2_IN14
ADC1_IN15,
- 33 45 P5 55 33 J6 P5 K4 45 55 PC5 I/O FT - FMC_SDCKE0, EVENTOUT
ADC2_IN15
65/226
66/226

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
(4) ADC1_IN8,
25 34 46 R5 56 34 F5 R5 L4 46 56 PB0 I/O FT TIM8_CH2N, UART4_CTS,
ADC2_IN8
OTG_HS_ULPI_D1, EVENTOUT
(4) ADC1_IN9,
26 35 47 R4 57 35 G5 R4 M4 47 57 PB1 I/O FT TIM8_CH3N, OTG_HS_ULPI_D2,
ADC2_IN9
EVENTOUT
SAI1_SD_A, SPI3_MOSI/I2S3_SD,
27 36 48 M6 58 36 K6 M6 J5 48 58 PB2 I/O FT - -
DS11853 Rev 9
QUADSPI_CLK, EVENTOUT
SPI5_MOSI, SAI2_SD_B,
- - 49 R6 59 - - R6 M5 49 59 PF11 I/O FT - -
FMC_SDNRAS, EVENTOUT
- - 50 P6 60 - - P6 L5 50 60 PF12 I/O FT - FMC_A6, EVENTOUT -

- - 51 M8 61 - - M8 - 51 61 VSS S - - - -
- - 52 N8 62 - - N8 G5 52 62 VDD S - - - -
- - 53 N6 63 - - N6 K5 53 63 PF13 I/O FT - FMC_A7, EVENTOUT -
- - 54 R7 64 - - R7 M6 54 64 PF14 I/O FT - FMC_A8, EVENTOUT -
- - 55 P7 65 - - P7 L6 55 65 PF15 I/O FT - FMC_A9, EVENTOUT -
- - 56 N7 66 - - N7 K6 56 66 PG0 I/O FT - FMC_A10, EVENTOUT -
- - 57 M7 67 - - M7 J6 57 67 PG1 I/O FT - FMC_A11, EVENTOUT -
TIM1_ETR, UART7_Rx,
- 37 58 R8 68 37 J5 R8 M7 58 68 PE7 I/O FT - QUADSPI_BK2_IO0, FMC_D4, -
EVENTOUT
Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
TIM1_CH1N, UART7_Tx,
- 38 59 P8 69 38 H5 P8 L7 59 69 PE8 I/O FT - QUADSPI_BK2_IO1, FMC_D5, -
EVENTOUT
TIM1_CH1, UART7_RTS,
- 39 60 P9 70 39 K5 P9 K7 60 70 PE9 I/O FT - QUADSPI_BK2_IO2, FMC_D6, -
EVENTOUT
- - 61 M9 71 - - M9 H6 61 71 VSS S - - - -
- - 62 N9 72 - - N9 G6 62 72 VDD S - - - -
DS11853 Rev 9
TIM1_CH2N, UART7_CTS,
- 40 63 R9 73 40 E4 R9 J7 63 73 PE10 I/O FT - QUADSPI_BK2_IO3, FMC_D7, -
EVENTOUT
TIM1_CH2, SPI4_NSS,
- 41 64 P10 74 41 G4 P10 H8 64 74 PE11 I/O FT - -
SAI2_SD_B, FMC_D8, EVENTOUT
TIM1_CH3N, SPI4_SCK,
- 42 65 R10 75 42 H4 R10 J8 65 75 PE12 I/O FT - SAI2_SCK_B, FMC_D9, -
EVENTOUT
TIM1_CH3, SPI4_MISO,

- 43 66 N11 76 43 J4 N11 K8 66 76 PE13 I/O FT - SAI2_FS_B, FMC_D10, -
EVENTOUT
TIM1_CH4, SPI4_MOSI,
- 44 67 P11 77 44 K4 P11 L8 67 77 PE14 I/O FT - SAI2_MCK_B, FMC_D11,, -
EVENTOUT
TIM1_BKIN, FMC_D12,
- 45 68 R11 78 45 F4 R11 M8 68 78 PE15 I/O FT - -
EVENTOUT
67/226
68/226

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
TIM2_CH3, I2C2_SCL,
28 46 69 R12 79 46 G3 R12 M9 69 79 PB10 I/O FTf (4)
SPI2_SCK/I2S2_CK, USART3_TX, -
TIM2_CH4, I2C2_SDA,
(4)
29 47 70 R13 80 47 H3 R13 M10 70 80 PB11 I/O FTf USART3_RX, OTG_HS_ULPI_D4, -
EVENTOUT
DS11853 Rev 9
30 48 71 M10 81 48 J3 M10 H7 71 81 VCAP_1 S - - - -

31 49 - - - 49 K3 - - - - VSS S - - - -
32 50 72 N10 82 50 K2 N10 G7 72 82 VDD S - - - -
I2C2_SMBA, SPI5_SCK,
- - - M11 83 - - M11 - - 83 PH6 I/O FT - TIM12_CH1, FMC_SDNE1, -
EVENTOUT
I2C3_SCL, SPI5_MISO,
- - - N12 84 - - N12 - - 84 PH7 I/O FTf - -
FMC_SDCKE1, EVENTOUT
- - - M12 85 - - M12 - - 85 PH8 I/O FTf - I2C3_SDA, FMC_D16, EVENTOUT -
I2C3_SMBA, TIM12_CH2,
- - - M13 86 - - M13 - - 86 PH9 I/O FT - -
FMC_D17, EVENTOUT
- - - L13 87 - - L13 - - 87 PH10 I/O FT - TIM5_CH1, FMC_D18, EVENTOUT -
- - - L12 88 - - L12 - - 88 PH11 I/O FT - TIM5_CH2, FMC_D19, EVENTOUT -
- - - K12 89 - - K12 - - 89 PH12 I/O FT - TIM5_CH3, FMC_D20, EVENTOUT -

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
- - - H12 90 - - H12 - - 90 VSS S - - - -

- - - J12 91 - K2 J12 - - 91 VDD S - - - -
TIM1_BKIN, I2C2_SMBA,
(4) SPI2_NSS/I2S2_WS,
33 51 73 P12 92 51 J2 P12 M11 73 92 PB12 I/O FT -
USART3_CK, OTG_HS_ULPI_D5,
OTG_HS_ID, EVENTOUT
DS11853 Rev 9
TIM1_CH1N, SPI2_SCK/I2S2_CK,
(4)
34 52 74 P13 93 52 H2 P13 M12 74 93 PB13 I/O FT USART3_CTS, OTG_HS_VBUS
- - - - - 53 G2 J15 H11 75 94 OTG_HS_REXT - - - USB HS OTG PHY calibration resistor

- - - - - 54 - - - - - VDDPHYHS - - - - -
- - - - - 55 G1 J14 H10 76 95 VDD12OTGHS - - - - -
TIM1_CH2N, TIM8_CH2N,
SPI2_MISO, USART3_RTS,
35 53 75 R14 94 - - - - - - PB14 I/O FT - -

TIM12_CH1, SDMMC2_D0,
OTG_HS_DM, EVENTOUT
- - - - - 56 J1 R14 L11 77 96 PB14 I/O FT - OTG_HS_DM -

69/226
70/226

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N,
36 54 76 R15 95 - - - - - - PB15 I/O FT - SPI2_MOSI/I2S2_SD, TIM12_CH2, -
SDMMC2_D1, OTG_HS_DP,
EVENTOUT
- - - - - 57 H1 R15 L12 78 97 PB15 I/O FT - OTG_HS_DP -

DS11853 Rev 9
USART3_TX, FMC_D13,
- 55 77 P15 96 - - P15 L9 79 98 PD8 I/O FT - -
EVENTOUT
USART3_RX, FMC_D14,
- 56 78 P14 97 - - P14 K9 80 99 PD9 I/O FT - -
EVENTOUT
USART3_CK, FMC_D15,
- 57 79 N15 98 - - N15 J9 81 100 PD10 I/O FT - -
EVENTOUT
USART3_CTS,
- 58 80 N14 99 58 F3 N14 H9 82 101 PD11 I/O FT - QUADSPI_BK1_IO0, SAI2_SD_A, -
FMC_A16/FMC_CLE, EVENTOUT
TIM4_CH1, LPTIM1_IN1,
USART3_RTS,
- 59 81 N13 100 59 F2 N13 L10 83 102 PD12 I/O FT - -
QUADSPI_BK1_IO1, SAI2_FS_A,
FMC_A17/FMC_ALE, EVENTOUT
TIM4_CH2, LPTIM1_OUT,
QUADSPI_BK1_IO3,
- 60 82 M15 101 60 E3 M15 K10 84 103 PD13 I/O FT - -
SAI2_SCK_A, FMC_A18,
EVENTOUT
- - 83 - 102 - - - G8 85 104 VSS S - - - -
Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
- - 84 J13 103 - - J13 F8 86 105 VDD S - - - -

TIM4_CH3, UART8_CTS,
- 61 85 M14 104 61 F1 M14 K11 87 106 PD14 I/O FT - -
FMC_D0, EVENTOUT
TIM4_CH4, UART8_RTS,
- 62 86 L14 105 62 E2 L14 K12 88 107 PD15 I/O FT - -
FMC_D1, EVENTOUT
- - 87 L15 106 - - L15 J12 89 108 PG2 I/O FT - FMC_A12, EVENTOUT -
- - 88 K15 107 - - K15 J11 90 109 PG3 I/O FT - FMC_A13, EVENTOUT -
DS11853 Rev 9
- - 89 K14 108 - - K14 J10 91 110 PG4 I/O FT - FMC_A14/FMC_BA0, EVENTOUT -

- - 90 K13 109 - - K13 H12 92 111 PG5 I/O FT - FMC_A15/FMC_BA1, EVENTOUT -
- - 91 J15 110 - - - - - - PG6 I/O FT - EVENTOUT -
USART6_CK, FMC_INT,
- - 92 J14 111 - - - - - - PG7 I/O FT - -
EVENTOUT
USART6_RTS, FMC_SDCLK,
- - 93 H14 112 - - H14 G11 93 112 PG8 I/O FT - -
EVENTOUT
- - 94 G12 113 - - G12 - 94 113 VSS S - - - -

- - - - - - - - F10 - - VDD - - - - -
- - 95 H13 114 - K1 H13 C11 95 114 VDDUSB S - - - -
TIM3_CH1, TIM8_CH1, I2S2_MCK,
37 63 96 H15 115 63 E1 H15 G12 96 115 PC6 I/O FT - USART6_TX, SDMMC2_D6, -
SDMMC1_D6, EVENTOUT
TIM3_CH2, TIM8_CH2, I2S3_MCK,
38 64 97 G15 116 64 D4 G15 F12 97 116 PC7 I/O FT - USART6_RX, SDMMC2_D7, -
71/226
SDMMC1_D7, EVENTOUT
72/226

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
TRACED1, TIM3_CH3, TIM8_CH3,

39 65 98 G14 117 65 D2 G14 F11 98 117 PC8 I/O FT - UART5_RTS, USART6_CK, -
SDMMC1_D0, EVENTOUT
MCO2, TIM3_CH4, TIM8_CH4,
I2C3_SDA, I2S_CKIN,
40 66 99 F14 118 66 D1 F14 E11 99 118 PC9 I/O FTf - -
UART5_CTS, QUADSPI_BK1_IO0,
SDMMC1_D1, EVENTOUT
MCO1, TIM1_CH1, TIM8_BKIN2,
DS11853 Rev 9
41 67 100 F15 119 67 D3 F15 E12 100 119 PA8 I/O FTf - I2C3_SCL, USART1_CK, -
OTG_FS_SOF, EVENTOUT
TIM1_CH2, I2C3_SMBA,
42 68 101 E15 120 68 C3 E15 D12 101 120 PA9 I/O FT - SPI2_SCK/I2S2_CK, USART1_TX, OTG_FS_VBUS
EVENTOUT
TIM1_CH3, USART1_RX,
43 69 102 D15 121 69 C2 D15 D11 102 121 PA10 I/O FT - -
OTG_FS_ID, EVENTOUT
TIM1_CH4, USART1_CTS,
44 70 103 C15 122 70 C1 C15 C12 103 122 PA11 I/O FT - CAN1_RX, OTG_FS_DM, -
EVENTOUT
TIM1_ETR, USART1_RTS,
45 71 104 B15 123 71 B2 B15 B12 104 123 PA12 I/O FT - SAI2_FS_B, CAN1_TX, -
OTG_FS_DP, EVENTOUT
PA13(JTMS-
46 72 105 A15 124 72 B1 A15 A12 105 124 I/O FT - JTMS-SWDIO, EVENTOUT -
SWDIO)
- 73 106 F13 125 73 B3 F13 G9 106 125 VCAP_2 S - - - -
47 74 107 F12 126 74 A2 F12 G10 107 126 VSS S - - - -
48 75 108 G13 127 75 A1 G13 F9 108 127 VDD S - - - -
Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
TIM8_CH1N, UART4_TX,
- - - E12 128 - - E12 - - 128 PH13 I/O FT - -
CAN1_TX, FMC_D21, EVENTOUT
TIM8_CH2N, UART4_RX,
- - - E13 129 - - E13 - - 129 PH14 I/O FT - -
CAN1_RX, FMC_D22, EVENTOUT
TIM8_CH3N, FMC_D23,
- - - D13 130 - - D13 - - 130 PH15 I/O FT - -
EVENTOUT
TIM5_CH4, SPI2_NSS/I2S2_WS,
- - - E14 131 - - E14 - - 131 PI0 I/O FT - -
DS11853 Rev 9
FMC_D24, EVENTOUT
TIM8_BKIN2, SPI2_SCK/I2S2_CK,
- - - D14 132 - - D14 - - 132 PI1 I/O FT - -
FMC_D25, EVENTOUT
TIM8_CH4, SPI2_MISO,
- - - C14 133 - - C14 - - 133 PI2 I/O FT - -
FMC_D26, EVENTOUT
TIM8_ETR, SPI2_MOSI/I2S2_SD,
- - - C13 134 - - C13 - - 134 PI3 I/O FT - -
FMC_D27, EVENTOUT
- - - D9 135 - - D9 - - 135 VSS S - - - -

- - - C9 136 - - C9 - - 136 VDD S - - - -
PA14(JTCK-
49 76 109 A14 137 76 C4 A14 A11 109 137 I/O FT - JTCK-SWCLK, EVENTOUT -
SWCLK)
JTDI, TIM2_CH1/TIM2_ETR,
SPI1_NSS/I2S1_WS,
50 77 110 A13 138 77 B4 A13 A10 110 138 PA15(JTDI) I/O FT - -
SPI3_NSS/I2S3_WS, UART4_RTS,
EVENTOUT
73/226
74/226

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
SPI3_SCK/I2S3_CK, USART3_TX,
51 78 111 B14 139 78 A3 B14 B11 111 139 PC10 I/O FT - UART4_TX, QUADSPI_BK1_IO1, -
SDMMC1_D2, EVENTOUT
SPI3_MISO, USART3_RX,
52 79 112 B13 140 79 C5 B13 B10 112 140 PC11 I/O FT - UART4_RX, QUADSPI_BK2_NCS, -
SDMMC1_D3, EVENTOUT
TRACED3, SPI3_MOSI/I2S3_SD,
DS11853 Rev 9
53 80 113 A12 141 80 D5 A12 C10 113 141 PC12 I/O FT - USART3_CK, UART5_TX, -
SDMMC1_CK, EVENTOUT
- 81 114 B12 142 81 B5 B12 E10 114 142 PD0 I/O FT - CAN1_RX, FMC_D2, EVENTOUT -
- 82 115 C12 143 82 A4 C12 D10 115 143 PD1 I/O FT - CAN1_TX, FMC_D3, EVENTOUT -
TRACED2, TIM3_ETR,
54 83 116 D12 144 83 E5 D12 E9 116 144 PD2 I/O FT - UART5_RX, SDMMC1_CMD, -
EVENTOUT
SPI2_SCK/I2S2_CK,
- 84 117 D11 145 84 C6 D11 D9 117 145 PD3 I/O FT - USART2_CTS, FMC_CLK, -
EVENTOUT
USART2_RTS, FMC_NOE,
- 85 118 D10 146 85 B6 D10 C9 118 146 PD4 I/O FT - -
EVENTOUT
USART2_TX, FMC_NWE,
- 86 119 C11 147 86 A5 C11 B9 119 147 PD5 I/O FT - -
EVENTOUT
- - 120 D8 148 - - D8 E7 120 148 VSS S - - - -
- - 121 C8 149 - - C8 F7 121 149 VDDSDMMC S - - - -
Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
SPI3_MOSI/I2S3_SD, SAI1_SD_A,
- 87 122 B11 150 87 D6 B11 A8 122 150 PD6 I/O FT - USART2_RX, SDMMC2_CK, -
FMC_NWAIT, EVENTOUT
USART2_CK SDMMC2_CMD,
- 88 123 A11 151 88 E6 A11 A9 123 151 PD7 I/O FT - -
FMC_NE1, EVENTOUT
USART6_RX, QUADSPI_BK2_IO2,
- - 124 C10 152 - - C10 E8 124 152 PG9 I/O FT - SAI2_FS_B, SDMMC2_D0, -
FMC_NE2/FMC_NCE, EVENTOUT
DS11853 Rev 9
SAI2_SD_B, SDMMC2_D1,
- - 125 B10 153 - - B10 D8 125 153 PG10 I/O FT - -
FMC_NE3, EVENTOUT
SDMMC2_D2, FMC_INT,
- - 126 B9 154 - - B9 C8 126 154 PG11 I/O FT - -
EVENTOUT

LPTIM1_IN1, USART6_RTS,
- - 127 B8 155 - - B8 B8 127 155 PG12 I/O FT - SDMMC2_D3, FMC_NE4, -
EVENTOUT
TRACED0, LPTIM1_OUT,
- - 128 A8 156 - - A8 D7 128 156 PG13 I/O FT - USART6_CTS, FMC_A24, -
75/226
EVENTOUT
76/226

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
TRACED1, LPTIM1_ETR,
- - 129 A7 157 - - A7 C7 129 157 PG14 I/O FT - USART6_TX, QUADSPI_BK2_IO3, -
FMC_A25, EVENTOUT
- - 130 D7 158 - - D7 - 130 158 VSS S - - - -

- - 131 C7 159 - - C7 F6 131 159 VDD S - - - -
DS11853 Rev 9
USART6_CTS, FMC_SDNCAS,
- - 132 B7 160 - - B7 B7 132 160 PG15 I/O FT - -
EVENTOUT
JTDO/TRACESWO, TIM2_CH2,
PB3(JTDO/TRA SPI1_SCK/I2S1_CK,
55 89 133 A10 161 89 A6 A10 A7 133 161 I/O FT - -
CESWO) SPI3_SCK/I2S3_CK,
SDMMC2_D2, EVENTOUT
NJTRST, TIM3_CH1, SPI1_MISO,

56 90 134 A9 162 90 B7 A9 A6 134 162 PB4(NJTRST) I/O FT - SPI3_MISO, SPI2_NSS/I2S2_WS, -
SDMMC2_D3, EVENTOUT
TIM3_CH2, I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
(4)
57 91 135 A6 163 91 C7 A6 B6 135 163 PB5 I/O FT SPI3_MOSI/I2S3_SD, -
OTG_HS_ULPI_D7,
FMC_SDCKE1, EVENTOUT
Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
TIM4_CH1, I2C1_SCL,
USART1_TX,
58 92 136 B6 164 92 D7 B6 C6 136 164 PB6 I/O FTf - -
QUAD SPI_BK1_NCS,
FMC_SDNE1, EVENTOUT
TIM4_CH2, I2C1_SDA,
59 93 137 B5 165 93 B8 B5 D6 137 165 PB7 I/O FTf - USART1_RX, FMC_NL, -
EVENTOUT
DS11853 Rev 9
60 94 138 D6 166 94 A7 D6 D5 138 166 BOOT I B - - VPP
TIM4_CH3, TIM10_CH1,
I2C1_SCL, CAN1_RX,
61 95 139 A5 167 95 C8 A5 C5 139 167 PB8 I/O FTf - -
SDMMC2_D4, SDMMC1_D4,
EVENTOUT
TIM4_CH4, TIM11_CH1,
I2C1_SDA, SPI2_NSS/I2S2_WS,
62 96 140 B4 168 96 D8 B4 B5 140 168 PB9 I/O FTf - -

CAN1_TX, SDMMC2_D5,
SDMMC1_D5, EVENTOUT
TIM4_ETR, LPTIM1_ETR,
- 97 141 A4 169 97 E7 A4 A5 141 169 PE0 I/O FT - UART8_Rx, SAI2_MCK_A, -
FMC_NBL0, EVENTOUT
77/226
78/226

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
LPTIM1_IN2, UART8_Tx,
- 98 142 A3 170 98 B9 A3 A4 142 170 PE1 I/O FT - -
FMC_NBL1, EVENTOUT
63 99 - D5 - 99 A8 D5 E6 - - VSS S - - - -
- - 143 C6 171 - - C6 E5 143 171 PDR_ON S - - - -
64 100 144 C5 172 100 A9 C5 F5 144 172 VDD S - - - -
DS11853 Rev 9
TIM8_BKIN, SAI2_MCK_A,
- - - D4 173 - - D4 - - 173 PI4 I/O FT - -
FMC_NBL2, EVENTOUT
TIM8_CH1, SAI2_SCK_A,
- - - C4 174 - - C4 - - 174 PI5 I/O FT - -
FMC_NBL3, EVENTOUT
TIM8_CH2, SAI2_SD_A,
- - - C3 175 - - C3 - - 175 PI6 I/O FT - -
FMC_D28, EVENTOUT
TIM8_CH3, SAI2_FS_A,
- - - C2 176 - - C2 - - 176 PI7 I/O FT - -
FMC_D29, EVENTOUT
- - - F6 - - - F6 - - - VSS S - - - -
- - - F7 - - - F7 - - - VSS S - - - -
Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
- - - F8 - - - F8 - - - VSS S - - - -
- - - F9 - - - F9 - - - VSS S - - - -
- - - F10 - - - F10 - - - VSS S - - - -
- - - G6 - - - G6 - - - VSS S - - - -
- - - G7 - - - G7 - - - VSS S - - - -
- - - G8 - - - G8 - - - VSS S - - - -
DS11853 Rev 9
- - - G9 - - - G9 - - - VSS S - - - -
- - - G10 - - - G10 - - - VSS S - - - -
- - - H6 - - - H6 - - - VSS S - - - -
- - - H7 - - - H7 - - - VSS S - - - -
- - - H8 - - - H8 - - - VSS S - - - -
- - - H9 - - - H9 - - - VSS S - - - -
- - - H10 - - - H10 - - - VSS S - - - -
- - - J6 - - - J6 - - - VSS S - - - -

- - - J7 - - - J7 - - - VSS S - - - -
- - - J8 - - - J8 - - - VSS S - - - -
- - - J9 - - - J9 - - - VSS S - - - -
- - - J10 - - - J10 - - - VSS S - - - -
- - - K6 - - - K6 - - - VSS S - - - -
- - - K7 - - - K7 - - - VSS S - - - -
79/226
- - - K8 - - - K8 - - - VSS S - - - -
80/226

Pin number
I/O structure
Pin type
Pin name
Notes
Additional
WLCSP100
UFBGA176
UFBGA176
UFBGA144
functions
LQFP100
LQFP144
LQFP176
LQFP100
LQFP144
LQFP176
LQFP64 reset)(1)
- - - K9 - - - K9 - - - VSS S - - - -
- - - K10 - - - K10 - - - VSS S - - - -
1. Function availability depends on the chosen device.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8
in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
DS11853 Rev 9
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the
main reset).
4. ULPI signals not available on the STM32F723xx devices.
5. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low).
Table 11. FMC pin definition

NOR/PSRAM/ NOR/PSRAM
Pin name NAND16 SDRAM
SRAM Mux
PF0 A0 - - A0
PF1 A1 - - A1
PF2 A2 - - A2
PF3 A3 - - A3
PF4 A4 - - A4
PF5 A5 - - A5
PF12 A6 - - A6
PF13 A7 - - A7
PF14 A8 - - A8
PF15 A9 - - A9
PG0 A10 - - A10
PG1 A11 - - A11
PG2 A12 - - A12
PG3 A13 - - -
PG4 A14 - - BA0
PG5 A15 - - BA1
PD11 A16 A16 CLE -
PD12 A17 A17 ALE -
PD13 A18 A18 - -
PE3 A19 A19 - -
PE4 A20 A20 - -
PE5 A21 A21 - -
PE6 A22 A22 - -
PE2 A23 A23 - -
PG13 A24 A24 - -
PG14 A25 A25 - -
PD14 D0 DA0 D0 D0
PD15 D1 DA1 D1 D1
PD0 D2 DA2 D2 D2
PD1 D3 DA3 D3 D3
PE7 D4 DA4 D4 D4
PE8 D5 DA5 D5 D5
PE9 D6 DA6 D6 D6
PE10 D7 DA7 D7 D7
DS11853 Rev 9 81/226

94
Table 11. FMC pin definition (continued)

SRAM Mux
PE11 D8 DA8 D8 D8
PE12 D9 DA9 D9 D9
PE13 D10 DA10 D10 D10
PE14 D11 DA11 D11 D11
PE15 D12 DA12 D12 D12
PD8 D13 DA13 D13 D13
PD9 D14 DA14 D14 D14
PD10 D15 DA15 D15 D15
PH8 D16 - - D16
PH9 D17 - - D17
PH10 D18 - - D18
PH11 D19 - - D19
PH12 D20 - - D20
PH13 D21 - - D21
PH14 D22 - - D22
PH15 D23 - - D23
PI0 D24 - - D24
PI1 D25 - - D25
PI2 D26 - - D26
PI3 D27 - - D27
PI6 D28 - - D28
PI7 D29 - - D29
PI9 D30 - - D30
PI10 D31 - - D31
PD7 NE1 NE1 - -
PG9 NE2 NE2 NCE -
PG10 NE3 NE3 - -
PG11 - - - -
PG12 NE4 NE4 - -
PD3 CLK CLK - -
PD4 NOE NOE NOE -
PD5 NWE NWE NWE -
PD6 NWAIT NWAIT NWAIT -
PB7 NADV NADV - -
82/226 DS11853 Rev 9

Table 11. FMC pin definition (continued)

SRAM Mux
PF6 - - - -
PF7 - - - -
PF8 - - - -
PF9 - - - -
PF10 - - - -
PG6 - - - -
PG7 - - INT -
PE0 NBL0 NBL0 - NBL0
PE1 NBL1 NBL1 - NBL1
PI4 NBL2 - - NBL2
PI5 NBL3 - - NBL3
PG8 - - - SDCLK
PC0 - - - SDNWE
PF11 - - - SDNRAS
PG15 - - - SDNCAS
PH2 - - - SDCKE0
PH3 - - - SDNE0
PH6 - - - SDNE1
PH7 - - - SDCKE1
PH5 - - - SDNWE
PC2 - - - SDNE0
PC3 - - - SDCKE0
PB5 - - - SDCKE1
PB6 - - - SDNE1
DS11853 Rev 9 83/226

94
84/226

Table 12. STM32F722xx and STM32F723xx alternate function mapping
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15
SPI2/I2S2/ CAN1/ SAI2/

Port SPI1/I2S1/ SPI2/I2S2/S UART7/
SPI3/I2S3/ SAI2/USART6 TIM12/13/14 QUADSPI/
TIM8/9/10/11/ I2C1/2/3/ SPI2/I2S2/ PI3/I2S3/ FMC/
SYS TIM1/2 TIM3/4/5 SPI3/I2S3/ /UART4/5/7/8/ /QUADSPI/ SDMMC2/ SDMMC2 SYS
LPTIM1 USART1 SPI3/I2S3/ USART1/2/3/ SDMMC1/
SAI1/ OTG1_FS FMC/ OTG2_HS/
SPI4/5 UART5 OTG2_FS
UART4 OTG2_HS OTG1_FS
TIM2_CH1
USART2_ EVEN
PA0 - /TIM2_ TIM5_CH1 TIM8_ETR - - - UART4_ TX - SAI2_SD_B - -
CTS TOUT
ETR
USART2_ QUADSPI_ SAI2_ EVEN

PA1 - TIM2_CH2 TIM5_CH2 - - - - UART4_RX - -
RTS BK1_IO3 MCK_B TOUT
EVEN
PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_TX SAI2_SCK_B - - - -
TOUT
OTG_HS_ EVEN
PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - USART2_RX - - - -
ULPI_D0 TOUT
DS11853 Rev 9
SPI1_NSS SPI3_NSS OTG_HS_ EVEN

PA4 - - - - - USART2_CK - - - -
/I2S1_WS /I2S3_WS SOF TOUT
TIM2_CH1
SPI1_SCK OTG_HS_ EVEN
PA5 - /TIM2_ - TIM8_CH1N - - - - - - -
Port A
/I2S1_CK ULPI_CK TOUT

ETR
TIM1_ SPI1_ EVEN

PA6 - TIM3_CH1 TIM8_BKIN - - - - TIM13_CH1 - - -
BKIN MISO TOUT
SPI1_MO
TIM1_ FMC_SDN EVEN
PA7 - TIM3_CH2 TIM8_CH1N - SI/I2S1_S - - - TIM14_CH1 - -
CH1N WE TOUT
D
OTG_FS EVEN
PA8 MCO1 TIM1_CH1 - TIM8_BKIN2 I2C3_SCL - - USART1_CK - - - -
_SOF TOUT
I2C3_SMB SPI2_SCK EVEN

PA9 - TIM1_CH2 - - - USART1_TX - - - - -
A /I2S2_CK TOUT
EVEN
PA10 - TIM1_CH3 - - - - - USART1_RX - - OTG_FS_ID - -
TOUT
USART1_ OTG_FS_ EVEN

PA11 - TIM1_CH4 - - - - - - CAN1_RX - -
CTS DM TOUT
Table 12. STM32F722xx and STM32F723xx alternate function mapping (continued)

USART1_ EVEN
PA12 - TIM1_ETR - - - - - SAI2_FS_B CAN1_TX OTG_FS_DP - -
RTS TOUT
JTMS- EVEN
PA13 - - - - - - - - - - - -
SWDIO TOUT
Port A
JTCK- EVEN
PA14 - - - - - - - - - - - -
SWCLK TOUT
TIM2_CH1
SPI1_NSS SPI3_NSS EVEN
PA15 JTDI /TIM2_ - - - - UART4_RTS - - - -
/I2S1_WS /I2S3_WS TOUT
ETR
TIM1_ OTG_HS_ EVEN

PB0 -
CH2N
TIM3_CH3 TIM8_CH2N - - - - UART4_CTS - ULPI_D1
- -
TOUT
DS11853 Rev 9
TIM1_ OTG_HS_ EVEN

PB1 -
CH3N
TIM3_CH4 TIM8_CH3N - - - - - - ULPI_D2
- -
TOUT
SAI1_ SPI3_MOSI QUADSPI_ EVEN

PB2 - - - - - -
SD_A /I2S3_SD
- CLK
- - -
TOUT
JTDO/TR SPI1_SCK SPI3_SCK SDMMC2 EVEN

PB3 TIM2_CH2 - - - - - - - -
ACESWO /I2S1_CK /I2S3_CK _D2 TOUT
SPI1_ SPI3_ SPI2_NSS SDMMC2 EVEN

Port B
PB4 NJTRST - TIM3_CH1 - - - - - -

MISO MISO /I2S2_WS _D3 TOUT
SPI1_ SPI3_
I2C1_ OTG_HS_ FMC_ EVEN
PB5 - - TIM3_CH2 - MOSI/ MOSI/ - - - -
SMBA ULPI_D7 SDCKE1 TOUT
I2S1_SD I2S3_SD

QUADSPI_ FMC_ EVEN
PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - - -
BK1_NCS SDNE1 TOUT
EVEN
PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - - - - FMC_NL
TOUT
SDMMC2_ SDMMC1 EVEN

PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - - - - CAN1_RX -
D4 _D4 TOUT
85/226
86/226


SPI2_NSS SDMMC2_ SDMMC1 EVEN

PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA - - - CAN1_TX -
/I2S2_WS D5 _D5 TOUT
SPI2_SCK OTG_HS_ EVEN

PB10 - TIM2_CH3 - - I2C2_SCL - USART3_TX - - - -
/I2S2_CK ULPI_D3 TOUT
OTG_HS_ EVEN
PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX - - - -
ULPI_D4 TOUT
Port B
TIM1_ I2C2_ SPI2_NSS OTG_HS_ OTG_ EVEN

PB12 - - - - USART3_CK - - -
BKIN SMBA /I2S2_WS ULPI_D5 HS_ID TOUT
TIM1_ SPI2_SCK USART3_CT OTG_HS_ EVEN

PB13 - - - - - - - - -
DS11853 Rev 9
CH1N /I2S2_CK S ULPI_D6 TOUT
TIM1_ SPI2_ USART3_RT SDMMC2_ OTG_ EVEN

PB14 - - TIM8_CH2N - - - TIM12_CH1 -
CH2N MISO S D0 HS_DM TOUT
SPI2_
RTC_ TIM1_ SDMMC2_ OTG_ EVEN
PB15 - TIM8_CH3N - MOSI/ - - - TIM12_CH2 -
REFIN CH3N D1 HS_DP TOUT
I2S2_SD
OTG_HS_ FMC_ EVEN

PC0 - - - - - - - - SAI2_FS_B - -
ULPI_STP SDNWE TOUT
SPI2_
SAI1_SD_ EVEN
PC1 TRACED0 - - - - MOSI/ - - - - - -
A TOUT
I2S2_SD
Port C
SPI2_ OTG_HS_UL FMC_ EVEN
PC2 - - - - - - - - - -
MISO PI_DIR SDNE0 TOUT
SPI2_
OTG_HS_UL FMC_ EVEN
PC3 - - - - - MOSI/ - - - - -
PI_NXT SDCKE0 TOUT
I2S2_SD

FMC_S EVEN
PC4 - - - - - I2S1_MCK - - - - - -
DNE0 TOUT
FMC_ EVEN
PC5 - - - - - - - - - - - -
SDCKE0 TOUT
SDMMC2_ SDMMC1 EVEN

PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK - - USART6_TX - -
D6 _D6 TOUT
SDMMC2_ SDMMC1 EVEN

PC7 - - TIM3_CH2 TIM8_CH2 - - I2S3_MCK - USART6_RX - -
D7 _D7 TOUT
SDMMC1 EVEN
PC8 TRACED1 - TIM3_CH3 TIM8_CH3 - - - UART5_RTS USART6_CK - - -
_D0 TOUT
DS11853 Rev 9
QUADSPI_ SDMMC1 EVEN

PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - UART5_CTS - - -
BK1_IO0 _D1 TOUT
Port C
SPI3_SCK QUADSPI_ SDMMC1 EVEN

PC10 - - - - - - USART3_TX UART4_TX - -
/I2S3_CK BK1_IO1 _D2 TOUT
SPI3_ QUADSPI_ SDMMC1 EVEN

PC11 - - - - - - USART3_RX UART4_RX - -
MISO BK2_NCS _D3 TOUT
SPI3_
SDMMC1 EVEN
PC12 TRACED3 - - - - - MOSI/ USART3_CK UART5_TX - - -
_CK TOUT
I2S3_SD
EVEN
PC13 - - - - - - - - - - - - -
TOUT
EVEN

PC14 - - - - - - - - - - - - -
TOUT
EVEN
PC15 - - - - - - - - - - - - -
TOUT
87/226
88/226


EVEN
PD0 - - - - - - - - - CAN1_RX - - FMC_D2
TOUT
EVEN
PD1 - - - - - - - - - CAN1_TX - - FMC_D3
TOUT
SDMMC1 EVEN
PD2 TRACED2 - TIM3_ETR - - - - - UART5_RX - - -
_CMD TOUT
SPI2_SCK USART2_ EVEN

PD3 - - - - - - - - - - FMC_CLK
/I2S2_CK CTS TOUT
USART2_ FMC_ EVEN

PD4 - - - - - - - - - - -
RTS NOE TOUT
DS11853 Rev 9
FMC_ EVEN
PD5 - - - - - - - USART2_TX - - - -
NWE TOUT
SPI3_
SAI1_SD_ SDMMC2 FMC_ EVEN
PD6 - - - - - MOSI/ USART2_RX - - -
A _CK NWAIT TOUT
I2S3_SD
SDMMC2 EVEN
PD7 - - - - - - - USART2_CK - - - FMC_NE1
Port D
_CMD TOUT
EVEN
PD8 - - - - - - - USART3_TX - - - - FMC_D13
TOUT
EVEN
PD9 - - - - - - - USART3_RX - - - - FMC_D14
TOUT
EVEN
PD10 - - - - - - - USART3_CK - - - - FMC_D15
TOUT
USART3_ QUADSPI_ FMC_A16/ EVEN

PD11 - - - - - - - - SAI2_SD_A -
CTS BK1_IO0 FMC_CLE TOUT
USART3_ QUADSPI_ FMC_A17/ EVEN

PD12 - - TIM4_CH1 LPTIM1_IN1 - - - - SAI2_FS_A -
RTS BK1_IO1 FMC_ALE TOUT
LPTIM1_ QUADSPI_ EVEN

PD13 - - TIM4_CH2 - - - - - SAI2_SCK_A - FMC_A18
OUT BK1_IO3 TOUT
EVEN
PD14 - - TIM4_CH3 - - - - - UART8_CTS - - - FMC_D0
TOUT
EVEN
PD15 - - TIM4_CH4 - - - - - UART8_RTS - - - FMC_D1
TOUT

SAI2_MCK_ FMC_ EVEN

PE0 - - TIM4_ETR LPTIM1_ETR - - - - UART8_Rx - -
A NBL0 TOUT
FMC_N EVEN
PE1 - - - LPTIM1_IN2 - - - - UART8_Tx - - -
BL1 TOUT
TRACECL SAI1_ QUADSPI_ EVEN

PE2 - - - - SPI4_SCK - - - - FMC_A23
K MCLK_A BK1_IO2 TOUT
SAI1_ EVEN
PE3 TRACED0 - - - - - - - - - - FMC_A19
SD_B TOUT
SAI1_ EVEN
PE4 TRACED1 - - - - SPI4_NSS - - - - - FMC_A20
FS_A TOUT
DS11853 Rev 9
SPI4_ SAI1_ EVEN

PE5 TRACED2 - - TIM9_CH1 - - - - - - FMC_A21
MISO SCK_A TOUT
TIM1_ SPI4_ SAI1_ SAI2_MCK_ EVEN

PE6 TRACED3 - TIM9_CH2 - - - - - FMC_A22
BKIN2 MOSI SD_A B TOUT
QUADSPI_ EVEN
PE7 - TIM1_ETR - - - - - - UART7_Rx - - FMC_D4
BK2_IO0 TOUT
Port E
TIM1_ QUADSPI_ EVEN

PE8 - - - - - - - UART7_Tx - - FMC_D5
CH1N BK2_IO1 TOUT
QUADSPI_ EVEN
PE9 - TIM1_CH1 - - - - - - UART7_RTS - - FMC_D6
BK2_IO2 TOUT
TIM1_ QUADSPI_ EVEN

PE10 - - - - - - - UART7_CTS - - FMC_D7
CH2N BK2_IO3 TOUT

EVEN
PE11 - TIM1_CH2 - - - SPI4_NSS - - - - SAI2_SD_B - FMC_D8
TOUT
TIM1_ EVEN
PE12 - - - - SPI4_SCK - - - - SAI2_SCK_B - FMC_D9
CH3N TOUT
SPI4_ EVEN
PE13 - TIM1_CH3 - - - - - - - SAI2_FS_B - FMC_D10
MISO TOUT
SPI4_ SAI2_MCK EVEN

PE14 - TIM1_CH4 - - - - - - - - FMC_D11
MOSI _B TOUT
TIM1_ EVEN
89/226
PE15 - - - - - - - - - - - FMC_D12
BKIN TOUT
90/226


EVEN
PF0 - - - - I2C2_SDA - - - - - - - FMC_A0
TOUT
EVEN
PF1 - - - - I2C2_SCL - - - - - - - FMC_A1
TOUT
I2C2_ EVEN
PF2 - - - - - - - - - - - FMC_A2
SMBA TOUT
EVEN
PF3 - - - - - - - - - - - - FMC_A3
TOUT
EVEN
PF4 - - - - - - - - - - - - FMC_A4
TOUT
DS11853 Rev 9
EVEN
PF5 - - - - - - - - - - - - FMC_A5
TOUT
SAI1_SD QUADSPI_ EVEN

PF6 - - - TIM10_CH1 - SPI5_NSS - UART7_Rx - - -
_B BK1_IO3 TOUT
SAI1_MCL QUADSPI_ EVEN

PF7 - - - TIM11_CH1 - SPI5_SCK - UART7_Tx - - -
K_B BK1_IO2 TOUT
Port F
SPI5_ SAI1_SCK QUADSPI_ EVEN

PF8 - - - - - - UART7_RTS TIM13_CH1 - -
MISO _B BK1_IO0 TOUT
SPI5_ SAI1_FS QUADSPI_ EVEN

PF9 - - - - - - UART7_CTS TIM14_CH1 - -
MOSI _B BK1_IO1 TOUT
EVEN
PF10 - - - - - - - - - - - - -
TOUT
SPI5_ FMC_ EVEN
PF11 - - - - - - - - - SAI2_SD_B -
MOSI SDNRAS TOUT
EVEN
PF12 - - - - - - - - - - - - FMC_A6
TOUT
EVEN
PF13 - - - - - - - - - - - - FMC_A7
TOUT
EVEN
PF14 - - - - - - - - - - - - FMC_A8
TOUT
EVEN
PF15 - - - - - - - - - - - - FMC_A9
TOUT

EVEN
PG0 - - - - - - - - - - - - FMC_A10
TOUT
EVEN
PG1 - - - - - - - - - - - - FMC_A11
TOUT
EVEN
PG2 - - - - - - - - - - - - FMC_A12
TOUT
EVEN
PG3 - - - - - - - - - - - - FMC_A13
TOUT
FMC_A14/ EVEN
PG4 - - - - - - - - - - - -
FMC_BA0 TOUT
DS11853 Rev 9
FMC_A15/ EVEN
PG5 - - - - - - - - - - - -
FMC_BA1 TOUT
EVEN
PG6 - - - - - - - - - - - - -
TOUT
Port G
EVEN
PG7 - - - - - - - - USART6_CK - - - FMC_INT
TOUT
FMC_ EVEN
PG8 - - - - - - - - USART6_RTS - - -
SDCLK TOUT
FMC_NE2
QUADSPI_ SDMMC2 EVEN
PG9 - - - - - - - - USART6_RX SAI2_FS_B /FMC_
BK2_IO2 _D0 TOUT
NCE
SDMMC2 EVEN
PG10 - - - - - - - - - - SAI2_SD_B FMC_NE3

_D1 TOUT
SDMMC2_ EVEN
PG11 - - - - - - - - - - - -
D2 TOUT
SDMMC2 EVEN
PG12 - - - LPTIM1_IN1 - - - - USART6_RTS - - FMC_NE4
_D3 TOUT
LPTIM1_ EVEN
PG13 TRACED0 - - - - - - USART6_CTS - - - FMC_A24
OUT TOUT
91/226
92/226


QUADSPI_ EVEN
PG14 TRACED1 - - LPTIM1_ETR - - - - USART6_TX - - FMC_A25
BK2_IO3 TOUT
Port G
FMC_ EVEN
PG15 - - - - - - - - USART6_CTS - - -
SDNCAS TOUT
EVEN
PH0 - - - - - - - - - - - - -
TOUT
EVEN
PH1 - - - - - - - - - - - - -
TOUT
QUADSPI_ FMC_ EVEN

PH2 - - - LPTIM1_IN2 - - - - - SAI2_SCK_B -
BK2_IO0 SDCKE0 TOUT
DS11853 Rev 9
QUADSPI_ SAI2_MCK_ FMC_ EVEN

PH3 - - - - - - - - - -
BK2_IO1 B SDNE0 TOUT
OTG_HS_ EVEN
PH4 - - - - I2C2_SCL - - - - - - -
ULPI_NXT TOUT
FMC_ EVEN
PH5 - - - - I2C2_SDA SPI5_NSS - - - - - -
SDNWE TOUT
I2C2_ FMC_ EVEN

PH6 - - - - SPI5_SCK - - - TIM12_CH1 - -
SMBA SDNE1 TOUT
Port H
SPI5_ FMC_ EVEN

PH7 - - - - I2C3_SCL - - - - - -
MISO SDCKE1 TOUT
EVEN
PH8 - - - - I2C3_SDA - - - - - - - FMC_D16
TOUT
I2C3_SMB EVEN
PH9 - - - - - - - - TIM12_CH2 - - FMC_D17
A TOUT
EVEN
PH10 - - TIM5_CH1 - - - - - - - - - FMC_D18
TOUT
EVEN
PH11 - - TIM5_CH2 - - - - - - - - - FMC_D19
TOUT
EVEN
PH12 - - TIM5_CH3 - - - - - - - - - FMC_D20
TOUT
EVEN
PH13 - - - TIM8_CH1N - - - - UART4_TX CAN1_TX - - FMC_D21
TOUT

EVEN
PH14 - - - TIM8_CH2N - - - - UART4_RX CAN1_RX - - FMC_D22
TOUT
Port H
EVEN
PH15 - - - TIM8_CH3N - - - - - - - - FMC_D23
TOUT
SPI2_NSS EVEN
PI0 - - TIM5_CH4 - - - - - - - - FMC_D24
/I2S2_WS TOUT
SPI2_SCK EVEN
PI1 - - - TIM8_BKIN2 - - - - - - - FMC_D25
/I2S2_CK TOUT
SPI2_MIS EVEN
PI2 - - - TIM8_CH4 - - - - - - - FMC_D26
O TOUT
DS11853 Rev 9
SPI2_MO
EVEN
PI3 - - - TIM8_ETR - SI/I2S2_S - - - - - - FMC_D27
TOUT
D
SAI2_MCK_ FMC_NBL EVEN

PI4 - - - TIM8_BKIN - - - - - - -
A 2 TOUT
Port I
FMC_NBL EVEN
PI5 - - - TIM8_CH1 - - - - - - SAI2_SCK_A -
3 TOUT
EVEN
PI6 - - - TIM8_CH2 - - - - - - SAI2_SD_A - FMC_D28
TOUT
EVEN
PI7 - - - TIM8_CH3 - - - - - - SAI2_FS_A - FMC_D29
TOUT
EVEN
PI8 - - - - - - - - - - - - -

TOUT
EVEN
PI9 - - - - - - - - UART4_RX CAN1_RX - - FMC_D30
TOUT
EVEN
PI10 - - - - - - - - - - - - FMC_D31
TOUT
93/226
94/226


OTG_HS_UL EVEN
PI11 - - - - - - - - - - - -
PI_DIR TOUT
EVEN
PI12 - - - - - - - - - - - - -
TOUT
Port I
EVEN
PI13 - - - - - - - - - - - - -
TOUT
EVEN
PI14 - - - - - - - - - - - - -
TOUT
EVEN
PI15 - - - - - - - - - - - - -
TOUT
DS11853 Rev 9
STM32F722xx STM32F723xx Memory mapping
5 Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
DS11853 Rev 9 95/226

95
Electrical characteristics STM32F722xx STM32F723xx
6 Electrical characteristics
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 26.
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 27.
Figure 26. Pin loading conditions Figure 27. Pin input voltage
MCU pin MCU pin
C = 50 pF VIN
MS19011V2 MS19010V2
96/226 DS11853 Rev 9

STM32F722xx STM32F723xx Electrical characteristics
6.1.6 Power supply scheme
Figure 28. STM32F722xx power supply scheme

VBAT
Backup circuitry
VBAT = Power switch (OSC32K,RTC,
1.65 to 3.6V Wakeup logic
Backup registers,
backup RAM)
Level shifter
OUT
IO
GP I/Os Logic
V IN
DDSDMMC
V
DDSDMMC
100 nF
Level shifter
+ 1 μF OUT
PG[9..12], PD[6,7]
IO
Logic
IN Kernel logic
(CPU,
VCAP_1
VCAP_2 digital
2 × 2.2 μF & RAM)
VDD
VDD Voltage
1/2/...11/12
regulator
12 × 100 nF VSS
+ 1 × 4.7 μF 1/2/...11/12
BYPASS_REG Flash memory

VDDUSB
VDDUSB
OTG FS
100 nF PHY
+ 1 μF
Reset
PDR_ON controller
VDD
VDDA
VREF
VREF+
100 nF Analog:
100 nF VREF- ADC RCs, PLL,
+ 1 μF + 1 μF
...
VSSA
MSv42076V2
1. The two 2.2 µF ceramic capacitors must be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VDDA = VDD and VSSA = VSS.
DS11853 Rev 9 97/226

196
Figure 29. STM32F723xx power supply scheme

VBAT
Backup circuitry
VBAT = Power switch (OSC32K,RTC,
1.65 to 3.6V Wakeup logic
Backup registers,
backup RAM)
Level shifter
OUT
IO
GP I/Os Logic
V IN
DDSDMMC
VDDSDMMC
100 nF
Level shifter
+ 1 μF OUT
PG[9..12], PD[6,7]
IO
IN
Logic
Level shifter
OUT
PA[11,12], PB[14,15]
IO
VDDUSB
IN
Logic
VDDUSB
100 nF
+ 1 μF
OTG FS
PHY Kernel logic
(CPU,
V CAP_1
digital
2 × 2.2 μF V CAP_2
& RAM)
VDD
V DD Voltage
1/2/...11/12
regulator
12 × 100 nF
VSS
+ 1 × 4.7 μF 1/2/...11/12
BYPASS_REG Flash memory
OTG HS PHY
voltage
regulator
VDD12OTGHS
OTG HS PHY
2.2 μF
OTG_HS_REXT
3 Kohm +/-1% Reset

PDR_ON controller
VDD
VDDA
VREF
VREF+
100 nF Analog:
100 nF VREF- ADC RCs, PLL,
+ 1 μF + 1 μF
...
VSSA
MSv42069V1
1. In all the packages (except LQFP100), the VDDUSB allows supplying the PHY FS in PA11/PA12 and the
PHY HS on PB14/PB15. In the LQFP100, the PHY HS on PB14/PB15 is supplied by VDDPHYHS.
98/226 DS11853 Rev 9

2. The two 2.2 µF ceramic capacitors must be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
4. VDDA = VDD and VSSA = VSS.
Caution: Each power supply pair (such as VDD/VSS or VDDA/VSSA) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure good operation of
the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This may cause incorrect operation of the device.
6.1.7 Current consumption measurement
Figure 30. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics,
Table 14: Current characteristics, and Table 15: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. The device mission profile (application
conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission
profiles are available on demand.
Table 13. Voltage characteristics

Symbol Ratings Min Max Unit
External main supply voltage (including VDDA, VDD,

VDD–VSS − 0.3 4.0
VBAT, VDDUSB, VDDPHYHS and VDDSDMMC) (1)
Input voltage on FT pins(2) VSS − 0.3 VDD+4.0
V
Input voltage on TTa pins VSS − 0.3 4.0
VIN
Input voltage on any other pin VSS − 0.3 4.0
Input voltage on BOOT pin VSS 9.0
DS11853 Rev 9 99/226

196
Table 13. Voltage characteristics (continued)

Symbol Ratings Min Max Unit
|ΔVDDx| Variations between different VDD power pins - 50

mV
|VSSX −VSS| Variations between all the different ground pins(3) - 50
see Section 6.3.18:
Absolute maximum
VESD(HBM) Electrostatic discharge voltage (human body model) -
ratings (electrical
sensitivity)
1. All main power (VDD, VDDA, VDDSDMMC, VDDPHYHS, VDDUSB) and ground (VSS, VSSA) pins must always be
connected to the external power supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed
injected current.
3. Include VREF- pin.
Table 14. Current characteristics

Symbol Ratings Max. Unit
ΣIVDD Total current into sum of all VDD_x power lines (source)(1) 300
Σ IVSS Total current out of sum of all VSS_x ground lines (sink)(1) − 300
Σ IVDDUSB Total current into VDDUSB power line (source) 25
Σ IVDDSDMMC Total current into VDDSDMMC power line (source) 60
IVDD Maximum current into each VDD_x power line (source)(1) 100
IVDDSDMMC Maximum current into VDDSDMMC power line (source): PG[12:9], PD[7:6] 100
IVSS Maximum current out of each VSS_x ground line (sink)(1) − 100
Output current sunk by any I/O and control pin 25 mA
IIO
Output current sourced by any I/Os and control pin − 25
(2)
Total output current sunk by sum of all I/O and control pins 120
ΣIIO Total output current sunk by sum of all USB I/Os 25
(2) − 120
Total output current sourced by sum of all I/Os and control pins
(3)
Injected current on FT, FTf, RST and B pins − 5/+0
IINJ(PIN)
Injected current on TTa pins(4) ±5
(4)
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(5) ±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN > VDDA while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 13: Voltage characteristics for the values of the maximum allowed input voltage.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
100/226 DS11853 Rev 9

Table 15. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range − 65 to +150

°C
TJ Maximum junction temperature 125
6.3 Operating conditions
6.3.1 General operating conditions
Table 16. General operating conditions

Symbol Parameter Conditions(1) Min Typ Max Unit
Power scale 3 (VOS[1:0] bits in

PWR_CR register = 0x01), regulator 0 - 144
ON, over-drive OFF
Over-
drive - 168
Power scale 2 (VOS[1:0] bits OFF
in PWR_CR register = 0x10), 0
Regulator ON Over-
fHCLK Internal AHB clock frequency drive - 180
ON
Over- MH
drive - 180 z
Power scale 1 (VOS[1:0] bits OFF
in PWR_CR register= 0x11), 0
Regulator ON Over-
drive - 216(2)
ON
Over-drive OFF 0 - 45
fPCLK1 Internal APB1 clock frequency
Over-drive ON 0 - 54
Over-drive OFF 0 - 90
fPCLK2 Internal APB2 clock frequency
Over-drive ON 0 - 108
DS11853 Rev 9 101/226

196
Table 16. General operating conditions (continued)

(3)
VDD Standard operating voltage - 1.7 - 3.6
Analog operating voltage
1.7(3) - 2.4
(ADC limited to 1.2 M samples)
VDDA(4)(5) Must be the same potential as VDD (6)
Analog operating voltage
2.4 - 3.6
(ADC limited to 2.4 M samples)
USB supply voltage (supply USB not used 1.7 3.3 3.6
VDDUSB voltage for PA11,PA12, PB14 and
PB15 pins) USB used 3.0 - 3.6 V
USB PHY HS supply voltage in USB PHY HS not used 1.7 3.3 3.6
VDDSPHYHS the STM32F723 LQFP100 (supply
voltage for PB14 and PB15) USB PHY HS used 3.0 - 3.6
VBAT Backup operating voltage - 1.65 - 3.6

SDMMC2 supply voltage (supply
VDDSDMMC voltage for PG[12:9] and PD6 It can be different from VDD 1.7 - 3.6
pins)
Power scale 3 ((VOS[1:0] bits in
PWR_CR register = 0x01), 144 MHz 1.08 1.14 1.20
HCLK max frequency
Power scale 2 ((VOS[1:0] bits in
PWR_CR register = 0x10), 168 MHz
Regulator ON: 1.2 V internal 1.20 1.26 1.32
HCLK max frequency with over-drive
voltage on VCAP_1/VCAP_2 pins
OFF or 180 MHz with over-drive ON
V12 Power scale 1 ((VOS[1:0] bits in
PWR_CR register = 0x11), 180 MHz
1.26 1.32 1.40
HCLK max frequency with over-drive
OFF or 216 MHz with over-drive ON V
Regulator OFF: 1.2 V external Max frequency 144 MHz 1.10 1.14 1.20
voltage must be supplied from
Max frequency 168MHz 1.20 1.26 1.32
external regulator on
VCAP_1/VCAP_2 pins(7) Max frequency 180 MHz 1.26 1.32 1.38
Input voltage on RST and FT 2 V ≤VDD ≤3.6 V − 0.3 - 5.5

pins(8) VDD ≤2 V − 0.3 - 5.2
VIN VDDA+
Input voltage on TTa pins - − 0.3 -
0.3
Input voltage on BOOT pin - 0 - 9
102/226 DS11853 Rev 9

Table 16. General operating conditions (continued)

LQFP64 - - 881
LQFP100 - - 1117
WLCSP100 - - 558
Power dissipation at TA = 85 °C for
PD suffix 6 or TA = 105 °C for suffix LQFP144 - - 1587 mW
7(9)
LQFP176 - - 1869
UFBGA144 - - 476
UFBGA176 - - 485
Ambient temperature for 6 suffix Maximum power dissipation − 40 - 85

°C
version Low power dissipation (10)
− 40 - 105
TA
Ambient temperature for 7 suffix Maximum power dissipation − 40 - 105
°C
version Low power dissipation (10)
− 40 - 125
6 suffix version − 40 - 105
TJ Junction temperature range °C
7 suffix version − 40 - 125
1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
2. 216 MHz maximum frequency for 6 suffix version (200 MHz maximum frequency for 7 suffix version).
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
Internal reset OFF).
4. When the ADC is used, refer to Table 67: ADC characteristics.
5. If VREF+ pin is present, it must respect the following condition: VDDA - VREF+ < 1.2 V.
6. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA
can be tolerated during power-up and power-down operation.
7. The over-drive mode is not supported when the internal regulator is OFF.
8. To sustain a voltage higher than VDD + 0.3, the internal pull-up and pull-Down resistors must be disabled.
9. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
10. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
Table 17. Limitations depending on the operating power supply range

Maximum Flash
Maximum HCLK
Operating memory access Possible Flash
frequency vs Flash
power supply ADC operation frequency with I/O operation memory
memory wait states
range no wait states (1)(2) operations
(fFlashmax)
180 MHz with 8 wait 8-bit erase and

VDD =1.7 to Conversion time No I/O
20 MHz states and over-drive program
2.1 V(3) up to 1.2 Msps compensation
OFF operations only
VDD = 2.1 to Conversion time No I/O
2.4 V up to 1.2 Msps compensation
ON operations
DS11853 Rev 9 103/226

196
Table 17. Limitations depending on the operating power supply range (continued)
Maximum Flash
Maximum HCLK
Operating memory access Possible Flash
frequency vs Flash
power supply ADC operation frequency with I/O operation memory
memory wait states
range no wait states (1)(2) operations
(fFlashmax)

VDD = 2.4 to Conversion time I/O compensation
2.7 V up to 2.4 Msps works
ON operations
VDD = 2.7 to Conversion time I/O compensation
3.6 V(4) up to 2.4 Msps works
ON operations
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here
does not impact the execution speed from Flash memory since the ART accelerator or L1-cache is used to achieve a
performance equivalent to 0-wait state program execution.
3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
4. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+
pins are degraded between 2.7 and 3 V.
6.3.2 VCAP1/VCAP2 external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP1/VCAP2 pins. CEXT is specified in Table 18.
Note: The VCAP2 pin is not available on the LQFP64 package.
Figure 31. External capacitor CEXT

C
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
Table 18. VCAP1/VCAP2 operating conditions(1)

Symbol Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF

ESR ESR of external capacitor <2Ω
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
104/226 DS11853 Rev 9

Table 19. VCAP1 operating conditions in the LQFP64 package(1)

CEXT Capacitance of external capacitor 4.7 µF

ESR ESR of external capacitor between 0.1 Ω and 0.2 Ω
1. When bypassing the voltage regulator, the 4.7 µF VCAP capacitor is not required and should be replaced
by two 100 nF decoupling capacitors.
6.3.3 Operating conditions at power-up/power-down (regulator ON)

Subject to general operating conditions for TA.
Table 20. Operating conditions at power-up/power-down (regulator ON)

Symbol Parameter Min Max Unit
VDD rise time rate 20 ∞

tVDD µs/V
VDD fall time rate 20 ∞
6.3.4 Operating conditions at power-up/power-down (regulator OFF)

Subject to general operating conditions for TA.
Table 21. Operating conditions at power-up/power-down (regulator OFF)(1)

Symbol Parameter Conditions Min Max Unit
VDD rise time rate Power-up 20 ∞

tVDD
VDD fall time rate Power-down 20 ∞
µs/V
VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞
tVCAP
VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reaches
below 1.08 V.
DS11853 Rev 9 105/226

196
6.3.5 Reset and power control block characteristics

The parameters given in Table 22 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 16.
Table 22. Reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit
PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V

PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 V
PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 V
PLS[2:0]=010 (rising edge) 2.39 2.45 2.51 V
PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 V
Programmable voltage PLS[2:0]=011 (falling edge) 2.44 2.51 2.56 V

VPVD
detector level selection PLS[2:0]=100 (rising edge) 2.70 2.76 2.82 V
PLS[2:0]=101 (rising edge) 2.86 2.93 2.99 V
PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 V
PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 V
VPVDhyst(1) PVD hysteresis - - 100 - mV
Power-on/power-down Falling edge 1.60 1.68 1.76 V

VPOR/PDR
reset threshold Rising edge 1.64 1.72 1.80 V
(1)
VPDRhyst PDR hysteresis - - 40 - mV
Brownout level 1 Falling edge 2.13 2.19 2.24 V

VBOR1
threshold Rising edge 2.23 2.29 2.33 V

VBOR2

VBOR3
VBORhyst(1) BOR hysteresis - - 100 - mV
TRSTTEMPO
(1)(2) POR reset temporization - 0.5 1.5 3.0 ms
106/226 DS11853 Rev 9

Table 22. Reset and power control block characteristics (continued)

InRush current on
voltage regulator power-
IRUSH(1) - - 160 250 mA
on (POR or wakeup
from Standby)
InRush energy on
voltage regulator power- VDD = 1.7 V, TA = 105 °C,
ERUSH(1) - - 5.4 µC
on (POR or wakeup IRUSH = 171 mA for 31 µs
from Standby)
1. Guaranteed by design.
2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant
when first instruction is read by the user application code.
6.3.6 Over-drive switching characteristics

When the over-drive mode switches from enabled to disabled or disabled to enabled, the
system clock is stalled during the internal voltage set-up.
The over-drive switching characteristics are given in Table 23. They are sbject to general
operating conditions for TA.
Table 23. Over-drive switching characteristics(1)

HSI - 45 -
HSE max for 4 MHz
Over_drive switch 45 - 100
Tod_swen and min for 26 MHz
enable time
External HSE
- 40 -
50 MHz
µs
HSI - 20 -
HSE max for 4 MHz
Over_drive switch 20 - 80
Tod_swdis and min for 26 MHz.
disable time
External HSE
- 15 -
50 MHz
6.3.7 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 30: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
DS11853 Rev 9 107/226

196
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in input mode with a static value at VDD or VSS (no load).
• All peripherals are disabled except if it is explicitly mentioned.
• The Flash memory access time is adjusted both to fHCLK frequency and VDD range
(see Table 17: Limitations depending on the operating power supply range).
• When the regulator is ON, the voltage scaling and over-drive mode are adjusted to
fHCLK frequency as follows:
– Scale 3 for fHCLK ≤ 144 MHz
– Scale 2 for 144 MHz < fHCLK ≤ 168 MHz
– Scale 1 for 168 MHz < fHCLK ≤ 216 MHz. The over-drive is only ON at 216 MHz.
• When the regulator is OFF, the V12 is provided externally as described in Table 16:
General operating conditions:
• The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
• External clock frequency is 25 MHz and PLL is ON when fHCLK is higher than 25 MHz.
• The typical current consumption values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage
range and for TA= 25 °C unless otherwise specified.
• The maximum values are obtained for 1.7 V ≤ VDD ≤ 3.6 V voltage range and a
maximum ambient temperature (TA) unless otherwise specified.
• For the voltage range 1.7 V ≤ VDD ≤ 3.6 V, the maximum frequency is 180 MHz.
running from ITCM RAM, regulator ON
Max(1)
Symbol Parameter Conditions fHCLK (MHz) Typ Unit
TA = 25 °C TA = 85 °C TA = 105 °C
216 156 170(4) 180(4) 200

200 144 154 164.6 183
(4)
180 127 134 143(4) 158(4)
All peripherals
168 113 119 127.4 141
enabled(2)(3)
144 86 96 112.6 126
60 41 44 52.8 65
Supply cur- 25 22 24 33.5 45
IDD rent in Run mA
mode 216 99 110(4) 119.6(4) 138.5
200 92 102 113.1 132
180 81 90(4) 96.7(4) 125(4)
All peripherals
168 72 78 86.5 100.1
disabled(3)
144 55 61 77.1 90.8
60 24 25 38.5 50.3
25 12 13 26.3 38.1
1. Guaranteed by characterization results.
108/226 DS11853 Rev 9

2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption
should be considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC
for the analog part.
4. Guaranteed by test in production.
or SRAM on AXI (L1-cache ON), regulator ON
Max(1)
TA = 25 °C TA = 85 °C TA = 105 °C
216 155.3 164 175.8 185

200 144.7 153.6 165.2 176
180 127.3 135 143.5 154
All peripherals
168 113.1 119.1 127.8 138
enabled(2)(3)
144 86.9 91.6 99.5 110
60 41.2 43.6 53.1 64
Supply cur- 25 21.7 24 33.6 43.8
IDD rent in Run mA
mode 216 90 106 120.4 130
200 84 99 113.8 124
180 74 86.6 97.3 107
All peripherals
168 66 76 87 97
disabled(3)
144 51 59 68.2 78
60 23 27 38.8 49
25 11 13.6 26.4 36.8
DS11853 Rev 9 109/226

196
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON
Max(1)
TA= 25 °C TA=85 °C TA=105 °C
216 129.3 137.6 162.8 173

200 122 128 153.2 163.3
180 108 117 136.4 146
All peripherals
168 99 104.5 122.3 132
enabled(2)(3)
144 80 84.7 99.3 109.2
60 42 45 59.5 70
Supply cur- 25 23 23.4 37.8 48
IDD rent in Run mA
mode 216 73.3 82.3 107.4 119
200 70 77 101.8 113.5
180 62 71 90.2 101
All peripherals
168 59 63.6 81.4 92.1
disabled(3)
144 49 53.3 67.9 79
60 26 31 45.1 56
25 14 16 30.6 41.2
110/226 DS11853 Rev 9

running from Flash memory on ITCM interface (ART disabled), regulator ON
Max(1)
TA= 25 °C TA=85 °C TA=105 °C
216 138 151 174.7 184

200 133 141 164.3 174
180 110 131 149.2 159
All peripherals
168 99 117 134 144
enabled(2)(3)
144 79 98 111.7 121
60 49 53 64 75
Supply cur- 25 27 30 38.3 48
IDD rent in Run mA
mode 216 82 96 119.5 131
200 81 89 113.1 124
180 65 85 103.1 114
All peripherals
168 58 76 93.2 104
disabled(3)
144 48 67 80.4 91
60 33 36 49.7 60
25 18 21 31.1 41
DS11853 Rev 9 111/226

196
or SRAM on AXI (L1-cache ON), regulator OFF
Max(1)
Typ
fHCLK
Symbol Parameter Conditions TA= 25 °C TA= 85 °C TA= 105 °C Unit
(MHz)
IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD
180 112 1.4 120 2 132.7 2 142 2

168 110 1.4 106.4 2 118.7 2 130 2
All peripherals
144 78 1.3 82.5 2 93.6 2 103 2
enabled(2)(3)
Supply cur- 60 37 1.1 37.6 2 49.3 2 60 2
rent in Run 25 19 1.1 18.5 2 30.4 2 40 2
IDD12/
mode from mA
IDD 180 74 1.4 78 2 89.3 2 99 2
V12 and VDD
supplies 168 64 1.4 68 2 80.1 2 90 2
All peripherals
144 51 1.3 54 2 63.5 2 74 2
disabled(3)
60 22 1.1 24 2 35.2 2 45 2
25 10 1.2 12 2 23.2 2 35 2
112/226 DS11853 Rev 9

Table 29. Typical and maximum current consumption in Sleep mode, regulator ON
Max(1)
TA= 25 °C TA=85 °C TA=105 °C
216 82 96(3) 109.3(3) 128.3

200 77 84 103.4 122.6
180 67 72(3) 88.3(3) 120(3)
All peripherals
168 60 64 78.9 92.7
enabled(2)
144 46 49 61.8 73.6
60 24 26 37.2 49
Supply cur-
rent in 25 14 16 27 38.8
IDD mA
Sleep 216 24 28 (3)
42.9(3) 62.2
mode
200 22 26 41.9 61.2
180 19 21(3) 33.2(3) 48(3)
All peripherals
168 17 19 30.1 43.9
disabled
144 13 15 24.6 36.3
60 7 9 20.5 32.3
25 5 7 18.8 30.6
3. Guaranteed by test in production.
Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF
Max(1)
Typ Unit
fHCLK
Symbol Parameter Conditions TA= 25 °C TA= 85 °C TA= 105 °C
(MHz)
IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD
180 62 1.3 67.5 2 84.4 2 95 2

168 55 1.3 59.8 2 75.4 2 86 2
All peripherals
144 43 1.3 46.3 2 59.6 2 70 2
enabled(2)
60 22 1 24 2 35.8 2 46 2
Supply current
IDD12/ in Run mode 25 13 1 15 2 25.8 2 36 2
mA
IDD from V12 and 180 17 1.3 19 2 31.4 2 42 2
VDD supplies
168 15 1.3 17 2 28.4 2 40 2
All peripherals
144 12 1.2 14 2 23.2 2 33 2
disabled
60 5 1 6 2 19.3 2 29 2
25 3 1 4 2 17.6 2 28 2
DS11853 Rev 9 113/226

196

Table 31. Typical and maximum current consumptions in Stop mode

Max(1)
Typ
Symbol Parameter Conditions VDD = 3.6 V Unit
TA = TA = TA = TA =
25 °C 25 °C 85 °C 105 °C
Flash memory in Stop mode,

Supply current in Stop all oscillators OFF, no IWDG 0.45 2 12 22
mode, main regulator in
Run mode Flash memory in Deep power
0.4 2 12 22
down mode, all oscillators OFF
IDD_STOP_NM
(normal mode) Flash memory in Stop mode, all
0.32 1.5 10 18
Supply current in Stop oscillators OFF, no IWDG
mode, main regulator in Flash memory in Deep power
low-power mode down mode, all oscillators OFF, no 0.27 1.5 10 18
IWDG mA
Regulator in Run mode, Flash

memory in Deep power down
0.15 0.8 5 7
Supply current in Stop mode, all oscillators OFF, no
IDD_STOP_UDM
mode, main regulator in IWDG
(under-drive
low-voltage and under- Regulator in Low-power mode,
mode)
drive modes Flash memory in Deep power
0.1 0.7 4 7
down mode, all oscillators OFF, no
IWDG
1. Data based on characterization, tested in production.
114/226 DS11853 Rev 9

Table 32. Typical and maximum current consumptions in Standby mode

Typ(1) Max(2)
TA = TA = TA =
TA = 25 °C
Symbol Parameter Conditions 25 °C 85 °C 105 °C Unit
VDD = VDD= VDD =

VDD = 3.3 V
1.7 V 2.4 V 3.3 V
Backup SRAM OFF, RTC and

1.09 1.13 1.4 4 27 55
LSE OFF
Backup SRAM ON, RTC and
1.85 1.88 2.17 5 30 60
LSE OFF
Backup SRAM OFF, RTC ON
1.65 1.86 2.43 7 47 95.5
and LSE in low drive mode
and LSE in medium low drive 1.67 1.88 2.46 7 47.5 97
mode
and LSE in medium high drive 1.8 2.01 2.61 7.5 50.5 102.5
Supply current mode
IDD_STBY in Standby µA
mode Backup SRAM OFF, RTC ON
1.92 2.13 2.73 8 53 107
and LSE in high drive mode
Backup SRAM ON, RTC ON
2.39 2.6 3.23 9 62 127
and LSE in medium low drive 2.41 2.64 3.25 9 63 128
mode
and LSE in medium high drive 2.67 2.89 2.53 10 68 139
mode
2.68 2.9 3.51 10 68 138
1. PDR is OFF for VDD=1.7V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by
additional 1.2 µA.
DS11853 Rev 9 115/226

196
Table 33. Typical and maximum current consumptions in VBAT mode

Typ Max(2)
TA =25 °C TA =85 °C TA =105 °C

Symbol Parameter Conditions(1) Unit
VBAT = VBAT= VBAT=
VBAT = 3.6 V
1.7 V 2.4 V 3.3 V
Backup SRAM OFF, RTC and
0.035 0.037 0.043 4 10
LSE OFF
Backup SRAM ON, RTC and
0.69 0.71 0.73 9 20
LSE OFF
0.57 0.74 1.05 98 244
and LSE in medium low drive 0.59 0.76 1.08 101 251
mode
Supply current and LSE in medium high drive 0.69 0.86 1.19 111 277
IDD_VBAT µA
in VBAT mode mode
0.8 0.98 1.31 122 305
Backup SRAM ON, RTC ON and
1.22 1.41 1.74 162 405
LSE in low drive mode
1.25 1.43 1.78 166 414
LSE in Medium low drive mode
1.46 1.65 2.01 187 468
LSE in Medium high drive mode
1.46 1.65 2.01 187 468
LSE in High drive mode
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
116/226 DS11853 Rev 9

LSE in low drive mode)
3.5
3
1.65 V
IDD_VBAT (uA)
2.5 1.7 V
1.8 V
2 2V
2.4 V
1.5
2.7 V
3V
1
3.3 V
0.5 3.6 V
0
0 20 40 60 80 100 120
Temperature °C
MS37585V1
LSE in medium low drive mode)
4.5
3.5
1.65 V
IDD_VBAT (uA)
3
1.7 V
2.5 1.8 V
2V
2
2.4 V
1.5 2.7 V
3V
1 3.3 V
3.6 V
0.5
0
0 20 40 60 80 100 120
Temperature °C MS37586V1
DS11853 Rev 9 117/226

196
LSE in medium high drive mode)
4.5
3.5
1.65 V
3
IDD_VBAT (uA)
1.7 V
2.5 1.8 V
2V
2
2.4 V
1.5 2.7 V
3V
1 3.3 V
0.5 3.6 V
0
0 20 40 60 80 100 120
Temperature °C
MS37587V1
LSE in high drive mode)
4.5
3.5
3 1.65 V
IDD_VBAT (uA)
1.7 V
2.5
1.8 V
2V
2
2.4 V
1.5 2.7 V
3V
1 3.3 V
3.6 V
0.5
0
0 20 40 60 80 100 120
Temperature °C MS37588V1
118/226 DS11853 Rev 9

LSE in high medium drive mode)
6 1.65 V
IDD_VBAT (uA)
1.7 V
5 1.8 V
2V
4 2.4 V
2.7 V
3
3V
3.3 V
2
3.6 V
0
0 20 40 60 80 100 120
Temperature( °C)
MS37589V1
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 61: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which must be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 35: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
DS11853 Rev 9 119/226

196
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
I SW = V DD × f SW × C
Where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load.
VDD is the MCU supply voltage.
fSW is the I/O switching frequency.
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
Table 34. Switching output I/O current consumption(1)

I/O toggling Typ Typ
Symbol Parameter Conditions Unit
frequency (fsw) MHz VDD = 3.3 V VDD = 1.8 V
2 0.1 0.1
8 0.4 0.2
25 1.1 0.7
50 2.4 1.3
CEXT = 0 pF
60 3.1 1.6
C = CINT + CS + CEXT
84 4.3 2.4
90 4.9 2.6
100 5.4 2.8
I/O switching 108 5.6 -

IDDIO mA
current 2 0.2 0.1
8 0.6 0.3
25 1.8 1.1
50 3.1 2.3
CEXT = 10 pF
60 4.6 3.4
84 9.7 3.6
90 10.12 5.2
100 14.92 5.4
108 18.11 -
120/226 DS11853 Rev 9

Table 34. Switching output I/O current consumption(1) (continued)

I/O toggling Typ Typ
frequency (fsw) MHz VDD = 3.3 V VDD = 1.8 V
2 0.3 0.1
8 1.0 0.5
25 3.5 1.6
CEXT = 22 pF
50 5.9 4.2
60 10.0 4.4
I/O switching 84 19.12 5.8

IDDIO mA
current 90 19.6 -
2 0.3 0.2
8 1.3 0.7
CEXT = 33 pF
25 3.5 2.3
50 10.26 5.19
60 16.53 -
1. CINT + CS, PCB board capacitance including the pad pin is estimated to15 pF.
On-chip peripheral current consumption

• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• I/O compensation cell enabled
• The ART/L1-cache is ON.
• Scale 1 mode selected, internal digital voltage V12 = 1.32 V.
• HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2.
The given value is calculated by measuring the difference of current consumption
– with all peripherals clocked off
– with only one peripheral clocked on
– fHCLK = 216 MHz (Scale 1 + over-drive ON), fHCLK = 168 MHz (Scale 2),
fHCLK = 144 MHz (Scale 3)
• Ambient operating temperature is 25 °C and VDD=3.3 V.
DS11853 Rev 9 121/226

196
Table 35. Peripheral current consumption

IDD(Typ)(1)
Peripheral Unit
Scale 1 Scale 2 Scale 3
GPIOA 3.6 3.4 2.9

GPIOB 3.7 3.6 3.1
GPIOC 3.7 3.4 3.0
GPIOD 3.7 3.6 3.0
GPIOE 3.6 3.4 2.9
GPIOF 3.5 3.4 2.9
AHB1 GPIOG 3.5 3.3 2.8
(up to µA/MHz
216 MHz) GPIOH 3.5 3.4 2.9
GPIOI 3.5 3.3 2.9
CRC 1.2 1.1 0.9
BKPSRAM 0.8 0.7 0.6
DMA1 3.07 x N + 8.7 2.98 x N + 8.4 2.52 x N + 7.02
DMA2 3.01 x N + 7.98 2.95 x N + 7.95 2.48 x N + 6.69
OTG_HS+ULPI 54.4 53.2 44.6
RNG 1.9 1.8 1.6
AHB2
(up to USB_OTG_FS 28.7 27.9 23.5 µA/MHz
216 MHz)
FMC 16.2 15.8 13.3
AHB3
(up to µA/MHz
216 MHz)
QSPI 16.9 16.3 13.8
Bus matrix(2) 15.8 12.8 8.5 µA/MHz
122/226 DS11853 Rev 9

Table 35. Peripheral current consumption (continued)

IDD(Typ)(1)
Peripheral Unit
TIM2 19.3 18.2 15.6

TIM3 15 14 12.2
TIM4 15.7 15.1 12.8
TIM5 18 16.9 14.4
TIM6 3.7 3.1 2.8
TIM7 3.5 2.9 2.5
TIM12 8.1 7.8 6.4
TIM13 6.1 5.1 4.7
TIM14 6.3 5.6 4.7
LPTIM1 9.4 9.8 8.3
WWDG 2.4 1.3 1.4
(3)
SPI2/I2S2 6.7 6 5.3
APB1
(up to SPI3/I2S3(3) 4.8 3.8 3.3 µA/MHz
54 MHz)
USART2 13.3 12 10.6
USART3 12.8 12 10.3
UART4 11.7 10.7 9.2
UART5 11.7 10.2 8.9
I2C1 10.6 9.6 8.3
I2C2 10.6 9.6 8.3
I2C3 10.7 9.8 8.3
CAN1 8.9 8 6.9
PWR 11.3 11.3 8.9
(4)
DAC 6.1 5.1 4.4
UART7 13.3 12 10.3
UART8 12.6 11.6 9.7
DS11853 Rev 9 123/226

196
Table 35. Peripheral current consumption (continued)

IDD(Typ)(1)
Peripheral Unit
TIM1 24.9 23.8 20

TIM8 24.5 23.7 20
USART1 12.4 11.6 10
USART6 12.3 11.7 10
ADC1(5) 6.3 5.8 4.9
(5)
ADC2 6.3 5.6 4.9
(5)
ADC3 6.4 5.8 5
SDMMC1 9.1 8.3 7.1
SDMMC2 7 7.2 6
APB2 (3)
SPI1/I2S1 3.2 3.2 2.6
(up to µA/MHz
108 MHz) SPI4 2.9 2.9 2.2
SYSCFG 1 1 0.7
TIM9 9.9 9.1 7.8
TIM10 7 6.4 5.6
TIM11 7.2 6.8 5.7
SPI5 4.8 4.1 3.6
SAI1 5.6 4.9 4.2
SAI2 5.4 4.7 4
USB PHY HS
8.3 7.9 6.7
Controller
1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA.
2. The BusMatrix is automatically active when at least one master is ON.
3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.
4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of
0.75 mA per DAC channel for the analog part.
5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of
1.73 mA per ADC for the analog part.
124/226 DS11853 Rev 9

USB OTG HS and USB OTG HS PHY current consumption (on STM32F723xx
devices)
• STM32 MCU is enumerated as a HID device.
• fHCLK = 216 MHz (Scale 1 + over-drive ON), fHCLK = 168 MHz (Scale 2),
fHCLK = 144 MHz (Scale 3)
The given value is calculated by measuring the difference of current consumption in
case:
– USB is configured but no transfer is done.
– USB is configured and there is a transmission on going.
• Ambient operating temperature is 25 °C, VDD = VDDUSB = 3.3 V.
Table 36. USB OTG HS and USB OTG PHY HS current consumption
IDD (Typ)
- Unit
USB OTG HS and USB OTG HS PHY

50.16 44.92 38.98 mA
current consumption
6.3.8 Wakeup time from low-power modes

The wakeup times given in Table 37 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD = 3.3 V.
Table 37. Low-power mode wakeup timings

Symbol Parameter Conditions Typ(1) Max(1) Unit
CPU
Wakeup from Sleep
tWUSLEEP(2) - 13 13 clock
mode
cycles
Main regulator is ON 14 14.9
Main regulator is ON and Flash

104.1 107.6
memory in Deep power down mode
Wakeup from Stop mode
tWUSTOP(2) with MR/LP regulator in µs
normal mode Low power regulator is ON 21.4 24.2
Low power regulator is ON and Flash

111.5 116.5
memory in Deep power down mode
DS11853 Rev 9 125/226

196
Table 37. Low-power mode wakeup timings (continued)

Symbol Parameter Conditions Typ(1) Max(1) Unit
Main regulator in under-drive mode

(Flash memory in Deep power-down 107.4 113.2
Wakeup from Stop mode mode)
tWUSTOP(2) with MR/LP regulator in Low power regulator in under-drive µs
Under-drive mode mode
112.7 120
(Flash memory in Deep power-down
mode)
Wakeup from Standby Exit Standby mode on rising edge 308 313
tWUSTDBY(2) µs
mode Exit Standby mode on falling edge 307 313
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first
6.3.9 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 61: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 37.
The characteristics given in Table 38 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 16.
Table 38. High-speed external user clock characteristics

fHSE_ext External user clock source frequency(1) 1 - 50 MHz

VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
-
tw(HSE)
OSC_IN high or low time(1) 5 - -
tw(HSE)
ns
tr(HSE)
OSC_IN rise or fall time(1) - - 10
tf(HSE)
Cin(HSE) OSC_IN input capacitance(1) - - 5 - pF
DuCy(HSE) Duty cycle - 45 - 55 %
IL OSC_IN Input leakage current VSS ≤VIN ≤VDD - - ±1 µA
126/226 DS11853 Rev 9

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 61: I/O static characteristics. However, the
recommended clock input waveform is shown in Figure 38.
The characteristics given in Table 39 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 16.
Table 39. Low-speed external user clock characteristics

User External clock source

fLSE_ext - 32.768 1000 kHz
frequency(1)
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3VDD
tw(LSE)
OSC32_IN high or low time(1) 450 - -
tf(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time(1) - - 50
tf(LSE)
Cin(LSE) OSC32_IN input capacitance(1) - - 5 - pF
DuCy(LSE) Duty cycle - 30 - 70 %
IL OSC32_IN Input leakage current VSS ≤VIN ≤VDD - - ±1 µA
Figure 37. High-speed external clock source AC timing diagram
VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t
THSE
External fHSE_ext
IL
clock source OSC_IN
STM32F
ai17528
DS11853 Rev 9 127/226

196
Figure 38. Low-speed external clock source AC timing diagram
VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t
TLSE
External fLSE_ext
OSC32_IN IL
clock source
STM32F
ai17529
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 40. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 40. HSE 4-26 MHz oscillator characteristics(1)

fOSC_IN Oscillator frequency - 4 - 26 MHz

RF Feedback resistor - - 200 - kΩ
VDD=3.3 V,
ESR= 30 Ω, - 450 -
CL=5 pF@25 MHz
IDD HSE current consumption µA
VDD=3.3 V,
ESR= 30 Ω, - 530 -
CL=10 pF@25 MHz
ACCHSE(2) HSE accuracy - − 500 - 500 ppm
Gm_crit_max Maximum critical crystal gm Startup - - 1 mA/V
tSU(HSE(3) Startup time VDD is stabilized - 2 - ms
2. This parameter depends on the crystal used in the application. The minimum and maximum values must
be respected to comply with USB standard specifications.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is based on characterization results. It is measured for a standard crystal
resonator and it can vary significantly with the crystal manufacturer.
128/226 DS11853 Rev 9

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 39). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 39. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MHz RF controlled
resonator
gain
REXT(1) OSC_OU T STM32F

CL2
ai17530
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 41. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) (1)

LSEDRV[1:0]=00
- 250 -
Low drive capability
LSEDRV[1:0]=10
- 300 -
Medium low drive capability
IDD LSE current consumption nA
LSEDRV[1:0]=01
- 370 -
Medium high drive capability
LSEDRV[1:0]=11
- 480 -
High drive capability
DS11853 Rev 9 129/226

196
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) (continued)
LSEDRV[1:0]=00
- - 0.48
Low drive capability
LSEDRV[1:0]=10
- - 0.75
Medium low drive capability
Gm_crit_max Maximum critical crystal gm µA/V
LSEDRV[1:0]=01
- - 1.7
Medium high drive capability
LSEDRV[1:0]=11
- - 2.7
High drive capability
tSU(2) start-up time VDD is stabilized - 2 - s
2. Guaranteed by characterization results. tSU is the start-up time measured from the moment it is enabled
(by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST Microelectronics website
www.st.com.
Figure 40. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
C L1
OSC32_ IN f LSE
Bias
32.768 kHz RF controlled
resonator
gain
OSC32_ OU T STM32F
C L2
ai17531a
6.3.10 Internal clock source characteristics

The parameters given in Table 42 and Table 43 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 16.
High-speed internal (HSI) RC oscillator
Table 42. HSI oscillator characteristics (1)

fHSI Frequency - - 16 - MHz

HSI user trimming step(2) - - - 1 %
TA = –40 to 105 °C(3) −8 - 4.5 %
ACCHSI
Accuracy of the HSI oscillator TA = –10 to 85 °C(3) −4 - 4 %
TA = 25 °C(4) −1 - 1 %
130/226 DS11853 Rev 9

Table 42. HSI oscillator characteristics (1) (continued)

(2)
tsu(HSI) HSI oscillator startup time - - 2.2 4 µs
IDD(HSI)(2) HSI oscillator power consumption - - 60 80 µA
1. VDD = 3.3 V, PLL OFF, TA = –40 to 105 °C unless otherwise specified.
4. Factory calibrated, parts not soldered.
Figure 41. ACCHSI versus temperature
2
ACCHSI(%)
0
-40 0 25 55 85 105 125
TA ( °C)
-2
-4
Min Max Typical

-6
-8
MSv41055V1
Low-speed internal (LSI) RC oscillator
Table 43. LSI oscillator characteristics (1)

Symbol Parameter Min Typ Max Unit
fLSI(2) Frequency 17 32 47 kHz

(3)
tsu(LSI) LSI oscillator startup time - 15 40 µs
(3)
IDD(LSI) LSI oscillator power consumption - 0.4 0.6 µA
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
DS11853 Rev 9 131/226

196
Figure 42. LSI deviation versus temperature
8.0%
6.0%
4.0%
Normalized deviation (%)
2.0%
Min
0.0% Max
-40°C 0°C 25°C 85°C 105°C 125°C
Typical
-2.0%
-4.0%
-6.0%
-8.0%
Temperature (°C)
MS37554V1
6.3.11 PLL characteristics

The parameters given in Table 44 and Table 45 are derived from tests performed under
Table 44. Main PLL characteristics

fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10

fPLL_OUT PLL multiplier output clock - 24 - 216
MHz
fPLL48_OUT 48 MHz PLL multiplier output clock - - 48 75
fVCO_OUT PLL VCO output - 100 - 432
VCO freq = 100 MHz 75 - 200
tLOCK PLL lock time µs
VCO freq = 432 MHz 100 - 300
132/226 DS11853 Rev 9

Table 44. Main PLL characteristics (continued)

RMS - 25 -
Cycle-to-cycle jitter peak to
- ±150 -
System clock peak
216 MHz RMS - 15 -
Period Jitter peak to
- ±200 -
(3) peak
Jitter ps
Main clock output (MCO) for RMII Cycle to cycle at 50 MHz
- 32 -
Ethernet on 1000 samples
Main clock output (MCO) for MII Cycle to cycle at 25 MHz
- 40 -
Ethernet on 1000 samples
Cycle to cycle at 1 MHz
Bit Time CAN jitter - 330 -
on 1000 samples
VCO freq = 100 MHz 0.15 0.40
IDD(PLL)(4) PLL power consumption on VDD - mA
VCO freq = 432 MHz 0.45 0.75
VCO freq = 100 MHz 0.30 0.40
IDDA(PLL)(4) PLL power consumption on VDDA - mA
VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
Table 45. PLLI2S characteristics

fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.10

fPLLI2SQ_OUT PLLI2S multiplier output clock for SAI - - - 216
MHz
fPLLI2SR_OUT PLLI2S multiplier output clock for I2S - - - 216
fVCO_OUT PLLI2S VCO output - 100 - 432
VCO freq = 100 MHz 75 - 200
tLOCK PLLI2S lock time µs
VCO freq = 432 MHz 100 - 300
Cycle to cycle at RMS - 90 - ps
12.288 MHz on
48KHz period, peak
- ±280 - ps
N=432, R=5 to peak
Master I2S clock jitter
Average frequency of
(3)
Jitter 12.288 MHz
- 90 - ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 kHz
WS I2S clock jitter - 400 - ps
on 1000 samples
DS11853 Rev 9 133/226

196
Table 45. PLLI2S characteristics (continued)

VCO freq = 100 MHz 0.15 0.40

IDD(PLLI2S)(4) PLLI2S power consumption on VDD - mA
VCO freq = 432 MHz 0.45 0.75
VCO freq = 100 MHz 0.30 0.40
IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA - mA
VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
3. Value given with main PLL running.
Table 46. PLLISAI characteristics

fPLLSAI_IN PLLSAI input clock(1) - 0.95(2) 1 2.10

PLLSAI multiplier output clock
fPLLSAIP_OUT - - 48 75
for 48 MHz
MHz
PLLSAI multiplier output clock
fPLLSAIQ_OUT - - - 216
for SAI
fVCO_OUT PLLSAI VCO output - 100 - 432
VCO freq = 100 MHz 75 - 200
tLOCK PLLSAI lock time µs
VCO freq = 432 MHz 100 - 300
Cycle to cycle at RMS - 90 - ps

12.288 MHz on peak
48KHz period, to - ± 280 - ps
N=432, R=5 peak
Master SAI clock jitter
(3) Average frequency of
Jitter
12.288 MHz
- 90 - ps
N = 432, R = 5
on 1000 samples
Cycle to cycle at 48 KHz
FS clock jitter - 400 - ps
on 1000 samples
PLLSAI power consumption on VCO freq = 100 MHz 0.15 0.40
IDD(PLLSAI)(4) - mA
VDD VCO freq = 432 MHz 0.45 0.75
PLLSAI power consumption on VCO freq = 100 MHz 0.30 0.40
IDDA(PLLSAI)(4) - mA
VDDA VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
3. Value given with main PLL running.
134/226 DS11853 Rev 9

6.3.12 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature is used to reduce electromagnetic
interferences (see Table 57: EMI characteristics). It is available only on the main PLL.
Table 47. SSCG parameters constraint

Symbol Parameter Min Typ Max(1) Unit
fMod Modulation frequency - - 10 kHz

md Peak modulation depth 0.25 - 2 %
MODEPER * INCSTEP - - - 215 −1 -
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round [ f PLL_IN ⁄ ( 4 × f Mod ) ]
fPLL_IN and fMod must be expressed in Hz.

As an example:
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
6 3
MODEPER = round [ 10 ⁄ ( 4 × 10 ) ] = 250
Equation 2
Equation 2 calculates the increment step (INCSTEP):
15
INCSTEP = round [ ( ( 2 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ]
fVCO_OUT must be expressed in MHz.

With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
15
INCSTEP = round [ ( ( 2 – 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
15
md quantized % = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2 – 1 ) × PLLN )
As a result:
15
md quantized % = ( 250 × 126 × 100 × 5 ) ⁄ ( ( 2 – 1 ) × 240 ) = 2.002%(peak)
DS11853 Rev 9 135/226

196
Figure 43 and Figure 44 show the main PLL output clock waveforms in center spread and
down spread modes, where:
• F0 is fPLL_OUT nominal.
• Tmode is the modulation period.
• md is the modulation depth.
Figure 43. PLL output clock waveforms in center spread mode
Frequency (PLL_OUT)
md
F0
md
Time
tmode 2xtmode
ai17291
Figure 44. PLL output clock waveforms in down spread mode

Frequency (PLL_OUT)
F0
2xmd
Time
tmode 2xtmode
ai17292b
6.3.13 USB OTG HS PHY PLLs characteristics (on STM32F723xx devices)

The parameters given in Table 48 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 16.
Table 48. USB OTG HS PLL1 characteristics(1)

fPLL1_IN PLL1 input clock - 12, 12.5, 16, 24, 25

fPLL1_OUT PLL1 output clock(2) - - 60 - MHz
fVCO_OUT PLL1 VCO output - 600 - 720
tLOCK PLL1 lock time(2) - - - 22 µs
IDD(PLL1) PLL1 digital power consumption - - - 1.8
mA
IDDA(PLL1) PLL1 analog power consumption - - - 2.75
136/226 DS11853 Rev 9

2. Based on test during characterization.
Table 49. USB OTG HS PLL2 characteristics(1)

fPLL2_IN PLL2 input clock - - 60 -

fPLL2_OUT PLL2 output clock(2) - - 480 - MHz
fVCO_OUT PLL2 VCO output - - 480 -
tLOCK PLL2 lock time(2) - - - 91 µs
IDD(PLL2) PLL2 digital power consumption - - - 2.1
mA
IDDA(PLL2) PLL2 analog power consumption - - - 1.5
6.3.14 USB OTG HS PHY regulator characteristics
The parameters given in Table 50 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 16.
Table 50. USB OTG HS PHY regulator characteristics(1)

VDD12OTGHS 1.2 V internal voltage on VDD12OTGHS - 1.18 1.2 1.24 V

CEXT External capacitor on VDD12OTGHS - 1.1 2.2 3.3 µF
IDDPHYHSREG Regulator power consumption - 100 120 125 µA
DS11853 Rev 9 137/226

196
6.3.15 USB HS PHY external resistor characteristics

(on STM32F723xx devices)
Table 51. USB HS PHY external resistor characteristics (on STM32F723xx devices)
External calibration resistor connected Required if using

REXT 2.97 3.00 3.03 kΩ
(to GND) from OTG_HS_REXT USB HS PHY
6.3.16 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Table 52. Flash memory characteristics

Write/erase 8-bit mode, VDD = 1.7 V - 6.7 -

IDD Supply current Write/erase 16-bit mode, VDD = 2.1 V - 9.2 - mA
Write/erase 32-bit mode, VDD = 3.3 V - 12.6 -
Table 53. Flash memory programming

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Program/erase parallelism
tprog Word programming time - 16 100(2) µs
(PSIZE) = x 8/16/32
- 346 418
(PSIZE) = x 8
Sector (16 Kbytes) erase Program/erase parallelism
tERASE16KB - 252 312 ms
time (PSIZE) = x 16
- 208 265
(PSIZE) = x 32
- 1953 2500
(PSIZE) = x 8
tERASE128KB - 1252 1639 ms
time (PSIZE) = x 16
- 927 1322
(PSIZE) = x 32
- 1027 1298
(PSIZE) = x 8
tERASE64KB - 675 840 ms
time (PSIZE) = x 16
- 505 682
(PSIZE) = x 32
138/226 DS11853 Rev 9

Table 53. Flash memory programming (continued)

- 7718 9883
(PSIZE) = x 8
tME Mass erase time - 4869 6379 ms
(PSIZE) = x 16
- 3503 5180
(PSIZE) = x 32
32-bit program operation 2.7 - 3.6 V
Vprog Programming voltage 16-bit program operation 2.1 - 3.6 V
8-bit program operation 1.7 - 3.6 V
2. The maximum programming time is measured after 10 K erase operations.
Table 54. Flash memory programming with VPP

tprog Double word programming - 16 100(2) µs

Sector (16 Kbytes) erase
tERASE16KB - 180 -
time
TA = 0 to +40 °C
tERASE128KB VDD = 3.3 V - 900 - ms
time
VPP = 8.5 V
tERASE64KB - 450 -
time
tME Mass erase time - 6.9 - s
Vprog Programming voltage - 2.7 - 3.6 V
VPP VPP voltage range - 7 - 9 V
Minimum current sunk on
IPP - 10 - - mA
the VPP pin
Cumulative time during
tVPP(3) - - - 1 hour
which VPP is applied
2. The maximum programming time is measured after 10 K erase operations.
3. VPP should only be connected during programming/erasing.
Table 55. Flash memory endurance and data retention

Value
Min(2)
TA = –40 to +85 °C (6 suffix versions)

NEND Endurance 10 kcycles
TA = –40 to +105 °C (7 suffix versions)
DS11853 Rev 9 139/226

196
Table 55. Flash memory endurance and data retention (continued)

Value
Min(2)
1 kcycle(3) at TA = 85 °C 30
tRET Data retention 1 kcycle(3) at TA = 105 °C 10 Years
(3)
10 kcycles at TA = 55 °C 20
1. Tj can not go above 125°C (current consumption limitation).
3. Cycling performed over the whole temperature range.
6.3.17 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 56. They are based on the EMS levels and classes
defined in application note AN1709.
Table 56. EMS characteristics

Level/
Class
VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O
VFESD fHCLK = 216 MHz, 2B
pin to induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA =+25 °C,

VEFTB applied through 100 pF on VDD and VSS fHCLK = 216 MHz, 5A
pins to induce a functional disturbance conforms to IEC 61000-4-2
As a consequence, it is recommended to add a serial resistor (1 kΩ) located as close as

possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm
on PCB).
140/226 DS11853 Rev 9

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 57. EMI characteristics

Max vs.
Monitored [fHSE/fCPU]
frequency band
25/200 MHz
0.1 MHz to 30 MHz 23

VDD = 3.6 V, TA = 25 °C, conforming to 30 MHz to 130 MHz 20
IEC61967-2 ART/L1-cache OFF, over-drive ON, dBµV
SEMI Peak level 130 MHz to 1 GHz 34
all peripheral clocks enabled, clock dithering
disabled. 1 GHz to 2 GHz 24
EMI Level 4 -
6.3.18 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
DS11853 Rev 9 141/226

196
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/ESDA/JEDEC JS-001-2012 and ANSI/ESD S5.3.1-2009 standards.
Table 58. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)
Electrostatic discharge TA = +25 °C conforming to

VESD(HBM) 2 2000
voltage (human body model) ANSI/ESDA/JEDEC JS-001-2012
TA = +25 °C conforming to ANSI/ESD V
Electrostatic discharge
VESD(CDM) STM5.3.1-2009, all the packages 3 250
voltage (charge device model)
excepted WLCSP100
Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
Table 59. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
6.3.19 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit
(>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins
(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator
frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 60.
142/226 DS11853 Rev 9

Table 60. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on BOOT0, PDR_ON, BYPASS_REG,

-0 0
OTG_HS_REXT
Injected current on NRST -0 NA(1)
IINJ Injected current on PF9, PF10, PH0_OSCIN, PH1_OSCOUT, PC0, mA
-0 NA(1)
PC1, PC2, PC3, PB14(2), PB15(2)
Injected current on any other FT or FTf pins -5 NA(1)
Injected current on any other pins -5 +5
1. Injection is not possible.
2. PB14 and PB15 in the STM32F723xx devices.
Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.20 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 61: I/O static characteristics are
derived from tests performed under the conditions summarized in Table 16. All I/Os are
CMOS and TTL compliant.
Table 61. I/O static characteristics

FT, TTa and NRST I/O input 0.35VDD −0.04(1)

1.7 V≤VDD≤3.6 V - -
low level voltage 0.3VDD(2)
VIL 1.75 V≤VDD ≤3.6 V, V

- -
BOOT I/O input low level –40 °C≤TA ≤105 °C
0.1VDD+0.1(1)
voltage 1.7 V≤VDD ≤3.6 V,
- -
0 °C≤TA ≤105 °C
FT, TTa and NRST I/O input 0.45VDD+0.3(1)

1.7 V≤VDD≤3.6 V - -
high level voltage(5) 0.7VDD(2)
VIH 1.75 V≤VDD ≤3.6 V, V

BOOT I/O input high level –40 °C≤TA ≤105 °C
0.17VDD +0.7(1) - -
voltage 1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
DS11853 Rev 9 143/226

196
Table 61. I/O static characteristics (continued)

FT, TTa and NRST I/O input

1.7 V≤VDD≤3.6 V 10%VDD(3) - -
hysteresis
1.75 V≤VDD ≤3.6 V,
VHYS V
–40 °C≤TA ≤105 °C
BOOT I/O input hysteresis 0.1 - -
1.7 V≤VDD ≤3.6 V,
0 °C≤TA ≤105 °C
I/O input leakage current (4) VSS ≤VIN ≤VDD - - ±1
Ilkg µA
I/O FT input leakage current (5) VIN = 5 V - - 3
All pins except
for
PA10/PB12 30 40 50
Weak pull-up (OTG_FS_ID,
RPU equivalent OTG_HS_ID) VIN = VSS
resistor(6)
PA10/PB12
(OTG_FS_ID, 7 10 14
OTG_HS_ID)
kΩ
All pins except
for
Weak pull- PA10/PB12 30 40 50
down (OTG_FS_ID,
RPD OTG_HS_ID) VIN = VDD
equivalent
resistor(7) PA10/PB12
(OTG_FS_ID, 7 10 14
OTG_HS_ID)
CIO(8) I/O pin capacitance - - 5 - pF
2. Tested in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 60: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 60: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
144/226 DS11853 Rev 9

All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 45.
Figure 45. FT I/O input characteristics

VIL/VIH (V)
2.52
DD
7V
0.
=
in
IHm
tV
en
m
uire TTL requirement
req VIHmin = 2V
2.0 OS
M .3
1.92 -C +0
n V DD
io .45
u ct 0
1.7 od in=
pr VIH
m
in ,
d ns
st
e
la tio
Te imu
igns
D es
1.22 on
d Area not determined 4
1.19 se -0.0
Ba VDD
.35
1.065 a x= 0
ILm
atio ns, V
simul
0.8 sign
o n De
B ased TTL requirement
0.55 VILmax = 0.8V
0.51
Tested in production - CMOS requirement VILmax = 0.3VDD
VDD (V)
1.7 2.0 2.4 2.7 3.3 3.6
MS33746V2
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which
can sink or source up to ±3 mA. When using the PC13 to PC15 and PI8 GPIOs in output
mode, the speed must not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 14).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 14).
DS11853 Rev 9 145/226

196
Output voltage levels

Unless otherwise specified, the parameters given in Table 62 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 16. All I/Os are CMOS and TTL compliant.
Table 62. Output voltage characteristics

CMOS port(2)
VOL(1) Output low level voltage for an I/O pin IIO = +8 mA - 0.4
2.7 V ≤VDD ≤3.6 V
CMOS port(2)
Output high level voltage for an I/O pin
VOH(3) IIO = -8 mA VDD − 0.4 - V
except PC14
2.7 V ≤VDD ≤3.6 V
CMOS port(2)
VOH(3) Output high level voltage for PC14 IIO = -2 mA VDD − 0.4 -
2.7 V ≤VDD ≤3.6 V
TTL port(2)
(1)
VOL Output low level voltage for an I/O pin IIO =+8mA - 0.4
2.7 V ≤VDD ≤3.6 V
V
TTL port(2)
Output high level voltage for an I/O pin
VOH (3) IIO =-8mA 2.4 -
except PC14
2.7 V ≤VDD ≤3.6 V
IIO = +20 mA
VOL(1) Output low level voltage for an I/O pin - 1.3(4)
2.7 V ≤VDD ≤3.6 V
V
Output high level voltage for an I/O pin IIO = -20 mA
VOH(3) VDD −1.3(4) -
except PC14 2.7 V ≤VDD ≤3.6 V
IIO = +6 mA
1.8 V ≤VDD ≤3.6 V
V
VOH(3) VDD −0.4(4) -
except PC14 1.8 V ≤VDD ≤3.6 V
IIO = +4 mA
1.7 V ≤VDD ≤3.6V
VOH(3) VDD −0.4(5) - V
except PC14 1.7 V ≤VDD ≤3.6V
IIO = -1 mA
VOH(3) Output high level voltage for PC14 VDD −0.4(5) -
1.7 V ≤VDD ≤3.6V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 14.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data.
146/226 DS11853 Rev 9

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 46 and
Table 63, respectively.
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 16.
Table 63. I/O AC characteristics(1)(2)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)
CL = 50 pF, VDD ≥ 2.7 V - - 4

CL = 50 pF, VDD ≥ 1.7 V - - 2
fmax(IO)out Maximum frequency(3) CL = 10 pF, VDD ≥ 2.7 V - - 8 MHz
00 CL = 10 pF, VDD ≥ 1.8 V - - 4

CL = 10 pF, VDD ≥ 1.7 V - - 3
Output high to low level fall
tf(IO)out/ CL = 50 pF, VDD = 1.7 V to
time and output low to high - - 100 ns
tr(IO)out 3.6 V
level rise time
CL = 50 pF, VDD≥ 2.7 V - - 25
CL = 50 pF, VDD≥ 1.8 V - - 12.5
CL = 50 pF, VDD≥ 1.7 V - - 10
fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD ≥ 2.7 V - - 50
CL = 10 pF, VDD≥ 1.8 V - - 20
01
CL = 10 pF, VDD≥ 1.7 V - - 12.5
CL = 50 pF, VDD ≥ 2.7 V - - 10
Output high to low level fall CL = 10 pF, VDD ≥ 2.7 V - - 6
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 50 pF, VDD ≥ 1.7 V - - 20
level rise time
CL = 10 pF, VDD ≥ 1.7 V - - 10
CL = 40 pF, VDD ≥ 2.7 V - - 50(4)
CL = 10 pF, VDD ≥ 2.7 V - - 100(4)
fmax(IO)out Maximum frequency(3) CL = 40 pF, VDD ≥ 1.7 V - - 25 MHz
CL = 10 pF, VDD ≥ 1.8 V - - 50
10 CL = 10 pF, VDD ≥ 1.7 V - - 42.5
CL = 40 pF, VDD ≥2.7 V - - 6
Output high to low level fall CL = 10 pF, VDD ≥ 2.7 V - - 4
tf(IO)out/
tr(IO)out CL = 40 pF, VDD ≥ 1.7 V - - 10
level rise time
CL = 10 pF, VDD ≥ 1.7 V - - 6
DS11853 Rev 9 147/226

196
Table 63. I/O AC characteristics(1)(2) (continued)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)
CL = 30 pF, VDD ≥ 2.7 V - - 100(4)

CL = 30 pF, VDD ≥ 1.8 V - - 50
CL = 30 pF, VDD ≥ 1.7 V - - 42.5
fmax(IO)out Maximum frequency(3) MHz
CL = 10 pF, VDD≥ 2.7 V - - 180(4)
CL = 10 pF, VDD ≥ 1.8 V - - 100
CL = 10 pF, VDD ≥ 1.7 V - - 72.5
11
CL = 30 pF, VDD ≥ 2.7 V - - 4
CL = 30 pF, VDD ≥1.8 V - - 6
Output high to low level fall CL = 30 pF, VDD ≥1.7 V - - 7
tf(IO)out/
tr(IO)out CL = 10 pF, VDD ≥ 2.7 V - - 2.5
level rise time
CL = 10 pF, VDD ≥1.8 V - - 3.5
CL = 10 pF, VDD ≥1.7 V - - 4
Pulse width of external signals
- tEXTIpw detected by the EXTI - 10 - - ns
controller
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F72xxx and STM32F73xxx reference
manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 46.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Figure 46. I/O AC characteristics definition
90% 10%
50% 50%
10% 90%
EXTERNAL tr(IO)out tf(IO)out

OUTPUT
ON CL T
Maximum frequency is achieved if (tr + tf 7DQGLIWKHGXW\F\FOHLV

ZKHQORDGHGE\&LVSHFLILHGLQWKHWDEOH³I/O AC characteristics”.
ai14131d
148/226 DS11853 Rev 9

6.3.21 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 61: I/O static characteristics).
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 16.
Table 64. NRST pin characteristics

RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 kΩ

VF(NRST) (2) NRST Input filtered pulse - - - 100 ns
VNF(NRST)(2) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns
TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
Figure 47. Recommended NRST pin protection
VDD
External
reset circuit (1)
RPU
NRST (2) Internal Reset
Filter
0.1 μF
STM32F
ai14132c
1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as
possible to the chip.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 61. Otherwise the reset is not taken into account by the device.
DS11853 Rev 9 149/226

196
6.3.22 TIM timer characteristics

The parameters given in Table 65 are guaranteed by design.
Refer to Section 6.3.20: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 65. TIMx characteristics(1)(2)

Symbol Parameter Conditions(3) Min Max Unit
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK = 1 - tTIMxCLK
216 MHz
tres(TIM) Timer resolution time
AHB/APBx
prescaler>4, fTIMxCLK = 1 - tTIMxCLK
108 MHz
Timer external clock
fEXT 0 fTIMxCLK/2 MHz
frequency on CH1 to CH4 f
TIMxCLK = 216 MHz
ResTIM Timer resolution - 16/32 bit
Maximum possible count 65536 ×
tMAX_COUNT - - tTIMxCLK
with 32-bit counter 65536
1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.
3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the
RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK,
otherwise TIMxCLK = 4x PCLKx.
6.3.23 RTC characteristics
Table 66. RTC characteristics

Symbol Parameter Conditions Min Max
Any read/write operation

- fPCLK1/RTCCLK frequency ratio 4 -
from/to an RTC register
6.3.24 12-bit ADC characteristics

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 16.
Table 67. ADC characteristics
VDDA Power supply 1.7(1) - 3.6 V

VDDA −VREF+ < 1.2 V
VREF+ Positive reference voltage 1.7(1) - VDDA V
VREF- Negative reference voltage - - 0 - V
(1)
VDDA = 1.7 to 2.4 V 0.6 15 18 MHz
fADC ADC clock frequency
VDDA = 2.4 to 3.6 V 0.6 30 36 MHz
150/226 DS11853 Rev 9

Table 67. ADC characteristics (continued)

fADC = 30 MHz,
- - 1764 kHz
fTRIG(2) External trigger frequency 12-bit resolution
- - - 17 1/fADC
0
VAIN Conversion voltage range(3) - (VSSA or VREF- - VREF+ V
tied to ground)
See Equation 1 for
RAIN(2) External input impedance - - 50 κΩ
details
RADC(2)(4) Sampling switch resistance - 1.5 - 6 κΩ
Internal sample and hold
CADC(2) - - 4 7 pF
capacitor
Injection trigger conversion fADC = 30 MHz - - 0.100 µs

tlat(2)
latency - - - 3(5) 1/fADC
Regular trigger conversion fADC = 30 MHz - - 0.067 µs

tlatr(2)
latency - - - 2(5) 1/fADC
fADC = 30 MHz 0.100 - 16 µs
tS(2) Sampling time
- 3 - 480 1/fADC
tSTAB(2) Power-up time - - 2 3 µs
fADC = 30 MHz
0.50 - 16.40 µs
12-bit resolution
fADC = 30 MHz
0.43 - 16.34 µs
10-bit resolution
Total conversion time (including fADC = 30 MHz
tCONV(2) 0.37 - 16.27 µs
sampling time) 8-bit resolution
fADC = 30 MHz
0.30 - 16.20 µs
6-bit resolution
9 to 492 (tS for sampling +n-bit resolution for successive
1/fADC
approximation)
12-bit resolution
- - 2.4 Msps
Single ADC
Sampling rate 12-bit resolution

Interleave Dual ADC - - 4.5 Msps
fS(2) (fADC = 36 MHz, and
mode
tS = 3 ADC cycles)
12-bit resolution
Interleave Triple ADC - - 7.2 Msps
mode
DS11853 Rev 9 151/226

196
Table 67. ADC characteristics (continued)

ADC VREF DC current

IVREF+(2) consumption in conversion - - 300 500 µA
mode
ADC VDDA DC current
IVDDA(2) consumption in conversion - - 1.6 1.8 mA
mode
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
4. RADC maximum value is given for VDD = 1.7 V, and minimum value for VDD = 3.3 V.
5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67.
Equation 1: RAIN max formula
R AIN
( k – 0.5 )
= ---------------------------------------------------------------
- – R ADC
N+2
f ADC × C ADC × ln ( 2 )
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
Table 68. ADC static accuracy at fADC = 18 MHz

Symbol Parameter Test conditions Typ Max(1) Unit
ET Total unadjusted error ±3 ±4

fADC =18 MHz
EO Offset error ±2 ±3
VDDA = 1.7 to 3.6 V
LSB
EG Gain error VREF = 1.7 to 3.6 V ±1 ±3
ED Differential linearity error VDDA −VREF < 1.2 V ±1 ±2
EL Integral linearity error ±2 ±3


fADC = 30 MHz,
EO Offset error ±1.5 ±2.5
RAIN < 10 kΩ,
EG Gain error VDDA = 2.4 to 3.6 V, ±1.5 ±4 LSB
VREF = 1.7 to 3.6 V,
ED Differential linearity error ±1 ±2
VDDA −VREF < 1.2 V
EL Integral linearity error ±1.5 ±3
152/226 DS11853 Rev 9



fADC =36 MHz,
EO Offset error ±2 ±3
VDDA = 2.4 to 3.6 V,
EG Gain error ±3 ±6 LSB
VREF = 1.7 to 3.6 V
ED Differential linearity error VDDA −VREF < 1.2 V ±2 ±3
EL Integral linearity error ±3 ±6
Table 71. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit
ENOB Effective number of bits 10.3 10.4 - bits

fADC =18 MHz
SINAD Signal-to-noise and distortion ratio VDDA = VREF+= 1.7 V 64 64.2 -
SNR Signal-to-noise ratio Input Frequency = 20 kHz 64 65 - dB
Temperature = 25 °C
THD Total harmonic distortion − 67 − 72 -
Table 72. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1)
Symbol Parameter Test conditions Min Typ Max Unit
ENOB Effective number of bits 10.6 10.8 - bits

fADC =36 MHz
SINAD Signal-to noise and distortion ratio VDDA = VREF+ = 3.3 V 66 67 -
SNR Signal-to noise ratio Input Frequency = 20 kHz 64 68 - dB
Temperature = 25 °C
THD Total harmonic distortion − 70 − 72 -
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.20 does not affect the ADC accuracy.
DS11853 Rev 9 153/226

196
Figure 48. ADC accuracy characteristics

V REF+ V DDA
[1LSB IDEAL = (or depending on package)]
4096 4096
EG
4095
4094
4093
(2)
ET
7 (3)
(1)
6
5
EO EL
4
3
ED
2
1L SBIDEAL
1
0
1 2 3 456 7 4093 4094 4095 4096
V SSA VDDA
ai14395c
1. See also Table 69.

2. Example of an actual transfer curve.
3. Ideal transfer curve.
4. End point correlation line.
5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 49. Typical connection diagram using the ADC
VDD STM32F
Sample and hold ADC
VT converter
0.6 V
RAIN(1) AINx RADC(1)
12-bit
converter
VT
VAIN
0.6 V C ADC(1)
Cparasitic
IL±1 μA
ai17534
1. Refer to Table 67 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
154/226 DS11853 Rev 9

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 50 or Figure 51,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32
VREF+ (1)
1 μF // 10 nF
VDDA
1 μF // 10 nF
(1)
VSSA/VREF+
ai17535c
1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on
UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA.
Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F
VREF+/VDDA (1)
1 μF // 10 nF
(1)
VREF-/VSSA
ai17536c
1. VREF+ input is available on all the packages except LQFP64, whereas the VREF– is available only on
UFBGA176 and UFBGA144. When VREF- is not available, it is internally connected to VSSA.
DS11853 Rev 9 155/226

196
6.3.25 Temperature sensor characteristics
Table 73. Temperature sensor characteristics

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

(1)
Avg_Slope Average slope - 2.5 - mV/°C
V25(1) Voltage at 25 °C - 0.76 - V
tSTART(2) Startup time - 6 10 µs
TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs
Table 74. Temperature sensor calibration values

Symbol Parameter Memory address
TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA= 3.3 V 0x1FF0 7A2C - 0x1FF0 7A2D
TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA= 3.3 V 0x1FF0 7A2E - 0x1FF0 7A2F
6.3.26 VBAT monitoring characteristics
Table 75. VBAT monitoring characteristics

R Resistor bridge for VBAT - 50 - KΩ

Q Ratio on VBAT measurement - 4 - -
Er(1) Error on Q –1 - +1 %
ADC sampling time when reading the VBAT
TS_vbat(2)(2) 5 - - µs
1 mV accuracy
2. Shortest sampling time can be determined in the application by multiple iterations.
6.3.27 Reference voltage

The parameters given in Table 76 are derived from tests performed under ambient
Table 76. internal reference voltage

VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V
ADC sampling time when reading the
TS_vrefint(1) - 10 - - µs
internal reference voltage
Internal reference voltage spread over the
VRERINT_s(2) VDD = 3V ± 10mV - 3 5 mV
temperature range
156/226 DS11853 Rev 9

Table 76. internal reference voltage (continued)

TCoeff(2) Temperature coefficient - - 30 50 ppm/°C

tSTART(2) Startup time - - 6 10 µs
1. Shortest sampling time can be determined in the application by multiple iterations.
Table 77. Internal reference voltage calibration values

Symbol Parameter Memory address
VREFIN_CAL Raw data acquired at temperature of 30 °C VDDA = 3.3 V 0x1FF0 7A2A - 0x1FF0 7A2B
6.3.28 DAC electrical characteristics
Table 78. DAC characteristics

Symbol Parameter Min Typ Max Unit Comments
VDDA Analog supply voltage 1.7(1) - 3.6 V -
VREF+ Reference supply voltage 1.7(1) - 3.6 V VREF+ ≤VDDA

VSSA Ground 0 - 0 V -
Connected to
5 - - kΩ -
(2) Resistive load VSSA
RLOAD
with buffer ON Connected to
25 - - kΩ -
VDDA
When the buffer is OFF, the Minimum
Impedance output with buffer
RO(2) - - 15 kΩ resistive load between DAC_OUT and
OFF
VSS to have a 1% accuracy is 1.5 MΩ
Maximum capacitive load at DAC_OUT
CLOAD(2) Capacitive load - - 50 pF
pin (when the buffer is ON).
DAC_OUT Lower DAC_OUT voltage It gives the maximum output excursion of

0.2 - - V the DAC.
min(2) with buffer ON
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V and
DAC_OUT Higher DAC_OUT voltage VDDA −
- - V (0x1C7) to (0xE38) at VREF+ = 1.7 V
max(2) with buffer ON 0.2
DAC_OUT Lower DAC_OUT voltage
- 0.5 - mV
min(2) with buffer OFF It gives the maximum output excursion of
DAC_OUT Higher DAC_OUT voltage VREF+ − the DAC.
- - V
max(2) with buffer OFF 1LSB
DS11853 Rev 9 157/226

196
Table 78. DAC characteristics (continued)

With no load, worst code (0x800) at

- 170 240 VREF+ = 3.6 V in terms of DC
DAC DC VREF current consumption on the inputs
IVREF+(4) consumption in quiescent µA
mode (Standby mode) With no load, worst code (0xF1C) at
- 50 75 VREF+ = 3.6 V in terms of DC
consumption on the inputs
With no load, middle code (0x800) on the
- 280 380 µA
DAC DC VDDA current inputs
IDDA(4) consumption in quiescent With no load, worst code (0xF1C) at
mode(3) - 475 625 µA VREF+ = 3.6 V in terms of DC
consumption on the inputs
Differential non linearity - - ±0.5 LSB Given for the DAC in 10-bit configuration.
DNL(4) Difference between two
consecutive code-1LSB)
- - ±2 LSB Given for the DAC in 12-bit configuration.
Integral non linearity - - ±1 LSB Given for the DAC in 10-bit configuration.
(difference between
measured value at Code i
INL(4)
and the value at Code i on a - - ±4 LSB Given for the DAC in 12-bit configuration.
line drawn between Code 0
and last Code 1023)
- - ±10 mV Given for the DAC in 12-bit configuration
Offset error
(difference between Given for the DAC in 10-bit at
- - ±3 LSB
Offset(4) measured value at Code VREF+ = 3.6 V
(0x800) and the ideal value =
Given for the DAC in 12-bit at
VREF+/2) - - ±12 LSB
VREF+ = 3.6 V
Gain
Gain error - - ±0.5 % Given for the DAC in 12-bit configuration
error(4)
Settling time (full scale: for a
10-bit input code transition
(4) between the lowest and the CLOAD ≤ 50 pF,
tSETTLING - 3 6 µs
highest input codes when RLOAD ≥ 5 kΩ
DAC_OUT reaches final
value ±4LSB
Total Harmonic Distortion CLOAD ≤ 50 pF,
THD(4) - - - dB
Buffer ON RLOAD ≥ 5 kΩ
Max frequency for a correct

Update DAC_OUT change when CLOAD ≤ 50 pF,
- - 1 MS/s
rate(2) small variation in the input RLOAD ≥ 5 kΩ
code (from code i to i+1LSB)
158/226 DS11853 Rev 9

Table 78. DAC characteristics (continued)

Wakeup time from off state CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ

tWAKEUP(4) (Setting the ENx bit in the - 6.5 10 µs input code between lowest and highest
DAC Control register) possible ones.
Power supply rejection ratio
PSRR+ (2) (to VDDA) (static DC - –67 –40 dB No RLOAD, CLOAD = 50 pF
measurement)
1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2:
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
Figure 52. 12-bit buffered /non-buffered DAC
Buffered/Non-buffered DAC
Buffer(1)
RL
12-bit DAC_OUTx
digital to
analog
converter
CL
ai17157V3
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.29 Communications interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
• Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0431 reference manual) and when the I2CCLK frequency is greater
than the minimum shown in the table below:
DS11853 Rev 9 159/226

196
Table 79. Minimum I2CCLK frequency in all I2C modes

Symbol Parameter Condition Min Unit
Standard-mode - 2
Analog Filter ON
10
DNF=0
Fast-mode
Analog Filter OFF
I2CCLK 9
f(I2CCLK) DNF=1 MHz
frequency
Analog Filter ON
22.5
DNF=0
Fast-mode Plus
Analog Filter OFF
16
DNF=1
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present.
The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the
maximum load Cload supported in Fm+, which is given by these formulas:
• Tr(SDA/SCL)=0.8473 x Rp x Cload
• Rp(min)= (VDD - VOL(max))/IOL(max)
Where Rp is the I2C lines pull-up. Refer to Section 6.3.20: I/O port characteristics for the
I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 80. I2C analog filter characteristics(1)

Maximum pulse width of spikes that

tAF 50(2) 260(3) ns
are suppressed by the analog filter
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
160/226 DS11853 Rev 9

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 81 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 16, with the following configuration:
• Output speed set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 81. SPI dynamic characteristics(1)

Master mode
SPI1,4,5 - - 54(2)
2.7≤VDD≤3.6
Master mode
SPI1,4,5 - - 27
1.71≤VDD≤3.6
Master transmitter mode
SPI1,4,5 - - 54
1.71≤VDD≤3.6
Slave receiver mode
fSCK
SPI clock frequency SPI1,4,5 - - 54 MHz
1/tc(SCK)
1.71≤VDD≤3.6
Slave mode transmitter/full duplex
SPI1,4,5 - - 50(3)
2.7≤VDD≤3.6
Slave mode transmitter/full duplex
SPI1,4,5 - - 37(3)
1.71≤VDD≤3.6
Master & Slave mode
SPI2,3 - - 27
1.71≤VDD≤3.6
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4xTpclk - -
th(NSS) NSS hold time Slave mode, SPI presc = 2 2xTpclk - -
ns
tw(SCKH)
SCK high and low time Master mode Tpclk-1 Tpclk Tpclk+1
tw(SCKL)
DS11853 Rev 9 161/226

196
Table 81. SPI dynamic characteristics(1) (continued)

tsu(MI) Master mode 5 - -

Data input setup time
tsu(SI) Slave mode 2 - -
th(MI) Master mode 3 - -
Data input hold time
th(SI) Slave mode 1 - -
ta(SO) Data output access time Slave mode 7 9 21
tdis(SO) Data output disable time Slave mode 5 7 12
ns
Slave mode 2.7≤VDD≤3.6V - 6.5 10
tv(SO)
Data output valid time Slave mode 1.71≤VDD≤3.6V - 6.5 13.5
tv(MO) Master mode - 2 3
Slave mode
th(SO) 4.5 - -
Data output hold time 1.71≤VDD≤3.6V
th(MO) Master mode 0 - -
2. Excepting SPI1 with SCK IO=PA5. In this configuration, the maximum achievable frequency is 40 MHz.
3. Maximum frequency of the slave transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK
level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having
Tsu(MI) = 0 while signal Duty(SCK) = 50%.
Figure 53. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
162/226 DS11853 Rev 9

Figure 54. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V1
Figure 55. SPI timing diagram - master mode
High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(MO) th(MO)
ai14136c
DS11853 Rev 9 163/226

196
I2S interface characteristics

Unless otherwise specified, the parameters given in Table 82 for the I2S interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
• Output speed is set to OSPEEDRy[1:0] = 10
function characteristics (CK, SD, WS).
Table 82. I2S dynamic characteristics(1)

fMCK I2S Main clock output - 256 x 8K 256xFs(2) MHz

Master data: 32 bits - 64xFs
fCK I2S clock frequency MHz
Slave data: 32 bits - 64xFs
DCK I2S clock frequency duty cycle Slave receiver 30 70 %
tv(WS) WS valid time Master mode - 3
th(WS) WS hold time Master mode 0 -
tsu(WS) WS setup time Slave mode 5 -
th(WS) WS hold time Slave mode 2 -
tsu(SD_MR) Master receiver 2.5 -
tsu(SD_SR) Slave receiver 2.5 -
ns
th(SD_MR) Master receiver 3.5 -
th(SD_SR) Slave receiver 2 -
tv(SD_ST) Slave transmitter (after enable edge) - 12
Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 3
th(SD_ST) Slave transmitter (after enable edge) 5 -
Data output hold time
th(SD_MT) Master transmitter (after enable edge) 0 -
2. 256xFs maximum is 49.152 MHz (APB1 Maximum frequency).
Note: Refer to RM0431 reference manual I2S section for more details on the sampling
frequency (FS).
fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these
parameters might be slightly impacted by the source clock precision. DCK depends mainly
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS
maximum value is supported for each mode/condition.
164/226 DS11853 Rev 9

Figure 56. I2S slave timing diagram (Philips protocol)(1)
tc(CK)
CPOL = 0
CK Input
CPOL = 1
tw(CKH) tw(CKL) th(WS)
WS input
tsu(WS) tv(SD_ST) th(SD_ST)

SDtransmit
LSB transmit(1) MSB transmit Bitn transmit LSB transmit
tsu(SD_SR) th(SD_SR)
SDreceive LSB receive(1) MSB receive Bitn receive LSB receive
MS46528V1
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 57. I2S master timing diagram (Philips protocol)(1)
tf(CK) tr(CK)
tc(CK)
CK output
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS) tw(CKL) th(WS)
WS output
tv(SD_MT) th(SD_MT)
SDtransmit LSB transmit(1) MSB transmit Bitn transmit LSB transmit
tsu(SD_MR) th(SD_MR)
SDreceive LSB receive(1) MSB receive Bitn receive LSB receive
MS46529V1
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
DS11853 Rev 9 165/226

196
SAI characteristics
Unless otherwise specified, the parameters given in Table 83 for SAI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 16, with the following configuration:
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5VDD
function characteristics (SCK,SD,WS).
Table 83. SAI characteristics(1)

fMCKL SAI main clock output - 256x8K 256xFs

Master data: 32 bits - 128xFs(3) MHz
FCK SAI clock frequency(2)
Slave data: 32 bits - 128xFs(3)
Master mode
- 18
2.7≤VDD≤3.6V
tv(FS) FS valid time
Master mode
- 20
1.71≤VDD≤3.6V
tsu(FS) FS setup time Slave mode 1 -
Master mode 7 -
th(FS) FS hold time
Slave mode 0.5 -
tsu(SD_A_MR) Master receiver 1 -
tsu(SD_B_SR) Slave receiver 2.5 -
th(SD_A_MR) Master receiver 3.5 -
Data input hold time ns
th(SD_B_SR) Slave receiver 0.5 -
Slave transmitter (after enable edge)
- 11
2.7≤VDD≤3.6V
tv(SD_B_MT) Data output valid time
Slave transmitter (after enable edge)
- 18
1.71≤VDD≤3.6V
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 5 -
Master transmitter (after enable edge)
- 16
2.7≤VDD≤3.6V
tv(SD_A_MT) Data output valid time
Master transmitter (after enable edge)
- 18.5
1.71≤VDD≤3.6V
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 7.5 -
2. APB clock frequency must be at least twice SAI clock frequency.
3. With Fs = 192 kHz.
166/226 DS11853 Rev 9

Figure 58. SAI master timing waveforms

1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X
(output) tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_MR) th(SD_MR)
SAI_SD_X Slot n
(receive)
MS32771V1
Figure 59. SAI slave timing waveforms

1/fSCK
SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X
(input) tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X
Slot n Slot n+2
(transmit)
tsu(SD_SR) th(SD_SR)
SAI_SD_X Slot n
(receive)
MS32772V1
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196
USB OTG full speed (FS) characteristics

This interface is present in both the USB OTG HS and USB OTG FS controllers.
Table 84. USB OTG full speed startup time

Symbol Parameter Max Unit
tSTARTUP(1) USB OTG full speed transceiver startup time 1 µs

Table 85. USB OTG full speed DC electrical characteristics

Min. Max.(
Symbol Parameter Conditions (1) Typ. 1) Unit
USB OTG full speed

VDDUSB transceiver operating - 3.0(2) - 3.6 V
voltage
I(USB_FS_DP/DM,
Input VDI(3) Differential input sensitivity 0.2 - -
USB_HS_DP/DM)
levels
Differential common mode
VCM(3) Includes VDI range 0.8 - 2.5 V
range
Single ended receiver
VSE(3) - 1.3 - 2.0
threshold
Output VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3
V
levels VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
PA11, PA12
VIN = VDD 14.25 - 24.8
(USB_FS_DP/DM)
RPD PA9, PB13
(OTG_FS_VBUS, VIN = VDD 2.4 5.2 8
OTG_HS_VBUS) kΩ
PA12 (USB_FS_DP) VIN = VSS, during idle 0.9 1.25 1.575
RPU PA9, PB13

(OTG_FS_VBUS, VIN = VSS, during reception 0.55 0.95 1.35
OTG_HS_VBUS)
1. All the voltages are measured from the local ground potential.
2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed
electrical characteristics which are degraded in the 2.7-to-3.0 V VDDUSB voltage range.
4. RL is the load connected on the USB OTG full speed drivers.
Note: When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state
(floating input), not as alternate function. A typical 200 µA current consumption of the
sensing block (current to voltage conversion to determine the different sessions) can be
observed on PA9 and PB13 when the feature is enabled.
168/226 DS11853 Rev 9

Figure 60. USB OTG full speed timings: definition of data signal rise and fall time
Cross over
points
Differential
data lines
VCRS
VSS
tf tr
ai14137b
Table 86. USB OTG full speed electrical characteristics(1)

Driver characteristics
tr Rise time(2) CL = 50 pF 4 20 ns
tf Fall time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf 90 111 %
VCRS Output signal crossover voltage - 1.3 2.0 V
Driving high or
ZDRV Output driver impedance(3) 28 44 Ω
low
2. Measured from 10% to 90% of the data signal. For more detailed informations, refer to USB Specification -
Chapter 7 (version 2.0).
3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching
impedance is included in the embedded driver.
USB high speed (HS) characteristics (through ULPI in STM32F722xx devices)

Unless otherwise specified, the parameters given in Table 89 for ULPI are derived from
tests performed under the ambient temperature, fHCLK frequency summarized in Table 88
and VDD supply voltage conditions summarized in Table 87, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified
• Capacitive load C = 20 pF, unless otherwise specified
• Measurement points are done at CMOS levels: 0.5VDD.
Refer to Section 6.3.20: I/O port characteristics for more details on the input/output
characteristics.
Table 87. USB HS DC electrical characteristics

Symbol Parameter Min.(1) Max.(1) Unit
Input level VDD USB OTG HS operating voltage 1.7 3.6 V

1. All the voltages are measured from the local ground potential.
DS11853 Rev 9 169/226

196
Table 88. USB HS clock timing parameters(1)

fHCLK value to guarantee proper operation of

- 30 - - MHz
USB HS interface
FSTART_8BIT Frequency (first transition) 8-bit ±10% 54 60 66 MHz
FSTEADY Frequency (steady state) ±500 ppm 59.97 60 60.03 MHz
DSTART_8BIT Duty cycle (first transition) 8-bit ±10% 40 50 60 %
DSTEADY Duty cycle (steady state) ±500 ppm 49.975 50 50.025 %
Time to reach the steady state frequency and
tSTEADY - - 1.4 ms
duty cycle after the first transition
tSTART_DEV Clock startup time after the Peripheral - - 5.6
ms
tSTART_HOST de-assertion of SuspendM Host - - -
PHY preparation time after the first transition
tPREP - - - µs
of the input clock
Figure 61. ULPI timing diagram
Clock
tSC tHC
Control In
(ULPI_DIR,
ULPI_NXT) tSD tHD
data In
(8-bit)
tDC tDC
Control out
(ULPI_STP)
tDD
data out
(8-bit)
ai17361c
170/226 DS11853 Rev 9

Table 89. Dynamic characteristics: USB ULPI(1)

Symbol Parameter Conditions Min. Typ. Max. Unit
tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 1.5 - -

tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 1 - -
tSD Data in setup time - 1.5 - -
tHD Data in hold time - 1 - -
2.7 V < VDD < 3.6 V,
ns
CL = 20 pF and - 6 7.5
OSPEEDRy[1:0] = 11
tDC/tDD Data/control output delay - -
1.7 V < VDD < 3.6 V, 9.5 11
CL = 15 pF and -
OSPEEDRy[1:0] = 11
USB high speed (HS) characteristics (embedded PHY High speed on

STM32F723xx devices)
Table 90. USB OTG high speed DC electrical characteristics

Vhssq High speed squelch detection threshold - 100 - 150 mV

Vhsdsc High speed disconnect detection threshold - 525 - 625 mV
Vhsdif High speed differential detection threshold - 100 - - mV
Vhscm High speed data signaling common mode voltage range - -50 - 500 mV
Vhsoi High speed idle level - -10 - 10 mV
Vhsoh High speed data signaling high - 360 - 440 mV
Vhsol High speed data signaling low - -10 - 10 mV
Vchirpj Chirp J level - 700 - 1100 mV
Vchirpk Chirp K level - -900 - -500 mV
Table 91. USB OTG high speed electrical characteristics

Parameter Comments Conditions Min Typ Max Unit
tlr Rise time - 0.5 - - ns

tlf Fall time - 0.5 - - ns
Setup time from INHSDRIVERENABLE=1 to the
tlrfm - 10 - - ns
transition on INHSDATAP/INHSDATAN
Zdrv Driver output impedance - 40.5 - 49.5 Ω
DS11853 Rev 9 171/226

196
Table 92. USB FS PHY BCD electrical characteristics

Primary detection mode consumption - - - 300

IDDUSB µA
Secondary detection mode consumption - - - 300
RDAT_LKG Data line leakage resistance - 300 - - kΩ
VDAT_LKG Data line leakage voltage - 0.0 - 3.6 V
RDCP_DAT Dedicated charging port resistance across D+/D- - - - 200 Ω
VLGC_HI Logic high - 2.0 - 3.6
VLGC_LOW Logic low - - - 0.8
VLGC Logic threshold - 0.8 - 2.0
V
VDAT_REF Data detect voltage - 0.25 - 3.6
VDP_SRC D+ source voltage - 0.5 - 3.6
VDM_SRC D- source voltage - 0.5 - 3.6
IDM_SINK D- sink current - 25 - 175
IDP_SINK D+ sink current - 25 - 175 µA
IDP_SRC Data contact detect current source - 7 - 30
CAN (controller area network) interface

function characteristics (CANx_TX and CANx_RX).
6.3.30 FMC characteristics

Unless otherwise specified, the parameters given in Table 93 to Table 106 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 16, with the following configuration:
characteristics.
Asynchronous waveforms and timings

Figure 62 through Figure 65 represent asynchronous waveforms and Table 93 through
Table 100 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all timing tables, the THCLK is the HCLK clock period
172/226 DS11853 Rev 9

Figure 62. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE) t w(NOE) t h(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE) t h(A_NOE)
FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE) th(Data_NOE)
t su(Data_NE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32753V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
DS11853 Rev 9 173/226

196
Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

tw(NE) FMC_NE low time 2Thclk -1 2Thclk +1

tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 0.5
tw(NOE) FMC_NOE low time 2Thclk -1 2Thclk +1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
th(A_NOE) Address hold time after FMC_NOE high 0 -
tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5
ns
th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time Thclk -1.5 -
tsu(Data_NOE) Data to FMC_NOEx high setup time Thclk -1.5 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Thclk -0.5
1. CL = 30 pF.
Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT

timings(1)
tw(NE) FMC_NE low time 7Thclk +1 7Thclk +1
tw(NOE) FMC_NWE low time 5Thclk -1 5Thclk +1

ns
tw(NWAIT) FMC_NWAIT low time Thclk -0.5 -
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Thclk +1.5 -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Thclk +1 -
174/226 DS11853 Rev 9

Figure 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)
FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32754V1
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 95. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

tw(NE) FMC_NE low time 3Thclk +1 3Thclk +1

tv(NWE_NE) FMC_NEx low to FMC_NWE low Thclk - 0.5 Thclk +0.5
tw(NWE) FMC_NWE low time Thclk - 1.5 Thclk +0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Thclk -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
th(A_NWE) Address hold time after FMC_NWE high Thclk - 0.5 -
ns
th(BL_NWE) FMC_BL hold time after FMC_NWE high Thclk - 0.5 -
tv(Data_NE) Data to FMC_NEx low to Data valid - Thclk +1.5
th(Data_NWE) Data hold time after FMC_NWE high Thclk +0.5 -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0
tw(NADV) FMC_NADV low time - Thclk - 0.5
DS11853 Rev 9 175/226

196
Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT

timings(1)
tw(NWE) FMC_NWE low time 6Thclk -1.5 6Thclk +0.5

ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6Thclk -1 -
FMC_NEx hold time after FMC_NWAIT
th(NE_NWAIT) 4Thclk + 2 -
invalid
Figure 64. Asynchronous multiplexed PSRAM/NOR read waveforms

tw(NE)
FMC_ NE
tv(NOE_NE) t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
tv(A_NE) th(A_NOE)
FMC_ A[25:16] Address

tv(BL_NE) th(BL_NOE)
FMC_ NBL[1:0] NBL

th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)
FMC_ AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32755V1
176/226 DS11853 Rev 9

Table 97. Asynchronous multiplexed PSRAM/NOR read timings(1)


tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Thclk 2Thclk +0.5
ttw(NOE) FMC_NOE low time Thclk -1 Thclk +1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time 0 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Thclk -0.5 Thclk +1
FMC_AD(address) valid hold time after
th(AD_NADV) Thclk +0.5 - ns
FMC_NADV high)
th(A_NOE) Address hold time after FMC_NOE high Thclk -0.5 -
th(BL_NOE) FMC_BL time after FMC_NOE high 0 -
tsu(Data_NE) Data to FMC_NEx high setup time Thclk -1.5 -
tsu(Data_NOE) Data to FMC_NOE high setup time Thclk -1.5 -
th(Data_NE) Data hold time after FMC_NEx high 0 -
th(Data_NOE) Data hold time after FMC_NOE high 0 -
Table 98. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

tw(NOE) FMC_NWE low time 5Thclk -1.5 8Thclk +0.5 ns

tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Thclk +1.5 -
th(NE_NWAIT) 4Thclk +1 -
invalid
DS11853 Rev 9 177/226

196
Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms
tw(NE)
FMC_ NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_ A[25:16] Address

tv(BL_NE) th(BL_NWE)
FMC_ NBL[1:0] NBL

t v(A_NE) t v(Data_NADV) th(Data_NWE)
FMC_ AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
MS32756V1
Table 99. Asynchronous multiplexed PSRAM/NOR write timings(1)


tv(NWE_NE) FMC_NEx low to FMC_NWE low Thclk -0.5 Thclk +0.5
tw(NWE) FMC_NWE low time 2Thclk -0.5 2Thclk +0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Thclk -0.5 -
tv(A_NE) FMC_NEx low to FMC_A valid - 0
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 0.5
tw(NADV) FMC_NADV low time Thclk Thclk +1
ns
FMC_AD(adress) valid hold time after
th(AD_NADV) Thclk +0.5 -
FMC_NADV high)
th(A_NWE) Address hold time after FMC_NWE high Thclk +0.5 -
th(BL_NWE) FMC_BL hold time after FMC_NWE high Thclk -0.5 -
tv(Data_NADV) FMC_NADV high to Data valid - Thclk +1.5
th(Data_NWE) Data hold time after FMC_NWE high Thclk +0.5 -
178/226 DS11853 Rev 9

Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)

tw(NE) FMC_NE low time 9Thclk - 1 9Thclk + 1
tw(NWE) FMC_NWE low time 7Thclk -0.5 7Thclk + 0.5 ns

tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6Thclk + 2 -
th(NE_NWAIT) 4Thclk - 1 -
invalid
Synchronous waveforms and timings

Figure 66 through Figure 69 represent synchronous waveforms and Table 101 through
Table 104 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable;
• MemoryType = FMC_MemoryType_CRAM;
• WriteBurst = FMC_WriteBurst_Enable;
• CLKDivision = 1;
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
• CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
– For 2.7 V≤VDD≤3.6 V, maximum FMC_CLK = 108 MHz at CL=20 pF or 90 MHz at
CL=30 pF (on FMC_CLK).
– For 1.71 V≤VDD<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK).
DS11853 Rev 9 179/226

196
Figure 66. Synchronous multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
t d(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
MS32757V1
180/226 DS11853 Rev 9

Table 101. Synchronous multiplexed NOR/PSRAM read timings(1)

tw(CLK) FMC_CLK period 2Thclk - 0.5 -

td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Thclk + 0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 -
td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25) - 3
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Thclk -
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2
ns
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Thclk - 0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
FMC_A/D[15:0] valid data before FMC_CLK
tsu(ADV-CLKH) 1.5 -
high
th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 3 -
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 -
DS11853 Rev 9 181/226

196
Figure 67. Synchronous multiplexed PSRAM write timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
FMC_A[25:16]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
td(CLKH-NBLH)
FMC_NBL
MS32758V1
182/226 DS11853 Rev 9

Table 102. Synchronous multiplexed PSRAM write timings(1)


td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Thclk +0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
ns
t(CLKH-NWEH) FMC_CLK high to FMC_NWE high Thclk +0.5 -
td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3
td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 -
td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Thclk +0.5 -
DS11853 Rev 9 183/226

196
Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
MS32759V1
Table 103. Synchronous non-multiplexed NOR/PSRAM read timings(1)


t(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 2
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Thclk +0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5
td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25) Thclk - ns
td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 2
td(CLKH-NOEH) FMC_CLK high to FMC_NOE high Thclk -0.5 -
tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high 1.5 -
th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 3 -
t(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 -
184/226 DS11853 Rev 9

Figure 69. Synchronous non-multiplexed PSRAM write timings
tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:0]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-Data) td(CLKL-Data)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
MS32760V1
DS11853 Rev 9 185/226

196
Table 104. Synchronous non-multiplexed PSRAM write timings(1)

t(CLK) FMC_CLK period 2Thclk - 0.5 -

t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) Thclk +0.5 -
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5
ns
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 1.5
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high Thclk +1 -
td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3
td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Thclk +1 -
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3.5 -
NAND controller waveforms and timings

Figure 70 through Figure 73 represent synchronous waveforms, and Table 105 and
Table 106 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
186/226 DS11853 Rev 9

Figure 70. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
td(ALE-NOE) th(NOE-ALE)
FMC_NOE (NRE)
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MS32767V1
Figure 71. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) th(NWE-ALE)
FMC_NWE
FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32768V1
Figure 72. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
MS32769V1
DS11853 Rev 9 187/226

196
Figure 73. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)
FMC_NWE
FMC_N OE
td(D-NWE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
MS32770V1
Table 105. Switching characteristics for NAND Flash read cycles(1)

tw(N0E) FMC_NOE low width 4Thclk -0.5 4Thclk +0.5

tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 11 -
th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - ns
td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Thclk +1.5
th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Thclk - 2 -
Table 106. Switching characteristics for NAND Flash write cycles(1)

tw(NWE) FMC_NWE low width 4Thclk -0.5 4Thclk +0.5

tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid 0 -
th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2Thclk - 1 -
ns
td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5Thclk - 1 -
td(ALE-NWE) FMC_ALE valid before FMC_NWE low - 3Thclk +1.5
th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2Thclk - 2 -
188/226 DS11853 Rev 9

SDRAM waveforms and timings

• CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise
specified.
– For 3.0 V≤VDD≤3.6 V, maximum FMC_SDCLK= 100 MHz at CL=20 pF
(on FMC_SDCLK).
– For 2.7 V≤VDD≤3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF
(on FMC_SDCLK).
– For 1.71 V≤VDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF
(on FMC_SDCLK).
Figure 74. SDRAM read access waveforms (CL = 1)
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
FMC_A[12:0] Row n Col1 Col2 Coli Coln
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)
FMC_D[31:0] Data1 Data2 Datai Datan
MS32751V2
DS11853 Rev 9 189/226

196
Table 107. SDRAM read timings(1)

tw(SDCLK) FMC_SDCLK period 2Thclk -0.5 2Thclk +0.5

tsu(SDCLKH _Data) Data input setup time 2.5 -
th(SDCLKH_Data) Data input hold time 1 -
td(SDCLKL_Add) Address valid time - 1.5
td(SDCLKL- SDNE) Chip select valid time - 1.5
ns
th(SDCLKL_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
Table 108. LPSDR SDRAM read timings(1)

tW(SDCLK) FMC_SDCLK period 2Thclk -0.5 2Thclk +0.5

tsu(SDCLKH_Data) Data input setup time 1 -
th(SDCLKH_Data) Data input hold time 3.5 -

td(SDCLKL_SDNE) Chip select valid time - 1.5
ns
th(SDCLKL_SDNE) Chip select hold time 0 -
td(SDCLKL_SDNRAS SDNRAS valid time - 0.5
th(SDCLKL_SDNRAS) SDNRAS hold time 0 -
th(SDCLKL_SDNCAS) SDNCAS hold time 0 -
190/226 DS11853 Rev 9

Figure 75. SDRAM write access waveforms
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
FMC_A[12:0] Row n Col1 Col2 Coli Coln
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_SDNWE
td(SDCLKL_Data)
FMC_D[31:0] Data1 Data2 Datai Datan
td(SDCLKL_NBL) th(SDCLKL_Data)
FMC_NBL[3:0]
MS32752V2
Table 109. SDRAM write timings(1)


td(SDCLKL _Data) Data output valid time - 1.5
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL_SDNWE) SDNWE valid time - 1.5
th(SDCLKL_SDNWE) SDNWE hold time 0.5 -
ns
td(SDCLKL_ SDNE) Chip select valid time - 1.5
th(SDCLKL-_SDNE) Chip select hold time 0.5 -
td(SDCLKL_SDNRAS) SDNRAS valid time - 1
th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 -
td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 -
DS11853 Rev 9 191/226

196
Table 110. LPSDR SDRAM write timings(1)


td(SDCLKL _Data) Data output valid time - 2
th(SDCLKL _Data) Data output hold time 0 -
td(SDCLKL-SDNWE) SDNWE valid time - 1.5
th(SDCLKL-SDNWE) SDNWE hold time 0 -
ns
td(SDCLKL- SDNE) Chip select valid time - 0.5
th(SDCLKL- SDNE) Chip select hold time 0. -
td(SDCLKL-SDNRAS) SDNRAS valid time - 2
th(SDCLKL-SDNRAS) SDNRAS hold time 0 -
td(SDCLKL-SDNCAS) SDNCAS valid time - 2
td(SDCLKL-SDNCAS) SDNCAS hold time 0 -
6.3.31 Quad-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 111 and Table 112 for Quad-SPI
are derived from tests performed under the ambient temperature, fAHB frequency and VDD
supply voltage conditions summarized in Table 16: General operating conditions, with the
following configuration:
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
function characteristics.
Table 111. Quad-SPI characteristics in SDR mode(1)

2.7 V≤VDD<3.6 V
- - 108
Quad-SPI clock CL=20 pF
Fck1/t(CK) MHz
frequency 1.71 V<VDD<3.6 V
- - 100
CL=15 pF
192/226 DS11853 Rev 9

Table 111. Quad-SPI characteristics (continued)in SDR mode(1) (continued)

tw(CKH) Quad-SPI clock high t(CK)/2 - 0.5 - t(CK)/2 + 0.5

-
tw(CKL) and low time t(CK)/2 - 0.5 - t(CK)/2 + 0.5
2.7 V<VDD<3.6 V 2 - -
ts(IN) Data input setup time
1.71 V<VDD<3.6 V 2 - -
2.7 V<VDD<3.6 V 1 - - ns
th(IN) Data input hold time
1.71 V<VDD<3.6 V 2 - -
2.7 V<VDD<3.6 V - 1.5 2.5
tv(OUT) Data output valid time
1.71 V<VDD<3.6 V - 1.5 3
th(OUT) Data output hold time - 0.5 - -
Table 112. Quad-SPI characteristics in DDR mode(1)

2.7 V<VDD<3.6 V
- - 80
CL=20 pF
1.8 V<VDD<3.6 V
Fck1/t(CK) Quad-SPI clock frequency - - 80 MHz
CL=15 pF
1.71 V<VDD<3.6 V
- - 80
CL=10 pF
t(CK)/2 - t(CK)/2 +
tw(CKH) -
Quad-SPI clock high and 0.5 0.5
-
low time t(CK)/2 - t(CK)/2 +
tw(CKL) -
0.5 0.5
ts(IN), 2.7 V<VDD<3.6 V 2 - -

tsf(IN) 1.71 V<VDD<2 V 1.5 - -
thr(IN), 2.7 V<VDD<3.6 V 1.25 - -

thf(IN) 1.71 V<VDD<2 V 1.75 - -
ns
2.7 V<VDD<3.6 V - 9.5 11.5
1.71 V<VDD<3.6 V
tvr(OUT), - 9.5 12.25
Data output valid time DHHC=0
tvf(OUT)
DHHC=1 Thclk/2 Thclk/2
-
Pres=1, 2... +2 +2.5
DHHC=0 5.5 - -
thr(OUT),
Data output hold time DHHC=1 Thclk/2
thf(OUT) - -
Pres=1, 2... +0.75
DS11853 Rev 9 193/226

196
Figure 76. Quad-SPI timing diagram - SDR mode
tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
MSv36878V1
Figure 77. Quad-SPI timing diagram - DDR mode

tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK)
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output D0 D1 D2 D3 D4 D5
tsf(IN) thf(IN) tsr(IN) thr(IN)
Data input D0 D1 D2 D3 D4 D5
MSv36879V1
6.3.32 SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 113 for the SDIO/MMC interface
are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD
characteristics.
194/226 DS11853 Rev 9

Figure 78. SDIO high-speed mode
Figure 79. SD default mode
CK
tOVD tOHD
D, CMD
(output)
ai14888
Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp =50 MHz 9 10 -
ns
tW(CKH) Clock high time fpp =50 MHz 9 10 -
CMD, D inputs (referenced to CK) in MMC and SD HS mode
tISU Input setup time HS fpp =50 MHz 2 - -

ns
tIH Input hold time HS fpp =50 MHz 2 - -
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV Output valid time HS fpp =50 MHz - 11 12

ns
tOH Output hold time HS fpp =50 MHz 9 - -
DS11853 Rev 9 195/226

196
Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1) (continued)

CMD, D inputs (referenced to CK) in SD default mode
tISUD Input setup time SD fpp =25 MHz 2 - -

ns
tIHD Input hold time SD fpp =25 MHz 2 - -
CMD, D outputs (referenced to CK) in SD default mode
tOVD Output valid default time SD fpp =25 MHz - 2 2.5

ns
tOHD Output hold default time SD fpp =25 MHz 0.5 - -
1. Guaranteed by characterization results,.
Table 114. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V(1)(2)

fPP Clock frequency in data transfer mode - 0 - 50 MHz

- SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 -
tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 -
ns
tW(CKH) Clock high time fpp =50 MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in eMMC mode
tISU Input setup time HS fpp =50 MHz 1 - -

ns
tIH Input hold time HS fpp =50 MHz 3.5 - -
CMD, D outputs (referenced to CK) in eMMC mode
tOV Output valid time HS fpp =50 MHz - 12 14

ns
tOH Output hold time HS fpp =50 MHz 10.5 - -
2. Cload = 20 pF.
196/226 DS11853 Rev 9

STM32F722xx STM32F723xx Package information
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
7.1 LQFP64 – 10 x 10 mm, low-profile quad flat package

information
LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
Figure 80. LQFP64 outline
SEATING PLANE
C
A2
A
0.25 mm
GAUGE PLANE
A1
c
ccc C
D A1 K
D1 L
D3 L1
48 33
32
49
b
E1
E3
64 17
PIN 1 1 16
IDENTIFICATION e
5W_ME_V3
1. Drawing is not to scale.
Table 115. LQFP64 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.60 - - 0.0630
A1 0.05 - 0.15 0.0020 - 0.0059
A2 1.350 1.40 1.45 0.0531 0.0551 0.0571
DS11853 Rev 9 197/226

220
Package information STM32F722xx STM32F723xx
Table 115. LQFP64 mechanical data (continued)

Symbol
b 0.17 0.22 0.27 0.0067 0.0087 0.0106

c 0.09 - 0.20 0.0035 - 0.0079
D - 12.00 - - 0.4724 -
D1 - 10.00 - - 0.3937 -
D3 - 7.50 - - 0.2953 -
E - 12.00 - - 0.4724 -
E1 - 10.00 - - 0.3937 -
E3 - 7.50 - - 0.2953 -
e - 0.50 - - 0.0197 -
K 0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 - 1.00 - - 0.0394 -
ccc - - 0.08 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 81. LQFP64 recommended footprint
48 33
0.3
49 0.5 32
12.7
10.3
10.3
64 17
1.2
1 16
7.8
12.7
ai14909c
1. Dimensions are in millimeters.
198/226 DS11853 Rev 9

LQFP64 device marking

The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 82. LQFP64 top view example
Product identification(1) Revision code
R
STM32F722
RET6
Date code
Y WW
Pin 1
indentifier
MSv42090V1
1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DS11853 Rev 9 199/226

220
7.2 LQFP100, 14 x 14 mm low-profile quad flat package

information
SEATING PLANE
C
0.25 mm
A2
A
A1
c
GAUGE PLANE
ccc C
A1
K
L
D1
L1
D3
75 51
76 50
b
E1
E3
100 26
PIN 1 1 25
IDENTIFICATION
e 1L_ME_V5
Table 116. LQPF100 mechanical data

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
200/226 DS11853 Rev 9

Table 116. LQPF100 mechanical data (continued)

Symbol
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
75 51
76 50
0.5
0.3
16.7 14.3
100 26
1.2
1 25
12.3
16.7
ai14906c
1. Dimensions are expressed in millimeters.
DS11853 Rev 9 201/226

220

location.
Product identification (1)
STM32F722 Revision code
VET6 R
Date code
Y WW
Pin 1 identifier
MS42091V1
202/226 DS11853 Rev 9

7.3 LQFP144, 20 x 20 mm low-profile quad flat package

information

SEATING
PLANE
C
A1
A2
A
c
0.25 mm
ccc C GAUGE PLANE
A1
D
L
K
D1
L1
D3
108 73
109
72
b
E1
E3
37
144
PIN 1 1 36
IDENTIFICATION
e
1A_ME_V3
Table 117. LQFP144 mechanical data

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.874
DS11853 Rev 9 203/226

220
Table 117. LQFP144 mechanical data (continued)

Symbol
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953

D3 - 17.500 - - 0.689 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1.35
108 73
109 0.35 72
0.5
19.9 17.85
22.6
144 37
1 36
19.9
22.6
ai14905e
204/226 DS11853 Rev 9

LQP144 device marking

location.
Revision code
Product identification(1) R
STM32F722ZET6
Y WW
Pin 1 Date code
identifier
MS42092V1
DS11853 Rev 9 205/226

220
7.4 LQFP176 24 x 24 mm low-profile quad flat package

information
This LQFP is a 176-pin, 24 x 24 mm, 0.5 mm pitch, low profile quad flat package.
Figure 89. LQFP176 - Outline

Package LQFP176 (package code 1T)
ș2 ș1
R1
H R2
B(See SECTION B-B)

GAUGE PLANE
0.25
D1/4
S
B ș
L
E1/4 ș
4x N/4 TIPS 4x (L1)
bbb H A-B D
aaa C A-B D
BOTTOM VIEW SECTION A-A
A2 0.05
(N-4) x e
C
A
A1 ddd C A-BD ccc C
b
SIDE VIEW
D
D1
D
N
b WITH PLATING
E1/4
c c1
D1/4
A B
E1 E b1 BASE METAL
SECTION A-A
A A
SECTION B-B
TOP VIEW 1T_LQFP176_ME_V1

2. Dimensioning and tolerance schemes conform to ASME Y14.5M-1994.
3. Datums A-B and D to be determined at datum plane H.
4. Detail of pin 1 identifier are optional but must be located within the zone indicated.
5. Exact shape of each corner is optional.
Table 118. LQFP176 - Mechanical data

Symbol
A - - 1.600 - - 0.0630
(2)
A1 0.050 - 0.150 0.0020 - 0.0059
206/226 DS11853 Rev 9

Table 118. LQFP176 - Mechanical data (continued)

Symbol
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
(3)(4)
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
(4)
b1 0.170 0.200 0.230 0.0067 0.0079 0.0091
c(4) 0.090 - 0.200 0.0035 - 0.0079
(4)
c1 0.090 - 0.160 0.0035 - 0.063
(5)
D 26.000 1.0236
(6)(7)
D1 24.000 0.9449
E(5) 26.000 0.0197
(6)(7)
E1 24.000 0.9449
e 0.500 0.1970
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1(4) 1 0.0394 REF
N(8) 176
θ 0° 3.5° 7° 0° 3.5° 7°
θ1 0° - - 0° - -
θ2 10° 12° 14° 10° 12° 14°
θ3 10° 12° 14° 10° 12° 14°
R1 0.080 - - 0.0031 - -
R2 0.080 - 0.200 0.0031 - 0.0079
S 0.200 - - 0.0079 - -
(9)
aaa 0.200 0.0079
(9)
bbb 0.200 0.0079
(9)
ccc 0.080 0.0031
ddd(9) 0.080 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. A1 is defined as the distance from the seating plane to the lowest point on the package body.
3. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead
width to exceed the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the
lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm
and 0.5 mm pitch packages.
4. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
5. To be determined at seating datum plane C.
6. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is
“0.25 mm” per side. D1 and E1 are Maximum plastic body size dimensions including mold mismatch.
8. “N” is the max number of terminal positions for the specified body size.
9. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994.
DS11853 Rev 9 207/226

220
Figure 90. LQFP176 - Recommended footprint
1.2
176 133
1 0.5 132
0.3
26.7
21.8
44 89
45 88
1.2
21.8
26.7
1T_FP_V1

208/226 DS11853 Rev 9


location.
Product identification(1)
STM32F722IET6
Revision code
Y WW Date code
R
Pin 1
identifier
MS44207V1
DS11853 Rev 9 209/226

220
7.5 UFBGA144 package information

UFBGA144 is a 144-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package.
Figure 92. UFBGA144 outline

Z Seating plane
ddd Z
A4 A3 A2 A1 A
E1 A1 ball A1 ball X
identifier index area E
e F
A
F
D1 D
e
Y
M
12 1
BOTTOM VIEW Øb (144 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z A0AS_ME_V2
Table 119. UFBGA144 mechanical data

Symbol
Min. Typ. Max. Min. Typ. Max.
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 - 0.130 - - 0.0051 -
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.230 0.280 0.320 0.0091 0.0110 0.0126
D 6.950 7.000 7.050 0.2736 0.2756 0.2776
D1 5.450 5.500 5.550 0.2146 0.2165 0.2185
E 6.950 7.000 7.050 0.2736 0.2756 0.2776
E1 5.450 5.500 5.550 0.2146 0.2165 0.2185
e - 0.500 - - 0.0197 -
F 0.700 0.750 0.800 0.0276 0.0295 0.0315
210/226 DS11853 Rev 9

Table 119. UFBGA144 mechanical data (continued)

Symbol
ddd - - 0.100 - - 0.0039

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
Figure 93. UFBGA144 recommended footprint
Dpad
Dsm
A0AS_FP_V1
Table 120. UFBGA144 recommended PCB design rules (0.50 mm pitch BGA)
Dimension Recommended values
Pitch 0.50 mm
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm
DS11853 Rev 9 211/226

220
UFBGA144 device marking

The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 94. UFBGA144 top view example
Product
(1)
STM32F
identification
723ZEI6
Date code
Standard ST logo Y WW
Revision code
Ball 1 identifier
R
MS44251V1
212/226 DS11853 Rev 9

7.6 UFBGA176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid

array package information
This UFBGA is a 176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array
package
Figure 95. UFBGA(176+25) - Outline

Seating plane
C A4
ddd C
A
A2 A3 b A1
A1 ball A
A1 ball index E
identifier area
E1
e F
A
F
D1 D
e
B
R
15 1
Øb (176 + 25 balls)
BOTTOM VIEW TOP VIEW
Ø eee M C A B
Ø fff M C
A0E7_ME_V10
Table 121. UFBGA(176+25) - Mechanical data

Symbol
A - - 0.600 - - 0.0236
A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
b 0.240 0.290 0.340 0.0094 0.0114 0.0134
D 9.850 10.000 10.150 0.3878 0.3937 0.3996
D1 - 9.100 - - 0.3583 -
E 9.850 10.000 10.150 0.3878 0.3937 0.3996
E1 - 9.100 - - 0.3583 -
e - 0.650 - - 0.0256 -
F - 0.450 - - 0.0177 -
DS11853 Rev 9 213/226

220
Table 121. UFBGA(176+25) - Mechanical data (continued)

Symbol
ddd - - 0.080 - - 0.0031

eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
Figure 96. UFBGA(176+25) - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 122. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA)
Pitch 0.65 mm
Dpad 0.300 mm
Dsm 0.400 mm typ. (depends on the soldermask registration tolerance)
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
214/226 DS11853 Rev 9

UFBGA176+25 device marking

location.
Figure 97. UFBGA176 top view example
Revision code
(1)
Product identification
R
STM32F722
IEK6
Date code
Ball A1
indentifier Y WW
MS44208V1
DS11853 Rev 9 215/226

220
7.7 WLCSP100 package information

This WLCSP is a 100-ball, 4.341x4.775 mm, 0.4 mm pitch, wafer level chip scale package.
Figure 98. WLCSP100 - Outline
bbb Z
A1
e1 A1 BALL LOCATION
F
G
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
C10 C9 C8 C7 C6 C5 C4 C3 C2 C1
DETAIL A
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
E10 E9 E8 E7 E6 E5 E4 E3 E2 E1
e2 E
F10 F9 F8 F7 F6 F5 F4 F3 F2 F1
G10 G9 G8 G7 G6 G5 G4 G3 G2 G1
e H10 H9 H8 H7 H6 H5 H4 H3 H2 H1
J10 J9 J8 J7 J6 J5 J4 J3 J2 J1
K10 K9 K8 K7 K6 K5 K4 K3 K2 K1
e
A
D
BOTTOM VIEW
A2
A2 SIDE VIEW
BUMP
FRONT VIEW b
A1
eee Z
Z
b (100)
ccc Z X Y
E ddd Z
SEATING PLANE
DETAIL A
ROTATED 90
A1 ORIENTATION
REFERENCE
aaa (4x)
D
TOP VIEW
A084_WLCSP100_ME_V1
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010.
216/226 DS11853 Rev 9

Table 123. WLCSP100 - Mechanical data

Symbol
A 0.525 0.555 0.585 0.0207 0.0219 0.0230

A1 - 0.175 - - 0.0069 -
A2(2) - 0.380 - - 0.0150 -
A3 - 0.025(3) - - 0.0010 -
b 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 4.306 4.341 4.376 0.1695 0.1709 0.1723
E 4.740 4.775 4.810 0.1866 0.1880 0.1894
e - 0.400 - - 0.0157 -
e1 - 3.600 - - 0.1417 -
e2 - 3.600 - - 0.1417 -
F(4) - 0.3705 - - 0.0146 -
G(4) - 0.5875 - - 0.0231 -
N 100
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to the 4rd decimal place.
2. Back side coating.
3. Nominal dimension rounded to the 3rd decimal place results from process capability.
4. Calculated dimensions are rounded to 3rd decimal place.
Figure 99. WLCSP100 - Recommended footprint
Dpad
Dsm
BGA_WLCSP_FT_V1
DS11853 Rev 9 217/226

220
Table 124. WLCSP100 - Recommended PCB design rules

Pitch 0.4 mm
Dpad 0.250 mm
0.290 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil thickness 0.100 mm
218/226 DS11853 Rev 9

WLCSP100 device marking

location.
Figure 100. WLCSP100 top view example

Ball A1 identifier
Product identification(1)
32F723VEY6
Revision code
Y WW R
MSv44209V1
DS11853 Rev 9 219/226

220
7.8 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in ° C,
• ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 125. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

48.5
LQFP64 - 10 × 10 mm / 0.5 mm pitch
47.1
LQFP100 - 14× 14 mm / 0.5 mm pitch
35.85
WLCSP100 - 0.4 mm pitch
ΘJA 45.6 °C/W
LQFP144 - 20 × 20 mm / 0.5 mm pitch
43.9
LQFP176 - 24 × 24 mm / 0.5 mm pitch
42
UFBGA144 - 7 × 7 mm / 0.5 mm pitch
41.2
UFBGA176 - 10× 10 mm / 0.65 mm pitch
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
220/226 DS11853 Rev 9

STM32F722xx STM32F723xx Ordering information
8 Ordering information
Table 126. Ordering information scheme

Example: STM32 F 722 V C T 6 xxx
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
722 = STM32F722xx, no OTG PHY HS
723 = STM32F723xx, with OTG PHY HS
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
I = 176 pins
Flash memory size

C = 256 Kbytes of Flash memory
E = 512 Kbytes of Flash memory
Package
T = LQFP
K = UFBGA (10 x 10 mm)
I = UFBGA (7 x 7 mm)
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (such as speed or package) or for further information on any
aspect of this device, contact the nearest ST sales office.
DS11853 Rev 9 221/226

222
Recommendations when using internal reset OFF STM32F722xx STM32F723xx
Appendix A Recommendations when using internal reset

OFF
When the internal reset is OFF, the following integrated features are no longer supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
• The brownout reset (BOR) circuitry must be disabled.
• The embedded programmable voltage detector (PVD) is disabled.
• VBAT functionality is no more available and VBAT pin should be connected to VDD.
• The over-drive mode is not supported.
A.1 Operating conditions

Table 127. Limitations depending on the operating power supply range
Maximum
Flash
Operating memory Maximum Flash
Possible Flash
power ADC access memory access
I/O operation memory
supply operation frequency frequency with
operations
range with no wait wait states (1)(2)
states
(fFlashmax)
Conversion 180 MHz with 8 8-bit erase and

VDD =1.7 to – No I/O
time up to 20 MHz wait states and program
2.1 V(3) compensation
1.2 Msps over-drive OFF operations only
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states
given here does not impact the execution speed from the Flash memory since the ART accelerator or
L1-cache is used to achieve a performance equivalent to 0-wait state program execution.
3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor
(refer to Section 3.15.1: Internal reset ON).
222/226 DS11853 Rev 9

STM32F722xx STM32F723xx Important security notice
9 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
DS11853 Rev 9 223/226

223
Revision history STM32F722xx STM32F723xx
10 Revision history
Table 128. Document revision history

Date Revision Changes
03-Feb-2017 1 Initial release.

Updated cover with the maximum SPI speed at 54 Mbit/s.
30-Mar-2017 2
Updated Figure 14: STM32F732xx LQFP64 pinout.
Updated Figure 16: STM32F733xx WLCSP100 ballout (with OTG PHY HS).
Updated note 1 below all the package device marking figures.
Updated Section 1: Introduction.
Updated Table 60: I/O current injection susceptibility note by ‘injection is not possible’.
01-Jun-2017 3 Updated Table 67: ADC characteristics RADC min at 1.5 kΩ
Updated Figure 45: Recommended NRST pin protection note about the 0.1uF
capacitor.
Updated Table 78: DAC characteristics RLOAD feature.
Updated Figure 39: ACCHSI versus temperature.
Added Section 1: Introduction.
Removed memory mapping, transferred in the reference manual (RM0431).
10-Apr-2018 4 Updated Table 10: STM32F732xx and STM32F733xx pin and ball definition footnote
5 only for PC14, PC15, PH0, PH1.
Updated Table 125: Package thermal characteristics thermal values for LQFP
packages.
Updated Table 1: Device summary adding STM32F723VC.
Added LQFP100 package for STM32F723xx devices:
– Updated Table 2: STM32F722xx and STM32F723xx features and peripheral
counts.
– Updated Section 2.2: STM32F723xx versus STM32F722xx LQFP100/ LQFP144/
LQFP176 packages.
– Added Figure 3: Compatible board design for LQFP100 package.
23-Mar-2020 5 – Added Figure 17: STM32F723xx LQFP100 pinout.
– Updated Table 10: STM32F722xx and STM32F723xx pin and ball definition
Added VDDPHYS
– Updated Figure 6: STM32F722xx and STM32F723xx block diagram.
– Updated Figure 29: STM32F723xx power supply scheme.
– Updated Table 13: Voltage characteristics
– Updated Table 16: General operating conditions
Updated Section 7: Package information.
Updated Table 53: Flash memory programming maximum programming voltage
04-Apr-2020 6
(Vprog) for 32-bit Flash program operation at 3.6V (instead of 3V).
Updated
– Section 2: Description
05-Nov-2020 7
– Section 2.1: Full compatibility throughout the family
– Note 1 of Table 42: HSI oscillator characteristics
224/226 DS11853 Rev 9

STM32F722xx STM32F723xx Revision history
Table 128. Document revision history (continued)

Date Revision Changes
3-Feb-2022 8 Updated Section 7.7: WLCSP100 package information

Updated:
– Table 81: SPI dynamic characteristics
– Table 101: Synchronous multiplexed NOR/PSRAM read timings
– Table 103: Synchronous non-multiplexed NOR/PSRAM read timings
– Table 107: SDRAM read timings
27-Jul-2022 9 – Table 108: LPSDR SDRAM read timings
– Table 111: Quad-SPI characteristics in SDR mode
– Table 112: Quad-SPI characteristics in DDR mode
– Table 113: Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V
– Table 114: Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V
– New Section 9: Important security notice
DS11853 Rev 9 225/226

225
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product
or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
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STM32F722xx

July 2022 DS11853 Rev 9 1/226

– 1 x CAN (2.0B active) • CRC calculation unit

STM32F722IC, STM32F722IE, STM32F722RC, STM32F722RE, STM32F722VC,

2/226 DS11853 Rev 9

DS11853 Rev 9 3/226

3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4/226 DS11853 Rev 9

6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

DS11853 Rev 9 5/226

6.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 222

9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

6/226 DS11853 Rev 9

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

DS11853 Rev 9 7/226

Table 42. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

8/226 DS11853 Rev 9

Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 174

DS11853 Rev 9 9/226

Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

10/226 DS11853 Rev 9

Figure 42. LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

DS11853 Rev 9 11/226

Figure 94. UFBGA144 top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

12/226 DS11853 Rev 9

DS11853 Rev 9 13/226

14/226 DS11853 Rev 9

Table 2. STM32F722xx and STM32F723xx features and peripheral counts

DS11853 Rev 9 15/226

Table 2. STM32F722xx and STM32F723xx features and peripheral counts (continued)

2.1 Full compatibility throughout the family

16/226 DS11853 Rev 9

Figure 1. Compatible board design for LQFP100 package

DS11853 Rev 9 17/226

Figure 2. Compatible board design for LQFP64 package

V CAP increased to 4.7 μf

ESR 1 ohm or below 1 ohm

Not compatible STM32F722xx pins with either

ESR between 0.1 ohm and 0.2 ohm

18/226 DS11853 Rev 9

2.2 STM32F723xx versus STM32F722xx LQFP100/ LQFP144/

Not compatible pins

Figure 4. Compatible board design for LQFP144 package

PG6, PG7 removed on the STM32F723xx

Not compatible pins

DS11853 Rev 9 19/226

Figure 5. Compatible board design for LQFP176 package

112 PG8 112 PG8

PG6, PG7 removed on the STM32F723xx

Not compatible pins

Figure 6 shows the general block diagram of the device family.

20/226 DS11853 Rev 9

Figure 6. STM32F722xx and STM32F723xx block diagram

DP, DM DMA/ Quad-SPI CLK, CS,D[7:0]