STM32F205RFT6

STM32F205xx
STM32F207xx
ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, USB
OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
Datasheet - production data
Features &"'!
• Core: ARM 32-bit Cortex™-M3 CPU (120 MHz

max) with Adaptive real-time accelerator (ART LQFP64 (10 × 10 mm)
Accelerator™ allowing 0-wait state execution LQFP100 (14 × 14 mm)
UFBGA176 WLCSP64+2
(0.400 mm pitch)
(10 × 10 mm)
performance from Flash memory, MPU, LQFP144 (20 × 20 mm)
LQFP176 (24 × 24 mm)
150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)
• Up to 140 I/O ports with interrupt capability:
• Memories
– Up to 136 fast I/Os up to 60 MHz
– Up to 1 Mbyte of Flash memory
– Up to 138 5 V-tolerant I/Os
– 512 bytes of OTP memory
– Up to 128 + 4 Kbytes of SRAM • Up to 15 communication interfaces
– Flexible static memory controller that – Up to 3 × I2C interfaces (SMBus/PMBus)
supports Compact Flash, SRAM, PSRAM, – Up to 4 USARTs and 2 UARTs (7.5 Mbit/s,
NOR and NAND memories ISO 7816 interface, LIN, IrDA, modem ctrl)
– LCD parallel interface, 8080/6800 modes – Up to 3 SPIs (30 Mbit/s), 2 with muxed I2S
to achieve audio class accuracy via audio
• Clock, reset and supply management
PLL or external PLL
– From 1.8 to 3.6 V application supply+I/Os
– 2 × CAN interfaces (2.0B Active)
– POR, PDR, PVD and BOR
– SDIO interface
– 4 to 26 MHz crystal oscillator
• Advanced connectivity
– Internal 16 MHz factory-trimmed RC
– USB 2.0 full-speed device/host/OTG
– 32 kHz oscillator for RTC with calibration
controller with on-chip PHY
– Internal 32 kHz RC with calibration
– USB 2.0 high-speed/full-speed
• Low power device/host/OTG controller with dedicated
– Sleep, Stop and Standby modes DMA, on-chip full-speed PHY and ULPI
– VBAT supply for RTC, 20 × 32 bit backup – 10/100 Ethernet MAC with dedicated DMA:
registers, and optional 4 KB backup SRAM supports IEEE 1588v2 hardware, MII/RMII
• 3 × 12-bit, 0.5 µs ADCs with up to 24 channels • 8- to 14-bit parallel camera interface
and up to 6 MSPS in triple interleaved mode (48 Mbyte/s max.)
• 2 × 12-bit D/A converters –
• General-purpose DMA: 16-stream controller • CRC calculation unit
with centralized FIFOs and burst support • 96-bit unique ID
• Up to 17 timers Table 1. Device summary
– Up to twelve 16-bit and two 32-bit timers, Reference Part number
up to 120 MHz, each with up to 4 STM32F205RB, STM32F205RC, STM32F205RE,

IC/OC/PWM or pulse counter and STM32F205xx
STM32F205RF, STM32F205RG, STM32F205VB,
STM32F205VC, STM32F205VE, STM32F205VF STM32F205VG,
quadrature (incremental) encoder input STM32F205ZC, STM32F205ZE, STM32F205ZF, STM32F205ZG
• Debug mode: Serial wire debug (SWD), JTAG, STM32F207xx

STM32F207IC, STM32F207IE, STM32F207IF, STM32F207IG,
STM32F207ZC, STM32F207ZE, STM32F207ZF, STM32F207ZG,
and Cortex-M3 Embedded Trace Macrocell™ STM32F207VC, STM32F207VE, STM32F207VF, STM32F207VG
November 2013 DocID15818 Rev 11 1/178

This is information on a product in full production. www.st.com
Contents STM32F20xxx
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . . 18
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 19
3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 21
3.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.16.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 28
3.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 28
3.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.20.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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3.20.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.20.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.21 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.22 Universal synchronous/asynchronous receiver transmitters
(UARTs/USARTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.23 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.24 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.25 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.26 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 34
3.27 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.28 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 35
3.29 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 35
3.30 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.31 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.32 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.33 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.34 ADCs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.35 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.38 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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Contents STM32F20xxx
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 73
6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 73
6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 74
6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 95
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 100
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.24 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 148
6.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 148
6.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
DocID15818 Rev 11 5/178

5
List of tables STM32F20xxx
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F205xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. STM32F207xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 8. STM32F20x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 9. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 10. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 15. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 71
Table 16. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 17. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 73
Table 18. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 73
Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 20. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 76
running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 22. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 23. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 24. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 83
Table 25. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 83
Table 26. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 28. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 29. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 30. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 31. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 32. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 33. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 34. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 35. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 36. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 37. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 38. Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 39. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 40. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 45. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 46. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 48. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 49. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 50. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 51. Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 52. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 53. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 54. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 55. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 56. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 57. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 58. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 59. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 60. Clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 61. ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 62. Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 63. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 64. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 65. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 66. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 67. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 68. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 69. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 70. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 71. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 130
Table 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 131
Table 74. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 75. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 76. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 77. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 78. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 79. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 80. Switching characteristics for PC Card/CF read and write cycles in
attribute/common space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 81. Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . 145
Table 82. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 83. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 84. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 85. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 86. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 87. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 151
Table 88. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . 153
Table 89. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 155
Table 90. LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data. . . . . . . . 157
Table 91. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 92. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . 162
Table 93. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 94. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 95. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
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7
List of figures STM32F20xxx
List of figures
Figure 1. Compatible board design between STM32F10xx and STM32F2xx

for LQFP64 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. STM32F20x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 6. Regulator OFF/internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. Regulator OFF/internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. Startup in regulator OFF: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10. STM32F20x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. STM32F20x WLCSP64+2 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. STM32F20x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 15. STM32F20x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 16. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 17. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 18. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 19. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 20. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 21. Number of wait states versus fCPU and VDD range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 22. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 23. Typical current consumption vs temperature, Run mode, code with data
processing running from RAM, and peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
processing running from RAM, and peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
processing running from Flash, ART accelerator OFF, peripherals ON . . . . . . . . . . . . . . . 79
processing running from Flash, ART accelerator OFF, peripherals OFF . . . . . . . . . . . . . . 79
Figure 27. Typical current consumption vs temperature in Sleep mode,
peripherals ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
peripherals OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 29. Typical current consumption vs temperature in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 30. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 31. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 34. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 35. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 36. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 37. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8/178 DocID15818 Rev 11

STM32F20xxx List of figures
Figure 38. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 39. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 40. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 41. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 42. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 43. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 44. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 45. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 46. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 117
Figure 47. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 48. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 49. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 50. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 51. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 52. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 53. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 125
Figure 54. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 125
Figure 55. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 130
Figure 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 131
Figure 58. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 59. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 60. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 61. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 62. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 63. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 64. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 141
Figure 65. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 141
Figure 66. PC Card/CompactFlash controller waveforms for attribute memory read
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 67. PC Card/CompactFlash controller waveforms for attribute memory write
access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 68. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 143
Figure 69. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 144
Figure 70. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 71. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 72. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 147
Figure 73. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 147
Figure 74. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 75. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 151
Figure 77. Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 78. WLCSP64+2 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . 153
Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 155
Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 83. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline . . . . . . . . 159
Figure 84. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 85. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
DocID15818 Rev 11 9/178

9
Introduction STM32F20xxx
1 Introduction
This datasheet provides the description of the STM32F205xx and STM32F207xx lines of
microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please
refer to Section 2.1: Full compatibility throughout the family.
The STM32F205xx and STM32F207xx datasheet should be read in conjunction with the
STM32F20x/STM32F21x reference manual. They will be referred to as STM32F20x devices
throughout the document.
For information on programming, erasing and protection of the internal Flash memory,
please refer to the STM32F20x/STM32F21x Flash programming manual (PM0059).
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
10/178 DocID15818 Rev 11

STM32F20xxx Description
2 Description
The STM32F20x family is based on the high-performance ARM® Cortex™-M3 32-bit RISC
core operating at a frequency of up to 120 MHz. The family incorporates high-speed
embedded memories (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM), up
to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals
connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.
The devices also feature an adaptive real-time memory accelerator (ART Accelerator™)
which allows to achieve a performance equivalent to 0 wait state program execution from
Flash memory at a CPU frequency up to 120 MHz. This performance has been validated
using the CoreMark benchmark.
All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose
16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers.
a true number random generator (RNG). They also feature standard and advanced
communication interfaces. New advanced peripherals include an SDIO, an enhanced
flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins
and more), and a camera interface for CMOS sensors. The devices also feature standard
peripherals.
• Up to three I2Cs
• Three SPIs, two I2Ss. To achieve audio class accuracy, the I2S peripherals can be
clocked via a dedicated internal audio PLL or via an external PLL to allow
synchronization.
• 4 USARTs and 2 UARTs
• A USB OTG high-speed with full-speed capability (with the ULPI)
• A second USB OTG (full-speed)
• Two CANs
• An SDIO interface
• Ethernet and camera interface available on STM32F207xx devices only.
Note: The STM32F205xx and STM32F207xx devices operate in the –40 to +105 °C temperature
range from a 1.8 V to 3.6 V power supply. On devices in WLCSP64+2 package, if IRROFF
is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to
70 °C temperature range using an external power supply supervisor (see Section 3.16).
A comprehensive set of power-saving modes allow the design of low-power applications.
STM32F205xx and STM32F207xx devices are offered in various packages ranging from 64
pins to 176 pins. The set of included peripherals changes with the device chosen.These
features make the STM32F205xx and STM32F207xx microcontroller family suitable for a
wide range of applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
Figure 4 shows the general block diagram of the device family.
DocID15818 Rev 11 11/178

177
12/178
Description
Table 2. STM32F205xx features and peripheral counts
Peripherals STM32F205Rx STM32F205Vx STM32F205Zx
Flash memory in Kbytes 128 256 512 768 1024 128 256 512 768 1024 256 512 768 1024
System 64 96 128 64 96 128 96 128

SRAM in Kbytes (SRAM1+SRAM2) (48+16) (80+16) (112+16) (48+16) (80+16) (112+16) (80+16) (112+16)
Backup 4 4 4
FSMC memory controller No Yes(1)
Ethernet No
General-purpose 10
Advanced-control 2
Timers Basic 2
IWDG Yes
WWDG Yes
RTC Yes
DocID15818 Rev 11
Random number generator Yes

2
SPI/(I S) 3 (2)(2)
2
I C 3
USART 4
Comm. UART 2
interfaces
USB OTG FS Yes
USB OTG HS Yes
CAN 2
Camera interface No
GPIOs 51 82 114
SDIO Yes
12-bit ADC 3
Number of channels 16 16 24
12-bit DAC Yes

Number of channels 2
STM32F20xxx
Maximum CPU frequency 120 MHz
Operating voltage 1.8 V to 3.6 V(3)

Table 2. STM32F205xx features and peripheral counts (continued)
STM32F20xxx
Peripherals STM32F205Rx STM32F205Vx STM32F205Zx
Ambient temperatures: –40 to +85 °C /–40 to +105 °C

Operating temperatures
Junction temperature: –40 to + 125 °C
LQFP64 LQFP64
LQFP6
Package LQFP64 WLCSP64 WLCSP6 LQFP100 LQFP144
4
+2 4+2
1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip
Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not
available in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature
range using an external power supply supervisor (see Section 3.16).
Table 3. STM32F207xx features and peripheral counts

Peripherals STM32F207Vx STM32F207Zx STM32F207Ix
DocID15818 Rev 11
Flash memory in Kbytes 256 512 768 1024 256 512 768 1024 256 512 768 1024
System 128
SRAM in Kbytes (SRAM1+SRAM2) (112+16)
Backup 4
FSMC memory controller Yes(1)
Ethernet Yes
General-purpose 10
Advanced-control 2
Timers Basic 2
IWDG Yes
WWDG Yes
RTC Yes
Random number generator Yes
Description
13/178
Table 3. STM32F207xx features and peripheral counts (continued)
14/178
Description
Peripherals STM32F207Vx STM32F207Zx STM32F207Ix
2 (2)
SPI/(I S) 3 (2)
I2C 3
USART 4
Comm. interfaces UART 2
USB OTG FS Yes
USB OTG HS Yes
CAN 2
Camera interface Yes
GPIOs 82 114 140
SDIO Yes
12-bit ADC 3
Number of channels 16 24 24
DocID15818 Rev 11
12-bit DAC Yes

Number of channels 2
Maximum CPU frequency 120 MHz
Operating voltage 1.8 V to 3.6 V(3)
Ambient temperatures: –40 to +85 °C/–40 to +105 °C

Operating temperatures
Junction temperature: –40 to + 125 °C
LQFP176/
Package LQFP100 LQFP144
UFBGA176
1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can
only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package.
2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an
external power supply supervisor (see Section 3.16).
STM32F20xxx
2.1 Full compatibility throughout the family

The STM32F205xx and STM32F207xx constitute the STM32F20x family whose members
are fully pin-to-pin, software and feature compatible, allowing the user to try different
memory densities and peripherals for a greater degree of freedom during the development
cycle.
The STM32F205xx and STM32F207xx devices maintain a close compatibility with the
whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The
STM32F205xx and STM32F207xx, however, are not drop-in replacements for the
STM32F10xxx devices: the two families do not have the same power scheme, and so their
power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F20x
family remains simple as only a few pins are impacted.
Figure 3 and Figure 1 provide compatible board designs between the STM32F20x and the
STM32F10xxx family.

for LQFP64 package
VSS
48 VSS 33
49 47 32
31
VSS
VSS
0 resistor or soldering bridge
present for the STM32F10xx
configuration, not present in the
STM32F2xx configuration
64 17
1 16
ai15962b
DocID15818 Rev 11 15/178

177
Description STM32F20xxx

for LQFP100 package
75 VSS 51
76 73 50
49
VSS
VSS
0 Ω resistor or soldering bridge
99 (RFU)
STM32F2xx configuration
100 19 20 26
1 25
VSS
VDD V
SS
Two 0 Ω resistors connected to: VDD VSS VSS for STM32F10xx
- VSS for the STM32F10xx VDD for STM32F2xx
- VDD, VSS, or NC for the STM32F2xx
ai15961c

for LQFP144 package
108 VSS 73
109 106 72
71
VSS
VSS
0 Ω resistor or soldering bridge
143 (RFU) STM32F2xx configuration
144 30 31 37
1 36
VSS
VDD V
SS
Two 0 Ω resistors connected to:
- VSS for the STM32F10xx VDD VSS
- VDD, VSS, or NC for the STM32F2xx
ai15960c
1. RFU = reserved for future use.
16/178 DocID15818 Rev 11

Figure 4. STM32F20x block diagram

NJTRST, JTDI, CLK, NE [3:0], A[23:0]
JTCK/SWCLK External memory D[31:0], OEN, WEN,
JTDO/SWD JTAG & SW MPU controller (FSMC) NBL[3:0], NL, NREG
JTDO/TRACESWO ETM NVIC AHB3 SRAM, PSRAM, NOR Flash, NWAIT/IORDY, CD
TRACECLK
PC Card (ATA), NAND Flash NIORD, IOWR, INT[2:3]
TRACED[3:0]
ARM Cortex-M3 INTN, NIIS16 as AF
I-BUS
ACCEL/
CACHE
120 MHz Flash
AHB bus-matrix 8S7M

ART accelerator D-BUS 1 Mbyte
S-BUS
RNG
MII or RMII as AF Ethernet MAC DMA/
FIFO
MDIO as AF FIFO SRAM 112 KB Camera HSYNC, VSYNC
10/100 PIXCLK, D[13:0]
interface
SRAM 16 KB
PHY
DP, DM USB DMA/

ULPI: CK, D(7:0), DIR, STP, NXT OTG HS FIFO DP
FIFO
PHY
SCL/SDA, INTN, ID, VBUS, SOF USB
AHB2 120 MHz DM
8 Streams OTG FS SCL, SDA, INTN, ID, VBUS, SOF
DMA2 FIFO
AHB1 120 MHz
8 Streams
DMA1 FIFO VDD12 Power managmt
Voltage
VDD = 1.8 to 3.6 V
regulator VSS
3.3 V to 1.2 V
VCAP1, VCAP2
@VDDA @VDD
POR Supply
PA[15:0] RC HS
GPIO PORT A Reset supervision
RC LS Int POR/PDR/
PB[15:0] BOR VDDA, VSSA
GPIO PORT B
PLL1&2 NRST
PVD
PC[15:0] GPIO PORT C
@VDDA @VDD
PD[15:0] GPIO PORT D XTAL OSC OSC_IN
4- 26 MHz OSC_OUT
PE[15:0] Reset &
GPIO PORT E
IWDG
clock
MANAGT
PF[15:0]
GPIO PORT F control
PWR VBAT = 1.65 to 3.6 V
PG[15:0] interface
GPIO PORT G @VBAT
HCLKx
FCLK
PCLKx
OSC32_IN
PH[15:0] XTAL 32 kHz
GPIO PORT H OSC32_OUT
LS
PI[11:0] RTC
GPIO PORT I AWU RTC_AF1
Backup register RTC_AF1
LS
4 KB BKSPRAM
TIM2 32b 4 channels, ETR as AF

16b
TIM3 4 channels, ETR as AF
DMA2 DMA1
16b 4 channels, ETR as AF
TIM4
AHB/APB2 AHB/APB1
TIM5 32b 4 channels
140 AF EXT IT. WKUP 16b

TIM12 2 channels as AF
D[7:0]
TIM13 16b
FIFO
CMD, CK as AF SDIO / MMC 1 channel as AF
4 compl. channels (TIM1_CH[1:4]N)

4 channels (TIM1_CH[1:4]), ETR, 16b TIM14 16b 1 channel as AF
BKIN as AF
TIM1 / PWM
smcard RX, TX, CK,
4 compl. channels (TIM1_CH[1:4]N) USART2
4 channels (TIM1_CH[1:4]), ETR, TIM8 / PWM 16b WWDG
irDA CTS, RTS as AF
BKIN as AF smcard RX, TX, CK
16b USART3
2 channels as AF TIM9 irDA CTS, RTS as AF
APB1 30MHz
UART4 RX, TX as AF
1 channel as AF TIM10 16b
16b UART5 RX, TX as AF
APB1 30MHz
1 channel as AF TIM11
MOSI/DOUT, MISO/DIN, SCK/CK
60MHz
RX, TX, CK, smcard SPI2/I2S2

USART 1 16b NSS/WS, MCK as AF
CTS, RTS as AF irDA TIM6
60MHz
smcard SPI3/I2S3 MOSI/DOUT, MISO/DIN, SCK/CK

RX, TX, CK, USART 6
APB2
16b NSS/WS, MCK as AF

CTS, RTS as AF irDA TIM7
APB2
I2C1/SMBUS SCL, SDA, SMBA as AF

MOSI, MISO SPI1
SCK, NSS as AF
@VDDA I2C2/SMBUS SCL, SDA, SMBA as AF
VDDREF_ADC
USART 2MBps
Temperature sensor I2C3/SMBUS SCL, SDA, SMBA as AF
8 analog inputs common @VDDA
to the 3 ADCs ADC1
8 analog inputs common ADC2 DAC1 ITF bxCAN1 TX, RX
FIFO
to the ADC1 & 2 IF

8 analog inputs to ADC3 ADC 3 DAC2
bxCAN2 TX, RX
DAC1_OUT DAC2_OUT
as AF as AF ai17614c
1. The timers connected to APB2 are clocked from TIMxCLK up to 120 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 60 MHz.
2. The camera interface and Ethernet are available only in STM32F207xx devices.
DocID15818 Rev 11 17/178

177
Functional overview STM32F20xxx
3 Functional overview
3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM

The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded
systems. It was developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced response to interrupts.
The ARM Cortex-M3 32-bit RISC processor features exceptional code-efficiency, delivering
the high-performance expected from an ARM core in the memory size usually associated
with 8- and 16-bit devices.
With its embedded ARM core, the STM32F20x family is compatible with all ARM tools and
software.
Figure 4 shows the general block diagram of the STM32F20x family.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)

The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard ARM® Cortex™-M3 processors. It balances the inherent performance advantage
of the ARM Cortex-M3 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher operating frequencies.
To release the processor full 150 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 120 MHz.
3.3 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
18/178 DocID15818 Rev 11

STM32F20xxx Functional overview
3.4 Embedded Flash memory

The STM32F20x devices embed a 128-bit wide Flash memory of 128 Kbytes, 256 Kbytes,
512 Kbytes, 768 Kbytes or 1 Mbytes available for storing programs and data.
The devices also feature 512 bytes of OTP memory that can be used to store critical user
data such as Ethernet MAC addresses or cryptographic keys.
3.5 CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
3.6 Embedded SRAM

All STM32F20x products embed:
• Up to 128 Kbytes of system SRAM accessed (read/write) at CPU clock speed with 0
wait states
• 4 Kbytes of backup SRAM.
The content of this area is protected against possible unwanted write accesses, and is
retained in Standby or VBAT mode.
3.7 Multi-AHB bus matrix

The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB
HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a
seamless and efficient operation even when several high-speed peripherals work
simultaneously.
DocID15818 Rev 11 19/178

177
Figure 5. Multi-AHB matrix
ARM GP GP MAC USB OTG

Cortex-M3 DMA1 DMA2 Ethernet HS
I-bus
D-bus
S-bus
DMA_P1
DMA_MEM1
DMA_MEM2
DMA_P2
ETHERNET_M
USB_HS_M
S0 S1 S2 S3 S4 S5 S6 S7
ICODE
ACCEL.
M0
Flash
ART
memory
M1 DCODE
M2 SRAM
112 Kbyte
M3 SRAM
16 Kbyte APB1
M4 AHB1
periph
APB2
M5 AHB2
periph
M6 FSMC
Static MemCtl
Bus matrix-S
ai15963c
3.8 DMA controller (DMA)

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB
peripherals, support burst transfer and are designed to provide the maximum peripheral
bandwidth (AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
20/178 DocID15818 Rev 11

The DMA can be used with the main peripherals:

• SPI and I2S
• I2C
• USART and UART
• General-purpose, basic and advanced-control timers TIMx
• DAC
• SDIO
• Camera interface (DCMI)
• ADC.
3.9 Flexible static memory controller (FSMC)

The FSMC is embedded in all STM32F20x devices. It has four Chip Select outputs
supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR Flash and
NAND Flash.
Functionality overview:
• Write FIFO
• Code execution from external memory except for NAND Flash and PC Card
• Maximum frequency (fHCLK) for external access is 60 MHz
LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-
effective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
3.10 Nested vectored interrupt controller (NVIC)

The STM32F20x devices embed a nested vectored interrupt controller able to manage 16
priority levels, and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of
the Cortex™-M3.
The NVIC main features are the following:
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
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177
3.11 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 23 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected
to the 16 external interrupt lines.
3.12 Clocks and startup

On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can
then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
This clock is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator and a software interrupt is generated (if enabled). Similarly,
full interrupt management of the PLL clock entry is available when necessary (for example if
an indirectly used external oscillator fails).
The advanced clock controller clocks the core and all peripherals using a single crystal or
oscillator. In particular, the ethernet and USB OTG FS peripherals can be clocked by the
system clock.
Several prescalers and PLLs allow the configuration of the three AHB buses, the high-
speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of
the three AHB buses is 120 MHz and the maximum frequency the high-speed APB domains
is 60 MHz. The maximum allowed frequency of the low-speed APB domain is 30 MHz.
The devices embed a dedicate PLL (PLLI2S) which allow to achieve audio class
performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
3.13 Boot modes

At startup, boot pins are used to select one out of three boot options:
• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB
OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade).
3.14 Power supply schemes

• VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins. On devices in WLCSP64+2 package, if
IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device operates
22/178 DocID15818 Rev 11

in the 0 to 70 °C temperature range using an external power supply supervisor (see

Section 3.16).
• VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Refer to Figure 19: Power supply scheme for more details.
3.15 Power supply supervisor

The devices have an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry.
At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V.
After the 1.8 V POR threshold level is reached, the option byte loading process starts, either
to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three
BOR thresholds are available through option bytes.
The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or
VBOR, without the need for an external reset circuit. On devices in WLCSP64+2 package,
the BOR, POR and PDR features can be disabled by setting IRROFF pin to VDD. In this
mode an external power supply supervisor is required (see Section 3.16).
The devices also feature an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.16 Voltage regulator

The regulator has five operating modes:
• Regulator ON
– Main regulator mode (MR)
– Low power regulator (LPR)
– Power-down
• Regulator OFF
– Regulator OFF/internal reset ON
– Regulator OFF/internal reset OFF
3.16.1 Regulator ON
The regulator ON modes are activated by default on LQFP packages.On WLCSP64+2
package, they are activated by connecting both REGOFF and IRROFF pins to VSS, while
only REGOFF must be connected to VSS on UFBGA176 package (IRROFF is not available).
VDD minimum value is 1.8 V.
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177
There are three power modes configured by software when the regulator is ON:
• MR is used in the nominal regulation mode
• LPR is used in Stop modes
The LP regulator mode is configured by software when entering Stop mode.
• Power-down is used in Standby mode.
The Power-down mode is activated only when entering Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost).
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin. Refer to
Figure 19: Power supply scheme and Table 16: VCAP1/VCAP2 operating conditions.
All packages have the regulator ON feature.
3.16.2 Regulator OFF

This feature is available only on packages featuring the REGOFF pin. The regulator is
disabled by holding REGOFF high. The regulator OFF mode allows to supply externally a
V12 voltage source through VCAP_1 and VCAP_2 pins.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors. Refer to Figure 19: Power supply scheme.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset the part of the 1.2 V logic
power domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used at power-on reset. As a
consequence, PA0 and NRST pins must be managed separately if the debug
connection at reset or pre-reset is required.
Regulator OFF/internal reset ON

On WLCSP64+2 package, this mode is activated by connecting REGOFF pin to VDD and
IRROFF pin to VSS. On UFBGA176 package, only REGOFF must be connected to VDD
(IRROFF not available). In this mode, VDD/VDDA minimum value is 1.8 V.
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through VCAP_1 and VCAP_2 pins, in addition to VDD.
24/178 DocID15818 Rev 11

Figure 6. Regulator OFF/internal reset ON

Power-down reset risen
before VCAP_1/VCAP_2 stabilization
External VCAP_1/2
power supply supervisor Application reset
signal (optional)
Ext. reset controller active
when VCAP_1/2 < 1.08 V
VDD
(1.8 to 3.6 V)
PA0 NRST
VDD
REGOFF
1.2 V
VCAP_1 IRROFF
VCAP_2
ai18476b
The following conditions must be respected:

• VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
• If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to
reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and
VCAP_2 reach 1.08 V and until VDD reaches 1.8 V (see Figure 8).
• Otherwise, If the time for VCAP_1 and VCAP_2 to reach 1.08 V is slower than the time for
VDD to reach 1.8 V, then PA0 should be asserted low externally (see Figure 9).
• If VCAP_1 and VCAP_2 go below 1.08 V and VDD is higher than 1.8 V, then a reset must
be asserted on PA0 pin.
Regulator OFF/internal reset OFF

On WLCSP64+2 package, this mode activated by connecting REGOFF to VSS and IRROFF
to VDD. IRROFF cannot be activated in conjunction with REGOFF. This mode is available
only on the WLCSP64+2 package. It allows to supply externally a 1.2 V voltage source
through VCAP_1 and VCAP_2 pins. In this mode, the integrated power-on reset (POR)/ power-
down reset (PDR) circuitry is disabled.
An external power supply supervisor should monitor both the external 1.2 V and the external
VDD supply voltage, and should maintain the device in reset mode as long as they remain
below a specified threshold. The VDD specified threshold, below which the device must be
maintained under reset, is 1.8 V. This supply voltage can drop to 1.7 V when the device
operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving modes
allows to design low-power applications.
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177
Figure 7. Regulator OFF/internal reset OFF
VDD 1.2 V
External VDD/VCAP_1/2
power supply supervisor
Ext. reset controller active
when VDD<1.7V and
VCAP_1/2 < 1.08 V VDD
PA0 NRST
REGOFF IRROFF
1.2 V
VCAP_1
VCAP_2
ai18477b
The following conditions must be respected:

• VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains (see Figure 8).
• PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.08 V,
and until VDD reaches 1.7 V.
• NRST should be controlled by an external reset controller to keep the device under
reset when VDD is below 1.7 V (see Figure 9).
In this mode, when the internal reset is OFF, the following integrated features are no more
supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
• The brownout reset (BOR) circuitry is disabled.
• The embedded programmable voltage detector (PVD) is disabled.
• VBAT functionality is no more available and VBAT pin should be connected to VDD.
26/178 DocID15818 Rev 11

Figure 8. Startup in regulator OFF: slow VDD slope

- power-down reset risen after VCAP_1/VCAP_2 stabilization
VDD
PDR=1.8 V
VCAP_1 /V CAP_2
1.2 V
1.08 V
time
PA0 tied to NRST

NRST
time
1. This figure is valid both whatever the internal reset mode (ON or OFF).
Figure 9. Startup in regulator OFF: fast VDD slope

- power-down reset risen before VCAP_1/VCAP_2 stabilization
VDD
PDR=1.8 V
VCAP_1 /V CAP_2
1.2 V
1.08 V
time
PA0 asserted externally

NRST
time
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177
3.16.3 Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability

Regulator ON/internal Regulator Regulator OFF/internal
Package
reset ON OFF/internal reset ON reset OFF
LQFP64
LQFP100
Yes No No
LQFP144
LQFP176
Yes Yes Yes
WLCSP 64+2 REGOFF and IRROFF REGOFF set to VDD REGOFF set to VSS and
set to VSS and IRROFF set to VSS IRROFF set to VDD
Yes Yes
UFBGA176 No
REGOFF set to VSS REGOFF set to VDD
3.17 Real-time clock (RTC), backup SRAM and backup registers

The backup domain of the STM32F20x devices includes:
• The real-time clock (RTC)
• 4 Kbytes of backup SRAM
• 20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Its main features are the
following:
• Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 day of the month.
• Programmable alarm and programmable periodic interrupts with wakeup from Stop and
Standby modes.
• It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-
power RC oscillator or the high-speed external clock divided by 128. The internal low-
speed RC has a typical frequency of 32 kHz. The RTC can be calibrated using an
external 512 Hz output to compensate for any natural quartz deviation.
• Two alarm registers are used to generate an alarm at a specific time and calendar
fields can be independently masked for alarm comparison. To generate a periodic
interrupt, a 16-bit programmable binary auto-reload downcounter with programmable
resolution is available and allows automatic wakeup and periodic alarms from every
120 µs to every 36 hours.
• A 20-bit prescaler is used for the time base clock. It is by default configured to generate
a time base of 1 second from a clock at 32.768 kHz.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
The 4-Kbyte backup SRAM is an EEPROM-like area.It can be used to store data which
need to be retained in VBAT and standby mode.This memory area is disabled to minimize
power consumption (see Section 3.18: Low-power modes). It can be enabled by software.
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The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 3.18: Low-power
modes).
Like backup SRAM, the RTC and backup registers are supplied through a switch that is
powered either from the VDD supply when present or the VBAT pin.
3.18 Low-power modes

The STM32F20x family supports three low-power modes to achieve the best compromise
between low power consumption, short startup time and available wakeup sources:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup.
• Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event
occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped when the device
enters the Stop or Standby mode.
3.19 VBAT operation

The VBAT pin allows to power the device VBAT domain from an external battery or an
external supercapacitor.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When using WLCSP64+2 package, if IRROFF pin is connected to VDD, the VBAT
functionality is no more available and VBAT pin should be connected to VDD.
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177
3.20 Timers and watchdogs

The STM32F20x devices include two advanced-control timers, eight general-purpose
timers, two basic timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 5 compares the features of the advanced-control, general-purpose and basic timers.
Table 5. Timer feature comparison

DMA Capture/ Max Max
Counter Counter Prescaler Complementary
Timer type Timer request compare interface timer
resolution type factor output
generation channels clock clock
Up, Any integer

Advanced- TIM1, 120
16-bit Down, between 1 Yes 4 Yes 60 MHz
control TIM8 MHz
Up/down and 65536
Up, Any integer
TIM2, 60
32-bit Down, between 1 Yes 4 No 30 MHz
TIM5 MHz
General Up/down and 65536
purpose Up, Any integer
TIM3, 60
16-bit Down, between 1 Yes 4 No 30 MHz
TIM4 MHz
Up/down and 65536
Any integer
TIM6, 60
Basic 16-bit Up between 1 Yes 0 No 30 MHz
TIM7 MHz
and 65536
Any integer
120
TIM9 16-bit Up between 1 No 2 No 60 MHz
MHz
and 65536
Any integer
TIM10, 120
16-bit Up between 1 No 1 No 60 MHz
TIM11 MHz
General and 65536
purpose Any integer
60
TIM12 16-bit Up between 1 No 2 No 30 MHz
MHz
and 65536
Any integer
TIM13, 60
16-bit Up between 1 No 1 No 30 MHz
TIM14 MHz
and 65536
3.20.1 Advanced-control timers (TIM1, TIM8)

The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge- or center-aligned modes)
• One-pulse mode output
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If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The TIM1 and TIM8 counters can be frozen in debug mode. Many of the advanced-control
timer features are shared with those of the standard TIMx timers which have the same
architecture. The advanced-control timer can therefore work together with the TIMx timers
via the Timer Link feature for synchronization or event chaining.
3.20.2 General-purpose timers (TIMx)

There are ten synchronizable general-purpose timers embedded in the STM32F20x devices
(see Table 5 for differences).
TIM2, TIM3, TIM4, TIM5

The STM32F20x include 4 full-featured general-purpose timers. TIM2 and TIM5 are 32-bit
timers, and TIM3 and TIM4 are 16-bit timers. The TIM2 and TIM5 timers are based on a 32-
bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4
independent channels for input capture/output compare, PWM or one-pulse mode output.
This gives up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other
general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link
feature for synchronization or event chaining.
The counters of TIM2, TIM3, TIM4, TIM5 can be frozen in debug mode. Any of these
general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable
of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-
effect sensors.
TIM10, TIM11 and TIM9

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10 and
TIM11 feature one independent channel, whereas TIM9 has two independent channels for
input capture/output compare, PWM or one-pulse mode output. They can be synchronized
with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be
used as simple time bases.
TIM12, TIM13 and TIM14

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM13 and
TIM14 feature one independent channel, whereas TIM12 has two independent channels for
input capture/output compare, PWM or one-pulse mode output. They can be synchronized
with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers.
They can also be used as simple time bases.
3.20.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
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177
3.20.4 Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
The counter can be frozen in debug mode.
3.20.5 Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.20.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
• A 24-bit downcounter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source
3.21 Inter-integrated circuit interface (I²C)

Up to three I2C bus interfaces can operate in multimaster and slave modes. They can
support the Standard- and Fast-modes. They support the 7/10-bit addressing mode and the
7-bit dual addressing mode (as slave). A hardware CRC generation/verification is
embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
3.22 Universal synchronous/asynchronous receiver transmitters

(UARTs/USARTs)
The STM32F20x devices embed four universal synchronous/asynchronous receiver
transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous
receiver transmitters (UART4 and UART5).
These six interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 7.5 Mbit/s. The other available interfaces communicate at
up to 3.75 Mbit/s.
USART1, USART2, USART3 and USART6 also provide hardware management of the CTS
and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication
capability. All interfaces can be served by the DMA controller.
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Table 6. USART feature comparison

Max. baud rate Max. baud rate
USART Standard Modem SPI Smartcard in Mbit/s in Mbit/s APB
LIN irDA
name features (RTS/CTS) master (ISO 7816) (oversampling (oversampling mapping
by 16) by 8)
APB2 (max.
USART1 X X X X X X 1.87 7.5
60 MHz)
APB1 (max.
USART2 X X X X X X 1.87 3.75
30 MHz)
APB1 (max.
USART3 X X X X X X 1.87 3.75
30 MHz)
APB1 (max.
UART4 X - X - X - 1.87 3.75
30 MHz)
APB1 (max.
UART5 X - X - X - 3.75 3.75
30 MHz)
APB2 (max.
USART6 X X X X X X 3.75 7.5
60 MHz)
3.23 Serial peripheral interface (SPI)

The STM32F20x devices feature up to three SPIs in slave and master modes in full-duplex
and simplex communication modes. SPI1 can communicate at up to 30 Mbits/s, while SPI2
and SPI3 can communicate at up to 15 Mbit/s. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the
DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
3.24 Inter-integrated sound (I2S)

Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can
operate in master or slave mode, in half-duplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as input or output channels. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx interfaces can be served by the DMA controller.
3.25 SDIO
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
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177
The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with the
SD Memory Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.26 Ethernet MAC interface with dedicated DMA and IEEE 1588
support
Peripheral available only on the STM32F207xx devices.
The STM32F207xx devices provide an IEEE-802.3-2002-compliant media access controller
(MAC) for ethernet LAN communications through an industry-standard medium-
independent interface (MII) or a reduced medium-independent interface (RMII). The
STM32F207xx requires an external physical interface device (PHY) to connect to the
physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F207xx MII
port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz
(MII) or 50 MHz (RMII) output from the STM32F207xx.
The STM32F207xx includes the following features:
• Supports 10 and 100 Mbit/s rates
• Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F20x and STM32F21x reference manual for
details)
• Tagged MAC frame support (VLAN support)
• Half-duplex (CSMA/CD) and full-duplex operation
• MAC control sublayer (control frames) support
• 32-bit CRC generation and removal
• Several address filtering modes for physical and multicast address (multicast and
group addresses)
• 32-bit status code for each transmitted or received frame
• Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes, that is 4 Kbytes in total
• Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
• Triggers interrupt when system time becomes greater than target time
3.27 Controller area network (CAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
34/178 DocID15818 Rev 11

CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared
with any other peripheral.
3.28 Universal serial bus on-the-go full-speed (OTG_FS)

The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
• Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 4 bidirectional endpoints
• 8 host channels with periodic OUT support
• HNP/SNP/IP inside (no need for any external resistor)
• For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
• Internal FS OTG PHY support
3.29 Universal serial bus on-the-go high-speed (OTG_HS)

The STM32F20x devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG
peripheral. The USB OTG HS supports both full-speed and high-speed operations. It
integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin
interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS
mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
• Combined Rx and Tx FIFO size of 1024× 35 bits with dynamic FIFO sizing
• Supports the session request protocol (SRP) and host negotiation protocol (HNP)
• 6 bidirectional endpoints
• 12 host channels with periodic OUT support
• Internal FS OTG PHY support
• External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
• Internal USB DMA
• HNP/SNP/IP inside (no need for any external resistor)
• For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
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177
3.30 Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S application. It allows to
achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S sample rate change without
disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 kHz to 192 kHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S
flow with an external PLL (or Codec output).
3.31 Digital camera interface (DCMI)

The camera interface is not available in STM32F205xx devices.
STM32F207xx products embed a camera interface that can connect with camera modules
and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The
camera interface can sustain up to 27 Mbyte/s at 27 MHz or 48 Mbyte/s at 48 MHz. It
features:
• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12- or 14-bit
• Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
• Supports continuous mode or snapshot (a single frame) mode
• Capability to automatically crop the image
3.32 True random number generator (RNG)

All STM32F2xxx products embed a true RNG that delivers 32-bit random numbers
produced by an integrated analog circuit.
3.33 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O alternate function configuration can be locked if needed by following a specific
sequence in order to avoid spurious writing to the I/Os registers.
To provide fast I/O handling, the GPIOs are on the fast AHB1 bus with a clock up to
120 MHz that leads to a maximum I/O toggling speed of 60 MHz.
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3.34 ADCs (analog-to-digital converters)

Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simultaneous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
The events generated by the timers TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 can be
internally connected to the ADC start trigger and injection trigger, respectively, to allow the
application to synchronize A/D conversion and timers.
3.35 DAC (digital-to-analog converter)

The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The design structure is composed of integrated resistor
strings and an amplifier in inverting configuration.
This dual digital Interface supports the following features:
• two DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• external triggers for conversion
• input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
3.36 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.8 and 3.6 V. The temperature sensor is internally connected
to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a
digital value.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
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177
3.37 Serial wire JTAG debug port (SWJ-DP)

The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
3.38 Embedded Trace Macrocell™

The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F20x through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
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STM32F20xxx Pinouts and pin description
4 Pinouts and pin description
Figure 10. STM32F20x LQFP64 pinout
BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD2
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT 1 48 VDD
PC13-RTC_AF1 2 47 VCAP_2
PC14-OSC32_IN 3 46 PA13
PC15-OSC32_OUT 4 45 PA12
PH0-OSC_IN 5 44 PA11
PH1-OSC_OUT 6 43 PA10
NRST 7 42 PA9
PC0 8 41 PA8
PC1 9 LQFP64 40 PC9
PC2 10 39 PC8
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0-WKUP 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD
PA3
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS
VCAP_1
VDD
ai15969c
1. The above figure shows the package top view.
Figure 11. STM32F20x WLCSP64+2 ballout
1 2 3 4 5 6 7 8 9
A PA14 PA15 PB3 PB5 PB7 PB9 VDD VBAT

PC12
B VSS PA13 PC10 PB4 PB6 BOOT0 PB8 PC13 PC14
C PA12 VCAP_2 PC11 PD2 IRROFF PC15
D PC9 PA11 PA10 PC2 VSS VDD
PH0-
E VDD PA8 PA9 PA0 NRST
OSC_IN
PH1-
F VSS PC7 PC8 VREF+ PC1 OSC_OUT
G PB15 PC6 PC5 PA3 PC3 PC0
H PB14 PB13 PB10 PC4 PA6 PA5 REGOFF PA1 VSS_5
J PB12 PB11 VCAP_1 PB2 PB1 PB0 PA7 PA4 PA2
ai18470c
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177
Pinouts and pin description STM32F20xxx
BOOT0
PC12
PC10
PC11
PA15
PA14
RFU
VDD
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VCAP_2
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13-RTC_AF1 7 69 PA10
PC14-OSC32_IN 8 68 PA 9
PC15-OSC32_OUT 9 67 PA 8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 LQFP100 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2 17 59 PD12
PC3 18 58 PD11
VDD 19 57 PD10
VSSA 20 56 PD9
VREF+ 21 55 PD8
VDDA 22 54 PB15
PA0-WKUP 23 53 PB14
PA1 24 52 PB13
PA2 25 51 PB12
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCAP_1
PA3
PA4
PA5
PA6
PA7
PC4
PC5
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VDD
PB0
PB1
PB2
PE7
PE8
PE9
PE11
PB11
ai15970e
1. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected.
40/178 DocID15818 Rev 11

BOOT0
PG15
PG14
PG13
PG12
PG11
PG10
PC12
PC11
PC10
PA15
PA14
PG9
RFU
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
VDD
VDD
VSS
VSS
VDD
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
109
120
119
118
117
116
115
114
113
112
110
111
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VCAP_2
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13-RTC_AF1 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19 LQFP144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2 28 81 PD12
PC3 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0-WKUP 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
72
61
62
63
64
65
66
67
68
69
70
71
PA3
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP_1
VDD
VDD
VDD
VDD
VSS
VSS
VSS
ai15971e
DocID15818 Rev 11 41/178

177
PDR_ON
BOOT0
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
PG9
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
VDD
VDD
VDD
VSS
VSS
VSS
DD
PI7
PI6
PI5
PI4
PI3
PI2
V
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
141
140
152
151
150
149
148
147
146
145
144
143
142
139
138
137
136
135
134
133
PE2 1 132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8-RTC_AF2 7 126 VSS
PC13-RTC_AF1 8 125 VCAP_2
PC14-OSC32_IN 9 124 PA13
PC15-OSC32_OUT 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDD
PF4 20 113 VSS
PF5 21 112 PG8
VSS 22
LQFP176 111 PG7
VDD 23 110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
PF10 28 105 PD15
PH0-OSC_IN 29 104 PD14
PH1-OSC_OUT 30 103 VDD
NRST 31 102 VSS
PC0 32 101 PD13
PC1 33 100 PD12
PC2 34 99 PD11
PC3 35 98 PD10
VDD 36 97 PD9
VSSA 37 96 PD8
VREF+ 38 95 PB15
VDDA 39 94 PB14
PA0-WKUP 40 93 PB13
PA1 41 92 PB12
PA2 42 91 VDD
PH2 43 90 VSS
PH3 44 89 PH12
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
80
69
70
71
72
73
74
75
76
77
78
79
88
81
82
83
84
85
86
87
VDD
VDD
VDD
VDD
VCAP_1
VSS
PC4
PC5
PH10
PF12
PF13
PF14
PF15
VSS
PH4
PH5
VSS
PG0
PG1
PE10
PE12
PE13
PE14
PE15
PB10
PH6
PH7
PH8
PH9
PB0
PB1
PB2
PE7
PE8
PE9
PH11
PF11
PE11
PB11
PA3
PA4
PA5
PA6
PA7
ai15972e
42/178 DocID15818 Rev 11

Figure 15. STM32F20x UFBGA176 ballout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
C VBAT PI7 PI6 PI5 VDD RFU VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11
PC13- PI8-
D PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10
TAMP1 TAMP2
PC14-
E PF0 PI10 PI11 PH13 PH14 PI0 PA9
OSC32_IN
PC15-
F VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP_2 PC9 PA8
OSC32_OUT
PH0-
G VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
OSC_IN
PH1-
H PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD PG8 PC6
OSC_OUT
J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6
K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
L PF10 PF9 PF8 REGOFF PH11 PH10 PD15 PG2
M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13
PA0-
N VREF- PA1 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10
WKUP
P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15
ai17293c
Table 7. Legend/abbreviations used in the pinout table

Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input/ output pin
FT 5 V tolerant I/O
TTa 3.3 V tolerant I/O
I/O structure
B Dedicated BOOT0 pin
NRST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
Functions selected through GPIOx_AFR registers
functions
Additional
Functions directly selected/enabled through peripheral registers
functions
DocID15818 Rev 11 43/178

177
Table 8. STM32F20x pin and ball definitions

Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64
(function after Alternate functions

functions
reset)(1)
TRACECLK, FSMC_A23,
- - 1 1 1 A2 PE2 I/O FT
ETH_MII_TXD3, EVENTOUT
TRACED0,FSMC_A19,
- - 2 2 2 A1 PE3 I/O FT
EVENTOUT
TRACED1,FSMC_A20,
- - 3 3 3 B1 PE4 I/O FT
DCMI_D4, EVENTOUT
TRACED2, FSMC_A21,
- - 4 4 4 B2 PE5 I/O FT TIM9_CH1, DCMI_D6,
EVENTOUT
TRACED3, FSMC_A22,
- - 5 5 5 B3 PE6 I/O FT TIM9_CH2, DCMI_D7,
EVENTOUT
1 A9 6 6 6 C1 VBAT S
- - - - 7 D2 PI8 I/O FT (2)(3) EVENTOUT RTC_AF2
2 B8 7 7 8 D1 PC13 I/O FT (2)(3) EVENTOUT RTC_AF1
PC14/OSC32_IN
3 B9 8 8 9 E1 I/O FT (2)(3) EVENTOUT OSC32_IN(4)
(PC14)
PC15-OSC32_OUT
4 C9 9 9 10 F1 I/O FT (2)(3) EVENTOUT OSC32_OUT(4)
(PC15)
- - - - 11 D3 PI9 I/O FT CAN1_RX,EVENTOUT
ETH_MII_RX_ER,
- - - - 12 E3 PI10 I/O FT
EVENTOUT
OTG_HS_ULPI_DIR,
- - - - 13 E4 PI11 I/O FT
EVENTOUT
- - - - 14 F2 VSS S
- - - - 15 F3 VDD S
FSMC_A0, I2C2_SDA,
- - - 10 16 E2 PF0 I/O FT
EVENTOUT
FSMC_A1, I2C2_SCL,
- - - 11 17 H3 PF1 I/O FT
EVENTOUT
FSMC_A2, I2C2_SMBA,
- - - 12 18 H2 PF2 I/O FT
EVENTOUT
(4)
- - - 13 19 J2 PF3 I/O FT FSMC_A3, EVENTOUT ADC3_IN9
44/178 DocID15818 Rev 11

Table 8. STM32F20x pin and ball definitions (continued)

Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
- - - 14 20 J3 PF4 I/O FT (4) FSMC_A4, EVENTOUT ADC3_IN14

- - - 15 21 K3 PF5 I/O FT (4)
FSMC_A5, EVENTOUT ADC3_IN15
- H9 10 16 22 G2 VSS S
- - 11 17 23 G3 VDD S
(4) TIM10_CH1, FSMC_NIORD,

- - - 18 24 K2 PF6 I/O FT ADC3_IN4
EVENTOUT
(4) TIM11_CH1,FSMC_NREG,
- - - 19 25 K1 PF7 I/O FT ADC3_IN5
EVENTOUT
(4) TIM13_CH1,
- - - 20 26 L3 PF8 I/O FT ADC3_IN6
FSMC_NIOWR, EVENTOUT
(4) TIM14_CH1, FSMC_CD,

- - - 21 27 L2 PF9 I/O FT ADC3_IN7
EVENTOUT
(4)
- - - 22 28 L1 PF10 I/O FT FSMC_INTR, EVENTOUT ADC3_IN8
PH0/OSC_IN
5 E9 12 23 29 G1 I/O FT EVENTOUT OSC_IN(4)
(PH0)
PH1/OSC_OUT
6 F9 13 24 30 H1 I/O FT EVENTOUT OSC_OUT(4)
(PH1)
7 E8 14 25 31 J1 NRST I/O
(4) OTG_HS_ULPI_STP, ADC123_

8 G9 15 26 32 M2 PC0 I/O FT
EVENTOUT IN10
(4) ADC123_
9 F8 16 27 33 M3 PC1 I/O FT ETH_MDC, EVENTOUT
IN11
SPI2_MISO,
(4) ADC123_
10 D7 17 28 34 M4 PC2 I/O FT OTG_HS_ULPI_DIR,
IN12
SPI2_MOSI, I2S2_SD,
(4) OTG_HS_ULPI_NXT, ADC123_
11 G8 18 29 35 M5 PC3 I/O FT
ETH_MII_TX_CLK, IN13
EVENTOUT
- - 19 30 36 - VDD S
12 - 20 31 37 M1 VSSA S
- - - - - N1 VREF- S
- F7 21 32 38 P1 VREF+ S
DocID15818 Rev 11 45/178

177

Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
13 - 22 33 39 R1 VDDA S
USART2_CTS, UART4_TX,
ETH_MII_CRS,
PA0-WKUP ADC123_IN0,
14 E7 23 34 40 N3 I/O FT (4)(5) TIM2_CH1_ETR,
(PA0) WKUP
TIM5_CH1, TIM8_ETR,
EVENTOUT
USART2_RTS, UART4_RX,
ETH_RMII_REF_CLK,
(4)
15 H8 24 35 41 N2 PA1 I/O FT ETH_MII_RX_CLK, ADC123_IN1
TIM5_CH2, TIM2_CH2,
EVENTOUT
USART2_TX,TIM5_CH3,
(4)
16 J9 25 36 42 P2 PA2 I/O FT TIM9_CH1, TIM2_CH3, ADC123_IN2
ETH_MDIO, EVENTOUT
- - - - 43 F4 PH2 I/O FT ETH_MII_CRS, EVENTOUT
- - - - 44 G4 PH3 I/O FT ETH_MII_COL, EVENTOUT
I2C2_SCL,
- - - - 45 H4 PH4 I/O FT OTG_HS_ULPI_NXT,
EVENTOUT
- - - - 46 J4 PH5 I/O FT I2C2_SDA, EVENTOUT
USART2_RX, TIM5_CH4,
(4) TIM9_CH2, TIM2_CH4,
17 G7 26 37 47 R2 PA3 I/O FT ADC123_IN3
OTG_HS_ULPI_D0,
ETH_MII_COL, EVENTOUT
18 F1 27 38 48 - VSS S
H7 L4 REGOFF I/O
19 E1 28 39 49 K4 VDD S
SPI1_NSS, SPI3_NSS,
USART2_CK,
(4) ADC12_IN4,
20 J8 29 40 50 N4 PA4 I/O TTa DCMI_HSYNC,
DAC_OUT1
OTG_HS_SOF, I2S3_WS,
EVENTOUT
SPI1_SCK,
(4) OTG_HS_ULPI_CK, ADC12_IN5,
21 H6 30 41 51 P4 PA5 I/O TTa
TIM2_CH1_ETR, DAC_OUT2
TIM8_CH1N, EVENTOUT
46/178 DocID15818 Rev 11


Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
SPI1_MISO, TIM8_BKIN,
(4) TIM13_CH1, DCMI_PIXCLK,
22 H5 31 42 52 P3 PA6 I/O FT ADC12_IN6
TIM3_CH1, TIM1_BKIN,
EVENTOUT
SPI1_MOSI, TIM8_CH1N,
TIM14_CH1, TIM3_CH2,
(4) ETH_MII_RX_DV,
23 J7 32 43 53 R3 PA7 I/O FT ADC12_IN7
TIM1_CH1N,
ETH_RMII_CRS_DV,
EVENTOUT
ETH_RMII_RXD0,
(4)
24 H4 33 44 54 N5 PC4 I/O FT ETH_MII_RXD0, ADC12_IN14
EVENTOUT
ETH_RMII_RXD1,
(4)
25 G3 34 45 55 P5 PC5 I/O FT ETH_MII_RXD1, ADC12_IN15
EVENTOUT
TIM3_CH3, TIM8_CH2N,
(4) OTG_HS_ULPI_D1,
26 J6 35 46 56 R5 PB0 I/O FT ADC12_IN8
ETH_MII_RXD2,
TIM1_CH2N, EVENTOUT
TIM3_CH4, TIM8_CH3N,
(4) OTG_HS_ULPI_D2,
27 J5 36 47 57 R4 PB1 I/O FT ADC12_IN9
ETH_MII_RXD3,
TIM1_CH3N, EVENTOUT
28 J4 37 48 58 M6 PB2/BOOT1 (PB2) I/O FT EVENTOUT
- - - 49 59 R6 PF11 I/O FT DCMI_D12, EVENTOUT
- - - 50 60 P6 PF12 I/O FT FSMC_A6, EVENTOUT
- - - 51 61 M8 VSS S
- - - 52 62 N8 VDD S
- - - 53 63 N6 PF13 I/O FT FSMC_A7, EVENTOUT
- - - 54 64 R7 PF14 I/O FT FSMC_A8, EVENTOUT
- - - 55 65 P7 PF15 I/O FT FSMC_A9, EVENTOUT
- - - 56 66 N7 PG0 I/O FT FSMC_A10, EVENTOUT
- - - 57 67 M7 PG1 I/O FT FSMC_A11, EVENTOUT
DocID15818 Rev 11 47/178

177

Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
FSMC_D4,TIM1_ETR,
- - 38 58 68 R8 PE7 I/O FT
EVENTOUT
FSMC_D5,TIM1_CH1N,
- - 39 59 69 P8 PE8 I/O FT
EVENTOUT
FSMC_D6,TIM1_CH1,
- - 40 60 70 P9 PE9 I/O FT
EVENTOUT
- - - 61 71 M9 VSS S
- - - 62 72 N9 VDD S
FSMC_D7,TIM1_CH2N,
- - 41 63 73 R9 PE10 I/O FT
EVENTOUT
FSMC_D8,TIM1_CH2,
- - 42 64 74 P10 PE11 I/O FT
EVENTOUT
FSMC_D9,TIM1_CH3N,
- - 43 65 75 R10 PE12 I/O FT
EVENTOUT
FSMC_D10,TIM1_CH3,
- - 44 66 76 N11 PE13 I/O FT
EVENTOUT
FSMC_D11,TIM1_CH4,
- - 45 67 77 P11 PE14 I/O FT
EVENTOUT
FSMC_D12,TIM1_BKIN,
- - 46 68 78 R11 PE15 I/O FT
EVENTOUT
SPI2_SCK, I2S2_SCK,
I2C2_SCL,USART3_TX,OT
29 H3 47 69 79 R12 PB10 I/O FT G_HS_ULPI_D3,ETH_MII_R
X_ER,TIM2_CH3,
EVENTOUT
I2C2_SDA, USART3_RX,
OTG_HS_ULPI_D4,
30 J2 48 70 80 R13 PB11 I/O FT ETH_RMII_TX_EN,
ETH_MII_TX_EN,
TIM2_CH4, EVENTOUT
31 J3 49 71 81 M10 VCAP_1 S
32 - 50 72 82 N10 VDD S
I2C2_SMBA, TIM12_CH1,
- - - - 83 M11 PH6 I/O FT ETH_MII_RXD2,
EVENTOUT
48/178 DocID15818 Rev 11


Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
I2C3_SCL, ETH_MII_RXD3,
- - - - 84 N12 PH7 I/O FT
EVENTOUT
I2C3_SDA, DCMI_HSYNC,
- - - - 85 M12 PH8 I/O FT
EVENTOUT
I2C3_SMBA, TIM12_CH2,
- - - - 86 M13 PH9 I/O FT
DCMI_D0, EVENTOUT
TIM5_CH1, DCMI_D1,
- - - - 87 L13 PH10 I/O FT
EVENTOUT
TIM5_CH2, DCMI_D2,
- - - - 88 L12 PH11 I/O FT
EVENTOUT
TIM5_CH3, DCMI_D3,
- - - - 89 K12 PH12 I/O FT
EVENTOUT
- - - - 90 H12 VSS S
- - - - 91 J12 VDD S
SPI2_NSS, I2S2_WS,
I2C2_SMBA, USART3_CK,
TIM1_BKIN, CAN2_RX,
33 J1 51 73 92 P12 PB12 I/O FT OTG_HS_ULPI_D5,
ETH_RMII_TXD0,
ETH_MII_TXD0,
OTG_HS_ID, EVENTOUT
SPI2_SCK, I2S2_SCK,
USART3_CTS, TIM1_CH1N,
CAN2_TX, OTG_HS_
34 H2 52 74 93 P13 PB13 I/O FT
OTG_HS_ULPI_D6, VBUS
ETH_RMII_TXD1,
SPI2_MISO, TIM1_CH2N,
TIM12_CH1, OTG_HS_DM
35 H1 53 75 94 R14 PB14 I/O FT
USART3_RTS, TIM8_CH2N,
EVENTOUT
SPI2_MOSI, I2S2_SD,
TIM1_CH3N, TIM8_CH3N,
36 G1 54 76 95 R15 PB15 I/O FT
TIM12_CH2, OTG_HS_DP,
RTC_50Hz, EVENTOUT
FSMC_D13, USART3_TX,
- - 55 77 96 P15 PD8 I/O FT
EVENTOUT
DocID15818 Rev 11 49/178

177

Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
FSMC_D14, USART3_RX,
- - 56 78 97 P14 PD9 I/O FT
EVENTOUT
FSMC_D15, USART3_CK,
- - 57 79 98 N15 PD10 I/O FT
EVENTOUT
FSMC_A16,USART3_CTS,
- - 58 80 99 N14 PD11 I/O FT
EVENTOUT
FSMC_A17,TIM4_CH1,
- - 59 81 100 N13 PD12 I/O FT
USART3_RTS, EVENTOUT
FSMC_A18,TIM4_CH2,
- - 60 82 101 M15 PD13 I/O FT
EVENTOUT
- - - 83 102 - VSS S
- - - 84 103 J13 VDD S
FSMC_D0,TIM4_CH3,
- - 61 85 104 M14 PD14 I/O FT
EVENTOUT
FSMC_D1,TIM4_CH4,
- - 62 86 105 L14 PD15 I/O FT
EVENTOUT
- - - 87 106 L15 PG2 I/O FT FSMC_A12, EVENTOUT
- - - 88 107 K15 PG3 I/O FT FSMC_A13, EVENTOUT
- - - 91 110 J15 PG6 I/O FT FSMC_INT2, EVENTOUT
FSMC_INT3 ,USART6_CK,
- - - 92 111 J14 PG7 I/O FT
EVENTOUT
USART6_RTS,
- - - 93 112 H14 PG8 I/O FT ETH_PPS_OUT,
EVENTOUT
- - - 94 113 G12 VSS S
- - - 95 114 H13 VDD S
I2S2_MCK, TIM8_CH1,
SDIO_D6, USART6_TX,
37 G2 63 96 115 H15 PC6 I/O FT
DCMI_D0, TIM3_CH1,
EVENTOUT
50/178 DocID15818 Rev 11


Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
I2S3_MCK, TIM8_CH2,
SDIO_D7, USART6_RX,
38 F2 64 97 116 G15 PC7 I/O FT
DCMI_D1, TIM3_CH2,
EVENTOUT
TIM8_CH3,SDIO_D0,
39 F3 65 98 117 G14 PC8 I/O FT TIM3_CH3, USART6_CK,
DCMI_D2, EVENTOUT
I2S2_CKIN, I2S3_CKIN,
MCO2, TIM8_CH4,
40 D1 66 99 118 F14 PC9 I/O FT SDIO_D1, I2C3_SDA,
DCMI_D3, TIM3_CH4,
EVENTOUT
MCO1, USART1_CK,
41 E2 67 100 119 F15 PA8 I/O FT TIM1_CH1, I2C3_SCL,
OTG_FS_SOF, EVENTOUT
USART1_TX, TIM1_CH2,
OTG_FS_
42 E3 68 101 120 E15 PA9 I/O FT I2C3_SMBA, DCMI_D0,
VBUS
EVENTOUT
43 D3 69 102 121 D15 PA10 I/O FT OTG_FS_ID,DCMI_D1,
EVENTOUT
USART1_CTS, CAN1_RX,
44 D2 70 103 122 C15 PA11 I/O FT TIM1_CH4,OTG_FS_DM,
EVENTOUT
USART1_RTS, CAN1_TX,
45 C1 71 104 123 B15 PA12 I/O FT TIM1_ETR, OTG_FS_DP,
EVENTOUT
PA13
46 B2 72 105 124 A15 I/O FT JTMS-SWDIO, EVENTOUT
(JTMS-SWDIO)
47 C2 73 106 125 F13 VCAP_2 S
- B1 74 107 126 F12 VSS S
48 A8 75 108 127 G13 VDD S
TIM8_CH1N, CAN1_TX,
- - - - 128 E12 PH13 I/O FT
EVENTOUT
TIM8_CH2N, DCMI_D4,
- - - - 129 E13 PH14 I/O FT
EVENTOUT
DocID15818 Rev 11 51/178

177

Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
TIM8_CH3N, DCMI_D11,
- - - - 130 D13 PH15 I/O FT
EVENTOUT
TIM5_CH4, SPI2_NSS,
- - - - 131 E14 PI0 I/O FT I2S2_WS, DCMI_D13,
EVENTOUT
SPI2_SCK, I2S2_SCK,
- - - - 132 D14 PI1 I/O FT
DCMI_D8, EVENTOUT
TIM8_CH4 ,SPI2_MISO,
- - - - 133 C14 PI2 I/O FT
DCMI_D9, EVENTOUT
TIM8_ETR, SPI2_MOSI,
- - - - 134 C13 PI3 I/O FT I2S2_SD, DCMI_D10,
EVENTOUT
- - - - 135 D9 VSS S
- - - - 136 C9 VDD S
PA14
49 A1 76 109 137 A14 I/O FT JTCK-SWCLK, EVENTOUT
(JTCK-SWCLK)
JTDI, SPI3_NSS,
50 A2 77 110 138 A13 PA15 (JTDI) I/O FT I2S3_WS,TIM2_CH1_ETR,
SPI1_NSS, EVENTOUT
SPI3_SCK, I2S3_SCK,
UART4_TX, SDIO_D2,
51 B3 78 111 139 B14 PC10 I/O FT
DCMI_D8, USART3_TX,
EVENTOUT
UART4_RX, SPI3_MISO,
SDIO_D3,
52 C3 79 112 140 B13 PC11 I/O FT
DCMI_D4,USART3_RX,
EVENTOUT
UART5_TX, SDIO_CK,
DCMI_D9, SPI3_MOSI,
53 A3 80 113 141 A12 PC12 I/O FT
I2S3_SD, USART3_CK,
EVENTOUT
FSMC_D2,CAN1_RX,
- - 81 114 142 B12 PD0 I/O FT
EVENTOUT
FSMC_D3, CAN1_TX,
- - 82 115 143 C12 PD1 I/O FT
EVENTOUT
52/178 DocID15818 Rev 11


Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
TIM3_ETR,UART5_RX,
54 C7 83 116 144 D12 PD2 I/O FT SDIO_CMD, DCMI_D11,
EVENTOUT
FSMC_CLK,USART2_CTS,
- - 84 117 145 D11 PD3 I/O FT
EVENTOUT
FSMC_NOE, USART2_RTS,
- - 85 118 146 D10 PD4 I/O FT
EVENTOUT
FSMC_NWE,USART2_TX,
- - 86 119 147 C11 PD5 I/O FT
EVENTOUT
- - - 120 148 D8 VSS S
- - - 121 149 C8 VDD S
FSMC_NWAIT,
- - 87 122 150 B11 PD6 I/O FT
USART2_RX, EVENTOUT
USART2_CK,FSMC_NE1,
- - 88 123 151 A11 PD7 I/O FT
FSMC_NCE2, EVENTOUT
USART6_RX,
- - - 124 152 C10 PG9 I/O FT FSMC_NE2,FSMC_NCE3,
EVENTOUT
FSMC_NCE4_1,
- - - 125 153 B10 PG10 I/O FT
FSMC_NE3, EVENTOUT
FSMC_NCE4_2,
ETH_MII_TX_EN ,
- - - 126 154 B9 PG11 I/O FT
ETH _RMII_TX_EN,
EVENTOUT
FSMC_NE4, USART6_RTS,
- - - 127 155 B8 PG12 I/O FT
EVENTOUT
FSMC_A24, USART6_CTS,
ETH_MII_TXD0,
- - - 128 156 A8 PG13 I/O FT
ETH_RMII_TXD0,
EVENTOUT
FSMC_A25, USART6_TX,
ETH_MII_TXD1,
- - - 129 157 A7 PG14 I/O FT
ETH_RMII_TXD1,
EVENTOUT
- - - 130 158 D7 VSS S
DocID15818 Rev 11 53/178

177

Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
- - - 131 159 C7 VDD S

USART6_CTS, DCMI_D13,
- - - 132 160 B7 PG15 I/O FT
EVENTOUT
JTDO/ TRACESWO,
PB3 SPI3_SCK, I2S3_SCK,
55 A4 89 133 161 A10 I/O FT
(JTDO/TRACESWO) TIM2_CH2, SPI1_SCK,
EVENTOUT
NJTRST, SPI3_MISO,
56 B4 90 134 162 A9 PB4 I/O FT TIM3_CH1, SPI1_MISO,
EVENTOUT
I2C1_SMBA, CAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT, TIM3_CH2,
57 A5 91 135 163 A6 PB5 I/O FT
SPI1_MOSI, SPI3_MOSI,
DCMI_D10, I2S3_SD,
EVENTOUT
I2C1_SCL,, TIM4_CH1,
CAN2_TX,
58 B5 92 136 164 B6 PB6 I/O FT
DCMI_D5,USART1_TX,
EVENTOUT
I2C1_SDA, FSMC_NL(6),
DCMI_VSYNC,
59 A6 93 137 165 B5 PB7 I/O FT
EVENTOUT
60 B6 94 138 166 D6 BOOT0 I B VPP
TIM4_CH3,SDIO_D4,
TIM10_CH1, DCMI_D6,
61 B7 95 139 167 A5 PB8 I/O FT
ETH_MII_TXD3, I2C1_SCL,
CAN1_RX, EVENTOUT
SPI2_NSS, I2S2_WS,
TIM4_CH4, TIM11_CH1,
62 A7 96 140 168 B4 PB9 I/O FT SDIO_D5, DCMI_D7,
I2C1_SDA, CAN1_TX,
EVENTOUT
TIM4_ETR, FSMC_NBL0,
- - 97 141 169 A4 PE0 I/O FT
DCMI_D2, EVENTOUT
54/178 DocID15818 Rev 11


Pins
I/O structure
Pin name
Pin type
WLCSP64+2
UFBGA176 Additional
Note
LQFP100
LQFP144
LQFP176
LQFP64

functions
reset)(1)
FSMC_NBL1, DCMI_D3,
- - 98 142 170 A3 PE1 I/O FT
EVENTOUT
- - - - - D5 VSS S
63 D8 - - - - VSS S
- - 99 143 171 C6 RFU (7)
64 D9 100 144 172 C5 VDD S

TIM8_BKIN, DCMI_D5,
- - - - 173 D4 PI4 I/O FT
EVENTOUT
TIM8_CH1, DCMI_VSYNC,
- - - - 174 C4 PI5 I/O FT
EVENTOUT
TIM8_CH2, DCMI_D6,
- - - - 175 C3 PI6 I/O FT
EVENTOUT
TIM8_CH3, DCMI_D7,
- - - - 176 C2 PI7 I/O FT
EVENTOUT
- C8 - - - - IRROFF I/O
1. Function availability depends on the chosen device.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a
maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics
website: www.st.com.
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
5. If the device is delivered in an UFBGA176 package and if the REGOFF pin is set to VDD (Regulator OFF), then PA0 is
used as an internal Reset (active low).
6. FSMC_NL pin is also named FSMC_NADV on memory devices.
Table 9. FSMC pin definition

FSMC
Pins LQFP100
NOR/PSRAM/S
CF NOR/PSRAM Mux NAND 16 bit
RAM
PE2 A23 A23 Yes

PE3 A19 A19 Yes
DocID15818 Rev 11 55/178

177
Table 9. FSMC pin definition (continued)

FSMC
Pins LQFP100
NOR/PSRAM/S
RAM
PE4 A20 A20 Yes

PE5 A21 A21 Yes
PE6 A22 A22 Yes
PF0 A0 A0 -
PF1 A1 A1 -
PF2 A2 A2 -
PF3 A3 A3 -
PF4 A4 A4 -
PF5 A5 A5 -
PF6 NIORD -
PF7 NREG -
PF8 NIOWR -
PF9 CD -
PF10 INTR -
PF12 A6 A6 -
PF13 A7 A7 -
PF14 A8 A8 -
PF15 A9 A9 -
PG0 A10 A10 -
PG1 A11 -
PE7 D4 D4 DA4 D4 Yes
PD8 D13 D13 DA13 D13 Yes
PD11 A16 A16 CLE Yes
56/178 DocID15818 Rev 11

Table 9. FSMC pin definition (continued)

FSMC
Pins LQFP100
NOR/PSRAM/S
RAM
PD12 A17 A17 ALE Yes

PD13 A18 A18 Yes
PG2 A12 -
PG3 A13 -
PG4 A14 -
PG5 A15 -
PG6 INT2 -
PG7 INT3 -
PD3 CLK CLK Yes
PD4 NOE NOE NOE NOE Yes
PD5 NWE NWE NWE NWE Yes
PD6 NWAIT NWAIT NWAIT NWAIT Yes
PD7 NE1 NE1 NCE2 Yes
PG9 NE2 NE2 NCE3 -
PG10 NCE4_1 NE3 NE3 -
PG11 NCE4_2 -
PG12 NE4 NE4 -
PG13 A24 A24 -
PG14 A25 A25 -
PB7 NADV NADV Yes
PE0 NBL0 NBL0 Yes
PE1 NBL1 NBL1 Yes
DocID15818 Rev 11 57/178

177
58/178
Pinouts and pin description

Table 10. Alternate function mapping
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13
Port AF014 AF15
UART4/5/ CAN1/CAN2/ FSMC/SDIO/
SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 I2C1/I2C2/I2C3 SPI1/SPI2/I2S2 SPI3/I2S3 USART1/2/3 OTG_FS/ OTG_HS ETH DCMI
USART6 TIM12/13/14 OTG_HS
PA0-WKUP TIM2_CH1_ETR TIM 5_CH1 TIM8_ETR USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT
ETH_MII
_RX_CLK
PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX EVENTOUT
ETH_RMII
_REF_CLK
PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX ETH_MDIO EVENTOUT
PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX OTG_HS_ULPI_D0 ETH _MII_COL EVENTOUT
SPI3_NSS
PA4 SPI1_NSS USART2_CK OTG_HS_SOF DCMI_HSYNC EVENTOUT
I2S3_WS
OTG_HS_ULPI_C
PA5 TIM2_CH1_ETR TIM8_CH1N SPI1_SCK EVENTOUT
K
PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 DCMI_PIXCK EVENTOUT

ETH_MII _RX_DV
Port A PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI TIM14_CH1 ETH_RMII EVENTOUT
_CRS_DV
PA8 MCO1 TIM1_CH1 I2C3_SCL USART1_CK OTG_FS_SOF EVENTOUT
PA9 TIM1_CH2 I2C3_SMBA USART1_TX DCMI_D0 EVENTOUT

DocID15818 Rev 11
PA10 TIM1_CH3 USART1_RX OTG_FS_ID DCMI_D1 EVENTOUT
PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT
PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT
JTMS-
PA13 EVENTOUT
SWDIO
JTCK-
PA14 EVENTOUT
SWCLK
TIM 2_CH1 SPI3_NSS
PA15 JTDI SPI1_NSS EVENTOUT
TIM 2_ETR I2S3_WS
STM32F20xxx
Table 10. Alternate function mapping (continued)
STM32F20xxx
Port AF014 AF15
PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_D1 ETH _MII_RXD2 EVENTOUT
PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_D2 ETH _MII_RXD3 EVENTOUT
PB2 EVENTOUT
JTDO/ SPI3_SCK
PB3 TIM2_CH2 SPI1_SCK EVENTOUT
TRACESWO I2S3_SCK
PB4 JTRST TIM3_CH1 SPI1_MISO SPI3_MISO EVENTOUT
SPI3_MOSI
PB5 TIM3_CH2 I2C1_SMBA SPI1_MOSI CAN2_RX OTG_HS_ULPI_D7 ETH _PPS_OUT DCMI_D10 EVENTOUT
I2S3_SD
PB6 TIM4_CH1 I2C1_SCL USART1_TX CAN2_TX DCMI_D5 EVENTOUT
PB7 TIM4_CH2 I2C1_SDA USART1_RX FSMC_NL DCMI_VSYNC EVENTOUT
Port B PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL CAN1_RX ETH _MII_TXD3 SDIO_D4 DCMI_D6 EVENTOUT
SPI2_NSS
PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA CAN1_TX SDIO_D5 DCMI_D7 EVENTOUT
I2S2_WS
SPI2_SCK
PB10 TIM2_CH3 I2C2_SCL USART3_TX OTG_HS_ULPI_D3 ETH_ MII_RX_ER EVENTOUT
I2S2_SCK
ETH _MII_TX_EN
DocID15818 Rev 11
PB11 TIM2_CH4 I2C2_SDA USART3_RX OTG_HS_ULPI_D4 ETH EVENTOUT

_RMII_TX_EN
SPI2_NSS ETH _MII_TXD0
PB12 TIM1_BKIN I2C2_SMBA USART3_CK CAN2_RX OTG_HS_ULPI_D5 OTG_HS_ID EVENTOUT
I2S2_WS ETH _RMII_TXD0
SPI2_SCK ETH _MII_TXD1
PB13 TIM1_CH1N USART3_CTS CAN2_TX OTG_HS_ULPI_D6 EVENTOUT
I2S2_SCK ETH _RMII_TXD1
PB14 TIM1_CH2N TIM8_CH2N SPI2_MISO USART3_RTS TIM12_CH1 OTG_HS_DM EVENTOUT
SPI2_MOSI
PB15 RTC_50Hz TIM1_CH3N TIM8_CH3N TIM12_CH2 OTG_HS_DP EVENTOUT
I2S2_SD

59/178
60/178

Port AF014 AF15
OTG_HS_ULPI_
PC0 EVENTOUT
STP
PC1 ETH_MDC EVENTOUT
OTG_HS_ULPI_
PC2 SPI2_MISO ETH _MII_TXD2 EVENTOUT
DIR
OTG_HS_ULPI_ ETH
PC3 SPI2_MOSI EVENTOUT
NXT _MII_TX_CLK
ETH_MII_RXD0
PC4 EVENTOUT
ETH_RMII_RXD0
ETH _MII_RXD1
PC5 EVENTOUT
ETH _RMII_RXD1
PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK USART6_TX SDIO_D6 DCMI_D0 EVENTOUT
PC7 TIM3_CH2 TIM8_CH2 I2S3_MCK USART6_RX SDIO_D7 DCMI_D1 EVENTOUT

Port C
PC8 TIM3_CH3 TIM8_CH3 USART6_CK SDIO_D0 DCMI_D2 EVENTOUT
PC9 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S2_CKIN I2S3_CKIN SDIO_D1 DCMI_D3 EVENTOUT
SPI3_SCK
PC10 USART3_TX UART4_TX SDIO_D2 DCMI_D8 EVENTOUT
I2S3_SCK
PC11 SPI3_MISO USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT
DocID15818 Rev 11
SPI3_MOSI
PC12 USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT
I2S3_SD
PC13 EVENTOUT
PC14-
EVENTOUT
OSC32_IN
PC15-
OSC32_OU EVENTOUT
T
STM32F20xxx
STM32F20xxx
Port AF014 AF15
PD0 CAN1_RX FSMC_D2 EVENTOUT
PD1 CAN1_TX FSMC_D3 EVENTOUT
PD2 TIM3_ETR UART5_RX SDIO_CMD DCMI_D11 EVENTOUT
PD3 USART2_CTS FSMC_CLK EVENTOUT
PD4 USART2_RTS FSMC_NOE EVENTOUT
PD5 USART2_TX FSMC_NWE EVENTOUT
PD6 USART2_RX FSMC_NWAIT EVENTOUT
FSMC_NE1/
PD7 USART2_CK EVENTOUT
FSMC_NCE2
Port D
PD8 USART3_TX FSMC_D13 EVENTOUT
PD9 USART3_RX FSMC_D14 EVENTOUT
PD10 USART3_CK FSMC_D15 EVENTOUT
PD11 USART3_CTS FSMC_A16 EVENTOUT

DocID15818 Rev 11
PD12 TIM4_CH1 USART3_RTS FSMC_A17 EVENTOUT
PD13 TIM4_CH2 FSMC_A18 EVENTOUT
PD14 TIM4_CH3 FSMC_D0 EVENTOUT
PD15 TIM4_CH4 FSMC_D1 EVENTOUT
PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 EVENTOUT
PE1 FSMC_NBL1 DCMI_D3 EVENTOUT
PE2 TRACECLK ETH _MII_TXD3 FSMC_A23 EVENTOUT
PE3 TRACED0 FSMC_A19 EVENTOUT
PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT
PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT
PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 EVENTOUT

PE7 TIM1_ETR FSMC_D4 EVENTOUT
Port E
PE8 TIM1_CH1N FSMC_D5 EVENTOUT
PE9 TIM1_CH1 FSMC_D6 EVENTOUT

61/178
PE15 TIM1_BKIN FSMC_D12 EVENTOUT

62/178

Port AF014 AF15
PF0 I2C2_SDA FSMC_A0 EVENTOUT
PF1 I2C2_SCL FSMC_A1 EVENTOUT
PF2 I2C2_SMBA FSMC_A2 EVENTOUT
PF3 FSMC_A3 EVENTOUT
PF6 TIM10_CH1 FSMC_NIORD EVENTOUT
PF7 TIM11_CH1 FSMC_NREG EVENTOUT

Port F
PF8 TIM13_CH1 FSMC_NIOWR EVENTOUT
PF9 TIM14_CH1 FSMC_CD EVENTOUT
PF10 FSMC_INTR EVENTOUT
PF11 DCMI_D12 EVENTOUT

DocID15818 Rev 11
PG0 FSMC_A10 EVENTOUT
PG6 FSMC_INT2 EVENTOUT
PG7 USART6_CK FSMC_INT3 EVENTOUT
Port G PG8 USART6_RTS ETH _PPS_OUT EVENTOUT

FSMC_NE2/
PG9 USART6_RX EVENTOUT
FSMC_NCE3
FSMC_NCE4_1/
PG10 EVENTOUT
FSMC_NE3
ETH _MII_TX_EN
PG11 ETH FSMC_NCE4_2 EVENTOUT
STM32F20xxx
_RMII_TX_EN
PG12 USART6_RTS FSMC_NE4 EVENTOUT

ETH _MII_TXD0
PG13 UART6_CTS FSMC_A24 EVENTOUT
ETH _RMII_TXD0
ETH _MII_TXD1
PG14 USART6_TX FSMC_A25 EVENTOUT
ETH _RMII_TXD1
PG15 USART6_CTS DCMI_D13 EVENTOUT

STM32F20xxx
Port AF014 AF15
PH0 -
EVENTOUT
OSC_IN
PH1 -
EVENTOUT
OSC_OUT
PH2 ETH _MII_CRS EVENTOUT
PH3 ETH _MII_COL EVENTOUT
OTG_HS_ULPI_N
PH4 I2C2_SCL EVENTOUT
XT
PH5 I2C2_SDA EVENTOUT
PH6 I2C2_SMBA TIM12_CH1 ETH _MII_RXD2 EVENTOUT
PH7 I2C3_SCL ETH _MII_RXD3 EVENTOUT

Port H
PH8 I2C3_SDA DCMI_HSYNC EVENTOUT
PH9 I2C3_SMBA TIM12_CH2 DCMI_D0 EVENTOUT
PH10 TIM5_CH1 DCMI_D1 EVENTOUT

DocID15818 Rev 11
PH13 TIM8_CH1N CAN1_TX EVENTOUT
PH14 TIM8_CH2N DCMI_D4 EVENTOUT
PH15 TIM8_CH3N DCMI_D11 EVENTOUT

SPI2_NSS
PI0 TIM5_CH4 DCMI_D13 EVENTOUT
I2S2_WS
SPI2_SCK
PI1 DCMI_D8 EVENTOUT
I2S2_SCK
PI2 TIM8_CH4 SPI2_MISO DCMI_D9 EVENTOUT
SPI2_MOSI
PI3 TIM8_ETR DCMI_D10 EVENTOUT
I2S2_SD
PI4 TIM8_BKIN DCMI_D5 EVENTOUT
PI5 TIM8_CH1 DCMI_VSYNC EVENTOUT

Port I

PI8 EVENTOUT
PI9 CAN1_RX EVENTOUT
PI10 ETH _MII_RX_ER EVENTOUT
OTG_HS_ULPI_
PI11 EVENTOUT
DIR
63/178
Memory mapping STM32F20xxx
5 Memory mapping
The memory map is shown in Figure 16.
64/178 DocID15818 Rev 11

STM32F20xxx Memory mapping
Figure 16. Memory map
Reserved 0xA000 1000 - 0xBFFF FFFF

FSMC control register 0xA000 0000 - 0xA000 0FFF
FSMC bank4 PC Card 0x9000 0000 - 0x9FFF FFFF
FSMC bank3 NAND (NAND2) 0x8000 0000 - 0x8FFF FFFF
FSMC bank2 NAND (NAND1) 0x7000 0000 - 0x7FFF FFFF
FSMC bank1 NOR/PSRAM 4 0x6C00 0000 - 0x6FFF FFFF
FSMC bank1 NOR/PSRAM 3 0x6800 0000 - 0x6BFF FFFF
FSMC bank1 NOR/PSRAM 2 0x6400 0000 - 0x67FF FFFF
FSMC bank1 NOR/PSRAM 1 0x6000 0000 - 0x63FF FFFF
Reserved 0x5006 1000 - 0x5FFF FFFF
RNG 0x5006 0800 - 0x5006 0FFF
Reserved 0x5005 0400 - 0x5006 7FFF
DCMI 0x5005 0000 - 0x5005 03FF
Reserved 0x5004 0000 - 0x5004 0FFF
USB OTG FS 0x5000 0000 - 0x5003 FFFF
USB OTG HS 0x4004 0000 - 0x4007 FFFF
Reserved 0x4002 9400 - 0x4003 FFFF
ETHERNET 0x4002 8000 - 0x4002 93FF
Reserved 0x4002 6800 - 0x4002 7FFF
DMA2 0x4002 6400 - 0x4002 67FF
DMA1 0x4002 6000 - 0x4002 63FF
Reserved 0x4002 5000 - 0x4002 5FFF
BKPSRAM 0x4002 4000 - 0x4002 4FFF
Flash interface 0x4002 3C00 - 0x4002 3FFF
Reset clock controller (RCC) 0x4002 3800 - 0x4002 3BFF
Reserved 0x4002 3400 - 0x4002 37FF
CRC 0x4002 3000 - 0x4002 33FF
Reserved 0x4002 2400 - 0x4002 2FFF
Port I 0x4002 2000 - 0x4002 23FF
Port H 0x4002 1C00 - 0x4002 1FFF
Port G 0x4002 1800 - 0x4002 1BFF
Port F 0x4002 1400 - 0x4002 17FF
Port E 0x4002 1000 - 0x4002 13FF
Port D 0x4002 0C00 - 0x4002 0FFF
Port C 0x4002 0800 - 0x4002 0BFF
Port B 0x4002 0400 - 0x4002 07FF
Port A 0x4002 0000 - 0x4002 03FF
Reserved 0x4001 4C00 - 0x4001 FFFF
TIM11 0x4001 4800 - 0x4001 4BFF
TIM10 0x4001 4400 - 0x4001 47FF
TIM9 0x4001 4000 - 0x4001 43FF
EXTI 0x4001 3C00 - 0x4001 3FFF
SYSCFG 0x4001 3800 - 0x4001 3BFF
Reserved 0x4001 3400 - 0x4001 37FF
SPI1 0x4001 3000 - 0x4001 33FF
0xFFFF FFFF 512-Mbyte SDIO 0x4001 2C00 - 0x4001 2FFF
block 7 Reserved 0x4001 2800 - 0x4001 2BFF
Cortex-M3's Reserved 0x4001 2400 - 0x4001 27FF
internal ADC1 - ADC2 - ADC3 0x4001 2000 - 0x4001 23FF
0xE000 0000 peripherals Reserved 0x4001 1800 - 0x4001 1FFF
0xDFFF FFFF USART6 0x4001 1400 - 0x4001 17FF
512-Mbyte USART1 0x4001 1000 - 0x4001 13FF
Reserved 0x4001 0800 - 0x4001 0FFF
block 6
Not used TIM8 / PWM2 0x4001 0400 - 0x4001 07FF
TIM1 / PWM1 0x4001 0000 - 0x4001 03FF
0xC000 0000
0xBFFF FFFF Reserved 0x4000 7800 - 0x4000 FFFF
DAC1/DAC2 0x4000 7400 - 0x4000 77FF
512-Mbyte
PWR 0x4000 7000 - 0x4000 73FF
block 5
Reserved 0x4000 6C00 - 0x4000 6FFF
FSMC registers
BxCAN2 0x4000 6800 - 0x4000 6BFF
0xA000 0000 BxCAN1 0x4000 6400 - 0x4000 67FF
0x9FFF FFFF
512-Mbyte Reserved 0x4000 6000 - 0x4000 63FF
block 4 I2C3 0x4000 5C00 - 0x4000 5FFF
FSMC bank 3 I2C2 0x4000 5800 - 0x4000 5BFF
& bank4 I2C1 0x4000 5400 - 0x4000 57FF
0x8000 0000 UART5 0x4000 5000 - 0x4000 53FF
0x7FFF FFFF UART4 0x4000 4C00 - 0x4000 4FFF
512-Mbyte
USART3 0x4000 4800 - 0x4000 4BFF
block 3
USART2 0x4000 4400 - 0x4000 47FF
FSMC bank1
Reserved 0x4000 4000 - 0x4000 43FF
& bank2
0x6000 0000 SPI3/I2S3 0x4000 3C00 - 0x4000 3FFF
0x5FFF FFFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF
512-Mbyte Reserved 0x4000 3400 - 0x4000 37FF
block 2 IWDG 0x4000 3000 - 0x4000 33FF
Peripherals WWDG 0x4000 2C00 - 0x4000 2FFF
0x4000 0000 RTC & BKP registers 0x4000 2800 - 0x4000 2BFF
0x3FFF FFFF Reserved 0x4000 2400 - 0x4000 27FF
512-Mbyte TIM14 0x4000 2000 - 0x4000 23FF
block 1 TIM13 0x4000 1C00 - 0x4000 1FFF
SRAM SRAM (16 KB aliased 0x2001 C000 - 0x2001 FFFF TIM12 0x4000 1800 - 0x4000 1BFF
by bit-banding) TIM7 0x4000 1400 - 0x4000 17FF
0x2000 0000 SRAM (112 KB aliased 0x4000 1000 - 0x4000 13FF
0x1FFF FFFF 0x2000 0000 - 0x2001 BFFF TIM6
by bit-banding) TIM5 0x4000 0C00 - 0x4000 0FFF
512-Mbyte
TIM4 0x4000 0800 - 0x4000 0BFF
block 0
Reserved 0x1FFF C008 - 0x1FFF FFFF TIM3 0x4000 0400 - 0x4000 07FF
Code
Option Bytes 0x1FFF C000 - 0x1FFF C007 TIM2 0x4000 0000 - 0x4000 03FF
0x0000 0000
Reserved 0x1FFF 7A10 - 0x1FFF 7FFF
System memory + OTP 0x1FFF 0000 - 0x1FFF 7A0F
Flash 0x0800 0000 - 0x080F FFFF
Reserved 0x0001 C000 - 0x07FF FFFF
Aliased to Flash, system
memory or SRAM depending 0x0000 0000 - 0x000F FFFF
on the BOOT pins ai17615c
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177
Electrical characteristics STM32F20xxx
6 Electrical characteristics
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.8 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2Σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 17.
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 18.
Figure 17. Pin loading conditions Figure 18. Pin input voltage
MCU pin MCU pin
C = 50 pF VIN
MS19011V2 MS19010V2
66/178 DocID15818 Rev 11

STM32F20xxx Electrical characteristics
6.1.6 Power supply scheme
Figure 19. Power supply scheme
VBAT
Backup circuitry
Power switch (OSC32K,RTC,
1.8-3.6 V
Wakeup logic
Backup registers,
backup RAM)
Level shifter
OUT
IO
GP I/Os Logic
IN Kernel logic
(CPU,
VCAP_1
VCAP_2 digital
2 × 2.2 μF & RAM)
VDD
VDD
Voltage
1/2/...14/15
regulator
15 × 100 nF VSS
+ 1 × 4.7 μF 1/2/...14/15
REGOFF Flash memory

IRROFF
VDD
VDDA
VREF
VREF+
100 nF Analog
100 nF + 1 μF VREF- ADC RCs, PLL,
+ 1 μF
...
VSSA
ai17527e
1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be
placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality
of the device.
2. To connect REGOFF and IRROFF pins, refer to Section 3.16: Voltage regulator.
3. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is
OFF.
4. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
DocID15818 Rev 11 67/178

177
6.1.7 Current consumption measurement
Figure 20. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics,
Table 12: Current characteristics, and Table 13: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 11. Voltage characteristics

Symbol Ratings Min Max Unit
VDD–VSS External main supply voltage (including VDDA, VDD)(1) –0.3 4.0
Input voltage on five-volt tolerant pin(2) VSS–0.3 VDD+4 V
VIN
Input voltage on any other pin VSS–0.3 4.0
|ΔVDDx| Variations between different VDD power pins - 50
mV
|VSSX − VSS| Variations between all the different ground pins - 50
see Section 6.3.14:
Absolute maximum
VESD(HBM) Electrostatic discharge voltage (human body model)
ratings (electrical
sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed
injected current.
68/178 DocID15818 Rev 11

Table 12. Current characteristics

Symbol Ratings Max. Unit
IVDD Total current into VDD power lines (source)(1) 120

(1)
IVSS Total current out of VSS ground lines (sink) 120
Output current sunk by any I/O and control pin 25
IIO
Output current source by any I/Os and control pin 25 mA
(3)
Injected current on five-volt tolerant I/O –5/+0
IINJ(PIN) (2)
(4)
Injected current on any other pin ±5
ΣIINJ(PIN) (4) Total injected current (sum of all I/O and control pins) (5)
±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC
characteristics.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 13. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 125 °C
6.3 Operating conditions
6.3.1 General operating conditions
Table 14. General operating conditions(1)

Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency 0 120

fPCLK1 Internal APB1 clock frequency 0 30 MHz
fPCLK2 Internal APB2 clock frequency 0 60
VDD Standard operating voltage 1.8(2) 3.6 V
Analog operating voltage
1.8(2) 3.6
(ADC limited to 1 M samples) Must be the same potential as
VDDA (3) V
Analog operating voltage VDD(4)
2.4 3.6
(ADC limited to 2 M samples)
DocID15818 Rev 11 69/178

177
Table 14. General operating conditions(1) (continued)

VBAT Backup operating voltage 1.65 3.6

FT and TTa I/O TBD TBD V
VIN I/O input voltage
BOOT0 TBD TBD
VCAP1 Internal core voltage to be supplied
1.1 1.3 V
VCAP2 externally in REGOFF mode
LQFP64 - 444
WLCSP64+2 - 392
Power dissipation at TA = 85 °C for LQFP100 - 434

PD mW
suffix 6 or TA = 105 °C for suffix 7(5) LQFP144 - 500
LQFP176 - 526
UFBGA176 - 513
Ambient temperature for 6 suffix Maximum power dissipation –40 85

°C
version Low power dissipation (6)
–40 105
TA
Ambient temperature for 7 suffix Maximum power dissipation –40 105
°C
version Low power dissipation (6)
–40 125
6 suffix version –40 105
TJ Junction temperature range °C
7 suffix version –40 125
1. TBD stands for “to be defined”.
2. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when the device
operates in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16).
3. When the ADC is used, refer to Table 66: ADC characteristics.
4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and power-down operation.
5. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
6. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
70/178 DocID15818 Rev 11

Table 15. Limitations depending on the operating power supply range

Maximum Number of wait
Operating Flash states at FSMC_CLK Possible
power ADC memory maximum CPU frequency for Flash
I/O operation
supply operation access frequency synchronous memory
range frequency (fCPUmax= accesses operations
(fFlashmax) 120 MHz)(1)
– Degraded
16 MHz with speed 8-bit erase
Conversion
VDD =1.8 to no Flash (3) performance up to 30 MHz and program
time up to 7
2.1 V(2) memory wait operations
1 Msps – No I/O
state only
compensation
– Degraded
18 MHz with speed
Conversion 16-bit erase
VDD = 2.1 to no Flash
time up to 6(3) performance up to 30 MHz and program
2.4 V memory wait
1 Msps – No I/O operations
state
compensation
– Degraded
24 MHz with speed
Conversion performance 16-bit erase
VDD = 2.4 to no Flash
time up to 4(3) up to 48 MHz and program
2.7 V memory wait – I/O
2 Msps operations
state compensation
works
– up to
60 MHz
– Full-speed
30 MHz with when VDD =
Conversion operation 32-bit erase
VDD = 2.7 to no Flash 3.0 to 3.6 V
time up to 3(3) – I/O and program
3.6 V(4) memory wait – up to
2 Msps compensation operations
state 48 MHz
works
when VDD =
2.7 to 3.0 V
1. The number of wait states can be reduced by reducing the CPU frequency (see Figure 21).
3. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
4. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V.
DocID15818 Rev 11 71/178

177
Figure 21. Number of wait states versus fCPU and VDD range
Wait states vs Fcpu and VDD range
6
Number of Wait states
5
1.8 to 2.1V
2.1 to 2.4V
4
2.4 to 2.7V
2.7 to 3.6V
3
0
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
96
100
104
108
112
116
120
Fcpu (MHz)
ai18748b
1. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range and
IRROFF is set to VDD.
6.3.2 VCAP1/VCAP2 external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor to the
VCAP1/VCAP2 pins. CEXT is specified in Table 16.
Figure 22. External capacitor CEXT
ESR
R Leak
MS19044V2
1. Legend: ESR is the equivalent series resistance.
Table 16. VCAP1/VCAP2 operating conditions(1)

Symbol Parameter Conditions
CEXT Capacitance of external capacitor 2.2 µF

ESR ESR of external capacitor <2Ω
72/178 DocID15818 Rev 11

1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
6.3.3 Operating conditions at power-up / power-down (regulator ON)

Subject to general operating conditions for TA.
Table 17. Operating conditions at power-up / power-down (regulator ON)

Symbol Parameter Min Max Unit
VDD rise time rate 20 ∞

tVDD µs/V
VDD fall time rate 20 ∞
6.3.4 Operating conditions at power-up / power-down (regulator OFF)

Subject to general operating conditions for TA.
Table 18. Operating conditions at power-up / power-down (regulator OFF)

VDD rise time rate Power-up 20 ∞

tVDD
VDD fall time rate Power-down 20 ∞
VCAP_1 and VCAP_2 rise µs/V
time rate
Power-up 20 ∞
tVCAP
VCAP_1 and VCAP_2 fall
time rate
Power-down 20 ∞
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177
6.3.5 Embedded reset and power control block characteristics

The parameters given in Table 19 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 14.
Table 19. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit
PLS[2:0]=000 (rising
2.09 2.14 2.19 V
edge)
PLS[2:0]=000 (falling
1.98 2.04 2.08 V
edge)
2.23 2.30 2.37 V
edge)
2.13 2.19 2.25 V
edge)
2.39 2.45 2.51 V
edge)
2.29 2.35 2.39 V
edge)
PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 V
Programmable voltage edge) 2.44 2.51 2.56 V
VPVD
detector level selection
2.70 2.76 2.82 V
edge)
2.59 2.66 2.71 V
edge)
2.86 2.93 2.99 V
edge)
2.65 2.84 3.02 V
edge)
PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 V
2.85 2.93 2.99 V
edge)
PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 V
2.95 3.03 3.09 V
edge)
VPVDhyst(1) PVD hysteresis - 100 - mV
Power-on/power-down Falling edge 1.60 1.68 1.76 V

VPOR/PDR
reset threshold Rising edge 1.64 1.72 1.80 V
VPDRhyst(1) PDR hysteresis - 40 - mV
Brownout level 1 Falling edge 2.13 2.19 2.24 V

VBOR1
threshold Rising edge 2.23 2.29 2.33 V
74/178 DocID15818 Rev 11

Table 19. Embedded reset and power control block characteristics (continued)

VBOR2
threshold Rising edge 2.53 2.59 2.63 V

VBOR3
threshold Rising edge 2.85 2.92 2.97
(1)
VBORhyst BOR hysteresis - 100 - mV
TRSTTEMPO(1)(2) Reset temporization 0.5 1.5 3.0 ms
InRush current on
(1) voltage regulator
IRUSH - 160 200 mA
power-on (POR or
wakeup from Standby)
InRush energy on
voltage regulator VDD = 1.8 V, TA = 105 °C,
ERUSH(1) - - 5.4 µC
power-on (POR or IRUSH = 171 mA for 31 µs
wakeup from Standby)
1. Guaranteed by design, not tested in production.
2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant
when first instruction is read by the user application code.
6.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 20: Current consumption
measurement scheme.
All Run mode current consumption measurements given in this section are performed using
CoreMark code.
DocID15818 Rev 11 75/178

177
Typical and maximum current consumption

The MCU is placed under the following conditions:
• At startup, all I/O pins are configured as analog inputs by firmware.
• All peripherals are disabled except if it is explicitly mentioned.
• The Flash memory access time is adjusted to fHCLK frequency (0 wait state from 0 to
30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz and 3 wait
states from 90 to 120 MHz).
• When the peripherals are enabled HCLK is the system clock, fPCLK1 = fHCLK/4, and
fPCLK2 = fHCLK/2, except is explicitly mentioned.
• The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
running from Flash memory (ART accelerator enabled) or RAM (1)
Typ Max(2)
Symbol Parameter Conditions fHCLK Unit
TA = TA = TA =
25 °C 85 °C 105 °C
120 MHz 49 63 72
90 MHz 38 51 61
60 MHz 26 39 49
30 MHz 14 27 37
External clock(3), all
25 MHz 11 24 34
peripherals enabled(4)
16 MHz(5) 8 21 30
8 MHz 5 17 27
4 MHz 3 16 26
Supply current in 2 MHz 2 15 25

IDD mA
Run mode 120 MHz 21 34 44
90 MHz 17 30 40
60 MHz 12 25 35
30 MHz 7 20 30
25 MHz 5 18 28
peripherals disabled
16 MHz(5) 4.0 17.0 27.0
8 MHz 2.5 15.5 25.5
4 MHz 2.0 14.7 24.8
2 MHz 1.6 14.5 24.6
1. Code and data processing running from SRAM1 using boot pins.
2. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
3. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
4. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for
the analog part.
5. In this case HCLK = system clock/2.
76/178 DocID15818 Rev 11

running from Flash memory (ART accelerator disabled)
Typ Max(1)
TA = 25 °C TA = 85 °C TA = 105 °C
120 MHz 61 81 93
90 MHz 48 68 80
60 MHz 33 53 65
30 MHz 18 38 50
25 MHz 14 34 46
peripherals enabled(3)
16 MHz(4) 10 30 42
8 MHz 6 26 38
4 MHz 4 24 36
Supply current 2 MHz 3 23 35

IDD mA
in Run mode 120 MHz 33 54 66
90 MHz 27 47 59
60 MHz 19 39 51
30 MHz 11 31 43
25 MHz 8 28 41
16 MHz(4) 6 26 38
8 MHz 4 24 36
4 MHz 3 23 35
2 MHz 2 23 34
3. When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for
the analog part.
4. In this case HCLK = system clock/2.
DocID15818 Rev 11 77/178

177
processing running from RAM, and peripherals ON
60
50
105°C
40
85°C
IDD(RUN) (mA)
70°C
30 55°C
30°C
20 0°C
-45°C
10
0
0 20 40 60 80 100 120
CPU frequnecy (MHz)
MS19014V1
processing running from RAM, and peripherals OFF
30
25
105°C
20 85°C
IDD(RUN) (mA)
70°C
55°C
15
30°C
0°C
10 -45°C
0
0 20 40 60 80 100 120
CPU Frequency (MHz)
MS19015V1
78/178 DocID15818 Rev 11

processing running from Flash, ART accelerator OFF, peripherals ON
80.0
70.0
60.0
IDD(RUN) (mA)
50.0 105
85
40.0 30°C
-45°C
30.0
20.0
10.0
0.0
0 20 40 60 80 100 120
CPU frequnecy (MHz)
MS19016V1
processing running from Flash, ART accelerator OFF, peripherals OFF
45.0
40.0
35.0
DD(RUN) (mA)
30.0
105
25.0 85
I
30°C
20.0
-45°C
15.0
10.0
5.0
0.0
0.0 20.0 40.0 60.0 80.0 100.0 120.0
CPU Frequency (MHz)
MS19017V1
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177
Table 22. Typical and maximum current consumption in Sleep mode

Typ Max(1)
TA = TA = TA =
25 °C 85 °C 105 °C
120 MHz 38 51 61
90 MHz 30 43 53
60 MHz 20 33 43
30 MHz 11 25 35
External clock(2),
25 MHz 8 21 31
all peripherals enabled(3)
16 MHz 6 19 29
8 MHz 3.6 17.0 27.0
4 MHz 2.4 15.4 25.3
Supply current in 2 MHz 1.9 14.9 24.7

IDD mA
Sleep mode 120 MHz 8 21 31
90 MHz 7 20 30
60 MHz 5 18 28
30 MHz 3.5 16.0 26.0
25 MHz 2.5 16.0 25.0
16 MHz 2.1 15.1 25.0
8 MHz 1.7 15.0 25.0
4 MHz 1.5 14.6 24.6
2 MHz 1.4 14.2 24.3
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is on (ADON bit is set in the ADC_CR2 register).
80/178 DocID15818 Rev 11


peripherals ON
50
45
40
105°C
IDD(SLEEP) (mA)
35
85°C
30 70°C
55°C
25
30°C
20 0°C
-45°C
15
10
0
0 20 40 60 80 100 120
CPU Frequency (MHz)
MS19018V1

peripherals OFF
16
14
12
105°C
IDD(SLEEP) (mA)
85°C
10
70°C
55°C
8
30°C
6 0°C
-45°C
0
0 20 40 60 80 100 120
CPU Frequency (MHz)
MS19019V1
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177
Table 23. Typical and maximum current consumptions in Stop mode(1)

Typ Max
Symbol Parameter Conditions Unit
TA = TA = TA = TA =
25 °C 25 °C 85 °C 105 °C
Flash in Stop mode, low-speed and high-speed

Supply current internal RC oscillators and high-speed oscillator 0.55 1.2 11.00 20.00
in Stop mode OFF (no independent watchdog)
with main Flash in Deep power down mode, low-speed
regulator in and high-speed internal RC oscillators and
Run mode 0.50 1.2 11.00 20.00
high-speed oscillator OFF (no independent
watchdog)
IDD_STOP mA
Flash in Stop mode, low-speed and high-speed
Supply current internal RC oscillators and high-speed oscillator 0.35 1.1 8.00 15.00
in Stop mode OFF (no independent watchdog)
with main
regulator in Flash in Deep power down mode, low-speed
Low Power and high-speed internal RC oscillators and
0.30 1.1 8.00 15.00
mode high-speed oscillator OFF (no independent
watchdog)
1. All typical and maximum values will be further reduced by up to 50% as part of ST continuous improvement of test
procedures. New versions of the datasheet will be released to reflect these changes.
Figure 29. Typical current consumption vs temperature in Stop mode
10
Idd_stop_mr_flhstop
Idd_stop_mr_flhdeep
Idd_stop_lp_flhstop
Idd_stop_lp_flhdeep
(mA)
1
DD(STOP)
I
0.1
0.01
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Temperature (°C)
MS19020V1
1. All typical and maximum values from table 18 and figure 26 will be reduced over time by up to 50% as part
of ST continuous improvement of test procedures. New versions of the datasheet will be released to reflect
these changes
82/178 DocID15818 Rev 11

Table 24. Typical and maximum current consumptions in Standby mode

Typ Max(1)
TA = 25 °C TA = 85 °C TA = 105 °C
VDD = VDD= VDD =
VDD = 3.6 V
1.8 V 2.4 V 3.3 V
Backup SRAM ON, low-speed

3.0 3.4 4.0 15.1 25.8
oscillator and RTC ON
Supply current Backup SRAM OFF, low- 2.4 2.7 3.3 12.4 20.5
IDD_STBY in Standby speed oscillator and RTC ON µA
mode Backup SRAM ON, RTC OFF 2.4 2.6 3.0 12.5 24.8
Backup SRAM OFF, RTC
1.7 1.9 2.2 9.8 19.2
OFF
1. Based on characterization, not tested in production.
Table 25. Typical and maximum current consumptions in VBAT mode

Typ Max(1)
TA =
TA = 25 °C TA = 85 °C
Symbol Parameter Conditions 105 °C Unit
VDD = VDD= VDD =

VDD = 3.6 V
1.8 V 2.4 V 3.3 V
Backup SRAM ON, low-speed
1.29 1.42 1.68 12 19
oscillator and RTC ON
Backup Backup SRAM OFF, low-speed
IDD_VBAT domain supply oscillator and RTC ON 0.62 0.73 0.96 8 10 µA
current
Backup SRAM ON, RTC OFF 0.79 0.81 0.86 9 16
Backup SRAM OFF, RTC OFF 0.10 0.10 0.10 5 7
DocID15818 Rev 11 83/178

177
On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 26. The MCU is placed
under the following conditions:
• At startup, all I/O pins are configured as analog inputs by firmware.
• All peripherals are disabled unless otherwise mentioned
• The given value is calculated by measuring the current consumption
– with all peripherals clocked off
– with one peripheral clocked on (with only the clock applied)
• The code is running from Flash memory and the Flash memory access time is equal to
3 wait states at 120 MHz
• Prefetch and Cache ON
• When the peripherals are enabled, HCLK = 120MHz, fPCLK1 = fHCLK/4, and
fPCLK2 = fHCLK/2
• The typical values are obtained for VDD = 3.3 V and TA= 25 °C, unless otherwise
specified.
Table 26. Peripheral current consumption

Peripheral(1) Typical consumption at 25 °C Unit
GPIO A 0.45
GPIO B 0.43
GPIO C 0.46
GPIO D 0.44
GPIO E 0.44
GPIO F 0.42
GPIO G 0.44
GPIO H 0.42
AHB1 GPIO I 0.43

OTG_HS + ULPI 3.64
mA
CRC 1.17
BKPSRAM 0.21
DMA1 2.76
DMA2 2.85
ETH_MAC +
ETH_MAC_TX
2.99
ETH_MAC_RX
ETH_MAC_PTP
OTG_FS 3.16
AHB2
DCMI 0.60
AHB3 FSMC 1.74
84/178 DocID15818 Rev 11

Table 26. Peripheral current consumption (continued)

TIM2 0.61
TIM3 0.49
TIM4 0.54
TIM5 0.62
TIM6 0.20
TIM7 0.20
TIM12 0.36
TIM13 0.28
TIM14 0.25
USART2 0.25
USART3 0.25
UART4 0.25
APB1 mA
UART5 0.26
I2C1 0.25
I2C2 0.25
I2C3 0.25
SPI2 0.20/0.10
SPI3 0.18/0.09
CAN1 0.31
CAN2 0.30
(2)
DAC channel 1 1.11
DAC channel 1(3) 1.11
PWR 0.15
WWDG 0.15
DocID15818 Rev 11 85/178

177
Table 26. Peripheral current consumption (continued)

SDIO 0.69
TIM1 1.06
TIM8 1.03
TIM9 0.58
TIM10 0.37
TIM11 0.39
APB2 mA
(4)
ADC1 2.13
ADC2(4) 2.04
(4)
ADC3 2.12
SPI1 1.20
USART1 0.38
USART6 0.37
1. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on.
2. EN1 bit is set in DAC_CR register.
3. EN2 bit is set in DAC_CR register.
4. fADC = fPCLK2/2, ADON bit set in ADC_CR2 register.
6.3.7 Wakeup time from low-power mode

The wakeup times given in Table 27 is measured on a wakeup phase with a 16 MHz HSI
RC oscillator. The clock source used to wake up the device depends from the current
operating mode:
• Stop or Standby mode: the clock source is the RC oscillator
• Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 14.
Table 27. Low-power mode wakeup timings

Symbol Parameter Min(1) Typ(1) Max(1) Unit
tWUSLEEP(2) Wakeup from Sleep mode - 1 - µs
Wakeup from Stop mode (regulator in Run mode) - 13 -

Wakeup from Stop mode (regulator in low power mode) - 17 40
tWUSTOP(2) µs
Wakeup from Stop mode (regulator in low power mode
- 110 -
and Flash memory in Deep power down mode)
tWUSTDBY(2)(3) Wakeup from Standby mode 260 375 480 µs

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
3. tWUSTDBY minimum and maximum values are given at 105 °C and –45 °C, respectively.
86/178 DocID15818 Rev 11

6.3.8 External clock source characteristics

High-speed external user clock generated from an external source
The characteristics given in Table 28 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 14.
Table 28. High-speed external user clock characteristics

External user clock source

fHSE_ext 1 - 26 MHz
frequency(1)
VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD
tw(HSE)
OSC_IN high or low time(1) 5 - -
tw(HSE)
ns
tr(HSE)
OSC_IN rise or fall time(1) - - 20
tf(HSE)
Cin(HSE) OSC_IN input capacitance(1) - 5 - pF
DuCy(HSE) Duty cycle 45 - 55 %
IL OSC_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA
Low-speed external user clock generated from an external source

The characteristics given in Table 29 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
Table 29. Low-speed external user clock characteristics

User External clock source

fLSE_ext - 32.768 1000 kHz
frequency(1)
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage
V
OSC32_IN input pin low level
VLSEL VSS - 0.3VDD
voltage
tw(LSE)
OSC32_IN high or low time(1) 450 - -
tf(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time(1) - - 50
tf(LSE)
Cin(LSE) OSC32_IN input capacitance(1) - 5 - pF
DuCy(LSE) Duty cycle 30 - 70 %
IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA
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177
Figure 30. High-speed external clock source AC timing diagram
VHSEH
90 %
10 %
VHSEL
tr(HSE) tf(HSE) tW(HSE) tW(HSE) t
THSE
External fHSE_ext
IL
clock source OSC_IN
STM32F
ai17528
Figure 31. Low-speed external clock source AC timing diagram
VLSEH
90%
10%
VLSEL
tr(LSE) tf(LSE) tW(LSE) tW(LSE) t
TLSE
External fLSE_ext
OSC32_IN IL
clock source
STM32F
ai17529
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 30. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
88/178 DocID15818 Rev 11

Table 30. HSE 4-26 MHz oscillator characteristics(1) (2)

fOSC_IN Oscillator frequency 4 - 26 MHz

RF Feedback resistor - 200 - kΩ
VDD=3.3 V,
ESR= 30 Ω, - 449 -
CL=5 pF@25 MHz
IDD HSE current consumption µA
VDD=3.3 V,
ESR= 30 Ω, - 532 -
CL=10 pF@25 MHz
gm Oscillator transconductance Startup 5 - - mA/V
tSU(HSE(3) Startup time VDD is stabilized - 2 - ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 32). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 32. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
OSC_IN fHSE
Bias
8 MH z RF controlled
resonator
gain
OSC_OU T STM32F
CL2 REXT(1)
ai17530
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 31. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
DocID15818 Rev 11 89/178

177
Table 31. LSE oscillator characteristics (fLSE = 32.768 kHz) (1)

RF Feedback resistor - 18.4 - MΩ

IDD LSE current consumption - - 1 µA
gm Oscillator Transconductance 2.8 - - µA/V
tSU(LSE)(2) startup time VDD is stabilized - 2 - s
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 33. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
OSC32_IN fLSE
Bias
32.768 kH z RF controlled
resonator
gain
OSC32_OU T STM32F
CL2
ai17531
6.3.9 Internal clock source characteristics

The parameters given in Table 32 and Table 33 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 14.
High-speed internal (HSI) RC oscillator
Table 32. HSI oscillator characteristics (1)

fHSI Frequency - 16 - MHz

User-trimmed with the RCC_CR
- - 1 %
register(2)
Accuracy of the HSI TA = –40 to 105 °C –8 - 4.5 %
ACCHSI
oscillator Factory-
TA = –10 to 85 °C –4 - 4 %
calibrated
TA = 25 °C –1 - 1 %
HSI oscillator
tsu(HSI)(3) - 2.2 4 µs
startup time
HSI oscillator
IDD(HSI) - 60 80 µA
power consumption
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
90/178 DocID15818 Rev 11

2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the
ST website www.st.com.
Figure 34. ACCHSI versus temperature
max
avg
6
min
2
Normalized deviation (%)
-2
-4
-6
-8
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Temperature (°C)
MS19012V2
Low-speed internal (LSI) RC oscillator
Table 33. LSI oscillator characteristics (1)

Symbol Parameter Min Typ Max Unit
fLSI(2) Frequency 17 32 47 kHz

tsu(LSI) (3) LSI oscillator startup time - 15 40 µs
(3)
IDD(LSI) LSI oscillator power consumption - 0.4 0.6 µA
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
DocID15818 Rev 11 91/178

177
Figure 35. ACCLSI versus temperature
50
max
40 avg
min
30
Normalized deviati on (%)
20
10
-10
-20
-30
-40
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105
Temperat ure (°C)
MS19013V1
6.3.10 PLL characteristics

The parameters given in Table 34 and Table 35 are derived from tests performed under
Table 34. Main PLL characteristics

0.95
fPLL_IN PLL input clock(1) (2) 1 2.10(2) MHz
fPLL_OUT PLL multiplier output clock 24 - 120 MHz

48 MHz PLL multiplier output
fPLL48_OUT - - 48 MHz
clock
fVCO_OUT PLL VCO output 192 - 432 MHz
VCO freq = 192 MHz 75 - 200
tLOCK PLL lock time µs
VCO freq = 432 MHz 100 - 300
92/178 DocID15818 Rev 11

Table 34. Main PLL characteristics (continued)

RMS - 25 -
Cycle-to-cycle jitter peak

to - ±150 -
System clock peak
120 MHz RMS - 15 -
Period Jitter peak

(3) to - ±200 -
Jitter ps
peak
Main clock output (MCO) for Cycle to cycle at 50 MHz
- 32 -
RMII Ethernet on 1000 samples
Main clock output (MCO) for MII Cycle to cycle at 25 MHz
- 40 -
Ethernet on 1000 samples
Cycle to cycle at 1 MHz
Bit Time CAN jitter - 330 -
on 1000 samples
VCO freq = 192 MHz 0.15 0.40
IDD(PLL)(4) PLL power consumption on VDD - mA
VCO freq = 432 MHz 0.45 0.75
PLL power consumption on VCO freq = 192 MHz 0.30 0.40
IDDA(PLL)(4) - mA
VDDA VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M
factor is shared between PLL and PLLI2S.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
Table 35. PLLI2S (audio PLL) characteristics

fPLLI2S_IN PLLI2S input clock(1) 0.95(2) 1 2.10(2) MHz

fPLLI2S_OUT PLLI2S multiplier output clock - - 216 MHz
fVCO_OUT PLLI2S VCO output 192 - 432 MHz
VCO freq = 192 MHz 75 - 200
tLOCK PLLI2S lock time µs
VCO freq = 432 MHz 100 - 300
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177
Table 35. PLLI2S (audio PLL) characteristics (continued)

Cycle to cycle at RMS - 90 -

12.288 MHz on peak
48KHz period, to - ±280 - ps
N=432, R=5 peak
Master I2S clock jitter
(3) Average frequency of
Jitter
12.288 MHz
- 90 - ps
N=432, R=5
on 1000 samples
Cycle to cycle at 48 KHz
WS I2S clock jitter - 400 - ps
on 1000 samples
PLLI2S power consumption on VCO freq = 192 MHz 0.15 0.40
IDD(PLLI2S)(4) - mA
VDD VCO freq = 432 MHz 0.45 0.75
PLLI2S power consumption on VCO freq = 192 MHz 0.30 0.40
IDDA(PLLI2S)(4) - mA
VDDA VCO freq = 432 MHz 0.55 0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
3. Value given with main PLL running.
94/178 DocID15818 Rev 11

6.3.11 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 42: EMI characteristics). It is available only on the main PLL.
Table 36. SSCG parameters constraint

Symbol Parameter Min Typ Max(1) Unit
fMod Modulation frequency - - 10 KHz

md Peak modulation depth 0.25 - 2 %
MODEPER * INCSTEP - - 215 −1 -
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round [ f PLL_IN ⁄ ( 4 × fMod ) ]
fPLL_IN and fMod must be expressed in Hz.

As an example:
If fPLL_IN = 1 MHz and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation
1:
6 3
MODEPER = round [ 10 ⁄ ( 4 × 10 ) ] = 250
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
15
INCSTEP = round [ ( ( 2 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ]
fVCO_OUT must be expressed in MHz.

With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
15
INCSTEP = round [ ( ( 2 – 1 ) × 2 × 240 ) ⁄ ( 100 × 5 × 250 ) ] = 126md(quantitazed)%
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
15
md quantized % = ( MODEPER × INCSTEP × 100 × 5 ) ⁄ ( ( 2 – 1 ) × PLLN )
As a result:
15
md quantized % = ( 250 × 126 × 100 × 5 ) ⁄ ( ( 2 – 1 ) × 240 ) = 2.0002%(peak)
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177
Figure 36 and Figure 37 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.
Figure 36. PLL output clock waveforms in center spread mode
Frequency (PLL_OUT)
md
F0
md
Time
tmode 2xtmode
ai17291
Figure 37. PLL output clock waveforms in down spread mode
Frequency (PLL_OUT)
F0
2xmd
Time
tmode 2xtmode
ai17292
6.3.12 Memory characteristics

Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
96/178 DocID15818 Rev 11

Table 37. Flash memory characteristics

Write / Erase 8-bit mode

- 5 -
VDD = 1.8 V
IDD Supply current - 8 - mA
VDD = 2.1 V
- 12 -
VDD = 3.3 V
Table 38. Flash memory programming

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Program/erase parallelism
tprog Word programming time - 16 100(2) µs
(PSIZE) = x 8/16/32
- 400 800
(PSIZE) = x 8
tERASE16KB Sector (16 KB) erase time - 300 600 ms
(PSIZE) = x 16
- 250 500
(PSIZE) = x 32
- 1200 2400
(PSIZE) = x 8
tERASE64KB Sector (64 KB) erase time - 700 1400 ms
(PSIZE) = x 16
- 550 1100
(PSIZE) = x 32
- 2 4
(PSIZE) = x 8
tERASE128KB Sector (128 KB) erase time - 1.3 2.6 s
(PSIZE) = x 16
- 1 2
(PSIZE) = x 32
- 16 32
(PSIZE) = x 8
tME Mass erase time - 11 22 s
(PSIZE) = x 16
- 8 16
(PSIZE) = x 32
32-bit program operation 2.7 - 3.6 V
Vprog Programming voltage 16-bit program operation 2.1 - 3.6 V
8-bit program operation 1.8 - 3.6 V
2. The maximum programming time is measured after 100K erase operations.
DocID15818 Rev 11 97/178

177
Table 39. Flash memory programming with VPP

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
tprog Double word programming - 16 100(2) µs

tERASE16KB Sector (16 KB) erase time TA = 0 to +40 °C - 230 -
tERASE64KB Sector (64 KB) erase time VDD = 3.3 V - 490 - ms
tERASE128KB Sector (128 KB) erase time VPP = 8.5 V - 875 -
tME Mass erase time - 6.9 - s
Vprog Programming voltage 2.7 - 3.6 V
VPP VPP voltage range 7 - 9 V
Minimum current sunk on
IPP 10 - - mA
the VPP pin
Cumulative time during
tVPP(3) - - 1 hour
which VPP is applied
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.
Table 40. Flash memory endurance and data retention

Value
Min(1)
TA = –40 to +85 °C (6 suffix versions)

NEND Endurance 10 kcycles
TA = –40 to +105 °C (7 suffix versions)
1 kcycle(2) at TA = 85 °C 30
(2)
tRET Data retention 1 kcycle at TA = 105 °C 10 Years
(2)
10 kcycles at TA = 55 °C 20
2. Cycling performed over the whole temperature range.
6.3.13 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
98/178 DocID15818 Rev 11

The test results are given in Table 41. They are based on the EMS levels and classes
defined in application note AN1709.
Table 41. EMS characteristics

Level/
Symbol Parameter Conditions
Class
VDD = 3.3 V, LQFP176, TA = +25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHCLK = 120 MHz, conforms to 2B
induce a functional disturbance
IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, LQFP176, TA =
VEFTB applied through 100 pF on VDD and VSS +25 °C, fHCLK = 120 MHz, conforms 4A
pins to induce a functional disturbance to IEC 61000-4-2
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
DocID15818 Rev 11 99/178

177
Electromagnetic Interference (EMI)g

The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC® code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
Table 42. EMI characteristics

Max vs.
Monitored [fHSE/fCPU]
frequency band
25/120 MHz
0.1 to 30 MHz
VDD = 3.3 V, TA = 25 °C, LQFP176
package, conforming to SAE J1752/3 30 to 130 MHz 25 dBµV
EEMBC, code running with ART 130 MHz to 1GHz
enabled, peripheral clock disabled
SAE EMI Level 4 -
SEMI Peak level
VDD = 3.3 V, TA = 25 °C, LQFP176 0.1 to 30 MHz 28
package, conforming to SAE J1752/3 30 to 130 MHz 26 dBµV
EEMBC, code running with ART
enabled, PLL spread spectrum 130 MHz to 1GHz 22
enabled, peripheral clock disabled SAE EMI level 4 -
6.3.14 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 43. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)
Electrostatic discharge
VESD(HBM) voltage (human body TA = +25 °C conforming to JESD22-A114 2 2000(2)
model)
V
Electrostatic discharge
VESD(CDM) voltage (charge device TA = +25 °C conforming to JESD22-C101 II 500
model)
1. Based on characterization results, not tested in production.
2. On VBAT pin, VESD(HBM) is limited to 1000 V.
100/178 DocID15818 Rev 11

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 44. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
6.3.15 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 45.
Table 45. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on all FT pins –5 +0

IINJ mA
Injected current on any other pin –5 +5
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177
6.3.16 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 14: General operating conditions.
All I/Os are CMOS and TTL compliant except for BOOT0 and BOOT1.
Table 46. I/O static characteristics(1)

TTa, FT and
- - 0.35VDD–0.04(2)
NRST I/Os
Low level BOOT0 - - TBD(2)
VIL
input voltage
I/O input low
level voltage - - 0.3VDD(3)
except BOOT0
V
TTa, FT and
0.45VDD+0.3(2) - -
NRST I/Os(4) 1.6 V ≤ VDD ≤ 3.6 V
High level BOOT0 TBD(2) - -
VIH
input voltage
I/O input low
level voltage 0.7VDD(3) - -
except BOOT0
Schmitt TTa, FT and

10% VDDIO(2)(5) - -
Vhys trigger NRST I/Os mV
hysteresis BOOT0 TBD(2) - -
(6)
I/O input leakage current VSS ≤ VIN ≤ VDD - - ±1
Ilkg µA
(5)
I/O FT input leakage current VIN = 5 V - - 3
All pins except
Weak pull-up for PA10 and VIN = VSS 30 40 50
RPU equivalent PB12
resistor(7)
PA10 and PB12 8 11 15
kΩ
Weak pull- All pins except
down for PA10 and VIN = VDD 30 40 50
RPD PB12
equivalent
resistor PA10 and PB12 8 11 15
I/O pin
CIO(2) 5 pF
capacitance
1. TBD stands for “to be defined”.
2. Data based on design simulation only. Not tested in production.
3. Tested in production.
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
5. With a minimum of 200 mV.
6. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
102/178 DocID15818 Rev 11

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can
sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the
speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 12).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 12).
Output voltage levels

performed under ambient temperature and VDD supply voltage conditions summarized in
Table 14. All I/Os are CMOS and TTL compliant.
Table 47. Output voltage characteristics(1)

Output low level voltage for an I/O pin

VOL(2) CMOS ports - 0.4
when 8 pins are sunk at same time
IIO = +8 mA V
Output high level voltage for an I/O pin
VOH(3) 2.7 V < VDD < 3.6 V VDD–0.4 -
when 8 pins are sourced at same time
VOL (2) TTL ports - 0.4
when 8 pins are sunk at same time
IIO =+ 8mA V
Output high level voltage for an I/O pin
VOH (3) 2.7 V < VDD < 3.6 V 2.4 -
VOL(2)(4) - 1.3
when 8 pins are sunk at same time IIO = +20 mA
V
Output high level voltage for an I/O pin 2.7 V < VDD < 3.6 V
VOH(3)(4) VDD–1.3 -
VOL(2)(4) - 0.4
when 8 pins are sunk at same time IIO = +6 mA
V
Output high level voltage for an I/O pin 2 V < VDD < 2.7 V
VOH(3)(4) VDD–0.4 -
1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited
amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed
should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current
source (e.g. to drive an LED).
2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data, not tested in production.
DocID15818 Rev 11 103/178

177
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 38 and
Table 48, respectively.
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 14.
Table 48. I/O AC characteristics(1)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)
CL = 50 pF, VDD > 2.70 V - - 4

CL = 50 pF, VDD > 1.8 V - - 2
fmax(IO)out Maximum frequency(2) MHz
CL = 10 pF, VDD > 2.70 V - - 8
00
CL = 10 pF, VDD > 1.8 V - - 4
Output high to low level fall
tf(IO)out/ CL = 50 pF, VDD = 1.8 V to
time and output low to high - - 100 ns
tr(IO)out 3.6 V
level rise time
CL = 50 pF, VDD > 2.70 V - - 25
CL = 50 pF, VDD > 1.8 V - - 12.5
CL = 10 pF, VDD > 2.70 V - - 50(3)
CL = 10 pF, VDD > 1.8 V - - 20
01
CL = 50 pF, VDD >2.7 V - - 10
Output high to low level fall CL = 50 pF, VDD > 1.8 V - - 20
tf(IO)out/
time and output low to high ns
tr(IO)out CL = 10 pF, VDD > 2.70 V - - 6
level rise time
CL = 10 pF, VDD > 1.8 V - - 10
CL = 40 pF, VDD > 2.70 V - - 25
CL = 40 pF, VDD > 1.8 V - - 20
CL = 10 pF, VDD > 2.70 V - - 100(3)
CL = 10 pF, VDD > 1.8 V - - 50(3)
10
CL = 40 pF, VDD > 2.70 V - - 6
tf(IO)out/
tr(IO)out CL = 10 pF, VDD > 2.70 V - 4
level rise time
CL = 10 pF, VDD > 1.8 V - 6
104/178 DocID15818 Rev 11

Table 48. I/O AC characteristics(1) (continued)

OSPEEDRy
[1:0] bit Symbol Parameter Conditions Min Typ Max Unit
value(1)
CL = 30 pF, VDD > 2.70 V - - 100(3)

CL = 30 pF, VDD > 1.8 V - - 50(3)
CL = 10 pF, VDD > 2.70 V - - 180(3)
CL = 10 pF, VDD > 1.8 V - - 100(3)
11
CL = 30 pF, VDD > 2.70 V - - 4
tf(IO)out/
tr(IO)out CL = 10 pF, VDD > 2.70 V - - 2.5
level rise time
CL = 10 pF, VDD > 1.8 V - - 4
Pulse width of external
- tEXTIpw signals detected by the EXTI 10 - - ns
controller
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a
description of the GPIOx_SPEEDR GPIO port output speed register.
2. The maximum frequency is defined in Figure 38.
3. For maximum frequencies above 50 MHz, the compensation cell should be used.
Figure 38. I/O AC characteristics definition

90% 10%
50% 50%
10% 90%
EXTERNAL tr(IO)out tf(IO)out

OUTPUT
ON 50pF T
Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131c
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177
6.3.17 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 49).
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 14.
Table 49. NRST pin characteristics

VIL(NRST)(1) NRST input low level voltage TTL ports - - 0.8

V
VIH(NRST) (1) NRST input high level voltage 2.7 V ≤ VDD ≤ 3.6 V 2 - -
VIL(NRST)(1) NRST input low level voltage CMOS ports - - 0.3VDD
V
VIH(NRST) (1)
NRST input high level voltage 1.8 V ≤ VDD ≤ 3.6 V 0.7VDD - -
NRST Schmitt trigger voltage
Vhys(NRST) - 200 - mV
hysteresis
RPU Weak pull-up equivalent resistor(2) VIN = VSS 30 40 50 kΩ
(1)
VF(NRST) NRST Input filtered pulse - - 100 ns
VNF(NRST)(1) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns
TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - µs
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
Figure 39. Recommended NRST pin protection
VDD
External
reset circuit(1)
RPU Internal Reset
NRST(2)
Filter
0.1 μF
STM32Fxxx
ai14132c
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 49. Otherwise the reset is not taken into account by the device.
106/178 DocID15818 Rev 11

6.3.18 TIM timer characteristics

The parameters given in Table 50 and Table 51 are guaranteed by design.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 50. Characteristics of TIMx connected to the APB1 domain(1)

AHB/APB1 1 - tTIMxCLK
prescaler distinct
from 1, fTIMxCLK =
16.7 - ns
tres(TIM) Timer resolution time 60 MHz
prescaler = 1,
fTIMxCLK = 30 MHz 33.3 - ns
Timer external clock 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 0 30 MHz
ResTIM Timer resolution - 16/32 bit
16-bit counter clock period 1 65536 tTIMxCLK
when internal clock is fTIMxCLK = 60 MHz
selected 0.0167 1092 µs
tCOUNTER APB1= 30 MHz
32-bit counter clock period 1 - tTIMxCLK
when internal clock is
selected 0.0167 71582788 µs
- 65536 × 65536 tTIMxCLK

tMAX_COUNT Maximum possible count
- 71.6 s
1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers.
DocID15818 Rev 11 107/178

177
Table 51. Characteristics of TIMx connected to the APB2 domain(1)

prescaler distinct
from 1, fTIMxCLK =
8.3 - ns
tres(TIM) Timer resolution time 120 MHz
prescaler = 1,
fTIMxCLK = 60 MHz 16.7 - ns
Timer external clock 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 0 60 MHz
ResTIM Timer resolution - 16 bit
fTIMxCLK = 120 MHz
16-bit counter clock period 1 65536 tTIMxCLK
tCOUNTER when internal clock is APB2 = 60 MHz
selected 0.0083 546 µs
- 65536 × 65536 tTIMxCLK

tMAX_COUNT Maximum possible count
- 35.79 s
1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.
6.3.19 Communications interfaces

I2C interface characteristics
STM32F205xx and STM32F207xx I2C interface meets the requirements of the standard I2C
communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 52. Refer also to Section 6.3.16: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
108/178 DocID15818 Rev 11

Table 52. I2C characteristics

Standard mode
Fast mode I2C(1)(2)
I2C(1)(2)
Symbol Parameter Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 - 1.3 -

µs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
th(SDA) SDA data hold time - 3450(3) - 900(3)
tr(SDA) ns
SDA and SCL rise time - 1000 - 300
tr(SCL)
tf(SDA)
SDA and SCL fall time - 300 - 300
tf(SCL)
th(STA) Start condition hold time 4.0 - 0.6 -
Repeated Start condition µs
tsu(STA) 4.7 - 0.6 -
setup time
tsu(STO) Stop condition setup time 4.0 - 0.6 - μs
Stop to Start condition time
tw(STO:STA) 4.7 - 1.3 - μs
(bus free)
Capacitive load for each bus
Cb - 400 - 400 pF
line
Pulse width of the spikes
tSP that are suppressed by the 0 50(4) 0 50 ns
analog filter
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode
clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL
signal.
4. The minimum width of the spikes filtered by the analog filter is above tSP(max).
DocID15818 Rev 11 109/178

177
Figure 40. I2C bus AC waveforms and measurement circuit

V DD_I2C V DD_I2C
RP RP STM32Fxx
RS
SDA
I²C bus RS
SCL
S T AR T REPEATED
S T AR T
tsu(STA) S T AR T
SD A
tf(SDA) tr(SDA) tsu(SDA)
S TOP tw(STO:STA)
th(STA) tw(SCLL) th(SDA)
SCL
tw(SCLH) tr(SCL) tf(SCL) tsu(STO)
ai14979c
1. RS= series protection resistor.

2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
Table 53. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.3 V)(1)(2)

I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400 0x8019
300 0x8021
200 0x8032
100 0x0096
50 0x012C
20 0x02EE
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
110/178 DocID15818 Rev 11

I2S - SPI interface characteristics

Unless otherwise specified, the parameters given in Table 54 for SPI or in Table 55 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 14.
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 54. SPI characteristics

fSCK SPI1 master/slave mode - 30

SPI clock frequency MHz
1/tc(SCK) SPI2/SPI3 master/slave mode - 15
tr(SCL) SPI clock rise and fall Capacitive load: C = 30 pF,

- 8 ns
tf(SCL) time fPCLK = 30 MHz
SPI slave input clock
DuCy(SCK) Slave mode 30 70 %
duty cycle
tsu(NSS)(1) NSS setup time Slave mode 4tPCLK -
th(NSS)(1) NSS hold time Slave mode 2tPCLK -
(1)
tw(SCLH) Master mode, fPCLK = 30 MHz,
SCK high and low time tPCLK-3 tPCLK+3
tw(SCLL)(1) presc = 2
tsu(MI) (1) Master mode 5 -

Data input setup time
tsu(SI)(1) Slave mode 5 -
th(MI) (1) Master mode 5 -

Data input hold time
th(SI)(1) Slave mode 4 -
ns
Data output access
ta(SO)(1)(2) Slave mode, fPCLK = 30 MHz 0 3tPCLK
time
Data output disable
tdis(SO)(1)(3) Slave mode 2 10
time
tv(SO) (1) Data output valid time Slave mode (after enable edge) - 25
tv(MO)(1) Data output valid time Master mode (after enable edge) - 5
th(SO) (1) Slave mode (after enable edge) 15 -
Data output hold time
(1)
th(MO) Master mode (after enable edge) 2 -
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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177
Figure 41. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK)
tSU(NSS) th(NSS)
CPHA= 0
SCK Input
CPOL=0
tw(SCKH)
CPHA= 0 tw(SCKL)
CPOL=1
ta(SO) tv(SO) th(SO) tr(SCK) tdis(SO)

tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
th(SI)
ai14134c
Figure 42. SPI timing diagram - slave mode and CPHA = 1
NSS input
tSU(NSS) tc(SCK) th(NSS)
CPHA=1
SCK Input
CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1
tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI) th(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
ai14135
112/178 DocID15818 Rev 11

Figure 43. SPI timing diagram - master mode
High
NSS input
tc(SCK)
SCK Output
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MS BIN BI T6 IN LSB IN
th(MI)
MOSI
M SB OUT B I T1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
ai14136V2
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177
Table 55. I2S characteristics

Master, 16-bit data,

fCK audio frequency = 48 kHz, main 1.23 1.24
I2S clock frequency clock disabled MHz
1/tc(CK)
Slave 0 64FS(1)
tr(CK)
I2S clock rise and fall time capacitive load CL = 50 pF - (2)
tf(CK)
tv(WS) (3) WS valid time Master 0.3 -
(3)
th(WS) WS hold time Master 0 -
(3)
tsu(WS) WS setup time Slave 3 -
th(WS) (3) WS hold time Slave 0 -
(3)
tw(CKH)
CK high and low time Master fPCLK= 30 MHz 396 -
tw(CKL) (3)
tsu(SD_MR) (3) Master receiver 45
Data input setup time -
tsu(SD_SR) (3) Slave receiver 0 ns
th(SD_MR)(3)(4) Master receiver: fPCLK= 30 MHz, 13
Data input hold time -
th(SD_SR) (3)(4) Slave receiver: fPCLK= 30 MHz 0
Slave transmitter (after enable
tv(SD_ST) (3)(4) Data output valid time - 30
edge)
Slave transmitter (after enable
th(SD_ST) (3) Data output hold time 10 -
edge)
Master transmitter (after enable
tv(SD_MT) (3)(4) Data output valid time - 6
edge)
Master transmitter (after enable
th(SD_MT) (3) Data output hold time 0 -
edge)
1. FS is the sampling frequency. Refer to the I2S section of the STM32F20xxx/21xxx reference manual for more details. fCK
values reflect only the digital peripheral behavior which leads to a minimum of (I2SDIV/(2*I2SDIV+ODD), a maximum of
(I2SDIV+ODD)/(2*I2SDIV+ODD) and FS maximum values for each mode/condition.
2. Refer to Table 48: I/O AC characteristics.
3. Based on design simulation and/or characterization results, not tested in production.
4. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
114/178 DocID15818 Rev 11

Figure 44. I2S slave timing diagram (Philips protocol)(1)

tc(CK)
CK Input CPOL = 0
CPOL = 1
tw(CKH) tw(CKL) th(WS)
WS input
tsu(WS) tv(SD_ST) th(SD_ST)

SDtransmit
LSB transmit(2) MSB transmit Bitn transmit LSB transmit
tsu(SD_SR) th(SD_SR)
SDreceive LSB receive(2) MSB receive Bitn receive LSB receive
ai14881b
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 45. I2S master timing diagram (Philips protocol)(1)
tf(CK) tr(CK)
tc(CK)
CK output
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS) tw(CKL) th(WS)
WS output
tv(SD_MT) th(SD_MT)
SDtransmit LSB transmit(2) MSB transmit Bitn transmit LSB transmit
tsu(SD_MR) th(SD_MR)
SDreceive LSB receive(2) MSB receive Bitn receive LSB receive
ai14884b

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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177
USB OTG FS characteristics

The USB OTG interface is USB-IF certified (Full-Speed). This interface is present in both
the USB OTG HS and USB OTG FS controllers.
Table 56. USB OTG FS startup time

Symbol Parameter Max Unit
tSTARTUP(1) USB OTG FS transceiver startup time 1 µs

Table 57. USB OTG FS DC electrical characteristics

Symbol Parameter Conditions Min.(1) Typ. Max.(1) Unit
USB OTG FS operating

VDD 3.0(2) - 3.6 V
voltage
I(USB_FS_DP/DM,
VDI(3) Differential input sensitivity 0.2 - -
Input USB_HS_DP/DM)
levels Differential common mode
VCM(3) Includes VDI range 0.8 - 2.5 V
range
Single ended receiver
VSE(3) 1.3 - 2.0
threshold
Output VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) - - 0.3
V
levels VOH Static output level high RL of 15 kΩ to VSS(4) 2.8 - 3.6
PA11, PA12, PB14, PB15
(USB_FS_DP/DM, 17 21 24
USB_HS_DP/DM)
RPD VIN = VDD
PA9, PB13
(OTG_FS_VBUS, 0.65 1.1 2.0
OTG_HS_VBUS) kΩ
PA12, PB15 (USB_FS_DP,
VIN = VSS 1.5 1.8 2.1
USB_HS_DP)
RPU PA9, PB13
(OTG_FS_VBUS, VIN = VSS 0.25 0.37 0.55
OTG_HS_VBUS)
1. All the voltages are measured from the local ground potential.
2. The STM32F205xx and STM32F207xx USB OTG FS functionality is ensured down to 2.7 V but not the full
USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
4. RL is the load connected on the USB OTG FS drivers
116/178 DocID15818 Rev 11

Figure 46. USB OTG FS timings: definition of data signal rise and fall time
Crossover
points
Differen tial
Data L ines
VCRS
VS S
tf tr
ai14137
Table 58. USB OTG FS electrical characteristics(1)

Driver characteristics
tr Rise time(2) CL = 50 pF 4 20 ns
tf Fall time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf 90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
USB HS characteristics
Table 59 shows the USB HS operating voltage.
Table 59. USB HS DC electrical characteristics

Symbol Parameter Min.(1) Max.(1) Unit
Input level VDD USB OTG HS operating voltage 2.7 3.6 V

Table 60. Clock timing parameters

Parameter(1) Symbol Min Nominal Max Unit
Frequency (first transition) 8-bit ±10% FSTART_8BIT 54 60 66 MHz

Frequency (steady state) ±500 ppm FSTEADY 59.97 60 60.03 MHz
Duty cycle (first transition) 8-bit ±10% DSTART_8BIT 40 50 60 %
Duty cycle (steady state) ±500 ppm DSTEADY 49.975 50 50.025 %
Time to reach the steady state frequency and
TSTEADY - - 1.4 ms
duty cycle after the first transition
Clock startup time after the Peripheral TSTART_DEV - - 5.6

ms
de-assertion of SuspendM Host TSTART_HOST - - -
PHY preparation time after the first transition
TPREP - - - µs
of the input clock
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177
Figure 47. ULPI timing diagram
Clock
tSC tHC
Control In
(ULPI_DIR,
ULPI_NXT) tSD tHD
data In
(8-bit)
tDC tDC
Control out
(ULPI_STP)
tDD
data out
(8-bit)
ai17361c
Table 61. ULPI timing

Value(1)
Symbol Parameter Unit
Min. Max.
Control in (ULPI_DIR) setup time - 2.0

tSC
Control in (ULPI_NXT) setup time - 1.5
tHC Control in (ULPI_DIR, ULPI_NXT) hold time 0 -
tSD Data in setup time - 2.0 ns
tHD Data in hold time 0 -
tDC Control out (ULPI_STP) setup time and hold time - 9.2
tDD Data out available from clock rising edge - 10.7
1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C.
Ethernet characteristics
Table 62 shows the Ethernet operating voltage.
Table 62. Ethernet DC electrical characteristics

Symbol Parameter Min.(1) Max.(1) Unit
Input level VDD Ethernet operating voltage 2.7 3.6 V

Table 63 gives the list of Ethernet MAC signals for the SMI (station management interface)
and Figure 48 shows the corresponding timing diagram.
118/178 DocID15818 Rev 11

Figure 48. Ethernet SMI timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO) th(MDIO)
ETH_MDIO(I)
ai15666d
Table 63. Dynamics characteristics: Ethernet MAC signals for SMI

Symbol Rating Min Typ Max Unit
tMDC MDC cycle time (2.38 MHz) 411 420 425 ns

td(MDIO) MDIO write data valid time 6 10 13 ns
tsu(MDIO) Read data setup time 12 - - ns
th(MDIO) Read data hold time 0 - - ns
Table 64 gives the list of Ethernet MAC signals for the RMII and Figure 49 shows the
corresponding timing diagram.
Figure 49. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)
RMII_RXD[1:0]
RMII_CRS_DV
ai15667
Table 64. Dynamics characteristics: Ethernet MAC signals for RMII

tsu(RXD) Receive data setup time 1 - -

tih(RXD) Receive data hold time 1.5 - -
tsu(CRS) Carrier sense set-up time 0 - -
ns
tih(CRS) Carrier sense hold time 2 - -
td(TXEN) Transmit enable valid delay time 9 11 13
td(TXD) Transmit data valid delay time 9 11.5 14
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177
Table 65 gives the list of Ethernet MAC signals for MII and Figure 49 shows the
corresponding timing diagram.
Figure 50. Ethernet MII timing diagram
MII_RX_CLK
tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
td(TXEN)
td(TXD)
MII_TX_EN
MII_TXD[3:0]
ai15668
Table 65. Dynamics characteristics: Ethernet MAC signals for MII

tsu(RXD) Receive data setup time 7.5 - - ns

tih(RXD) Receive data hold time 1 - - ns
tsu(DV) Data valid setup time 4 - - ns
tih(DV) Data valid hold time 0 - - ns
tsu(ER) Error setup time 3.5 - - ns
tih(ER) Error hold time 0 - - ns
td(TXEN) Transmit enable valid delay time - 11 14 ns
td(TXD) Transmit data valid delay time - 11 14 ns
CAN (controller area network) interface

function characteristics (CANTX and CANRX).
120/178 DocID15818 Rev 11

6.3.20 12-bit ADC characteristics

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 14.
Table 66. ADC characteristics

VDDA (1)
Power supply 1.8 - 3.6 V
VREF+ Positive reference voltage 1.8(1)(2) - VDDA V
VDDA = 1.8(1) to 2.4 V 0.6 - 15 MHz
fADC ADC clock frequency
VDDA = 2.4 to 3.6 V 0.6 - 30 MHz
fADC = 30 MHz with
- - 1764 kHz
fTRIG(3) External trigger frequency 12-bit resolution
- - 17 1/fADC
0 (VSSA or VREF-
VAIN Conversion voltage range(4) - VREF+ V
tied to ground)
See Equation 1 for
RAIN(3) External input impedance - - 50 kΩ
details
RADC(3)(5) Sampling switch resistance 1.5 - 6 kΩ
Internal sample and hold
CADC(3) - 4 - pF
capacitor
Injection trigger conversion fADC = 30 MHz - - 0.100 µs

tlat(3)
latency - - 3(6) 1/fADC
fADC = 30 MHz - - 0.067 µs
tlatr(3) Regular trigger conversion latency
- - 2(6) 1/fADC
fADC = 30 MHz 0.100 - 16 µs
tS(3) Sampling time
3 - 480 1/fADC
tSTAB(3) Power-up time - 2 3 µs
fADC = 30 MHz
0.5 - 16.40 µs
12-bit resolution
fADC = 30 MHz
0.43 - 16.34 µs
10-bit resolution
Total conversion time (including fADC = 30 MHz
tCONV(3) 0.37 - 16.27 µs
sampling time) 8-bit resolution
fADC = 30 MHz
0.3 - 16.20 µs
6-bit resolution
9 to 492 (tS for sampling +n-bit resolution for successive
1/fADC
approximation)
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177
Table 66. ADC characteristics (continued)

12-bit resolution
- - 2 Msps
Single ADC
12-bit resolution
Sampling rate Interleave Dual ADC - - 3.75 Msps
fS(3)
(fADC = 30 MHz) mode
12-bit resolution
Interleave Triple ADC - - 6 Msps
mode
ADC VREF DC current
IVREF+(3) - 300 500 µA
consumption in conversion mode
ADC VDDA DC current
IVDDA(3) - 1.6 1.8 mA
consumption in conversion mode
2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V.
4. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
5. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V.
6. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 66.
Equation 1: RAIN max formula
R AIN
( k – 0.5 ) - – R ADC
= -------------------------------------------------------------
N+2
f ADC × C ADC × ln ( 2 )
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
Table 67. ADC accuracy (1)

a
Symbol Parameter Test conditions Typ Max(2) Unit
ET Total unadjusted error ±2 ±5

EO Offset error ±1.5 ±2.5
fPCLK2 = 60 MHz,
EG Gain error fADC = 30 MHz, RAIN < 10 kΩ, ±1.5 ±3 LSB
VDDA = 1.8(3) to 3.6 V
ED Differential linearity error ±1 ±2
EL Integral linearity error ±1.5 ±3
1. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
3. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.7 V when
the device operates in the 0 to 70 °C temperature range using an external power supply supervisor (see
Section 3.16).
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog
input pins should be avoided as this significantly reduces the accuracy of the conversion
122/178 DocID15818 Rev 11

being performed on another analog input. It is recommended to add a Schottky diode (pin to
ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
Section 6.3.16 does not affect the ADC accuracy.
Figure 51. ADC accuracy characteristics
V REF+ V DDA
[1LSB IDEAL = (or depending on package)]
4096 4096
EG
4095
4094
4093
(2)
ET
7 (3)
(1)
6
5
EO EL
4
3
ED
2
1L SBIDEAL
1
0
1 2 3 456 7 4093 4094 4095 4096
V SSA VDDA
ai14395c
1. Example of an actual transfer curve.

2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset Error: deviation between the first actual transition and the first ideal one.
EG = Gain Error: deviation between the last ideal transition and the last actual one.
ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one.
EL = Integral Linearity Error: maximum deviation between any actual transition and the end point
correlation line.
Figure 52. Typical connection diagram using the ADC
VDD STM32F
Sample and hold ADC

VT converter
0.6 V
RAIN(1) AINx RADC(1)
12-bit
converter
VT
VAIN 0.6 V
Cparasitic CADC(1)
IL±1 µA
ai17534
1. Refer to Table 66 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
DocID15818 Rev 11 123/178

177
pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
124/178 DocID15818 Rev 11

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 53 or Figure 54,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 53. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F
V REF+
(See note 1)
1 µF // 10 nF V DDA
1 µF // 10 nF
V SSA/V REF-
(See note 1)
ai17535
1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages
except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and
VSSA.
Figure 54. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F
VREF+/VDDA
(See note 1)
1 µF // 10 nF
VREF–/VSSA
(See note 1)
ai17536
1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages
except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and
VSSA.
DocID15818 Rev 11 125/178

177
6.3.21 DAC electrical characteristics
Table 68. DAC characteristics

Symbol Parameter Min Typ Max Unit Comments
VDDA Analog supply voltage 1.8(1) - 3.6 V
VREF+ Reference supply voltage 1.8(1) - 3.6 V VREF+ ≤ VDDA

VSSA Ground 0 - 0 V
RLOAD(2) Resistive load with buffer ON 5 - - kΩ
When the buffer is OFF, the
Impedance output with buffer Minimum resistive load between
RO(2) - - 15 kΩ
OFF DAC_OUT and VSS to have a 1%
accuracy is 1.5 MΩ
Maximum capacitive load at
CLOAD(2) Capacitive load - - 50 pF DAC_OUT pin (when the buffer is
ON).
It gives the maximum output
DAC_OUT Lower DAC_OUT voltage excursion of the DAC.
0.2 - - V
min(2) with buffer ON
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ =
DAC_OUT Higher DAC_OUT voltage 3.6 V and (0x1C7) to (0xE38) at
- - VDDA – 0.2 V
max(2) with buffer ON VREF+ = 1.8 V
DAC_OUT Lower DAC_OUT voltage
- 0.5 - mV
min(2) with buffer OFF It gives the maximum output
DAC_OUT Higher DAC_OUT voltage excursion of the DAC.
- - VREF+ – 1LSB V
max(2) with buffer OFF
With no load, worst code (0x800)
- 170 240 at VREF+ = 3.6 V in terms of DC
DAC DC VREF current consumption on the inputs
IVREF+(4) consumption in quiescent µA
mode (Standby mode) With no load, worst code (0xF1C)
- 50 75 at VREF+ = 3.6 V in terms of DC
consumption on the inputs
With no load, middle code (0x800)
- 280 380 µA
DAC DC VDDA current on the inputs
IDDA(4) consumption in quiescent With no load, worst code (0xF1C)
mode(3) - 475 625 µA at VREF+ = 3.6 V in terms of DC
consumption on the inputs
Given for the DAC in 10-bit

Differential non linearity - - ±0.5 LSB
configuration.
DNL(4) Difference between two
consecutive code-1LSB) Given for the DAC in 12-bit
- - ±2 LSB
configuration.
126/178 DocID15818 Rev 11

Table 68. DAC characteristics (continued)

Symbol Parameter Min Typ Max Unit Comments
Integral non linearity Given for the DAC in 10-bit

- - ±1 LSB
(difference between configuration.
measured value at Code i
INL(4)
and the value at Code i on a Given for the DAC in 12-bit
line drawn between Code 0 - - ±4 LSB
configuration.
and last Code 1023)
- - ±10 mV
Offset error
(difference between Given for the DAC in 10-bit at
- - ±3 LSB
Offset(4) measured value at Code VREF+ = 3.6 V
(0x800) and the ideal value =
Given for the DAC in 12-bit at
VREF+/2) - - ±12 LSB
VREF+ = 3.6 V
Gain Given for the DAC in 12-bit
Gain error - - ±0.5 %
error(4) configuration
Settling time (full scale: for a
10-bit input code transition
between the lowest and the CLOAD ≤ 50 pF,
tSETTLING(4) - 3 6 µs
highest input codes when RLOAD ≥ 5 kΩ
DAC_OUT reaches final
value ±4LSB
Total Harmonic Distortion CLOAD ≤ 50 pF,
THD(4) - - - dB
Buffer ON RLOAD ≥ 5 kΩ
Max frequency for a correct
Update DAC_OUT change when CLOAD ≤ 50 pF,
- - 1 MS/s
rate(2) small variation in the input RLOAD ≥ 5 kΩ
code (from code i to i+1LSB)
Wakeup time from off state CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
tWAKEUP(4) (Setting the ENx bit in the - 6.5 10 µs input code between lowest and
DAC Control register) highest possible ones.
Power supply rejection ratio
PSRR+ (2) (to VDDA) (static DC - –67 –40 dB No RLOAD, CLOAD = 50 pF
measurement)
3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
4. Guaranteed by characterization, not tested in production.
DocID15818 Rev 11 127/178

177
Figure 55. 12-bit buffered /non-buffered DAC

Buffered/Non-buffered DAC
Buffer(1)
R LOAD
12-bit DAC_OUTx
digital to
analog
converter
C LOAD
ai17157V2
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
6.3.22 Temperature sensor characteristics
Table 69. TS characteristics

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

Avg_Slope(1) Average slope - 2.5 mV/°C
V25(1) Voltage at 25 °C - 0.76 V
tSTART(2) Startup time - 6 10 µs
ADC sampling time when reading the
TS_temp(3)(2) temperature 10 - - µs
1°C accuracy
3. Shortest sampling time can be determined in the application by multiple iterations.
6.3.23 VBAT monitoring characteristics
Table 70. VBAT monitoring characteristics

R Resistor bridge for VBAT - 50 - KΩ

Q Ratio on VBAT measurement - 2 -
(1)
Er Error on Q –1 - +1 %
ADC sampling time when reading the VBAT
TS_vbat(2)(2) 5 - - µs
1mV accuracy
128/178 DocID15818 Rev 11

6.3.24 Embedded reference voltage

The parameters given in Table 71 are derived from tests performed under ambient
Table 71. Embedded internal reference voltage

VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V
ADC sampling time when
TS_vrefint(1) reading the internal reference 10 - - µs
voltage
Internal reference voltage
VRERINT_s
(2) spread over the temperature VDD = 3 V - 3 5 mV
range
TCoeff(2) Temperature coefficient - 30 50 ppm/°C
(2)
tSTART Startup time - 6 10 µs
6.3.25 FSMC characteristics

Asynchronous waveforms and timings
Figure 56 through Figure 59 represent asynchronous waveforms and Table 72 through
Table 75 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
• AddressSetupTime = 1
• AddressHoldTime = 1
• DataSetupTime = 1
• BusTurnAroundDuration = 0x0
In all timing tables, the THCLK is the HCLK clock period.
DocID15818 Rev 11 129/178

177
Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

tw(NE)
FSMC_NE
tv(NOE_NE) t w(NOE) t h(NE_NOE)
FSMC_NOE
FSMC_NWE
tv(A_NE) t h(A_NOE)
FSMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)
FSMC_NBL[1:0]
t h(Data_NE)
t su(Data_NOE) th(Data_NOE)
t su(Data_NE)
FSMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FSMC_NADV(1)
ai14991c
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 72. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)

tw(NE) FSMC_NE low time 2THCLK– 0.5 2THCLK+0.5 ns

tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0.5 2.5 ns
tw(NOE) FSMC_NOE low time 2THCLK- 1 2THCLK+ 0.5 ns
th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns
tv(A_NE) FSMC_NEx low to FSMC_A valid - 4 ns
th(A_NOE) Address hold time after FSMC_NOE high 0 - ns
tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns
th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns
tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+ 0.5 - ns
tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+ 2.5 - ns
th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns
th(Data_NE) Data hold time after FSMC_NEx high 0 - ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2.5 ns
tw(NADV) FSMC_NADV low time - THCLK– 0.5 ns
130/178 DocID15818 Rev 11

1. CL = 30 pF.
Figure 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
tw(NE)
FSMC_NEx
FSMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FSMC_NWE
tv(A_NE) th(A_NWE)
tv(BL_NE) th(BL_NWE)
FSMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FSMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FSMC_NADV(1)
ai14990
1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 73. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)

tw(NE) FSMC_NE low time 3THCLK 3THCLK+ 4 ns

tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK– 0.5 THCLK+ 0.5 ns
tw(NWE) FSMC_NWE low time THCLK– 0.5 THCLK+ 3 ns
FSMC_NWE high to FSMC_NE high hold
th(NE_NWE) THCLK - ns
time
th(A_NWE) Address hold time after FSMC_NWE high THCLK- 3 - ns
FSMC_BL hold time after FSMC_NWE
th(BL_NWE) THCLK– 1 - ns
high
tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+ 5 ns
th(Data_NWE) Data hold time after FSMC_NWE high THCLK+0.5 - ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns
tw(NADV) FSMC_NADV low time - THCLK+ 1.5 ns
DocID15818 Rev 11 131/178

177
1. CL = 30 pF.
Figure 58. Asynchronous multiplexed PSRAM/NOR read waveforms
tw(NE)
FSMC_NE
tv(NOE_NE) t h(NE_NOE)
FSMC_NOE
t w(NOE)
FSMC_NWE
tv(A_NE) t h(A_NOE)
tv(BL_NE) th(BL_NOE)
FSMC_NBL[1:0] NBL
th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)
FSMC_AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FSMC_NADV
ai14892b
Table 74. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)

tw(NE) FSMC_NE low time 3THCLK-1 3THCLK+1 ns

tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 2THCLK 2THCLK+0.5 ns
tw(NOE) FSMC_NOE low time THCLK-1 THCLK+1 ns
th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2.5 ns
tw(NADV) FSMC_NADV low time THCLK– 1.5 THCLK ns
FSMC_AD(adress) valid hold time after
th(AD_NADV) THCLK - ns
FSMC_NADV high)
th(A_NOE) Address hold time after FSMC_NOE high THCLK - ns
th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns
tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1 ns
tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+ 2 - ns
132/178 DocID15818 Rev 11

Table 74. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued)

tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+ 3 - ns

th(Data_NE) Data hold time after FSMC_NEx high 0 - ns
th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns
1. CL = 30 pF.
DocID15818 Rev 11 133/178

177
Figure 59. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)
FSMC_NEx
FSMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FSMC_NWE
tv(A_NE) th(A_NWE)
tv(BL_NE) th(BL_NWE)
FSMC_NBL[1:0] NBL
t v(A_NE) t v(Data_NADV) th(Data_NWE)
FSMC_AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FSMC_NADV
ai14891B
Table 75. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)

tw(NE) FSMC_NE low time 4THCLK-1 4THCLK+1 ns

tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK- 1 THCLK ns
tw(NWE) FSMC_NWE low tim e 2THCLK 2THCLK+1 ns
th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK- 1 - ns
tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2 ns
tw(NADV) FSMC_NADV low time THCLK– 2 THCLK+ 2 ns
FSMC_AD(adress) valid hold time after
th(AD_NADV) THCLK - ns
FSMC_NADV high)
th(A_NWE) Address hold time after FSMC_NWE high THCLK– 0.5 - ns
th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK- 1 - ns
tv(Data_NADV) FSMC_NADV high to Data valid - THCLK+2 ns
th(Data_NWE) Data hold time after FSMC_NWE high THCLK– 0.5 - ns
1. CL = 30 pF.
134/178 DocID15818 Rev 11

Synchronous waveforms and timings

Figure 60 through Figure 63 represent synchronous waveforms and Table 77 through
Table 79 provide the corresponding timings. The results shown in these tables are obtained
• BurstAccessMode = FSMC_BurstAccessMode_Enable;
• MemoryType = FSMC_MemoryType_CRAM;
• WriteBurst = FSMC_WriteBurst_Enable;
• CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual)
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 60. Synchronous multiplexed NOR/PSRAM read timings

tw(CLK) tw(CLK) BUSTURN = 0
FSMC_CLK
Data latency = 0
td(CLKL-NExL) t d(CLKL-NExH)
FSMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FSMC_NADV
td(CLKL-AV) td(CLKL-AIV)
FSMC_A[25:16]
td(CLKH-NOEL) td(CLKL-NOEH)
FSMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
td(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FSMC_AD[15:0] AD[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 1b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
ai14893h
DocID15818 Rev 11 135/178

177
Table 76. Synchronous multiplexed NOR/PSRAM read timings(1)(2)

tw(CLK) FSMC_CLK period 2THCLK - ns

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns
td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns
td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1.5 ns
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 2.5 - ns
td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns
td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - ns
td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low - 1 ns
td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1 - ns
td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 3 ns
td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns
FSMC_A/D[15:0] valid data before FSMC_CLK
tsu(ADV-CLKH) 5 - ns
high
th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns
1. CL = 30 pF.
136/178 DocID15818 Rev 11

Figure 61. Synchronous multiplexed PSRAM write timings

FSMC_CLK
Data latency = 0
td(CLKL-NExL) td(CLKL-NExH)
FSMC_NEx
FSMC_NADV
FSMC_A[25:16]
td(CLKL-NWEL) td(CLKL-NWEH)
FSMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)
FSMC_AD[15:0] AD[15:0] D1 D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV)
td(CLKL-NBLH)
FSMC_NBL
ai14992g
Table 77. Synchronous multiplexed PSRAM write timings(1)(2)

tw(CLK) FSMC_CLK period 2THCLK- 1 - ns

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns
td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns
td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns
td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns
td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 2 ns
td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0.5 - ns
DocID15818 Rev 11 137/178

177
1. CL = 30 pF.
Figure 62. Synchronous non-multiplexed NOR/PSRAM read timings

FSMC_CLK
Data latency = 0
FSMC_NEx
FSMC_NADV
FSMC_A[25:0]
td(CLKH-NOEL) td(CLKL-NOEH)
FSMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
FSMC_D[15:0] D1 D2
FSMC_NWAIT
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FSMC_NWAIT
ai14894g
Table 78. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2)

tw(CLK) FSMC_CLK period 2THCLK - ns

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2.5 ns
td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 4 - ns
td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low - 1 ns
td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns
tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 8 - ns
th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 0 - ns
138/178 DocID15818 Rev 11

1. CL = 30 pF.
Figure 63. Synchronous non-multiplexed PSRAM write timings

FSMC_CLK
Data latency = 0
FSMC_NEx
FSMC_NADV
FSMC_A[25:0]
td(CLKL-NWEL) td(CLKL-NWEH)
FSMC_NWE
td(CLKL-Data) td(CLKL-Data)
FSMC_D[15:0] D1 D2
FSMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKL-NBLH)
th(CLKH-NWAITV)
FSMC_NBL
ai14993g
Table 79. Synchronous non-multiplexed PSRAM write timings(1)(2)

tw(CLK) FSMC_CLK period 2THCLK- 1 - ns

td(CLKL-
FSMC_CLK low to FSMC_NADV low - 5 ns
NADVL)
td(CLKL-
FSMC_CLK low to FSMC_NADV high 6 - ns
NADVH)

td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns
td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1 - ns
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177
Table 79. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued)

td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 2 ns

td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 2 - ns
1. CL = 30 pF.
PC Card/CompactFlash controller waveforms and timings

Figure 64 through Figure 69 represent synchronous waveforms together with Table 80 and
Table 81 provides the corresponding timings. The results shown in this table are obtained
• COM.FSMC_SetupTime = 0x04;
• COM.FSMC_WaitSetupTime = 0x07;
• COM.FSMC_HoldSetupTime = 0x04;
• COM.FSMC_HiZSetupTime = 0x00;
• ATT.FSMC_SetupTime = 0x04;
• ATT.FSMC_WaitSetupTime = 0x07;
• ATT.FSMC_HoldSetupTime = 0x04;
• ATT.FSMC_HiZSetupTime = 0x00;
• IO.FSMC_SetupTime = 0x04;
• IO.FSMC_WaitSetupTime = 0x07;
• IO.FSMC_HoldSetupTime = 0x04;
• IO.FSMC_HiZSetupTime = 0x00;
• TCLRSetupTime = 0;
• TARSetupTime = 0;
140/178 DocID15818 Rev 11

Figure 64. PC Card/CompactFlash controller waveforms for common memory read

access
FSMC_NCE4_2(1)
FSMC_NCE4_1
tv(NCEx-A) th(NCEx-AI)
FSMC_A[10:0]
th(NCEx-NREG)
td(NREG-NCEx)
th(NCEx-NIORD)
td(NIORD-NCEx)
th(NCEx-NIOWR)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
FSMC_NWE
td(NCE4_1-NOE) tw(NOE)
FSMC_NOE
tsu(D-NOE) th(NOE-D)
FSMC_D[15:0]
ai14895b
1. FSMC_NCE4_2 remains high (inactive during 8-bit access.
Figure 65. PC Card/CompactFlash controller waveforms for common memory write

access
FSMC_NCE4_1
FSMC_NCE4_2 High
tv(NCE4_1-A) th(NCE4_1-AI)
FSMC_A[10:0]
th(NCE4_1-NREG)
td(NREG-NCE4_1)
th(NCE4_1-NIORD)
td(NIORD-NCE4_1)
th(NCE4_1-NIOWR)
FSMC_NREG
FSMC_NIOWR
FSMC_NIORD
td(NCE4_1-NWE) tw(NWE) td(NWE-NCE4_1)
FSMC_NWE
FSMC_NOE
MEMxHIZ =1
td(D-NWE)
tv(NWE-D) th(NWE-D)
FSMC_D[15:0]
ai14896b
DocID15818 Rev 11 141/178

177
Figure 66. PC Card/CompactFlash controller waveforms for attribute memory read

access
FSMC_NCE4_1
FSMC_NCE4_2
High
FSMC_A[10:0]
FSMC_NIOWR
FSMC_NIORD
td(NREG-NCE4_1) th(NCE4_1-NREG)
FSMC_NREG
FSMC_NWE
td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1)
FSMC_NOE
FSMC_D[15:0](1)
ai14897b
1. Only data bits 0...7 are read (bits 8...15 are disregarded).
142/178 DocID15818 Rev 11

Figure 67. PC Card/CompactFlash controller waveforms for attribute memory write

access
FSMC_NCE4_1
FSMC_NCE4_2 High
FSMC_A[10:0]
FSMC_NIOWR
FSMC_NIORD
td(NREG-NCE4_1) th(NCE4_1-NREG)
FSMC_NREG
td(NCE4_1-NWE) tw(NWE)
FSMC_NWE
td(NWE-NCE4_1)
FSMC_NOE
tv(NWE-D)
FSMC_D[7:0](1)
ai14898b
1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z).
Figure 68. PC Card/CompactFlash controller waveforms for I/O space read access
FSMC_NCE4_1
FSMC_NCE4_2
tv(NCEx-A) th(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIOWR
td(NIORD-NCE4_1) tw(NIORD)
FSMC_NIORD
tsu(D-NIORD) td(NIORD-D)
FSMC_D[15:0]
ai14899B
DocID15818 Rev 11 143/178

177
Figure 69. PC Card/CompactFlash controller waveforms for I/O space write access
FSMC_NCE4_1
FSMC_NCE4_2
tv(NCEx-A) th(NCE4_1-AI)
FSMC_A[10:0]
FSMC_NREG
FSMC_NWE
FSMC_NOE
FSMC_NIORD
td(NCE4_1-NIOWR) tw(NIOWR)
FSMC_NIOWR
ATTxHIZ =1
th(NIOWR-D)
tv(NIOWR-D)
FSMC_D[15:0]
ai14900c
Table 80. Switching characteristics for PC Card/CF read and write cycles in
attribute/common space(1)(2)
tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns

th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid 4 - ns
td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid - 3.5 ns
th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid THCLK+ 4 - ns
td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+ 1 ns
td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low - 5THCLK ns
tw(NOE) FSMC_NOE low width 8THCLK– 0.5 8THCLK+ 1 ns
td(NOE_NCEx) FSMC_NOE high to FSMC_NCEx high 5THCLK+ 2.5 - ns
tsu (D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 4 - ns
th (N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid 2 - ns
tw(NWE) FSMC_NWE low width 8THCLK- 1 8THCLK+ 4 ns
td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high 5THCLK+ 1.5 ns
td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5HCLK+ 1 ns
tv (NWE-D) FSMC_NWE low to FSMC_D[15:0] valid - 0 ns
th (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 8 THCLK - ns
td (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13THCLK - ns
1. CL = 30 pF.
144/178 DocID15818 Rev 11

Table 81. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2)
tw(NIOWR) FSMC_NIOWR low width 8THCLK - 0.5 - ns

tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid - 5THCLK- 1 ns
th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid 8THCLK- 3 - ns
td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK+ 1.5 ns
th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid 5THCLK - ns
td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid - 5THCLK+ 1 ns
th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5THCLK– 0.5 - ns
tw(NIORD) FSMC_NIORD low width 8THCLK+ 1 - ns
FSMC_D[15:0] valid before FSMC_NIORD
tsu(D-NIORD) 9.5 ns
high
td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 0 ns
1. CL = 30 pF.
NAND controller waveforms and timings

Figure 70 through Figure 73 represent synchronous waveforms, together with Table 82 and
Table 83 provides the corresponding timings. The results shown in this table are obtained
• COM.FSMC_SetupTime = 0x01;
• COM.FSMC_WaitSetupTime = 0x03;
• COM.FSMC_HoldSetupTime = 0x02;
• COM.FSMC_HiZSetupTime = 0x01;
• ATT.FSMC_SetupTime = 0x01;
• ATT.FSMC_WaitSetupTime = 0x03;
• ATT.FSMC_HoldSetupTime = 0x02;
• ATT.FSMC_HiZSetupTime = 0x01;
• Bank = FSMC_Bank_NAND;
• MemoryDataWidth = FSMC_MemoryDataWidth_16b;
• ECC = FSMC_ECC_Enable;
• ECCPageSize = FSMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0;
DocID15818 Rev 11 145/178

177
Figure 70. NAND controller waveforms for read access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16)
FSMC_NWE
td(ALE-NOE) th(NOE-ALE)
FSMC_NOE (NRE)
FSMC_D[15:0]
ai14901c
Figure 71. NAND controller waveforms for write access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NWE) th(NWE-ALE)
FSMC_NWE
FSMC_NOE (NRE)
tv(NWE-D) th(NWE-D)
FSMC_D[15:0]
ai14902c
146/178 DocID15818 Rev 11

Figure 72. NAND controller waveforms for common memory read access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NOE) th(NOE-ALE)
FSMC_NWE
tw(NOE)
FSMC_NOE
FSMC_D[15:0]
ai14912c
Figure 73. NAND controller waveforms for common memory write access
FSMC_NCEx
ALE (FSMC_A17)
CLE (FSMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)
FSMC_NWE
FSMC_NOE
td(D-NWE)
tv(NWE-D) th(NWE-D)
FSMC_D[15:0]
ai14913c
Table 82. Switching characteristics for NAND Flash read cycles(1)(2)

tw(N0E) FSMC_NOE low width 4THCLK- 1 4THCLK+ 2 ns

FSMC_D[15-0] valid data before FSMC_NOE
tsu(D-NOE) 9 - ns
high
th(NOE-D) FSMC_D[15-0] valid data after FSMC_NOE high 3 - ns
td(ALE-NOE) FSMC_ALE valid before FSMC_NOE low - 3THCLK ns
th(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK+ 2 - ns
1. CL = 30 pF.
DocID15818 Rev 11 147/178

177
Table 83. Switching characteristics for NAND Flash write cycles(1)(2)

tw(NWE) FSMC_NWE low width 4THCLK- 1 4THCLK+ 3 ns

tv(NWE-D) FSMC_NWE low to FSMC_D[15-0] valid - 0 ns
th(NWE-D) FSMC_NWE high to FSMC_D[15-0] invalid 3THCLK - ns
td(D-NWE) FSMC_D[15-0] valid before FSMC_NWE high 5THCLK - ns
td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low - 3THCLK+ 2 ns
th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK- 2 - ns
1. CL = 30 pF.
6.3.26 Camera interface (DCMI) timing specifications
Table 84. DCMI characteristics

Symbol Parameter Conditions Min Max
Frequency ratio
- DCMI_PIXCLK= 48 MHz 0.4
DCMI_PIXCLK/fHCLK
6.3.27 SD/SDIO MMC card host interface (SDIO) characteristics

performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
function characteristics (D[7:0], CMD, CK).
Figure 74. SDIO high-speed mode
tf tr
tC
tW(CKH) tW(CKL)
CK
tOV tOH
D, CMD
(output)
tISU tIH
D, CMD
(input)
ai14887
148/178 DocID15818 Rev 11

Figure 75. SD default mode
CK
tOVD tOHD
D, CMD
(output)
ai14888
Table 85. SD / MMC characteristics

Clock frequency in data transfer

fPP CL ≤ 30 pF 0 48 MHz
mode
- SDIO_CK/fPCLK2 frequency ratio - - 8/3 -
tW(CKL) Clock low time, fPP = 16 MHz CL ≤ 30 pF 32
tW(CKH) Clock high time, fPP = 16 MHz CL ≤ 30 pF 31
ns
tr Clock rise time CL ≤ 30 pF 3.5
tf Clock fall time CL ≤ 30 pF 5
CMD, D inputs (referenced to CK)
tISU Input setup time CL ≤ 30 pF 2
ns
tIH Input hold time CL ≤ 30 pF 0
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV Output valid time CL ≤ 30 pF 6
ns
tOH Output hold time CL ≤ 30 pF 0.3
CMD, D outputs (referenced to CK) in SD default mode(1)

tOVD Output valid default time CL ≤ 30 pF 7
ns
tOHD Output hold default time CL ≤ 30 pF 0.5
1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output.
6.3.28 RTC characteristics
Table 86. RTC characteristics

Symbol Parameter Conditions Min Max
Any read/write operation

- fPCLK1/RTCCLK frequency ratio 4 -
from/to an RTC register
DocID15818 Rev 11 149/178

177
Package characteristics STM32F20xxx
7 Package characteristics
7.1 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
150/178 DocID15818 Rev 11

STM32F20xxx Package characteristics
Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline
SEATING
PLANE
C
A2
A
A1
c
0.25 mm
GAUGE PLANE
ccc C
A1
K
D L
D1 L1
D3
48 33
32
49
E1
E3
64 17
PIN 1 1 16
IDENTIFICATION e
5W_ME_V2
1. Drawing is not to scale.
Table 87. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 11.800 12.000 12.200 0.4646 0.4724 0.4803
D1 9.800 10.000 10.200 0.3937 0.3937 0.4016
D3 - 7.500 - - 0.2953 -
DocID15818 Rev 11 151/178

177
Table 87. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data (continued)
Symbol
E 11.800 12.000 12.200 0.4646 0.4724 0.4803

E1 9.800 10.000 10.200 0.3937 0.3937 0.4016
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 77. Recommended footprint
48 33
0.3
49 0.5 32
12.7
10.3
10.3
64 17
1.2
1 16
7.8
12.7
ai14909c
2. Dimensions are in millimeters.
152/178 DocID15818 Rev 11

Figure 78. WLCSP64+2 - 0.400 mm pitch wafer level chip size package outline
A1 ball location e1
D
e
e
Detail A
E e1
A2
A F
Wafer back side Side view Bump side
Detail A
rotated by 90 °C
eee A1
b Seating plane
A0FX_ME
Table 88. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data
millimeters inches
Symbol
A 0.520 0.570 0.600 0.0205 0.0224 0.0236

A1 0.170 0.190 0.210 0.0067 0.0075 0.0083
A2 0.350 0.380 0.410 0.0138 0.0150 0.0161
b 0.245 0.270 0.295 0.0096 0.0106 0.0116
D 3.619 3.639 3.659 0.1425 0.1433 0.1441
E 3.951 3.971 3.991 0.1556 0.1563 0.1571
e - 0.400 - - 0.0157 -
e1 - 3.218 - - 0.1267 -
F - 0.220 - - 0.0087 -
DocID15818 Rev 11 153/178

177
Table 88. WLCSP64+2 - 0.400 mm pitch wafer level chip size package mechanical data (continued)
millimeters inches
Symbol
G - 0.386 - - 0.0152 -
eee - - 0.050 - - 0.0020
154/178 DocID15818 Rev 11

Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline
SEATING
PLANE
C
A2
A
A1
c
0.25 mm
GAUGE PLANE
ccc C
A1
K
D L
D1 L1
D3
75 51
76 50
b
E1
E3
E
100 26
PIN 1 1 25
IDENTIFICATION
e
1L_ME_V4
Table 89. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data
Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
DocID15818 Rev 11 155/178

177
Table 89. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data
Symbol
E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
75 51
76 50
0.5
0.3
16.7 14.3
100 26
1.2
1 25
12.3
16.7
ai14906

156/178 DocID15818 Rev 11

Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad

flat package outline
SEATING
PLANE
C
A1
A2
A
c
0.25 mm
ccc C GAUGE PLANE
A1
D
L
K
D1
L1
D3
108 73
109
72
b
E1
E3
37
144
PIN 1 1 36
IDENTIFICATION
e
1A_ME_V3
Table 90. LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data
Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.874
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.689 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
DocID15818 Rev 11 157/178

177
Table 90. LQFP144 20 x 20 mm, 144-pin low-profile quad flat package mechanical data (continued)
Symbol
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.6890 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1.35
108 73
109 0.35 72
0.5
17.85
19.9 22.6
144 37
1 36
19.9
22.6
ai14905c

158/178 DocID15818 Rev 11

Figure 83. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline
C Seating plane
c
A1
A2
0.25 mm
gauge plane
k
A1
L
HD L1
PIN 1 D
IDENTIFICATION
ZE
E
HE
ZD
b
1T_ME_V2

package mechanical data
Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 - 1.450 0.0531 - 0.0571
b 0.170 - 0.270 0.0067 - 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 23.900 - 24.100 0.9409 - 0.9488
E 23.900 - 24.100 0.9409 - 0.9488
e - 0.500 - - 0.0197 -
HD 25.900 - 26.100 1.0197 - 1.0276
DocID15818 Rev 11 159/178

177

package mechanical data (continued)
Symbol
HE 25.900 26.100 1.0197 1.0276

L(2) 0.450 0.750 0.0177 0.0295
L1 1.000 0.0394
ZD 1.250 0.0492
ZE 1.250 0.0492
k 0° 7° 0° 7°
ccc 0.080 0.0031
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
160/178 DocID15818 Rev 11

Figure 84. LQFP176 recommended footprint
1.2
176 133
1 0.5 132
0.3
26.7
21.8
44 89
45 88
1.2
21.8
26.7
1T_FP_V1
1. Dimensions are expressed in millimeters.
DocID15818 Rev 11 161/178

177
Figure 85. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm,
package outline
C Seating plane
A2 ddd C
A
b A1 A
A1 ball A1 ball E
identifier index area
e F
A
F
e
B
R
15 1
BOTTOM VIEW TOP VIEW
Øb (176 + 25 balls)
Ø eee M C A B
Ø fff M C
A0E7_ME_V5
Table 92. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data
Symbol
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.002 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
b 0.230 0.280 0.330 0.0091 0.0110 0.0130
D 9.950 10.000 10.050 0.3917 0.3937 0.3957
E 9.950 10.000 10.050 0.3917 0.3937 0.3957
e - 0.650 - - 0.0256 -
F 0.400 0.450 0.500 0.0157 0.0177 0.0197
ddd - - 0.080 - - 0.0031
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0031
162/178 DocID15818 Rev 11

7.2 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 93. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

45
LQFP 64 - 10 × 10 mm / 0.5 mm pitch
51
WLCSP64+2 - 0.400 mm pitch
46
LQFP100 - 14 × 14 mm / 0.5 mm pitch
ΘJA °C/W
40
LQFP144 - 20 × 20 mm / 0.5 mm pitch
38
LQFP176 - 24 × 24 mm / 0.5 mm pitch
39
UFBGA176 - 10× 10 mm / 0.5 mm pitch
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DocID15818 Rev 11 163/178

177
Part numbering STM32F20xxx
8 Part numbering
Table 94. Ordering information scheme

Example: STM32 F 205 R E T 6 Vxxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
205 = STM32F20x, connectivity
207= STM32F20x, connectivity, camera interface,
Ethernet
Pin count
R = 64 pins or 66 pins(1)
V = 100 pins
Z = 144 pins
I = 176 pins
Flash memory size

B = 128 Kbytes of Flash memory
C = 256 Kbytes of Flash memory
E = 512 Kbytes of Flash memory
F = 768 Kbytes of Flash memory
G = 1024 Kbytes of Flash memory
Package
T = LQFP
H = UFBGA
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Software option
Internal code or Blank
Options
xxx = programmed parts
TR = tape and reel
1. The 66 pins is available on WLCSP package only.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
164/178 DocID15818 Rev 11

STM32F20xxx Revision history
9 Revision history
Table 95. Document revision history

Date Revision Changes
05-Jun-2009 1 Initial release.

Document status promoted from Target specification to Preliminary
data.
In Table 8: STM32F20x pin and ball definitions:
– Note 4 updated
09-Oct-2009 2 – VDD_SA and VDD_3 pins inverted (Figure 12: STM32F20x LQFP100
pinout, Figure 13: STM32F20x LQFP144 pinout and Figure 14:
STM32F20x LQFP176 pinout corrected accordingly).
Section 7.1: Package mechanical data changed to LQFP with no
exposed pad.
LFBGA144 package removed. STM32F203xx part numbers removed.
Part numbers with 128 and 256 Kbyte Flash densities added.
01-Feb-2010 3 Encryption features removed.
PC13-TAMPER-RTC renamed to PC13-RTC_AF1 and PI8-TAMPER-
RTC renamed to PI8-RTC_AF2.
Renamed high-speed SRAM, system SRAM.
Removed combination: 128 KBytes Flash memory in LQFP144.
Added UFBGA176 package. Added note 1 related to LQFP176
package in Table 2, Figure 14, and Table 94.
Added information on ART accelerator and audio PLL (PLLI2S).
Added Table 6: USART feature comparison.
Several updates on Table 8: STM32F20x pin and ball definitions and
Table 10: Alternate function mapping. ADC, DAC, oscillator, RTC_AF,
WKUP and VBUS signals removed from alternate functions and
moved to the “other functions” column in Table 8: STM32F20x pin and
ball definitions.
TRACESWO added in Figure 4: STM32F20x block diagram, Table 8:
STM32F20x pin and ball definitions, and Table 10: Alternate function
13-Jul-2010 4 mapping.
XTAL oscillator frequency updated on cover page, in Figure 4:
STM32F20x block diagram and in Section 3.11: External
interrupt/event controller (EXTI).
Updated list of peripherals used for boot mode in Section 3.13: Boot
modes.
Added Regulator bypass mode in Section 3.16: Voltage regulator, and
Section 6.3.4: Operating conditions at power-up / power-down
(regulator OFF).
Updated Section 3.17: Real-time clock (RTC), backup SRAM and
backup registers.
Added Note Note: in Section 3.18: Low-power modes.
Added SPI TI protocol in Section 3.23: Serial peripheral interface
(SPI).
DocID15818 Rev 11 165/178

177
Revision history STM32F20xxx
Table 95. Document revision history (continued)

Added USB OTG_FS features in Section 3.28: Universal serial bus on-
the-go full-speed (OTG_FS).
Updated VCAP_1 and VCAP_2 capacitor value to 2.2 µF in Figure 19:
Power supply scheme.
Removed DAC, modified ADC limitations, and updated I/O
compensation for 1.8 to 2.1 V range in Table 15: Limitations depending
on the operating power supply range.
Added VBORL, VBORM, VBORH and IRUSH in Table 19: Embedded reset
and power control block characteristics.
Removed table Typical current consumption in Sleep mode with Flash
memory in Deep power down mode. Merged typical and maximum
current consumption sections and added Table 21: Typical and
maximum current consumption in Run mode, code with data
processing running from Flash memory (ART accelerator disabled),
Table 20: Typical and maximum current consumption in Run mode,
code with data processing running from Flash memory (ART
accelerator enabled) or RAM, Table 22: Typical and maximum current
consumption in Sleep mode, Table 23: Typical and maximum current
consumptions in Stop mode, Table 24: Typical and maximum current
consumptions in Standby mode, and Table 25: Typical and maximum
current consumptions in VBAT mode.
Update Table 34: Main PLL characteristics and added Section 6.3.11:
PLL spread spectrum clock generation (SSCG) characteristics.
Added Note 8 for CIO in Table 48: I/O AC characteristics.
4 Updated Section 6.3.18: TIM timer characteristics.
13-Jul-2010 Added TNRST_OUT in Table 49: NRST pin characteristics.
(continued)
Updated Table 52: I2C characteristics.
Removed 8-bit data in and data out waveforms from Figure 47: ULPI
timing diagram.
Removed note related to ADC calibration in Table 67. Section 6.3.20:
12-bit ADC characteristics: ADC characteristics tables merged into one
single table; tables ADC conversion time and ADC accuracy removed.
Updated Table 68: DAC characteristics.
Updated Section 6.3.22: Temperature sensor characteristics and
Section 6.3.23: VBAT monitoring characteristics.
Update Section 6.3.26: Camera interface (DCMI) timing specifications.
Added Section 6.3.27: SD/SDIO MMC card host interface (SDIO)
characteristics, and Section 6.3.28: RTC characteristics.
Added Section 7.2: Thermal characteristics. Updated Table 91:
LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm package
mechanical data and Figure 83: LQFP176 - Low profile quad flat
package 24 × 24 × 1.4 mm, package outline.
Changed tape and reel code to TX in Table 94: Ordering information
scheme.
Added Table 101: Main applications versus package for STM32F2xxx
microcontrollers. Updated figures in Appendix A.2: USB OTG full
speed (FS) interface solutions and A.3: USB OTG high speed (HS)
interface solutions. Updated Figure 94: Audio player solution using
PLL, PLLI2S, USB and 1 crystal and Figure 95: Audio PLL (PLLI2S)
providing accurate I2S clock.
166/178 DocID15818 Rev 11


Update I/Os in Section : Features.

Added WLCSP64+2 package. Added note 1 related to LQFP176 on
cover page.
Added trademark for ART accelerator. Updated Section 3.2:
Adaptive real-time memory accelerator (ART Accelerator™).
Updated Figure 5: Multi-AHB matrix.
Added case of BOR inactivation using IRROFF on WLCSP devices in
Section 3.15: Power supply supervisor.
Reworked Section 3.16: Voltage regulator to clarify regulator off
modes. Renamed PDROFF, IRROFF in the whole document.
Added Section 3.19: VBAT operation.
Updated LIN and IrDA features for UART4/5 in Table 6: USART
feature comparison.
Table 8: STM32F20x pin and ball definitions: Modified VDD_3 pin, and
added note related to the FSMC_NL pin; renamed BYPASS-REG
REGOFF, and add IRROFF pin; renamed USART4/5 UART4/5.
USART4 pins renamed UART4.
Changed VSS_SA to VSS, and VDD_SA pin reserved for future use.
Updated maximum HSE crystal frequency to 26 MHz.
Section 6.2: Absolute maximum ratings: Updated VIN minimum and
maximum values and note related to five-volt tolerant inputs in
Table 11: Voltage characteristics. Updated IINJ(PIN) maximum values
and related notes in Table 12: Current characteristics.
25-Nov-2010 5 Updated VDDA minimum value in Table 14: General operating
conditions.
Added Note 2 and updated Maximum CPU frequency in Table 15:
Limitations depending on the operating power supply range, and
added Figure 21: Number of wait states versus fCPU and VDD range.
Added brownout level 1, 2, and 3 thresholds in Table 19: Embedded
reset and power control block characteristics.
Changed fOSC_IN maximum value in Table 30: HSE 4-26 MHz
oscillator characteristics.
Changed fPLL_IN maximum value in Table 34: Main PLL
characteristics, and updated jitter parameters in Table 35: PLLI2S
(audio PLL) characteristics.
Section 6.3.16: I/O port characteristics: updated VIH and VIL in
Table 48: I/O AC characteristics.
Added Note 1 below Table 47: Output voltage characteristics.
Updated RPD and RPU parameter description in Table 57: USB OTG
FS DC electrical characteristics.
Updated VREF+ minimum value in Table 66: ADC characteristics.
Updated Table 71: Embedded internal reference voltage.
Removed Ethernet and USB2 for 64-pin devices in Table 101: Main
applications versus package for STM32F2xxx microcontrollers.
Added A.2: USB OTG full speed (FS) interface solutions, removed
“OTG FS connection with external PHY” figure, updated Figure 87,
Figure 88, and Figure 90 to add STULPI01B.
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177

Changed datasheet status to “Full Datasheet”.

Introduced concept of SRAM1 and SRAM2.
LQFP176 package now in production and offered only for 256 Kbyte
and 1 Mbyte devices. Availability of WLCSP64+2 package limited to
512 Kbyte and 1 Mbyte devices.
Updated Figure 3: Compatible board design between STM32F10xx
and STM32F2xx for LQFP144 package and Figure 2: Compatible
board design between STM32F10xx and STM32F2xx for LQFP100
package.
Added camera interface for STM32F207Vx devices in Table 2:
STM32F205xx features and peripheral counts.
Removed 16 MHz internal RC oscillator accuracy in Section 3.12:
Clocks and startup.
Updated Section 3.16: Voltage regulator.
Modified I2S sampling frequency range in Section 3.12: Clocks and
startup, Section 3.24: Inter-integrated sound (I2S), and Section 3.30:
Audio PLL (PLLI2S).
Updated Section 3.17: Real-time clock (RTC), backup SRAM and
backup registers and description of TIM2 and TIM5 in Section 3.20.2:
General-purpose timers (TIMx).
Modified maximum baud rate (oversampling by 16) for USART1 in
Table 6: USART feature comparison.
Updated note related to RFU pin below Figure 12: STM32F20x
LQFP100 pinout, Figure 13: STM32F20x LQFP144 pinout, Figure 14:
STM32F20x LQFP176 pinout, Figure 15: STM32F20x UFBGA176
22-Apr-2011 6
ballout, and Table 8: STM32F20x pin and ball definitions.
In Table 8: STM32F20x pin and ball definitions,:changed I2S2_CK and
I2S3_CK to I2S2_SCK and I2S3_SCK, respectively; added PA15 and
TT (3.6 V tolerant I/O).
Added RTC_50Hz as PB15 alternate function in Table 8: STM32F20x
pin and ball definitions and Table 10: Alternate function mapping.
Removed ETH _RMII_TX_CLK for PC3/AF11 in Table 10: Alternate
function mapping.
Updated Table 11: Voltage characteristics and Table 12: Current
characteristics.
TSTG updated to –65 to +150 in Table 13: Thermal characteristics.
Added CEXT, ESL, and ESR in Table 14: General operating conditions
as well as Section 6.3.2: VCAP1/VCAP2 external capacitor.
Modified Note 4 in Table 15: Limitations depending on the operating
power supply range.
Updated Table 17: Operating conditions at power-up / power-down
(regulator ON), and Table 18: Operating conditions at power-up /
power-down (regulator OFF).
Added OSC_OUT pin in Figure 17: Pin loading conditions. and
Figure 18: Pin input voltage.
Updated Figure 19: Power supply scheme to add IRROFF and
REGOFF pins and modified notes.
Updated VPVD, VBOR1, VBOR2, VBOR3, TRSTTEMPO typical value, and
IRUSH, added ERUSH and Note 2 in Table 19: Embedded reset and
power control block characteristics.
168/178 DocID15818 Rev 11


Updated Typical and maximum current consumption conditions, as

well as Table 21: Typical and maximum current consumption in Run
mode, code with data processing running from Flash memory (ART
accelerator disabled) and Table 20: Typical and maximum current
consumption in Run mode, code with data processing running from
Flash memory (ART accelerator enabled) or RAM. Added Figure 23,
Figure 24, Figure 25, and Figure 26.
Updated Table 22: Typical and maximum current consumption in Sleep
mode, and added Figure 27 and Figure 28.
Updated Table 23: Typical and maximum current consumptions in Stop
mode. Added Figure 29: Typical current consumption vs temperature
in Stop mode.
Updated Table 24: Typical and maximum current consumptions in
Standby mode and Table 25: Typical and maximum current
consumptions in VBAT mode.
Updated On-chip peripheral current consumption conditions and
Table 26: Peripheral current consumption.
Updated tWUSTDBY and tWUSTOP, and added Note 3 in Table 27: Low-
power mode wakeup timings.
Maximum fHSE_ext and minimum tw(HSE) values updated in Table 28:
High-speed external user clock characteristics.
Updated C and gm in Table 30: HSE 4-26 MHz oscillator
characteristics. Updated RF, I2, gm, and tsu(LSE) in Table 31: LSE
oscillator characteristics (fLSE = 32.768 kHz).
6 Added Note 1 and updated ACCHSI, IDD(HSI, and tsu(HSI) in Table 32:
22-Apr-2011
(continued) HSI oscillator characteristics. Added Figure 34: ACCHSI versus
temperature.
Updated fLSI, tsu(LSI) and IDD(LSI) in Table 33: LSI oscillator
characteristics. Added Figure 35: ACCLSI versus temperature
Table 34: Main PLL characteristics: removed note 1, updated tLOCK,
jitter, IDD(PLL) and IDDA(PLL), added Note 2 for fPLL_IN minimum and
maximum values.
Table 35: PLLI2S (audio PLL) characteristics: removed note 1,
updated tLOCK, jitter, IDD(PLLI2S) and IDDA(PLLI2S), added Note 2 for
fPLLI2S_IN minimum and maximum values.
Added Note 1 in Table 36: SSCG parameters constraint.
Updated Table 37: Flash memory characteristics. Modified Table 38:
Flash memory programming and added Note 2 for tprog. Updated tprog
and added Note 1 in Table 39: Flash memory programming with VPP.
Modified Figure 39: Recommended NRST pin protection.
Updated Table 42: EMI characteristics and EMI monitoring conditions
in Section : Electromagnetic Interference (EMI)g. Added Note 2 related
to VESD(HBM)in Table 43: ESD absolute maximum ratings.
Updated Table 48: I/O AC characteristics.
Added Section 6.3.15: I/O current injection characteristics.
Modified maximum frequency values and conditions in Table 48: I/O
AC characteristics.
Updated tres(TIM) in Table 50: Characteristics of TIMx connected to the
APB1 domain. Modified tres(TIM) and fEXT Table 51: Characteristics of
TIMx connected to the APB2 domain.
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177

Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and

tf(SCK) to tf(SCL) in Table 52: I2C characteristics and in Figure 40: I2C
bus AC waveforms and measurement circuit.
Added Table 57: USB OTG FS DC electrical characteristics and
updated Table 58: USB OTG FS electrical characteristics.
Updated VDD minimum value in Table 62: Ethernet DC electrical
characteristics.
Updated Table 66: ADC characteristics and RAIN equation.
Updated RAIN equation. Updated Table 68: DAC characteristics.
Updated tSTART in Table 69: TS characteristics.
Updated R typical value in Table 70: VBAT monitoring characteristics.
Updated Table 71: Embedded internal reference voltage.
Modified FSMC_NOE waveform in Figure 56: Asynchronous non-
multiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of
FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK
period, changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-
AIV), td(CLKH-NOEH) to td(CLKL-NOEH), and td(CLKH-NWEH) to td(CLKL-
NWEH), and updated data latency from 1 to 0 in Figure 60:
6 Synchronous multiplexed NOR/PSRAM read timings, Figure 61:
22-Apr-2011
(continued) Synchronous multiplexed PSRAM write timings, Figure 62:
Synchronous non-multiplexed NOR/PSRAM read timings, and
Figure 63: Synchronous non-multiplexed PSRAM write timings,
Changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-AIV),
td(CLKH-NOEH) to td(CLKL-NOEH), td(CLKH-NWEH) to td(CLKL-NWEH), and
modified tw(CLK) minimum value in Table 76, Table 77, Table 78, and
Table 79.
Updated note 2 in Table 72, Table 73, Table 74, Table 75, Table 76,
Table 77, Table 78, and Table 79.
Modified th(NIOWR-D) in Figure 69: PC Card/CompactFlash controller
waveforms for I/O space write access.
Modified FSMC_NCEx signal in Figure 70: NAND controller
waveforms for read access, Figure 71: NAND controller waveforms for
write access, Figure 72: NAND controller waveforms for common
memory read access, and Figure 73: NAND controller waveforms for
common memory write access
Specified Full speed (FS) mode for Figure 89: USB OTG HS
peripheral-only connection in FS mode and Figure 90: USB OTG HS
host-only connection in FS mode.
170/178 DocID15818 Rev 11


Added SDIO in Table 2: STM32F205xx features and peripheral counts.

Updated VIN for 5V tolerant pins in Table 11: Voltage characteristics.
Updated jitter parameters description in Table 34: Main PLL
characteristics.
Remove jitter values for system clock in Table 35: PLLI2S (audio PLL)
characteristics.
Updated Table 42: EMI characteristics.
Update Note 2 in Table 52: I2C characteristics.
Updated Avg_Slope typical value and TS_temp minimum value in
14-Jun-2011 7 Table 69: TS characteristics.
Updated TS_vbat minimum value in Table 70: VBAT monitoring
characteristics.
Updated TS_vrefint mimimum value in Table 71: Embedded internal
reference voltage.
Added Software option in Section 8: Part numbering.
In Table 101: Main applications versus package for STM32F2xxx
microcontrollers, renamed USB1 and USB2, USB OTG FS and USB
OTG HS, respectively; and removed USB OTG FS and camera
interface for 64-pin package; added USB OTG HS on 64-pin package;
added Note 1 and Note 2.
Updated SDIO register addresses in Figure 16: Memory map.
Updated Figure 3: Compatible board design between STM32F10xx
and STM32F2xx for LQFP144 package, Figure 2: Compatible board
design between STM32F10xx and STM32F2xx for LQFP100 package,
Figure 1: Compatible board design between STM32F10xx and
STM32F2xx for LQFP64 package, and added Figure 4: Compatible
board design between STM32F10xx and STM32F2xx for LQFP176
package.
Updated Section 3.3: Memory protection unit.
Updated Section 3.6: Embedded SRAM.
Updated Section 3.28: Universal serial bus on-the-go full-speed
(OTG_FS) to remove external FS OTG PHY support.
20-Dec-2011 8 In Table 8: STM32F20x pin and ball definitions: changed SPI2_MCK
and SPI3_MCK to I2S2_MCK and I2S3_MCK, respectively. Added
ETH _RMII_TX_EN atlternate function to PG11. Added EVENTOUT in
the list of alternate functions for I/O pin/balls. Removed
OTG_FS_SDA, OTG_FS_SCL and OTG_FS_INTN alternate
functions.
In Table 10: Alternate function mapping: changed I2S3_SCK to
I2S3_MCK for PC7/AF6, added FSMC_NCE3 for PG9, FSMC_NE3
for PG10, and FSMC_NCE2 for PD7. Removed OTG_FS_SDA,
OTG_FS_SCL and OTG_FS_INTN alternate functions. Changed
I2S3_SCK into I2S3_MCK for PC7/AF6. Updated peripherals
corresponding to AF12.
Removed CEXT and ESR from Table 14: General operating
conditions.
DocID15818 Rev 11 171/178

177

Added maximum power consumption at TA=25 °C in Table 23: Typical

and maximum current consumptions in Stop mode.
Updated md minimum value in Table 36: SSCG parameters constraint.
Added examples in Section 6.3.11: PLL spread spectrum clock
generation (SSCG) characteristics.
Updated Table 54: SPI characteristics and Table 55: I2S
characteristics.
Updated Figure 47: ULPI timing diagram and Table 61: ULPI timing.
Updated Table 63: Dynamics characteristics: Ethernet MAC signals for
SMI, Table 64: Dynamics characteristics: Ethernet MAC signals for
RMII, and Table 65: Dynamics characteristics: Ethernet MAC signals
for MII.
Section 6.3.25: FSMC characteristics: updated Table 72 toTable 83,
changed CL value to 30 pF, and modified FSMC configuration for
asynchronous timings and waveforms. Updated Figure 61:
Synchronous multiplexed PSRAM write timings.
8
20-Dec-2011 UpdatedTable 84: DCMI characteristics.
(continued)
Updated Table 92: UFBGA176+25 - ultra thin fine pitch ball grid array
10 × 10 × 0.6 mm mechanical data.
Updated Table 94: Ordering information scheme.
Appendix A.2: USB OTG full speed (FS) interface solutions: updated
Figure 87: USB OTG FS (full speed) host-only connection and added
Note 2, updated Figure 88: OTG FS (full speed) connection dual-role
with internal PHY and added Note 3 and Note 4, modified Figure 89:
OTG HS (high speed) device connection, host and dual-role in high-
speed mode with external PHY and added Note 2.
Appendix A.3: USB OTG high speed (HS) interface solutions:
removed figures USB OTG HS device-only connection in FS mode and
USB OTG HS host-only connection in FS mode,updated Figure 89:
OTG HS (high speed) device connection, host and dual-role in high-
speed mode with external PHY.
Added Appendix A.4: Ethernet interface solutions.
Updated disclaimer on last page.
Updated VDD minimum value in Section 2: Description.
Updated number of USB OTG HS and FS, modified packages for
STM32F207Ix part numbers, added Note 1 related to FSMC and
Note 2 related to SPI/I2S, and updated Note 3 in Table 2:
STM32F205xx features and peripheral counts and Table 3:
STM32F207xx features and peripheral counts.
Added Note 2 and update TIM5 in Figure 4: STM32F20x block
24-Apr-2012 9 diagram.
Updated maximum number of maskable interrupts in Section 3.10:
Nested vectored interrupt controller (NVIC).
Updated VDD minimum value in Section 3.14: Power supply schemes.
Updated Note a in Section 3.16.1: Regulator ON.
Removed STM32F205xx in Section 3.28: Universal serial bus on-the-
go full-speed (OTG_FS).
172/178 DocID15818 Rev 11


Removed support of I2C for OTG PHY in Section 3.29: Universal serial
bus on-the-go high-speed (OTG_HS).
Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 8:
STM32F20x pin and ball definitions and Table 10: Alternate function
mapping.
Renamed PH10 alternate function into TIM5_CH1 in Table 10:
Alternate function mapping.
Added Table 9: FSMC pin definition.
Updated Note 2 in Table 14: General operating conditions, Note 2 in
Table 15: Limitations depending on the operating power supply range,
and Note 1 below Figure 21: Number of wait states versus fCPU and
VDD range.
Updated VPOR/PDR in Table 19: Embedded reset and power control
block characteristics.
Updated typical values in Table 24: Typical and maximum current
consumptions in Standby mode and Table 25: Typical and maximum
current consumptions in VBAT mode.
Updated Table 30: HSE 4-26 MHz oscillator characteristics and
Table 31: LSE oscillator characteristics (fLSE = 32.768 kHz).
9 Updated Table 37: Flash memory characteristics, Table 38: Flash
24-Apr-2012
(continued) memory programming, and Table 39: Flash memory programming with
VPP.
Updated Section : Output driving current.
Updated Note 3 and removed note related to minimum hold time value
in Table 52: I2C characteristics.
Updated Table 64: Dynamics characteristics: Ethernet MAC signals for
RMII.
Updated Note 1, CADC, IVREF+, and IVDDA in Table 66: ADC
characteristics.
Updated Note 3 and note concerning ADC accuracy vs. negative
injection current in Table 67: ADC accuracy.
Updated Note 1 in Table 68: DAC characteristics.
Updated Section Figure 85.: UFBGA176+25 - ultra thin fine pitch ball
grid array 10 × 10 × 0.6 mm, package outline.
Appendix A.1: Main applications versus package: removed number of
address lines for FSMC/NAND in Table 101: Main applications versus
package for STM32F2xxx microcontrollers.
Appendix A.4: Ethernet interface solutions: updated Figure 92:
Complete audio player solution 1 and Figure 93: Complete audio
player solution 2.
DocID15818 Rev 11 173/178

177

Changed minimum supply voltage from 1.65 to 1.8 V.

Updated number of AHB buses in Section 2: Description and
Section 3.12: Clocks and startup.
Removed Figure 4. Compatible board design between STM32F10xx
and STM32F2xx for LQFP176 package.
Updated Note 2 below Figure 4: STM32F20x block diagram.
Changed System memory to System memory + OTP in Figure 16:
Memory map.
Added Note 1 below Table 16: VCAP1/VCAP2 operating conditions.
Updated VDDA and VREF+ decouping capacitor in Figure 19: Power
supply scheme and updated Note 3.
Changed simplex mode into half-duplex mode in Section 3.24: Inter-
integrated sound (I2S).
Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and
DAC_OUT2, respectively.Changed TIM2_CH1/TIM2_ETR into
TIM2_CH1_ETR for PA0 and PA5 in Table 10: Alternate function
mapping.
Updated note applying to IDD (external clock and all peripheral
disabled) in Table 21: Typical and maximum current consumption in
Run mode, code with data processing running from Flash memory
(ART accelerator disabled). Updated Note 3 below Table 22: Typical
and maximum current consumption in Sleep mode.
Removed fHSE_ext typical value in Table 28: High-speed external user
29-Oct-2012 10
clock characteristics.
Updated master I2S clock jitter conditions and vlaues in Table 35:
PLLI2S (audio PLL) characteristics.
Updated equations in Section 6.3.11: PLL spread spectrum clock
generation (SSCG) characteristics.
Swapped TTL and CMOS port conditions for VOL and VOH in Table 47:
Output voltage characteristics.
Updated VIL(NRST) and VIH(NRST) in Table 49: NRST pin
characteristics.
Updated Table 54: SPI characteristics and Table 55: I2S
characteristics. Removed note 1 related to measurement points below
Figure 42: SPI timing diagram - slave mode and CPHA = 1, Figure 43:
SPI timing diagram - master mode, and Figure 44: I2S slave timing
diagram (Philips protocol)(1).
Updated tHC in Table 61: ULPI timing.
Updated Figure 48: Ethernet SMI timing diagram, Table 63: Dynamics
characteristics: Ethernet MAC signals for SMI and Table 65: Dynamics
characteristics: Ethernet MAC signals for MII.
Update fTRIG in Table 66: ADC characteristics.
Updated IDDA description in Table 68: DAC characteristics.
Updated note below Figure 53: Power supply and reference
decoupling (VREF+ not connected to VDDA) and Figure 54: Power
supply and reference decoupling (VREF+ connected to VDDA).
174/178 DocID15818 Rev 11


Replaced td(CLKL-NOEL) by td(CLKH-NOEL) in Table 76: Synchronous

multiplexed NOR/PSRAM read timings, Table 78: Synchronous non-
multiplexed NOR/PSRAM read timings, Figure 60: Synchronous
multiplexed NOR/PSRAM read timings and Figure 62: Synchronous
10 non-multiplexed NOR/PSRAM read timings.
29-Oct-2012
(continued) Added Figure 84: LQFP176 recommended footprint.
Added Note 2 below Figure 86: Regulator OFF/internal reset ON.
Updated device subfamily in Table 94: Ordering information scheme.
Remove reference to note 2 for USB IOTG FS in Table 101: Main
applications versus package for STM32F2xxx microcontrollers.
DocID15818 Rev 11 175/178

177

In the whole document, updated notes related to WLCSP64+2 usage

with IRROFF set to VDD. Updated Section 3.14: Power supply
schemes, Section 3.15: Power supply supervisor, Section 3.16.1:
Regulator ON and Section 3.16.2: Regulator OFF. Added
Section 3.16.3: Regulator ON/OFF and internal reset ON/OFF
availability. Added note related to WLCSP64+2 package.
Restructured RTC features and added reference clock detection in
Section 3.17: Real-time clock (RTC), backup SRAM and backup
registers.
Added note indicating the package view below Figure 10: STM32F20x
LQFP64 pinout, Figure 12: STM32F20x LQFP100 pinout, Figure 13:
STM32F20x LQFP144 pinout, and Figure 14: STM32F20x LQFP176
pinout.
Added Table 7: Legend/abbreviations used in the pinout table. Table 8:
STM32F20x pin and ball definitions: content reformatted; removed
indeces on VSS and VDD; updated PA4, PA5, PA6, PC4, BOOT0;
replaced DCMI_12 by DCMI_D12, TIM8_CHIN by TIM8_CH1N,
ETH_MII_RX_D0 by ETH_MII_RXD0, ETH_MII_RX_D1 by
ETH_MII_RXD1, ETH_RMII_RX_D0 by ETH_RMII_RXD0,
ETH_RMII_RX_D1 by ETH_RMII_RXD1, and RMII_CRS_DV by
ETH_RMII_CRS_DV.
Table 10: Alternate function mapping: replaced FSMC_BLN1 by
04-Nov-2013 11 FSMC_NBL1, added EVENTOUT as AF15 alternated fucntion for
PC13, PC14, PC15, PH0, PH1, and PI8.
Updated Figure 17: Pin loading conditions and Figure 18: Pin input
voltage.
Added VIN in Table 14: General operating conditions.
Removed note applying to VPOR/PDR minimum value in Table 19:
Embedded reset and power control block characteristics.
Updated notes related to CL1 and CL2 in Section : Low-speed external
clock generated from a crystal/ceramic resonator.
Updated conditions in Table 41: EMS characteristics. Updated
Table 42: EMI characteristics. Updated VIL, VIH and VHys in Table 46:
I/O static characteristics. Added Figure : Output driving current and
updated Figure 38: I/O AC characteristics definition.
Updated VIL(NRST) and VIH(NRST) in Table 49: NRST pin
characteristics, updated Figure 38: I/O AC characteristics definition.
Removed tests conditions in Section : I2C interface characteristics.
Updated Table 52: I2C characteristics and Figure 40: I2C bus AC
waveforms and measurement circuit.
Updated IVREF+ and IVDDA in Table 66: ADC characteristics. Updated
Offset comments in Table 68: DAC characteristics.
Updated minimum th(CLKH-DV) value in Table 78: Synchronous non-
multiplexed NOR/PSRAM read timings.
176/178 DocID15818 Rev 11


Removed Appendix A Application block diagrams.

Updated Figure 76: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat
package outline and Table 87: LQFP64 – 10 x 10 mm 64 pin low-
profile quad flat package mechanical data. Updated Figure 79:
11 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline,
04-Nov-2013 Figure 81: LQFP144, 20 x 20 mm, 144-pin low-profile quad flat
(continued)
package outline, Figure 83: LQFP176 - Low profile quad flat package
24 × 24 × 1.4 mm, package outline. Updated Figure 85:
UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm,
package outline and Figure 85: UFBGA176+25 - ultra thin fine pitch
ball grid array 10 × 10 × 0.6 mm, package outline.
DocID15818 Rev 11 177/178

177
STM32F20xxx
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178/178 DocID15818 Rev 11

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STM32F205xx

• Core: ARM 32-bit Cortex™-M3 CPU (120 MHz

up to 120 MHz, each with up to 4 STM32F205RB, STM32F205RC, STM32F205RE,

• Debug mode: Serial wire debug (SWD), JTAG, STM32F207xx

November 2013 DocID15818 Rev 11 1/178

2/178 DocID15818 Rev 11

3.20.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

DocID15818 Rev 11 3/178

6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

4/178 DocID15818 Rev 11

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

DocID15818 Rev 11 5/178

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

6/178 DocID15818 Rev 11

Table 47. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

DocID15818 Rev 11 7/178

Figure 1. Compatible board design between STM32F10xx and STM32F2xx

8/178 DocID15818 Rev 11

Figure 38. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

DocID15818 Rev 11 9/178

10/178 DocID15818 Rev 11

DocID15818 Rev 11 11/178

System 64 96 128 64 96 128 96 128

FSMC memory controller No Yes(1)

Random number generator Yes

USB OTG HS Yes

12-bit DAC Yes

Operating voltage 1.8 V to 3.6 V(3)

Ambient temperatures: –40 to +85 °C /–40 to +105 °C

Table 3. STM32F207xx features and peripheral counts

FSMC memory controller Yes(1)

Random number generator Yes

USB OTG FS Yes

USB OTG HS Yes

Camera interface Yes

GPIOs 82 114 140

12-bit DAC Yes

Maximum CPU frequency 120 MHz

Operating voltage 1.8 V to 3.6 V(3)

Ambient temperatures: –40 to +85 °C/–40 to +105 °C

2.1 Full compatibility throughout the family

Figure 1. Compatible board design between STM32F10xx and STM32F2xx

DocID15818 Rev 11 15/178

Figure 2. Compatible board design between STM32F10xx and STM32F2xx

Figure 3. Compatible board design between STM32F10xx and STM32F2xx

1. RFU = reserved for future use.

16/178 DocID15818 Rev 11

Figure 4. STM32F20x block diagram

AHB bus-matrix 8S7M

DP, DM USB DMA/

TIM2 32b 4 channels, ETR as AF

140 AF EXT IT. WKUP 16b

CMD, CK as AF SDIO / MMC 1 channel as AF

4 compl. channels (TIM1_CH[1:4]N)

RX, TX, CK, smcard SPI2/I2S2

smcard SPI3/I2S3 MOSI/DOUT, MISO/DIN, SCK/CK

16b NSS/WS, MCK as AF