En DM00090510 PDF

STM32F072x8 STM32F072xB
ARM-based 32-bit MCU, up to 128 KB Flash, crystal-less USB

FS 2.0, CAN, 12 timers, ADC, DAC & comm. interfaces, 2.0 - 3.6 V
Datasheet - production data
Features )%*$

Core: ARM 32-bit Cortex -M0 CPU,
frequency up to 48 MHz LQFP100 14x14 mm UFQFPN48 UFBGA100 WLCSP49
LQFP64 10x10 mm 7x7 mm 7x7 mm 3.3x3.1 mm
Memories LQFP48 7x7 mm UFBGA64
5x5 mm
64 to 128 Kbytes of Flash memory
16 Kbytes of SRAM with HW parity Calendar RTC with alarm and periodic wakeup
from Stop/Standby
CRC calculation unit
12 timers
Reset and power management
One 16-bit advanced-control timer for
Digital and I/O supply: VDD = 2.0 V to 3.6 V
six-channel PWM output
Analog supply: VDDA = VDD to 3.6 V
One 32-bit and seven 16-bit timers, with up
Selected I/Os: VDDIO2 = 1.65 V to 3.6 V to four IC/OC, OCN, usable for IR control
Power-on/Power down reset (POR/PDR) decoding or DAC control
Programmable voltage detector (PVD) Independent and system watchdog timers
Low power modes: Sleep, Stop, Standby SysTick timer
VBAT supply for RTC and backup registers Communication interfaces
Clock management Two I2C interfaces supporting Fast Mode
4 to 32 MHz crystal oscillator Plus (1 Mbit/s) with 20 mA current sink, one
32 kHz oscillator for RTC with calibration supporting SMBus/PMBus and wakeup
Internal 8 MHz RC with x6 PLL option Four USARTs supporting master
Internal 40 kHz RC oscillator synchronous SPI and modem control, two
with ISO7816 interface, LIN, IrDA, auto
Internal 48 MHz oscillator with automatic
baud rate detection and wakeup feature
trimming based on ext. synchronization
Two SPIs (18 Mbit/s) with 4 to 16
Up to 87 fast I/Os programmable bit frames, and with I2S
All mappable on external interrupt vectors interface multiplexed
Up to 68 I/Os with 5V tolerant capability CAN interface
and 19 with independent supply VDDIO2 USB 2.0 full-speed interface, able to run
Seven-channel DMA controller from internal 48 MHz oscillator and with
One 12-bit, 1.0 s ADC (up to 16 channels) BCD and LPM support
Conversion range: 0 to 3.6 V HDMI CEC wakeup on header reception
Separate analog supply: 2.4 V to 3.6 V Serial wire debug (SWD)
One 12-bit D/A converter (with 2 channels) 96-bit unique ID
Two fast low-power analog comparators with All packages ECOPACK2
programmable input and output
Up to 24 capacitive sensing channels for Table 1. Device summary
touchkey, linear and rotary touch sensors Reference Part number
STM32F072x8 STM32F072C8, STM32F072R8, STM32F072V8,

STM32F072xB STM32F072CB, STM32F072RB, STM32F072VB
January 2017 DocID025004 Rev 5 1/128

This is information on a product in full production. www.st.com
Contents STM32F072x8 STM32F072xB
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 ARM-Cortex-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 22
3.14.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23
3.16 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25
3.18 Serial peripheral interface (SPI) / Inter-integrated sound interface (I2S) . 26
3.19 High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.20 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.21 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.22 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.23 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 54
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 54
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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Contents STM32F072x8 STM32F072xB
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.16 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.17 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.18 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.20 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.21 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.22 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.1 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.3 UFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.4 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.5 WLCSP49 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
7.6 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
7.7 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
7.8 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.8.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.8.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 121
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
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STM32F072x8 STM32F072xB List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32F072x8/xB family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . 11
Table 3. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Capacitive sensing GPIOs available on STM32F072x8/xB devices. . . . . . . . . . . . . . . . . . 20
Table 6. Number of capacitive sensing channels available
on STM32F072x8/xB devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. STM32F072x8/xB I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10. STM32F072x8/xB USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. STM32F072x8/xB SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. STM32F072x8/xB pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14. Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 41
Table 15. Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 42
Table 16. Alternate functions selected through GPIOC_AFR registers for port C . . . . . . . . . . . . . . . 43
Table 17. Alternate functions selected through GPIOD_AFR registers for port D . . . . . . . . . . . . . . . 43
Table 18. Alternate functions selected through GPIOE_AFR registers for port E . . . . . . . . . . . . . . . 44
Table 19. Alternate functions available on port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 20. STM32F072x8/xB peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 27. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 28. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 29. Typical and maximum current consumption from VDD supply at VDD = 3.6 V . . . . . . . . . . 56
Table 30. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . 58
Table 31. Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 59
Table 32. Typical and maximum current consumption from the VBAT supply. . . . . . . . . . . . . . . . . . . 60
Table 33. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 34. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 35. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 36. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 37. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 38. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 39. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 41. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 42. HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 43. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 44. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 45. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 46. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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List of tables STM32F072x8 STM32F072xB
Table 47. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 48. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 49. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 50. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 51. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 52. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 53. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 54. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 55. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 56. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 57. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 58. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 59. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 60. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 61. Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 62. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 63. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 64. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 65. IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 66. WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 67. I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 68. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 69. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 70. USB electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 71. UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 72. UFBGA100 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 73. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 74. UFBGA64 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 75. UFBGA64 recommended PCB design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 76. LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 77. WLCSP49 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 78. LQFP48 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 79. UFQFPN48 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 80. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 81. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 82. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
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STM32F072x8 STM32F072xB List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 3. UFBGA100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 4. LQFP100 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5. UFBGA64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. LQFP64 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7. LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 8. UFQFPN48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 9. WLCSP49 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 10. STM32F072xB memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 13. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 17. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 19. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 71
Figure 20. HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 21. HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 22. TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 26. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 28. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 29. Maximum VREFINT scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 30. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 31. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 32. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 33. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 34. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 35. UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 36. Recommended footprint for UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 37. UFBGA100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 38. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 39. Recommended footprint for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 40. LQFP100 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 41. UFBGA64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 42. Recommended footprint for UFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 43. UFBGA64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 44. LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 45. Recommended footprint for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 46. LQFP64 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 47. WLCSP49 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 48. WLCSP49 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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8
List of figures STM32F072x8 STM32F072xB
Figure 49. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Figure 50. Recommended footprint for LQFP48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 51. LQFP48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 52. UFQFPN48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 53. Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 54. UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 55. LQFP64 PD max versus TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
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STM32F072x8 STM32F072xB Introduction
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F072x8/xB microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM Cortex-M0 core, please refer to the Cortex-M0 Technical
Reference Manual, available from the www.arm.com website.
DocID025004 Rev 5 9/128

27
Description STM32F072x8 STM32F072xB
2 Description
The STM32F072x8/xB microcontrollers incorporate the high-performance

ARM Cortex-M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed
embedded memories (up to 128 Kbytes of Flash memory and 16 Kbytes of SRAM), and an
extensive range of enhanced peripherals and I/Os. All devices offer standard
communication interfaces (two I2Cs, two SPI/I2S, one HDMI CEC and four USARTs), one
USB Full-speed device (crystal-less), one CAN, one 12-bit ADC, one 12-bit DAC with two
channels, seven 16-bit timers, one 32-bit timer and an advanced-control PWM timer.
The STM32F072x8/xB microcontrollers operate in the -40 to +85 C and -40 to +105 C
temperature ranges, from a 2.0 to 3.6 V power supply. A comprehensive set of
power-saving modes allows the design of low-power applications.
The STM32F072x8/xB microcontrollers include devices in seven different packages ranging
from 48 pins to 100 pins with a die form also available upon request. Depending on the
device chosen, different sets of peripherals are included.
These features make the STM32F072x8/xB microcontrollers suitable for a wide range of
applications such as application control and user interfaces, hand-held equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms and HVACs.
10/128 DocID025004 Rev 5

STM32F072x8 STM32F072xB Description
Table 2. STM32F072x8/xB family device features and peripheral counts

Peripheral STM32F072Cx STM32F072Rx STM32F072Vx
Flash memory (Kbyte) 64 128 64 128 64 128

SRAM (Kbyte) 16
Advanced
1 (16-bit)
control
Timers General 5 (16-bit)
purpose 1 (32-bit)
Basic 2 (16-bit)
SPI [I2S](1) 2 [2]
2C
I 2
Comm. USART 4
interfaces CAN 1
USB 1
CEC 1
12-bit ADC 1 1
(number of channels) (10 ext. + 3 int.) (16 ext. + 3 int.)
12-bit DAC 1
(number of channels) (2)
Analog comparator 2
GPIOs 37 51 87
Capacitive sensing
17 18 24
channels
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Ambient operating temperature: -40C to 85C / -40C to 105C
Operating temperature
Junction temperature: -40C to 105C / -40C to 125C
LQFP48
LQFP64 LQFP100
Packages UFQFPN48
UFBGA64 UFBGA100
WLCSP49
1. The SPI interface can be used either in SPI mode or in I2S audio mode.
DocID025004 Rev 5 11/128

27
Description STM32F072x8 STM32F072xB
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12/128 DocID025004 Rev 5

STM32F072x8 STM32F072xB Functional overview
3 Functional overview
Figure 1 shows the general block diagram of the STM32F072x8/xB devices.
3.1 ARM-Cortex-M0 core

The ARM Cortex-M0 is a generation of ARM 32-bit RISC processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex-M0 processors feature exceptional code-efficiency, delivering the high
performance expected from an ARM core, with memory sizes usually associated with 8- and
16-bit devices.
The STM32F072x8/xB devices embed ARM core and are compatible with all ARM tools and
software.
3.2 Memories
The device has the following features:
16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
The non-volatile memory is divided into two arrays:
64 to 128 Kbytes of embedded Flash memory for programs and data
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected

Level 2: chip readout protection, debug features (Cortex -M0 serial wire) and
boot in RAM selection disabled
3.3 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
boot from User Flash memory
boot from System Memory
boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART on pins PA14/PA15, or PA9/PA10 or I2C on pins PB6/PB7 or through the USB
DFU interface.
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27
Functional overview STM32F072x8 STM32F072xB
3.4 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.5 Power management
3.5.1 Power supply schemes

VDD = VDDIO1 = 2.0 to 3.6 V: external power supply for I/Os (VDDIO1) and the internal
regulator. It is provided externally through VDD pins.
VDDA = from VDD to 3.6 V: external analog power supply for ADC, DAC, Reset blocks,
RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC
are used). It is provided externally through VDDA pin. The VDDA voltage level must be
always greater or equal to the VDD voltage level and must be established first.
VDDIO2 = 1.65 to 3.6 V: external power supply for marked I/Os. VDDIO2 is provided
externally through the VDDIO2 pin. The VDDIO2 voltage level is completely independent
from VDD or VDDA, but it must not be provided without a valid supply on VDD. The
VDDIO2 supply is monitored and compared with the internal reference voltage
(VREFINT). When the VDDIO2 is below this threshold, all the I/Os supplied from this rail
are disabled by hardware. The output of this comparator is connected to EXTI line 31
and it can be used to generate an interrupt. Refer to the pinout diagrams or tables for
concerned I/Os list.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 13: Power supply scheme.
3.5.2 Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
14/128 DocID025004 Rev 5

threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
3.5.3 Voltage regulator

The regulator has two operating modes and it is always enabled after reset.
Main (MR) is used in normal operating mode (Run).
Low power (LPR) can be used in Stop mode where the power demand is reduced.
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
3.5.4 Low-power modes

The STM32F072x8/xB microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC, I2C1, USART1,
USART2, USB, COMPx, VDDIO2 supply comparator or the CEC.
The CEC, USART1, USART2 and I2C1 peripherals can be configured to enable the
HSI RC oscillator so as to get clock for processing incoming data. If this is used when
the voltage regulator is put in low power mode, the regulator is first switched to normal
mode before the clock is provided to the given peripheral.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.6 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
DocID025004 Rev 5 15/128

27
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Figure 2. Clock tree
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Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
16/128 DocID025004 Rev 5

Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL
input source. This oscillator can be automatically fine-trimmed by the means of the CRS
peripheral using the external synchronization.
3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.8 Direct memory access controller (DMA)

The 7-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers
(except TIM14), DAC and ADC.
3.9 Interrupts and events
3.9.1 Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to

32 maskable interrupt channels (not including the 16 interrupt lines of Cortex -M0) and 4
priority levels.
Closely coupled NVIC gives low latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
DocID025004 Rev 5 17/128

27
3.9.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 32 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 87
GPIOs can be connected to the 16 external interrupt lines.
3.10 Analog-to-digital converter (ADC)

The 12-bit analog-to-digital converter has up to 16 external and 3 internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1 Temperature sensor

The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3. Temperature sensor calibration values

Calibration value name Description Memory address
TS ADC raw data acquired at a

TS_CAL1 temperature of 30 C ( 5 C), 0x1FFF F7B8 - 0x1FFF F7B9
VDDA= 3.3 V ( 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 110 C ( 5 C), 0x1FFF F7C2 - 0x1FFF F7C3
VDDA= 3.3 V ( 10 mV)
3.10.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and comparators. VREFINT is internally connected to the ADC_IN17 input channel. The
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precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area. It is accessible in read-only mode.
Table 4. Internal voltage reference calibration values

Calibration value name Description Memory address
Raw data acquired at a

VREFINT_CAL temperature of 30 C ( 5 C), 0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V ( 10 mV)
3.10.3 VBAT battery voltage monitoring

This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.11 Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert digital signals into analog
voltage signal outputs. The chosen design structure is composed of integrated resistor
strings and an amplifier in non-inverting configuration.
This digital Interface supports the following features:
8-bit or 12-bit monotonic output
Left or right data alignment in 12-bit mode
Synchronized update capability
Noise-wave generation
Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channel
External triggers for conversion
Six DAC trigger inputs are used in the device. The DAC is triggered through the timer trigger
outputs and the DAC interface is generating its own DMA requests.
3.12 Comparators (COMP)

The device embeds two fast rail-to-rail low-power comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low power) and
with selectable output polarity.
The reference voltage can be one of the following:
External I/O
DAC output pins
Internal reference voltage or submultiple (1/4, 1/2, 3/4).Refer to Table 28: Embedded
internal reference voltage for the value and precision of the internal reference voltage.
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27
Both comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined into a window comparator.
3.13 Touch sensing controller (TSC)

The STM32F072x8/xB devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 24 capacitive sensing channels
distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists in
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
For operation, one capacitive sensing GPIO in each group is connected to an external
capacitor and cannot be used as effective touch sensing channel.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 5. Capacitive sensing GPIOs available on STM32F072x8/xB devices

Capacitive sensing Pin Capacitive sensing Pin
Group Group
signal name name signal name name
TSC_G1_IO1 PA0 TSC_G5_IO1 PB3

1 5
2 6
TSC_G3_IO1 PC5 TSC_G7_IO1 PE2
TSC_G3_IO2 PB0 TSC_G7_IO2 PE3
3 7
TSC_G4_IO1 PA9 TSC_G8_IO1 PD12
4 8
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Table 6. Number of capacitive sensing channels available

on STM32F072x8/xB devices
Number of capacitive sensing channels
Analog I/O group
STM32F072Vx STM32F072Rx STM32F072Cx
G1 3 3 3
G2 3 3 3
G3 3 3 2
G4 3 3 3
G5 3 3 3
G6 3 3 3
G7 3 0 0
G8 3 0 0
Number of capacitive
24 18 17
sensing channels
3.14 Timers and watchdogs

The STM32F072x8/xB devices include up to six general-purpose timers, two basic timers
and an advanced control timer.
Table 7 compares the features of the different timers.
Table 7. Timer feature comparison

DMA
Timer Counter Counter Prescaler Capture/compare Complementary
Timer request
type resolution type factor channels outputs
generation
Advanced Up, down, integer from

TIM1 16-bit Yes 4 3
control up/down 1 to 65536
Up, down, integer from
TIM2 32-bit Yes 4 -
up/down 1 to 65536
Up, down, integer from
TIM3 16-bit Yes 4 -
up/down 1 to 65536
General integer from
TIM14 16-bit Up No 1 -
purpose 1 to 65536
integer from
TIM15 16-bit Up Yes 2 1
1 to 65536
TIM16 integer from
16-bit Up Yes 1 1
TIM17 1 to 65536
TIM6 integer from
Basic 16-bit Up Yes - -
TIM7 1 to 65536
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27
3.14.1 Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
input capture
output compare
PWM generation (edge or center-aligned modes)
one-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17)

There are six synchronizable general-purpose timers embedded in the STM32F072x8/xB
devices (see Table 7 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3
STM32F072x8/xB devices feature two synchronizable 4-channel general-purpose timers.
TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM15, TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
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TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate
withTIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
3.14.3 Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.14.4 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.14.5 System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
3.14.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
a 24-bit down counter
autoreload capability
maskable system interrupt generation when the counter reaches 0
programmable clock source (HCLK or HCLK/8)
3.15 Real-time clock (RTC) and backup registers

The RTC and the five backup registers are supplied through a switch that takes power either
on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or at wake up from Standby mode.
DocID025004 Rev 5 23/128

27
The RTC is an independent BCD timer/counter. Its main features are the following:
calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
automatic correction for 28, 29 (leap year), 30, and 31 day of the month
programmable alarm with wake up from Stop and Standby mode capability
Periodic wakeup unit with programmable resolution and period.
on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock
digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection
timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection
reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
The RTC clock sources can be:
a 32.768 kHz external crystal
a resonator or oscillator
the internal low-power RC oscillator (typical frequency of 40 kHz)
the high-speed external clock divided by 32
3.16 Inter-integrated circuit interface (I2C)

Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode
Plus (up to 1 Mbit/s) with 20 mA output drive on most of the associated I/Os.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two
addresses, one with configurable mask). They also include programmable analog and
digital noise filters.
Table 8. Comparison of I2C analog and digital filters

Aspect Analog filter Digital filter
Pulse width of Programmable length from 1 to 15

50 ns
suppressed spikes I2Cx peripheral clocks
Extra filtering capability vs.
Benefits Available in Stop mode standard requirements
Stable length
Wakeup from Stop on address
Variations depending on
Drawbacks match is not available when digital
temperature, voltage, process
filter is enabled.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
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verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripherals can be served by the DMA controller.
Refer to Table 9 for the differences between I2C1 and I2C2.
Table 9. STM32F072x8/xB I2C implementation

I2C features(1) I2C1 I2C2
7-bit addressing mode X X

10-bit addressing mode X X
Standard mode (up to 100 kbit/s) X X
Fast mode (up to 400 kbit/s) X X
Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive I/Os X X
Independent clock X -
SMBus X -
Wakeup from STOP X -
1. X = supported.
3.17 Universal synchronous/asynchronous receiver/transmitter

(USART)
The device embeds four universal synchronous/asynchronous receivers/transmitters
(USART1, USART2, USART3, USART4) which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. USART1 and USART2 support also SmartCard
communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud
rate feature, and have a clock domain independent of the CPU clock, allowing to wake up
the MCU from Stop mode.
The USART interfaces can be served by the DMA controller.
Table 10. STM32F072x8/xB USART implementation

USART1 and USART3 and
USART modes/features(1)
USART2 USART4
Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X X
Smartcard mode X -
Single-wire half-duplex communication X X
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27
Table 10. STM32F072x8/xB USART implementation (continued)

USART1 and USART3 and
USART modes/features(1)
USART2 USART4
IrDA SIR ENDEC block X -

LIN mode X -
Dual clock domain and wakeup from Stop mode X -
Receiver timeout interrupt X -
Modbus communication X -
Auto baud rate detection X -
Driver Enable X X
1. X = supported.
3.18 Serial peripheral interface (SPI) / Inter-integrated sound

interface (I2S)
Two SPIs are able to communicate up to 18 Mbit/s in slave and master modes in full-duplex
and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
Two standard I2S interfaces (multiplexed with SPI1 and SPI2 respectively) supporting four
different audio standards can operate as master or slave at half-duplex communication
mode. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, they can output a clock for an external audio component at 256 times the sampling
frequency.
Table 11. STM32F072x8/xB SPI/I2S implementation

SPI features(1) SPI1 and SPI2
Hardware CRC calculation X

Rx/Tx FIFO X
NSS pulse mode X
I2S mode X
TI mode X
1. X = supported.
3.19 High-definition multimedia interface (HDMI) - consumer

electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
26/128 DocID025004 Rev 5

overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.20 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.21 Universal serial bus (USB)

The STM32F072x8/xB embeds a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with
added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up-to 1 KB (the last 256 byte are used for CAN peripheral if
enabled) and suspend/resume support. It requires a precise 48 MHz clock which can be
generated from the internal main PLL (the clock source must use an HSE crystal oscillator)
or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this
oscillator can be taken from the USB data stream itself (SOF signalization) which allows
crystal-less operation.
3.22 Clock recovery system (CRS)

The STM32F072x8/xB embeds a special block which allows automatic trimming of the
internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device
operational range. This automatic trimming is based on the external synchronization signal,
which could be either derived from USB SOF signalization, from LSE oscillator, from an
external signal on CRS_SYNC pin or generated by user software. For faster lock-in during
startup it is also possible to combine automatic trimming with manual trimming action.
3.23 Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
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27
Pinouts and pin descriptions STM32F072x8 STM32F072xB
4 Pinouts and pin descriptions
Figure 3. UFBGA100 package pinout
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STM32F072x8 STM32F072xB Pinouts and pin descriptions
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Figure 5. UFBGA64 package pinout
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3&
3$
3$
9''
966
3%
3%
3%
3%
3%
3%
3%

9%$7 9'',2
3& 966
3&26&B,1 3$
3&26&B287 3$
3)26&B,1 3$
3)26&B287 3$
1567 3$
3& 3$
3&
/4)3 3&
3& 3&
3& 3&
966$ 3&
9''$ 3%
3$ 3%
3$ 3%
3$ 3%

966
9''
3&
3&
3%
3%
3%
3%
966
9''
3$
3$
3$
3$
3$
3%
,2VXSSOLHGIURP9'',2
06Y9

%227
7RSYLHZ
3$
3$
9''
966
3%
3%
3%
3%
3%
3%
3%

9%$7 9'',2
3& 966
3&26&B,1 3$
3&26&B287 3$
3)26&B,1 3$
3)26&B287 3$
1567
/4)3 3$
966$ 3$
9''$ 3%
3$ 3%
3$ 3%
3$ 3%

3%
3%
3%
3%
966
9''
3$
3$
3$
3$
3$
3%
,2VXSSOLHGIURP9'',2
06Y9
DocID025004 Rev 5 31/128

40
Figure 8. UFQFPN48 package pinout
7RSYLHZ
%227
3$
3$
9''
966
3%
3%
3%
3%
3%
3%
3%

9%$7 9'',2
3& 966
3&26&B,1 3$
3&26&B287 3$
3)26&B,1 3$
3)26&B287 3$
1567
8)4)31 3$
966$ 3$
9''$ 3%
3$ 3%
([SRVHGSDG
3$ 3%
3$ 3%

3%
3%
3%
3%
966
9''
3$
3$
3$
3$
3$
3%
,2VXSSOLHGIURP9'',2
06Y9
Figure 9. WLCSP49 package pinout
7RSYLHZ

$ 3$ 3$ 3% 3% %227 966 9''
% 966 9'',2 3$ 3% 3% 1& 9%$7
3& 3&
& 3$ 3$ 3$ 3% 3% 26&B 26&B
287 ,1
3) 3)
' 3$ 3$ 966 3% 3& 26&B 26&B
287 ,1
( 3% 3% 3% 3$ 3$ 966$ 1567
) 3% 9'' 3$ 3$ 3$ 3$ 9''$
* 3% 3% 3% 3% 3% 3$ 3$
,2VXSSOLHGIURP9'',2
:/&63
06Y9
1. The above figure shows the package in top view, changing from bottom view in the previous document
versions.
32/128 DocID025004 Rev 5

Table 12. Legend/abbreviations used in the pinout table

Name Abbreviation Definition
Unless otherwise specified in brackets below the pin name, the pin function during and
Pin name
after reset is the same as the actual pin name
S Supply pin
Pin type I Input-only pin
I/O Input / output pin
FT 5 V-tolerant I/O
FTf 5 V-tolerant I/O, FM+ capable
TTa 3.3 V-tolerant I/O directly connected to ADC
I/O structure
TC Standard 3.3 V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
Table 13. STM32F072x8/xB pin definitions

Pin numbers Pin functions
LQFP48/UFQFPN48
I/O structure
Pin name
UFBGA100
Notes
WLCSP49
UFBGA64
Pin
LQFP100
LQFP64
(function upon
type Additional
reset) Alternate functions
functions
TSC_G7_IO1,
B2 1 - - - - PE2 I/O FT - -
TIM3_ETR
TSC_G7_IO2,
A1 2 - - - - PE3 I/O FT - -
TIM3_CH1
TSC_G7_IO3,
B1 3 - - - - PE4 I/O FT - -
TIM3_CH2
TSC_G7_IO4,
C2 4 - - - - PE5 I/O FT - -
TIM3_CH3
WKUP3,
D2 5 - - - - PE6 I/O FT - TIM3_CH4
RTC_TAMP3
E2 6 B2 1 1 B7 VBAT S - - Backup power supply
DocID025004 Rev 5 33/128

40
Table 13. STM32F072x8/xB pin definitions (continued)

LQFP48/UFQFPN48
I/O structure
Pin name
UFBGA100
Notes
WLCSP49
UFBGA64
Pin
LQFP100
LQFP64
(function upon
type Additional
functions
WKUP2,
(1)
RTC_TAMP1,
C1 7 A2 2 2 D5 PC13 I/O TC (2) -
RTC_TS,
RTC_OUT
PC14- (1)
D1 8 A1 3 3 C7 OSC32_IN I/O TC (2) - OSC32_IN
(PC14)
PC15- (1)
E1 9 B1 4 4 C6 OSC32_OUT I/O TC (2) - OSC32_OUT
(PC15)
F2 10 - - - - PF9 I/O FT - TIM15_CH1 -
G2 11 - - - PF10 I/O FT - TIM15_CH2 -
PF0-OSC_IN
F1 12 C1 5 5 D7 I/O FT - CRS_ SYNC OSC_IN
(PF0)
PF1-OSC_OUT
G1 13 D1 6 6 D6 I/O FT - - OSC_OUT
(PF1)
Device reset input / internal reset output
H2 14 E1 7 7 E7 NRST I/O RST -
(active low)
H1 15 E3 8 - - PC0 I/O TTa - EVENTOUT ADC_IN10
J2 16 E2 9 - - PC1 I/O TTa - EVENTOUT ADC_IN11
SPI2_MISO, I2S2_MCK,
J3 17 F2 10 - - PC2 I/O TTa - ADC_IN12
EVENTOUT
SPI2_MOSI, I2S2_SD,
K2 18 G1 11 - - PC3 I/O TTa - ADC_IN13
EVENTOUT
J1 19 - - - - PF2 I/O FT - EVENTOUT WKUP8
K1 20 F1 12 8 E6 VSSA S - - Analog ground
M1 21 H1 13 9 F7 VDDA S - - Analog power supply
L1 22 - - - - PF3 I/O FT - EVENTOUT
USART2_CTS,
RTC_ TAMP2,
TIM2_CH1_ETR,
WKUP1,
L2 23 G2 14 10 F6 PA0 I/O TTa - COMP1_OUT,
ADC_IN0,
TSC_G1_IO1,
COMP1_INM6
USART4_TX
34/128 DocID025004 Rev 5


LQFP48/UFQFPN48
I/O structure
Pin name
UFBGA100
Notes
WLCSP49
UFBGA64
Pin
LQFP100
LQFP64
(function upon
type Additional
functions
USART2_RTS,
TIM2_CH2,
TIM15_CH1N, ADC_IN1,
M2 24 H2 15 11 G7 PA1 I/O TTa -
TSC_G1_IO2, COMP1_INP
USART4_RX,
EVENTOUT
USART2_TX,
COMP2_OUT, ADC_IN2,
K3 25 F3 16 12 E5 PA2 I/O TTa - TIM2_CH3, COMP2_INM6,
TIM15_CH1, WKUP4
TSC_G1_IO3
USART2_RX,TIM2_CH4,
ADC_IN3,
L3 26 G3 17 13 E4 PA3 I/O TTa - TIM15_CH2,
COMP2_INP
TSC_G1_IO4
D3 27 C2 18 - - VSS S - - Ground
H3 28 D2 19 - - VDD S - - Digital power supply
SPI1_NSS, I2S1_WS, COMP1_INM4,
TIM14_CH1, COMP2_INM4,
M3 29 H3 20 14 G6 PA4 I/O TTa -
TSC_G2_IO1, ADC_IN4,
USART2_CK DAC_OUT1
SPI1_SCK, I2S1_CK, COMP1_INM5,
CEC, COMP2_INM5,
K4 30 F4 21 15 F5 PA5 I/O TTa -
TIM2_CH1_ETR, ADC_IN5,
TSC_G2_IO2 DAC_OUT2
TIM3_CH1, TIM1_BKIN,
TIM16_CH1,
L4 31 G4 22 16 F4 PA6 I/O TTa - COMP1_OUT, ADC_IN6
TSC_G2_IO3,
EVENTOUT,
USART3_CTS
SPI1_MOSI, I2S1_SD,
TIM3_CH2, TIM14_CH1,
TIM1_CH1N,
M4 32 H4 23 17 F3 PA7 I/O TTa - TIM17_CH1, ADC_IN7
COMP2_OUT,
TSC_G2_IO4,
EVENTOUT
DocID025004 Rev 5 35/128

40

LQFP48/UFQFPN48
I/O structure
Pin name
UFBGA100
Notes
WLCSP49
UFBGA64
Pin
LQFP100
LQFP64
(function upon
type Additional
functions
EVENTOUT,
K5 33 H5 24 - - PC4 I/O TTa - ADC_IN14
USART3_TX
TSC_G3_IO1, ADC_IN15,
L5 34 H6 25 - - PC5 I/O TTa -
USART3_RX WKUP5
TIM3_CH3, TIM1_CH2N,
TSC_G3_IO2,
M5 35 F5 26 18 G5 PB0 I/O TTa - ADC_IN8
EVENTOUT,
USART3_CK
TIM3_CH4,
USART3_RTS,
M6 36 G5 27 19 G4 PB1 I/O TTa - TIM14_CH1, ADC_IN9
TIM1_CH3N,
TSC_G3_IO3
L6 37 G6 28 20 G3 PB2 I/O FT - TSC_G3_IO4 -
M7 38 - - - - PE7 I/O FT - TIM1_ETR -
L7 39 - - - - PE8 I/O FT - TIM1_CH1N -
M8 40 - - - - PE9 I/O FT - TIM1_CH1 -
L8 41 - - - - PE10 I/O FT - TIM1_CH2N -
M9 42 - - - - PE11 I/O FT - TIM1_CH2 -
SPI1_NSS, I2S1_WS,
L9 43 - - - - PE12 I/O FT - -
TIM1_CH3N
SPI1_SCK, I2S1_CK,
M10 44 - - - - PE13 I/O FT - -
TIM1_CH3
M11 45 - - - - PE14 I/O FT - -
TIM1_CH4
SPI1_MOSI, I2S1_SD,
M12 46 - - - - PE15 I/O FT - -
TIM1_BKIN
SPI2_SCK, I2C2_SCL,
L10 47 G7 29 21 E3 PB10 I/O FT - USART3_TX, CEC, -
TSC_SYNC, TIM2_CH3
USART3_RX,
TIM2_CH4,
L11 48 H7 30 22 G2 PB11 I/O FT - EVENTOUT, -
TSC_G6_IO1,
I2C2_SDA
F12 49 D5 31 23 D3 VSS S - - Ground
36/128 DocID025004 Rev 5


LQFP48/UFQFPN48
I/O structure
Pin name
UFBGA100
Notes
WLCSP49
UFBGA64
Pin
LQFP100
LQFP64
(function upon
type Additional
functions
G12 50 E5 32 24 F2 VDD S - - Digital power supply

TIM1_BKIN,
TIM15_BKIN,
SPI2_NSS, I2S2_WS,
L12 51 H8 33 25 E2 PB12 I/O FT - -
USART3_CK,
TSC_G6_IO2,
EVENTOUT
SPI2_SCK, I2S2_CK,
I2C2_SCL,
K12 52 G8 34 26 G1 PB13 I/O FTf - USART3_CTS, -
TIM1_CH1N,
TSC_G6_IO3
I2C2_SDA,
USART3_RTS,
K11 53 F8 35 27 F1 PB14 I/O FTf - -
TIM1_CH2N,
TIM15_CH1,
TSC_G6_IO4
SPI2_MOSI, I2S2_SD,
TIM1_CH3N, WKUP7,
K10 54 F7 36 28 E1 PB15 I/O FT -
TIM15_CH1N, RTC_REFIN
TIM15_CH2
K9 55 - - - - PD8 I/O FT - USART3_TX -
K8 56 - - - - PD9 I/O FT - USART3_RX -
J12 57 - - - - PD10 I/O FT - USART3_CK -
J11 58 - - - - PD11 I/O FT - USART3_CTS -
USART3_RTS,
J10 59 - - - - PD12 I/O FT - -
TSC_G8_IO1
H12 60 - - - - PD13 I/O FT - TSC_G8_IO2 -
H11 61 - - - - PD14 I/O FT - TSC_G8_IO3 -
TSC_G8_IO4,
H10 62 - - - - PD15 I/O FT - -
CRS_SYNC
(3)
E12 63 F6 37 - - PC6 I/O FT TIM3_CH1 -
(3)
E11 64 E7 38 - - PC7 I/O FT TIM3_CH2 -
E10 65 E8 39 - - PC8 I/O FT (3) TIM3_CH3 -
(3)
D12 66 D8 40 - - PC9 I/O FT TIM3_CH4 -
DocID025004 Rev 5 37/128

40

LQFP48/UFQFPN48
I/O structure
Pin name
UFBGA100
Notes
WLCSP49
UFBGA64
Pin
LQFP100
LQFP64
(function upon
type Additional
functions
USART1_CK,
(3) TIM1_CH1,
D11 67 D7 41 29 D1 PA8 I/O FT -
EVENTOUT, MCO,
CRS_SYNC
USART1_TX,
(3) TIM1_CH2,
D10 68 C7 42 30 D2 PA9 I/O FT -
TIM15_BKIN,
TSC_G4_IO1
USART1_RX,
(3) TIM1_CH3,
C12 69 C6 43 31 C2 PA10 I/O FT -
TIM17_BKIN,
TSC_G4_IO2
CAN_RX,
USART1_CTS,
(3) TIM1_CH4,
B12 70 C8 44 32 C1 PA11 I/O FT USB_DM
COMP1_OUT,
TSC_G4_IO3,
EVENTOUT
CAN_TX, USART1_RTS,
TIM1_ETR,
(3)
A12 71 B8 45 33 C3 PA12 I/O FT COMP2_OUT, USB_DP
TSC_G4_IO4,
EVENTOUT
(3)
IR_OUT, SWDIO,
A11 72 A8 46 34 B3 PA13 I/O FT (4) -
USB_NOE
C11 73 - - - - PF6 I/O FT (3) - -
F11 74 D6 47 35 B1 VSS S - - Ground
G11 75 E6 48 36 B2 VDDIO2 S - - Digital power supply
(3)
A10 76 A7 49 37 A1 PA14 I/O FT (4) USART2_TX, SWCLK -
SPI1_NSS, I2S1_WS,
USART2_RX,
(3)
A9 77 A6 50 38 A2 PA15 I/O FT USART4_RTS, -
TIM2_CH1_ETR,
EVENTOUT
(3) USART3_TX,
B11 78 B7 51 - - PC10 I/O FT -
USART4_TX
38/128 DocID025004 Rev 5


LQFP48/UFQFPN48
I/O structure
Pin name
UFBGA100
Notes
WLCSP49
UFBGA64
Pin
LQFP100
LQFP64
(function upon
type Additional
functions
(3) USART3_RX,
C10 79 B6 52 - - PC11 I/O FT -
USART4_RX
(3) USART3_CK,
B10 80 C5 53 - - PC12 I/O FT -
USART4_CK
(3) SPI2_NSS, I2S2_WS,

C9 81 - - - - PD0 I/O FT -
CAN_RX
(3) SPI2_SCK, I2S2_CK,

B9 82 - - - - PD1 I/O FT -
CAN_TX
(3) USART3_RTS,
C8 83 B5 54 - - PD2 I/O FT -
TIM3_ETR
B8 84 - - - - PD3 I/O FT - -
USART2_CTS
SPI2_MOSI, I2S2_SD,
B7 85 - - - - PD4 I/O FT - -
USART2_RTS
A6 86 - - - - PD5 I/O FT - USART2_TX -
B6 87 - - - - PD6 I/O FT - USART2_RX -
A5 88 - - - - PD7 I/O FT - USART2_CK -
SPI1_SCK, I2S1_CK,
TIM2_CH2,
A8 89 A5 55 39 A3 PB3 I/O FT - -
TSC_G5_IO1,
EVENTOUT
TIM17_BKIN,
A7 90 A4 56 40 A4 PB4 I/O FT - TIM3_CH1, -
TSC_G5_IO2,
EVENTOUT
SPI1_MOSI, I2S1_SD,
I2C1_SMBA,
C5 91 C4 57 41 B4 PB5 I/O FT - WKUP6
TIM16_BKIN,
TIM3_CH2
I2C1_SCL, USART1_TX,
B5 92 D3 58 42 C4 PB6 I/O FTf - TIM16_CH1N, -
TSC_G5_I03
DocID025004 Rev 5 39/128

40

LQFP48/UFQFPN48
I/O structure
Pin name
UFBGA100
Notes
WLCSP49
UFBGA64
Pin
LQFP100
LQFP64
(function upon
type Additional
functions
I2C1_SDA,
USART1_RX,
B4 93 C3 59 43 D4 PB7 I/O FTf - USART4_CTS, -
TIM17_CH1N,
TSC_G5_IO4
A4 94 B4 60 44 A5 BOOT0 I B - Boot memory selection
I2C1_SCL, CEC,
TIM16_CH1,
A3 95 B3 61 45 B5 PB8 I/O FTf - -
TSC_SYNC,
CAN_RX
SPI2_NSS, I2S2_WS,
I2C1_SDA, IR_OUT,
B3 96 A3 62 46 C5 PB9 I/O FTf - TIM17_CH1, -
EVENTOUT,
CAN_TX
C3 97 - - - - PE0 I/O FT - EVENTOUT, TIM16_CH1 -
A2 98 - - - - PE1 I/O FT - EVENTOUT, TIM17_CH1 -
D3 99 D4 63 47 A6 VSS S - - Ground
C4 100 E4 64 48 A7 VDD S - - Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to
the RTC domain and RTC register descriptions in the reference manual.
3. PC6, PC7, PC8, PC9, PA8, PA9, PA10, PA11, PA12, PA13, PF6, PA14, PA15, PC10, PC11, PC12, PD0, PD1 and PD2 I/Os
are supplied by VDDIO2.
4. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO
pin and the internal pull-down on the SWCLK pin are activated.
40/128 DocID025004 Rev 5

Table 14. Alternate functions selected through GPIOA_AFR registers for port A
Pin name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PA0 - USART2_CTS TIM2_CH1_ETR TSC_G1_IO1 USART4_TX - - COMP1_OUT

PA1 EVENTOUT USART2_RTS TIM2_CH2 TSC_G1_IO2 USART4_RX TIM15_CH1N - -
PA2 TIM15_CH1 USART2_TX TIM2_CH3 TSC_G1_IO3 - - - COMP2_OUT
PA3 TIM15_CH2 USART2_RX TIM2_CH4 TSC_G1_IO4 - - - -
PA4 SPI1_NSS, I2S1_WS USART2_CK - TSC_G2_IO1 TIM14_CH1 - - -
PA5 SPI1_SCK, I2S1_CK CEC TIM2_CH1_ETR TSC_G2_IO2 - - - -
PA6 SPI1_MISO, I2S1_MCK TIM3_CH1 TIM1_BKIN TSC_G2_IO3 USART3_CTS TIM16_CH1 EVENTOUT COMP1_OUT
PA7 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM1_CH1N TSC_G2_IO4 TIM14_CH1 TIM17_CH1 EVENTOUT COMP2_OUT
PA8 MCO USART1_CK TIM1_CH1 EVENTOUT CRS_SYNC - - -
DocID025004 Rev 5
PA9 TIM15_BKIN USART1_TX TIM1_CH2 TSC_G4_IO1 - - - -

PA10 TIM17_BKIN USART1_RX TIM1_CH3 TSC_G4_IO2 - - - -
PA11 EVENTOUT USART1_CTS TIM1_CH4 TSC_G4_IO3 CAN_RX - - COMP1_OUT
PA12 EVENTOUT USART1_RTS TIM1_ETR TSC_G4_IO4 CAN_TX - - COMP2_OUT
PA13 SWDIO IR_OUT USB_NOE - - - - -
PA14 SWCLK USART2_TX - - - - - -
PA15 SPI1_NSS, I2S1_WS USART2_RX TIM2_CH1_ETR EVENTOUT USART4_RTS - - -
41/128
42/128
Table 15. Alternate functions selected through GPIOB_AFR registers for port B
Pin name AF0 AF1 AF2 AF3 AF4 AF5
PB0 EVENTOUT TIM3_CH3 TIM1_CH2N TSC_G3_IO2 USART3_CK -

PB1 TIM14_CH1 TIM3_CH4 TIM1_CH3N TSC_G3_IO3 USART3_RTS -
PB2 - - - TSC_G3_IO4 - -
PB3 SPI1_SCK, I2S1_CK EVENTOUT TIM2_CH2 TSC_G5_IO1 - -
PB4 SPI1_MISO, I2S1_MCK TIM3_CH1 EVENTOUT TSC_G5_IO2 - TIM17_BKIN
PB5 SPI1_MOSI, I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA - -
PB6 USART1_TX I2C1_SCL TIM16_CH1N TSC_G5_IO3 - -
PB7 USART1_RX I2C1_SDA TIM17_CH1N TSC_G5_IO4 USART4_CTS -
PB8 CEC I2C1_SCL TIM16_CH1 TSC_SYNC CAN_RX -
PB9 IR_OUT I2C1_SDA TIM17_CH1 EVENTOUT CAN_TX SPI2_NSS, I2S2_WS
DocID025004 Rev 5
PB10 CEC I2C2_SCL TIM2_CH3 TSC_SYNC USART3_TX SPI2_SCK, I2S2_CK

PB11 EVENTOUT I2C2_SDA TIM2_CH4 TSC_G6_IO1 USART3_RX -
PB12 SPI2_NSS, I2S2_WS EVENTOUT TIM1_BKIN TSC_G6_IO2 USART3_CK TIM15_BKIN
PB13 SPI2_SCK, I2S2_CK - TIM1_CH1N TSC_G6_IO3 USART3_CTS I2C2_SCL
PB14 SPI2_MISO, I2S2_MCK TIM15_CH1 TIM1_CH2N TSC_G6_IO4 USART3_RTS I2C2_SDA
PB15 SPI2_MOSI, I2S2_SD TIM15_CH2 TIM1_CH3N TIM15_CH1N - -
Table 16. Alternate functions selected through GPIOC_AFR registers for port C
Pin name AF0 AF1
PC0 EVENTOUT -
PC1 EVENTOUT -
PC2 EVENTOUT SPI2_MISO, I2S2_MCK
PC3 EVENTOUT SPI2_MOSI, I2S2_SD
PC4 EVENTOUT USART3_TX
PC5 TSC_G3_IO1 USART3_RX
PC6 TIM3_CH1 -
PC7 TIM3_CH2 -
PC8 TIM3_CH3 -
PC9 TIM3_CH4 -
PC10 USART4_TX USART3_TX
PC11 USART4_RX USART3_RX
PC12 USART4_CK USART3_CK
PC13 - -
PC14 - -
PC15 - -
Table 17. Alternate functions selected through GPIOD_AFR registers for port D
Pin name AF0 AF1
PD0 CAN_RX SPI2_NSS, I2S2_WS

PD1 CAN_TX SPI2_SCK, I2S2_CK
PD2 TIM3_ETR USART3_RTS
PD3 USART2_CTS SPI2_MISO, I2S2_MCK
PD4 USART2_RTS SPI2_MOSI, I2S2_SD
PD5 USART2_TX -
PD6 USART2_RX -
PD7 USART2_CK -
PD8 USART3_TX -
PD9 USART3_RX -
PD10 USART3_CK -
PD11 USART3_CTS -
PD12 USART3_RTS TSC_G8_IO1
PD13 - TSC_G8_IO2
PD14 - TSC_G8_IO3
PD15 CRS_SYNC TSC_G8_IO4
DocID025004 Rev 5 43/128

44
Table 18. Alternate functions selected through GPIOE_AFR registers for port E
Pin name AF0 AF1
PE0 TIM16_CH1 EVENTOUT

PE1 TIM17_CH1 EVENTOUT
PE2 TIM3_ETR TSC_G7_IO1
PE3 TIM3_CH1 TSC_G7_IO2
PE6 TIM3_CH4 -
PE7 TIM1_ETR -
PE8 TIM1_CH1N -
PE9 TIM1_CH1 -
PE10 TIM1_CH2N -
PE11 TIM1_CH2 -
PE12 TIM1_CH3N SPI1_NSS, I2S1_WS
PE13 TIM1_CH3 SPI1_SCK, I2S1_CK
PE14 TIM1_CH4 SPI1_MISO, I2S1_MCK
PE15 TIM1_BKIN SPI1_MOSI, I2S1_SD
Table 19. Alternate functions available on port F

Pin name AF
PF0 CRS_SYNC
PF1 -
PF2 EVENTOUT
PF3 EVENTOUT
PF6 -
PF9 TIM15_CH1
PF10 TIM15_CH2
44/128 DocID025004 Rev 5

STM32F072x8 STM32F072xB Memory mapping
5 Memory mapping
To the difference of STM32F072xB memory map in Figure 10, the two bottom code memory
spaces of STM32F072x8 end at 0x0000 FFFF and 0x0800 FFFF, respectively.
Figure 10. STM32F072xB memory map
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DocID025004 Rev 5 45/128

47
Memory mapping STM32F072x8 STM32F072xB
Table 20. STM32F072x8/xB peripheral register boundary addresses

Bus Boundary address Size Peripheral
0x4800 1800 - 0x5FFF FFFF ~384 MB Reserved

0x4800 1400 - 0x4800 17FF 1 KB GPIOF
0x4800 1000 - 0x4800 13FF 1 KB GPIOE
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD
AHB2
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
0x4002 4400 - 0x47FF FFFF ~128 MB Reserved
0x4002 4000 - 0x4002 43FF 1 KB TSC
0x4002 3400 - 0x4002 3FFF 3 KB Reserved
0x4002 3000 - 0x4002 33FF 1 KB CRC
AHB1 0x4002 2000 - 0x4002 23FF 1 KB Flash memory interface
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 0000 - 0x4002 03FF 1 KB DMA
0x4001 8000 - 0x4001 FFFF 32 KB Reserved
0x4001 5C00 - 0x4001 7FFF 9 KB Reserved
0x4001 5800 - 0x4001 5BFF 1 KB DBGMCU
0x4001 4C00 - 0x4001 57FF 3 KB Reserved
0x4001 4800 - 0x4001 4BFF 1 KB TIM17
0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 4000 - 0x4001 43FF 1 KB TIM15
0x4001 3800 - 0x4001 3BFF 1 KB USART1
0x4001 3400 - 0x4001 37FF 1 KB Reserved
0x4001 3000 - 0x4001 33FF 1 KB SPI1/I2S1
APB 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
0x4001 2800 - 0x4001 2BFF 1 KB Reserved
0x4001 2400 - 0x4001 27FF 1 KB ADC
0x4001 0800 - 0x4001 23FF 7 KB Reserved
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0000 - 0x4001 03FF 1 KB SYSCFG + COMP
0x4000 8000 - 0x4000 FFFF 32 KB Reserved
46/128 DocID025004 Rev 5

STM32F072x8 STM32F072xB Memory mapping
Table 20. STM32F072x8/xB peripheral register boundary addresses (continued)

Bus Boundary address Size Peripheral

0x4000 7800 - 0x4000 7BFF 1 KB CEC
0x4000 7400 - 0x4000 77FF 1 KB DAC
0x4000 7000 - 0x4000 73FF 1 KB PWR
0x4000 6C00 - 0x4000 6FFF 1 KB CRS
0x4000 6800 - 0x4000 6BFF 1 KB Reserved
0x4000 6400 - 0x4000 67FF 1 KB BxCAN
0x4000 6000 - 0x4000 63FF 1 KB USB/CAN RAM
0x4000 5C00 - 0x4000 5FFF 1 KB USB
0x4000 5800 - 0x4000 5BFF 1 KB I2C2
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 5000 - 0x4000 53FF 1 KB Reserved
0x4000 4C00 - 0x4000 4FFF 1 KB USART4
0x4000 4800 - 0x4000 4BFF 1 KB USART3
0x4000 4400 - 0x4000 47FF 1 KB USART2
0x4000 3C00 - 0x4000 43FF 2 KB Reserved
0x4000 3800 - 0x4000 3BFF 1 KB SPI2
APB 0x4000 3400 - 0x4000 37FF 1 KB Reserved
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
0x4000 2800 - 0x4000 2BFF 1 KB RTC
0x4000 2400 - 0x4000 27FF 1 KB Reserved
0x4000 2000 - 0x4000 23FF 1 KB TIM14
0x4000 1400 - 0x4000 17FF 1 KB TIM7
0x4000 1000 - 0x4000 13FF 1 KB TIM6
0x4000 0400 - 0x4000 07FF 1 KB TIM3
0x4000 0000 - 0x4000 03FF 1 KB TIM2
DocID025004 Rev 5 47/128

47
Electrical characteristics STM32F072x8 STM32F072xB
6 Electrical characteristics
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean 3).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean 2).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 11.
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions Figure 12. Pin input voltage
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48/128 DocID025004 Rev 5

STM32F072x8 STM32F072xB Electrical characteristics
6.1.6 Power supply scheme
Figure 13. Power supply scheme
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Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
DocID025004 Rev 5 49/128

99
6.1.7 Current consumption measurement
Figure 14. Current consumption measurement scheme
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50/128 DocID025004 Rev 5

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics,
Table 22: Current characteristics and Table 23: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 21. Voltage characteristics(1)

Symbol Ratings Min Max Unit
VDDVSS External main supply voltage - 0.3 4.0 V

VDDIO2VSS External I/O supply voltage - 0.3 4.0 V
VDDAVSS External analog supply voltage - 0.3 4.0 V
VDDVDDA Allowed voltage difference for VDD > VDDA - 0.4 V
VBATVSS External backup supply voltage - 0.3 4.0 V
Input voltage on FT and FTf pins VSS - 0.3 VDDIOx + 4.0(3) V
Input voltage on TTa pins VSS - 0.3 4.0 V
VIN(2)
BOOT0 0 9.0 V
Input voltage on any other pin VSS - 0.3 4.0 V
|VDDx| Variations between different VDD power pins - 50 mV
Variations between all the different ground
|VSSx - VSS| - 50 mV
pins
Electrostatic discharge voltage see Section 6.3.12: Electrical
VESD(HBM) -
(human body model) sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 22: Current characteristics for the maximum
allowed injected current values.
3. Valid only if the internal pull-up/pull-down resistors are disabled. If internal pull-up or pull-down resistor is
enabled, the maximum limit is 4 V.
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99
Table 22. Current characteristics

Symbol Ratings Max. Unit
IVDD Total current into sum of all VDD power lines (source)(1) 120
(1)
IVSS Total current out of sum of all VSS ground lines (sink) -120
(1)
IVDD(PIN) Maximum current into each VDD power pin (source) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) -100
Output current sunk by any I/O and control pin 25
IIO(PIN)
Output current source by any I/O and control pin -25
(2)
Total output current sunk by sum of all I/Os and control pins 80
IIO(PIN) Total output current sourced by sum of all I/Os and control pins(2) -80 mA
Total output current sourced by sum of all I/Os supplied by VDDIO2 -40
Injected current on B, FT and FTf pins -5/+0(4)
IINJ(PIN)(3) Injected current on TC and RST pin 5
Injected current on TTa pins(5) 5
IINJ(PIN) Total injected current (sum of all I/O and control pins)(6) 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 59: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 23. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range 65 to +150 C

TJ Maximum junction temperature 150 C
52/128 DocID025004 Rev 5

6.3 Operating conditions
6.3.1 General operating conditions
Table 24. General operating conditions

Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 48

MHz
fPCLK Internal APB clock frequency - 0 48
VDD Standard operating voltage - 2.0 3.6 V
Must not be supplied if VDD
VDDIO2 I/O supply voltage 1.65 3.6 V
is not present
Analog operating voltage
VDD 3.6
(ADC and DAC not used) Must have a potential equal
VDDA V
Analog operating voltage to or higher than VDD
2.4 3.6
(ADC and DAC used)
VBAT Backup operating voltage - 1.65 3.6 V
TC and RST I/O 0.3 VDDIOx+0.3
TTa I/O 0.3 VDDA+0.3(1)
VIN I/O input voltage V
FT and FTf I/O 0.3 5.5(1)
BOOT0 0 5.5
UFBGA100 - 364
LQFP100 - 476
UFBGA64 - 308
Power dissipation at TA = 85 C
PD for suffix 6 or TA = 105 C for LQFP64 - 455 mW
suffix 7(2)
LQFP48 - 370
UFQFPN48 - 625
WLCSP49 - 408
Ambient temperature for the Maximum power dissipation 40 85

C
suffix 6 version Low power dissipation (3) 40 105
TA
Ambient temperature for the Maximum power dissipation 40 105
C
suffix 7 version Low power dissipation (3)
40 125
Suffix 6 version 40 105
TJ Junction temperature range C
Suffix 7 version 40 125
1. For operation with a voltage higher than VDDIOx + 0.3 V, the internal pull-up resistor must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. See Section 7.8: Thermal characteristics.
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.8:
Thermal characteristics).
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99
6.3.2 Operating conditions at power-up / power-down

The parameters given in Table 25 are derived from tests performed under the ambient
temperature condition summarized in Table 24.
Table 25. Operating conditions at power-up / power-down

VDD rise time rate 0

tVDD -
VDD fall time rate 20
s/V
VDDA rise time rate 0
tVDDA -
VDDA fall time rate 20
6.3.3 Embedded reset and power control block characteristics

temperature and supply voltage conditions summarized in Table 24: General operating
conditions.
Table 26. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit
Power on/power down Falling edge(2) 1.80 1.88 1.96(3) V

VPOR/PDR(1)
reset threshold Rising edge 1.84(3) 1.92 2.00 V
VPDRhyst PDR hysteresis - - 40 - mV
tRSTTEMPO (4) Reset temporization - 1.50 2.50 4.50 ms
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Data based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.
Table 27. Programmable voltage detector characteristics

Rising edge 2.1 2.18 2.26 V

VPVD0 PVD threshold 0
Falling edge 2 2.08 2.16 V
Rising edge 2.19 2.28 2.37 V
Falling edge 2.09 2.18 2.27 V
Rising edge 2.28 2.38 2.48 V
Rising edge 2.38 2.48 2.58 V
54/128 DocID025004 Rev 5

Table 27. Programmable voltage detector characteristics (continued)

Rising edge 2.47 2.58 2.69 V

Rising edge 2.57 2.68 2.79 V
Rising edge 2.66 2.78 2.9 V
Rising edge 2.76 2.88 3 V
VPVDhyst(1) PVD hysteresis - - 100 - mV
IDD(PVD) PVD current consumption - - 0.15 0.26(1) A
6.3.4 Embedded reference voltage

conditions.
Table 28. Embedded internal reference voltage

VREFINT Internal reference voltage 40 C < TA < +105 C 1.2 1.23 1.25 V
ADC_IN17 buffer startup
tSTART - - - 10(1) s
time
ADC sampling time when
tS_vrefint reading the internal - 4(1) - - s
reference voltage
Internal reference voltage
VREFINT spread over the VDDA = 3 V - - 10(1) mV
temperature range
TCoeff Temperature coefficient - - 100(1) - 100(1) ppm/C

6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
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99
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption

The MCU is placed under the following conditions:
All I/O pins are in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the fHCLK frequency:
0 wait state and Prefetch OFF from 0 to 24 MHz
1 wait state and Prefetch ON above 24 MHz
When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 29 to Table 31 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 24: General
operating conditions.
Table 29. Typical and maximum current consumption from VDD supply at VDD = 3.6 V
All peripherals enabled(1) All peripherals disabled
Parameter
Symbol
Conditions fHCLK Max @ TA(2) Max @ TA(2) Unit

Typ Typ
25 C 85 C 105 C 25 C 85 C 105 C
HSI48 48 MHz 24.3 26.9 27.2 27.9 13.1 14.8 14.9 15.5
48 MHz 24.1 26.8 27.0 27.7 13.0 14.6 14.8 15.4
code executing from Flash memory
HSE bypass,
Supply current in Run mode,
32 MHz 16.0 18.3 18.6 19.2 8.76 9.56 9.73 10.6

PLL on
24 MHz 12.3 13.7 14.3 14.7 7.36 7.94 8.37 8.81
HSE bypass, 8 MHz 4.52 5.25 5.28 5.61 2.89 3.17 3.26 3.34
IDD PLL off 1 MHz 1.25 1.39 1.58 1.87 0.93 1.06 1.15 1.34 mA
48 MHz 24.1 27.1 27.6 27.8 12.9 14.7 14.9 15.5

HSI clock,
32 MHz 16.1 18.2 18.9 19.3 8.82 9.69 9.83 10.7
PLL on
24 MHz 12.4 14.0 14.4 14.8 7.31 7.92 8.34 8.75
HSI clock,
8 MHz 4.52 5.25 5.35 5.61 2.87 3.16 3.25 3.33
PLL off
56/128 DocID025004 Rev 5

Table 29. Typical and maximum current consumption from VDD supply at VDD = 3.6 V (continued)
Parameter All peripherals enabled(1) All peripherals disabled
Symbol
Conditions fHCLK Max @ TA(2) Max @ TA(2) Unit

Typ Typ
25 C 85 C 105 C 25 C 85 C 105 C
HSI48 48 MHz 23.1 25.4 25.8 26.6 12.8 13.5 13.7 13.9
(3) 26.5(3) 13.3(3) 13.8(3)
48 MHz 23.0 25.3 25.7 12.6 13.5
HSE bypass,
Supply current in Run mode,
32 MHz 15.4 17.3 17.8 18.3 7.96 8.92 9.17 9.73

code executing from RAM
PLL on
24 MHz 11.4 12.9 13.5 13.7 6.48 8.04 8.23 8.41
HSE bypass, 8 MHz 4.21 4.6 4.89 5.25 2.07 2.3 2.35 2.94
PLL off 1 MHz 0.78 0.9 0.92 1.15 0.36 0.48 0.59 0.82
48 MHz 23.1 24.5 25.0 25.2 12.6 13.7 13.9 14.0
HSI clock,
32 MHz 15.4 17.4 17.7 18.2 8.05 8.85 9.16 9.94
PLL on
24 MHz 11.5 13.0 13.6 13.9 6.49 8.06 8.21 8.47
HSI clock,
8 MHz 4.34 4.75 5.03 5.41 2.11 2.36 2.38 2.98
PLL off
IDD mA
HSI48 48 MHz 15.1 16.6 16.8 17.5 3.08 3.43 3.56 3.61
48 MHz 15.0 16.5(3) 16.7 17.3(3) 2.93 3.28(3) 3.41 3.46(3)
HSE bypass,
Supply current in Sleep mode
32 MHz 9.9 11.4 11.6 11.9 2.0 2.24 2.32 2.49

PLL on
24 MHz 7.43 8.17 8.71 8.82 1.63 1.82 1.88 1.9
HSE bypass, 8 MHz 2.83 3.09 3.26 3.66 0.76 0.88 0.91 0.93
PLL off 1 MHz 0.42 0.54 0.55 0.67 0.28 0.39 0.41 0.43
48 MHz 15.0 17.2 17.3 17.9 3.04 3.37 3.41 3.46
HSI clock,
32 MHz 9.93 11.3 11.6 11.7 2.11 2.35 2.44 2.65
PLL on
24 MHz 7.53 8.45 8.87 8.95 1.64 1.83 1.9 1.93
HSI clock,
8 MHz 2.95 3.24 3.41 3.8 0.8 0.92 0.94 0.97
PLL off
1. USB is kept disabled as this IP functions only with a 48 MHz clock.
2. Data based on characterization results, not tested in production unless otherwise specified.
3. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
DocID025004 Rev 5 57/128

99
Table 30. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V VDDA = 3.6 V
Para- Conditions
Symbol (1) fHCLK Max @ TA(2) Max @ TA(2) Unit
meter
Typ Typ
25 C 85 C 105 C 25 C 85 C 105 C
HSI48 48 MHz 311 326 334 343 322 337 345 354
(3) (3) (3)
48 MHz 152 170 178 182 165 184 196 200(3)
HSE
Supply
bypass, 32 MHz 105 121 126 128 113 129 136 138
current in
PLL on
Run or 24 MHz 81.9 95.9 99.5 101 88.7 102 107 108
Sleep
HSE 8 MHz 2.7 3.8 4.3 4.6 3.6 4.7 5.2 5.5
mode,
bypass,
IDDA code 1 MHz 2.7 3.8 4.3 4.6 3.6 4.7 5.2 5.5 A
PLL off
executing
from 48 MHz 223 244 255 260 245 265 279 284
Flash HSI clock,
32 MHz 176 195 203 206 193 212 221 224
memory PLL on
or RAM 24 MHz 154 171 178 181 168 185 192 195
HSI clock,
8 MHz 74.2 83.4 86.4 87.3 83.4 92.5 95.3 96.6
PLL off
1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being
in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, IDDA is independent from
the frequency.
58/128 DocID025004 Rev 5

Table 31. Typical and maximum consumption in Stop and Standby modes
Typ @VDD (VDD = VDDA) Max(1)
Sym- Para-
Conditions Unit
bol meter TA = TA = TA =
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
25 C 85 C 105 C
Regulator in run
Supply mode, all 15.4 15.5 15.6 15.7 15.8 15.9 23(2) 49 68(2)
current in oscillators OFF
Stop Regulator in low-
mode power mode, all 3.2 3.3 3.4 3.5 3.6 3.7 8(2) 33 51(2)
IDD oscillators OFF
Supply LSI ON and IWDG

0.8 1.0 1.1 1.2 1.3 1.4 - - -
current in ON
Standby LSI OFF and IWDG
mode 0.6 0.7 0.9 0.9 1.0 1.1 2.1(2) 2.6 3.1(2)
OFF
Regulator in
run mode, all
2.1 2.2 2.3 2.5 2.6 2.8 3.5(2) 3.6 4.6(2)
oscillators
Supply OFF
VDDA monitoring ON
current in
Stop Regulator in
mode low-power
mode, all 2.1 2.2 2.3 2.5 2.6 2.8 3.5(2) 3.6 4.6(2)
oscillators
OFF A
Supply LSI ON and

2.5 2.7 2.8 3.0 3.2 3.5 - - -
current in IWDG ON
Standby LSI OFF and
mode 1.9 2.1 2.2 2.3 2.5 2.6 3.5(2) 3.6 4.6(2)
IWDG OFF
IDDA
Regulator in
run mode, all
1.3 1.3 1.4 1.4 1.5 1.5 - - -
oscillators
Supply OFF
VDDA monitoring OFF
current in
Stop Regulator in
mode low-power
mode, all 1.3 1.3 1.4 1.4 1.5 1.5 - - -
oscillators
OFF
Supply LSI ON and

1.7 1.8 1.9 2.0 2.1 2.2 - - -
current in IWDG ON
Standby LSI OFF and
mode 1.2 1.2 1.2 1.3 1.3 1.4 - - -
IWDG OFF
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99
Table 32. Typical and maximum current consumption from the VBAT supply
Typ @ VBAT Max(1)
Symbol Parameter Conditions Unit
1.65 V
2.7 V
1.8 V
2.4 V
3.3 V
3.6 V
TA = TA = TA =
25 C 85 C 105 C
LSE & RTC ON; Xtal

mode: lower driving
0.5 0.6 0.7 0.8 1.1 1.2 1.3 1.7 2.3
RTC capability;
domain LSEDRV[1:0] = '00'
IDD_VBAT A
supply LSE & RTC ON; Xtal
current mode higher driving
0.8 0.9 1.1 1.2 1.4 1.6 1.7 2.1 2.8
capability;
LSEDRV[1:0] = '11'
Typical current consumption

The MCU is placed under the following conditions:
VDD = VDDA = 3.3 V
All I/O pins are in analog input configuration
The Flash memory access time is adjusted to fHCLK frequency:
0 wait state and Prefetch OFF from 0 to 24 MHz
1 wait state and Prefetch ON above 24 MHz
When the peripherals are enabled, fPCLK = fHCLK
PLL is used for frequencies greater than 8 MHz
AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
60/128 DocID025004 Rev 5

Table 33. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal
Typical consumption in Typical consumption in
Run mode Sleep mode
Symbol Parameter fHCLK Unit
Peripherals Peripherals Peripherals Peripherals
enabled disabled enabled disabled
48 MHz 24.1 13.5 14.6 3.5

36 MHz 18.3 10.5 11.1 2.9
32 MHz 16.5 9.6 10.0 2.7
24 MHz 12.9 7.6 7.8 2.2
Current
consumption 16 MHz 8.9 5.3 5.5 1.7
IDD mA
from VDD 8 MHz 4.8 3.1 3.1 1.2
supply
4 MHz 3.1 2.1 2.2 1.1
2 MHz 2.1 1.6 1.6 1.0
1 MHz 1.6 1.3 1.4 1.0
500 kHz 1.3 1.2 1.2 1.0
48 MHz 163.3
36 MHz 124.3
32 MHz 111.9
24 MHz 87.1
Current
consumption 16 MHz 62.5
IDDA A
from VDDA 8 MHz 2.5
supply
4 MHz 2.5
2 MHz 2.5
1 MHz 2.5
500 kHz 2.5
I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 53: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
DocID025004 Rev 5 61/128

99
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 35: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx f SW C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
62/128 DocID025004 Rev 5

Table 34. Switching output I/O current consumption

I/O toggling
Symbol Parameter Conditions(1) Typ Unit
frequency (fSW)
4 MHz 0.07
8 MHz 0.15
VDDIOx = 3.3 V
C =CINT 16 MHz 0.31
24 MHz 0.53
48 MHz 0.92
4 MHz 0.18
VDDIOx = 3.3 V 8 MHz 0.37

CEXT = 0 pF 16 MHz 0.76
C = CINT + CEXT+ CS 24 MHz 1.39
48 MHz 2.188
4 MHz 0.32

CEXT = 10 pF 16 MHz 1.25
I/O current 48 MHz 4.442

ISW mA
consumption
4 MHz 0.49
VDDIOx = 3.3 V
8 MHz 0.94
CEXT = 22 pF
16 MHz 2.38
C = CINT + CEXT+ CS
24 MHz 3.99
4 MHz 0.64
CEXT = 33 pF
16 MHz 3.24
C = CINT + CEXT+ CS
24 MHz 5.02
CEXT = 47 pF 8 MHz 1.7
C = CINT + CEXT+ CS
C = Cint 16 MHz 3.67
4 MHz 0.66
VDDIOx = 2.4 V
CEXT = 47 pF 8 MHz 1.43
C = Cint
24 MHz 4.97
1. CS = 7 pF (estimated value).
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99
On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 35. The MCU is placed
under the following conditions:
All I/O pins are in analog mode
All peripherals are disabled unless otherwise mentioned
The given value is calculated by measuring the current consumption
with all peripherals clocked off
with only one peripheral clocked on
Ambient operating temperature and supply voltage conditions summarized in Table 21:
Voltage characteristics
The power consumption of the digital part of the on-chip peripherals is given in
Table 35. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 35. Peripheral current consumption

Peripheral Typical consumption at 25 C Unit
BusMatrix(1) 2.2
CRC 1.6
DMA 5.7
Flash memory interface 13.0
GPIOA 8.2
GPIOB 8.5
AHB GPIOC 2.3 A/MHz
GPIOD 1.9
GPIOE 2.2
GPIOF 1.2
SRAM 0.9
TSC 5.0
All AHB peripherals 52.6
64/128 DocID025004 Rev 5

Table 35. Peripheral current consumption (continued)

Peripheral Typical consumption at 25 C Unit
(2)
APB-Bridge 2.8
ADC(3) 4.1
CAN 12.4
CEC 1.5
CRS 0.8
DAC(3) 4.7
DEBUG (MCU debug feature) 0.1
I2C1 3.9
I2C2 4.0
PWR 1.3
SPI1 8.7
SPI2 8.5
SYSCFG & COMP 1.7
TIM1 14.9
TIM2 15.5
APB TIM3 11.4 A/MHz
TIM6 2.5
TIM7 2.3
TIM14 5.3
TIM15 9.1
TIM16 6.6
TIM17 6.8
USART1 17.0
USART2 16.7
USART3 5.4
USART4 5.4
USB 7.2
WWDG 1.4
All APB peripherals 182
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The APB Bridge is automatically active when at least one peripheral is ON on the Bus.
3. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, is not
included. Refer to the tables of characteristics in the subsequent sections.
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99
6.3.6 Wakeup time from low-power mode

The wakeup times given in Table 36 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 24: General operating conditions.
Table 36. Low-power mode wakeup timings

Typ @VDD = VDDA
Symbol Parameter Conditions Max Unit
= 2.0 V = 2.4 V = 2.7 V =3V = 3.3 V
Regulator in run
3.2 3.1 2.9 2.9 2.8 5
Wakeup from Stop mode
tWUSTOP
mode Regulator in low
7.0 5.8 5.2 4.9 4.6 9
power mode
s
Wakeup from
tWUSTANDBY - 60.4 55.6 53.5 52 51 -
Standby mode
Wakeup from Sleep
tWUSLEEP - 4 SYSCLK cycles -
mode
6.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 15: High-speed external clock
source AC timing diagram.
Table 37. High-speed external user clock characteristics

Symbol Parameter(1) Min Typ Max Unit
fHSE_ext User external clock source frequency - 8 32 MHz

VHSEH OSC_IN input pin high level voltage 0.7 VDDIOx - VDDIOx
V
VHSEL OSC_IN input pin low level voltage VSS - 0.3 VDDIOx
tw(HSEH)
OSC_IN high or low time 15 - -
tw(HSEL)
ns
tr(HSE)
OSC_IN rise or fall time - - 20
tf(HSE)
66/128 DocID025004 Rev 5

Figure 15. High-speed external clock source AC timing diagram
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Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 16.
Table 38. Low-speed external user clock characteristics

Symbol Parameter(1) Min Typ Max Unit
fLSE_ext User external clock source frequency - 32.768 1000 kHz

VLSEH OSC32_IN input pin high level voltage 0.7 VDDIOx - VDDIOx
V
VLSEL OSC32_IN input pin low level voltage VSS - 0.3 VDDIOx
tw(LSEH)
OSC32_IN high or low time 450 - -
tw(LSEL)
ns
tr(LSE)
OSC32_IN rise or fall time - - 50
tf(LSE)
Figure 16. Low-speed external clock source AC timing diagram
WZ/6(+
9/6(+

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WI/6( WZ/6(/
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069
DocID025004 Rev 5 67/128

99
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 39. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 39. HSE oscillator characteristics

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit
fOSC_IN Oscillator frequency - 4 8 32 MHz

RF Feedback resistor - - 200 - k
(3)
During startup - - 8.5
VDD = 3.3 V,
Rm = 30 , - 0.4 -
CL = 10 pF@8 MHz
VDD = 3.3 V,
Rm = 45 , - 0.5 -
CL = 10 pF@8 MHz
IDD HSE current consumption VDD = 3.3 V, mA

Rm = 30 , - 0.8 -
CL = 5 pF@32 MHz
VDD = 3.3 V,
Rm = 30 , - 1 -
CL = 10 pF@32 MHz
VDD = 3.3 V,
Rm = 30 , - 1.5 -
CL = 20 pF@32 MHz
gm Oscillator transconductance Startup 10 - - mA/V
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 Oscillator
design guide for ST microcontrollers available from the ST website www.st.com.
68/128 DocID025004 Rev 5

Figure 17. Typical application with an 8 MHz crystal
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1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 40. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 40. LSE oscillator characteristics (fLSE = 32.768 kHz)

Symbol Parameter Conditions(1) Min(2) Typ Max(2) Unit
low drive capability - 0.5 0.9

medium-low drive capability - - 1
IDD LSE current consumption A
medium-high drive capability - - 1.3
high drive capability - - 1.6
low drive capability 5 - -
Oscillator medium-low drive capability 8 - -

gm A/V
transconductance medium-high drive capability 15 - -
high drive capability 25 - -
tSU(LSE) (3)
Startup time VDDIOx is stabilized - 2 - s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 Oscillator design guide for
ST microcontrollers.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
DocID025004 Rev 5 69/128

99
Note: For information on selecting the crystal, refer to the application note AN2867 Oscillator
design guide for ST microcontrollers available from the ST website www.st.com.
Figure 18. Typical application with a 32.768 kHz crystal
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Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
6.3.8 Internal clock source characteristics

The parameters given in Table 41 are derived from tests performed under ambient
conditions. The provided curves are characterization results, not tested in production.
70/128 DocID025004 Rev 5

High-speed internal (HSI) RC oscillator
Table 41. HSI oscillator characteristics(1)

fHSI Frequency - - 8 - MHz

(2)
TRIM HSI user trimming step - - - 1 %
DuCy(HSI) (2) (2)
Duty cycle - 45 - 55 %
(3) (3)
TA = -40 to 105C -2.8 - 3.8
TA = -10 to 85C -1.9(3) - 2.3(3)
Accuracy of the HSI TA = 0 to 85C -1.9(3) - 2(3)

ACCHSI %
oscillator TA = 0 to 70C -1.3(3) - 2(3)
TA = 0 to 55C -1(3) - 2(3)
TA = 25C(4) -1 - 1
tsu(HSI) HSI oscillator startup time - 1(2) - 2(2) s
HSI oscillator power
IDDA(HSI) - - 80 100(2) A
consumption
1. VDDA = 3.3 V, TA = -40 to 105C unless otherwise specified.
4. Factory calibrated, parts not soldered.
Figure 19. HSI oscillator accuracy characterization results for soldered parts
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99
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
Table 42. HSI14 oscillator characteristics(1)

fHSI14 Frequency - - 14 - MHz

(2)
TRIM HSI14 user-trimming step - - - 1 %
DuCy(HSI14) Duty cycle (2) (2)
- 45 - 55 %
TA = 40 to 105 C 4.2 (3) (3)
- 5.1 %
Accuracy of the HSI14 TA = 10 to 85 C 3.2(3) - 3.1(3) %

ACCHSI14
oscillator (factory calibrated) TA = 0 to 70 C 2.5 (3)
- 2.3 (3)
%
TA = 25 C 1 - 1 %
tsu(HSI14) HSI14 oscillator startup time - 1(2) - 2(2) s
HSI14 oscillator power
IDDA(HSI14) - - 100 150(2) A
consumption
1. VDDA = 3.3 V, TA = 40 to 105 C unless otherwise specified.
Figure 20. HSI14 oscillator accuracy characterization results

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72/128 DocID025004 Rev 5

High-speed internal 48 MHz (HSI48) RC oscillator
Table 43. HSI48 oscillator characteristics(1)

fHSI48 Frequency - - 48 - MHz

(2) (2)
TRIM HSI48 user-trimming step - 0.09 0.14 0.2 %
DuCy(HSI48) Duty cycle (2) (2)
- 45 - 55 %
TA = 40 to 105 C (3) (3)
-4.9 - 4.7 %
Accuracy of the HSI48 TA = 10 to 85 C -4.1(3) - 3.7(3) %

ACCHSI48
oscillator (factory calibrated) T = 0 to 70 C -3.8 (3)
- 3.4 (3)
%
A
TA = 25 C -2.8 - 2.9 %
tsu(HSI48) HSI48 oscillator startup time - - - 6(2) s
HSI48 oscillator power
IDDA(HSI48) - - 312 350(2) A
consumption
Figure 21. HSI48 oscillator accuracy characterization results

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99
Low-speed internal (LSI) RC oscillator
Table 44. LSI oscillator characteristics(1)

Symbol Parameter Min Typ Max Unit
fLSI Frequency 30 40 50 kHz

(2)
tsu(LSI) LSI oscillator startup time - - 85 s
IDDA(LSI)(2) LSI oscillator power consumption - 0.75 1.2 A
6.3.9 PLL characteristics

The parameters given in Table 45 are derived from tests performed under ambient
conditions.
Table 45. PLL characteristics

Value
Symbol Parameter Unit
Min Typ Max
PLL input clock(1) 1(2) 8.0 24(2) MHz

fPLL_IN
(2)
PLL input clock duty cycle 40 - 60(2) %
fPLL_OUT PLL multiplier output clock 16(2) - 48 MHz
tLOCK PLL lock time - - 200(2) s
JitterPLL Cycle-to-cycle jitter - - 300(2) ps
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT.
6.3.10 Memory characteristics

Flash memory
The characteristics are given at TA = 40 to 105 C unless otherwise specified.
Table 46. Flash memory characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit
tprog 16-bit programming time TA = - 40 to +105 C 40 53.5 60 s

tERASE Page (2 KB) erase time TA = - 40 to +105 C 20 - 40 ms
tME Mass erase time TA = - 40 to +105 C 20 - 40 ms
Write mode - - 10 mA
IDD Supply current
Erase mode - - 12 mA
74/128 DocID025004 Rev 5

Table 47. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
NEND Endurance TA = 40 to +105 C 10 kcycle

1 kcycle(2) at TA = 85 C 30
tRET (2)
Data retention 1 kcycle at TA = 105 C 10 Year
10 kcycle(2) at TA = 55 C 20
2. Cycling performed over the whole temperature range.
6.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 48. They are based on the EMS levels and classes
defined in application note AN1709.
Table 48. EMS characteristics

Level/
Symbol Parameter Conditions
Class
VDD = 3.3 V, LQFP100, TA = +25 C,

Voltage limits to be applied on any I/O pin
VFESD fHCLK = 48 MHz, 2B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, LQFP100, TA = +25C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 48 MHz, 4B
pins to induce a functional disturbance conforming to IEC 61000-4-4
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
DocID025004 Rev 5 75/128

99
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 49. EMI characteristics

Max vs. [fHSE/fHCLK]
Monitored
Symbol Parameter Conditions Unit
frequency band
8/48 MHz
0.1 to 30 MHz -2
VDD = 3.6 V, TA = 25 C,
LQFP100 package 30 to 130 MHz 27 dBV
SEMI Peak level
compliant with 130 MHz to 1 GHz 17
IEC 61967-2
EMI Level 4 -
6.3.12 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
76/128 DocID025004 Rev 5

Table 50. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value(1)
Electrostatic discharge voltage TA = +25 C, conforming

VESD(HBM) All 2 2000 V
(human body model) to JESD22-A114
Electrostatic discharge voltage TA = +25 C, conforming WLCSP49 C3 250

VESD(CDM) V
(charge device model) to ANSI/ESD STM5.3.1 All others C4 500
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin.
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 51. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 C conforming to JESD78A II level A
6.3.13 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 A/+0 A range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 52.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
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99
Table 52. I/O current injection susceptibility

Functional
susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on BOOT0 and PF1 pins 0 NA

Injected current on PC0 pin 0 +5
Injected current on PA11 and PA12 pins with induced
IINJ 5 NA mA
leakage current on adjacent pins less than -1 mA
Injected current on all other FT and FTf pins 5 NA
Injected current on all other TTa, TC and RST pins 5 +5
6.3.14 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under the conditions summarized in Table 24: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant (except BOOT0).
Table 53. I/O static characteristics

TC and TTa I/O - - 0.3 VDDIOx +0.07(1)

FT and FTf I/O - - 0.475 VDDIOx0.2(1)
Low level input
VIL BOOT0 - - 0.3 VDDIOx0.3(1) V
voltage
All I/Os except
- - 0.3 VDDIOx
BOOT0 pin
TC and TTa I/O 0.445 VDDIOx+0.398(1) - -
FT and FTf I/O 0.5 VDDIOx +0.2(1) - -
High level input
VIH BOOT0 0.2 VDDIOx+0.95(1) - - V
voltage
All I/Os except
0.7 VDDIOx - -
BOOT0 pin
TC and TTa I/O - 200(1) -
Schmitt trigger (1)
Vhys FT and FTf I/O - 100 - mV
hysteresis
(1)
BOOT0 - 300 -
78/128 DocID025004 Rev 5

Table 53. I/O static characteristics (continued)

TC, FT and FTf I/O

TTa in digital mode - - 0.1
VSS VIN VDDIOx
TTa in digital mode
Input leakage - - 1
Ilkg VDDIOx VIN VDDA A
current(2)
TTa in analog mode
- - 0.2
VSS VIN VDDA
FT and FTf I/O
- - 10
VDDIOx VIN 5 V
Weak pull-up
RPU equivalent resistor VIN = VSS 25 40 55 k
(3)
Weak pull-down
RPD equivalent VIN = - VDDIOx 25 40 55 k
resistor(3)
CIO I/O pin capacitance - - 5 - pF
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 52:
I/O current injection susceptibility.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 22 for standard I/Os, and in Figure 23 for
5 V-tolerant I/Os. The following curves are design simulation results, not tested in
production.
DocID025004 Rev 5 79/128

99
Figure 22. TC and TTa I/O input characteristics

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Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics

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Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 21: Voltage characteristics).
The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see
Table 21: Voltage characteristics).
Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 24: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or
TC unless otherwise specified).
Table 54. Output voltage characteristics(1)

VOL Output low level voltage for an I/O pin CMOS port(2) - 0.4
|IIO| = 8 mA V
VOH Output high level voltage for an I/O pin VDDIOx 2.7 V VDDIOx0.4 -
VOL Output low level voltage for an I/O pin TTL port(2) - 0.4
|IIO| = 8 mA V
VOH Output high level voltage for an I/O pin VDDIOx 2.7 V 2.4 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3
V
VOH(3) Output high level voltage for an I/O pin VDDIOx 2.7 V VDDIOx1.3 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 6 mA - 0.4
V
VOH(3) Output high level voltage for an I/O pin VDDIOx 2 V VDDIOx0.4 -
VOL(4) Output low level voltage for an I/O pin - 0.4 V
|IIO| = 4 mA
VOH(4) Output high level voltage for an I/O pin VDDIOx0.4 - V
|IIO| = 20 mA
Output low level voltage for an FTf I/O pin in - 0.4 V
VOLFm+(3) VDDIOx 2.7 V
Fm+ mode
|IIO| = 10 mA - 0.4 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Data based on characterization results. Not tested in production.
4. Data based on characterization results. Not tested in production.
DocID025004 Rev 5 81/128

99
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 55, respectively. Unless otherwise specified, the parameters given are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 24: General operating conditions.
Table 55. I/O AC characteristics(1)(2)

OSPEEDRy
[1:0] value(1)
fmax(IO)out Maximum frequency(3) - 2 MHz

tf(IO)out Output fall time CL = 50 pF, VDDIOx 2 V - 125
ns
tr(IO)out Output rise time - 125
x0
tf(IO)out Output fall time CL = 50 pF, VDDIOx < 2 V - 125
ns
ns
01
tf(IO)out Output fall time CL = 50 pF, VDDIOx < 2 V - 62.5
ns
tr(IO)out Output rise time - 62.5
CL = 30 pF, VDDIOx 2.7 V - 50
CL = 50 pF, VDDIOx 2.7 V - 30
fmax(IO)out Maximum frequency(3) MHz
CL = 50 pF, 2 V VDDIOx < 2.7 V - 20
CL = 50 pF, VDDIOx < 2 V - 10
CL = 30 pF, VDDIOx 2.7 V - 5
CL = 50 pF, VDDIOx 2.7 V - 8
11 tf(IO)out Output fall time
CL = 50 pF, 2 V VDDIOx < 2.7 V - 12
CL = 50 pF, VDDIOx < 2 V - 25
ns
CL = 30 pF, VDDIOx 2.7 V - 5
CL = 50 pF, VDDIOx 2.7 V - 8
tr(IO)out Output rise time
CL = 50 pF, 2 V VDDIOx < 2.7 V - 12
CL = 50 pF, VDDIOx < 2 V - 25
82/128 DocID025004 Rev 5

Table 55. I/O AC characteristics(1)(2) (continued)

OSPEEDRy
[1:0] value(1)

ns
Fm+ tr(IO)out Output rise time - 34
configuration
(4) fmax(IO)out Maximum frequency(3) - 0.5 MHz
tf(IO)out Output fall time CL = 50 pF, VDDIOx < 2 V - 16
ns
Pulse width of external
- tEXTIpw signals detected by the - 10 - ns
EXTI controller
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a
description of GPIO Port configuration register.
3. The maximum frequency is defined in Figure 24.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091
for a detailed description of Fm+ I/O configuration.
Figure 24. I/O AC characteristics definition

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6.3.15 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent pull-
up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 24: General operating conditions.
Table 56. NRST pin characteristics

VIL(NRST) NRST input low level voltage - - - 0.3 VDD+0.07(1)

V
VIH(NRST) NRST input high level voltage - 0.445 VDD+0.398(1) - -
DocID025004 Rev 5 83/128

99
Table 56. NRST pin characteristics (continued)

NRST Schmitt trigger voltage

Vhys(NRST) - - 200 - mV
hysteresis
Weak pull-up equivalent
RPU VIN = VSS 25 40 55 k
resistor(2)
VF(NRST) NRST input filtered pulse - - - 100(1) ns
2.7 < VDD < 3.6 300(3) - -
VNF(NRST) NRST input not filtered pulse ns
(3)
2.0 < VDD < 3.6 500 - -
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
Figure 25. Recommended NRST pin protection
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1. The external capacitor protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 56: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
6.3.16 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under the conditions summarized in Table 24: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 57. ADC characteristics

Analog supply voltage for

VDDA - 2.4 - 3.6 V
ADC ON
Current consumption of
IDDA (ADC) VDDA = 3.3 V - 0.9 - mA
the ADC(1)
fADC ADC clock frequency - 0.6 - 14 MHz
fS(2) Sampling rate 12-bit resolution 0.043 - 1 MHz
84/128 DocID025004 Rev 5

Table 57. ADC characteristics (continued)

fADC = 14 MHz,
- - 823 kHz
fTRIG(2) External trigger frequency 12-bit resolution
12-bit resolution - - 17 1/fADC
VAIN Conversion voltage range - 0 - VDDA V
See Equation 1 and
RAIN(2) External input impedance - - 50 k
Table 58 for details
Sampling switch
RADC(2) - - - 1 k
resistance
Internal sample and hold
CADC(2) - - - 8 pF
capacitor
fADC = 14 MHz 5.9 s
tCAL(2)(3) Calibration time
- 83 1/fADC
1.5 ADC 1.5 ADC
ADC clock = HSI14 cycles + 2 - cycles + 3 -
fPCLK cycles fPCLK cycles
ADC_DR register ready
WLATENCY(2)(4) fPCLK
latency ADC clock = PCLK/2 - 4.5 -
cycle
fPCLK
ADC clock = PCLK/4 - 8.5 -
cycle
fADC = fPCLK/2 = 14 MHz 0.196 s
fADC = fPCLK/2 5.5 1/fPCLK
tlatr(2) Trigger conversion latency fADC = fPCLK/4 = 12 MHz 0.219 s
fADC = fPCLK/4 10.5 1/fPCLK
fADC = fHSI14 = 14 MHz 0.179 - 0.250 s
ADC jitter on trigger
JitterADC fADC = fHSI14 - 1 - 1/fHSI14
conversion
fADC = 14 MHz 0.107 - 17.1 s
tS(2) Sampling time
- 1.5 - 239.5 1/fADC
tSTAB(2) Stabilization time - 14 1/fADC
fADC = 14 MHz,
1 - 18 s
Total conversion time 12-bit resolution
tCONV(2)
(including sampling time) 14 to 252 (tS for sampling +12.5 for
12-bit resolution 1/fADC
successive approximation)
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 A on IDDA and 60 A
on IDD should be taken into account.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
DocID025004 Rev 5 85/128

99
Equation 1: RAIN max formula

TS
R AIN < ---------------------------------------------------------------
N+2
- R ADC
f ADC C ADC ln ( 2 )
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 58. RAIN max for fADC = 14 MHz

Ts (cycles) tS (s) RAIN max (k)(1)
1.5 0.11 0.4

7.5 0.54 5.9
13.5 0.96 11.4
28.5 2.04 25.2
41.5 2.96 37.2
55.5 3.96 50
71.5 5.11 NA
239.5 17.1 NA
Table 59. ADC accuracy(1)(2)(3)

Symbol Parameter Test conditions Typ Max(4) Unit
ET Total unadjusted error 1.3 2

EO Offset error fPCLK = 48 MHz, 1 1.5
fADC = 14 MHz, RAIN < 10 k
EG Gain error 0.5 1.5 LSB
VDDA = 3 V to 3.6 V
ED Differential linearity error TA = 25 C 0.7 1
EL Integral linearity error 0.8 1.5
EO Offset error fPCLK = 48 MHz, 1.9 2.8
EG Gain error 2.8 3 LSB
VDDA = 2.7 V to 3.6 V
ED Differential linearity error TA = - 40 to 105 C 0.7 1.3
EO Offset error fPCLK = 48 MHz, 1.9 2.8
EG Gain error 2.8 3 LSB
VDDA = 2.4 V to 3.6 V
ED Differential linearity error TA = 25 C 0.7 1.3
1. ADC DC accuracy values are measured after internal calibration.
86/128 DocID025004 Rev 5

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
Figure 26. ADC accuracy characteristics
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Figure 27. Typical connection diagram using the ADC
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1. Refer to Table 57: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 13: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
DocID025004 Rev 5 87/128

99
6.3.17 DAC electrical specifications
Table 60. DAC characteristics

Symbol Parameter Min Typ Max Unit Comments
Analog supply voltage for

VDDA 2.4 - 3.6 V -
DAC ON
Resistive load with buffer 5 - - k Load connected to VSSA

RLOAD(1)
ON 25 - - k Load connected to VDDA
When the buffer is OFF, the
Impedance output with Minimum resistive load between
RO(1) - - 15 k
buffer OFF DAC_OUT and VSS to have a
1% accuracy is 1.5 M
Maximum capacitive load at
CLOAD(1) Capacitive load - - 50 pF DAC_OUT pin (when the buffer
is ON).
It gives the maximum output
DAC_OUT Lower DAC_OUT voltage excursion of the DAC.
0.2 - - V
min(1) with buffer ON
It corresponds to 12-bit input
code (0x0E0) to (0xF1C) at
DAC_OUT Higher DAC_OUT voltage VDDA = 3.6 V and (0x155) and
- - VDDA 0.2 V
max(1) with buffer ON (0xEAB) at VDDA = 2.4 V
DAC_OUT Lower DAC_OUT voltage
- 0.5 - mV
min(1) with buffer OFF It gives the maximum output
DAC_OUT Higher DAC_OUT voltage excursion of the DAC.
- - VDDA 1LSB V
max(1) with buffer OFF
With no load, middle code
DAC DC current - - 600 A
(0x800) on the input
IDDA(1) consumption in quiescent
mode(2) With no load, worst code
- - 700 A
(0xF1C) on the input
Given for the DAC in 10-bit

Differential non linearity - - 0.5 LSB
configuration
DNL(3) Difference between two
consecutive code-1LSB) Given for the DAC in 12-bit
- - 2 LSB
configuration
Integral non linearity Given for the DAC in 10-bit
- - 1 LSB
(difference between configuration
measured value at Code i
INL(3)
and the value at Code i on a Given for the DAC in 12-bit
line drawn between Code 0 - - 4 LSB
configuration
and last Code 1023)
- - 10 mV -
Offset error
(difference between Given for the DAC in 10-bit at
- - 3 LSB
Offset(3) measured value at Code VDDA = 3.6 V
(0x800) and the ideal value
Given for the DAC in 12-bit at
= VDDA/2) - - 12 LSB
VDDA = 3.6 V
88/128 DocID025004 Rev 5

Table 60. DAC characteristics (continued)

Symbol Parameter Min Typ Max Unit Comments
Given for the DAC in 12-bit

Gain error(3) Gain error - - 0.5 %
configuration
Settling time (full scale: for a
10-bit input code transition
(3) between the lowest and the
tSETTLING - 3 4 s CLOAD 50 pF, RLOAD 5 k
highest input codes when
DAC_OUT reaches final
value 1LSB
Max frequency for a correct
Update DAC_OUT change when
- - 1 MS/s CLOAD 50 pF, RLOAD 5 k
rate(3) small variation in the input
code (from code i to i+1LSB)
Wakeup time from off state CLOAD 50 pF, RLOAD 5 k
tWAKEUP(3) (Setting the ENx bit in the - 6.5 10 s input code between lowest and
DAC Control register) highest possible ones.
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC - 67 40 dB No RLOAD, CLOAD = 50 pF
measurement
2. The DAC is in quiescent mode when it keeps the value steady on the output so no dynamic consumption is involved.
Figure 28. 12-bit buffered / non-buffered DAC
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
DocID025004 Rev 5 89/128

99
6.3.18 Comparator characteristics

Table 61. Comparator characteristics
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
VDDA Analog supply voltage - VDD - 3.6 V

Comparator input
VIN - 0 - VDDA -
voltage range
VREFINT scaler offset
VSC - - 5 10 mV
voltage
First VREFINT scaler activation after device 1000
VREFINT scaler startup - - (2)
tS_SC power on ms
time from power down
Next activations - - 0.2
Comparator startup Startup time to reach propagation delay
tSTART - - 60 s
time specification
Ultra-low power mode - 2 4.5
Low power mode - 0.7 1.5 s
Propagation delay for
200 mV step with Medium power mode - 0.3 0.6
100 mV overdrive
VDDA 2.7 V - 50 100
High speed mode ns
VDDA < 2.7 V - 100 240
tD
Ultra-low power mode - 2 7
Low power mode - 0.7 2.1 s
Propagation delay for
full range step with Medium power mode - 0.3 1.2
100 mV overdrive
VDDA 2.7 V - 90 180
High speed mode ns
VDDA < 2.7 V - 110 300
Voffset Comparator offset error - - 4 10 mV
Offset error
dVoffset/dT - - 18 - V/C
temperature coefficient
Ultra-low power mode - 1.2 1.5
COMP current Low power mode - 3 5

IDD(COMP) A
consumption Medium power mode - 10 15
High speed mode - 75 100
90/128 DocID025004 Rev 5

Table 61. Comparator characteristics (continued)

Symbol Parameter Conditions Min(1) Typ Max(1) Unit
No hysteresis
- - 0 -
(COMPxHYST[1:0]=00)
High speed mode 3 13
Low hysteresis
8
(COMPxHYST[1:0]=01) All other power 5 10
modes
Vhys Comparator hysteresis High speed mode 7 26 mV
Medium hysteresis
15
modes
High speed mode 18 49
High hysteresis
31
modes
2. For more details and conditions see Figure 29: Maximum VREFINT scaler startup time from power down.
Figure 29. Maximum VREFINT scaler startup time from power down
ss s

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ss s

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DocID025004 Rev 5 91/128

99
6.3.19 Temperature sensor characteristics
Table 62. TS characteristics

TL(1) VSENSE linearity with temperature - 1 2 C

(1)
Avg_Slope Average slope 4.0 4.3 4.6 mV/C
(2)
V30 Voltage at 30 C ( 5 C) 1.34 1.43 1.52 V
tSTART(1) ADC_IN16 buffer startup time - - 10 s
ADC sampling time when reading the
tS_temp(1) 4 - - s
temperature
2. Measured at VDDA = 3.3 V 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 3:
Temperature sensor calibration values.
6.3.20 VBAT monitoring characteristics
Table 63. VBAT monitoring characteristics

R Resistor bridge for VBAT - 2 x 50 - k

Q Ratio on VBAT measurement - 2 - -
Er(1) Error on Q 1 - +1 %
tS_vbat(1) ADC sampling time when reading the VBAT 4 - - s
6.3.21 Timer characteristics

The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 64. TIMx characteristics

- - 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 48 MHz - 20.8 - ns
Timer external clock - - fTIMxCLK/2 - MHz
fEXT frequency on CH1 to
CH4 fTIMxCLK = 48 MHz - 24 - MHz
16-bit timer maximum - - 216 - tTIMxCLK

period fTIMxCLK = 48 MHz - 1365 - s
tMAX_COUNT
32-bit counter - - 232 - tTIMxCLK
maximum period fTIMxCLK = 48 MHz - 89.48 - s
92/128 DocID025004 Rev 5

Table 65. IWDG min/max timeout period at 40 kHz (LSI)(1)

Min timeout RL[11:0]= Max timeout RL[11:0]=
Prescaler divider PR[2:0] bits Unit
0x000 0xFFF
/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8 ms
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 or 7 6.4 26214.4
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 66. WWDG min/max timeout value at 48 MHz (PCLK)

Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0853 5.4613
2 1 0.1706 10.9226
ms
4 2 0.3413 21.8453
8 3 0.6826 43.6906
6.3.22 Communication interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
Standard-mode (Sm): with a bit rate up to 100 kbit/s
Fast-mode (Fm): with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2Cx peripheral is
properly configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not true open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
DocID025004 Rev 5 93/128

99
Table 67. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit
Maximum width of spikes that are

tAF 50(2) 260(3) ns
suppressed by the analog filter
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 68 for SPI or in Table 69 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and
supply voltage conditions summarized in Table 24: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 68. SPI characteristics(1)

fSCK Master mode - 18

SPI clock frequency MHz
1/tc(SCK) Slave mode - 18
tr(SCK) SPI clock rise and fall
Capacitive load: C = 15 pF - 6 ns
tf(SCK) time
tsu(NSS) NSS setup time Slave mode 4Tpclk -
th(NSS) NSS hold time Slave mode 2Tpclk + 10 -
tw(SCKH) Master mode, fPCLK = 36 MHz,
SCK high and low time Tpclk/2 -2 Tpclk/2 + 1
tw(SCKL) presc = 4
tsu(MI) Master mode 4 -

Data input setup time
tsu(SI) Slave mode 5 -
th(MI) Master mode 4 -
Data input hold time ns
th(SI) Slave mode 5 -
ta(SO)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3Tpclk
(3)
tdis(SO) Data output disable time Slave mode 0 18
tv(SO) Data output valid time Slave mode (after enable edge) - 22.5
tv(MO) Data output valid time Master mode (after enable edge) - 6
th(SO) Slave mode (after enable edge) 11.5 -
Data output hold time
th(MO) Master mode (after enable edge) 2 -
SPI slave input clock
DuCy(SCK) Slave mode 25 75 %
duty cycle
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
94/128 DocID025004 Rev 5

Figure 30. SPI timing diagram - slave mode and CPHA = 0
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026,LQSXW )LUVWELW,1 1H[WELWV,1 /DVWELW,1
06Y9
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
DocID025004 Rev 5 95/128

99
Figure 32. SPI timing diagram - master mode
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Table 69. I2S characteristics(1)

Master mode (data: 16 bits, Audio

fCK 1.597 1.601
I2S clock frequency frequency = 48 kHz) MHz
1/tc(CK)
Slave mode 0 6.5
tr(CK) I2S clock rise time - 10
Capacitive load CL = 15 pF
tf(CK) I2S clock fall time - 12
tw(CKH) I2S clock high time Master fPCLK= 16 MHz, audio 306 -
tw(CKL) 2
I S clock low time frequency = 48 kHz 312 -
ns
tv(WS) WS valid time Master mode 2 -
th(WS) WS hold time Master mode 2 -
tsu(WS) WS setup time Slave mode 7 -
th(WS) WS hold time Slave mode 0 -
I2S slave input clock duty
DuCy(SCK) Slave mode 25 75 %
cycle
96/128 DocID025004 Rev 5

Table 69. I2S characteristics(1) (continued)

tsu(SD_MR) Master receiver 6 -

Data input setup time
tsu(SD_SR) Slave receiver 2 -
(2)
th(SD_MR) Master receiver 4 -
Data input hold time
(2)
th(SD_SR) Slave receiver 0.5 -
ns
tv(SD_MT)(2) Master transmitter - 4
Data output valid time
tv(SD_ST)(2) Slave transmitter - 20
th(SD_MT) Master transmitter 0 -
Data output hold time
th(SD_ST) Slave transmitter 13 -
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns.
Figure 33. I2S slave timing diagram (Philips protocol)
WF&.
&32/
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WVX:6 WY6'B67 WK6'B67
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WVX6'B65 WK6'B65
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06Y9
1. Measurement points are done at CMOS levels: 0.3 VDDIOx and 0.7 VDDIOx.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
DocID025004 Rev 5 97/128

99
Figure 34. I2S master timing diagram (Philips protocol)

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WF&.
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06Y9

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
98/128 DocID025004 Rev 5

USB characteristics
The STM32F072x8/xB USB interface is fully compliant with the USB specification version
2.0 and is USB-IF certified (for Full-speed device operation).
Table 70. USB electrical characteristics

Symbol Parameter Conditions Min. Typ Max. Unit
USB transceiver operating

VDDIO2 - 3.0(1) - 3.6 V
voltage
tSTARTUP(2) USB transceiver startup time - - - 1.0 s
Embedded USB_DP pull-up
RPUI - 1.1 1.26 1.5
value during idle
k
Embedded USB_DP pull-up
RPUR - 2.0 2.26 2.6
value during reception
Driving high
ZDRV(2) Output driver impedance(3) 28 40 44
and low
1. The STM32F072x8/xB USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V voltage range.
3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching
impedance is already included in the embedded driver.
CAN (controller area network) interface

Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
DocID025004 Rev 5 99/128

99
Package information STM32F072x8 STM32F072xB
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
7.1 UFBGA100 package information

UFBGA100 is a 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra-fine-profile ball grid array
package.
Figure 35. UFBGA100 package outline

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1. Drawing is not to scale.
Table 71. UFBGA100 package mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.
A - - 0.600 - - 0.0236
A1 - - 0.110 - - 0.0043
A2 - 0.450 - - 0.0177 -
A3 - 0.130 - - 0.0051 0.0094
A4 - 0.320 - - 0.0126 -
100/128 DocID025004 Rev 5

STM32F072x8 STM32F072xB Package information
Table 71. UFBGA100 package mechanical data (continued)

Symbol
Min. Typ. Max. Min. Typ. Max.
b 0.240 0.290 0.340 0.0094 0.0114 0.0134

D 6.850 7.000 7.150 0.2697 0.2756 0.2815
D1 - 5.500 - - 0.2165 -
E 6.850 7.000 7.150 0.2697 0.2756 0.2815
E1 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
Z - 0.750 - - 0.0295 -
ddd - - 0.080 - - 0.0031
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 36. Recommended footprint for UFBGA100 package
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Table 72. UFBGA100 recommended PCB design rules

Dimension Recommended values
Pitch 0.5
Dpad 0.280 mm
0.370 mm typ. (depends on the solder mask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
DocID025004 Rev 5 101/128

124
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 37. UFBGA100 package marking example
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
102/128 DocID025004 Rev 5

7.2 LQFP100 package information

LQFP100 is a100-pin, 14 x 14 mm low-profile quad flat package.
Figure 38. LQFP100 package outline
6($7,1*3/$1(
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Table 73. LQPF100 package mechanical data

Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
DocID025004 Rev 5 103/128

124
Table 73. LQPF100 package mechanical data (continued)

Symbol
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0 3.5 7.0 0.0 3.5 7.0
ccc - - 0.080 - - 0.0031
Figure 39. Recommended footprint for LQFP100 package

DLF
1. Dimensions are expressed in millimeters.
104/128 DocID025004 Rev 5

Device marking
location.
Figure 40. LQFP100 package marking example

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DocID025004 Rev 5 105/128

124
7.3 UFBGA64 package information

UFBGA64 is a 64-ball, 5 x 5 mm, 0.5 mm pitch ultra-fine-profile ball grid array
package.
Figure 41. UFBGA64 package outline

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III 0 = $B0(B9
Table 74. UFBGA64 package mechanical data

Symbol
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

A1 0.050 0.080 0.110 0.0020 0.0031 0.0043
A2 0.400 0.450 0.500 0.0157 0.0177 0.0197
A3 0.080 0.130 0.180 0.0031 0.0051 0.0071
A4 0.270 0.320 0.370 0.0106 0.0126 0.0146
b 0.170 0.280 0.330 0.0067 0.0110 0.0130
D 4.850 5.000 5.150 0.1909 0.1969 0.2028
D1 3.450 3.500 3.550 0.1358 0.1378 0.1398
E 4.850 5.000 5.150 0.1909 0.1969 0.2028
E1 3.450 3.500 3.550 0.1358 0.1378 0.1398
e - 0.500 - - 0.0197 -
F 0.700 0.750 0.800 0.0276 0.0295 0.0315
106/128 DocID025004 Rev 5

Table 74. UFBGA64 package mechanical data (continued)

Symbol
A 0.460 0.530 0.600 0.0181 0.0209 0.0236

ddd - - 0.080 - - 0.0031
eee - - 0.150 - - 0.0059
fff - - 0.050 - - 0.0020
Figure 42. Recommended footprint for UFBGA64 package
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Table 75. UFBGA64 recommended PCB design rules

Dimension Recommended values
Pitch 0.5
Dpad 0.280 mm
0.370 mm typ. (depends on the soldermask
Dsm
registration tolerance)
Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
DocID025004 Rev 5 107/128

124
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 43. UFBGA64 package marking example
W
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108/128 DocID025004 Rev 5


LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package.
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Table 76. LQFP64 package mechanical data

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -
DocID025004 Rev 5 109/128

124
Table 76. LQFP64 package mechanical data (continued)

Symbol
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0 3.5 7 0 3.5 7
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031

DLF
110/128 DocID025004 Rev 5

Device marking
location.
Z
W
5
670)
5%7

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DocID025004 Rev 5 111/128

124
7.5 WLCSP49 package information

WLCSP49 is a 49-ball, 3.277 x 3.109 mm, 0.4 mm pitch wafer-level chip-scale package.
Figure 47. WLCSP49 package outline

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112/128 DocID025004 Rev 5

Table 77. WLCSP49 package mechanical data

Symbol
A 0.525 0.555 0.585 0.0207 0.0219 0.0230
A1 - 0.175 - - 0.0069 -
A2 - 0.380 - - 0.0150 -
(2)
A3 - 0.025 - - 0.0010 -
b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110
D 3.242 3.277 3.312 0.1276 0.1290 0.1304
E 3.074 3.109 3.144 0.1210 0.1224 0.1238
e - 0.400 - - 0.0157 -
e1 - 2.400 - - 0.0945 -
e2 - 2.400 - - 0.0945 -
F - 0.4385 - - 0.0173 -
G - 0.3545 - - 0.0140 -
aaa - - 0.100 - - 0.0039
bbb - - 0.100 - - 0.0039
ccc - - 0.100 - - 0.0039
ddd - - 0.050 - - 0.0020
eee - - 0.050 - - 0.0020
2. Back side coating
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
DocID025004 Rev 5 113/128

124
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 48. WLCSP49 package marking example
W

W
)&%<

Z
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D^s
114/128 DocID025004 Rev 5


LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package.
6($7,1*
3/$1(
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PP
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FFF &
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,'(17,),&$7,21
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DocID025004 Rev 5 115/128

124
Table 78. LQFP48 package mechanical data

Symbol
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0 3.5 7 0 3.5 7
ccc - - 0.080 - - 0.0031

DLG
116/128 DocID025004 Rev 5

Device marking
location.
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DocID025004 Rev 5 117/128

124
7.7 UFQFPN48 package information

UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.
Figure 52. UFQFPN48 package outline

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ODVHUPDUNLQJDUHD
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7 6HDWLQJ
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2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
118/128 DocID025004 Rev 5

Table 79. UFQFPN48 package mechanical data

Symbol
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
Figure 53. Recommended footprint for UFQFPN48 package

$%B)3B9
DocID025004 Rev 5 119/128

124
Device marking
location.
Figure 54. UFQFPN48 package marking example
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120/128 DocID025004 Rev 5

7.8 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 24: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x JA)
Where:
TA max is the maximum ambient temperature in C,
JA is the package junction-to-ambient thermal resistance, in C/W,
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL IOL) + ((VDDIOx VOH) IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 80. Package thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient

55
UFBGA100 - 7 7 mm
42
LQFP100 - 14 14 mm
65
UFBGA64 - 5 5 mm / 0.5 mm pitch
JA 44 C/W
LQFP64 - 10 10 mm / 0.5 mm pitch
54
LQFP48 - 7 7 mm
32
UFQFPN48 - 7 7 mm
49
WLCSP49 - 0.4 mm pitch
7.8.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
7.8.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Ordering information.
DocID025004 Rev 5 121/128

124
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at

maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F072x8/xB at maximum dissipation, it is
useful to calculate the exact power consumption and junction temperature to determine
which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application

Assuming the following application conditions:
Maximum temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50
mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL
= 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level
with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA 3.5 V= 175 mW
PIOmax = 20 8 mA 0.4 V + 8 20 mA 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax= 175 + 272 = 447 mW
Using the values obtained in Table 80 TJmax is calculated as follows:
For LQFP64, 45 C/W
TJmax = 82 C + (45 C/W 447 mW) = 82 C + 20.115 C = 102.115 C
This is within the range of the suffix 6 version parts (40 < TJ < 105 C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Ordering information).
Note: With this given PDmax we can find the TAmax allowed for a given device temperature range
(order code suffix 6 or 7).
Suffix 6: TAmax = TJmax - (45C/W 447 mW) = 105-20.115 = 84.885 C
Suffix 7: TAmax = TJmax - (45C/W 447 mW) = 125-20.115 = 104.885 C
Example 2: High-temperature application

Using the same rules, it is possible to address applications that run at high temperatures
with a low dissipation, as long as junction temperature TJ remains within the specified
range.
Assuming the following application conditions:
Maximum temperature TAmax = 100 C (measured according to JESD51-2), IDDmax =
20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with
IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA 3.5 V= 70 mW
PIOmax = 20 8 mA 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
122/128 DocID025004 Rev 5

Using the values obtained in Table 80 TJmax is calculated as follows:

For LQFP64, 45 C/W
TJmax = 100 C + (45 C/W 134 mW) = 100 C + 6.03 C = 106.03 C
This is above the range of the suffix 6 version parts (40 < TJ < 105 C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Ordering information) unless we reduce the power dissipation in order to be able
to use suffix 6 parts.
Refer to Figure 55 to select the required temperature range (suffix 6 or 7) according to your
temperature or power requirements.
Figure 55. LQFP64 PD max versus TA

3'P:
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DocID025004 Rev 5 123/128

124
Ordering information STM32F072x8 STM32F072xB
8 Ordering information
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Table 81. Ordering information scheme

Example: STM32 F 072 R 8 T 6 x
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
072 = STM32F072xx
Pin count
C = 48/49 pins
R = 64 pins
V = 100 pins
User code memory size

8 = 64 Kbyte
B = 128 Kbyte
Package
H = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = 40 to 85 C
7 = 40 to 105 C
Options
xxx = code ID of programmed parts (includes packing type)
TR = tape and reel packing
blank = tray packing
124/128 DocID025004 Rev 5

STM32F072x8 STM32F072xB Revision history
9 Revision history
Table 82. Document revision history

Date Revision Changes
13-Jan-2014 1 Initial release.

Updated Reset and power management data in Features.
Updated tS_vrefint in Table: Embedded internal reference
voltage.
Updated VHSEH and VHSEL in Table: High-speed external user
clock characteristics.
Updated VLSEH and VLSEL in Table: Low-speed external user
clock characteristics.
21-Feb-2014 2
Updated tS_temp in Table: TS characteristics.
Updated tS_vbat in Table: VBAT monitoring characteristics.
Updated Section: I2C interface characteristics.
Updated Figure: UFBGA100 package top view and Figure:
WLCSP49 package top view.
Modified value of ts_sc and removed row VBG in Table:
Comparator characteristics.
Section 2: Description:
Figure 1: Block diagram - AF number corrected
UFBGA64 package added
Section 3: Functional overview:
Table 7: Timer feature comparison - added number of
complementary outputs for TIM1, 15, 16 and TIM17
Section 4: Pinouts and pin descriptions: UFBGA64 added
Section 5: Memory mapping:
Figure 10: STM32F072xB memory map updated
Section 6: Electrical characteristics:
Table 21: Voltage characteristics and Table 22: Current
characteristics updated
Table 24: General operating conditions - footnote for VIN
18-Sep-2015 3 Table 28: Embedded internal reference voltage - tSTART
parameter added
Table 31: Typical and maximum consumption in Stop and
Standby modes updated
Merger of tables 33 and 34 into Table 33: Typical current
consumption, code executing from Flash memory, running
from HSE 8 MHz crystal
Table 37: High-speed external user clock characteristics:
replaced VDD with VDDIOX
Table 38: Low-speed external user clock characteristics
and Table 40: LSE oscillator characteristics (fLSE = 32.768
kHz): replaced VDD with VDDIOX
Table 41: HSI oscillator characteristics and Figure 19: HSI
oscillator accuracy characterization results for soldered
parts updated
DocID025004 Rev 5 125/128

127
Revision history STM32F072x8 STM32F072xB
Table 82. Document revision history (continued)

Table 42: HSI14 oscillator characteristics: changed the min

value for ACCHSI14
Table 46: Flash memory characteristics: removed Vprog
Table 49: EMI characteristics updated
Table 50: ESD absolute maximum ratings updated
Table 57: ADC characteristics - updated some parameter
values, test conditions and added footnotes (3) and (4)
Table 60: DAC characteristics - IDDA max value (DAC DC
current consumption) updated
Table 61: Comparator characteristics: changed the
18-Sep-2015 3 (continued)
description and values for tS_SC parameter
Table 62: TS characteristics: changed the min value for
tS-temp
Table 63: VBAT monitoring characteristics: changed the
typical value for R parameter
Table 69: I2S characteristics: updated the min value for data
input hold time (master and slave receiver)
Section 7: Package information:
information generally updated, UFBGA64 added
Section 8: Part numbering: UFBGA64 added
Section 2: Description:
Figure 1: Block diagram updated
Section 3: Functional overview:
Figure 2: Clock tree updated
Section 4: Pinouts and pin descriptions
Package pinout figures updated (look and feel)
Figure 9: WLCSP49 package pinout - now presented in
top view
Section 5: Memory mapping:
added information on STM32F072x8 difference versus
STM32F072xB map in Figure 10
17-Dec-2015 4
Table 28: Embedded internal reference voltage: removed
-40-to-85 condition for VREFINT and associated note
Table 61: Comparator characteristics - min value for VDDA
replaced with VDD
Figure 29: Maximum VREFINT scaler startup time from
power down added
Table 53: I/O static characteristics - note removed
Table 69: I2S characteristics: table reorganized
Section 8: Ordering information:
added tray packing to options
126/128 DocID025004 Rev 5

STM32F072x8 STM32F072xB Revision history
Table 82. Document revision history (continued)


Table 40: LSE oscillator characteristics (fLSE = 32.768 kHz)
- information on configuring different drive capabilities
removed. See the corresponding reference manual.
Table 28: Embedded internal reference voltage - VREFINT
values
10-Jan-2017 5 Table 60: DAC characteristics - min. RLOAD to VDDA defined
Figure 30: SPI timing diagram - slave mode and CPHA = 0
and Figure 31: SPI timing diagram - slave mode and CPHA
= 1 enhanced and corrected
Section 8: Ordering information:
The name of the section changed from the previous Part
numbering
DocID025004 Rev 5 127/128

127
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to STs terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
2017 STMicroelectronics All rights reserved
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STM32F072x8 STM32F072xB

ARM-based 32-bit MCU, up to 128 KB Flash, crystal-less USB

STM32F072x8 STM32F072C8, STM32F072R8, STM32F072V8,

January 2017 DocID025004 Rev 5 1/128

2/128 DocID025004 Rev 5

3.14.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DocID025004 Rev 5 3/128

6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

4/128 DocID025004 Rev 5

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

DocID025004 Rev 5 5/128

Table 47. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

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Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DocID025004 Rev 5 7/128

Figure 49. LQFP48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

8/128 DocID025004 Rev 5

DocID025004 Rev 5 9/128

The STM32F072x8/xB microcontrollers incorporate the high-performance

10/128 DocID025004 Rev 5

Table 2. STM32F072x8/xB family device features and peripheral counts

Flash memory (Kbyte) 64 128 64 128 64 128

DocID025004 Rev 5 11/128

Figure 1. Block diagram

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12/128 DocID025004 Rev 5

Figure 1 shows the general block diagram of the STM32F072x8/xB devices.

3.1 ARM-Cortex-M0 core

3.3 Boot modes

DocID025004 Rev 5 13/128

3.4 Cyclic redundancy check calculation unit (CRC)

3.5 Power management

3.5.1 Power supply schemes

3.5.2 Power supply supervisors

14/128 DocID025004 Rev 5

3.5.3 Voltage regulator

3.5.4 Low-power modes

3.6 Clocks and startup

DocID025004 Rev 5 15/128

Figure 2. Clock tree

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16/128 DocID025004 Rev 5

3.7 General-purpose inputs/outputs (GPIOs)

3.8 Direct memory access controller (DMA)

3.9 Interrupts and events

3.9.1 Nested vectored interrupt controller (NVIC)

DocID025004 Rev 5 17/128

3.9.2 Extended interrupt/event controller (EXTI)

3.10 Analog-to-digital converter (ADC)

3.10.1 Temperature sensor

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