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STM 32 WB 10 CC

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STM32WB10CC

Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4


with FPU, Bluetooth® 5.4 radio solution
Datasheet - production data

Features
• Include ST state-of-the-art patented
technology
• Radio
UFQFPN48
– 2.4 GHz
7 x 7 mm
– RF transceiver supporting Bluetooth® 5.4 solder pad
specification
– RX sensitivity: -95.5 dBm (Bluetooth® Low • Performance benchmark
Energy at 1 Mbps) – 1.25 DMIPS/MHz (Drystone 2.1)
– Programmable output power up to +4 dBm – 223.03 CoreMark® (3.48 CoreMark/MHz at
with 1 dB steps 64 MHz)
– Integrated balun to reduce BOM • Energy benckmark
– Support for 1 Mbps – 318 ULPMark™ CP score
– Support GATT caching
• Supply and reset management
– Support EATT (enhanced ATT)
– Ultra-safe, low-power BOR (brownout
– Dedicated Arm® 32-bit Cortex® M0+ CPU reset) with five selectable thresholds
for real-time Radio layer
– Ultra-low-power POR/PDR
– Accurate RSSI to enable power control
– Programmable voltage detector (PVD)
– Suitable for systems requiring compliance
– VBAT mode with RTC and backup registers
with radio frequency regulations ETSI EN
300 328, EN 300 440, FCC CFR47 Part 15 • Clock sources
and ARIB STD-T66 – 32 MHz crystal oscillator with integrated
– Support for external PA trimming capacitors (Radio and CPU clock)
– Available integrated passive device (IPD) – 32 kHz crystal oscillator for RTC (LSE)
companion chip for optimized matching – Internal low-power 32 kHz RC (LSI1)
solution (MLPF-WB-01E3) – Internal low-drift 32 kHz (stability
• Ultra-low-power platform ±500 ppm) RC (LSI2)
– 2.0 to 3.6 V power supply – Internal multispeed 100 kHz to 48 MHz
– – 10 °C to +85 °C temperature range oscillator, factory-trimmed
– 18 nA shutdown mode – High speed internal 16 MHz factory
trimmed RC (±1%)
– 700 nA Standby mode + RTC + 48 KB
RAM – 1x PLL for system clock, ADC
– Radio: Rx 7.7 mA / Tx at 0 dBm 8.6 mA • Memories
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, – 320 KB flash memory with sector
adaptive real-time accelerator (ART protection (PCROP) against R/W
Accelerator) allowing 0-wait-state execution operations, enabling radio stack and
from flash memory, frequency up to 64 MHz, application
MPU, 80 DMIPS, and DSP instructions – 48 KB SRAM, including 36 KB with
hardware parity check

November 2023 DS13259 Rev 7 1/112


This is information on a product in full production. www.st.com
STM32WB10CC

– 20x 32-bit backup register • Security and ID


– Boot loader supporting USART, SPI, I2C – Secure firmware installation (SFI) for
interfaces Bluetooth® Low Energy SW stack
– 1 Kbyte (128 double words) OTP – 2x hardware encryption AES maximum
– OTA (over the air) Bluetooth® Low Energy 256-bit for the application and the
Bluetooth® Low Energy
• Rich analog peripherals (down to 2.0 V)
– HW public key authority (PKA)
– 12-bit ADC 2.5 Msps, 190 µA/Msps
– Cryptographic algorithms: RSA,
• System peripherals Diffie-Helman, ECC over GF(p)
– Inter processor communication controller – True random number generator (RNG)
(IPCC) for communication with Bluetooth®
– Sector protection against R/W operation
Low Energy
(PCROP)
– HW semaphores for resource sharing
– CRC calculation unit
between CPUs
– Die information: 96-bit unique ID
– 1x DMA controller (7x channels) supporting
ADC, SPI, I2C, USART, AES, timers – IEEE 64-bit unique ID, possibility to derive
Bluetooth® Low Energy 48-bit EUI
– 1x USART (ISO 7816, IrDA, SPI Master,
Modbus, and Smartcard mode) • Up to 30 fast I/Os, 28 of them 5 V-tolerant
– 1x SPI 32 Mbit/s • Development support
– 1x I2C (SMBus/PMBus®) – Serial wire debug (SWD), JTAG for the
– Touch sensing controller, up to eight application processor
sensors – Application cross trigger
– 1x 16-bit, four channels advanced timer • ECOPACK2 compliant package
– 1x 32-bit, four channels timer
– 2x 16-bit ultra-low-power timer
– 1x independent Systick
– 1x independent watchdog
– 1x window watchdog

2/112 DS13259 Rev 7


STM32WB10CC Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . 14
3.3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.3 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Boot modes and FW update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.1 RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.2 Bluetooth Low Energy general description . . . . . . . . . . . . . . . . . . . . . . 18
3.6.3 RF pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6.4 Typical RF application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.2 Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.3 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 35
3.13.2 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 36

DS13259 Rev 7 3/112


5
Contents STM32WB10CC

3.14 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36


3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.15 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.16 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.17.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.17.2 General-purpose timer (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.17.3 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 39
3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.17.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.17.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.18 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 40
3.19 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . 42
3.21 Serial peripheral interface (SPI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.22 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.22.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 43

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.1 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4/112 DS13259 Rev 7


STM32WB10CC Contents

6.3.3 RF BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57


6.3.4 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 60
6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 60
6.3.6 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.8 Wake-up time from Low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.12 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.14 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.18 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.19 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 91
6.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.21 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.22 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.23 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . . 97

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103


7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.3.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.3.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 106

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

DS13259 Rev 7 5/112


5
List of tables STM32WB10CC

List of tables

Table 1. STM32WB10CC device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . 11


Table 2. Access status vs. readout protection level and execution modes . . . . . . . . . . . . . . . . . . . 15
Table 3. RF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Functionalities depending on system operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. STM32WB10CC modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. STM32WB10CC CPU1 peripherals interconnect matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 11. Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 14. STM32WB10CC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 15. Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 16. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 17. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 18. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 19. Main performance at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 20. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 21. RF transmitter BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 22. RF transmitter BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 23. RF receiver BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 24. RF BLE power consumption for VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 27. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 28. Current consumption in Run and Low-power run modes, code with data processing
running from flash memory, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . . 63
Table 29. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 30. Typical current consumption in Run and Low-power run modes, with different codes
running from flash memory, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V . . . . . . 64
Table 31. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 32. Current consumption in Sleep and Low-power sleep modes, flash memory ON . . . . . . . . 65
Table 33. Current consumption in Low-power sleep modes, flash memory in Power down. . . . . . . . 65
Table 34. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 35. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 36. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 37. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 38. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 39. Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 40. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 41. Low-power mode wake-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 42. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 43. Wake-up time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 44. HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6/112 DS13259 Rev 7


STM32WB10CC List of tables

Table 45. HSE clock source requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73


Table 46. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 47. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 48. Low-speed external user clock characteristics, bypass mode . . . . . . . . . . . . . . . . . . . . . . 76
Table 49. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 50. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Table 51. LSI1 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 52. LSI2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 53. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 54. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 55. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 56. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 57. EMI characteristics for fHSE / fCPUM4, fCPUM0 = 32 MHz / 64 MHz, 32 MHz . . . . . . . . 84
Table 58. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 59. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 60. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 61. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 62. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 63. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 64. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 65. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 66. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 67. Maximum ADC RAIN values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 68. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 69. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 70. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 71. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 72. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 73. IWDG min/max timeout period at 32 kHz (LSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 74. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 75. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 76. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 77. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 78. SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 79. UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 80. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 81. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

DS13259 Rev 7 7/112


7
List of figures STM32WB10CC

List of figures

Figure 1. STM32WB10CC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12


Figure 2. STM32WB10CC RF front-end block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. External components for the RF part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 6. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 7. STM32WB10CCU UFQFPN48 pinout (1) (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 8. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 12. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 13. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 14. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 15. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 16. Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 17. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 18. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 19. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 20. Typical connection diagram when using the ADC
with FT/TT pins featuring analog switch function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 21. SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 22. SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 23. SPI timing diagram - Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 24. UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 25. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

8/112 DS13259 Rev 7


STM32WB10CC Introduction

1 Introduction

This document provides the ordering information and mechanical device characteristics of
the STM32WB10CC microcontroller, based on Arm® cores(a). Throughout the whole
document TBD indicates a value to be defined.
This document must be read with the reference manual (RM0478), available from the
STMicroelectronics website www.st.com.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32WB10CC errata sheet (ES0556), available from the STMicroelectronics
website www.st.com.
For information on the Arm® Cortex®-M4 and Cortex®-M0+ cores, refer, respectively, to the
Cortex®-M4 Technical Reference Manual and to the Cortex®-M0+ Technical Reference
Manual, both available on the www.arm.com website.
For information on Bluetooth® refer to www.bluetooth.com.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

DS13259 Rev 7 9/112


43
Description STM32WB10CC

2 Description

The STM32WB10CC multiprotocol wireless and ultra-low-power device embeds a powerful


and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification 5.4.
It contains a dedicated Arm® Cortex®-M0+ for performing all the real-time low layer
operation.
The device is designed to be extremely low-power and is based on the high-performance
Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core
features a Floating point unit (FPU) single precision that supports all Arm®
single-precision data-processing instructions and data types. It also implements a full set of
DSP instructions and a memory protection unit (MPU) that enhances application security.
Enhanced inter-processor communication is provided by the IPCC with six bidirectional
channels. The HSEM provides hardware semaphores used to share common resources
between the two processors.
The device embeds high-speed memories (320 Kbytes of flash memory, 48 Kbytes of
SRAM) and an extensive range of enhanced I/Os and peripherals.
Direct data transfer between memory and peripherals and from memory to memory is
supported by seven DMA channels with a full flexible channel mapping by the DMAMUX
peripheral.
The device features several mechanisms for embedded flash memory and SRAM: readout
protection, write protection and proprietary code readout protection. Portions of the memory
can be secured for Cortex® -M0+ exclusive access.
The AES encryption engine, PKA, and RNG enable upper layer cryptography.
The device offers a fast 12-bit ADC.
The device embeds a low-power RTC, one advanced 16-bit timer, one general-purpose
32-bit timer, and two 16-bit low-power timers.
In addition, up to three capacitive sensing channels are available.
The STM32WB10CC also features standard and advanced communication interfaces,
namely one USART (ISO 7816, IrDA, Modbus, and Smartcard mode), one I2C
(SMBus/PMBus), one SPI up to 32 MHz.
The STM32WB10CC operates in the -10 to +85 °C (+105 °C junction) temperature range
from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving modes enables the
design of low-power applications.
The device includes independent power supplies for analog input for ADC.
A VBAT dedicated supply allows the device to back up the LSE 32.768 kHz oscillator, the
RTC and the backup registers, thus enabling the STM32WB10CC to supply these functions
even if the main VDD is not present through a CR2032-like battery, a Supercap or a small
rechargeable battery.
The STM32WB10CC is available in a 48-pin UFQFPN package.

10/112 DS13259 Rev 7


STM32WB10CC Description

Table 1. STM32WB10CC device features and peripheral counts


Feature STM32WB10CC

Flash memory density 320 Kbytes


SRAM density 48 Kbytes
BLE 5.4 (1 Mbps)
Advanced 1 (16-bit)
General purpose 1 (32-bit)
Timers
Low power 2 (16-bit)
SysTick 1
SPI 1
Communication
I2C 1
interface
(1)
USART 1
RTC 1
Tamper pin 1
Wakeup pin 2
GPIOs 30
Capacitive sensing 3
12-bit ADC 13 channels
Number of channels (including 3 internal)
Internal Vref Yes
Max CPU frequency 64 MHz
Ambient operating temperature:-10 to +85 °C
Operating temperature
Junction temperature: -10 to 105 °C
Operating voltage 2.0 to 3.6 V
UFQFPN48
Package
7 mm x 7 mm, 0.5 mm pitch, solder pad
1. USART peripheral can be used as SPI.

DS13259 Rev 7 11/112


43
Description STM32WB10CC

Figure 1. STM32WB10CC block diagram

APB asynchronous

AHB asynchronous
RCC2

CTI
NVIC BLE IP

AHB Lite
LSI2
32 kHz
Cortex-M0+ BLE RF IP
HSE2
32 MHz

WKUP
32 KB SRAM2a
BLE
LSE
RTC2 32 kHz
320 KB Flash

4 KB SRAM2b
shared memory

Arbiter + ART
LSI1
JTAG/SWD

I-WDG 32 kHz
PKA + RAM
TAMP
HSEM

AHB lite (shared)


RNG
ETM NVIC
HSI 1%
IPCC PLL1 16 MHz
Cortex-M4
MSI up to
(DSP) RCC + CSS 48 MHz
CTI

FPU MPU Power supply POR/


PWR PDR/BOR/PVD/AVD

EXTI
AHB Lite

AES2

DMA1 - 7 channels WWDG


12 KB SRAM1
DMAMUX DBG
GPIO ports Temp (oC) sensor
A, B, C, E, H SPI1
ADC1 12-bit ULP
CRC 2.5 Msps / 13 ch
I2C1
TSC
APB USART1

LPTIM1 TIM1

LPTIM2 TIM2 SYSCFG

MS53573V2

12/112 DS13259 Rev 7


STM32WB10CC Functional overview

3 Functional overview

3.1 Architecture
The STM32WB10CC multiprotocol wireless device embeds a Bluetooth Low Energy RF
subsystem that interfaces with a generic microcontroller subsystem using an Arm® Cortex®-
M4 CPU (called CPU1) on which the host application resides.
The RF subsystem is composed of an RF analog front end, Bluetooth Low Energy block as
well as of a dedicated Arm® Cortex®-M0+ microcontroller (called CPU2), plus proprietary
peripherals. The RF subsystem performs all of the Bluetooth Low Energy stack, reducing
the interaction with the CPU1 to high level exchanges.
Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU
(CPU1):
• Flash memories
• SRAM1, SRAM2a, and SRAM2b (all can be retained in Standby mode)
• Security peripherals (RNG, PKA)
• Clock RCC
• Power control (PWR)
The communication and the sharing of peripherals between the RF subsystem and the
Cortex®-M4 CPU is performed through a dedicated inter processor communication
controller (IPCC) and semaphore mechanism (HSEM).

3.2 Arm® Cortex®-M4 core with FPU


The Arm® Cortex®-M4 with FPU is a processor for embedded systems. It has been
developed to provide a low-cost platform that meets the needs of MCU implementation, with
a reduced pin count and low-power consumption, while delivering outstanding
computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional
code-efficiency, delivering the high-performance expected from an Arm® core in the
memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions enabling efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded Arm® core, the STM32WB10CC is compatible with all Arm® tools and
software.
Figure 1 shows the general block diagram of the device.

DS13259 Rev 7 13/112


43
Functional overview STM32WB10CC

3.3 Memories

3.3.1 Adaptive real-time memory accelerator (ART Accelerator)


The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm®
Cortex®-M4 processors. It balances the inherent performance advantage of the Arm®
Cortex®-M4 over flash memory technologies, which normally require the processor to wait
for the flash memory at higher frequencies.
To release the processor near 80 DMIPS performance at 64 MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from flash memory at a CPU frequency up to 64 MHz.

3.3.2 Memory protection unit


The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to eight protected areas, which can be divided
up into eight subareas. The protection area sizes are between 32 bytes and the whole
4 Gbytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by an RTOS
(real-time operating system). If a program accesses a memory location prohibited by the
MPU, the RTOS detects it and acts. In an RTOS environment, the kernel can dynamically
update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

3.3.3 Embedded flash memory


The STM32WB10CC device features 320 Kbytes of embedded flash memory available for
storing programs and data, as well as some customer keys.
Flexible protections can be configured thanks to option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the flash memory cannot be read from or
written to if either debug features are connected, boot in SRAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex®-M4 and Cortex®-M0+
JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG
fuse). This selection is irreversible.

14/112 DS13259 Rev 7


STM32WB10CC Functional overview

Table 2. Access status vs. readout protection level and execution modes
Debug, boot from SRAM or boot
User execution
Protection from system memory (loader)
Area
level
Read Write Erase Read Write Erase

Main 1 Yes Yes Yes No No No


memory 2 Yes Yes Yes N/A N/A N/A

System 1 Yes No No Yes No No


memory 2 Yes No No N/A N/A N/A

Option 1 Yes Yes Yes Yes Yes Yes


bytes 2 Yes No (1)
No (1)
N/A N/A N/A
(2)
Backup 1 Yes Yes N/A No No N/A(2)
registers 2 Yes Yes N/A N/A N/A N/A
(2)
SRAM2a 1 Yes Yes Yes No No No(2)
SRAM2b 2 Yes Yes Yes N/A N/A N/A
1. The option byte can be modified by the RF subsystem.
2. Erased when RDP changes from Level 1 to Level 0.

• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 4-Kbyte granularity.
• Proprietary code readout protection (PCROP): two parts of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
Two areas can be selected, with 2-Kbyte granularity. An additional option bit
(PCROP_RDP) makes possible to select if the PCROP area is erased or not when the
RDP protection is changed from Level 1 to Level 0.
A section of the flash memory is secured for the RF subsystem CPU2, and cannot be
accessed by the host CPU1.
The whole nonvolatile memory embeds the error correction code (ECC) feature supporting:
• single error detection and correction
• double error detection
• the address of the ECC fail can be read in the ECC register
The embedded flash memory is shared between CPU1 and CPU2 on a time sharing basis.
A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.

3.3.4 Embedded SRAM


The STM32WB10CC device features 48 Kbytes of embedded SRAM, split in three blocks:
• SRAM1: 12 Kbytes mapped at address 0x2000 0000
• SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000,
with hardware parity check
• SRAM2b: 4 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and
mirrored at 0x1000 8000 with hardware parity check

DS13259 Rev 7 15/112


43
Functional overview STM32WB10CC

SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the
SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the
host CPU1.
The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock
speeds.

3.4 Security and safety


The STM32WB10CC contains many security blocks both for the Bluetooth Low Energy and
the Host application.
It includes:
• Secure flash memory partition for RF subsystem-only access
• Secure SRAM partition, that can be accessed only by the RF subsystem
• True random number generator (RNG)
• Advance encryption standard hardware accelerator (AES-256bit, supporting chaining
modes ECB, CBC, CTR, GCM, GMAC, CCM)
• Private key acceleration (PKA) including:
– Modular arithmetic including exponentiation with maximum modulo size of 3136
bits
– Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA
verification with maximum modulo size of 521 bits
• Cyclic redundancy check calculation unit (CRC)
A specific mechanism is in place to ensure that all the code executed by the RF subsystem
CPU2 can be secure, whatever the Host application.

3.5 Boot modes and FW update


At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:
• Boot from user flash
• Boot from system memory
• Boot from embedded SRAM
The device always boots on CPU1 core. The embedded bootloader code makes it possible
to boot from various peripherals:
• UART
• I2C
• SPI
Secure Firmware update from system boot is provided.

3.6 RF subsystem
The STM32WB10CC embeds an ultra-low power multi-standard radio Bluetooth Low
Energy, compliant with Bluetooth specification 5.4. The Bluetooth Low Energy features
1 Mbps transfer rate, supports multiple roles simultaneously acting at the same time as

16/112 DS13259 Rev 7


STM32WB10CC Functional overview

Bluetooth Low Energy sensor and hub device, embeds Elliptic Curve Diffie-Hellman (ECDH)
key agreement protocol, thus ensuring a secure connection.
The Bluetooth Low Energy stack runs on an embedded Arm® Cortex®-M0+ core (CPU2).
The stack is stored on the embedded flash memory, which is also shared with the Arm®
Cortex®-M4 (CPU1) application, making it possible in-field stack update.

3.6.1 RF front-end block diagram


The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF
architecture in Rx mode.
Thanks to an internal transformer at RF pins, the circuit directly interfaces the antenna
(single ended connection, impedance close to 50 Ω). The natural bandpass behavior of the
internal transformer, simplifies outside circuitry aimed for harmonic filtering and out of band
interferer rejection.
In Transmit mode, the maximum output power is user selectable through the programmable
LDO voltage of the power amplifier. A linearized, smoothed analog control offers clean
power ramp-up.
In receive mode the circuit can be used in standard high performance or in reduced power
consumption (user programmable). The Automatic gain control (AGC) is able to reduce the
chain gain at both RF and IF locations, for optimized interference rejection. Thanks to the
use of complex filtering and highly accurate I/Q architecture, high sensitivity and excellent
linearity can be achieved.
The bill of material is reduced thanks to the high degree of integration. The radio frequency
source is synthesized form an external 32 MHz crystal that does not need any external
trimming capacitor network thanks to a dual network of user programmable integrated
capacitors.

DS13259 Rev 7 17/112


43
Functional overview STM32WB10CC

Figure 2. STM32WB10CC RF front-end block diagram

control
AGC
Timer and Power
AGC
control

RF_TX_
MOD_ RF control

ADC
EXT_PA G
Interrupt BLE BP
Wakeup modulator LNA
filter
BLE

ADC
AHB controller
BLE G
APB demodulator
RF1

Modulator

PLL

PA
See
note

generator
PA ramp
Adjust Adjust

HSE
Trimmed
bias

Max PA
LDO LDO LDO
level

VDD VDDRF

OSC_IN OSC_OUT

32 MHz

Note: UFQFPN48: VSS through exposed pad, and VSSRF pin must be connected to ground plane
MS53574V1

3.6.2 Bluetooth Low Energy general description


The Bluetooth Low Energy block is a master/slave processor, compliant with Bluetooth
specification 5.4 standard (1 Mbps).
It integrates a 2.4 GHz RF transceiver and a powerful Cortex®-M0+ core, on which a
complete power-optimized stack for Bluetooth Low Energy protocol runs, providing
master / slave role support
• GAP: central, peripheral, observer or broadcaster roles
• ATT/GATT: client and server
• SM: privacy, authentication and authorization
• L2CAP
• Link layer: AES-128 encryption and decryption

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STM32WB10CC Functional overview

In addition, according to Bluetooth specification 5.4, the Bluetooth Low Energy block
provides:
• Multiple roles simultaneous support
• Master/slave and multiple roles simultaneously
• LE data packet length extension (making it possible to reach 800 kbps at application
level)
• LE privacy 1.2
• LE secure connections
• Flexible Internet connectivity options
The device supports Piconet topology (master with up to eight slaves), Scatternet topology
(master with up to six slaves and dynamically as slave with up to two masters, or master
with up to four slaves and dynamically as slave with up to four masters), and multi slave
topology (slave with up to eight masters).
The device allows the applications to meet the tight peak current requirements imposed by
the use of standard coin cell batteries.
Ultra-low-power sleep modes and very short transition time between operating modes result
in very low average current consumption during real operating conditions, resulting in longer
battery life.
The Bluetooth Low Energy block integrates a full bandpass balun, thus reducing the need
for external components.
The link between the Cortex®-M4 application processor (CPU1) running the application, and
the Bluetooth Low Energy stack running on the dedicated Cortex®-M0+ (CPU2) is
performed through a normalized API, using a dedicated IPCC.

3.6.3 RF pin description


The RF block contains dedicated pins, listed in Table 3.
:

Table 3. RF pin list


Name Type Description

RF1 RF Input/output, must be connected to the antenna through a low-pass matching network
OSC_OUT
32 MHz main oscillator, also used as HSE source
OSC_IN I/O

RF_TX_
External PA transmit control
MOD_EXT_PA
VDDRF VDD Dedicated supply, must be connected to VDD
(1)
VSSRF VSS To be connected to GND
1. The exposed pad must be connected to GND plane for correct RF operation.

3.6.4 Typical RF application schematic


The schematic in Figure 3 and the external components listed in Table 3 are purely
indicative. For more details refer to the “Reference design” provided in separate documents.

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43
Functional overview STM32WB10CC

Figure 3. External components for the RF part

OSC_IN
X1 32 MHz
OSC_OUT
VDD
VDDRF

C1
STM32WB VSSRF
Antenna

microcontroller (including exposed pad)

Lf1
Cf1 Cf2

RF1
Antenna
Lf2 filter

MS53575V1

Table 4. Typical external components


Component Description Value

C1 Decoupling capacitance for RF 100 nF // 100 pF


X1 32 MHz crystal(1) 32 MHz
Antenna filter Antenna filter and matching network Refer to AN5165, on www.st.com
Antenna 2.4 GHz band antenna -
1. e.g. NDK reference: NX2016SA 32 MHz EXS00A-CS06654.

Note: For more details refer to AN5165 “Development of RF hardware using STM32WB
microcontrollers” available on www.st.com.

3.7 Power supply management

3.7.1 Power supply schemes


The device has different voltage supplies (see Figure 5) and can operate within the following
voltage ranges:
• VDD = 2.0 to 3.6 V: external power supply for I/Os (VDDIO), the internal regulator and
system functions such as RF, reset, power management and internal clocks. It is
provided externally through VDD pins. VDDRF must be always connected to VDD pins.
• VDDA = 2.0 to 3.6 V: external analog power supply for ADC. The VDDA voltage level can
be independent from the VDD voltage. When not used VDDA must be connected to VDD.

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STM32WB10CC Functional overview

During power up/down, the following power sequence requirements must be respected:
• When VDD is below 1 V the other power supply (VDDA), must remain below
VDD + 300 mV
• When VDD is above 1 V all power supplies are independent.

Figure 4. Power-up/down sequence


V

3.6
VDDX(1)

VDD

VBOR0

0.3

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1

1. VDDX refers to VDDA.

During the power down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling
capacitors to be discharged with different time constants during the power down transient
phase.
Note: VDD and VDDRF must be wired together, so they can follow the same voltage sequence.

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43
Functional overview STM32WB10CC

Figure 5. Power supply overview

Interruptible domain (VDD12I) On domain (VDD12O)

Level shifter
SysConfig, EXTI,
IO (CPU1, CPU2, RCC, PwrCtrl,
IOs peripherals)
logic LPTIM, USART1
Power Power
switch switch

VSS
VSS VSS
VDD MR

RFR

LPR
VDDRF
RF domain Backup domain
SRAM1,
Radio VBKP12
SRAM2a,
SRAM2b
Power switch
VSSRF
VSS
VSS
(including exposed pad)
Wakeup domain (VDDIO)
VDD HSI, HSE,
Power switch PLL,
VSW LSI1, LSI2,
VBAT IWDG, RF
VSS

Switch domain (VSW)


VBAT IO LSE, RTC,
IOs logic backup registers
VSS
VSS
VDDA Analog domain

ADC
=
VREF+ =
VREF-
VSS

MS53576V2

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STM32WB10CC Functional overview

3.7.2 Linear voltage regulator


Three embedded linear voltage regulators supply most of the digital and RF circuitries, the
main regulator (MR), the low-power regulator (LPR) and the RF regulator (RFR).
• The MR is used in the Run and Sleep modes and in the Stop 0 mode.
• The LPR is used in Low-Power Run, Low-Power Sleep and Stop 1 modes. It is also
used to supply the SRAMs in Standby with retention.
• The RFR is used to supply the RF analog part, its activity is automatically managed by
the RF subsystem.
All the regulators are in power-down in Standby and Shutdown modes: the regulator output
is in high impedance, and the kernel circuitry is powered down, inducing zero consumption.
The ultralow-power STM32WB10CC supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the main regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
VCORE can also be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode. In this case the CPU is running at up to
2 MHz, and peripherals with independent clock can be clocked by HSI16 (in this mode the
RF subsystem is not available).

3.7.3 Power supply supervisor


An integrated ultra-low-power brown-out reset (BOR) is active in all modes except
Shutdown ensuring proper operation after power-on and during power down. The device
remains in reset mode when the monitored supply voltage VDD is below a specified
threshold, without the need for an external reset circuit.
The lowest BOR level is 2.0 V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it with the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.

3.7.4 Low-power modes


This ultra-low-power device supports several low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wake-up sources.
By default, the microcontroller is in Run mode, after a system or a power on reset. It is up to
the user to select one of the low-power modes described below:
• Sleep
In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem,
continue to operate and can wake up the CPU when an interrupt/event occurs.
• Low-power run
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator operating current. The code can be executed from SRAM or from the
flash memory, and the CPU1 frequency is limited to 2 MHz. The peripherals with
independent clock can be clocked by HSI16. The RF subsystem is not available in this

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43
Functional overview STM32WB10CC

mode and must be OFF.


• Low-power sleep
This mode is entered from the low-power run mode. Only the CPU1 clock is stopped.
When wake-up is triggered by an event or an interrupt, the system reverts to the
low-power run mode. The RF subsystem is not available in this mode and must be
OFF.
• Stop 0 and Stop 1
Stop modes achieve the lowest power consumption while retaining the content of all
the SRAM and registers. The LSE (or LSI) is still running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wake-up capability can enable the HSI16 RC during Stop modes
to detect their wake-up condition.
Two modes are available: Stop 0 and Stop 1.
Stop 1 offers several active peripherals and wake-up sources. In Stop 0 mode the main
regulator remains ON, allowing a very fast wake-up time but with higher consumption.
In these modes the RF subsystem can wait for incoming events in all Stop modes.
The system clock when exiting from Stop 0 Stop1 modes can be either MSI up to
48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem is used the exits
must be set to HSI16 only.
• Standby
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off.
The RTC can remain active (Standby mode with RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, register content is lost except for registers in the Backup
domain and Standby circuitry. Optionally, SRAMs can be retained in Standby mode,
supplied by the low-power regulator (Standby with 48 KB SRAM retention mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wake-up, timestamp, tamper) or a failure is detected on LSE (CSS on LSE).
The system clock after wake-up is 16 MHz, derived from the HSI16. This low power
mode is not selectable for Radio activity.

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STM32WB10CC Functional overview

• Shutdown
This mode achieves the lowest power consumption. The internal regulator is switched
off so that the VCORE domain is powered off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the
Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wake-up, timestamp, tamper).
The system clock after wake-up is 4 MHz, derived from the MSI.
This low-power mode is not selectable for Radio activity.
When the RF subsystem is active, it changes the power state according to its needs (Run,
Stop, Standby). This operation is transparent for the CPU1 host application and managed by
a dedicated HW state machine. At any given time the effective power state reached is the
higher one needed by both the CPU1 and RF sub-system.
Table 5 summarizes the peripheral features over all available modes. Wake-up capability is
detailed in gray cells.

Table 5. Functionalities depending on system operating mode(1)


Stop0 Stop1 Standby Shutdow
Low-power sleep
Low-power run

Wake-up capability

Wake-up capability

Wake-up capability

Wake-up capability
Sleep

VBAT
Run

Peripheral
- - - -

CPU1 Y - Y - - - - - - - - - -
CPU2 Y - Y - - - - - - - - - -
Radio-system (BLE) Y Y - - Y Y Y Y Y(2) Y(2) - - -
Flash memory Y Y O O R - R - R - R - R
SRAM1 Y O(3) Y O(3) R - R - O(3) - - - -
SRAM2a Y O(3) Y O(3) R - R - O(3) - - - -
(3) (3) (3)
SRAM2b Y O Y O R - R - O - - - -
Backup registers Y Y Y Y R - R - R - R - R
Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - -
Programmable voltage detector
O O O O O O O O - - - - -
(PVD)
DMAx (x=1) O O O O - - - - - - - - -
High speed internal (HSI16) O O O O O(4) - O(4) - - - - - -
High speed external (HSE) O O O O - - - - - - - - -

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43
Functional overview STM32WB10CC

Table 5. Functionalities depending on system operating mode(1) (continued)


Stop0 Stop1 Standby Shutdow

Low-power sleep
Low-power run

Wake-up capability

Wake-up capability

Wake-up capability

Wake-up capability
Sleep

VBAT
Run
Peripheral
- - - -

Low speed internal (LSI) O O O O O - O - O - - - -


Low speed external (LSE) O O O O O - O - O - O - O
Multi-speed internal (MSI) O O O O - - - - - - - - -
Clock security system (CSS) O O O O - - - - - - - - -
Clock security system on LSE O O O O O O O O O O - - -
RTC / Auto wake-up O O O O O O O O O O O O O
Number of RTC tamper pins 1 1 1 1 1 O 1 O 1 O 1 O 1
(5) O(5) O(5) O(5)
USART1 O O O O O - - - - -
I2C1 O O O O O(6) O(6) O(6) O(6) - - - - -
SPIx (x=1) O O O O - - - - - - - - -
ADC1 O O O O - - - - - - - - -
Temperature sensor O O O O - - - - - - - - -
Timers (TIMx) O O O O - - - - - - - - -
Low-power timer 1 (LPTIM1) O O O O O O O O - - - - -
Low-power timer 2 (LPTIM2) O O O O O O O O - - - - -
Independent watchdog (IWDG) O O O O O O O O O O - - -
Window watchdog (WWDG) O O O O - - - - - - - - -
SysTick timer O O O O - - - - - - - - -
Touch sensing controller (TSC) O O O O - - - - - - - - -
True random number generator
O O - - - - - - - - - - -
(RNG)
AES hardware accelerator O O O O - - - - - - - - -
CRC calculation unit O O O O - - - - - - - - -
IPCC O - O - - - - - - - - - -
HSEM O - O - - - - - - - - - -
PKA O O O O - - - - - - - - -
2 2
(7) (9)
GPIOs O O O O O O O O pins pins -
(8) (9)

1. Legend: Y = Yes (enabled). O = Optional (disabled by default, can be enabled by software).


R = data retained. - = Not available. Gray cells indicate wake-up capability.
2. Standby with SRAM retention mode only.

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STM32WB10CC Functional overview

3. The SRAM clock can be gated on or off.


4. Some peripherals with wake-up from Stop capability can request HSI16 to be enabled. In this case, HSI16
is woken up by the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put
off when the peripheral does not need it anymore.
5. UART reception is functional in Stop mode, and generates a wake-up interrupt on Start, address match or
received frame event.
6. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address
match.
7. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
8. The I/Os with wake-up from Standby/Shutdown capability are PA0 and PA2.
9. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is
lost when exiting the Shutdown mode.

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Functional overview
Table 6. STM32WB10CC modes overview
Mode Regulator CPU1 Flash SRAM Clocks DMA and Peripherals Wake-up source Consumption(1) Wake-up time

Run MR Yes ON(2) ON Any All N/A 91 µA/MHz N/A


Any
LPRun LPR Yes ON(2) ON except All except RF and RNG N/A 90 µA/MHz 15.33 µs
PLL
Any interrupt
Sleep MR No ON(2) ON(3) Any All 28 µA/MHz 9 cycles
or event
Any
Any interrupt
LPSleep LPR No ON(2) ON(3) except All except RF and RNG 27 µA/MHz 9 cycles
or event
PLL
RF, BOR, PVD, RTC, IWDG, Reset pin, all I/Os, RF,
LSE, LSI, USART1(6), I2C1(7), BOR, PVD, RTC,
Stop 0 MR No OFF ON HSE(4), LPTIMx (x=1, 2) 100 µA 1.7 µs
IWDG, USART1, I2C1,
HSI16(5)
DS13259 Rev 7

All other peripherals are frozen. LPTIMx (x=1, 2)


RF, BOR, PVD, RTC, IWDG, Reset pin, all I/Os
LSE, LSI, USART1(6), I2C1(7), RF, BOR, PVD, RTC, 3.05 µA w/o RTC
Stop 1 LPR No OFF ON HSE(4), LPTIMx (x=1, 2) 4.7 µs
HSI16(5) IWDG, USART1, I2C1, 3.45 µA w RTC
All other peripherals are frozen. LPTIMx (x=1, 2)

SRAMs BOR, RTC, IWDG 0.345 µA w/o RTC


LPR
ON All other peripherals are Reset pin, two I/Os 0.70 µA w RTC
Standby No OFF LSE, LSI powered off. (WKUPx)(8) 51 µs
BOR, RTC, IWDG 0.245 µA w/o RTC
OFF OFF I/O configuration can be floating,
pull-up or pull-down 0.600 µA w RTC

RTC
All other peripherals are
Two I/Os (WKUPx)(8), 0.018 µA w/o RTC
Shutdown OFF No OFF OFF LSE powered off. -
RTC 0.425 µA w/ RTC
I/O configuration can be floating,
pull-up or pull-down(9)

STM32WB10CC
1. Typical current at VDD = 2.4 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C.
2. The flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM.
3. The SRAM1 and SRAM2 clocks can be gated off independently.
4. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem.
STM32WB10CC
5. HSI16 (16 MHz) automatically used by some peripherals.
6. U(S)ART reception is functional in Stop mode, and generates a wake-up interrupt on Start, Address match or Received frame event.
7. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address match.
8. I/Os with wake-up from Standby/Shutdown capability: PA0, PA2.
9. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.
DS13259 Rev 7

Functional overview
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Functional overview STM32WB10CC

3.7.5 Reset mode


To improve the consumption under reset, the I/Os state under and after reset is “analog
state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.

3.8 VBAT operation


The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers)
from an external battery, an external supercapacitor, or from VDD when no external battery
nor an external supercapacitor are present. One anti-tamper detection pin is available in
VBAT mode.
VBAT operation is automatically activated when VDD is not present.
An internal VBAT battery charging circuit is embedded and can be activated when VDD is
present.
Note: When the microcontroller is supplied only from VBAT, external interrupts and RTC
alarm/events do not exit it from VBAT operation.

3.9 Interconnect matrix


Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU1 resources and, consequently, reducing
power supply consumption. In addition, these hardware connections result in fast and
predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run and Sleep, Stop 0 and Stop 1 modes.

Table 7. STM32WB10CC CPU1 peripherals interconnect matrix


Low-power run

Stop 0 / Stop 1
Low-power
Sleep
Run

Source Destination Action

TIMx Timers synchronization or chaining Y Y Y Y -

TIMx ADC1 Conversion triggers Y Y Y Y -


DMA Memory to memory transfer trigger Y Y Y Y -
ADC1 TIM1 Timer triggered by analog watchdog Y Y Y Y -
Low-power timer triggered by RTC
RTC LPTIMERx Y Y Y Y Y
alarms or tampers

All clock sources Clock source used as input channel for


TIM2 Y Y Y Y -
(internal and external) RC measurement and trimming

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STM32WB10CC Functional overview

Table 7. STM32WB10CC CPU1 peripherals interconnect matrix (continued)

Low-power run

Stop 0 / Stop 1
Low-power
Sleep
Run
Source Destination Action

CSS
CPU (hard fault)
SRAM (parity error) TIM1 Timer break Y Y Y Y -
Flash memory (ECC error)
PVD

TIMx External trigger Y Y Y Y -


GPIO LPTIMERx External trigger Y Y Y Y Y
ADC1 Conversion external trigger Y Y Y Y -

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Functional overview STM32WB10CC

3.10 Clocks and startup


The STM32WB10CC device integrates several clock sources:
• LSE: 32.768 kHz external oscillator, for accurate RTC and calibration with other
embedded RC oscillators
• LSI1: 32 kHz on-chip low-consumption RC oscillator
• LSI2: 32 kHz (untrimmable), on-chip temperature stable RC oscillator, can be used by
the RF subsystem instead of LSE
• HSE: high quality 32 MHz external oscillator with trimming, needed by the RF
subsystem
• HSI16: 16 MHz high accuracy on-chip RC oscillator
• MSI: 100 kHz to 48 MHz multiple speed on-chip low power oscillator, can be trimmed
using the LSE signal
The clock controller (see Figure 6) distributes the clocks coming from the different
oscillators to the core and the peripherals including the RF subsystem. It also manages
clock gating for low power modes and ensures clock robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.
– System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency of
64 MHz.
• Auxiliary clock source: two ultralow-power clock sources that can be used to drive
the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI1), also used to drive the independent
watchdog. The LSI1 clock accuracy is ±5%.
– 32 kHz low-speed internal RC (LSI2), with ±200 ppm / °C stability over
temperature.
• Peripheral clock sources: Several peripherals (RNG, USARTs, I2C, LPTimers, ADC)
have their own independent clock whatever the system clock. A PLL having three
independent outputs for the highest flexibility can generate independent clocks for the
ADC and the RNG.
• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application

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STM32WB10CC Functional overview

program as soon as the code execution starts.


• Clock security system (CSS): this feature can be enabled by software. If an HSE
clock failure occurs, the master clock is automatically switched to HSI16 and a software
interrupt is generated if enabled. LSE failure can also be detected and an interrupt
generated.
• Clock-out capability:
– MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application. Low frequency clocks (LSIx, LSE) are available
down to Stop 1 low power state.
– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
down to Standby.
Several prescalers allow the user to configure the AHB frequencies, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 64 MHz.

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43
Functional overview STM32WB10CC

Figure 6. Clock tree


LSI1 RC 32 kHz to IWDG
LSI

LSI2 RC 32 kHz LSI


LSCO
LSE to RTC

OSC32_OUT LSE OSC


32.768 kHz LSE
OSC32_IN
to BLE wake-up
LSE CSS LSI
LSI1
/32
CPU1 to CPU1, AHB1, AHB2 and SRAM1
LSI2 HCLK1
HPRE
LSE /32 /1,2,...,512 to CPU1 FCLK

HSE to CPU1 system timer


/8
MCO SYSCLK
/1 - 16
APB1 PCLK1 to APB1
PLLRCLK
PPRE1
HSI16 SYS clock /1,2,4,8,16 x1 or to APB1 TIMx
source control x2
MSI
PLLRCLK APB2 PCLK2 to APB2
HSI PPRE2
OSC_OUT HSE OSC SYSCLK /1,2,4,8,16 x1 or to APB2 TIMx
32 MHz HSE x2
OSC_IN
HSE PRE PRE CPU2 to CPU2
HSE CSS HCLK2
/1,2 C2HPRE
MSI 1,2,...,512 to CPU2 FCLK
HSI16 RC
16 MHz to CPU2 system timer
/8
MSI RC AHBS
100 kHz - 48 MHz HCLK4 to AHB4, Flash memory and SRAM2
SHDHPRE
/1,2,...,512
to APB3
MSI HSI
HCLK5 to AHB5
HSI16 HSE
/M /2
to RF
HSEPRE

PLL MSI
PLLPCLK
xN /P
/3 PCLKn
PLLQCLK SYSCLK
/Q to RNG to USART1
LSI
HSI16
PLLRCLK LSE
/R
LSE

PCLKn

PLLPCLK PCLKn HSI16 to LPTIMx


to ADC to I2C1
HSI SYSCLK LSI

SYSCLK HSI16 LSE

MS53563V3

3.11 General-purpose inputs/outputs (GPIOs)


Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked, if needed, following a specific
sequence in order to avoid spurious writing to the I/Os registers.

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STM32WB10CC Functional overview

3.12 Direct memory access controller (DMA)


The device embeds one DMA. Refer to Table 8 for the features implementation.
Direct memory access (DMA) is used to provide high-speed data transfer between
peripherals and memory as well as between memories. Data can be quickly moved by DMA
without any CPU action. This keeps CPU resources free for other operations.
The DMA controller has seven channels in total, a full cross matrix allows any peripheral to
be mapped on any of the available DMA channels. The DMA has an arbiter for handling the
priority between DMA requests.
The DMA supports:
• seven independently configurable channels (requests)
• A full cross matrix between peripherals and all the DMA channels exist. There is also a
HW trigger possibility through the DMAMUX.
• Priorities between requests from DMA channels are software programmable (four
levels consisting in very high, high, medium and low) or hardware in case of equality
(request 1 has priority over request 2, etc.).
• Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
• Support for circular buffer management.
• Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically OR-ed together in a single interrupt request for each channel.
• Memory-to-memory transfer.
• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers.
• Access to flash memory, SRAM, APB and AHB peripherals as source and destination.
• Programmable number of data to be transferred: up to 65536.

Table 8. DMA implementation


DMA features DMA1
Number of regular channels 7

A DMAMUX block makes it possible to route any peripheral source to any DMA channel.

3.13 Interrupts and events

3.13.1 Nested vectored interrupt controller (NVIC)


The device embeds a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 63 maskable interrupt channels plus the 16 interrupt lines of the
Cortex®-M4 with FPU.

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43
Functional overview STM32WB10CC

The NVIC benefits are the following:


• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.

3.13.2 Extended interrupts and events controller (EXTI)


The EXTI manages wake-up through configurable and direct event inputs. It provides
wake-up requests to the Power control, and generates interrupt requests to the CPUx NVIC
and events to the CPUx event input.
Configurable events/interrupts come from peripherals able to generate a pulse, and make it
possible to select the Event/Interrupt trigger edge and/or a SW trigger.
Direct events/interrupts are coming from peripherals having their own clearing mechanism.

3.14 Analog to digital converter (ADC)


The 12-bit analog-to-digital converter has up to ten external and three internal (temperature
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
An analog watchdog feature makes possible a very precise monitoring of the converted
voltage of one, some or all selected channels. An interrupt is generated when the converted
voltage is outside the programmed thresholds.

3.14.1 Temperature sensor


The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN12 input channel, which is
used to convert the sensor output voltage into a digital value.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored in the system memory area, accessible in read-only mode.

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STM32WB10CC Functional overview

Table 9. Temperature sensor calibration values


Calibration value name Description Memory address

TS ADC raw data acquired at a


TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF 75A8 - 0x1FFF 75A9
VDDA = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 130 °C (± 5 °C), 0x1FFF 75CA - 0x1FFF 75CB
VDDA = 3.0 V (± 10 mV)

3.14.2 Internal voltage reference (VREFINT)


The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC. VREFINT is internally connected to the ADC1_IN13 input channel. The precise
voltage of VREFINT is individually measured for each part by ST during production test and
stored in the system memory area. It is accessible in read-only mode.

Table 10. Internal voltage reference calibration values


Calibration value name Description Memory address

Raw data acquired at a


VREFINT temperature of 30 °C (± 5 °C), 0x1FFF 75AA - 0x1FFF 75AB
VDDA = 3.6 V (± 10 mV)

3.15 Touch sensing controller (TSC)


The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode which is protected from direct touch by a dielectric such as
glass or plastic. The capacitive variation introduced by the finger (or any conductive object)
is measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library (free to use) and enables reliable touch sensing functionality in the end application.

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43
Functional overview STM32WB10CC

The main features of the touch sensing controller are the following:
• Proven and robust surface charge transfer acquisition principle
• Supports up to three capacitive sensing channels
• Up to three capacitive sensing channels can be acquired in parallel offering a very
good response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to three capacitive sensing channels to reduce the
system components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library

3.16 True random number generator (RNG)


The device embeds a true RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.

3.17 Timers and watchdogs


The STM32WB10CC includes one advanced 16-bit timer, one general-purpose 32-bit timer,
two low-power timers, two watchdog timers and a SysTick timer. Table 11 compares the
features of the advanced control, general purpose and low power timers.

Table 11. Timer features


DMA Capture/
Timer Counter Counter Prescaler Complementary
Timer request compare
type resolution type factor outputs
generation channels

Advanced Up, down,


TIM1 16-bits 4 3
control Up/down
Any integer
General Up, down,
TIM2 32-bits between 1 Yes 4 No
purpose Up/down
and 65536
LPTIM1
Low power 16-bits Up 1 1
LPTIM2

3.17.1 Advanced-control timer (TIM1)


The advanced-control timer can be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted

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STM32WB10CC Functional overview

dead-times. They can also be seen as complete general-purpose timers. The four
independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0 to
100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.17.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.

3.17.2 General-purpose timer (TIM2)


There is one synchronizable general-purpose timer embedded in the STM32WB10CC (see
Table 11), it can be used to generate PWM outputs, or act as a simple time base.
• TIM2
– Full-featured general-purpose timer
– Features four independent channels for input capture/output compare, PWM or
one-pulse mode output. Can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
– The counter can be frozen in debug mode.
– Independent DMA request generation, support of quadrature encoders.

3.17.3 Low-power timer (LPTIM1 and LPTIM2)


The device embeds two low-power timers, having an independent clock running in Stop
mode if they are clocked by LSE, LSIx or by an external clock. They are able to wake-up the
system from Stop mode.
LPTIM1 is active in Stop 0 and Stop 1 modes.
LPTIM2 is active in Stop 0 and Stop 1 modes.
The low-power timers support the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/ one shot mode
• Selectable software/hardware input trigger
• Selectable clock source
– Internal clock sources: LSE, either LSI1 or LSI2, HSI16 or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application)
• Programmable digital glitch filter
• Encoder mode (LPTIM1 only)

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Functional overview STM32WB10CC

3.17.4 Independent watchdog (IWDG)


The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.

3.17.5 System window watchdog (WWDG)


The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

3.17.6 SysTick timer


This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
• a 24-bit down counter
• autoreload capability
• a maskable system interrupt generation when the counter reaches 0
• a programmable clock source.

3.18 Real-time clock (RTC) and backup registers


The RTC is an independent BCD timer/counter, supporting the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• One anti-tamper detection pin with programmable filter.
• Timestamp feature, which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 20 backup registers are supplied through a switch that takes power either
from the VDD supply (when present) or from the VBAT pin.

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STM32WB10CC Functional overview

The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
• a 32.768 kHz external crystal (LSE)
• an external resonator or oscillator (LSE)
• one of the internal low power RC oscillators (LSI1 with typical frequency of 32 kHz or
LSI2)
• the high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by one of the LSIs, the RTC is not functional in VBAT mode, but is
functional in all low-power modes except Shutdown mode.
All RTC events (alarm, wake-up timer, timestamp or tamper) can generate an interrupt and
wake-up the device from the low-power modes.

3.19 Inter-integrated circuit interface (I2C)


The device embeds one I2C. Refer to Table 12 for the features implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBus™) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 6: Clock tree.
• Wake-up from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

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43
Functional overview STM32WB10CC

Table 12. I2C implementation


I2C features(1) I2C1

Standard-mode (up to 100 kbit/s) X


Fast-mode (up to 400 kbit/s) X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X
Programmable analog and digital noise filters X
SMBus/PMBus hardware support X
Independent clock X
Wake-up from Stop 0 / Stop 1 mode on address match X
1. X: supported.

3.20 Universal synchronous/asynchronous receiver transmitter


(USART)
The device embeds one universal synchronous receiver transmitter.
This interface provides asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and has
LIN master/slave capability. It provides hardware management of the CTS and RTS signals,
and RS485 driver enable.
The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart
Card mode (ISO 7816 compliant) and SPI-like communication capability.
The USART supports synchronous operation (SPI mode), and can be used as an SPI
master.
The USART has a clock domain independent from the CPU clock, allowing it to wake up the
MCU from Stop mode using baudrates up to 200 kbaud. The wake up events from Stop
mode are programmable and can be:
• the start bit detection
• any received data frame
• a specific programmed data frame.
The USART interface can be served by the DMA controller.

3.21 Serial peripheral interface (SPI1)


The SPI interface enable communication up to 32 Mbit/s in master and up to 24 Mbit/s in
slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8
master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI
interface support NSS pulse mode, TI mode and Hardware CRC calculation.
The SPI interface can be served by the DMA controller.

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STM32WB10CC Functional overview

3.22 Development support

3.22.1 Serial wire JTAG debug port (SWJ-DP)


The embedded Arm® SWJ-DP interface is a combined JTAG and serial wire debug port that
enables either a serial wire debug, or a JTAG probe to be connected to the target.
Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins
can then be reused as GPIOs with alternate function): the JTAG TMS and TCK pins are
shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is
used to switch between JTAG-DP and SW-DP.

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43
Pinouts and pin description STM32WB10CC

4 Pinouts and pin description

Figure 7. STM32WB10CCU UFQFPN48 pinout (1) (2)

PA15
PA14

PA13
PA12
PA11
VDD

VDD
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 PA10
PC14-OSC32_IN 2 35 VDD
PC15-OSC32_OUT 3 34 VDD
PH3-BOOT0 4 33 VDD
PB8 5 32 VSS
PB9 6 31 VDD
NRST 7
UFQFPN48 30 PE4
VDDA 8 29 PB1
PA0 9 28 PB0
PA1 10 27 AT1
PA2 11 26 AT0
PA3 12 25 OSC_IN
13
14
15
16
17
18
19
20
21
22
23
24
PB2
VDD
RF1
VSSRF
VDDRF
OSC_OUT
PA4
PA5
PA6
PA7
PA8
PA9

MS53577V1

1. The above figure shows the package top view.


2. The exposed pad must be connected to ground plane.

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STM32WB10CC Pinouts and pin description

Table 13. Legend/abbreviations used in the pinout table


Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name

S Supply pin

Pin type I Input only pin

I/O Input / output pin

FT 5 V tolerant I/O

TT 3.6 V tolerant I/O

RF RF I/O

I/O structure NRST Bidirectional reset pin with weak pull-up resistor

Option for TT or FT I/Os

_f (1) I/O, Fm+ capable

_a(2) (3) I/O, with analog switch function supplied by VDDA

Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.

Alternate
Functions selected through GPIOx_AFR registers
Pin functions
function Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 14 are FT_f and FT_fa.
2. The related I/O structures in Table 14 are FT_a, FT_la, FT_fa and TT_a.
3. The analog switch for the TSC function is supplied by VDD.

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Pinouts and pin description STM32WB10CC

Table 14. STM32WB10CC pin definitions


Pin

structure

Notes
Additional
Number

I/O
Alternate functions
Name (function functions

Type
after reset)

1 VBAT S - - - -
(1)
2 PC14-OSC32_IN I/O FT CM4_EVENTOUT OSC32_IN
(1)
3 PC15-OSC32_OUT I/O FT CM4_EVENTOUT OSC32_OUT
4 PH3-BOOT0 I/O FT - LSCO(2) , CM4_EVENTOUT -
TIM1_CH2N, I2C1_SCL, TSC_G7_IO3,
5 PB8 I/O FT_f - -
CM4_EVENTOUT
TIM1_CH3N, I2C1_SDA, TSC_G7_IO4,
6 PB9 I/O FT_f - -
CM4_EVENTOUT
7 NRST(PB11) I/O NRST (3) - -
8 VDDA S - - - -
ADC1_IN5,
9 PA0 I/O FT_a - TIM2_CH1, TIM2_ETR, CM4_EVENTOUT
RTC_TAMP2/WKUP1
TIM2_CH2, I2C1_SMBA, SPI1_SCK,
10 PA1 I/O FT_a - ADC1_IN6
CM4_EVENTOUT
11 PA2 I/O FT_a - LSCO(2), TIM2_CH3, CM4_EVENTOUT ADC1_IN7, WKUP4
12 PA3 I/O FT_a - TIM2_CH4, CM4_EVENTOUT ADC1_IN8
SPI1_NSS (boot), LPTIM2_OUT,
13 PA4 I/O FT_a - ADC1_IN9
CM4_EVENTOUT
TIM2_CH1, TIM2_ETR, SPI1_MOSI,
14 PA5 I/O FT_a - SPI1_SCK (boot), LPTIM2_ETR, ADC1_IN10
CM4_EVENTOUT
TIM1_BKIN, SPI1_MISO (boot),
15 PA6 I/O FT_a - ADC1_IN11
CM4_EVENTOUT
TIM1_CH1N, SPI1_MOSI (boot),
16 PA7 I/O FT_fa - ADC1_IN2
CM4_EVENTOUT
MCO, TIM1_CH1, USART1_CK, LPTIM2_OUT,
17 PA8 I/O FT_a - ADC1_IN3
CM4_EVENTOUT
TIM1_CH2, I2C1_SCL, USART1_TX (boot),
18 PA9 I/O FT_fa - ADC1_IN4
CM4_EVENTOUT
RTC_OUT, LPTIM1_OUT, SPI1_NSS,
19 PB2 I/O FT_a - -
CM4_EVENTOUT
20 VDD S - - - -
(4)
21 RF1 I/O RF - - -
22 VSSRF S - - - -
23 VDDRF S - - - -
(5)
24 OSC_OUT O RF - -

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STM32WB10CC Pinouts and pin description

Table 14. STM32WB10CC pin definitions (continued)


Pin

structure

Notes
Additional
Number

I/O
Alternate functions
Name (function functions

Type
after reset)

25 OSC_IN I RF - - -
26 AT0 I/O RF (6)
- -
(6)
27 AT1 I/O RF - -
(7)
28 PB0 I/O TT RF_TX_MOD_EXT_PA, CM4_EVENTOUT -
29 PB1 I/O TT (7)
LPTIM2_IN1, CM4_EVENTOUT -
30 PE4 I/O FT - CM4_EVENTOUT -
31 VDD S - - - -
32 VSS S - - - -
33 VDD S - - - -
34 VDD S - - - -
35 VDD S - - - -
TIM1_CH3, I2C1_SDA, USART1_RX (boot),
36 PA10 I/O FT_f - -
TSC_G7_IO2, CM4_EVENTOUT
TIM1_CH4, TIM1_BKIN2, SPI1_MISO,
37 PA11 I/O FT - -
USART1_CTS, CM4_EVENTOUT
TIM1_ETR, SPI1_MOSI, USART1_RTS,
38 PA12 I/O FT - -
CM4_EVENTOUT
JTMS-SWDIO, SPI1_MOSI, TSC_G7_IO1,
39 PA13 I/O FT - -
CM4_EVENTOUT
40 VDD S - - - -

(8) JTCK-SWCLK, LPTIM1_OUT, I2C1_SMBA,


41 PA14 I/O FT -
SPI1_NSS, CM4_EVENTOUT

(8) JTDI, TIM2_CH1, TIM2_ETR, SPI1_NSS,


42 PA15 I/O FT -
MCO, TSC_G3_IO1, CM4_EVENTOUT
JTDO-TRACESWO, TIM2_CH2, SPI1_SCK,
43 PB3 I/O FT - -
USART1_RTS, CM4_EVENTOUT
NJTRST, SPI1_MISO, USART1_CTS,
44 PB4 I/O FT_f - -
TSC_G2_IO1, CM4_EVENTOUT
LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI,
45 PB5(9) I/O FT - -
USART1_CK, TSC_G2_IO2, CM4_EVENTOUT
MCO, LPTIM1_ETR, I2C1_SCL (boot),
46 PB6 I/O FT_f - SPI1_NSS, USART1_TX, TSC_G2_IO3, -
CM4_EVENTOUT
LPTIM1_IN2, TIM1_BKIN, I2C1_SDA (boot),
47 PB7 I/O FT_f - USART1_RX, TSC_G2_IO4, TIM1_CH3, PVD_IN
CM4_EVENTOUT
48 VDD S - - - -

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51
Pinouts and pin description STM32WB10CC

1. PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited current (3 mA), the use of PC14
and PC15 GPIOs in output mode is limited:
- the speed must not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as current sources (e.g. to drive an LED).
After a Backup domain power-up PC14 and PC15 operate as GPIOs. Their function depends on the content of the RTC
registers not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC
register description in RM0478, available on www.st.com.
2. The clock on LSCO is available in Run and Stop modes, and on PA2 in Standby and Shutdown modes.
3. NRST pin is FT-tolerant if configured as PB11 GPIO.
4. RF pin, use the nominal PCB layout.
5. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165 available on www.st.com).
6. Reserved for production, must be kept unconnected.
7. High frequency (above 32 kHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0
and 1) during RF operation.
8. After reset this pin is configured as JTAG/SW debug alternate function, and the internal pull-up on PA15, PA13 and PB4
pins and the internal pull-down on PA14 pin are activated.
9. PB5 pin is configured as input with pull-up active under reset if NRST pin is active (external or internal reset).

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STM32WB10CC
Table 15. Alternate functions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF9 AF12 AF14 AF15
Port
LPTIM1/ I2C1/ RF/ LPTIM2/
SYS_AF TIM1/2 TIM1 SPI1 USART1 TSC TIM1 EVENTOUT
TIM1/2 SPI1 SYS_AF TIM2

TIM2_ TIM2_ CM4_


PA0 -
CH1
- - - - - - - -
ETR EVENTOUT

TIM2_ I2C1_ CM4_


PA1 -
CH2
- -
SMBA
SPI1_SCK - - - - -
EVENTOUT

TIM2_ CM4_
PA2 LSCO
CH3
- - - - - - - - -
EVENTOUT

TIM2_ CM4_
PA3 -
CH4
- - - - - - - - -
EVENTOUT

LPTIM2_ CM4_
PA4 - - - - SPI1_NSS - - - -
OUT EVENTOUT

TIM2_ TIM2_ LPTIM2_ CM4_


PA5 -
CH1 ETR
- SPI1_MOSI SPI1_SCK - - - -
ETR EVENTOUT
DS13259 Rev 7

TIM1_ CM4_
PA6 -
BKIN
- - SPI1_MISO - - - - -
EVENTOUT

TIM1_ CM4_
PA7 -
CH1N
- - - SPI1_MOSI - - - - -
EVENTOUT
A
TIM1_ USART1_ LPTIM2_ CM4_
PA8 MCO
CH1
- - - - -
CK
- -
OUT EVENTOUT

TIM1_ I2C1_ USART1_ CM4_


PA9 -
CH2
- -
SCL
- -
TX
- - -
EVENTOUT

TIM1_ I2C1_ USART1_ TSC_ CM4_


PA10 -
CH3
- -
SDA
- -
RX G7_IO2
- -
EVENTOUT

TIM1_ TIM1_ USART1_ CM4_


PA11 - - - SPI1_MISO - - - -

Pinouts and pin description


CH4 BKIN2 CTS EVENTOUT

TIM1_ USART1_ CM4_


PA12 -
ETR
- - - SPI1_MOSI -
RTS
- - -
EVENTOUT

JTMS- TSC_ CM4_


PA13 SWDIO
- - - - SPI1_MOSI - -
G7_IO1
- -
EVENTOUT

JTCK- LPTIM1_ I2C1_ CM4_


PA14 SWCLK OUT
- -
SMBA
SPI1_NSS - - - - -
EVENTOUT

TIM2_ TIM2_ TSC_ CM4_


PA15 JTDI
CH1 ETR
- SPI1_NSS MCO -
G3_IO1
- -
EVENTOUT
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Table 15. Alternate functions (continued)
50/112

Pinouts and pin description


AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF9 AF12 AF14 AF15
Port
LPTIM1/ I2C1/ RF/ LPTIM2/
SYS_AF TIM1/2 TIM1 SPI1 USART1 TSC TIM1 EVENTOUT
TIM1/2 SPI1 SYS_AF TIM2

RF_TX_ CM4_
PB0 - - - - - -
MOD_EXT_PA
- - - -
EVENTOUT

LPTIM2_ CM4_
PB1 - - - - - - - - - -
IN1 EVENTOUT

RTC_ LPTIM1_ CM4_


PB2 OUT OUT
- - - SPI1_NSS - - - - -
EVENTOUT

JTDO-
TIM2_ USART1_ CM4_
PB3 TRACE
CH2
- - - SPI1_SCK -
RTS_
- - -
EVENTOUT
SWO

USART1_ TSC_ CM4_


PB4 NJTRST - - - - SPI1_MISO -
CTS G2_IO1
- -
EVENTOUT
B
LPTIM1_ I2C1_ USART1_ TSC_ CM4_
PB5 -
IN1
- -
SMBA
SPI1_MOSI -
CK G2_IO2
- -
EVENTOUT
DS13259 Rev 7

LPTIM1_ I2C1_ USART1_ TSC_ CM4_


PB6 MCO
ETR
- -
SCL
SPI1_NSS -
TX G2_IO3
- -
EVENTOUT

LPTIM1_ I2C1_ USART1_ TSC_ CM4_


PB7 -
IN2
- TIM1_BKIN
SDA
- -
RX G2_IO4
TIM1_CH3 -
EVENTOUT

TIM1_ I2C1_ TSC_ CM4_


PB8 -
CH2N
- -
SCL
- - -
G7_IO3
- -
EVENTOUT

TIM1_ I2C1_ TSC_ CM4_


PB9 -
CH3N
- -
SDA
- - -
G7_IO4
- -
EVENTOUT

CM4_
PC14 - - - - - - - - - - -
EVENTOUT
C
CM4_
PC15 - - - - - - - - - - -
EVENTOUT

CM4_
E PE4 - - - - - - - - - - -
EVENTOUT

CM4_
H PH3 LSCO - - - - - - - - - -
EVENTOUT

STM32WB10CC
STM32WB10CC Memory mapping

5 Memory mapping

The STM32WB10CC devices feature a single physical address space that can be accessed
by the application processor and by the RF subsystem.
A part of the Flash memory and of the SRAM2a and SRAM2b is made secure, exclusively
accessible by the CPU2, protected against execution, read and write from CPU1 and DMA.
In case of shared resources the SW has to implement arbitration mechanism to avoid
access conflicts. This happens for peripherals Reset and clock controller (RCC), Power
controller (PWC), EXTI and Flash memory interface, and can be implemented using the
built-in semaphore block (HSEM).
By default the RF subsystem and the CPU2 operate in secure mode. This implies that part
of the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and
by the CPU2. In this case the Host processor (CPU1) has no access to these resources.
The detailed memory map and the peripheral mapping of the STM32WB10CC can be found
in the reference manual RM0478.

DS13259 Rev 7 51/112


51
Electrical characteristics STM32WB10CC

6 Electrical characteristics

6.1 Parameter conditions


Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values


Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3σ).

6.1.2 Typical values


Unless otherwise specified, typical data are based on VDD = VDDA = VDDRF = 3 V and
TA = 25 °C. They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2σ).

6.1.3 Typical curves


Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor


The loading conditions used for pin parameter measurement are shown in Figure 8.

6.1.5 Pin input voltage


The input voltage measurement on a pin of the device is described in Figure 9.

Figure 8. Pin loading conditions Figure 9. Pin input voltage

MCU pin MCU pin


C = 50 pF VIN

MS19210V1 MS19211V1

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STM32WB10CC Electrical characteristics

6.1.6 Power supply scheme

Figure 10. Power supply scheme

VBAT

Backup circuitry
1.55 V to 3.6 V (LSE, RTC and
backup registers)
Power switch
VDD VCORE
n x VDD
Regulator

VDDIO1
OUT
Kernel logic

Level shifter
IO (CPU, digital
GPIOs
n x 100 nF + 1 x 4.7 μF logic
IN and memories

VSS

VDDA
VDDA

10 nF + 1 μF VREF+
ADC
VREF-

VSS
VDDA
VDDRF
100 nF
+ 100 pF VSSRF Radio

MS53513V3
Exposed pad VSS
To all modules

1. The value of L1 depends upon the frequency, as indicated in Table 4: Typical external components.
Caution: Each power supply pair (e.g. VDD / VSS, VDDRF / VSSRF) must be decoupled with filtering
ceramic capacitors as shown in Figure 10. These capacitors must be placed as close as
possible to (or below) the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.

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102
Electrical characteristics STM32WB10CC

6.1.7 Current consumption measurement

Figure 11. Current consumption measurement scheme

IDDRF

VDDRF

IDDVBAT

VBAT
IDD

VDD

IDDA

VDDA

MSv63021V1

6.2 Absolute maximum ratings


Stresses above the absolute maximum ratings listed in Table 16, Table 17 and Table 18
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Device mission profile (application conditions) is compliant with JEDEC JESD47
Qualification standard, extended mission profiles are available on demand.

Table 16. Voltage characteristics(1)


Symbol Ratings Min Max Unit

External main supply voltage


VDDX - VSS -0.3 4.0
(including VDD, VDDA, VDDRF, VBAT)
Input voltage on FT_xxx pins min (VDD, VDDA, VDDRF) + 4.0(3)(4) V
VIN(2) Input voltage on TT_xx pins VSS-0.3 4.0
Input voltage on any other pin 4.0
Variation between different VDDX power pins of
|∆VDDx| - 50
the same domain mV
|VSSx-VSS| Variation between all the different ground pins - 50
1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS, VSSRF) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 17 for the maximum allowed injected current values.
3. This formula must be applied only on the power supplies related to the IO structures described in the pin definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

54/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 17. Current characteristics


Symbol Ratings Max Unit

∑IVDD Total current into sum of all VDD power lines (source)(1) 130
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 130
IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk by any I/O and control pin except FT_f 20
IIO(PIN) Output current sunk by any FT_f pin 20
mA
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins(2) 100
∑IIO(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 100
Injected current on FT_xxx, TT_xx, NRST and B pins, except PB0 and PB1 –5 / +0(4)
IINJ(PIN)(3)
Injected current on PB0 and PB1 -5/0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) 25
1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS, VSSRF) pins must always be connected to the external power
supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count packages.
3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 16: Voltage
characteristics for the maximum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).

Table 18. Thermal characteristics


Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150


°C
TJ Maximum junction temperature 130

DS13259 Rev 7 55/112


102
Electrical characteristics STM32WB10CC

6.3 Operating conditions

6.3.1 Summary of main performance

Table 19. Main performance at VDD = 3.3 V


Parameter Test conditions Typ Unit

VBAT (VBAT = 1.8 V, VDD = 0 V) 0.002


Shutdown (VDD = 2.0 V) 0.018
Standby (VDD = 3.0 V, 48 Kbytes RAM retention) 0.340

Core current Sleep (16 MHz) 0.610


ICORE
consumption LP run (2 MHz) 175
Run (64 MHz) 5850
Radio RX(1) 7700
(1)
Radio TX 0 dBm output power 8600
(2)
Advertising with Stop1 µA
19.2
(Tx = 0 dBm, period 1.28 s, 31 bytes, 3 channels)
Advertising(2) with Stop1
6
(Tx = 0 dBm, 6 bytes, period 1.24 s, 3 channels)
BLE
Peripheral Advertising(2) with Standby and LDO configuration
IPERI current 16.2
(Tx = 0 dBm, period 1.28 s, 31 bytes, 3 channels)
consumption
Advertising(2) with Standby and LDO configuration
2.3
(Tx = 0 dBm, 6 bytes, period 10.24 s, 3 channels)
LP timers - 5.800
RTC - 1.750
1. Power consumption including RF subsystem and digital processing.
2. Power consumption averaged over 300 s including Cortex M4, RF subsystem, digital processing and Cortex M0+.

6.3.2 General operating conditions

Table 20. General operating conditions


Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency -


fPCLK1 Internal APB1 clock frequency - 0 64 MHz
fPCLK2 Internal APB2 clock frequency -
VDD Standard operating voltage - 2.0(1)
3.6
ADC used 2.0
VDDA Analog supply voltage
ADC not used(2) 2.0 3.6 V
VBAT Backup operating voltage - 1.55
3.6
VDDRF Minimum RF voltage - 2.0

56/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 20. General operating conditions (continued)


Symbol Parameter Conditions Min Max Unit

TT_xx I/O –0.3 VDD + 0.3


VIN I/O input voltage min (min (VDD, VDDA) + V
All I/O except TT_xx –0.3
3.6 V, 5.5 V)(3)(4)

PD Power dissipation UFQFPN48 - 722 mW

Ambient temperature for Maximum power dissipation 85


TA –10
suffix 5 version Low-power dissipation (5) 105 °C
TJ Junction temperature range Suffix 5 version -10 105
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. When not used, VDDA must be connected to VDD.
3. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between min (VDD, VDDA) + 3.6 V and 5.5 V.
4. For operation with voltage higher than min (VDD, VDDA) + 0.3 V, the internal pull-up and pull-down resistors must be
disabled.
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.3:
Thermal characteristics).

6.3.3 RF BLE characteristics


RF characteristics are given at 1 Mbps, unless otherwise specified.

Table 21. RF transmitter BLE characteristics


Symbol Parameter Test conditions Min Typ Max Unit

Fop Frequency operating range - 2402 - 2480


MHz
Fxtal Crystal frequency - - 32 -

∆F Delta frequency - - 250 - kHz

Rgfsk On air data rate - - 1 - Mbps

PLLres RF channel spacing - - 2 - MHz

Table 22. RF transmitter BLE characteristics (1 Mbps)(1)


Symbol Parameter Test conditions Min Typ Max Unit

Maximum output power - - 4.0 -


Prf 0 dBm output power - - 0 - dBm
Minimum output power - - -20 -

Pband Output power variation over the band Tx = 0 dBm - Typical -0.5 - 0.4 dB

BW6dB 6 dB signal bandwidth Tx = max output power - 670 - kHz


2 MHz Bluetooth® Low Energy:-20 dBm - -50 -
IBSE In band spurious emission dBm
≥ 3 MHz Bluetooth® Low Energy: -30 dBm - -53 -

fd Frequency drift Bluetooth® Low Energy: ±50 kHz -50 - +50 kHz

DS13259 Rev 7 57/112


102
Electrical characteristics STM32WB10CC

Table 22. RF transmitter BLE characteristics (1 Mbps)(1) (continued)


Symbol Parameter Test conditions Min Typ Max Unit
®
Bluetooth Low Energy: kHz/
maxdr Maximum drift rate -20 - +20
±20 kHz / 50 µs 50 µs
Bluetooth® Low Energy:
fo Frequency offset -150 - +150
±150 kHz
kHz
Bluetooth® Low Energy:
∆f1 Frequency deviation average 225 - 275
between 225 and 275 kHz
Frequency deviation
∆fa Bluetooth® Low Energy:> 0.80 0.80 - - -
∆f2 (average) / ∆f1 (average)

Out of band < 1 GHz - - -62 -


OBSE(2) dBm
spurious emission ≥ 1 GHz - - -45 -
1. Measured in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and
impedance matching networks to interface with a 50 Ω antenna.
2. Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440
Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).

Table 23. RF receiver BLE characteristics (1 Mbps)


Symbol Parameter Test conditions Typ Unit

PER <30.8%
Prx_max Maximum input signal -4
Bluetooth® Low Energy: min -10 dBm

PER <30.8%
Psens(1) High sensitivity mode -95.5
Bluetooth® Low Energy: max -70 dBm dBm

Rssimaxrange RSSI maximum value - -7

Rssiminrange RSSI minimum value - -94

Rssiaccu RSSI accuracy - 2


dB
®
C/Ico Co-channel rejection Bluetooth Low Energy: 21 dB 9

58/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 23. RF receiver BLE characteristics (1 Mbps) (continued)


Symbol Parameter Test conditions Typ Unit

Adj ≥ 5 MHz
-46
Bluetooth® Low Energy: -27 dB
Adj ≤ -5 MHz
-48
Bluetooth® Low Energy:-27 dB
Adj = 4 MHz
-46
Bluetooth® Low Energy:-27 dB
Adj = -4 MHz
-33
Bluetooth® Low Energy:-15 dB
Adj = 3 MHz
C/I Adjacent channel interference -46
Bluetooth® Low Energy:-27 dB dB
Adj = 2 MHz
-39
Bluetooth® Low Energy:-17 dB
Adj = -2 MHz
-35
Bluetooth® Low Energy:-15 dB
Adj = 1 MHz
-2
Bluetooth® Low Energy: 15 dB
Adj = -1 MHz
2
Bluetooth® Low Energy: 15 dB
C/Image Image rejection (Fimage = -3 MHz) Bluetooth® Low Energy: -9 dB -28
|f2-f1| = 3 MHz
-36
Bluetooth® Low Energy: -50 dBm
|f2-f1| = 4 MHz
P_IMD Intermodulation -35
Bluetooth® Low Energy: -50 dBm
|f2-f1| = 5 MHz
-33
Bluetooth® Low Energy:-50 dBm
30 to 2000 MHz
-2 dBm
Bluetooth® Low Energy: -30 dBm
2003 to 2399 MHz
-8
Bluetooth® Low Energy: -35 dBm
P_OBB Out of band blocking
2484 to 2997 MHz
-4
Bluetooth® Low Energy: -35 dBm
3 to 12.75 GHz
6
Bluetooth® Low Energy: -30 dBm
1. With ideal TX.

Table 24. RF BLE power consumption for VDD = 3.3 V(1)


Symbol Parameter Typ Unit

Itxmax TX maximum output power consumption 11.3


Itx0dbm TX 0 dBm output power consumption 8.6 mA
Irxlo Rx consumption 7.7
1. Power consumption including RF subsystem and digital processing.

DS13259 Rev 7 59/112


102
Electrical characteristics STM32WB10CC

6.3.4 Operating conditions at power-up / power-down


The parameters given in Table 25 are derived from tests performed under the ambient
temperature condition summarized in Table 20.

Table 25. Operating conditions at power-up / power-down


Symbol Parameter Conditions Min Max Unit

VDD rise time rate - ∞


tVDD -
VDD fall time rate 10 ∞
VDDA rise time rate 0 ∞
tVDDA - µs/V
VDDA fall time rate 10 ∞
VDDRF rise time rate - ∞
tVDDRF -
VDDRF fall time rate - ∞

6.3.5 Embedded reset and power control block characteristics


The parameters given in Table 26 are derived from tests performed under the ambient
temperature conditions summarized in Table 20: General operating conditions.

Table 26. Embedded reset and power control block characteristics


Symbol Parameter Conditions(1) Min Typ Max Unit

tRSTTEMPO(2) Reset temporization after BOR0 is detected VDD rising - 250 400 μs
Rising edge 1.62 1.66 1.70
VBOR0(2) Brown-out reset threshold 0
Falling edge 1.60 1.64 1.69
Rising edge 2.06 2.10 2.14
VBOR1 Brown-out reset threshold 1
Falling edge 1.96 2.00 2.04
Rising edge 2.26 2.31 2.35
VBOR2 Brown-out reset threshold 2
Falling edge 2.16 2.20 2.24
Rising edge 2.56 2.61 2.66
VBOR3 Brown-out reset threshold 3
Falling edge 2.47 2.52 2.57
V
Rising edge 2.85 2.90 2.95
VBOR4 Brown-out reset threshold 4
Falling edge 2.76 2.81 2.86
Rising edge 2.10 2.15 2.19
VPVD0 Programmable voltage detector threshold 0
Falling edge 2.00 2.05 2.10
Rising edge 2.26 2.31 2.36
VPVD1 PVD threshold 1
Falling edge 2.15 2.20 2.25
Rising edge 2.41 2.46 2.51
VPVD2 PVD threshold 2
Falling edge 2.31 2.36 2.41

60/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 26. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit

Rising edge 2.56 2.61 2.66


VPVD3 PVD threshold 3
Falling edge 2.47 2.52 2.57
Rising edge 2.69 2.74 2.79
VPVD4 PVD threshold 4
Falling edge 2.59 2.64 2.69
V
Rising edge 2.85 2.91 2.96
VPVD5 PVD threshold 5
Falling edge 2.75 2.81 2.86
Rising edge 2.92 2.98 3.04
VPVD6 PVD threshold 6
Falling edge 2.84 2.90 2.96
Hysteresis in
- 20 -
continuous mode
Vhyst_BORH0 Hysteresis voltage of BORH0
Hysteresis in
- 30 - mV
other mode
Hysteresis voltage of BORH (except
Vhyst_BOR_PVD - - 100 -
BORH0) and PVD
BOR(3) (except BOR0) and PVD
IDD (BOR_PVD)(2) - - 1.1 1.6 µA
consumption from VDD
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
2. Specified by design, not tested in production.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current
characteristics tables.

DS13259 Rev 7 61/112


102
Electrical characteristics STM32WB10CC

6.3.6 Embedded voltage reference


The parameters given in Table 27 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20: General operating
conditions.

Table 27. Embedded internal voltage reference


Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage –10 °C < TJ < +105 °C 1.182 1.212 1.232 V
ADC sampling time when reading
tS_vrefint (1) - 4(2) - -
the internal reference voltage
µs
Start time of reference voltage
tstart_vrefint - - 8 12(2)
buffer when ADC is enabled
VREFINT buffer consumption from
IDD(VREFINTBUF) - - 12.5 20(2) µA
VDD when converted by ADC
Internal reference voltage spread
∆VREFINT VDD = 3 V - 5 7.5(2) mV
over the temperature range
TCoeff Temperature coefficient –10 °C < TJ < +105 °C - 30 50(2) ppm/°C
ACoeff Long term stability 1000 hours, TJ = 25 °C - 300 1000(2) ppm
VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage 24 25 26
%
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Specified by design, not tested in production.

Figure 12. VREFINT vs. temperature

1.235

1.230

1.225

1.220
VREFINT (V)

1.215

1.210

1.205

1.200

1.195

1.190

1.185
o
40 -20 0 20 40 60 80 100 T ( C)
120 °C
Mean Min Max
MSv63022V1

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STM32WB10CC Electrical characteristics

6.3.7 Supply current characteristics


The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.

Typical and maximum current consumption


The MCU is put under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0478 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
• For flash memory and shared peripherals fPCLK = fHCLK = fHCLKS
The parameters given in Table 28 to Table 38 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 20: General
operating conditions.

Table 28. Current consumption in Run and Low-power run modes, code with data processing
running from flash memory, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V
Typ Max(1)
Symbol Parameter Conditions fHCLK Unit
25 °C 55 °C 85 °C 25 °C 85 °C

fHCLK = fHSI16 up to 16 MHz 64 MHz 6.35 6.40 6.45 7.25 7.37


Supply
included, fHCLK = fHSE = 32 MHz
IDD(Run) current in 32 MHz 3.25 3.30 3.35 3.29 3.53
fHSI16 + PLL ON above 32 MHz
Run mode
All peripherals disabled 16 MHz 1.75 1.75 1.80 2.06 2.18
2 MHz 0.190 0.205 0.235 0.270 0.460 mA
Supply
IDD current in fHCLK = fMSI 1 MHz 0.105 0.115 0.145 0.170 0.320
(LPRun) Low-power All peripherals disabled 400 kHz 0.051 0.0605 0.0905 0.080 0.230
run mode
100 kHz 0.024 0.034 0.0645 0.040 0.190
1. Evaluated by characterization (mean ± 4 σ), not tested in production, unless otherwise specified.

DS13259 Rev 7 63/112


102
Electrical characteristics STM32WB10CC

Table 29. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1, VDD = 3.3 V
Typ Max(1)
Symbol Parameter Conditions- fHCLK Unit
25 °C 55 °C 85 °C 25 °C 85 °C

fHCLK = fHSI16 up to 16 MHz 64 MHz 6.75 6.80 6.85 8.05 8.22


Supply
included, fHCLK = fHSE = 32 MHz
IDD(Run) current in 32 MHz 3.45 3.50 3.55 3.55 3.69
fHSI16 + PLL ON above 32 MHz
Run mode
All peripherals disabled 16 MHz 1.85 1.85 1.90 1.77 1.94
2 MHz 0.200 0.215 0.245 0.330 0.600 mA
Supply
IDD current in fHCLK = fMSI 1 MHz 0.110 0.120 0.150 0.240 0.420
(LPRun) Low-power All peripherals disabled 400 kHz 0.0525 0.0615 0.0905 0.160 0.310
run mode
100 kHz 0.024 0.034 0.0625 0.130 0.180
1. Evaluated by characterization (mean ± 4 σ), not tested in production, unless otherwise specified.

Table 30. Typical current consumption in Run and Low-power run modes, with different codes
running from flash memory, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V
Typ Typ
Symbol Parameter Conditions Code Unit Unit
25 °C 25 °C

Reduced code(1) 6.35 99


All peripherals disabled
fHCLK = fHSI16 up to
16 MHz included,
fHSI16 + PLL ON
above 32 MHz

Coremark 6.20 97
Supply current
IDD(Run) fHCLK = 64 MHz Dhrystone 2.1 6.75 mA 105 µA/MHz
in Run mode
Fibonacci 6.05 95

While(1) 5.85 91

Reduced code(1) 190 95


Coremark 190 95
Supply current
fHCLK = fMSI = 2 MHz
IDD(LPRun) in Dhrystone 2.1 215 µA 108 µA/MHz
All peripherals disabled
Low-power run
Fibonacci 185 93
While(1) 175 88
1. Reduced code used for characterization results provided in Table 28 and Table 29.

64/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 31. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1, VDD = 3.3 V
Typ Typ
Symbol Parameter Conditions Code Unit Unit
25 °C 25 °C

Reduced code(1) 6.75 105

All peripherals disabled


fHCLK = fHSI16 up to
16 MHz included,
fHSI16 + PLL ON
above 32 MHz
Coremark 6.30 98
Supply current
IDD(Run) fHCLK = 64 MHz Dhrystone 2.1 6.20 mA 97 µA/MHz
in Run mode
Fibonacci 6.05 95

While(1) 6.20 98

Reduced code(1) 200 100


Coremark 190 95
Supply current
fHCLK = fMSI = 2 MHz
IDD(LPRun) in Dhrystone 2.1 185 µA 93 µA/MHz
All peripherals disabled
Low-power run
Fibonacci 180 90
While(1) 185 93
1. Reduced code used for characterization results provided in Table 28 and Table 29.

Table 32. Current consumption in Sleep and Low-power sleep modes, flash memory ON
Conditions Typ Max(1)
Symbol Parameter Unit
All peripherals disabled fHCLK 25 °C 55 °C 85 °C 25 °C 85 °C

Supply fHCLK = fHSI16 up to 16 MHz 64 MHz 1.80 1.85 1.85 2.04 2.20
IDD current in included,
32 MHz 0.990 1.00 1.05 0.980 1.22
(Sleep) Sleep fHCLK = fHSE up to 32 MHz
mode, fHSI16 + PLL ON above 32 MHz 16 MHz 0.605 0.610 0.640 0.690 0.910
2 MHz 0.055 0.065 0.095 0.080 0.240 mA
Supply
IDD current in 1 MHz 0.036 0.047 0.0765 0.060 0.210
f =f
(LPSleep) Low-power HCLK MSI 400 kHz 0.022 0.033 0.0625 0.030 0.180
sleep mode
100 kHz 0.016 0.0265 0.057 0.030 0.170
1. Evaluated by characterization (mean ± 4 σ), not tested in production, unless otherwise specified.

Table 33. Current consumption in Low-power sleep modes, flash memory in Power down
Conditions Typ Max(1)
Symbol Parameter Unit
All peripherals disabled fHCLK 25 °C 55 °C 85 °C 25 °C 85 °C

Supply 2 MHz 55 66 96 79 291


IDD current in 1 MHz 37 47 77 62 252
fHCLK = fMSI µA
(LPSleep) low-power 400 kHz 22 33 63 36 225
sleep mode
100 kHz 17 27 57 34 219
1. Evaluated by characterization (mean ± 4 σ), not tested in production, unless otherwise specified.

DS13259 Rev 7 65/112


102
Electrical characteristics STM32WB10CC

Table 34. Current consumption in Stop 1 mode


Conditions Typ Max(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C

Supply current 2.4 V 1.85 3.05 5.50 10.0 31.0 - - -


IDD
in Stop 1 mode, BLE disabled 3.0 V 1.85 3.05 5.55 10.0 31.5 2.50 9.30 112.6
(Stop 1)
RTC disabled 3.6 V 1.90 3.10 5.65 10.0 32.0 2.60 9.40 115.2
2.4 V 2.20 3.45 5,85 10.5 31.5 - - -
RTC clocked
IDD Supply current 3.0 V 2.30 3.50 6.00 10.5 32.0 3.10 10.9 114.0
by LSI
(Stop 1 in Stop 1 mode, 3.6 V 2.45 3.65 6.25 11.0 32.5 3.40 10.9 115.4
with RTC enabled, 2.4 V 2.05 3.45 5.90 10.5 31.5 - - -
RTC clocked by µA
RTC) BLE disabled
LSE quartz(2) in 3.0 V 2.25 3.60 6.05 10.5 32.0 2.90 10.7 113.8
Low drive mode 3.6 V 2.40 3.75 6.30 11.0 32.5 3.10 11.0 114.6
Wake-up clock
IDD Supply current HSI16. See (3). - 77 - - - - - -
(wake-up during wake-up
Wake-up clock 3.0 V
from from Stop 1
Stop1) bypass mode MSI = 32 MHz. - 54 - - - - - -
See (3).
1. Evaluated by characterization (mean ± 4 σ), not tested in production, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
3. Wake-up with code execution from flash memory. Average value given for a typical wake-up time as specified in Table 41:
Low-power mode wake-up timings.

Table 35. Current consumption in Stop 0 mode


Conditions Typ Max(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C

Supply current 2.4 V 99.5 100 105 115 140 - - -


in Stop 0 mode,
- 3.0 V 100 105 110 115 140 119.1 134.3 331.5
RTC disabled,
BLE disabled 3.6 V 100 105 110 115 145 165.0 135.7 358.2
IDD
µA
(Stop 0) Wake-up clock
Supply current HSI16. See (2). - 217 - - - - - -
during wake-up
Wake-up clock 3.0 V
from Stop 0
Bypass mode MSI = 32 MHz. - 234 - - - - - -
See (2).
1. Evaluated by characterization (mean ± 4 σ), not tested in production, unless otherwise specified.
2. Wake-up with code execution from flash memory. Average value given for a typical wake-up time as specified in Table 41:
Low-power mode wake-up timings.

66/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 36. Current consumption in Standby mode


Conditions Typ Max(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C

BLE disabled 2.4 V 250 345 540 935 3000 - - -


Supply current No
in Standby 3.0 V 255 355 565 985 3150 334 907 6959
independent
mode (backup watchdog 3.6 V 280 390 625 1050 3400 373 989 7270
IDD
registers and
(Standby) BLE disabled 2.4 V 465 565 765 1150 3200 - - -
SRAMs
retained), with
3.0 V 520 625 840 1250 3400 1309 1169 7188
RTC disabled independent
watchdog 3.6 V 595 715 950 1400 3750 1716 1259 7630
RTC clocked 2.4 V 600 700 900 1300 3350 - - -
by LSI, no
3.0 V 700 800 1000 1450 3600 898 1419 8182
independent
Supply current watchdog 3.6 V 815 935 1150 1600 3950 995 1569 604
in Standby
mode (backup RTC clocked 2.4 V 650 750 950 1350 3400 - - - nA
IDD by LSI, with
registers and 3.0 V 765 865 1100 1500 3650 1085 1487 7358
(Standby independent
SRAMs
with RTC) watchdog 3.6 V 905 1000 1250 1700 4050 1190 1641 8042
retained),
RTC enabled RTC clocked 2.4 V 645 755 955 1350 3400 - - -
BLE disabled by LSE
quartz (2) in 3.0 V 760 875 1100 1500 3700 588 1094 7332
low drive 3.6 V 920 1050 1300 1750 4100 738 1171 7757
mode
Supply current 2.4 V 85.0 100 145 240 850 - - -
to be
IDD subtracted in 3.0 V 95.0
- 110 165 285 1000 - - -
(SRAM)(3) Standby mode
when SRAM is
3.6 V 115 150 220 370 1250 - - -
not retained
IDD Supply current Wake-up
(wake-up during wake-up clock is
3.0 V - 0.5 - - - - - - mA
from from Standby HSI16.
Standby) mode See (4)
1. Evaluated by characterization (mean ± 4 σ), not tested in production, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
3. The supply current in Standby with SRAMs mode is IDD(Standby) + IDD(SRAMs). The supply current in Standby with RTC
with SRAM mode is IDD(Standby + RTC) + IDD(SRAM).
4. Wake-up with code execution from flash memory. Average value given for a typical wake-up time as specified in Table 41.

DS13259 Rev 7 67/112


102
Electrical characteristics STM32WB10CC

Table 37. Current consumption in Shutdown mode


Conditions Typ Max(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C
Supply current 2.4 V 10.0 18.0 41.0 93.0 440 - - -
in Shutdown
IDD mode (backup
- 3.0 V 16.0 28.0 58.0 125 560 - 140 1495
(Shutdown) registers
retained) RTC
3.6 V 34.0 54.0 99.0 190 745 - 143 1788
disabled
nA
Supply current RTC 2.4 V 405 425 455 515 875 - - -
in Shutdown clocked by
IDD
mode (backup LSE
(Shutdown 3.0 V 525 550 585 660 1100 - 2310 2193
quartz (2) in
with RTC) registers
retained) RTC low drive
3.6 V 680 710 760 860 1450 - 2283 2704
enabled mode
1. Evaluated by characterization (mean ± 4 σ), not tested in production, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.

Table 38. Current consumption in VBAT mode


Conditions Typ Max(1)
Symbol Parameter Unit
- VBAT 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C

2.4 V 1.00 2.00 5.00 13.0 62.0 - - -

RTC disabled 3.0 V 1.00 3.00 8.00 19.0 88.0 - - -


Backup
IDD domain 3.6 V 2.00 6.00 15.0 33.0 145 - - -
nA
(VBAT) supply 2.4 V 250 265 275 285 350 - - -
current RTC enabled
and clocked by 3.0 V 315 330 340 360 440 - - -
LSE quartz(2)
3.6 V 405 415 430 455 580 - - -

1. Evaluated by characterization, not tested in production, unless otherwise specified.


2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.

Table 39. Current under Reset condition


Typ Max(1)
Symbol Conditions Unit
0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C
2.4 V 330 335 345 350 385 - - -
IDD(RST) 3.0 V 350 355 365 370 410 - 484 - µA
3.6 V 370 375 385 390 430 - - -
1. Evaluated by characterization, not tested in production, unless otherwise specified.

68/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

I/O system current consumption


The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull resistors generate current consumption when the pin is
externally held to the opposite level. The value of this current can be computed using the
pull-up/pull-down resistors values given in Table 61: I/O static characteristics.
For the output pins, all internal or external pull-up/pull-down loads must be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is applied externally. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins, which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 40) the I/Os used by the application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal and external) connected to
the pin:
I SW = V DD × f SW × C
• ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
• VDD is the I/O supply voltage
• fSW is the I/O switching frequency
• C is the total capacitance seen by the I/O pin: C = CI/O+ CEXT
• CI/O is the I/O pin capacitance
• CEXT is the PCB board capacitance plus any connected external device pin
capacitance.
The test pin is configured in push-pull output mode, and is toggled by software at a fixed
frequency.

DS13259 Rev 7 69/112


102
Electrical characteristics STM32WB10CC

On-chip peripheral current consumption


The current consumption of the on-chip peripherals is given in Table 40. The MCU is placed
under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 16:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in
Table 40. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.

Table 40. Peripheral current consumption


Low-power
Peripheral Run Unit
run and Sleep

Bus Matrix(1) 2.10 1.70


TSC 0.940 0.900
CRC 0.400 0.380
AHB1
DMA1 1.70 1.60
DMAMUX 1.90 1.80
All AHB1 peripherals 5.30 5.00
(2)
AHB2 All AHB2 peripherals 1.70 1.70
µA/MHz
TRNG independent clock domain 2.35 NA
TRNG clock domain 1.55 NA
SRAM2 1.35 1.25
AHB Shared FLASH 7.05 6.70
AES2 5.30 5.45
PKA 2.80 2.70
All AHB shared peripherals 11.5 12.5

70/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 40. Peripheral current consumption (continued)


Low-power
Peripheral Run Unit
run and Sleep

RTC 0.940 0.875


I2C1 independent clock domain 1.95 3.90
I2C1 clock domain 3.75 4.10
LPTIM1 independent clock domain 1.95 2.90
LPTIM1 clock domain 3.45 3.60
APB1
TIM2 4.55 4.00
LPTIM2 clock domain 3.45 3.70
LPTIM2 independent clock domain 1.95 3.50
WWDG 0.350 0.625
All APB1 peripherals 15.5 16.0 µA/MHz
AHB to APB2(3) 0.900 1.10
TIM1 6.25 6.10
USART1 independent clock domain 3.05 6.50
USART1 clock domain 6.25 5.50
APB2
SPI1 1.25 1.05
ADC1 independent clock domain 0.940 0.600
ADC1 clock domain 0.780 0.600
All APB2 on 14.5 15.5
All peripherals 48.5 45.0
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. GPIOs consumption during read and write accesses.
3. The AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2.

6.3.8 Wake-up time from Low-power modes and voltage scaling


transition times
The wake-up times given in Table 41 are the latency between the event and the execution of
the first user instruction.
The device goes in Low-power mode after the WFE (Wait For Event) instruction.

Table 41. Low-power mode wake-up timings(1)


Symbol Parameter Conditions Typ Max Unit

Wake-up time from


tWUSLEEP Sleep mode - 9 10
to Run mode No. of
CPU
Wake-up time from Wake-up in flash with memory in power-down cycles
tWULPSLEEP Low-power sleep mode during low-power sleep mode (FPDS = 1 in 9 10
to Low-power run mode PWR_CR1) and with clock MSI = 2 MHz

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102
Electrical characteristics STM32WB10CC

Table 41. Low-power mode wake-up timings(1) (continued)


Symbol Parameter Conditions Typ Max Unit

Wake up time from Wake-up clock MSI = 32 MHz 2.38 2.96


Stop 0 mode
to Run mode in flash
Wake-up clock HSI16 = 16 MHz 1.69 2.00
tWUSTOP0 memory
Wake up time from Wake-up clock MSI = 32 MHz 2.63 3.00
Stop 0 mode
to Run mode in SRAM1 Wake-up clock HSI16 = 16 MHz 1.80 2.00
-
Wake up time from Wake-up clock MSI = 32 MHz 4.67 5.56
Stop 1 mode
to Run in flash memory Wake-up clock HSI16 = 16 MHz 5.09 6.03

Wake up time from Wake-up clock MSI = 32 MHz 4.88 5.55


Stop 1 mode
Wake-up clock HSI16 = 16 MHz 5.29 5.95 µs
to Run in SRAM1

tWUSTOP1 Wake up time from


Stop 1 mode to
7.96 9.59
Low-power run mode Regulator in
in flash memory Low-power
Wake-up clock MSI = 4 MHz
Wake up time from mode (LPR = 1
Stop 1 mode to in PWR_CR1)
8.00 9.47
Low-power run mode
in SRAM1
Wake-up time from
tWUSTBY Standby mode - Wake-up clock HSI16 = 16 MHz 51.0 58.1
to Run mode
1. Evaluated by characterization results (VDD = 3 V, T = 25 °C), not tested in production.

Table 42. Regulator modes transition times(1)


Symbol Parameter Conditions Typ Max Unit

Wake-up time from Low-power run mode


tWULPRUN Code run with MSI 2 MHz 15.33 16.30 µs
to Run mode(2)
1. Evaluated by characterization results (VDD = 3 V, T = 25 °C), not tested in production.
2. Time until REGLPF flag is cleared in PWR_SR2.

Table 43. Wake-up time using USART(1)


Symbol Parameter Conditions Typ Max Unit

Wake-up time needed to calculate the maximum Stop mode 0 - 1.7


tWUUSART USART baud rate allowing to wake-up from Stop µs
modes when USART clock source is HSI16 Stop mode 1/2 - 8.5

1. Specified by design, not tested in production.

72/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

6.3.9 External clock source characteristics


High-speed external user clock generated from an external source
The high-speed external (HSE) clock is supplied with a 32 MHz crystal oscillator, a sine or a
square wave.
The STM32WB10CC includes internal programmable capacitances that can be used to tune
the crystal frequency in order to compensate the PCB parasitic one.
The characteristics in Table 44 and Table 46 are measured over recommended operating
conditions, unless otherwise specified. Typical values are referred to TA = 25 °C and
VDD = 3.0 V.

Table 44. HSE crystal requirements(1)


Symbol Parameter Conditions Min Typ Max Unit

fNOM Oscillator frequency - - 32 - MHz


Includes initial accuracy, stability over
fTOL Frequency tolerance temperature, aging and frequency pulling - - 50 ppm
due to incorrect load capacitance.
CL Load capacitance - 6 - 8 pF
ESR Equivalent series resistance - - - 100 Ω
PD Drive level - - - 100 µW
1. 32 MHz XTAL validated for specific reference NX2016SA. For additional information refer to AN 5165 “Development of RF
hardware using STM32WB microcontrollers”, available on www.st.com.

Table 45. HSE clock source requirements(1)


Symbol Parameter Conditions Min Typ Max Unit

User external clock source


fHSE_ext - - 32 - MHz
frequency
Includes initial accuracy,
fTOLHSE Frequency tolerance - - 50 ppm
stability over temperature, aging.
VHSE Clock input voltage limit Sine or square wave, AC coupled(2) 0.4 - 1.6 VPP
tr, tf Rise and fall times 10%-90% square wave - - 15 * VPP ns
DuCy(HSE) Duty cycle - 45 50 55 %
Offset = 10 kHz - - -127
dBc /
φn(HSE) Phase noise for 32 MHz Offset = 100 kHz - - -135
Hz
Offset = 1 MHz - - -138
1. Specified by design, not tested in production.
2. Only AC coupling supported (capacitor 470 pF to 100 nF).

DS13259 Rev 7 73/112


102
Electrical characteristics STM32WB10CC

Table 46. HSE oscillator characteristics


Symbol Parameter Conditions Min Typ Max Unit

Startup time VDDRF stabilized, XOTUNE = 000000,


tSUA(HSE) - 1000 -
for 80% amplitude stabilization –10 to +85 °C range
µs
Startup time VDDRF stabilized, XOTUNE = 000000,
tSUR(HSE) - 250 -
for XOREADY signal –10 to +85 °C range
IDDRF(HSE) HSE current consumption(1) HSEGMC=000, XOTUNE = 000000 - 50 - µA
XOTg(HSE) XOTUNE granularity - 1 5
ppm
XOTfp(HSE) XOTUNE frequency pulling ±20 ±40 -
Capacitor bank
XOTnb(HSE) XOTUNE number of tuning bits - 6 - bit
XOTst(HSE) XOTUNE setting time - - 0.1 ms
1. Current consumption in standalone mode. The current consumption at device level is 350 µA in design simulation.

Note: For information about the trimming of the oscillator refer to AN5165 “Development of RF
hardware using STM32WB microcontrollers”, available on www.st.com.

Low-speed external user clock generated from an external source


The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. The information provided in this section is based on design simulation results
obtained with typical external components specified in Table 47. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins to minimize output distortion and startup stabilization time.
Refer to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

Table 47. Low-speed external user clock characteristics(1)


Symbol Parameter Conditions Min Typ Max Unit

LSEDRV[1:0] = 00
- 250 -
Low drive capability
LSEDRV[1:0] = 01
- 315 -
Medium low drive capability
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10
- 500 -
Medium high drive capability
LSEDRV[1:0] = 11
- 630 -
High drive capability
LSEDRV[1:0] = 00
- - 0.50
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Medium low drive capability
Gmcritmax Maximum critical crystal gm µA/V
LSEDRV[1:0] = 10
- - 1.70
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.70
High drive capability

74/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 47. Low-speed external user clock characteristics(1) (continued)


Symbol Parameter Conditions Min Typ Max Unit
(2)
tSU(LSE) Startup time VDD stabilized - 2 - s
Includes initial accuracy, stability
ftolLSE Frequency tolerance over temperature, aging, and -500 - 500 ppm
frequency pulling
1. Specified by design, not tested in production.
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) until a stable 32 MHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal refer to application note AN2867 “Oscillator design
guide for STM8S, STM8A and STM32 microcontrollers” available from www.st.com.

Figure 13. Typical application with a 32.768 kHz crystal

Resonator with integrated


capacitors
CL1

OSC32_IN fLSE

32.768 kHz Drive


resonator programmable
amplifier

OSC32_OUT
CL2

MS30253V2

Note: No external resistors are required between OSC32_IN and OSC32_OUT, and it is forbidden
to add one.
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics detailed in Section 6.3.16.
The recommend clock input waveform is shown in Figure 14.

Figure 14. Low-speed external clock source AC timing diagram

tw(LSEH)

VLSEH
90%
10%
VLSEL

tr(LSE) t
tf(LSE) tw(LSEL)
TLSE

MS19215V2

DS13259 Rev 7 75/112


102
Electrical characteristics STM32WB10CC

Table 48. Low-speed external user clock characteristics, bypass mode(1)


Symbol Parameter Conditions Min Typ Max Unit

User external clock


fLSE_ext - 21.2 32.768 44.4 kHz
source frequency
OSC32_IN input pin
VLSEH - 0.7 VDDx - VDDx
high level voltage
V
OSC32_IN input pin
VLSEL - VSS - 0.3 VDDx
low level voltage
tw(LSEH) OSC32_IN
- 250 - - ns
tw(LSEL) high or low time
Includes initial accuracy,
ftolLSE Frequency tolerance stability over temperature, -500 - +500 ppm
aging and frequency pulling
1. Specified by design, not tested in production.

6.3.10 Internal clock source characteristics


The parameters given in Table 49 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20: General operating
conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Table 49. HSI16 oscillator characteristics(1)


Symbol Parameter Conditions Min Typ Max Unit

fHSI16 HSI16 frequency VDD = 3.0 V, TA= 30 °C 15.88 - 16.08 MHz


Trimming code is not a
0.2 0.3 0.4
multiple of 64
TRIM HSI16 user trimming step
Trimming code is a
-4 -6 -8
multiple of 64
DuCy(HSI16)(2) Duty cycle - 45 - 55 %
HSI16 oscillator frequency drift TA = 0 to 85 °C -1 - 1
∆Temp(HSI16)
over temperature TA = –10 to 85 °C -2 - 1.5
HSI16 oscillator frequency drift
∆VDD(HSI16) VDD = 2.0 V to 3.6 V -0.1 - 0.05
over VDD
tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2
μs
tstab (HSI16)(2) HSI16 oscillator stabilization time - - 3 5
IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA
1. Evaluated by characterization, not tested in production.
2. Specified by design, not tested in production.

76/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Figure 15. HSI16 frequency vs. temperature

MHz
16.4
+2%
16.3
+1.5%
16.2 +1%

16.1

16

15.9

-1%
15.8
-1.5%
15.7
-2%
15.6
0 20 40 60 80 100
min mean max
MSv63023V1

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102
Electrical characteristics STM32WB10CC

Multi-speed internal (MSI) RC oscillator

Table 50. MSI oscillator characteristics(1)


Symbol Parameter Conditions Min Typ Max Unit

Range 0 98.7 100 101.3


Range 1 197.4 200 202.6
kHz
Range 2 394.8 400 405.2
Range 3 789.6 800 810.4
Range 4 0.987 1 1.013
Range 5 1.974 2 2.026
MSI mode
Range 6 3.948 4 4.052
Range 7 7.896 8 8.104
MHz
Range 8 15.79 16 16.21
Range 9 23.69 24 24.31

MSI frequency Range 10 31.58 32 32.42


after factory Range 11 47.38 48 48.62
fMSI calibration, done
at VDD = 3 V and Range 0 - 98.304 -
TA = 30 °C Range 1 - 196.608 -
kHz
Range 2 - 393.216 -
Range 3 - 786.432 -
Range 4 - 1.016 -
PLL mode Range 5 - 1.999 -
XTAL=
32.768 kHz Range 6 - 3.998 -
Range 7 - 7.995 -
MHz
Range 8 - 15.991 -
Range 9 - 23.986 -
Range 10 - 32.014 -
Range 11 - 48.005 -
MSI oscillator TA= 0 to 85 °C -3.5 - 3
∆TEMP(MSI)(2) frequency drift MSI mode %
over temperature TA= –10 to 85 °C -8 - 6

78/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 50. MSI oscillator characteristics(1) (continued)


Symbol Parameter Conditions Min Typ Max Unit

VDD =
-1.2 -
2.0 to 3.6 V
Range 0 to 3 0.5
VDD =
-0.5 -
2.4 to 3.6 V

MSI oscillator VDD =


-2.5 -
frequency drift 2.0 to 3.6 V
∆VDD(MSI)(2) Range 4 to 7 0.7
over VDD VDD =
(reference is 3 V) MSI mode -0.8 -
2.4 to 3.6 V %
VDD =
-5 -
2.0 to 3.6 V
Range 8 to 11 1
VDD =
-1.6 -
2.4 to 3.6 V
Frequency
∆FSAMPLING
variation in TA= –10 to 85 °C - 1 2
(MSI)(2)(4)
sampling mode(3)
RMS cycle-to-
CC jitter(MSI)(4) PLL mode Range 11 - - 60 -
cycle jitter ps
P jitter(MSI)(4) RMS period jitter PLL mode Range 11 - - 50 -
Range 0 - - 10 20
Range 1 - - 5 10

MSI oscillator Range 2 - - 4 8


tSU(MSI)(4) μs
start-up time Range 3 - - 3 7
Range 4 to 7 - - 3 6
Range 8 to 11 - - 2.5 6
10 % of final
- - 0.25 0.5
frequency
MSI oscillator PLL mode 5 % of final
tSTAB(MSI)(4) - - 0.5 1.25 ms
stabilization time Range 11 frequency
1 % of final
- - - 2.5
frequency

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Electrical characteristics STM32WB10CC

Table 50. MSI oscillator characteristics(1) (continued)


Symbol Parameter Conditions Min Typ Max Unit

Range 0 - - 0.6 1
Range 1 - - 0.8 1.2
Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
MSI oscillator Range 5 - - 6.5 9
MSI and
IDD(MSI)(4) power µA
PLL mode Range 6 - - 11 15
consumption
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190
1. Evaluated by characterization, not tested in production.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Specified by design, not tested in production.

Figure 16. Typical current consumption vs. MSI frequency

80/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Low-speed internal (LSI) RC oscillator

Table 51. LSI1 oscillator characteristics(1)


Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.0 V, TA = 30 °C 31.04 - 32.96


fLSI LSI1 frequency kHz
VDD = 2.0 to 3.6 V, TA = –10 to 85 °C 29.5 - 34
tSU(LSI1)(2) LSI1 oscillator start-up time - - 80 130
μs
tSTAB(LSI1)(2) LSI1 oscillator stabilization time 5% of final frequency - 125 180
LSI1 oscillator power
IDD(LSI1)(2) - - 110 180 nA
consumption
1. Evaluated by characterization, not tested in production.
2. Specified by design, not tested in production.

Table 52. LSI2 oscillator characteristics(1)


Symbol Parameter Conditions Min Typ Max Unit

fLSI2 Frequency(2) VDD = 2.0 to 3.6 V, TA = –10 to 85 °C 22 32 48 kHz


tSU (LSI2)(3) Start-up time - 1 - 3.5 ms
IDD(LSI2)(3) Power consumption - - 1 2 μA
∆TEMP(LSI2)(4) Stability over temperature - -200 - 200 ppm / °C
1. Evaluated by characterization, not tested in production.
2. LSI2 cannot be trimmed.
3. Specified by design, not tested in production, LSI2TRIM[3:0] field of register RCC_CSR = 0xC.
4. The ±500 ppm performance is respected when the temperature variation is lower than 1 °C between two LSI2 frequency
calibrations, with a maximum calibration interval of 4 s.

6.3.11 PLL characteristics


The parameters given in Table 53 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 20: General operating conditions.

Table 53. PLL characteristics(1)


Symbol Parameter Conditions Min Typ Max Unit

PLL input clock(2) - 2.66 - 16 MHz


fPLL_IN
PLL input clock duty cycle - 45 - 55 %
fPLL_P_OUT PLL multiplier output clock P - 2 - 64
fPLL_Q_OUT PLL multiplier output clock Q - 8 - 64
MHz
fPLL_R_OUT PLL multiplier output clock R - 8 - 64
fVCO_OUT PLL VCO output - 96 - 344
tLOCK PLL lock time - - 15 40 μs
RMS cycle-to-cycle jitter - 40 -
Jitter System clock 64 MHz ps
RMS period jitter - 30 -

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Electrical characteristics STM32WB10CC

Table 53. PLL characteristics(1) (continued)


Symbol Parameter Conditions Min Typ Max Unit

VCO freq = 96 MHz - 200 260


PLL power consumption
IDD(PLL) VCO freq = 192 MHz - 300 380 μA
on VDD(1)
VCO freq = 344 MHz - 520 650
1. Specified by design, not tested in production.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the two PLLs.

6.3.12 Flash memory characteristics

Table 54. Flash memory characteristics(1)


Symbol Parameter Conditions Typ Max Unit

tprog 64-bit programming time - 81.7 90.8 µs

One row (64 double word) Normal programming 5.2 5.5


tprog_row
programming time Fast programming 3.8 4.0

One page (2 Kbytes) Normal programming 41.8 43.0


tprog_page ms
programming time Fast programming 30.4 31.0
tERASE Page (2 Kbytes) erase time - 22.0 24.5
tME Mass erase time - 22.1 25.0
Write mode 3.4 -
IDD Average consumption from VDD mA
Erase mode 3.4 -
1. Specified by design, not tested in production.

Table 55. Flash memory endurance and data retention


Symbol Parameter Conditions Min(1) Unit

NEND Endurance TA = –10 to +85 °C 10 kcycles


(2)
1 kcycle at TA = 85 °C 30
tRET Data retention 10 kcycles(2) at TA = 55 °C 30 Years
(2)
10 kcycles at TA = 85 °C 15
1. Evaluated by characterization, not tested in production.
2. Cycling performed over the whole temperature range.

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6.3.13 EMC characteristics


Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)


While a simple application is executed on the device (toggling two LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: a burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 56. They are based on the EMS levels and classes
defined in application note AN1709 “EMC design guide for STM8, STM32 and Legacy
MCUs”, available on www.st.com.

Table 56. EMS characteristics


Symbol Parameter Conditions Level/Class

VDD = 3.3 V, TA = +25 °C,


Voltage limits to be applied on any I/O pin
VFESD fHCLK = 64 MHz, 3B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 64 MHz, 5A
pins to induce a functional disturbance conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems


EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flow must include the management of runaway conditions such as:
• corrupted program counter
• unexpected reset
• critical data corruption (e.g. control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for
1 second.
To complete these trials, ESD stress is applied directly on the device, over the specified
values range. When unexpected behavior is detected, the software can be hardened to

DS13259 Rev 7 83/112


102
Electrical characteristics STM32WB10CC

prevent the occurrence of unrecoverable errors (see AN1015 “Software techniques for
improving microcontrollers EMC performance”, available on www.st.com).

Electromagnetic interference (EMI)


The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with the
IEC 61967-2 standard, which specifies the test board and the pin loading.

Table 57. EMI characteristics for fHSE / fCPUM4, fCPUM0 = 32 MHz / 64 MHz, 32 MHz
Monitored
Symbol Parameter Conditions Peripheral ON Unit
frequency band

0.1 MHz to 30 MHz 4


30 MHz to 130 MHz 8
Peak(1) VDD = 3.6 V, TA = 25 °C, dBµV
SEMI UFQFPN48 package 130 MHz to 1 GHz 0
compliant with IEC 61967-2
1 GHz to 2 GHz 9
Level(2) 0.1 MHz to 2 GHz 1.5 -
1. Refer to AN1709, “EMI radiated test” section.
2. Refer to AN1709, “EMI level classsification” section.

6.3.14 Electrical sensitivity characteristics


Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)


Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pins). This test
conforms to the ANSI/JEDEC standard.

Table 58. ESD absolute maximum ratings


Symbol Ratings Conditions Class Maximum value(1) Unit

Electrostatic discharge voltage TA = +25 °C, conforming to


VESD(HBM) 2 2000
(human body model) ANSI/ESDA/JEDEC JS-001
V
Electrostatic discharge voltage TA = +25 °C, conforming to
VESD(CDM) C2a 500
(charge device model) ANSI/ESD STM5.3.1 JS-002
1. Evaluated by characterization, not tested in production.

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• a supply overvoltage is applied to each power supply pin
• a current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.

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Table 59. Electrical sensitivities


Symbol Parameter Conditions Class

LU Static latch-up class TA = +105 °C conforming to JESD78A II

6.3.15 I/O current injection characteristics


As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibility to I/O current injection


While a simple application is executed, the device is stressed by injecting current into the
I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at
a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5/0 µA range) or other functional failure (for example reset occurrence or oscillator
frequency deviation).
The characterization results are given in Table 60.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.

Table 60. I/O current injection susceptibility(1)


Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on all pins,


-5 N/A(2)
IINJ except AT0, AT1, PB0, and PB1 mA
Injected current on AT0, AT1, PB0, and PB1 pins 0 0
1. Evaluated by characterization, not tested in production.
2. Injection not possible.

6.3.16 I/O port characteristics


General input/output characteristics
For information on GPIO configuration, refer to AN4899 “STM32 GPIO configuration for
hardware settings and low-power consumption” available on www.st.com.
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under the conditions summarized in Table 20: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.

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Electrical characteristics STM32WB10CC

Table 61. I/O static characteristics


Symbol Parameter Conditions Min Typ Max Unit

I/O input
- - 0.3 x VDD
low level voltage(1)
VIL
I/O input
0.39 x VDD - 0.06
low level voltage(1)
V
I/O input
0.7 x VDD - -
high level voltage(1) 2.0 V < VDD < 3.6 V
VIH
I/O input
0.49 x VDD + 0.26 - -
high level voltage(1)
TT_xx, FT_xxx
Vhys and NRST I/O - 200 - mV
input hysteresis
0 ≤ VIN ≤ Max(VDDXXX)(2) - - ±100
Max(VDDXXX) ≤ VIN ≤
FT_xx - - 650
Max(VDDXXX) +1 V(1)(2)(3)
input leakage current
Max(VDDXXX) +1 V < VIN ≤
Ilkg - - 200(6) nA
5.5 V(1)(2)(3)(4)(5)
VIN ≤ Max(VDDXXX)(2) - - ±150
TT_xx
input leakage current Max(VDDXXX) ≤ VIN < - - 2000
3.6 V(2)
Weak pull-up
RPU VIN = VSS 25 40 55
equivalent resistor(1)
kΩ
Weak pull-down
RPD VIN = VDD 25 40 55
equivalent resistor(1)
I/O pin
CIO - - 5 - pF
capacitance(7)
1. Specified by design, not tested in production.
2. Represents the pad leakage of the I/O itself. The total product pad leakage is given by
ITotal_Ileak_max = 10 μA + number of I/Os where VIN is applied on the pad x Ilkg(Max).
3. Max(VDDXXX) is the maximum value among all the I/O supplies.
4. VIN must be lower than [Max(VDDXXX) + 3.6 V].
5. Refer to Figure 17: I/O input characteristics.
6. To sustain a voltage higher than min(VDD, VDDA) + 0.3 V, the internal pull-up and pull-down resistors must be disabled. All
FT_xx IOs.
7. RF I/O structure excluded.

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All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
in Figure 17 .

Figure 17. I/O input characteristics


Vil-Vih (all IO except BOOT0)
3

2.5

TTL requirement Vih min = 2V


2

cmos vil spec 30%


cmos vih spec 70%
Voltage

1.5 ttl vil spec ttl


ttl vih spec ttl
datasheet Vil_rule
datasheet Vih_rule
1

TTL requirement Vil min = 0.8V

0.5

0
2 2.5 3 3.5
MSv63025V1

Output driving current


The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL / VOH).
In the user application, the number of I/O pins that can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2.
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 16: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 16: Voltage characteristics).

Output voltage levels


Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 20: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT or TT
unless otherwise specified).

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Electrical characteristics STM32WB10CC

Table 62. Output voltage characteristics(1)


Symbol Parameter Conditions Min Max Unit

VOL(2) Output low level voltage for an I/O pin CMOS port(3) - 0.4
|IIO| = 8 mA
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V VDD - 0.4 -

VOL(2) Output low level voltage for an I/O pin TTL port(3) - 0.4
|IIO| = 8 mA
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V 2.4 -

VOL(2) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V VDD - 1.3 - V

VOL(2) Output low level voltage for an I/O pin |IIO| = 4 mA - 0.4
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.0 V VDD - 0.45 -
|IIO| = 20 mA
- 0.4
Output low level voltage for an FT I/O VDD ≥ 2.7 V
VOLFM+(2)
pin in FM+ mode (FT I/O with “f” option) |I | = 10 mA
IO - 0.4
VDD ≥ 2.0 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 16: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports
and control pins) must always respect the absolute maximum ratings Σ IIO.
2. Specified by design, not tested in production.
3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Table 63.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 20: General
operating conditions.

Table 63. I/O AC characteristics(1)(2)


Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5


C=50 pF, 2.0 V ≤ VDD ≤ 2.7 V - 1
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 10
C=10 pF, 2.0 V ≤ VDD ≤ 2.7 V - 1.5
00
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 25
C=50 pF, 2.0 V ≤ VDD ≤ 2.7 V - 52
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 17
C=10 pF, 2.0 V ≤ VDD ≤ 2.7 V - 37

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Table 63. I/O AC characteristics(1)(2) (continued)


Speed Symbol Parameter Conditions Min Max Unit

C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 25


C=50 pF, 2.0 V ≤ VDD ≤ 2.7 V - 10
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50
C=10 pF, 2.0 V ≤ VDD ≤ 2.7 V - 15
01
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 9
C=50 pF, 2.0 V ≤ VDD ≤ 2.7 V - 16
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 4.5
C=10 pF, 2.0 V ≤ VDD ≤ 2.7 V - 9
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50
C=50 pF, 2.0 V ≤ VDD ≤ 2.7 V - 25
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100(3)
C=10 pF, 2.0 V ≤ VDD ≤ 2.7 V - 37.5
10
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.8
C=50 pF, 2.0 V ≤ VDD ≤ 2.7 V - 11
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.5
C=10 pF, 2.0 V ≤ VDD ≤ 2.7 V - 5
C=30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 120(3)
C=30 pF, 2.0 V ≤ VDD ≤ 2.7 V - 50
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 180(3)
C=10 pF, 2.0 V ≤ VDD ≤ 2.7 V - 75(3)
11
C=30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.3
C=30 pF, 2.0 V ≤ VDD ≤ 2.7 V - 6
Tr/Tf Output rise and fall time ns
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.7
C=10 pF, 2.0 V ≤ VDD ≤ 2.7 V - 3.3
1. The maximum frequency is achieved with a duty cycle comprised between 45 and 55%, when loaded by
the specified capacitance.
2. The fall and rise times are defined, respectively, between 90 and 10%, and between 10 and 90% of the
output waveform.
3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.

6.3.17 NRST pin characteristics


The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pull-up resistor, RPU.
Unless otherwise specified, the parameters given in Table 64 are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 20: General operating conditions.

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Electrical characteristics STM32WB10CC

Table 64. NRST pin characteristics(1)


Symbol Parameter Conditions Min Typ Max Unit

NRST input
VIL(NRST) - - - 0.3 x VDD
low level voltage
V
NRST input
VIH(NRST) - 0.7 x VDD - -
high level voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up
RPU VIN = VSS 25 40 55 kΩ
equivalent resistor(2)
NRST input
VF(NRST) - - - 70
filtered pulse
ns
NRST input
VNF(NRST) 2.0 V ≤ VDD ≤ 3.6 V 350 - -
not filtered pulse
1. Specified by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10%).

Figure 18. Recommended NRST pin protection

External
reset circuit(1) VDD

RPU
NRST(2) Internal reset
Filter

0.1 μF(3)

MS19878V3

1. The reset network protects the device against parasitic resets.


2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 64, otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.

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6.3.18 Analog switches booster

Table 65. Analog switches booster characteristics(1)


Symbol Parameter Min Typ Max Unit

VDD Supply voltage 2.0 - 3.6 V


tSU(BOOST) Booster startup time - - 240 µs
Booster consumption for
- - 500
2.0 V ≤ VDD < 2.7 V
IDD(BOOST) µA
Booster consumption for
- - 900
2.7 V ≤ VDD ≤ 3.6 V
1. Specified by design, not tested in production.

6.3.19 Analog-to-Digital converter characteristics


Unless otherwise specified, the parameters given in Table 66 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 20: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.

Table 66. ADC characteristics(1) (2)


Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 2.0 - 3.6 V


fADC ADC clock frequency - 0.14 - 35 MHz
12 bits - - 2.50
10 bits - - 2.92
fs Sampling rate Msps
8 bits - - 3.50
6 bits - - 4.38
fADC = 35 MHz
External trigger - - 2.33
fTRIG 12 bits MHz
frequency
12 bits - - fADC / 15
Conversion voltage
VAIN (3) - 0 - VDDA V
range(2)
External input
RAIN - - - 50 kΩ
impedance
Internal sample and hold
CADC - - 5 - pF
capacitor
Conversion
tSTAB Power-up time - 2
cycle
fADC = 35 MHz 2.35 µs
tCAL Calibration time
- 82 1 / fADC

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Electrical characteristics STM32WB10CC

Table 66. ADC characteristics(1) (2) (continued)


Symbol Parameter Conditions Min Typ Max Unit

CKMODE = 00 2 - 3

Trigger conversion CKMODE = 01 - 6.5 -


tLATR 1 / fADC
latency CKMODE = 10 - 12.5 -
CKMODE = 11 - 3.5 -
fADC = 35 MHz 0.043 - 4.59 µs
ts Sampling time
- 1.5 - 160.5 1 / fADC
ADC voltage regulator
tADCVREG_STUP - - - 20 µs
start-up time
fADC = 35 MHz
0.40 - 4.95 µs
Total conversion time Resolution = 12 bits
tCONV
(including sampling time) ts + 12.5 cycles for successive
Resolution = 12 bits 1 / fADC
approximations = 14 to 173
fs = 2.5 Msps - 475 -
ADC consumption from
IDDA(ADC) fs = 1 Msps - 190 - µA
the VDDA supply
fs = 10 ksps - 17.3 -
1. Specified by design, not tested in production
2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSS.

Table 67. Maximum ADC RAIN values


Resolution Sampling cycle at 35 MHz (ns) Sampling time at 35 MHz (ns) Max. RAIN(1)(2)(Ω)

1.5 43 50
3.5 100 680
7.5 214 2200
12.5 357 4700
12 bits
19.5 557 8200
39.5 1129 15000
79.5 2271 33000
160.5 4586 50000

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Table 67. Maximum ADC RAIN values (continued)


Resolution Sampling cycle at 35 MHz (ns) Sampling time at 35 MHz (ns) Max. RAIN(1)(2)(Ω)

1.5 43 68
3.5 100 820
7.5 214 3300
12.5 357 5600
10 bits
19.5 557 10000
39.5 1129 22000
79.5 2271 39000
160.5 4586 50000
1.5 43 82
3.5 100 1500
7.5 214 3900
12.5 357 6800
8 bits
19.5 557 12000
39.5 1129 27000
79.5 2271 50000
160.5 4586 50000
1.5 43 390
3.5 100 2200
7.5 214 5600
12.5 357 10000
6 bits
19.5 557 15000
39.5 1129 33000
79.5 2271 50000
160.5 4586 50000
1. Specified by design, not tested in production.
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and
disabled when VDDA ≥ 2.4 V.

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Table 68. ADC accuracy(1)(2)(3)


Symbol Parameter Conditions(4) Min Typ Max Unit

VDDA = 3 V, fADC = 35 MHz,


Total - 3 4
fs ≤ 2.5 Msps, TA = 25 °C
ET unadjusted
error 2.0 V < VDDA < 3.6 V, fADC = 35 MHz,
- 3 6.5
fs ≤ 2.5 Msps, TA = entire range
VDDA = 3 V, fADC = 35 MHz,
- 1.5 2
fs ≤ 2.5 Msps, TA = 25 °C
EO Offset error
2.0 V < VDDA < 3.6 V, fADC = 35 MHz,
- 1.5 4.5
fs ≤ 2.5 Msps, TA = entire range
VDDA = 3 V, fADC = 35 MHz,
- 3 3.5
fs ≤ 2.5 Msps, TA = 25 °C
EG Gain error LSB
2.0 V < VDDA < 3.6 V, fADC = 35 MHz,
- 3 5
fs ≤ 2.5 Msps, TA = entire range
VDDA = 3 V, fADC = 35 MHz,
- 1.2 1.5
Differential fs ≤ 2.5 Msps, TA = 25 °C
ED
linearity error 2.0 V < VDDA < 3.6 V, fADC = 35 MHz,
- 1.2 1.5
fs ≤ 2.5 Msps, TA = entire range
VDDA = 3 V, fADC = 35 MHz,
- 2.5 3
Integral fs ≤ 2.5 Msps, TA = 25 °C
EL
linearity error 2.0 V < VDDA < 3.6 V, fADC = 35 MHz,
- 2.5 3
fs ≤ 2.5 Msps, TA = entire range
VDDA = 3 V, fADC = 35 MHz,
10.1 10.2 -
Effective fs ≤ 2.5 Msps, TA = 25 °C
ENOB bit
number of bits 2.0 V < VDDA < 3.6 V, fADC = 35 MHz,
9.6 10.2 -
fs ≤ 2.5 Msps, TA = entire range
VDDA = 3 V, fADC = 35 MHz,
Signal-to-noise f ≤ 2.5 Msps, T = 25 °C 62.5 63.0 -
s A
SINAD and
distortion ratio 2.0 V < VDDA < 3.6 V, fADC = 35 MHz, 59.5 63.0 -
fs ≤ 2.5 Msps, TA = entire range
VDDA = 3 V, fADC = 35 MHz,
63.0 64.0 -
Signal-to-noise fs ≤ 2.5 Msps, TA = 25 °C
SNR dB
ratio 2.0 V < VDDA < 3.6 V, fADC = 35 MHz,
60.0 64.0 -
fs ≤ 2.5 Msps, TA = entire range
VDDA = 3 V, fADC = 35 MHz,
- -74 -73
Total harmonic fs ≤ 2.5 Msps, TA = 25 °C
THD distortion 2.0 V < VDDA < 3.6 V, fADC = 35 MHz,
- -74 -70
fs ≤ 2.5 Msps, TA = entire range
1. Based on characterization results, not tested in production.
2. ADC DC accuracy values are measured after internal calibration.
3. Injecting negative current on any analog input pin significantly reduces the accuracy of A-to-D conversion of signal on
another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins susceptible to receive
negative current.
4. I/O analog switch voltage booster is enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled
when VDDA ≥ 2.4 V.

94/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Figure 19. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA

MSv19880V6

Figure 20. Typical connection diagram when using the ADC


with FT/TT pins featuring analog switch function

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter


analog
RAIN(1) switch RADC
Converter
(2)
Cparasitic Ilkg(3) CADC
VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to Table 66: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 61: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value downgrades the conversion accuracy. To remedy this fADC must be reduced.
3. Refer to Table 61: I/O static characteristics for the values of Ilkg.
4. Refer to Figure 10: Power supply scheme.

General PCB design guidelines


Power supply decoupling has to be performed as shown in Figure 10: Power supply
scheme. The 10 nF capacitor must be ceramic (good quality), placed as close as possible to
the chip.

DS13259 Rev 7 95/112


102
Electrical characteristics STM32WB10CC

6.3.20 Temperature sensor characteristics

Table 69. TS characteristics


Symbol Parameter Min Typ Max Unit

TL(1) VTS linearity with temperature - ±1 ±2 °C


(2)
Avg_Slope Average slope 2.3 2.5 2.7 mV / °C
V30 Voltage at 30 °C (±5 °C)(3) 0.742 0.76 0.785 V
tSTART
Sensor buffer start-up time in continuous mode(4) - 8 15 µs
(TS_BUF)(1)

tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs

tS_temp(1) ADC sampling time when reading the temperature 5 - - µs

Temperature sensor consumption from VDD, when


IDD(TS)(1) - 4.7 7 µA
selected by ADC
1. Specified by design, not tested in production.
2. Evaluated by characterization, not tested in production.
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 9:
Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

6.3.21 VBAT monitoring characteristics

Table 70. VBAT monitoring characteristics(1)


Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 3 x 39 - kΩ


Q Ratio on VBAT measurement - 3 - -
(2)
Er Error on Q -10 - 10 %
tS_vbat(2) ADC sampling time when reading the VBAT 12 - - µs
1. 1.55 V < VBAT < 3.6 V.
2. Specified by design, not tested in production.

Table 71. VBAT charging characteristics


Symbol Parameter Conditions Min Typ Max Unit

VBRS = 0 - 5 -
RBC Battery charging resistor kΩ
VBRS = 1 - 1.5 -

6.3.22 Timer characteristics


The parameters given in the following tables are Specified by design, not tested in
production. Refer to Section 6.3.16 for details on the input/output alternate function
characteristics (output compare, input capture, external clock, PWM output).

96/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 72. TIMx(1) characteristics


Symbol Parameter Conditions Min Max Unit

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 64 MHz 15.625 - ns

Timer external clock frequency - 0 fTIMxCLK / 2


fEXT MHz
on CH1 to CH4 fTIMxCLK = 64 MHz 0 40
TIM1 - 16
ResTIM Timer resolution bit
TIM2 - 32
- 1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period
fTIMxCLK = 64 MHz 0.015625 1024 µs

Maximum possible count with - - 65536 × 65536 tTIMxCLK


tMAX_COUNT
32-bit counter fTIMxCLK = 64 MHz - 67.10 s
1. TIMx, is used as a general term, x stands for 1 or 2.

Table 73. IWDG min/max timeout period at 32 kHz (LSI1)(1)


Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF Unit

/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock vs. the LSI clock, hence there is always a full RC
period of uncertainty.

6.3.23 Communication interfaces characteristics


I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): bit rate up to 100 kbit/s
• Fast-mode (Fm): bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s.

DS13259 Rev 7 97/112


102
Electrical characteristics STM32WB10CC

Table 74. Minimum I2CCLK frequency in all I2C modes


Symbol Parameter Condition Min Unit

Standard-mode - 2
Analog filter ON, DNF = 0 8
I2CCLK Fast-mode
f(I2CCLK) Analog filter OFF, DNF = 1 9 MHz
frequency
Analog filter ON, DNF = 0 17
Fast-mode Plus
Analog filter OFF, DNF = 1 16

The I2C timings requirements are Specified by design, not tested in production when the
I2C peripheral is properly configured (refer to the reference manual RM0478).
The SDA and SCL I/O requirements are met with the following restriction: the SDA and SCL
I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present. The 20 mA output drive
requirement in Fast-mode Plus is supported partially.
This limits the maximum load Cload supported in Fast-mode Plus, given by these formulas:
• tr(SDA/SCL) = 0.8473 x Rp x Cload
• Rp(min) = [VDD - VOL(max)] / IOL(max)
where Rp is the I2C lines pull-up. Refer to Section 6.3.16 for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter, refer to Table 75 for its characteristics.

Table 75. I2C analog filter characteristics(1)


Symbol Parameter Min Max Unit

Maximum pulse width of spikes that


tAF 50(2) 100(3) ns
are suppressed by the analog filter
1. Specified by design, not tested in production.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered

SPI characteristics
Unless otherwise specified, the parameters given in Table 76 are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 20: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD
Refer to Section 6.3.16 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).

98/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Table 76. SPI characteristics(1)


Symbol Parameter Conditions Min Typ Max Unit

Master mode
- - 32
2.0 < VDD < 3.6 V
Slave receiver mode
- - 32
fSCK 2.0 < VDD < 3.6 V
SPI clock frequency MHz
1/tc(SCK) Slave mode transmitter/full duplex
- - 32(2)
2.7 < VDD < 3.6 V
Slave mode transmitter/full duplex
- - 24(2)
2.0 < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4 x TPCLK - -
th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2 x TPCLK - -
-
tw(SCKH)
SCK high and low time Master mode TPCLK - 1.5 TPCLK TPCLK + 1
tw(SCKL)
tsu(MI) Master mode 6.5 - -
Data input setup time
tsu(SI) Slave mode 1.5 - -
th(MI) Master mode 4.5 - -
Data input hold time
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time 9.0 - 34
Slave mode
tdis(SO) Data output disable time 9.0 - 16 ns
Slave mode 2.7 < VDD < 3.6 V - 10.5 13.0
tv(SO)
Data output valid time Slave mode 2.0 < VDD < 3.6 V - 10.5 20.5
tv(MO) Master mode (after enable edge) - 2.5 3.0
th(SO) Slave mode (after enable edge) 8.0 - -
Data output hold time
th(MO) Master mode (after enable edge) 1.0 - -
1. Evaluated by characterization, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.

DS13259 Rev 7 99/112


102
Electrical characteristics STM32WB10CC

Figure 21. SPI timing diagram - Slave mode and CPHA = 0

NSS input

tc(SCK) th(NSS)

tsu(NSS) tw(SCKH) tr(SCK)


CPHA=0
SCK input

CPOL=0

CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

th(SI)
tsu(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41658V1

Figure 22. SPI timing diagram - Slave mode and CPHA = 1

NSS input

tc(SCK)

tsu(NSS) tw(SCKH) tf(SCK) th(NSS)


CPHA=1
SCK input

CPOL=0

CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)

MISO output First bit OUT Next bits OUT Last bit OUT

tsu(SI) th(SI)

MOSI input First bit IN Next bits IN Last bit IN

MSv41659V1

1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.

100/112 DS13259 Rev 7


STM32WB10CC Electrical characteristics

Figure 23. SPI timing diagram - Master mode

High
NSS input
tc(SCK)
SCK Output

CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT

tv(MO) th(MO)

ai14136c

1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.

DS13259 Rev 7 101/112


102
Electrical characteristics STM32WB10CC

JTAG/SWD interface characteristics


Unless otherwise specified, the parameters given in Table 77 and Table 78 are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 20: General operating conditions. with the following
configuration:
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD

Table 77. JTAG characteristics


Symbol Parameter Conditions Min Typ Max Unit

2.7 < VDD < 3.6 V - - 29


1/tc(TCK) TCK clock frequency MHz
2.0 < VDD < 3.6 V - - 21
tisu(TMS) TMS input setup time - 2.5 - -
tih(TMS) TMS input hold time - 2.0 - -
tisu(TDI) TDI input setup time - 2.0 - -
tih(TDI) TDI input hold time - 2.0 - - ns
2.7 < VDD < 3.6 V - 13.5 16.5
tov(TDO) TDO output valid time
2.0 < VDD < 3.6 V - 13.5 23.0
toh(TDO) TDO output hold time - 11.0 - -

Table 78. SWD characteristics


Symbol Parameter Conditions Min Typ Max Unit

2.7 < VDD < 3.6 V - - 55


1 / tc(SWCLK) SWCLK clock frequency MHz
2.0 < VDD < 3.6 V - - 35
tisu(TMS) SWDIO input setup time - 2.5 - -
tih(TMS) SWDIO input hold time - 2.0 - -
2.7 < VDD < 3.6 V - 16 18 ns
tov(TDO) SWDIO output valid time
2.0 < VDD < 3.6 V - 16 28
toh(TDO) SWDIO output hold time - 13 - -

Refer to Section 6.3.16 for more details on the input/output alternate function characteristics
(CK, SD, WS).

102/112 DS13259 Rev 7


STM32WB10CC Package information

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of


ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.

7.1 Device marking


Refer to “Reference device marking schematics for STM32 microcontrollers and
microprocessors” (TN1433) available on www.st.com, for the location of pin 1 / ball A1 as
well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.

DS13259 Rev 7 103/112


107
Package information STM32WB10CC

7.2 UFQFPN48 package information


UFQFPN48 is a 48-lead, 7 x 7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 24. UFQFPN48 outline


Pin 1 identifier
laser marking area
D

A
E E
T Seating
plane
ddd A1
e b

Detail Y
D
Y

Exposed pad
area D2
1

L
48
C 0.500x45°
pin1 corner R 0.125 typ.

E2 Detail Z

48
Z
A0B9_ME_V3

1. Drawing is not to scale.


2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package, it must be electrically connected to
the PCB ground.

104/112 DS13259 Rev 7


STM32WB10CC Package information

Table 79. UFQFPN48 mechanical data


millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236


A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.

Figure 25. UFQFPN48 recommended footprint

7.30

6.20

48 37

1 36

0.20 5.60

7.30
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80
A0B9_FP_V2

1. Dimensions are expressed in millimeters.

DS13259 Rev 7 105/112


107
Package information STM32WB10CC

7.3 Thermal characteristics


The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 24: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated
using the equation:
TJ max = TA max + (PD max x ΘJA)
where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C / W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max),
• PINT max is the product of IDD and VDD, expressed in Watt. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins:
• PI/O max = Σ (VOL × IOL) + Σ ((VDD – VOH) × IOH)
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Note: As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the
chip power consumption.

Table 80. Package thermal characteristics


Symbol Parameter Value Unit

Thermal resistance junction-ambient


ΘJA 27.7
UFQFPN48 - 7 mm x 7 mm
Thermal resistance junction-board
ΘJB 12.0 °C / W
UFQFPN48 - 7 mm x 7 mm
Thermal resistance junction-case
ΘJC 1.6
UFQFPN48 - 7 mm x 7 mm

7.3.1 Reference document


JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org

7.3.2 Selecting the product temperature range


When ordering the microcontroller, the temperature range is specified in the information
scheme shown in Section 8.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and to a specific maximum junction temperature.
As applications do not commonly use the device at maximum dissipation, it is useful to
calculate the exact power consumption and junction temperature to determine the
temperature range that best suits the application.
The following example show how to calculate the temperature range needed for a given
application.

106/112 DS13259 Rev 7


STM32WB10CC Package information

Example: High-performance application


Assuming the following application conditions:
Maximum ambient temperature TA max = 82 °C (measured according to JESD51-2),
IDD max = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at
low level with IOL = 8 mA, VOL = 0.4 V and maximum 8 I/Os used at the same time in
output at low level with IOL = 20 mA, VOL= 1.3 V
PINT max = 50 mA × 3.5 V = 175 mW
PIO max = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINT max = 175 mW and PIO max = 272 mW
PD max = 175 + 272 = 447 mW
Using the values obtained in Table 80 TJ max is calculated as follows:
– For UFQFPN48, 27.7 °C / W
TJ max = 82 °C + (27.7 °C / W × 447 mW) = 82 °C + 12 °C = 94 °C
This is within the range of the suffix 5 version parts (–10 < TJ < 105 °C), see Section 8.

DS13259 Rev 7 107/112


107
Ordering information STM32WB10CC

8 Ordering information

Example: STM32 WB 10 C C U 5 TR

Device family
STM32 = Arm® based 32-bit microcontroller

Product type
WB = Wireless Bluetooth®

Device subfamily
10 = Die 1, full set of features

Pin count
C = 48 pins

Flash memory size


C = 320 Kbytes

Package
U = UFQFPN48 7 x 7 mm

Temperature range
5 = Industrial temperature range, -10 to 85 °C (105 °C junction)

Packing
TR = tape and reel
xxx = programmed parts

For a list of available options (such as speed or package), or for further information on any
aspect of this device, contact the nearest ST sales office.

108/112 DS13259 Rev 7


STM32WB10CC Important security notice

9 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

DS13259 Rev 7 109/112


109
Revision history STM32WB10CC

10 Revision history

Table 81. Document revision history


Date Revision Changes

17-Feb-2021 1 Initial release.


Updated Features, Section 1: Introduction, Section 2: Description,
Section 3.6: RF subsystem, Section 3.6.2: Bluetooth Low Energy general
description, Section 3.7.4: Low-power modes, Section 3.10: Clocks and
startup, Section 6.1.6: Power supply scheme and Section 6.3.9: External
clock source characteristics.
Updated Table 1: STM32WB10CC device features and peripheral counts,
Table 5: Functionalities depending on system operating mode, Table 6:
STM32WB10CC modes overview, Table 19: Main performance at VDD =
3.3 V and its footnote 2, Table 20: General operating conditions,
Table 24: RF BLE power consumption for VDD = 3.3 V, Table 34: Current
10-Jun-2021 2 consumption in Stop 1 mode, Table 35: Current consumption in Stop 0
mode, Table 36: Current consumption in Standby mode, Table 41: Low-
power mode wake-up timings, Table 42: Regulator modes transition
times, Table 45: HSE clock source requirements, Table 46: HSE oscillator
characteristics, Table 52: LSI2 oscillator characteristics and its footnote 3,
Table 61: I/O static characteristics and Table 68: ADC accuracy.
Added Table 43: Wake-up time using USART.
Updated Figure 6: Clock tree, Figure 19: ADC accuracy characteristics,
Figure 20: Typical connection diagram when using the ADC with FT/TT
pins featuring analog switch function and its footnotes.
Minor text edits across the whole document.
Updated Features, Section 3.6.2: Bluetooth Low Energy general
description, Section 3.7.4: Low-power modes, and Section 7.3: Thermal
characteristics.
Updated Table 13: Legend/abbreviations used in the pinout table,
Table 14: STM32WB10CC pin definitions, Table 17: Current
characteristics, Table 19: Main performance at VDD = 3.3 V and its
08-Mar-2022 3 footnote 2, Table 20: General operating conditions, and Table 27:
Embedded internal voltage reference.
Updated footnote of Table 44: HSE crystal requirements and footnote 6 of
Table 61: I/O static characteristics.
Updated Figure 40: UFQFPN48 marking example (package top view).
Minor text edits across the whole document.
Updated document title, Features, Section 2: Description, Section 3.6:
RF subsystem, and Section 3.6.2: Bluetooth Low Energy general
description.
Added footnote to Table 46: HSE oscillator characteristics.
Updated Table 1: STM32WB10CC device features and peripheral counts
07-Jun-2022 4 and Table 57: EMI characteristics for fHSE / fCPUM4, fCPUM0 = 32 MHz
/ 64 MHz, 32 MHz.
Added Section 9: Important security notice.
Updated Figure 21: SPI timing diagram - Slave mode and CPHA = 0 and
Figure 22: SPI timing diagram - Slave mode and CPHA = 1.
Minor text edits across the whole document.

110/112 DS13259 Rev 7


STM32WB10CC Revision history

Table 81. Document revision history (continued)


Date Revision Changes

Updated Features and I/O system current consumption.


Updated Table 5: Functionalities depending on system operating mode.
24-Jan-2023 5 Added footnote 7 to Table 61: I/O static characteristics.
Updated footnote 1 of Table 63: I/O AC characteristics.
Minor text edits across the whole document.
Updated document title, Features, Section 2: Description, Section 3.6:
RF subsystem, Section 3.6.2: Bluetooth Low Energy general description,
and Section 3.17: Timers and watchdogs.
22-Aug-2023 6 Updated Table 1: STM32WB10CC device features and peripheral counts
and Table 47: Low-speed external user clock characteristics.
Added Section 7.1: Device marking.
Removed former Device marking for UFQFPN48.
Updated Figure 10: Power supply scheme.
21-Nov-2023 7
Added footnote 4 to Table 52: LSI2 oscillator characteristics.

DS13259 Rev 7 111/112


111
STM32WB10CC

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112/112 DS13259 Rev 7

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