STM 32 WB 10 CC
STM 32 WB 10 CC
STM 32 WB 10 CC
Features
• Include ST state-of-the-art patented
technology
• Radio
UFQFPN48
– 2.4 GHz
7 x 7 mm
– RF transceiver supporting Bluetooth® 5.4 solder pad
specification
– RX sensitivity: -95.5 dBm (Bluetooth® Low • Performance benchmark
Energy at 1 Mbps) – 1.25 DMIPS/MHz (Drystone 2.1)
– Programmable output power up to +4 dBm – 223.03 CoreMark® (3.48 CoreMark/MHz at
with 1 dB steps 64 MHz)
– Integrated balun to reduce BOM • Energy benckmark
– Support for 1 Mbps – 318 ULPMark™ CP score
– Support GATT caching
• Supply and reset management
– Support EATT (enhanced ATT)
– Ultra-safe, low-power BOR (brownout
– Dedicated Arm® 32-bit Cortex® M0+ CPU reset) with five selectable thresholds
for real-time Radio layer
– Ultra-low-power POR/PDR
– Accurate RSSI to enable power control
– Programmable voltage detector (PVD)
– Suitable for systems requiring compliance
– VBAT mode with RTC and backup registers
with radio frequency regulations ETSI EN
300 328, EN 300 440, FCC CFR47 Part 15 • Clock sources
and ARIB STD-T66 – 32 MHz crystal oscillator with integrated
– Support for external PA trimming capacitors (Radio and CPU clock)
– Available integrated passive device (IPD) – 32 kHz crystal oscillator for RTC (LSE)
companion chip for optimized matching – Internal low-power 32 kHz RC (LSI1)
solution (MLPF-WB-01E3) – Internal low-drift 32 kHz (stability
• Ultra-low-power platform ±500 ppm) RC (LSI2)
– 2.0 to 3.6 V power supply – Internal multispeed 100 kHz to 48 MHz
– – 10 °C to +85 °C temperature range oscillator, factory-trimmed
– 18 nA shutdown mode – High speed internal 16 MHz factory
trimmed RC (±1%)
– 700 nA Standby mode + RTC + 48 KB
RAM – 1x PLL for system clock, ADC
– Radio: Rx 7.7 mA / Tx at 0 dBm 8.6 mA • Memories
• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, – 320 KB flash memory with sector
adaptive real-time accelerator (ART protection (PCROP) against R/W
Accelerator) allowing 0-wait-state execution operations, enabling radio stack and
from flash memory, frequency up to 64 MHz, application
MPU, 80 DMIPS, and DSP instructions – 48 KB SRAM, including 36 KB with
hardware parity check
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . 14
3.3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.3 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 Boot modes and FW update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.1 RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6.2 Bluetooth Low Energy general description . . . . . . . . . . . . . . . . . . . . . . 18
3.6.3 RF pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6.4 Typical RF application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.2 Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.3 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 35
3.13.2 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 36
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.1 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
List of tables
List of figures
1 Introduction
This document provides the ordering information and mechanical device characteristics of
the STM32WB10CC microcontroller, based on Arm® cores(a). Throughout the whole
document TBD indicates a value to be defined.
This document must be read with the reference manual (RM0478), available from the
STMicroelectronics website www.st.com.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32WB10CC errata sheet (ES0556), available from the STMicroelectronics
website www.st.com.
For information on the Arm® Cortex®-M4 and Cortex®-M0+ cores, refer, respectively, to the
Cortex®-M4 Technical Reference Manual and to the Cortex®-M0+ Technical Reference
Manual, both available on the www.arm.com website.
For information on Bluetooth® refer to www.bluetooth.com.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
2 Description
APB asynchronous
AHB asynchronous
RCC2
CTI
NVIC BLE IP
AHB Lite
LSI2
32 kHz
Cortex-M0+ BLE RF IP
HSE2
32 MHz
WKUP
32 KB SRAM2a
BLE
LSE
RTC2 32 kHz
320 KB Flash
4 KB SRAM2b
shared memory
Arbiter + ART
LSI1
JTAG/SWD
I-WDG 32 kHz
PKA + RAM
TAMP
HSEM
EXTI
AHB Lite
AES2
LPTIM1 TIM1
MS53573V2
3 Functional overview
3.1 Architecture
The STM32WB10CC multiprotocol wireless device embeds a Bluetooth Low Energy RF
subsystem that interfaces with a generic microcontroller subsystem using an Arm® Cortex®-
M4 CPU (called CPU1) on which the host application resides.
The RF subsystem is composed of an RF analog front end, Bluetooth Low Energy block as
well as of a dedicated Arm® Cortex®-M0+ microcontroller (called CPU2), plus proprietary
peripherals. The RF subsystem performs all of the Bluetooth Low Energy stack, reducing
the interaction with the CPU1 to high level exchanges.
Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU
(CPU1):
• Flash memories
• SRAM1, SRAM2a, and SRAM2b (all can be retained in Standby mode)
• Security peripherals (RNG, PKA)
• Clock RCC
• Power control (PWR)
The communication and the sharing of peripherals between the RF subsystem and the
Cortex®-M4 CPU is performed through a dedicated inter processor communication
controller (IPCC) and semaphore mechanism (HSEM).
3.3 Memories
Table 2. Access status vs. readout protection level and execution modes
Debug, boot from SRAM or boot
User execution
Protection from system memory (loader)
Area
level
Read Write Erase Read Write Erase
• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 4-Kbyte granularity.
• Proprietary code readout protection (PCROP): two parts of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
Two areas can be selected, with 2-Kbyte granularity. An additional option bit
(PCROP_RDP) makes possible to select if the PCROP area is erased or not when the
RDP protection is changed from Level 1 to Level 0.
A section of the flash memory is secured for the RF subsystem CPU2, and cannot be
accessed by the host CPU1.
The whole nonvolatile memory embeds the error correction code (ECC) feature supporting:
• single error detection and correction
• double error detection
• the address of the ECC fail can be read in the ECC register
The embedded flash memory is shared between CPU1 and CPU2 on a time sharing basis.
A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.
SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the
SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the
host CPU1.
The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock
speeds.
3.6 RF subsystem
The STM32WB10CC embeds an ultra-low power multi-standard radio Bluetooth Low
Energy, compliant with Bluetooth specification 5.4. The Bluetooth Low Energy features
1 Mbps transfer rate, supports multiple roles simultaneously acting at the same time as
Bluetooth Low Energy sensor and hub device, embeds Elliptic Curve Diffie-Hellman (ECDH)
key agreement protocol, thus ensuring a secure connection.
The Bluetooth Low Energy stack runs on an embedded Arm® Cortex®-M0+ core (CPU2).
The stack is stored on the embedded flash memory, which is also shared with the Arm®
Cortex®-M4 (CPU1) application, making it possible in-field stack update.
control
AGC
Timer and Power
AGC
control
RF_TX_
MOD_ RF control
ADC
EXT_PA G
Interrupt BLE BP
Wakeup modulator LNA
filter
BLE
ADC
AHB controller
BLE G
APB demodulator
RF1
Modulator
PLL
PA
See
note
generator
PA ramp
Adjust Adjust
HSE
Trimmed
bias
Max PA
LDO LDO LDO
level
VDD VDDRF
OSC_IN OSC_OUT
32 MHz
Note: UFQFPN48: VSS through exposed pad, and VSSRF pin must be connected to ground plane
MS53574V1
In addition, according to Bluetooth specification 5.4, the Bluetooth Low Energy block
provides:
• Multiple roles simultaneous support
• Master/slave and multiple roles simultaneously
• LE data packet length extension (making it possible to reach 800 kbps at application
level)
• LE privacy 1.2
• LE secure connections
• Flexible Internet connectivity options
The device supports Piconet topology (master with up to eight slaves), Scatternet topology
(master with up to six slaves and dynamically as slave with up to two masters, or master
with up to four slaves and dynamically as slave with up to four masters), and multi slave
topology (slave with up to eight masters).
The device allows the applications to meet the tight peak current requirements imposed by
the use of standard coin cell batteries.
Ultra-low-power sleep modes and very short transition time between operating modes result
in very low average current consumption during real operating conditions, resulting in longer
battery life.
The Bluetooth Low Energy block integrates a full bandpass balun, thus reducing the need
for external components.
The link between the Cortex®-M4 application processor (CPU1) running the application, and
the Bluetooth Low Energy stack running on the dedicated Cortex®-M0+ (CPU2) is
performed through a normalized API, using a dedicated IPCC.
RF1 RF Input/output, must be connected to the antenna through a low-pass matching network
OSC_OUT
32 MHz main oscillator, also used as HSE source
OSC_IN I/O
RF_TX_
External PA transmit control
MOD_EXT_PA
VDDRF VDD Dedicated supply, must be connected to VDD
(1)
VSSRF VSS To be connected to GND
1. The exposed pad must be connected to GND plane for correct RF operation.
OSC_IN
X1 32 MHz
OSC_OUT
VDD
VDDRF
C1
STM32WB VSSRF
Antenna
Lf1
Cf1 Cf2
RF1
Antenna
Lf2 filter
MS53575V1
Note: For more details refer to AN5165 “Development of RF hardware using STM32WB
microcontrollers” available on www.st.com.
During power up/down, the following power sequence requirements must be respected:
• When VDD is below 1 V the other power supply (VDDA), must remain below
VDD + 300 mV
• When VDD is above 1 V all power supplies are independent.
3.6
VDDX(1)
VDD
VBOR0
0.3
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1
During the power down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling
capacitors to be discharged with different time constants during the power down transient
phase.
Note: VDD and VDDRF must be wired together, so they can follow the same voltage sequence.
Level shifter
SysConfig, EXTI,
IO (CPU1, CPU2, RCC, PwrCtrl,
IOs peripherals)
logic LPTIM, USART1
Power Power
switch switch
VSS
VSS VSS
VDD MR
RFR
LPR
VDDRF
RF domain Backup domain
SRAM1,
Radio VBKP12
SRAM2a,
SRAM2b
Power switch
VSSRF
VSS
VSS
(including exposed pad)
Wakeup domain (VDDIO)
VDD HSI, HSE,
Power switch PLL,
VSW LSI1, LSI2,
VBAT IWDG, RF
VSS
ADC
=
VREF+ =
VREF-
VSS
MS53576V2
• Shutdown
This mode achieves the lowest power consumption. The internal regulator is switched
off so that the VCORE domain is powered off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the
Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wake-up, timestamp, tamper).
The system clock after wake-up is 4 MHz, derived from the MSI.
This low-power mode is not selectable for Radio activity.
When the RF subsystem is active, it changes the power state according to its needs (Run,
Stop, Standby). This operation is transparent for the CPU1 host application and managed by
a dedicated HW state machine. At any given time the effective power state reached is the
higher one needed by both the CPU1 and RF sub-system.
Table 5 summarizes the peripheral features over all available modes. Wake-up capability is
detailed in gray cells.
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Sleep
VBAT
Run
Peripheral
- - - -
CPU1 Y - Y - - - - - - - - - -
CPU2 Y - Y - - - - - - - - - -
Radio-system (BLE) Y Y - - Y Y Y Y Y(2) Y(2) - - -
Flash memory Y Y O O R - R - R - R - R
SRAM1 Y O(3) Y O(3) R - R - O(3) - - - -
SRAM2a Y O(3) Y O(3) R - R - O(3) - - - -
(3) (3) (3)
SRAM2b Y O Y O R - R - O - - - -
Backup registers Y Y Y Y R - R - R - R - R
Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - -
Programmable voltage detector
O O O O O O O O - - - - -
(PVD)
DMAx (x=1) O O O O - - - - - - - - -
High speed internal (HSI16) O O O O O(4) - O(4) - - - - - -
High speed external (HSE) O O O O - - - - - - - - -
Low-power sleep
Low-power run
Wake-up capability
Wake-up capability
Wake-up capability
Wake-up capability
Sleep
VBAT
Run
Peripheral
- - - -
Functional overview
Table 6. STM32WB10CC modes overview
Mode Regulator CPU1 Flash SRAM Clocks DMA and Peripherals Wake-up source Consumption(1) Wake-up time
RTC
All other peripherals are
Two I/Os (WKUPx)(8), 0.018 µA w/o RTC
Shutdown OFF No OFF OFF LSE powered off. -
RTC 0.425 µA w/ RTC
I/O configuration can be floating,
pull-up or pull-down(9)
STM32WB10CC
1. Typical current at VDD = 2.4 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C.
2. The flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM.
3. The SRAM1 and SRAM2 clocks can be gated off independently.
4. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem.
STM32WB10CC
5. HSI16 (16 MHz) automatically used by some peripherals.
6. U(S)ART reception is functional in Stop mode, and generates a wake-up interrupt on Start, Address match or Received frame event.
7. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address match.
8. I/Os with wake-up from Standby/Shutdown capability: PA0, PA2.
9. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.
DS13259 Rev 7
Functional overview
29/112
Functional overview STM32WB10CC
Stop 0 / Stop 1
Low-power
Sleep
Run
Low-power run
Stop 0 / Stop 1
Low-power
Sleep
Run
Source Destination Action
CSS
CPU (hard fault)
SRAM (parity error) TIM1 Timer break Y Y Y Y -
Flash memory (ECC error)
PVD
PLL MSI
PLLPCLK
xN /P
/3 PCLKn
PLLQCLK SYSCLK
/Q to RNG to USART1
LSI
HSI16
PLLRCLK LSE
/R
LSE
PCLKn
MS53563V3
A DMAMUX block makes it possible to route any peripheral source to any DMA channel.
The main features of the touch sensing controller are the following:
• Proven and robust surface charge transfer acquisition principle
• Supports up to three capacitive sensing channels
• Up to three capacitive sensing channels can be acquired in parallel offering a very
good response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to three capacitive sensing channels to reduce the
system components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
dead-times. They can also be seen as complete general-purpose timers. The four
independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0 to
100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.17.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
• a 32.768 kHz external crystal (LSE)
• an external resonator or oscillator (LSE)
• one of the internal low power RC oscillators (LSI1 with typical frequency of 32 kHz or
LSI2)
• the high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by one of the LSIs, the RTC is not functional in VBAT mode, but is
functional in all low-power modes except Shutdown mode.
All RTC events (alarm, wake-up timer, timestamp or tamper) can generate an interrupt and
wake-up the device from the low-power modes.
PA15
PA14
PA13
PA12
PA11
VDD
VDD
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 PA10
PC14-OSC32_IN 2 35 VDD
PC15-OSC32_OUT 3 34 VDD
PH3-BOOT0 4 33 VDD
PB8 5 32 VSS
PB9 6 31 VDD
NRST 7
UFQFPN48 30 PE4
VDDA 8 29 PB1
PA0 9 28 PB0
PA1 10 27 AT1
PA2 11 26 AT0
PA3 12 25 OSC_IN
13
14
15
16
17
18
19
20
21
22
23
24
PB2
VDD
RF1
VSSRF
VDDRF
OSC_OUT
PA4
PA5
PA6
PA7
PA8
PA9
MS53577V1
Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
FT 5 V tolerant I/O
RF RF I/O
I/O structure NRST Bidirectional reset pin with weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
function Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 14 are FT_f and FT_fa.
2. The related I/O structures in Table 14 are FT_a, FT_la, FT_fa and TT_a.
3. The analog switch for the TSC function is supplied by VDD.
structure
Notes
Additional
Number
I/O
Alternate functions
Name (function functions
Type
after reset)
1 VBAT S - - - -
(1)
2 PC14-OSC32_IN I/O FT CM4_EVENTOUT OSC32_IN
(1)
3 PC15-OSC32_OUT I/O FT CM4_EVENTOUT OSC32_OUT
4 PH3-BOOT0 I/O FT - LSCO(2) , CM4_EVENTOUT -
TIM1_CH2N, I2C1_SCL, TSC_G7_IO3,
5 PB8 I/O FT_f - -
CM4_EVENTOUT
TIM1_CH3N, I2C1_SDA, TSC_G7_IO4,
6 PB9 I/O FT_f - -
CM4_EVENTOUT
7 NRST(PB11) I/O NRST (3) - -
8 VDDA S - - - -
ADC1_IN5,
9 PA0 I/O FT_a - TIM2_CH1, TIM2_ETR, CM4_EVENTOUT
RTC_TAMP2/WKUP1
TIM2_CH2, I2C1_SMBA, SPI1_SCK,
10 PA1 I/O FT_a - ADC1_IN6
CM4_EVENTOUT
11 PA2 I/O FT_a - LSCO(2), TIM2_CH3, CM4_EVENTOUT ADC1_IN7, WKUP4
12 PA3 I/O FT_a - TIM2_CH4, CM4_EVENTOUT ADC1_IN8
SPI1_NSS (boot), LPTIM2_OUT,
13 PA4 I/O FT_a - ADC1_IN9
CM4_EVENTOUT
TIM2_CH1, TIM2_ETR, SPI1_MOSI,
14 PA5 I/O FT_a - SPI1_SCK (boot), LPTIM2_ETR, ADC1_IN10
CM4_EVENTOUT
TIM1_BKIN, SPI1_MISO (boot),
15 PA6 I/O FT_a - ADC1_IN11
CM4_EVENTOUT
TIM1_CH1N, SPI1_MOSI (boot),
16 PA7 I/O FT_fa - ADC1_IN2
CM4_EVENTOUT
MCO, TIM1_CH1, USART1_CK, LPTIM2_OUT,
17 PA8 I/O FT_a - ADC1_IN3
CM4_EVENTOUT
TIM1_CH2, I2C1_SCL, USART1_TX (boot),
18 PA9 I/O FT_fa - ADC1_IN4
CM4_EVENTOUT
RTC_OUT, LPTIM1_OUT, SPI1_NSS,
19 PB2 I/O FT_a - -
CM4_EVENTOUT
20 VDD S - - - -
(4)
21 RF1 I/O RF - - -
22 VSSRF S - - - -
23 VDDRF S - - - -
(5)
24 OSC_OUT O RF - -
structure
Notes
Additional
Number
I/O
Alternate functions
Name (function functions
Type
after reset)
25 OSC_IN I RF - - -
26 AT0 I/O RF (6)
- -
(6)
27 AT1 I/O RF - -
(7)
28 PB0 I/O TT RF_TX_MOD_EXT_PA, CM4_EVENTOUT -
29 PB1 I/O TT (7)
LPTIM2_IN1, CM4_EVENTOUT -
30 PE4 I/O FT - CM4_EVENTOUT -
31 VDD S - - - -
32 VSS S - - - -
33 VDD S - - - -
34 VDD S - - - -
35 VDD S - - - -
TIM1_CH3, I2C1_SDA, USART1_RX (boot),
36 PA10 I/O FT_f - -
TSC_G7_IO2, CM4_EVENTOUT
TIM1_CH4, TIM1_BKIN2, SPI1_MISO,
37 PA11 I/O FT - -
USART1_CTS, CM4_EVENTOUT
TIM1_ETR, SPI1_MOSI, USART1_RTS,
38 PA12 I/O FT - -
CM4_EVENTOUT
JTMS-SWDIO, SPI1_MOSI, TSC_G7_IO1,
39 PA13 I/O FT - -
CM4_EVENTOUT
40 VDD S - - - -
1. PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited current (3 mA), the use of PC14
and PC15 GPIOs in output mode is limited:
- the speed must not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as current sources (e.g. to drive an LED).
After a Backup domain power-up PC14 and PC15 operate as GPIOs. Their function depends on the content of the RTC
registers not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup domain and RTC
register description in RM0478, available on www.st.com.
2. The clock on LSCO is available in Run and Stop modes, and on PA2 in Standby and Shutdown modes.
3. NRST pin is FT-tolerant if configured as PB11 GPIO.
4. RF pin, use the nominal PCB layout.
5. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165 available on www.st.com).
6. Reserved for production, must be kept unconnected.
7. High frequency (above 32 kHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0
and 1) during RF operation.
8. After reset this pin is configured as JTAG/SW debug alternate function, and the internal pull-up on PA15, PA13 and PB4
pins and the internal pull-down on PA14 pin are activated.
9. PB5 pin is configured as input with pull-up active under reset if NRST pin is active (external or internal reset).
TIM2_ CM4_
PA2 LSCO
CH3
- - - - - - - - -
EVENTOUT
TIM2_ CM4_
PA3 -
CH4
- - - - - - - - -
EVENTOUT
LPTIM2_ CM4_
PA4 - - - - SPI1_NSS - - - -
OUT EVENTOUT
TIM1_ CM4_
PA6 -
BKIN
- - SPI1_MISO - - - - -
EVENTOUT
TIM1_ CM4_
PA7 -
CH1N
- - - SPI1_MOSI - - - - -
EVENTOUT
A
TIM1_ USART1_ LPTIM2_ CM4_
PA8 MCO
CH1
- - - - -
CK
- -
OUT EVENTOUT
RF_TX_ CM4_
PB0 - - - - - -
MOD_EXT_PA
- - - -
EVENTOUT
LPTIM2_ CM4_
PB1 - - - - - - - - - -
IN1 EVENTOUT
JTDO-
TIM2_ USART1_ CM4_
PB3 TRACE
CH2
- - - SPI1_SCK -
RTS_
- - -
EVENTOUT
SWO
CM4_
PC14 - - - - - - - - - - -
EVENTOUT
C
CM4_
PC15 - - - - - - - - - - -
EVENTOUT
CM4_
E PE4 - - - - - - - - - - -
EVENTOUT
CM4_
H PH3 LSCO - - - - - - - - - -
EVENTOUT
STM32WB10CC
STM32WB10CC Memory mapping
5 Memory mapping
The STM32WB10CC devices feature a single physical address space that can be accessed
by the application processor and by the RF subsystem.
A part of the Flash memory and of the SRAM2a and SRAM2b is made secure, exclusively
accessible by the CPU2, protected against execution, read and write from CPU1 and DMA.
In case of shared resources the SW has to implement arbitration mechanism to avoid
access conflicts. This happens for peripherals Reset and clock controller (RCC), Power
controller (PWC), EXTI and Flash memory interface, and can be implemented using the
built-in semaphore block (HSEM).
By default the RF subsystem and the CPU2 operate in secure mode. This implies that part
of the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and
by the CPU2. In this case the Host processor (CPU1) has no access to these resources.
The detailed memory map and the peripheral mapping of the STM32WB10CC can be found
in the reference manual RM0478.
6 Electrical characteristics
MS19210V1 MS19211V1
VBAT
Backup circuitry
1.55 V to 3.6 V (LSE, RTC and
backup registers)
Power switch
VDD VCORE
n x VDD
Regulator
VDDIO1
OUT
Kernel logic
Level shifter
IO (CPU, digital
GPIOs
n x 100 nF + 1 x 4.7 μF logic
IN and memories
VSS
VDDA
VDDA
10 nF + 1 μF VREF+
ADC
VREF-
VSS
VDDA
VDDRF
100 nF
+ 100 pF VSSRF Radio
MS53513V3
Exposed pad VSS
To all modules
1. The value of L1 depends upon the frequency, as indicated in Table 4: Typical external components.
Caution: Each power supply pair (e.g. VDD / VSS, VDDRF / VSSRF) must be decoupled with filtering
ceramic capacitors as shown in Figure 10. These capacitors must be placed as close as
possible to (or below) the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
IDDRF
VDDRF
IDDVBAT
VBAT
IDD
VDD
IDDA
VDDA
MSv63021V1
∑IVDD Total current into sum of all VDD power lines (source)(1) 130
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 130
IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk by any I/O and control pin except FT_f 20
IIO(PIN) Output current sunk by any FT_f pin 20
mA
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins(2) 100
∑IIO(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 100
Injected current on FT_xxx, TT_xx, NRST and B pins, except PB0 and PB1 –5 / +0(4)
IINJ(PIN)(3)
Injected current on PB0 and PB1 -5/0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) 25
1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS, VSSRF) pins must always be connected to the external power
supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count packages.
3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer also to Table 16: Voltage
characteristics for the maximum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
Pband Output power variation over the band Tx = 0 dBm - Typical -0.5 - 0.4 dB
fd Frequency drift Bluetooth® Low Energy: ±50 kHz -50 - +50 kHz
PER <30.8%
Prx_max Maximum input signal -4
Bluetooth® Low Energy: min -10 dBm
PER <30.8%
Psens(1) High sensitivity mode -95.5
Bluetooth® Low Energy: max -70 dBm dBm
Adj ≥ 5 MHz
-46
Bluetooth® Low Energy: -27 dB
Adj ≤ -5 MHz
-48
Bluetooth® Low Energy:-27 dB
Adj = 4 MHz
-46
Bluetooth® Low Energy:-27 dB
Adj = -4 MHz
-33
Bluetooth® Low Energy:-15 dB
Adj = 3 MHz
C/I Adjacent channel interference -46
Bluetooth® Low Energy:-27 dB dB
Adj = 2 MHz
-39
Bluetooth® Low Energy:-17 dB
Adj = -2 MHz
-35
Bluetooth® Low Energy:-15 dB
Adj = 1 MHz
-2
Bluetooth® Low Energy: 15 dB
Adj = -1 MHz
2
Bluetooth® Low Energy: 15 dB
C/Image Image rejection (Fimage = -3 MHz) Bluetooth® Low Energy: -9 dB -28
|f2-f1| = 3 MHz
-36
Bluetooth® Low Energy: -50 dBm
|f2-f1| = 4 MHz
P_IMD Intermodulation -35
Bluetooth® Low Energy: -50 dBm
|f2-f1| = 5 MHz
-33
Bluetooth® Low Energy:-50 dBm
30 to 2000 MHz
-2 dBm
Bluetooth® Low Energy: -30 dBm
2003 to 2399 MHz
-8
Bluetooth® Low Energy: -35 dBm
P_OBB Out of band blocking
2484 to 2997 MHz
-4
Bluetooth® Low Energy: -35 dBm
3 to 12.75 GHz
6
Bluetooth® Low Energy: -30 dBm
1. With ideal TX.
tRSTTEMPO(2) Reset temporization after BOR0 is detected VDD rising - 250 400 μs
Rising edge 1.62 1.66 1.70
VBOR0(2) Brown-out reset threshold 0
Falling edge 1.60 1.64 1.69
Rising edge 2.06 2.10 2.14
VBOR1 Brown-out reset threshold 1
Falling edge 1.96 2.00 2.04
Rising edge 2.26 2.31 2.35
VBOR2 Brown-out reset threshold 2
Falling edge 2.16 2.20 2.24
Rising edge 2.56 2.61 2.66
VBOR3 Brown-out reset threshold 3
Falling edge 2.47 2.52 2.57
V
Rising edge 2.85 2.90 2.95
VBOR4 Brown-out reset threshold 4
Falling edge 2.76 2.81 2.86
Rising edge 2.10 2.15 2.19
VPVD0 Programmable voltage detector threshold 0
Falling edge 2.00 2.05 2.10
Rising edge 2.26 2.31 2.36
VPVD1 PVD threshold 1
Falling edge 2.15 2.20 2.25
Rising edge 2.41 2.46 2.51
VPVD2 PVD threshold 2
Falling edge 2.31 2.36 2.41
Table 26. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit
VREFINT Internal reference voltage –10 °C < TJ < +105 °C 1.182 1.212 1.232 V
ADC sampling time when reading
tS_vrefint (1) - 4(2) - -
the internal reference voltage
µs
Start time of reference voltage
tstart_vrefint - - 8 12(2)
buffer when ADC is enabled
VREFINT buffer consumption from
IDD(VREFINTBUF) - - 12.5 20(2) µA
VDD when converted by ADC
Internal reference voltage spread
∆VREFINT VDD = 3 V - 5 7.5(2) mV
over the temperature range
TCoeff Temperature coefficient –10 °C < TJ < +105 °C - 30 50(2) ppm/°C
ACoeff Long term stability 1000 hours, TJ = 25 °C - 300 1000(2) ppm
VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V
VREFINT_DIV1 1/4 reference voltage 24 25 26
%
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Specified by design, not tested in production.
1.235
1.230
1.225
1.220
VREFINT (V)
1.215
1.210
1.205
1.200
1.195
1.190
1.185
o
40 -20 0 20 40 60 80 100 T ( C)
120 °C
Mean Min Max
MSv63022V1
Table 28. Current consumption in Run and Low-power run modes, code with data processing
running from flash memory, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V
Typ Max(1)
Symbol Parameter Conditions fHCLK Unit
25 °C 55 °C 85 °C 25 °C 85 °C
Table 29. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1, VDD = 3.3 V
Typ Max(1)
Symbol Parameter Conditions- fHCLK Unit
25 °C 55 °C 85 °C 25 °C 85 °C
Table 30. Typical current consumption in Run and Low-power run modes, with different codes
running from flash memory, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V
Typ Typ
Symbol Parameter Conditions Code Unit Unit
25 °C 25 °C
Coremark 6.20 97
Supply current
IDD(Run) fHCLK = 64 MHz Dhrystone 2.1 6.75 mA 105 µA/MHz
in Run mode
Fibonacci 6.05 95
While(1) 5.85 91
Table 31. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1, VDD = 3.3 V
Typ Typ
Symbol Parameter Conditions Code Unit Unit
25 °C 25 °C
While(1) 6.20 98
Table 32. Current consumption in Sleep and Low-power sleep modes, flash memory ON
Conditions Typ Max(1)
Symbol Parameter Unit
All peripherals disabled fHCLK 25 °C 55 °C 85 °C 25 °C 85 °C
Supply fHCLK = fHSI16 up to 16 MHz 64 MHz 1.80 1.85 1.85 2.04 2.20
IDD current in included,
32 MHz 0.990 1.00 1.05 0.980 1.22
(Sleep) Sleep fHCLK = fHSE up to 32 MHz
mode, fHSI16 + PLL ON above 32 MHz 16 MHz 0.605 0.610 0.640 0.690 0.910
2 MHz 0.055 0.065 0.095 0.080 0.240 mA
Supply
IDD current in 1 MHz 0.036 0.047 0.0765 0.060 0.210
f =f
(LPSleep) Low-power HCLK MSI 400 kHz 0.022 0.033 0.0625 0.030 0.180
sleep mode
100 kHz 0.016 0.0265 0.057 0.030 0.170
1. Evaluated by characterization (mean ± 4 σ), not tested in production, unless otherwise specified.
Table 33. Current consumption in Low-power sleep modes, flash memory in Power down
Conditions Typ Max(1)
Symbol Parameter Unit
All peripherals disabled fHCLK 25 °C 55 °C 85 °C 25 °C 85 °C
Note: For information about the trimming of the oscillator refer to AN5165 “Development of RF
hardware using STM32WB microcontrollers”, available on www.st.com.
LSEDRV[1:0] = 00
- 250 -
Low drive capability
LSEDRV[1:0] = 01
- 315 -
Medium low drive capability
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10
- 500 -
Medium high drive capability
LSEDRV[1:0] = 11
- 630 -
High drive capability
LSEDRV[1:0] = 00
- - 0.50
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Medium low drive capability
Gmcritmax Maximum critical crystal gm µA/V
LSEDRV[1:0] = 10
- - 1.70
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.70
High drive capability
Note: For information on selecting the crystal refer to application note AN2867 “Oscillator design
guide for STM8S, STM8A and STM32 microcontrollers” available from www.st.com.
OSC32_IN fLSE
OSC32_OUT
CL2
MS30253V2
Note: No external resistors are required between OSC32_IN and OSC32_OUT, and it is forbidden
to add one.
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics detailed in Section 6.3.16.
The recommend clock input waveform is shown in Figure 14.
tw(LSEH)
VLSEH
90%
10%
VLSEL
tr(LSE) t
tf(LSE) tw(LSEL)
TLSE
MS19215V2
MHz
16.4
+2%
16.3
+1.5%
16.2 +1%
16.1
16
15.9
-1%
15.8
-1.5%
15.7
-2%
15.6
0 20 40 60 80 100
min mean max
MSv63023V1
VDD =
-1.2 -
2.0 to 3.6 V
Range 0 to 3 0.5
VDD =
-0.5 -
2.4 to 3.6 V
Range 0 - - 0.6 1
Range 1 - - 0.8 1.2
Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
MSI oscillator Range 5 - - 6.5 9
MSI and
IDD(MSI)(4) power µA
PLL mode Range 6 - - 11 15
consumption
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190
1. Evaluated by characterization, not tested in production.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Specified by design, not tested in production.
prevent the occurrence of unrecoverable errors (see AN1015 “Software techniques for
improving microcontrollers EMC performance”, available on www.st.com).
Table 57. EMI characteristics for fHSE / fCPUM4, fCPUM0 = 32 MHz / 64 MHz, 32 MHz
Monitored
Symbol Parameter Conditions Peripheral ON Unit
frequency band
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• a supply overvoltage is applied to each power supply pin
• a current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
I/O input
- - 0.3 x VDD
low level voltage(1)
VIL
I/O input
0.39 x VDD - 0.06
low level voltage(1)
V
I/O input
0.7 x VDD - -
high level voltage(1) 2.0 V < VDD < 3.6 V
VIH
I/O input
0.49 x VDD + 0.26 - -
high level voltage(1)
TT_xx, FT_xxx
Vhys and NRST I/O - 200 - mV
input hysteresis
0 ≤ VIN ≤ Max(VDDXXX)(2) - - ±100
Max(VDDXXX) ≤ VIN ≤
FT_xx - - 650
Max(VDDXXX) +1 V(1)(2)(3)
input leakage current
Max(VDDXXX) +1 V < VIN ≤
Ilkg - - 200(6) nA
5.5 V(1)(2)(3)(4)(5)
VIN ≤ Max(VDDXXX)(2) - - ±150
TT_xx
input leakage current Max(VDDXXX) ≤ VIN < - - 2000
3.6 V(2)
Weak pull-up
RPU VIN = VSS 25 40 55
equivalent resistor(1)
kΩ
Weak pull-down
RPD VIN = VDD 25 40 55
equivalent resistor(1)
I/O pin
CIO - - 5 - pF
capacitance(7)
1. Specified by design, not tested in production.
2. Represents the pad leakage of the I/O itself. The total product pad leakage is given by
ITotal_Ileak_max = 10 μA + number of I/Os where VIN is applied on the pad x Ilkg(Max).
3. Max(VDDXXX) is the maximum value among all the I/O supplies.
4. VIN must be lower than [Max(VDDXXX) + 3.6 V].
5. Refer to Figure 17: I/O input characteristics.
6. To sustain a voltage higher than min(VDD, VDDA) + 0.3 V, the internal pull-up and pull-down resistors must be disabled. All
FT_xx IOs.
7. RF I/O structure excluded.
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
in Figure 17 .
2.5
0.5
0
2 2.5 3 3.5
MSv63025V1
VOL(2) Output low level voltage for an I/O pin CMOS port(3) - 0.4
|IIO| = 8 mA
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V VDD - 0.4 -
VOL(2) Output low level voltage for an I/O pin TTL port(3) - 0.4
|IIO| = 8 mA
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V 2.4 -
VOL(2) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V VDD - 1.3 - V
VOL(2) Output low level voltage for an I/O pin |IIO| = 4 mA - 0.4
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.0 V VDD - 0.45 -
|IIO| = 20 mA
- 0.4
Output low level voltage for an FT I/O VDD ≥ 2.7 V
VOLFM+(2)
pin in FM+ mode (FT I/O with “f” option) |I | = 10 mA
IO - 0.4
VDD ≥ 2.0 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 16: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports
and control pins) must always respect the absolute maximum ratings Σ IIO.
2. Specified by design, not tested in production.
3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Table 63.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 20: General
operating conditions.
NRST input
VIL(NRST) - - - 0.3 x VDD
low level voltage
V
NRST input
VIH(NRST) - 0.7 x VDD - -
high level voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up
RPU VIN = VSS 25 40 55 kΩ
equivalent resistor(2)
NRST input
VF(NRST) - - - 70
filtered pulse
ns
NRST input
VNF(NRST) 2.0 V ≤ VDD ≤ 3.6 V 350 - -
not filtered pulse
1. Specified by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10%).
External
reset circuit(1) VDD
RPU
NRST(2) Internal reset
Filter
0.1 μF(3)
MS19878V3
CKMODE = 00 2 - 3
1.5 43 50
3.5 100 680
7.5 214 2200
12.5 357 4700
12 bits
19.5 557 8200
39.5 1129 15000
79.5 2271 33000
160.5 4586 50000
1.5 43 68
3.5 100 820
7.5 214 3300
12.5 357 5600
10 bits
19.5 557 10000
39.5 1129 22000
79.5 2271 39000
160.5 4586 50000
1.5 43 82
3.5 100 1500
7.5 214 3900
12.5 357 6800
8 bits
19.5 557 12000
39.5 1129 27000
79.5 2271 50000
160.5 4586 50000
1.5 43 390
3.5 100 2200
7.5 214 5600
12.5 357 10000
6 bits
19.5 557 15000
39.5 1129 33000
79.5 2271 50000
160.5 4586 50000
1. Specified by design, not tested in production.
2. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and
disabled when VDDA ≥ 2.4 V.
VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA
MSv19880V6
VDDA(4) VREF+(4)
MSv67871V3
1. Refer to Table 66: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 61: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value downgrades the conversion accuracy. To remedy this fADC must be reduced.
3. Refer to Table 61: I/O static characteristics for the values of Ilkg.
4. Refer to Figure 10: Power supply scheme.
VBRS = 0 - 5 -
RBC Battery charging resistor kΩ
VBRS = 1 - 1.5 -
- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 64 MHz 15.625 - ns
/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock vs. the LSI clock, hence there is always a full RC
period of uncertainty.
Standard-mode - 2
Analog filter ON, DNF = 0 8
I2CCLK Fast-mode
f(I2CCLK) Analog filter OFF, DNF = 1 9 MHz
frequency
Analog filter ON, DNF = 0 17
Fast-mode Plus
Analog filter OFF, DNF = 1 16
The I2C timings requirements are Specified by design, not tested in production when the
I2C peripheral is properly configured (refer to the reference manual RM0478).
The SDA and SCL I/O requirements are met with the following restriction: the SDA and SCL
I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present. The 20 mA output drive
requirement in Fast-mode Plus is supported partially.
This limits the maximum load Cload supported in Fast-mode Plus, given by these formulas:
• tr(SDA/SCL) = 0.8473 x Rp x Cload
• Rp(min) = [VDD - VOL(max)] / IOL(max)
where Rp is the I2C lines pull-up. Refer to Section 6.3.16 for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter, refer to Table 75 for its characteristics.
SPI characteristics
Unless otherwise specified, the parameters given in Table 76 are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 20: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 x VDD
Refer to Section 6.3.16 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).
Master mode
- - 32
2.0 < VDD < 3.6 V
Slave receiver mode
- - 32
fSCK 2.0 < VDD < 3.6 V
SPI clock frequency MHz
1/tc(SCK) Slave mode transmitter/full duplex
- - 32(2)
2.7 < VDD < 3.6 V
Slave mode transmitter/full duplex
- - 24(2)
2.0 < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4 x TPCLK - -
th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2 x TPCLK - -
-
tw(SCKH)
SCK high and low time Master mode TPCLK - 1.5 TPCLK TPCLK + 1
tw(SCKL)
tsu(MI) Master mode 6.5 - -
Data input setup time
tsu(SI) Slave mode 1.5 - -
th(MI) Master mode 4.5 - -
Data input hold time
th(SI) Slave mode 1.5 - -
ta(SO) Data output access time 9.0 - 34
Slave mode
tdis(SO) Data output disable time 9.0 - 16 ns
Slave mode 2.7 < VDD < 3.6 V - 10.5 13.0
tv(SO)
Data output valid time Slave mode 2.0 < VDD < 3.6 V - 10.5 20.5
tv(MO) Master mode (after enable edge) - 2.5 3.0
th(SO) Slave mode (after enable edge) 8.0 - -
Data output hold time
th(MO) Master mode (after enable edge) 1.0 - -
1. Evaluated by characterization, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.
NSS input
tc(SCK) th(NSS)
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MSv41658V1
NSS input
tc(SCK)
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MSv41659V1
1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.
High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(MO) th(MO)
ai14136c
1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.
Refer to Section 6.3.16 for more details on the input/output alternate function characteristics
(CK, SD, WS).
7 Package information
A
E E
T Seating
plane
ddd A1
e b
Detail Y
D
Y
Exposed pad
area D2
1
L
48
C 0.500x45°
pin1 corner R 0.125 typ.
E2 Detail Z
48
Z
A0B9_ME_V3
7.30
6.20
48 37
1 36
0.20 5.60
7.30
5.80
6.20
5.60
0.30
12 25
13 24
0.50 0.75
0.55
5.80
A0B9_FP_V2
8 Ordering information
Example: STM32 WB 10 C C U 5 TR
Device family
STM32 = Arm® based 32-bit microcontroller
Product type
WB = Wireless Bluetooth®
Device subfamily
10 = Die 1, full set of features
Pin count
C = 48 pins
Package
U = UFQFPN48 7 x 7 mm
Temperature range
5 = Industrial temperature range, -10 to 85 °C (105 °C junction)
Packing
TR = tape and reel
xxx = programmed parts
For a list of available options (such as speed or package), or for further information on any
aspect of this device, contact the nearest ST sales office.
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
10 Revision history
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other
product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.