Lecture 31: Jfets As Variable Resistors: Automatic Gain Control

Whites, EE 322 Lecture 31 Page 1 of 7
Lecture 31: JFETs as Variable Resistors

One nice feature of the NorCal 40A is the Automatic Gain
Control (AGC). This circuit keeps the audio output at a
reasonably constant level as you tune across the band and
receive very strong or weak signals.
A key part of the AGC is the pair of JFETs Q2 and Q3. These
are simply J309s, as we used for the Buffer Amplifier (Q5) and
the VFO (Q8).
As well see, Q2 and Q3 in the AGC simply act as voltage

controlled variable resistors! For the remainder of this lecture,
we will discuss this valuable behavior of JFETs, while in the
next lecture we will discuss the details behind the AGC.
JFET with an Open Channel (Triode Region)
Recall from our previous discussion on JFETs in Lecture 21 that

an n-type JFET can be physically approximated by the geometry
shown in the figure below.
The JFET has a negative Vgs which increases the depletion

regions (and decreases the channel width) as Vgs is made more
negative.
2017 Keith W. Whites

D
Depletion
regions
Ids
G G Vds
p p
(small)
n
Vgs
Current Ids will flow from drain to source. The amount of current
(at a given Vds) depends on the channel resistance, rds.
As Vgs becomes more negative, the depletion regions grow wider

and the channel narrows. Consequently, the channel resistance
rds increases.
Assuming Vds is small enough, this behavior can be represented

by straight lines of varying slope in a characteristic plot of the
JFET transistor:
Id
Vgs=0
Vgs=-1
Vgs=-2
Vgs=Vc
Vds (small)
As Vgs becomes more negative, eventually the two depletion

regions combine and the channel is depleted of all charge
carriers (e- for n channel) and no current will flow. This
particular Vgs is the JFET pinch off (or cut off) voltage Vc. It is a
negative number for n-channel JFETs.
We can view this effect in a JFET as a voltage controlled

resistance (VCR).
Saturated JFETs
For completeness, well quickly mention what happens to the

channel as Vds becomes large, though this is not the regime in
which Q2 and Q3 operate in the NorCal 40A.
As Vds increases, Vgs remains constant while the reverse bias

voltage of each pn junction will increase as we move up the
channel. This will give a tapered shape to the depletion region:
D
n
E E
G G
p p Vds
Ids Vgs
The channel becomes pinched off at the drain end when

Vgd Vc
However, current still flows in the channel because charge

carriers can drift through this relatively small depletion region.
Note that this pinch off is not the same as the JFET being
completely pinched off so that no current can flow. Here, pinch
off is occurring only at the drain end of the device.
Also, notice that as Vds increases from this pinched off state,
there will be little change in Id! The maximum Id occurs when
Vgs = 0 and is defined as Idss, the drain-to-source current with the
gate shorted. There is maximum Id in this case because with Vgs
= 0, the channel is depleted only near the drain end.
As Vgs (< 0) varies, a larger region of the channel becomes

depleted. This implies rds increases, which implies a smaller Id.
From this behavior, we can generate a family of characteristic
curves as shown in Fig. 13.4:
When the JFET is biased with a large Vds and Vc Vgs 0 , it

will operate in the so-called active (or saturation) region.
Linear or Triode Region of the JFET
In the Automatic Gain Control (AGC) circuit of the NorCal

40A, the JFETs Q2 and Q3 are operated not in the active (i.e.,
the saturation) region. Rather, they are operated in the JFET
linear region (also called the triode region or VCR region). In
this linear region shown above in Fig. 13.4, the drain current is
expressed as
2I Vds
I d Vds dss2 gs
V Vc [A] (13.12)
c
V 2
For small Vds [ 2 Vgs Vc ], as is the case in the linear region,
2 I dss
I d Vds 2 Vgs Vc [A] (1)
c
V
By definition, the channel resistance rds is computed as

V
rds ds [] (2)
I d V small
ds
Using (1) in (2) we find for small Vds that

1
I
rds 2 dss2 Vgs Vc
1
[] (3)
cV G13.13
Plots of these two quantities in (3) are shown in Fig. 13.5:

JFETs in the AGC
So how are the JFETs applied as variable controlled resistors in

the NorCal 40A? Fig. 13.9 shows them as the AGC attenuators:
More specifically, consider the Q2 circuit connected to U3:

C20 charges to VC20 Vs through Q2 and the internal 50-k

resistor at pin 2 of U3. Vd will be slightly less than Vs because of
the Q2 channel resistance. Because of this, Vds is small, which
implies Q2 operates in the triode region. The VCR control
voltage is Vgs.
Here is an equivalent model for this Q2 circuit:
A similar model applies to the Q3 circuit.
Well see in the next lecture that the AGC will vary rds in
response to the output voltage at the speaker.

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Whites, EE 322 Lecture 31 Page 1 of 7

Lecture 31: JFETs as Variable Resistors

As well see, Q2 and Q3 in the AGC simply act as voltage

JFET with an Open Channel (Triode Region)

Recall from our previous discussion on JFETs in Lecture 21 that

The JFET has a negative Vgs which increases the depletion

2017 Keith W. Whites

As Vgs becomes more negative, the depletion regions grow wider

Assuming Vds is small enough, this behavior can be represented

As Vgs becomes more negative, eventually the two depletion

We can view this effect in a JFET as a voltage controlled

For completeness, well quickly mention what happens to the

As Vds increases, Vgs remains constant while the reverse bias

The channel becomes pinched off at the drain end when

However, current still flows in the channel because charge

As Vgs (< 0) varies, a larger region of the channel becomes

When the JFET is biased with a large Vds and Vc Vgs 0 , it

Linear or Triode Region of the JFET

In the Automatic Gain Control (AGC) circuit of the NorCal

By definition, the channel resistance rds is computed as

Using (1) in (2) we find for small Vds that

Plots of these two quantities in (3) are shown in Fig. 13.5:

JFETs in the AGC

So how are the JFETs applied as variable controlled resistors in

More specifically, consider the Q2 circuit connected to U3:

C20 charges to VC20 Vs through Q2 and the internal 50-k

Here is an equivalent model for this Q2 circuit:

A similar model applies to the Q3 circuit.

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