a AN-392

APPLICATION NOTE
ONE TECHNOLOGY WAY • P.O. BOX 9106 • NORWOOD, MASSACHUSETTS 02062-9106 • 617/329-4700

Circuit Design and Applications of the ADM663A/ADM666A

Micropower Linear Voltage Regulators
by Khy Vijeh, Matt Smith

GENERAL INFORMATION may be set using a suitable voltage divider connected to

The ADM663A/ADM666A contains a micropower band- LBI. When the voltage on LBI falls below 1.3 V, the open
gap reference voltage source; an error amplifier, A1; drain output LBO is pulled low.
three comparators, C1, C2, C3, and a series pass output
transistor. A P-channel FET and an NPN transistor are
22k
used on the ADM663A while the ADM666A uses an NPN VIN VOUT2
output transistor. VOUT1

1.3V 0.5V
CIRCUIT DESCRIPTION A1 C1
SENSE
The internal bandgap reference is trimmed to 1.3 V
± 30 mV. This is used as a reference input to the error
SHDN D
amplifier A1. The feedback signal from the regulator out- E C2 VIN –50mV
put is supplied to the other input by an on-chip voltage C
O VSET
divider or by two external resistors. When V SET is at D
E
ground, the internal divider tap between R1 and R2, pro- R
C3

vides the error amplifier’s feedback signal giving a +5 V 50mV

output. When V SET is at V IN , the internal divider tap be- R1

tween R2 and R3 provides the error amplifier’s feedback

R2 A2 VTC
signal giving a +3.3 V output. When V SET is at more than 0.9V
50 mV above ground and less than 50 mV below V IN, the R3 ADM663A
GND
error amplifier’s input is switched directly to the V SET
pin, and external resistors are used to set the output
voltage. The external resistors are selected so that the Figure 1. ADM663A Functional Block Diagram
desired output voltage gives 1.3 V at V SET.
VIN VOUT
Comparator C1 monitors the output current via the
SENSE input. This input, referenced to V OUT(2), monitors 1.3V 0.5V
A1 C1
the voltage drop across a load sense resistor. If the volt- SENSE
age drop exceeds 0.5 V, then the error amplifier A1 is
disabled and the output current is limited. SHDN D
E C2 VIN –50mV
The ADM663A has an additional amplifier, A2, which C
O VSET
provides a temperature proportional output, V TC . If this D
is summed into the inverting input of the error amplifier, E
C3
R
a negative temperature coefficient results at the output. 50mV
This is useful when powering liquid crystal displays over R1 LBI
wide temperature ranges.
R2 LBO
C4
The ADM666A has an additional comparator, C4, that 1.3V
R3 ADM666A
compares the voltage on the low battery input, LBI, pin
GND
to the internal +1.3 V reference. The output from the
comparator drives an open drain FET connected to the
Figure 2. ADM666A Functional Block Diagram
low battery output pin, LBO. The low battery threshold
Both the ADM663A and the ADM666A contain a shut- VIN SENSE +1.3V TO +15V
+2V TO +16V RCL OUTPUT
down (SHDN) input that can be used to disable the error INPUT
VOUT2

amplifier and hence the voltage output. The power con- ADM663A
sumption in shutdown reduces to less than 9 µA. ADM666A R2

SHDN
Circuit Configurations VSET
GND
For a fixed +5 V output the V SET input is grounded and no R1
external resistors are necessary. This basic configura-
tion is shown in Figure 3. For a fixed +3.3 V output, the
V SET input is connected to V IN as shown in Figure 4. Cur- Figure 5. Adjustable Output
rent limiting is not being utilized so the SENSE input is
connected to V OUT(2). Table I. Output Voltage Selection

+6V TO +16V
VSET VOUT
INPUT
VIN SENSE +5V GND +5 V
OUTPUT
0.1µF
VOUT2 VIN +3 V
ADM663A 0.1µF R1/R2 ADJ
ADM666A

Current Limiting
VSET GND SHDN
Current limiting may be achieved by using an external
current sense resistor in series with V OUT(2) . When the
voltage across the sense resistor exceeds the internal
0.5 V threshold, current limiting is activated. The sense
Figure 3. A Fixed +5 V Output
resistor is therefore chosen such that the voltage across
+4.5V TO +16V it will be 0.5 V when the desired current limit is reached.
INPUT
VIN SENSE +3.3V
OUTPUT
0.5
0.1µF
VOUT2
RCL =
ADM663A 0.1µF ICL
ADM666A
where R CL is the current sense resistor, I CL is the maxi-
VSET GND SHDN mum current limit.

The value chosen for R CL should also ensure that the cur-
rent is limited to less than the 100 mA absolute maxi-
Figure 4. A Fixed +3.3 V Output mum rating and also that the power dissipation will also
be within the package maximum ratings.
Output Voltage Setting
If V SET is not connected to GND or to V IN, the output volt- If current limiting is employed, there will be an addi-
age is set according to the following equation: tional voltage drop across the external sense resistor
that must be considered when determining the regula-
(R1+ R 2) tors dropout voltage.
V OUT = V SET ×
R1
If current limiting is not used, the SENSE input should
where V SET = 1.30 V. be connected to V OUT(2). In this case, input current should
be limited so that in case of short circuited output,
The resistor values may be selected by first choosing a
device power dissipation does not exceed the rated
value for R1 and then selecting R2 according to the fol-
maximum.
lowing equation:
Shutdown Input (SHDN)
V  The SHDN input allows the regulator to be turned off
R 2 = R1×  OUT – 1
 1.30  with a logic level signal. This will disable the output and
reduce the current drain to a low quiescent (9 µA maxi-
The input leakage current on V SET is 10 nA maximum. mum) current. This is very useful for low power applica-
This allows large resistor values to be chosen for R1 and tions. The SHDN input should be driven with a CMOS
R2 with little degradation in accuracy. For example, a logic level signal since the input threshold is 0.3 V. In
1 MΩ resistor may be selected for R1, and then R2 may TTL systems, an open collector driver with a pull-up re-
be calculated accordingly. The tolerance on V SET is guar- sistor may be used.
anteed at less than ±30 mV so in most applications, fixed
If the shutdown function is not being used, then it
resistors will be suitable.
should be connected to GND.

–2–
Low Supply or Low Battery Detection High Current Operation
The ADM666A contains on-chip circuitry for low power The ADM663A contains an additional output, V OUT1 , suit-
supply or battery detection. If the voltage on the LBI pin able for directly driving the base of an external NPN
falls below the internal 1.3 V reference, then the open transistor. Figure 8 shows a configuration which can be
drain output LBO will go low. The low threshold voltage used to provide +5 V with boosted current drive. A 1 Ω
may be set to any voltage above 1.3 V by appropriate current sensing resistor limits the current at 0.5 A.
resistor divider selection.
VIN
V 
R 3 = R 4  BATT – 1 +
 1.3 V  10µF VIN
VOUT1 2N4237

VOUT2
where R3 and R4 are the resistive divider resistors and 100Ω
ADM663A 1.0Ω
V BATT is the desired low voltage threshold.
SHDN
+ +5V, 0.5A
Since the LBI input leakage current is less than 10 nA, SENSE
SHUTDOWN VSET GND 10µF OUTPUT
large values may be selected for R3 and R4 in order to
minimize loading. For example, a 6 V low threshold may
be set using 10 M Ω for R3 and 2.7 M Ω for R4.
Figure 8. ADM663A Boosted Output Current (0.5 A)
+2V TO +16V
INPUT Temperature Proportional Output
VIN SENSE +1.3V TO +15V
RCL OUTPUT The ADM663A contains a V TC output with a positive tem-
R3
VOUT
perature coefficient of +2.5 mV/ °C typ. This may be con-
ADM666A R2
LBI VSET
nected to the summing junction of the error amplifier
R4 R1
(V SET) through a resistor resulting in a negative tempera-
SHDN LBO
GND
LOW ture coefficient at the output of the regulator. This is
BATTERY
OUTPUT especially useful in multiplexed LCD displays to com-
pensate for the inherent negative temperature coeffi-
cient of the LCD threshold. At +25 °C, the voltage at the
Figure 6. ADM666A Adjustable Output with Low VTC output is typically 0.9 V. The equations for setting
Battery Detection
both the output voltage and the tempco are given be-
Low Output Detection low. If this function is not being used, then V TC should be
The circuit in Figure 7 will generate a low LBO when out- left unconnected.
put voltage drops below a preset value determined by
 R2 R2
the following equations: V OUT = V SET 1+ + (V – V TC )
 R1  R 3 SET
V 
R 2 + R 3 = R1  OUT – 1 TCV OUT =
–R 2
(TCV TC )
 1.3  R3
V 
R 3 = (R1+ R 2)  OL – 1 where V SET = +1.3 V, V TC = +0.9 V, TCV TC = +2.5 mV/ °C
 1.3 
SENSE
for V OUT = 5.0 V nominal, V OL = 3% of V OUT = 4.85 V and R1
VOUT2 VOUT
= 1 MΩ solving the equations simultaneously we will get
ADM663A R2
R2 = 31 k Ω and R3 = 2.82 M Ω. VSET
R3 R1
VOUT = 5V
VTC
VIN VOUT
0.1µF SENSE 0.1µF
R3
2.82MΩ
LBO LBI Figure 9. ADM663A Temperature Proportional Output
R2
31kΩ
SHDN VSET
GND R1
1MΩ

Figure 7. Voltage Regulator Circuit with Low Output

Detector

–3–
APPLICATION HINTS PD = Power Dissipation (W)
Input-Output (Dropout Voltage)
A regulator’s minimum input-output differential or θJA = Junction to Ambient Thermal Resistance ( °C/W)
dropout voltage determines the lowest input voltage for If the device is being operated at the maximum permit-
a particular output voltage. The ADM663A/ADM666A ted ambient temperature of +85 °C, the maximum power
dropout voltage is 1 V at 100 mA output current. For dissipation permitted is:
example when used as a fixed +5 V regulator, the mini-
mum input voltage is +6 V. At lower output currents PD (max ) = (TJ (max) – TA)/(θJA )
(IOUT < 10 mA) on the ADM663A, V OUT1 may be used as PD (max) = (125 – 85)/(θ JA)
the output driver in order to achieve lower dropout volt-
ages. In this case the dropout voltage depends on the = 40/θ JA
voltage drop across the internal FET transistor. This may θ JA = 120 °C/W for the 8-pin DIP (N-8) package
be calculated by multiplying the FET’s saturation resis- θ JA = 170 °C/W for the 8-pin SOIC (R-8) package
tance by the output current, for example with V IN = 9 V,
R SAT = 20 Ω. Therefore, the dropout voltage for 5 mA is Therefore, for a maximum ambient temperature of 85 °C
100 mV. As the current limit circuitry is referenced to PD (max) = 333 mW for N-8
V OUT2 , V OUT2 should be connected to V OUT1 . For high cur-
rent operation V OUT2 should be used alone and V OUT1 left PD (max ) = 235 mW for R-8
unconnected.

VIN SENSE
At lower ambient temperatures the maximum permitted
+6V TO +16V +5V
INPUT ADM663A OUTPUT
power dissipation increases accordingly up to the
VOUT2 maximum limits specified in the absolute maximum
specifications.
VOUT1

VSET GND SHDN

The thermal impedance ( θ JA ) figures given are mea-
sured in still air conditions and are reduced consider-
ably where fan assisted cooling is employed. Other
techniques for reducing the thermal impedance include
Figure 10. Low Current, Low Dropout Configuration large contact pads on the printed circuit board and wide
traces. The copper will act as a heat exchanger thereby
Thermal Considerations
reducing the effective thermal impedance.
The ADM663A/ADM666A can supply up to 100 mA load
current and can operate with input voltages up to 16.5 V, High Power Dissipation Recommendations
but the package power dissipation and hence the die Where excessive power dissipation due to high
temperature must be kept within the maximum limits. input-output differential voltages and or high current
The package power dissipation is calculated from the conditions exists, the simplest method of reducing the
product of the voltage differential across the regulator power requirements on the regulator is to use a series
times the current being supplied to the load. The power dropping resistor. In this way the excess power can be
dissipation must be kept within the maximum limits dissipated in the external resistor. As an example, con-
given in the Absolute Maximum Ratings section. sider an input voltage of +12 V and an output voltage
requirement of +5 V @ 100 mA with an ambient tem-
PD = ( VIN–VOUT) (I L)
perature of +85 °C. The package power dissipation under
The die temperature is dependent on both the ambient these conditions is 700 mW which exceeds the maxi-
temperature and on the power being dissipated by the mum ratings. By using a dropper resistor to drop 4 V,
device. The ADM663A/ADM666A contains an internal the power dissipation requirement for the regulator is
thermal limiting circuit which will shut down the regula- reduced to 300 mW which is within the maximum speci-
tor if the internal die temperature exceeds 125 °C. There- fications for the N-8 package at +85 °C. The resistor value
fore, care must be taken to ensure that, under normal is calculated as R = 4/0.1 = 40 Ω. A resistor power rating
operating conditions, the die temperature is kept below of 400 mW or greater may be used.
the thermal limit.
Bypass Capacitors
TJ = TA + PD (θJA ) The high frequency performance of the ADM663A/
ADM666A may be improved by decoupling the output
This may be expressed in terms of power dissipation as
using a filter capacitor. A capacitor of 0.1 µF is suitable.
follows:
An input capacitor helps reduce noise, improves dy-
PD = (TJ – T A)/(θJA )
namic performance and reduces the input dV/dt at the
where: regulator input. A suitable input capacitor is 0.1 µF or
greater.
TJ = Die Junction Temperature ( °C)
TA = Ambient Temperature ( °C)

–4–
Typical Performance Characteristics
80 2.0
VINDC = +9V
VIN p-p = +2V 1.8
VOUT DC = +5V TA = +25°C
1.6
60 TA = +25°C 663A/666A
1.4

VI N – VOUT – Volts
1.2
PSRR – dB

40 1.0 VIN = +9V

VIN = +2V

0.8

0.6 VIN = +15V

20
0.4

0.2

0 0.0
0.01 0.1 1 10 100 1000 10000 0 20 40 60 80 100 120
IOUT – mA
FREQUENCY – Hz

Figure 11. Power Supply Rejection Ratio vs. Frequency Figure 14. ADM663 VOUT2, ADM666 Input-Output
Differential vs. Output Current

2.0

1.8
VIN = +2V TA = +25°C C2 = 10µF
1.6

1.4
(VIN – VOUT ) – Volts

1.2

1.0 VIN = 9V SCOPE

VIN
0.8 10µF C2 80Ω
0-4V
0.6
VIN = +9V
0.4
VIN = +15V
0.2

0 C2 = 1µF
0 2 4 6 8 10 12 14 16 18 20
IOUT1 – mA

Figure 12. ADM663A VOUT1 Input-Output

Differential vs. Output Current
50mV 200µs

12
Figure 15. Load Transient Response
TA = +25°C

10 2.0A LDO Voltage Regulator with Short Circuit Protection

In battery powered systems, battery life is significantly
8 affected by the voltage regulator’s dropout voltage.
VOUT = +5V
These systems often require low dropout linear regula-
6 tors capable of high output current and extremely low
IIN – µA

VOUT = +3.3V
quiescent current.
4
The circuit in Figure 16 can source current in excess of
2 A with less than 400 mV dropout voltage and con-
2
sumes less than 10 µA in shutdown mode. The c ircuit
exhibits excellent line and load regulation and better
0
2 4 6 8 10 12 14 16 than 5% initial output voltage accuracy.
VIN – Volts
Unlike other LDO voltage regulators which require large
Figure 13. Quiescent Current vs. Input Voltage capacitors in excess of 10 µF for stability, a very small
0.1 µF bypass capacitor is sufficient for this circuit.

–5–
 VIN = 5.5 2N6111 5V @ 2A For high current applications where low dropout voltage
+
R3
1kΩ
Q1 is not required, a power Darlington transistor can be
1µF R1 0.1µF
– 8 28kΩ substituted to take advantage of its relatively high ß.
VIN 1%
The trade-off of this approach is higher power dissipa-
VSET 6
tion due to Darlington’s high saturation voltage.
R2
ADM666A 9.5kΩ
5 2 1% Output voltage is programmable between 1.3 V to 15.4 V
SHDN VOUT
by selecting appropriate resistor values for the voltage
GND SENSE R4 divider network using the following equation:
5Ω
4 1

 R1+ R 2 
V OUT = 1.3 V  
 R2 

Figure 16. 2.0A LDO Regulator The circuit’s performance is shown in Figures 18 and 19.
The circuit’s maximum current is determined by the
5.050
selection of the pass transistor’s current gain, ß, and its 5.0036

maximum power dissipation. For low dropout voltage, a 5.000

viable choice is a PNP pass transistor with appropriate
4.990
power dissipation and ß. The s implified functional dia- 0.0136
4.950
gram in Figure 17 helps clarify the circuit’s operation.

VOUT
4.900
2N6111
VIN VOUT RL = 2.05Ω
R3 Q1
1µF R1 4.850
1kΩ 0.1µF
28kΩ

6 8 4.800
R2
9.5kΩ
4.750
A1 Q2 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0
1.3V
VIN

ADM666 Figure 18. Output Voltage vs. Input Voltage

4 1 2
R4
5Ω
0

5
VOUT – VARIATION – mV

Figure 17. Simplified Functional Diagram 10

The 2N6111 is in a servo loop with ADM666A’s voltage 15

reference, error amplifier and driver circuit.
20
To maintain regulation, output voltage is continuously
monitored by comparing the voltage on the set pin 25

(Pin 6) to a 1.3 V internal voltage reference. The differ- 30

ence is amplified by the error amplifier, A1, and used to
control the pass transistor’s base current, thus control- 0 0.2 0.4 0.6 0.8 1.0 1.5 2.0 3.0
ling its collector current. As output voltage changes due ILOAD – A
to a change in input voltage or load current, the pass
transistor’s base current is adjusted to maintain a con- Figure 19. Output Voltage Variation vs. Load Current
stant output voltage.
The short circuit current is limited by limiting the pass
Since maximum base current is limited to ADM666A’s, transistor’s base current, I b to a value determined by:
short circuit current set by R4 to 100 mA, pass transis-
0.5
tors with higher ß will source higher currents to the Ib =
load. As a result, output short circuit current behavior of R4
the circuit depends on the pass transistor’s ß. The actual value of the short circuit current is deter-
Another significant advantage of using a pass transistor mined by the ß of the pass transistor which in this case
with high ß is to achieve higher efficiency since most of is in 30 to 150 range at a collector current of 3.0 A dc.
the input current is diverted to the load and only a small For more accurate short circuit current control, the
fraction of it is used to control the servo loop. circuit in Figure 20 is a simple way to add short circuit
protection.

–6–
 RSC = 0.05Ω 2N6111 An N-channel power FET switch with very low R ON is
2kΩ used to achieve a very low dropout across the switch
1µF
R1 0.1µF when it is ON.
1N4728 28kΩ
2x
3.3V, ZENER 8 Optional resistor R3 is used to compensate for constant
2N3906
VIN losses by self-discharge or trickle charging of the bat-
50kΩ VSET 6
tery. Consult the battery specification to determine
ADM666 R2 trickle charge current and maximum permissible over
750kΩ 9.5kΩ
5 2 charge current.
SHDN VOUT

20Ω 850Ω R4 Resistor values used in this circuit are optimized for low
GND SENSE
5Ω power operation, when monitoring BAT-ON output;
4 1
avoid excessive loads on this output.

Shut-down pin should be tied to ground if it is not used.

Figure 20. External Short Circuit Protection
3.3V
The short circuit current is determined by using the D1
8 2 100mA
VIN VOUT
following equation: 6 1
VSET SENSE 0.1µF
1µF
0.1
RSC = 100kΩ

ISC 7
VP12A LBO
50kΩ
An appropriate heat sink must be utilized to avoid dam- 150kΩ
R3 ADM666A
age to the pass transistor as well as controller IC. Figure 6V
R1
21 is a plot of the current through the controller and volt- 7.31MΩ
3
age across it vs. input voltage at a constant load current. LBI
R2
2.5MΩ SHDN
As the curve indicates, maximum power dissipation for GND
4 5
controller occurs when input voltage is between 5.4 V to
SHUTDOWN
5.6 V, worst case being 215 mW at V IN = 5.53 V, which is BAT ON
well within the product specification.

130
IB RL = 2.05Ω 5.0
Figure 22. LDO Regulator with Battery Crossover
Switch Circuit
VOLTAGE ACROSS PINS 8 AND 2

110 V8–2
4.8
90
VIN Low Battery Disconnect Circuit
IB 4.6 To prevent damage to the battery and loss of data due to
I
mA 70 8 battery over-discharge, the circuit illustrated in Figure
ADM666
4.4 23 monitors the battery voltage and disconnects the bat-
50 V
tery from the circuit when it drops below a preset value.
4.2
2 215 mW
30 5Ω 6V SEALED LEAD-ACID
D2* MAIN
4.0 BATTERY SOURCE 8 2 V+
VIN VOUT
10 +
6V R1 6
1µF
3.8 6.54MΩ VSET
5.0 5.2 5.4 5.6 5.8 6.0 7.0
R3 R5 D1* D3 MEMORY
VIN 1 V+
600kΩ 9.1MΩ SENSE
3
LBI
R6
R2 R4 5 SHDN
10Ω
Figure 21. Controller IC Power Dissipation 2.5MΩ 2MΩ
0.1µF
ADM666A
However, the pass transistor requires adequate heat 2N2222 7
LBO
sink specially if it were to operate with large input output
LBO
voltage differential.
* FOR BEST TEMPERATURE TRACKING PERFORMANCE,
LDO Regulator with Battery Crossover Switch DIODES MUST BE IN THERMAL CONTACT.
The circuit in Figure 22 automatically connects the
standby battery to the circuit when primary voltage Figure 23. Low Battery Disconnect and Memory
source is disconnected or drops below a preset voltage Backup Circuit
level.
Diode D2 is added for isolation; D1 is to compensate for
Battery ON voltage level is determined using the follow-
voltage drop across D2. For better output voltage accu-
ing equation:
racy performance, diodes D1 and D2 must be in thermal
 (V )  contact. Surface mount Schottky diodes mounted in
R1 = R 2  BAT – 1 close proximity of each other offer the best temperature
 1.3 V 
tracking performance.

–7–
In battery disconnect mode, the circuit’s quiescent cur- Charge termination voltage, V T, and charge resume volt-
rent is less than 20 µA. If LBO function is not needed or it age, V CH , are set by R3, R4 and R5. Charging is termi-
is monitored via a high impedance input, the circuit’s nated when battery voltage reaches V T.
current consumption can be reduced significantly by re- Charge termination voltage, which in this case is 7.2 V,
placing R4 with a short and R3 with a 9 M Ω resistor. This is calculated using the following equation:
circuit has less than 10 µA quiescent current.
V 
5 Volt Supply with Battery Backup and Battery ON Lag R 4 = (R 5 + R 6)  T – 1
 1.3 
The circuit in Figure 24 switches to NiCd backup battery
when the main input voltage drops below value set by where R6 = 20 k Ω, and R4 = 9.2 M Ω.

E2032–12–5/95
R1, R2 and R3 and returns to the main input when its
ADM666A continues to monitor the battery voltage
voltage reaches the preset value set by R3.
level; charging will resume when it drops below the V CH .
8
VIN VOUT
2 MAIN 5V The V CH level is set by adjusting R3.
1 MEMORY 5V
+
1µF R1
SENSE With resistor values selected in Figure 26, charging
0.1µF
3
ADM666A 100kΩ starts when the battery voltage is around V CH = 5 volts
LBI
51kΩ
and will terminate when the battery voltage reaches
7
R2 LBO VP12A slightly above 7.2 V.

5 150kΩ Charger status is indicated by the LED. A lighted LED

SHDN
+
GND VSET 5V NICD indicates charger ON; a flashing LED indicates battery
BACKUP
4 6 – disconnect.
SHOULD BE
CONNECTED
TO GND R3
LOW BATTERY
FLAG
To minimize calculation errors and maximize the circuit
IF NOT USED efficiency, LED current should be limited to about 2 mA.
HYST ADJ
To minimize current drain by battery voltage monitoring
circuit’s, large resistor values are selected for R4 and R5
Figure 24. 5 V Battery Powered Supply with Backup
and Battery ON Flag (see text for recommended values).

The Battery ON flag goes low whenever the circuit is Charge current is limited to 100 mA by a short circuit
switched to NiCd battery. current limiting resistor. However higher charge current
is possible using the circuit in Figure 26.
Low Cost Battery Charger Circuits
A simple, low cost and yet flexible battery charger is pre-
22k
sented in Figure 25. Maximum output voltage is pro- VI N VOUT2

grammed by selection of R1 and R2 ratio’s using VOUT1

1.3V 0.5V
 ( V OUT )  A1 C1
R1= R 2  – 1 SENSE

 1. 3V 
SHDN D
VI N –50mV
for V OUT = 7.8 V, R1 = 2.82 M Ω, and R2 = 560 k Ω. Maxi- E C2
C
O VSET
mum charge current is determined by the current limit- D
E
ing resistor which in this case is 100 mA set by R8. R
C3

50mV

R1
2 R8 5Ω
VI N = 9V VOUT
8 A2 VTC
VIN 1 R2
SENSE 5 0.9V
+ R1 2.82MΩ CELLS
1µF 0.1µF R3
R7 ADM666A ADM663A
R4 GND

PRINTED IN U.S.A.
3k 6 9.2MΩ
VSET
R2 560kΩ
Figure 26. High Charge Current Battery Charger
5
SHDN 3
LBI Power PNP pass transistor with appropriate current rat-
R5
LBO
7
2MΩ
ing is controlled by the ADM666A.
R3
GND
4 270kΩ R6 Available charge current is determined by the
20kΩ
transistor’s power rating, its current gain, ß, and con-
trolled by the short circuit current limit resistor.

Figure 25. Low Cost Battery Charger

–8–