3-A DC Motor Driver TLE 5203

Overview SPT IC 1)

Features
• Output current ± 3 A
• I/O error diagnostics
• Short-circuit proof
• Four-quadrant operation
• Integrated free-wheeling diodes
• Wide temperature range
• Open load detection P-TO220-7-1
• Break low, if break high required, the device
TLE 5204 will fit

P-TO220-7-8

Type Ordering Code Package

TLE 5203 Q67000-A9096 P-TO220-7-1
TLE 5203 G Q67006-A9242 P-TO220-7-8

Description
TLE 5203 is an integrated power bridge with DMOS output stages for driving DC motors.
This motor bridge is optimized for driving DC motors in reversible operation. The internal
protective circuitry in particular ensures that no crossover currents can occur.
Because the free-wheeling diodes are integrated, the external circuitry that is necessary
is reduced to the capacitors on the supply voltage.
The control inputs have TTL/CMOS-compatible levels.

1) SIEMENS Power Technology

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 TLE 5203

TLE 5203 TLE 5203 G

1 2 3 4 5 6 7

EF GND VS
Q1 Ι1 Ι2 Q2
AEP01224

Figure 1 Pin Configuration (top view)

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Pin Definitions and Functions

Pin No. Symbol Function
1 Q1 Output of channel 1; Short-circuit proof, free-wheeling
diodes integrated for inductive loads
2 EF Error flag; TTL/CMOS-compatible output for error detection
(open drain)
3 I1 Control input 1; TTL/CMOS-compatible
4 GND Ground; connected internally to cooling fin
5 I2 Control input 2; TTL/CMOS-compatible
6 VS Supply voltage; wire with capacitor matching load
7 Q2 Output of channel 2; Short-circuit proof, free-wheeling
diodes integrated for inductive loads

Circuit Description

Input Circuit
The control inputs consist of TTL/CMOS-compatible Schmitt triggers with hysteresis.
Buffer amplifiers are driven by these stages and convert the logic signal into the
necessary form for driving the power output stages.

Output Stages
The output stages form a switched H-bridge. Protective circuits make the outputs short-
circuit proof to ground and to the supply voltage throughout the operating range. Positive
and negative voltage spikes, which occur when switching inductive loads, are clamped
by integrated power diodes.

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Functional Truth Table

E1 E2 Q1 Q2 Comments
L L H L Motor turns counterclockwise
L H L H Motor turns clockwise
H L L L Brake; both low side transistors turned-ON
H H Z Z Open circuit detection

Notes for Output Stage

Symbol Value
L Low side transistor is turned-ON
High side transistor is turned-OFF
H High side transistor is turned-ON
Low side transistor is turned-OFF
Z High side transistor is turned-OFF
Low side transistor is turned-OFF

Monitoring Functions
An internal circuit ensures that all output transistors are turned-OFF if the supply voltage
is below the operating range.
A monitoring circuit for each output transistor detects whether the particular transistor is
active and in this case prevents the corresponding source transistor (sink transistor) from
conducting in sink operation (source operation). Therefore no crossover currents can
occur. Pulse-width operation is possible up to a maximum switching frequency of 1 kHz
for any load.
Depending on the load current higher frequencies are possible.

Protective Function
Various errors like short-circuit to + VS, ground or across the load are detected. All faults
result in turn-OFF of the output stages after a delay of 40 µs and setting of the error flag
EF to ground. Changing the inputs resets the error flag.

Output Shorted to Ground Detection

If a high side transistor is switched on and its output is shorted to ground, the output
current is limited to typ 8 A. After a delay of 40 µs all outputs will be switched off and the
error flag EF is set to ground.

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Output Shorted to + VS and Overload Detection

An internal circuit detects if the current through the low side transistor is higher than 4 A
typ. In this case all outputs are turned off after 40 µs and the error flag EF is set to
ground.
At a junction temperature higher than 160 °C the thermal shutdown turns off, all four
output stages commonly and the error flag is set without a delay.

Open Load Detection

The output Q1 has a 10 kΩ pull-up resistor and the output Q2 has a 10 kΩ pull-down
resistor. If E1 and E2 are high, all output power stages are turned-OFF. In case of no
load between Q1 and Q2 the output voltage Q1 is VS and Q2 is ground. This state will
be detected by two comparators and an error flag will be set after a delay time of 40 µs.
Changing the inputs resets the error flip flop.

Diagnosis
Input Output Diagnosis EF
E1 E2 Q1 Q2 Shorted Shorted Overload Open Load
to GND to VS
L L H L Q1 Q2 X – L
L H L H Q2 Q1 X – L
H L L L – Q1, Q2 – – L
H H Z Z – – – X L

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V EH =
Pull Up
10 k Ω

EF
Pull
Down & 40 µs RS
10 k Ω = V EL
FF

AES01688

Figure 2 Simplified Schematic for Open Load Detection

Error Flag VS
2 6

Error
Flag

Protection
Circuit 1

3 1
Control Input 1 Output 1

5 7
Control Input 2 Output 2

Protection
Circuit 1

4
GND AEB01225

Figure 3 Block Diagram

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Absolute Maximum Ratings

Tj = – 40 to 150 °C
Parameter Symbol Limit Values Unit Remarks
min. max.

Voltage
Supply voltage VS – 0.3 40 V –
Supply voltage VS –1 – V t < 500 ms; IS < 5 A
Logic input voltage VI1 , 2 – 0.3 7 V VS = 0 – 40 V
Diagnostics output voltage VEF – 0.3 7 V –

Current
Free-wheeling current IF –4 4 A Tj ≤ 150 °C
Output current 1) IQ –4 4 A –
Junction temperature Tj – 40 150 °C –
Storage temperature Tstg – 50 150 °C –

Thermal Resistance
Junction-case Rth jC – 4 K/W –
Junction-ambient Rth jA – 65 K/W –

Operating Range
Supply voltage VS 6 24 V –
Logic input voltage VI1 , 2 – 0.3 7 V –
Switching frequency 2) f – 1 kHz –
Junction temperature Tj – 40 150 °C –

1)
During overload condition currents higher than 4 A can dynamically occur, before the device shuts off, without
any damaging the device.
2) Depending on load higher frequencies are possible.

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Electrical Characteristics
VS = 6 to 18 V; Tj = – 40 to 150 °C
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.

General
Quiescent current Iq – – 10 mA IL = 0 A
Turn-ON delay td1 – 10 20 µs Input to output
Turn-OFF delay td2 – – 10 µs Input to output
Turn-ON time tr – 10 20 µs IQ = 2.5 A;
cf diagram
Turn-OFF time tf – – 10 µs IQ = 2.5 A;
cf diagram
Undervoltage VS – 5.5 5.9 V IC ON
Undervoltage VS – 4.5 5.2 V IC OFF

Logic
Control inputs
H-input voltage VIH 2.8 – – V –
L-input voltage VIL – – 1.2 V –
Hysteresis of ∆VI 0.4 0.8 1.2 V –
input voltage
H-input current II –2 – 2 µA VI = VIH
L-input current II – 10 –4 0 µA VI = VIL
Diagnosis output
Delay time td 20 40 60 µs –
L-output voltage VEF – – 0.4 V I = 3 mA
Leakage current IRD – – 10 µA –
Error detection
Switching threshold U VEH 2 2.7 3.5 V Error low
Switching threshold L VEL 2 2.7 3.5 V Error high
Overcurrent 1 IF1 3 4 5 A Error low

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Electrical Characteristics (cont’d)

VS = 6 to 18 V; Tj = – 40 to 150 °C
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.

Outputs
RDSONU – – – 0.4 Ω VS > 6 V; Tj = 25 °C 1)
RDSONU – – – 0.65 Ω VS > 6 V; Tj = 150 °C 1)
RDSONL – – – 0.4 Ω VS > 6 V; Tj = 25 °C 1)
RDSONL – – – 0.65 Ω VS > 6 V; Tj = 150 °C 1)
Diode forward voltage VFU – – 1.5 V IF = 3 A
Diode forward voltage VFL – – 1.5 V IF = 3 A
Pull up/pull down R 5 10 25 kΩ –

1) Values for RDSON are for t > 100 µs after applying + VS.

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4700 µF
Ιq, ΙS 470nF
63V

6 2
Ι Ι1 Ι Q1
VS 3 1

TLE 5203 RL VEF

Ι Ι2 Ι Q2
V Ι1 5 7

4
V Ι2 VQ2 V Q1
ΙM

AES01226

Figure 4 Test Circuit

Figure 5 Timing Diagram

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+ VS = 12 V
*)
220 nF

5V
6
2 kΩ
Error
2 1
Flag

TLE 5203 M
3
Control
7
Inputs
5
4

AES01228

*) Necessary for isolating supply voltage or interruption (e.g. 470 µF).

Figure 6 Application Circuit

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Diagrams
RON Resistance of Output Stage Output Voltage on Diagnostics
over Temperature Output versus Current
AED01305 AED01306
800 300
R ON 6 V< VS <18 V VEF
mV
mΩ
250
600 VS =12 V T j = 150 ˚C
max
200

typ
400 150

T j = 25 ˚C
100
200

50

0 0
0 25 50 75 100 ˚C 150 0 1 2 3 4 mA 6
Tj

Forward Current of Upper Forward Current of Lower

Free-Wheeling Diode versus Voltage Free-Wheeling Diode versus Voltage
AED01303 AED01304
4 4
ΙF ΙF
A A

3 3
T j = 150 ˚C

T j = 25 ˚C T j = 150 ˚C
2 2
T j = 25 ˚C

1 1

0 0
0.2 0.6 1 V 1.4 0.2 0.6 1 V 1.4
VF VF

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Overcurrent Threshold Quiescent Current

versus Temperature versus Temperature

AED01681 AED01682
10 5
ΙQ ΙS
A mA

8 4

typ
typ
6 3
min

4 2

2 1

0 0
-40 0 40 80 120 ˚C 160 -40 0 40 80 120 ˚C 160
Tj Tj

Input Threshold Switching Threshold VEL, EH

versus Temperature versus Temperature

AED01683 AED01684
3.5 5.5
VΙ VF
V V

3.0 5.0

typ VΙ H
2.5 4.5

typ

2.0 4.0

typ VΙ L

1.5 3.5

1.0 3.0
-40 0 40 80 120 ˚C 160 -40 0 40 80 120 ˚C 160
Tj Tj

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E2 E1 = Low

8A

Ι Q2

V Q2 R Short x 8 A

V FL
40 µ s

EF
AED01685

Figure 7 Timing Diagram for Output Shorted to Ground

E2 E1 = Low

20 A

Ι Q1

VS
V Q1 R Short x 20 A V FU

40 µ s

EF
AED01686

Figure 8 Timing Diagram for Output Shorted to VS

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E2 E1 = Low

Ι F1
Overcurrent
Switching
Threshold
Ι Load
40 µ s

VS VF

V Q1

R ON x Ι Load

VS

R ON x Ι Load

V Q2

VF

EF
AED01687

Figure 9 Timing Diagram for Overcurrent

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Normal Mode Open Circuit

E1

E2

VS

V S /2
V Q1

V Q2

40 µ s

EF
AED01691

Figure 10 Timing Diagram for Open Load

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Package Outlines

P-TO220-7-1
(Plastic Transistor Single Outline)

10 +0.4 4.6 -0.2

10.2 -0.2 1 x 45˚
+0.1 +0.1
3.75 1.27

2.8

15.4 ±0.3
19.5 max

8.8 -0.2
16 ±0.4

8.6 ±0.3
10.2 ±0.3
2.6
1 7
1.27 0.4 +0.1
1)
0.6 +0.1 4.5 ±0.4
0.6 M
7x 8.4 ±0.4

1) 0.75 -0.15 at dam bar (max 1.8 from body)

1) 0.75 -0.15 im Dichtstegbereich (max 1.8 vom Körper) GPT05108

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”. Dimensions in mm

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P-TO220-7-8 (SMD)
(Plastic Transistor Single Outline)

4.6
1.27
10.2 0.2
8.0 2.6

1)
10.1

8.8
3.5

1.5
0.6
1.27 0.4

6 x 1.27 = 7.62 GPT05874

1) shear and punch direction burr free surface

Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device Dimensions in mm

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