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Soft Switching Technolsgies Corporataorr

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Abstract-In this pager, both peak current mode and average

current mode control schemes will be iniveskigated as applied to
a full bridge PWM converter with a two iinductor rectifier. The
two inductor rectifier circuit offers reduced secondary side
current rating and i s most suitable for high current
applications. With current mode control, the two ~ n d ~ c ~ o r
rectifier is modelled as two parallel connected buck converlcrs.

I. INTRODUCTION

Since its inception in the late 1960s, current mode control

has been widely applied to switch mode powex supplies.
This approach offers improved dynamic response and
Fig. I : A full bridge PWM iX-to-.DCconverter with a two indiictor
paralleling capability as compared to vloltage mode, control or rectifier
duty cycle control by effectively elimiiieiting the phase lag of
the control to inductor current transfer function. The output voltage is controlled using hase shift control
TWOtypes of current mode control relevant eo this work which allows zero voltage switchjng (ZVS) of the input
are peak and average current mode control. Peak current bridge. The advantages o f the two inductor rectifier circuit
mode control (PCMC) offers inhie rent input voltage include lower secondary s.i& current rating and hence lower
feedforward, pulse by pulse peak current limiting and losses, frequency doubling at the output capacitor, output
consequent flux balance in isolated power supplies. De!jpite current doubling in addition to an inherent 24. voltage ratio.
these advantages, PCMC incurs poor noise immunity, This makes this converter attractivk: for high current, Low
average current error, and instabilities in the absence of slope volta,ge applications.
complznsation. Alternatively, average current mode control 'Flhree circuit. modes c m be identified for the converter of
(ACMC) exhibits accurate regulation o f the programmed Fig. 'L within half a switching cycle: a power delivery mode
current and improved noise immunity without slope (mode-I), a freewheeling mode (mode-IT) and a commutation
compensation. mode (mode-111) as shown in Fig. 2.
In this paper, peak and average current mode control In phase shift control, when a switch in the leading edge
techniques are applied to a full bridge E'WM converter .with is t u n e d off, the energy available for achieving ZVS for the
two inductor rectifier. The two inductor rectifier circuit leading leg is the output filter energy. However, for the
offers reduced secondary side current rating compared to a lagging leg switches, the only energy available for
full bridge or center tapped rectifier topology and is most commutation i s the leakage inductance energy. Hence, the
suitable for high current applications. Fixthermore, the two leading leg switches achieve ZVS even at light loads,
inductor rectifier can be modeled a s two parallel buck whereas %VS i s lost in the lagging leg switches below a
converters. However the analysis differs from parallel certain load condition. Typical voltage and current
connected modules in that the output inductors share the waveforms are shown in Fig. 3. In the sie.ady state the output
same output filter capacitor. This leads to cross coupling voltage is given by
between the two converters which needs to be accounted for.

CONV WIT
Note that sirice the output cunent is the sum of the two
A full bridge PWM DC-to-DC converter with a two output filter cun-enes, the current rating of transformer
inductor rectifier was first proposed by the author in [ l ] and secondary winding is one half the load current. This
is shown in Fig. 1. The two inductor rectifier circuit was effectively reduces the ac winding losses in the transformer
first reported in [2]. and output fileer inductors.
 The two inductor rectifier can be modeled as two parallel
connected buck converters. However the analysis differs
from parallel connected modules in that the output inductors
share the same output filter capacitor. This results in cross
coupling between the two output inductor currents and care
sec.
must be taken when designing the control loops.
(a)
111. Average Current Mode Control Implementation

vfpyq prim.
I l fLs+ + Ls

(b)
v o

sec.
Average current mode control is preferred for accurate
control of the average output current and offers higher noise
immunity compared with peak current control. This is
advantageous in current limited power supplies where the
supply current is limited. For this mode of control, current

q=lIl/ppp
sensing can be performed either on the input side or the
output side of the isolation transformer. However, with input
current sensing, the negative slope of the output current
in' + needs to be synthesized which can result in an error if the
Ls Ls output filter inductors are designed using swinging cores.
prim. sec.
On the other hand, output current sensing offers accurate
measurement of the average output current but does not
(C)
guarantee flux balancing in the isolation transformer. As a
Fig. 2: Equivalent circuit modes of the convertex result, a dc bloclung capacitor is needed to prevent flux
imbalance. Figure 4 shows a converter schematic with
average current control and output current sensing. In this
i Mode-I :Mode-111 Mode-III! configuration, a dc blocking capacitor (C,) is utilized to
prevent flux imbalance.

. . . .. .. I I&
:" Lf I ,I

.. .. ..
.
,
.. ..
.. .. +
t
.. .. .. .. ..
... . . I I I I -1'5
.. ..

..
..
.
...
.
... . ..
._ . .
... . .
... ...
_ . .
. .
i i 'Ds2

Fig. 4: Converter under average current mode control

.. .. .., .. .. .. .. ..
.... .. .. . .
.. ..
.
.. .. .. t
.. , . . . .. . Different techniques have been proposed to analyze
switching converters utilizing current mode control [3-51.
. . c The simplified PWM switch model will be used to analyze
the system at hand and is shown in Fig. 5 [3].

i. -DTs
2

Fig. 3: Typical waveforms of the converter

Adopting current mode control ensures current sharing

transformer
between the two output filter inductors. An inner current Fig. 5: PWM switch model
loop regulates the filter inductor currents while an outer
voltage loop regulates the output voltage. In power supply Since the output current is the sum of the two output filter
applications operating in current limit, the inner current loop inductor currents, the system can be reduced to two parallel
is the only active loop. connected buck converters [7,8]. Furthermore, since the

2 04
output filter inductor currents are not individually regulated,
the small signal model of the system can be reduced to that i
k : . I+- s ,
of a single buck converter with average current mode control (7)
where the resultant filter inductor is the parallel combination
of the two output inductors. Although each inductor current
is not separately regulated, any difference between the
average currents will be corrected by the input dc blocking
capacitor which maintains zero net dc flux within the: This transfer function represents an integrator followed by a
transformer. This guarantees that the two inductor currents, 1ea.d-lag network. T o ensure stability, the zero should be
remain equal. Note that the effective switching frequency of placed before the power stage filter frequency of the current
the resultant system is twice the switching frequency for the loop where the phase shift of the integrator is canceled by the
two filter inductor currents are out of phase which results in zero at half the switching frequency. The pole is normally
frequency doubling at the output. placed above half the switching frequency to roll off the gain
Using the PWM switch model and assuming the and thereby eliminate high frequency noise. Furthermore,
transformer is ideal, the equivalent small signal model of the this pole placement minimizes interaction with the current
converter is shown in Fig. 6. loop.
L. By straightforward analysis, the control to output current
L =-+.
loop transfer function is given by
+ q (s)= R, . H , ( s ) . G,(s).F, . F, (s) (1 1)
where
"0

is the direct (forward) gain transfer function.

'The loop transfer function for a 5kW converter were
computed using MATLAB and the results are shown in Fig.
7 (see appendix A).

Fig. 6: Small signal model of the converter

Here, Rs is the sense resistor, He(S) is the sampling gain, Fm

is the modulator gain and Gc(s) is the compensation transfer
function. The sampling and modulator gains are defined in
[6]to be Frequency ( Hz )
2 100
S :i
H e ( $ ) = 1+-+-- 2
Qzun OI,, - 0
U
2
F, =---
1 ;
-100
(3)
se+s; 2
c
a -200
where,
r)
-300
Q =-f 101 102 103 104 105
n Frequency ( Hz )
0,= n f,$'
Fig 7 Loop transfer function with average current control

It is clear from the above figure that the current loop can
be stabilized with proper compensator design and without
slope compensation. In fact, the compensator gain can be
adjusted in a similar fashion to adding slope compensation in
In average current mode control, a possible current peak current mode systems. The gain margin of the current
compensation transfer function is given by loop is 13.5dB and the phase margin is 67.7" while the
current loop bandwidth is 1OkHz.

205
 The corresponding closed loop transfer function of the
system is shown in Fig. 8 and the output current step
response is shown in Fig. 9.

Frequency In Hr
102 103 I OH 105 Fig 10 Loop transfer funcbon with average current control
Frequency ( Hz )

c 80.00

40.00

Frequency ( Hz ) 0

Fig 8 Closed loop transfer function with average current control 1

3000U DOOOU 1SOOU 21O.OU 279.011
I
TIME In Secs
Fig. I I : Output currents step response with average current control

Unlike average current mode control, since peak current

control regulates the peak of the inductor currents, the
average output current may not be regulated. In this case, the
negative slope needs to be reconstructed or an outer average
current loop can be used to regulate the output current.
The implementation of the peak current loop control is
similar to that of average current control except that the
current sensing is done on the primary side of the transformer
n o.os (1.1 0.15 02 (1.2s 0.3 and no dc blocking capacitor is used. In this case, the switch
Time (ni,xccs) currents in one leg can be sensed using current transformers.
Fig. 9: Output current step response with average current control This offers one more level of protection since an active
switch current limit is implemented.
As expected, the output current overshoot is low (5%) The small signal equivalent circuit with peak current
and the system reaches steady state in 0.3ms. mode control is shown in Fig. 12 [9]. Note that each of
To verify the analysis results, a SPICE average model of inductor currents are driven at half the actual duty cycle of
the converter was simulated. In this case, the system was the converter. Hence, in the small signal model, the duty
modeled as two parallel connected buck converters with a cycle D needs to be halved.
single output current loop. The resultant current loop
transfer function is shown in Fig. 10 while the step response
of the converter is shown in Fig. 11. It is clear from these
figures that the simulation data match the analytical ones.
Note also that the output filter current response is the same as
the total output current.

III. Peak Current ode Control Implementation

In applications where flux balancing is required on the

primary side of the transformer and dc blocking capacitors
I I
are not used, peak current control can be adopted to ensure
current sharing between the two inductors.
Ti *
Fig. 12: Small signal model with peak current mode control

206
In contrast to average current mode control small signal , =: F12and Fzz= F,,.
Note that for L I = L ~F,,
model, the peak current small signal model is more involved To guarantee stability, each loop of the system must be
in that the two converters are coupl~sclvia the common output stablc. Two current loops can be identified, a direct loop
filter capacitor. As a result, the sjstem can no longer be associated with each current with its corresponding duty
reduced to that of a single buck converter with peak current cycle and a cross coupled loop with the ~ o ~ ~ l e r ~ e iduty
~tary
control. The equivalent control block diagram of the systern cycle. These loops are given by,
under peak current mode is shown i n Fig. 13.

P' iJ E k e , the negative sign of T12 and T, implies that the phase
lag at the cross over frequency should be less than 360" as
opposed to the conventional 180".
The control to output transfer function may be evaluated
as

Fig. 13: Block diagram of the peak current control model H; = Rb7* H e (23)
Tlhe condition for instability of the control to output transfer
The transfer functions are computed using the average function (21) i s
PWM switch model as shown in Fig. 14.

which imposes an additional criteria for overall system

stability.
'The converter of appendix A was further analyzed using
MATLAB with peak current mode control. The direct and
cross coupled loop transfer functions are shown in Fig. IS.
Fig. 14:Sinal1 signal cquivaleit circuit

The direct (forward) gain transfer function is given by [ 101

where
Frequency ( Hz )
Fij = i i / d j (14)
The cross coupled transfer function is given by

where io I 102 I03 104 105

L,, = Ll I1 L2 Frequeiicy ( Hz )

R, = R N R , Fig. 15: Direct and cross coupled loop gains

R, = R + R,
As shown above, both loops can be stabilized with slope
compensation. In this case, the added slope, Se is assumed to

207
be one half the down slope of the output filter inductor 80
currents, Sf or 60
,.-.
5 40
L LL
. , E:
d 20
Again, note that the cross coupled loop phase margin is
computed in reference to 360". 0
The stability condition of (24) was evaluated and the
10' 102 103 104 105
results are shown in Fig. 16. The loop transfer function for a
Frequency ( H z )
single converter case is overlaid for reference.

1-1

101 102 103 104 105

101 102 103 104 105 Frequency ( Hz )
Frequency ( Hz )
Fig. 17: Loop gains with peak current control, Se= -St

,""
101 102 101 10a 105
Frequency ( H z )
10' 102 103 104 105
Frequency ( Hz )
Fig. 16: Loop gains with peak current control, Se = -0.5 St

As expected, the loop transfer response of a single converter

is stabilized with the addition of slope compensation. Unlike
the single converter case, the overall loop response of the
system has higher gain and the phase characteristics reveal
the presence of a low frequency pole and a high frequency
zero which reduces the relative stability of the of the system.
To improve stability of the current loop, more slope 101 102 103 104 105
compensation may be added. Figure 17 shows the loop Frequency ( Hz )
response with additional slope compensation where Se = -Sf.
Fig 18: Closed loop gains with peak current control, Se = -St
The resultant gain margin is 6.5dB while the phase margin is
4.5'. The closed loop transfer function of the system is
shown in Fig. 18. 40.00

A SPICE average model of the converter was simulated

to verify the analysis results presented above. The system I
30.00

was modeled as two parallel connected buck converters with

two individual peak current loops. The resultant closed loop
transfer function is shown in Fig. 19, while the step response
-
i
m 20.00
a
=:

of the converter is shown in Fig. 20. As shown in Fig. 19, 10 ow

the simulated loop response matches the analytical model of
Fig. 18. 0

t I I I I
io0 1K 10K
Frequency in Hz

Fig. 19: SPICE loop gains with peak current control, Se = -St

208
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-
111
1-- 1996.
2000u 6OOOU 101loIlU 14oou 18OOU

TIME in Secs

Fig 20. Step re5ponse undcr peak carrent mode control

The analyzed 5kW converter data:
V,,:=320 V V,=4& v, I,=100 A
R==0.55n a=2.5 fs=75 kWz
Lf=30 PH c,,=10000 pF R,=20 ma
In this paper, the analysis and implementation of peak
R,=0.024 R,=0.045 L
2 V,=5V (ramp pcak)
and average current mode control teclhniques applied to a full
bridge PWM converter with two inductor rectifier were
discussed. The two inductor rectifkr circuit offers reduced
secondary side current rating compared to a full bridge or
center tapped rectifier topology and is suitable for high
current applications. Furthermore, t h e two inductor rectifier
can be modeled as two parallel buck converters.
In average current mode control, the two converters are
reduced to a single converter operating at twice the switching
frequency. An integrator in series with a lead lag network
ensuires stability o f the current loop. In contrast, the system
in peak current mode control cannot b:: reduced to that of a
sin& buck converter. This is due io the presence of cross
coupling between the two converters for the output inductors
share the same output filter capacitor. It has been shown that
unlike the single converter case, the relative stability of the
overall peak c!Jrrcnt loop is less than that of the single loop.
As a result, more slope compensatior, may be required to
improve the relative stability of the system.

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209