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Soft Switching Technolsgies Corporataorr 2224 Evergreen Rd. Suite .B 6, Middleton, WI 53562 T l S h Tel : (608) 835-6552, Fax : (e1O8) 836-6553, E-naanl. i j i a t f i l r t ~ ~ ~ ~ ~ ~ - w ~ t c h . c o n n

Abstract-In this pager, both peak current mode and average current mode control schemes will be iniveskigated as applied to a full bridge PWM converter with a two iinductor rectifier. The two inductor rectifier circuit offers reduced secondary side current rating and i s most suitable for high current applications. With current mode control, the two ~ n d ~ c ~ o r rectifier is modelled as two parallel connected buck converlcrs.

I. INTRODUCTION
Since its inception in the late 1960s, current mode control has been widely applied to switch mode powex supplies. This approach offers improved dynamic response and paralleling capability as compared to vloltage mode, control or duty cycle control by effectively elimiiieiting the phase lag of the control to inductor current transfer function. TWO types of current mode control relevant eo this work are peak and average current mode control. Peak current mode control (PCMC) offers inhie rent input voltage feedforward, pulse by pulse peak current limiting and consequent flux balance in isolated power supplies. De!jpite these advantages, PCMC incurs poor noise immunity, average current error, and instabilities in the absence of slope complznsation. Alternatively, average current mode control (ACMC) exhibits accurate regulation o f the programmed current and improved noise immunity without slope compensation. In this paper, peak and average current mode control techniques are applied to a full bridge E'WM converter .with two inductor rectifier. The two inductor rectifier circuit offers reduced secondary side current rating compared to a full bridge or center tapped rectifier topology and is most suitable for high current applications. Fixthermore, the two inductor rectifier can be modeled a s two parallel buck converters. However the analysis differs from parallel connected modules in that the output inductors share the same output filter capacitor. This leads to cross coupling between the two converters which needs to be accounted for.

Fig. I : A full bridge PWM iX-to-.DCconverter with a two indiictor rectifier

The output voltage is controlled using hase shift control which allows zero voltage switchjng (ZVS) of the input bridge. The advantages o f the two inductor rectifier circuit include lower secondary s.i& current rating and hence lower losses, frequency doubling at the output capacitor, output current doubling in addition to an inherent 2 4 . voltage ratio. This makes this converter attractivk: for high current, Low volta,ge applications. 'Flhree circuit. modes c m be identified for the converter of Fig. 'L within half a switching cycle: a power delivery mode (mode-I), a freewheeling mode (mode-IT) and a commutation mode (mode-111) as shown in Fig. 2. In phase shift control, when a switch in the leading edge is t u n e d off, the energy available for achieving ZVS for the leading leg is the output filter energy. However, for the lagging leg switches, the only energy available for commutation i s the leakage inductance energy. Hence, the leading leg switches achieve ZVS even at light loads, whereas %VS i s lost in the lagging leg switches below a certain load condition. Typical voltage and current waveforms are shown in Fig. 3. In the sie.ady state the output voltage is given by

CONV

WIT
Note that sirice the output cunent is the sum of the two output filter cun-enes, the current rating of transformer secondary winding is one half the load current. This effectively reduces the ac winding losses in the transformer and output fileer inductors.

A full bridge PWM DC-to-DC converter with a two inductor rectifier was first proposed by the author in [ l ] and is shown in Fig. 1. The two inductor rectifier circuit was first reported in [2].

sec.
(a)

The two inductor rectifier can be modeled as two parallel connected buck converters. However the analysis differs from parallel connected modules in that the output inductors share the same output filter capacitor. This results in cross coupling between the two output inductor currents and care must be taken when designing the control loops.

111. Average Current Mode Control Implementation

Average current mode control is preferred for accurate control of the average output current and offers higher noise immunity compared with peak current control. This is advantageous in current limited power supplies where the supply current is limited. For this mode of control, current sensing can be performed either on the input side or the output side of the isolation transformer. However, with input current sensing, the negative slope of the output current needs to be synthesized which can result in an error if the output filter inductors are designed using swinging cores. On the other hand, output current sensing offers accurate measurement of the average output current but does not guarantee flux balancing in the isolation transformer. As a result, a dc bloclung capacitor is needed to prevent flux imbalance. Figure 4 shows a converter schematic with average current control and output current sensing. In this configuration, a dc blocking capacitor (C,) is utilized to prevent flux imbalance.

vfpyq q=lIl/ppp
I l f Ls+ + Ls v o
sec. prim.

(b)

i n '

Ls

Ls

prim.

sec. (C)

Fig. 2: Equivalent circuit modes of the convertex

Mode-I

:Mode-111 Mode-III!

. .
. . . .
. . . .

. .

. .

I&

:"

Lf

I ,I

. . . .

. .. .
. . . . . . . . . .
'Ds2

. . , . . . .

. . . . . . . . . .
.

+
t

. . . . . . .. . .. .
. .

I I I

I 1 ' 5

. ..

. . .

. . _ _ . .

i i
. . . . . . . . . . . .

Fig. 4: Converter under average current mode control

. . , . .
,

. . . . . . . . . .
. .

. . . . . .

. . . . . . . . .. .

. .

c
-DTs

Different techniques have been proposed to analyze switching converters utilizing current mode control [3-51. The simplified PWM switch model will be used to analyze the system at hand and is shown in Fig. 5 [3].

i.

Fig. 3: Typical waveforms of the converter

Adopting current mode control ensures current sharing between the two output filter inductors. An inner current loop regulates the filter inductor currents while an outer voltage loop regulates the output voltage. In power supply applications operating in current limit, the inner current loop is the only active loop.

transformer Fig. 5: PWM switch model

Since the output current is the sum of the two output filter inductor currents, the system can be reduced to two parallel connected buck converters [7,8]. Furthermore, since the

2 04

output filter inductor currents are not individually regulated, the small signal model of the system can be reduced to that of a single buck converter with average current mode control where the resultant filter inductor is the parallel combination of the two output inductors. Although each inductor current is not separately regulated, any difference between the average currents will be corrected by the input dc blocking capacitor which maintains zero net dc flux within the: transformer. This guarantees that the two inductor currents, remain equal. Note that the effective switching frequency of the resultant system is twice the switching frequency for the two filter inductor currents are out of phase which results in frequency doubling at the output. Using the PWM switch model and assuming the transformer is ideal, the equivalent small signal model of the converter is shown in Fig. 6.
L. L =-+.

k : . I+- s ,
(7)

+
"0

This transfer function represents an integrator followed by a 1ea.d-lag network. T o ensure stability, the zero should be placed before the power stage filter frequency of the current loop where the phase shift of the integrator is canceled by the zero at half the switching frequency. The pole is normally placed above half the switching frequency to roll off the gain and thereby eliminate high frequency noise. Furthermore, this pole placement minimizes interaction with the current loop. By straightforward analysis, the control to output current loop transfer function is given by (1 1) q (s)= R, . H , ( s ) . G,(s).F, . F, (s) where

is the direct (forward) gain transfer function. 'The loop transfer function for a 5kW converter were computed using MATLAB and the results are shown in Fig. 7 (see appendix A).

Fig. 6: Small signal model of the converter

Here, Rs is the sense resistor, He(S) is the sampling gain, Fm is the modulator gain and Gc(s) is the compensation transfer function. The sampling and modulator gains are defined in [6]to be

Frequency ( Hz )
100 U

H e ( $ ) = 1+-+-F, =--where,
r)

: i

Qzun
1

2 OI,,

se+s;

(3)

; -100
2 c

a -200
-300 101
102
103
104

=-f n 0 ,= n f,$
Q
'

105

Frequency ( Hz ) Fig 7 Loop transfer function with average current control

In average current mode control, a possible current compensation transfer function is given by

It is clear from the above figure that the current loop can be stabilized with proper compensator design and without slope compensation. In fact, the compensator gain can be adjusted in a similar fashion to adding slope compensation in peak current mode systems. The gain margin of the current loop is 13.5dB and the phase margin is 67.7" while the current loop bandwidth is 1OkHz.

205

The corresponding closed loop transfer function of the system is shown in Fig. 8 and the output current step response is shown in Fig. 9.

Frequency In Hr

102

103

IO H

105

Fig 10 Loop transfer funcbon with average current control

Frequency ( Hz )

80.00

40.00

Frequency ( Hz ) Fig 8 Closed loop transfer function with average current control

1
3000U

DOOOU

1SOOU

21O.OU

279.011

TIME In Secs

Fig. I I : Output currents step response with average current control

o.os

(1.1

0.15

02

(1.2s

0.3

Time (ni,xccs)

Fig. 9: Output current step response with average current control

As expected, the output current overshoot is low (5%) and the system reaches steady state in 0.3ms. To verify the analysis results, a SPICE average model of the converter was simulated. In this case, the system was modeled as two parallel connected buck converters with a single output current loop. The resultant current loop transfer function is shown in Fig. 10 while the step response of the converter is shown in Fig. 11. It is clear from these figures that the simulation data match the analytical ones. Note also that the output filter current response is the same as the total output current.

Unlike average current mode control, since peak current control regulates the peak of the inductor currents, the average output current may not be regulated. In this case, the negative slope needs to be reconstructed or an outer average current loop can be used to regulate the output current. The implementation of the peak current loop control is similar to that of average current control except that the current sensing is done on the primary side of the transformer and no dc blocking capacitor is used. In this case, the switch currents in one leg can be sensed using current transformers. This offers one more level of protection since an active switch current limit is implemented. The small signal equivalent circuit with peak current mode control is shown in Fig. 12 [9]. Note that each of inductor currents are driven at half the actual duty cycle of the converter. Hence, in the small signal model, the duty cycle D needs to be halved.

III. Peak Current

ode Control Implementation

In applications where flux balancing is required on the primary side of the transformer and dc blocking capacitors are not used, peak current control can be adopted to ensure current sharing between the two inductors.

Ti *
Fig. 12: Small signal model with peak current mode control

206

In contrast to average current mode control small signal model, the peak current small signal model is more involved in that the two converters are coupl~scl via the common output filter capacitor. As a result, the sjstem can no longer be reduced to that of a single buck converter with peak current control. The equivalent control block diagram of the systern under peak current mode is shown i n Fig. 13.

Note that for L I = L ~ F,, , = : F12 and Fzz= F,,. To guarantee stability, each loop of the system must be stablc. Two current loops can be identified, a direct loop associated with each current with its corresponding duty cycle and a cross coupled loop with the ~ o ~ ~ l e r ~ e i duty ~tary cycle. These loops are given by,

P '

iJ

, implies that the phase E k e , the negative sign of T12 and T lag at the cross over frequency should be less than 360" as opposed to the conventional 180". The control to output transfer function may be evaluated

as

Fig. 13: Block diagram of the peak current control model

The transfer functions are computed using the average

(23) Tlhe condition for instability of the control to output transfer function (21) i s

H; = Rb7* H e

PWM switch model as shown in Fig. 14.

Fig. 14:Sinal1 signal cquivaleit circuit

which imposes an additional criteria for overall system stability. 'The converter of appendix A was further analyzed using MATLAB with peak current mode control. The direct and cross coupled loop transfer functions are shown in Fig. IS.

The direct (forward) gain transfer function is given by [ 101

where

Fij = i i / d j
The cross coupled transfer function is given by

(14)

Frequency ( Hz )

where

io I

102

L,, = Ll I 1 L2 R, = R N R ,
R, = R + R,

I03 104 Frequeiicy ( Hz )

105

Fig. 15: Direct and cross coupled loop gains

As shown above, both loops can be stabilized with slope compensation. In this case, the added slope, Se is assumed to

207

be one half the down slope of the output filter inductor currents, Sf or
, . .
L LL

80

60

5
d
E:

40

Again, note that the cross coupled loop phase margin is computed in reference to 360". The stability condition of (24) was evaluated and the results are shown in Fig. 16. The loop transfer function for a single converter case is overlaid for reference.

20
0
10'
102

103

104

105

Frequency ( H z )

1-1

101
101

102

103

104

105

102

103

104

105

Frequency ( Hz ) Fig. 17: Loop gains with peak current control, Se= -St

Frequency ( Hz )

,""

101

102

101

10a

105
10'

Frequency ( H z ) Fig. 16: Loop gains with peak current control, Se = -0.5 St

102

103

104

105

Frequency ( Hz )

As expected, the loop transfer response of a single converter is stabilized with the addition of slope compensation. Unlike the single converter case, the overall loop response of the system has higher gain and the phase characteristics reveal the presence of a low frequency pole and a high frequency zero which reduces the relative stability of the of the system. To improve stability of the current loop, more slope compensation may be added. Figure 17 shows the loop response with additional slope compensation where Se = -Sf. The resultant gain margin is 6.5dB while the phase margin is 4.5'. The closed loop transfer function of the system is shown in Fig. 18. A SPICE average model of the converter was simulated to verify the analysis results presented above. The system was modeled as two parallel connected buck converters with two individual peak current loops. The resultant closed loop transfer function is shown in Fig. 19, while the step response of the converter is shown in Fig. 20. As shown in Fig. 19, the simulated loop response matches the analytical model of Fig. 18.

101

102

103

104

105

Frequency ( Hz ) Fig 18: Closed loop gains with peak current control, Se = -St

40.00

30.00
I

i m

20.00

= :

10

o w
0

I
io0

I
1K Frequency in Hz

I
10K

Fig. 19: SPICE loop gains with peak current control, Se = -St

208

R.B. Ridley, B.H. Cho, F.C. Lee, "Analysis and Interpretation of Loop Gains of Multiloop-Controlled Switching Regulators," EEE Trens. on Power Electronics, vol. 3, No. 4, pp. 489-498, Oct. 1988. [8] K. Sin, C.Q. Lee, T.E. Wu, "Current Distribution Control of Para-llel Converters: P a t I," E E E Trans. on Aerospace and Electronic Systems, vol. 28, No. 3, pp. 829-840, July 1992. [SI R.B. Ridley, "A New Continuous Time Model for Current Mode C,ontrol," IEEE Trans. on Power Electronics, vol. 6, pp. 271-280, April [7]

1 1 1 1 -

2000u

6OOOU

101loIlU

14oou

18OOU

1991. [IO] 3. Rajagopalan, K. Xing, Y. Guo, F.C. Lee, B. Manners, "Modeling and Dynamic Analysis o f Paralleled DClDC Converters with MasterSlave Current Sharing Control," IEEE APEC Conf. Rec., ppl578-684, 1996.

TIME

in

Secs

Fig 20. Step re5ponse undcr peak carrent mode control

The analyzed 5kW converter data: V,,:=320 V V,=4& v, I,=100 A R==0.55 n a=2.5 fs=75 kWz

Lf=30 PH
In this paper, the analysis and implementation of peak and average current mode control teclhniques applied to a full bridge PWM converter with two inductor rectifier were discussed. The two inductor rectifkr circuit offers reduced secondary side current rating compared to a full bridge or center tapped rectifier topology and is suitable for high current applications. Furthermore, t h e two inductor rectifier can be modeled as two parallel buck converters. In average current mode control, the two converters are reduced to a single converter operating at twice the switching frequency. An integrator in series with a lead lag network ensuires stability o f the current loop. In contrast, the system in peak current mode control cannot b:: reduced to that of a sin& buck converter. This is due io the presence of cross coupling between the two converters for the output inductors share the same output filter capacitor. It has been shown that unlike the single converter case, the relative stability of the overall peak c!Jrrcnt loop is less than that of the single loop. As a result, more slope compensatior, may be required to improve the relative stability of the system.

c,,= 10000 pF
R,=0.045 L 2

R,=20

ma

R,=0.024

V,=5V (ramp pcak)

N.H. Kutkut, D.M. Divan, R.W. Gascoigne, "An Improved Zero Voltage Switching Full Bridge DC/DC Converter IJsing A Two Inductor Rectifier," IEEE Trans. on Industqr Applications, vol. 31, No.
I , pp. 119-126, JadFeb 1995. Black, Jackson and Jackscon, Eiectricir)! mu' Mugnetism and Their ilppiiccrtion r Macinilan Co., 19 19, pp 4313-13 1. V. Vorpcrian, "Simplified Analysis of I'Tv'M Converters Using the Model of PWM Switch: Parts I and 111,'' IEEE Trans. on Aerospace and Electronic Systems, vol. 26, No. 3, pp. 1.90-505, May 1990. S . I-Isu, A.R. Brown, L. Rensink, R.D, Middlebrook, "Modeling and Analysis of Switching DC-to-DC Conve:rt:rs in constant Frequency Current-Programmed Mode," IEEE PESC Conf. Rec., pp. 284-301, 1979. 1R.D. Middlebrook, "Topics in Multip1e-~.oOpRegulators and Current Mode Programming," E E E PESC ConF. Rc,;., pp. 716-732, 1985. 'W. Tang, F.C. Lee, R.B. Ridley, "Small-,Sipd Modeling of Average Current-Mode Control," E E E Trans. on Power Electronics, vol. 8, No. 2, pp. 112-1 19, April 1993.

209