Department of Electrical and Computer Engineering

ELEC 499B

LCC Resonant Inverter

For A High Frequency Distributed Power System

July 28, 2006

Project Supervisor: Dr A.K.S. Bhat

Matt Weber (02-32601)

Tyler Nitsch (01-31768)
Sean Clutterbuck (00-29577)
Geoff Lindsay (02-35351)
Abstract

An LCC Resonant Inverter is proposed for applications in high frequency

distributed AC power systems. The advantages of the LCC topology are low
total harmonic distortion (THD) high efficiency and the ability to handle varying
loads. Design of the LCC resonant tank was based around previously developed
theory. This report documents one LCC configuration with a variety of load
configurations.

A microprocessor approach is taken over previous fixed frequency phase shift

circuitry and FPGA chips to provide a lower cost solution to pulse width
modulation control. This also enables later development of a more robust closed
loop design.

Efficiencies greater than 90% were obtained down to resistive loads of 50%.
Efficiencies greater than 75% were obtained at significantly reduced loads (11%).
Operation above resonance was utilized to increase the efficiency and maintain
zero voltage switching (ZVS) for varied loads. Total harmonic distortion (THD) of
less than 10% was achieved for all resistive loads.

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay Page i

Table of Contents
1. Introduction ................................................................................................1
Problem .............................................................................................................1
Project Specifications ........................................................................................2
2. Applications................................................................................................3
3. Construction ...............................................................................................4
Components ......................................................................................................4
H-Bridge..........................................................................................................4
Driver Board....................................................................................................4
Microcontroller Gate Generator.......................................................................4
Fixed Frequency Phase Shift Board ...............................................................4
LCC Resonant Tank .......................................................................................4
LCC Configuration.............................................................................................5
Driver Board ......................................................................................................6
Bridge Board .....................................................................................................7
Fixed Frequency Phase Shift Board..................................................................9
ATmega8 Microcontroller ................................................................................10
4. Analysis....................................................................................................11
Design Calculations, Theoretical Output Values and Harmonic Analysis........11
Snubber Calculations ......................................................................................14
5. Simulation Results ...................................................................................15
Full Load Resistive Load Simulation Results ..................................................16
11% Load Resistive Load Simulation Results .................................................17
Full Load Inductive Load Simulation Results...................................................18
Full Load Capacitive Load Simulation Results ................................................19
Summary of Simulation Results ......................................................................20
6. Experimental Results ...............................................................................21
Summary of Experimental Results and Efficiency ...........................................27
Summary of Load Values ................................................................................27
7. Harmonic Analysis ...................................................................................28
Current Total Harmonic Distortion for Varied Resistive Loading .....................32
8. Discussion................................................................................................33
Microcontroller Selection and Programming Challenges.................................33
Choosing of the LCC .......................................................................................34
Concluding Comments ....................................................................................35
9. Recommendations ...................................................................................36
Closed Loop Design ........................................................................................36
LCC Resonant Tank Optimization ...................................................................36
Packaging .......................................................................................................37
10. References...............................................................................................38
11. Appendices ..............................................................................................39
ATmega8 Microcontroller Code.......................................................................39

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay Page

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Table of Figures
Figure 1 - Simulation Circuit................................................................................15
Figure 2 - VAB and ILs at Full Load Resistive Load ..............................................16
Figure 3 Vout and Iout at Full Load Resistive Load................................................16
Figure 4 - VAB and ILs at 11% Load Resistive Load .............................................17
Figure 5 - Vout and Iout at 11% Load Resistive Load ............................................17
Figure 6 - VAB and ILs at Full Load Lagging Power Factor ...................................18
Figure 7 - Vout and Iout at Full Load Lagging Power Factor ..................................18
Figure 8 - VAB and ILs at Full Load Leading Power Factor ...................................19
Figure 9 - Vout and Iout at Full Load Leading Power Factor ..................................19
Figure 10 – VAB and ILs at Full Load Resistive Load............................................22
Figure 11 - Vout and Iout at Full Load Resistive Load ...........................................22
Figure 12 - VAB and ILs at 50% Load Resistive Load ...........................................23
Figure 13 - Vout and Iout at 50% Load Resistive Load ..........................................23
Figure 14 - VAB and ILs at 11% Load Resistive Load ...........................................24
Figure 15 - Vout and Iout at 11% Load Resistive Load ..........................................24
Figure 16 – VAB and ILs at Full Load Lagging Power Factor ................................25
Figure 17 – Vout and Iout at Full Load Lagging Power Factor ...............................25
Figure 18 – VAB and ILs at Full Load Leading Power Factor ................................26
Figure 19 – Vout and Iout at Full Load Leading Power Factor ...............................26
Figure 20- Full Load Current Spectrum...............................................................29
Figure 21 - Full Load Voltage Spectrum .............................................................29
Figure 22 - 50% Load Current Spectrum ............................................................30
Figure 23 - 50% Load Voltage Spectrum ............................................................30
Figure 24 - 11% Load Current Spectrum ............................................................31
Figure 25 - 11% Load Voltage Spectrum ............................................................31

Table 1 - Final LCC Resonant Tank Components ................................................5

Table 2 - Summary of RMS Current and Voltage from Simulation Results.........20
Table 3 - Summary of Experimental Results and Efficiency Calculations ...........27
Table 4 - Summary of Load Values.....................................................................27
Table 5 – Current Total Harmonic Distortion for Varied Resistive Loading .........32

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay Page

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1. Introduction
Problem

The increased use of distributed power systems (DPS) in recent years has driven
the need for high efficiency power conversion techniques. Resonant inverters
have come to be recognized as the next generation of power conversion circuits
due to low component costs, small component sizes and high efficiency. Power
systems for avionic applications require high frequency, high efficiency
conversion systems, making resonant inverters ideal.

Recent research by several authors [1, 2, 3] has shown that LCC topology
resonant inverters have a number of desirable features as compared to series or
parallel topologies. Designing an LCC-type resonant inverter that can operate
under resistive and reactive loads is still a challenging process. Efforts to improve
the efficiency under varying loads have shown good promise. We intend to focus
primarily on designing a LCC topology to handle varied loads while maintaining
constant output voltage with low total harmonic distortion (THD).

While LCC topologies have been designed and tested for various applications,
we intend to replace the FPGA phase shifter circuitry with a microcontroller. The
microcontroller approach is ideal considering the rising cost of high frequency
FPGAs.

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay Page

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Project Specifications

A High-Frequency DC/AC Power Inverter is proposed which is capable of

supplying power to an AC bus with varying loads. Design parameters have been
taken from previous work [1, 2, 3] and LCC configuration is based on these
parameters. Zero voltage switching (ZVS) at full load ensures very low losses in
the bridge circuit while at reduced loads the mode of operation in the MOSFET
switches in one arm of the bridge is zero current switching (ZCS). By adjusting
the resonant frequency of the LCC tank we intend to maximize the range of ZVS
and therefore increase the total efficiency of the bridge.

Having decided on an LCC resonant inverter topology our primary efforts will be
towards optimizing the LCC parameters for the highest efficiency given varying
loads. Considerable efforts will also be devoted to designing a microcontroller
circuit to mimic existing fixed frequency phase shift circuits.

Preliminary Specifications for our circuit are:

Input Voltage 40-60V DC

Output Power ~250 VA
Output Voltage ~ 28 VRMS
Output Current ~ 10 A
Output Frequency 20 kHz
Minimum Load Power Factor unity, 0.9 leading, 0.9 lagging
Minimum Load Efficiency In excess of 80%
Full Load Efficiency In excess of 90%

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2. Applications

The target application for LCC resonant inverter topology detailed in this report is
a high frequency distributed bus. A high frequency distributed bus implies a rail-
like system where multiple loads can be connected in parallel to the same
inverter output.

The LCC resonant inverter topology has a number of advantages over other
simpler topologies such as the parallel and series resonant topologies. Some of
the advantages of the LCC topology are:

• Low total harmonic distortion (THD)

• Low electromagnetic interference (EMI)
• High efficiency
• Load independence
• Power factor stability
• Small component size
• Low component cost

LCC resonant inverter topologies are currently being used in the aerospace and
aeronautics industries. For example, the international space station combines
multiple LCC resonant inverters to convert the DC power produced by solar
panels to a high frequency AC bus which supplies power throughout the space
station. At high frequencies, the LCC resonant inverter components are very
small. Smaller components yield a lighter inverter which is desirable for
aerospace applications. Aircraft also utilize an LCC topology to provide efficient
and highly reliable power throughout the aircraft. Obviously aircraft require highly
reliable power sources to supply power to electronics and control circuitry.

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay Page

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3. Construction
Components

H-Bridge
• 4 x IRPF3710 HEXFET Power MOSFETs
• Power H-Bridge PCB
• 1 x 2µF High Frequency High Voltage Bias Capacitor
• 1 x 10µF High Voltage Bias Capacitor
• 4 x 1.9nF, 100Ω (1/4 Watt) Snubber Circuits
• 4 x MOSFET Bolt Mounted Heat Sinks

Driver Board
• Driver Board PCB
• 2 x IR2110 High Power, High Frequency High and Low Side Drivers
• 2 x A 2630 Dual Channel Optocouplers
• 1 x CD4081BE CMOS Quad 2-Input AND Gate
• 1 x HCF4049UBE CMOS-Input Level Translator - Hex Inverting Buffer

Microcontroller Gate Generator

• ATmega8 Microcontroller
• 16MHz Crystal Oscillator

Fixed Frequency Phase Shift Board

• Fixed Frequency Phase Shift Board (Prebuilt)
• 1 x UC3875N Phase Shift Resonant Controller

LCC Resonant Tank

• 3 x Syntax Generic Protoboards
• 2 x High Frequency Magnetic Cores
• 9 x 0.1µF High Frequency High Voltage Capacitors

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LCC Configuration

An LCC topology was designed based on recommendations and references from

Dr. A.K.S. Bhat. The benefits of the LCC topology are mentioned previously.

The LCC components were calculated as is shown in the analysis section of this
report. Design parameters Qs and Cn were very important to the design of the
LCC resonant tank. Other important parameters included the ratio of the
switching frequency (fsw) to the resonant frequency of the tank (fr) and the LCC
tank gain. By reviewing reference papers values of Cn and Qs were chosen as 2
and 4 respectively. The frequency ratio (y) was chosen such that the circuit
would operate above resonance and thus all 4 switches would operate in zero
voltage switching. A resonant frequency was chosen as 19kHz initially and
simulations confirmed that this would ensure zero voltage switching at full load.

Once Qs, Cn and y were chosen, the LCC resonant tank gain was computed and
the value of Ls and the load resistance were finalized. Simulations verified this
design and a number of other scenarios were simulated to assure that this
design performed better. Final LCC component values are shown in Table 1
below.

Table 1 - Final LCC Resonant Tank Components

Transformer Winding
Ls Cs Cp (on secondary)
Ratio

174.5µH 400nF 350nF 1.357

The LCC resonant tank gain was not sufficient to bring the 48VDC rail voltage
down to the specified 28VRMS output. As such, a step-down transformer was
hand-wound to bring the RMS output voltage down to 28V. Another benefit of
the step-down transformer is that it serves to electrically isolate the load from the
bridge circuit. The transformer ratio was to be 1.357 but in practice a slightly
higher ratio was achieved.

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay Page

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Driver Board

The output power of both the fixed frequency phase shift board and the
ATmega8 microcontroller was too low to properly gate the MOSFET switches. As
such, a driver board was necessary as an intermediate circuit between the gating
circuitry and the bridge board.

The main purpose of the driver board is to amplify the gating signals to the
appropriate voltage levels with sufficient current to turn on the MOSFET
switches. The driver board also acts to isolate the gating circuitry from the bridge
board. Additionally the driver board provides current to charge the MOSFET
internal capacitance before gating. This serves to protect the MOSFET’s. Along
with these attributes the driver board was designed to provide gating signals to
MOSFET’s within an H-bridge and as such handles other possibly inherent
behaviors of such a circuit.

Fortunately the board design was provided by Dr. A.K.S. Bhat, along with an
empty PCB to construct the driver board on.

The basic driver board components were obtained from the engineering lab
technicians in ELWB320. The integrated circuits as well as large high frequency
capacitors were obtained from Dr. A.K.S. Bhat. Construction of the driver board
was performed in ELWB320, using the high end soldering equipment. All team
members participated in this phase, providing a valuable experience in
electronics assembly.

Once the driver board was constructed, Deepak Gautam helped our team test its
function using a proven MOSFET H-bridge. Testing was immediately successful,
allowing us to proceed to the next phase of the project.

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Bridge Board

Due to the large currents in the H-bridge circuit, a special PCB was required to
ensure safe operation. Fortunately a generic H-Bridge PCB was provided by Dr.
A.K.S. Bhat. The circuit schematic for the generic board was also provided and
gave us a starting point.

The H-bridge schematic was analyzed to determine which components would

have to be soldered onto the PCB and where. Due to the complexity of the circuit
given, Dr. A.K.S. Bhat was consulted for all changes deemed necessary.

Snubber Circuits

Snubber circuits are required across each MOSFET switch to protect them
during turn-on and turn-off from voltage and current transients. When a MOSFET
switch is operating with zero voltage switching (ZVS) lossless snubbers are
adequate. Lossless snubbers consist of only a capacitor. When a MOSFET
switch is operating with zero current switching (ZCS) lossy snubbers are
necessary to dissipate the high current through the snubber circuit. Lossy
snubbers consist of a capacitor and a resistor in series. The final snubber circuit
calculations are detailed in the analysis section of this report.

During testing of the bridge circuit the snubber circuits were targeted as a
possible cause of the input DC voltage ripple. Snubber values were recalculated
for worst case scenarios and implemented. This did not solve the problem with
the DC voltage ripple.

The main considerations in calculating the snubber components were the

MOSFET fall time and the dead gap time between consecutive gating pulses.
The reason that the snubber circuit was required to complete its discharge period
before gating the next MOSFET is to prevent a momentary short circuit across
the H-bridge.

Bias Capacitor

A 2uF high frequency capacitor was connected across the input DC terminals to
further clean up the DC input voltage. It was thought that this would be sufficient
to smooth any ripple seen on the DC voltage, but this was not the case. During
the first testing phase a large high frequency ripple was observed on the output
of H-bridge (VAB). Some variation in VAB is expected due to the varying loss in the
MOSFETs as the current varies sinusoidally, however the observed variation was
clearly too great. Initially the variation was thought to be a result of an oscillation
occurring between the bridge capacitances and the series inductor within the
LCC. This theory was put to rest when a proven bridge board was connected
and a similar ripple was observed. As mentioned above, the snubber circuitry
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was analyzed to ensure it was not the cause of the ripple observed. Finally a
10uF capacitor was added in parallel across the DC voltage and the ripple was
significantly reduced.

Heat Sinks

Heat sinks were mounted on the MOSFET switches to assist in heat dissipation.
Under normal ZVS operation, the switches do not heat up, however when the
load is reduced, the operation of the MOSFETs within the right arm of the H-
bridge changes to ZCS and significant heating of the MOSFETs is noticable.

Due to the geometry of the H-bridge and the heat sinks available to us, we were
forced to mount two of the MOSFET switches on the top side of the PCB in order
to avoid contact between the heat sinks themselves.

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay Page

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Fixed Frequency Phase Shift Board

Once the driver board and the H-bridge were constructed, a means of generating
gating pulses to the MOSFETs with appropriate dead gap time and phase
shifting ability for pulse width modulation was required. Two approaches were
available: (1) Fixed Frequency Phase Shifting Board, (2) ATmega8
microcontroller.

A fixed frequency phase shift board was available but it was designed to operate
at a switching frequency of 100kHz. Modifications to the board were required in
order to use it at 20kHz. The following changes were made to the fixed frequency
phase shift board:

• Series resistor added to the frequency control potentiometer to change the

range of operating frequencies.
• Parallel resistors added to the reference voltage resistor to bring the
reference voltage into the proper range
• Ramp potentiometer added in order to properly vary the dV/dt rise of the
ramp function. This allowed proper phase shifting at 20kHz.

The fixed frequency phase shift board was used for all experimental results and
the demonstration because it was easy to adjust the pulse width modulation for
varying loads. The ATmega8 controller was tested to ensure that operation
exactly duplicated the fixed frequency phase shift board however it required
reprogramming for different pulse widths.

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay Page

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ATmega8 Microcontroller

The ATmega8 microcontroller was used to perform the same function as the
fixed frequency phase shift board. The ATmega8 microcontroller was chosen
because it is a smaller and cheaper solution to PWM gating pulse generation.
Assembly language was chosen as the platform for coding the microcontroller
and a custom programming jig was available from the engineering lab
technicians.

The code was generated by using the microcontroller timer interrupts to toggle
output pins between high state (+5V) and low state (0V). A difficulty realized in
this approach was the clock frequency of the microcontroller. It was decided that
the internal clock was both too slow and too unreliable to adequately generate
the 20kHz gating pulses to the MOSFETs. As a solution to this, an external clock
with frequency 16MHz was connected to the microcontroller. This external clock
provided highly reliable timing to the microcontroller. The interrupt flags were
triggered when timer counter compare register (TCCR1B) matches either of two
high values.

A 40kHz control signal was generated. The falling edge of the control signal was
used as a trigger for the phase shifted gating pulses while the stable rising edge
was used to generate the non-shifted gating pulses. The maximum time delay
between the rising edge and the falling edge corresponds to the full load 50%
duty cycle pulse train to the MOSFETs. A sufficient dead gap is ensured by a
delay routine that has been programmed to generate an 800ns dead gap. This
can be adjusted down to 3-5 clock cycles. This introduces a limitation in the
gating frequency that can be achieved with this implementation.

The current implementation of the microcontroller requires reprogramming of the

controller whenever the duty cycle requires tuning. This is not ideal for testing
but can be overcome by connecting an adjustable input voltage signal and
scaling the value over the range of duty cycle tuning.

The actual assembly language code is attached in the first appendix of this
report.

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4. Analysis
Design Calculations, Theoretical Output Values and Harmonic
Analysis
Circuit Parameters

fsw := 20kHz fr := 19kHz D := 1 V ≡ 48volt ωr := 2πfr

fsw 38
y := y = 1.053 k := k is the transformer winding ratio
fr 28

Design Calculations

2 2V
sin ⎜
⎛ D⋅ π ⎞
Vin := ⎟
π ⎝ 2 ⎠
Vin = 43.215V
Cn := 2
Qs := 4
2⋅ 2 y ⎛ D⋅ π ⎞
⋅ sin ⎜
V_gain := ⋅ ⎟
π
y ⋅ ⎛⎜ 1 +
1 2 1
−y ⋅ ⎟ ( )
⎞ + i⋅ Qs ⋅ y 2 − 1 ⎝ 2 ⎠
⎝ Cn Cn ⎠
V_gain = 0.873
Vout := Vin⋅ V_gain
Vout = 37.729V
−9
Cs := 400⋅ 10 farad
−7
Cs = 4 × 10 F
2 −9
Cp := k ⋅ 200⋅ 10 farad
−7
Cp = 3.684 × 10 F
1
Ls :=
2
ωr ⋅ Cs
−4
Ls = 1.754 × 10 H
ωr⋅ Ls
R_load :=
2
k ⋅ Qs
R_load = 2.842Ω
2
Vout
rating :=
2
k R_load
rating = 271.902W
ωsw := 2⋅ π⋅ fsw
1
Tsw :=
fsw

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Equivalent Impedance Computations
X_load ( n ) := n ⋅ ωsw ⋅ L_load Inherent Inductance X_load ( 1) = 0.729Ω
i⋅ X_load ( n )
RL_load( n ) := R_load + RL_load( 1) = 2.87Ω
2
k Primary Side Load
1
Xcp( n ) :=
Cp
ωsw ⋅ n ⋅
2
k
1
Xcs ( n ) :=
ωsw ⋅ n ⋅ Cs

Xl( n ) := ωsw ⋅ n ⋅ Ls

−i⋅ Xcp( n ) ⋅ RL_load( n )

Zparallel( n ) :=
( −i⋅ Xcp( n ) ) + ( RL_load( n ) )

Zs ( n ) := i⋅ Xl( n ) − i Xcs ( n )

Zeq ( n ) := Zs ( n ) + Zparallel( n )

φ( n ) := atan ⎛⎜ ⎞
Im( Zeq ( n ) )
⎟
⎝ Re( Zeq ( n ) ) ⎠

VAB Calculations
⎛ 4⋅ V ⋅ sin ⎛ n⋅ π ⎞ ⋅ sin ⎛ D⋅ n ⋅ π ⎞ ⋅ sin ( n⋅ ωsw ⋅ t) ⎞
Vab( n , t) := ⎜ ⎜ ⎟ ⎜ ⎟ ⎟
⎝ n⋅ π ⎝ 2 ⎠ ⎝ 2⎠ ⎠

1
2
⎛ Tsw ⎞
⎜ ⌠ 2 ⎟
⎜ 2 ⎮ 2 ⎟
Vabrms( n ) :=
⎜ Tsw ⋅ ⎮
⌡
Vab( n , t) dt
⎟
⎝ 0 ⎠
Vabrms( 1) = 43.215V
Vabrms( 3) = 14.405V
Vabrms( 5) = 8.643V
Vabrms( 7) = 6.174V
Vabrms( 9) = 4.802V
Vabrms( 11) = 3.929V
Vabrms( 13) = 3.324V

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Output Voltage Across the Parallel Capacitor

Vab( n , t)
Io( n , t) :=
Zeq ( n )
Io( n , t) ⋅ Zparallel( n )
Vcp( n , t) :=
k
1
2
⎛ Tsw ⎞
⎜ ⌠ 2 ⎟
⎜ 2 ⎮ 2 ⎟
Vcprms( n ) :=
⎜ Tsw ⋅ ⎮
⌡
Vcp( n , t) dt
⎟
⎝ 0 ⎠
Vcprms( 1) = 24.781V
Vcprms( 3) = 0.581V
Vcprms( 5) = 0.248V
Vcprms( 7) = 0.166V
Vcprms( 9) = 0.124V
Vcprms( 11) = 0.079V
Vcprms( 13) = 0.051V
Output Current Through the Load

Vcprms( n )
Iorms( n ) :=
Zparallel( n )
Iorms( 1) = 8.571A
Iorms( 3) = 0.177A
Iorms( 5) = 0.06A
Iorms( 7) = 0.03A
Iorms( 9) = 0.018A
Iorms( 11) = 0.012A
−3
Iorms( 13) = 9.917 × 10 A
13
Ilrms := ∑ Iorms( n ) Ilrms = 8.571A
n =1

13
Vlrms := ∑ Vcprms( n ) Vlrms = 24.781V
n =1

Output Current Total Harmonic Distortion

2 2 2 2 2 2
Iorms( 3) + Iorms( 5) + Iorms( 7) + Iorms( 9) + Iorms( 11) + Iorms( 13)
THD :=
Iorms( 1)

THD = 2.219%

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Snubber Calculations

Iturnoff ≡ 10amp
tfall ≡ 48ns
Vdc ≡ 48volt
tdeadgap ≡ 800ns
Iturnoff ⋅ tfall −8
Csnubber_max := Csnubber_max = 1 × 10 F
Vdc

Csnubber ≡ 1.9nF
tdeadgap
Rsnubber := Rsnubber = 105.263Ω
4⋅ Csnubber

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5. Simulation Results

The evaluation version of PSIM was used to model the LCC topology for varied
loads and LCC configurations. The test circuit is shown in Figure 1 below. All
components are assumed to be ideal for the simulation and the measured
leakage inductance of the transformer is incorporated in the series inductor (Ls).
The circuit in Figure 1 is used to model for the resistive load in the lab. The
resistors had an intrinsic inductance which has been added in as Lload.

Figure 1 - Simulation Circuit

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Simulations were conducted for a number of different load configurations. Below
are some of the simulation results that were compared to experimental results.

Full Load Resistive Load Simulation Results

Figure 2 - VAB and ILs at Full Load Resistive Load

Figure 3 Vout and Iout at Full Load Resistive Load

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11% Load Resistive Load Simulation Results

Figure 4 - VAB and ILs at 11% Load Resistive Load

Figure 5 - Vout and Iout at 11% Load Resistive Load

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Full Load Inductive Load Simulation Results

Figure 6 - VAB and ILs at Full Load Lagging Power Factor

Figure 7 - Vout and Iout at Full Load Lagging Power Factor

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Full Load Capacitive Load Simulation Results

Figure 8 - VAB and ILs at Full Load Leading Power Factor

Figure 9 - Vout and Iout at Full Load Leading Power Factor

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Summary of Simulation Results

Table 2 - Summary of RMS Current and Voltage from Simulation Results

ILS (ARMS) Iout (ARMS) Vout (VRMS)

Full Load Resistive 12.0804 9.14905 31.002
11% Load Resistive 2.22031 1.0695 32.6106
Full Load Inductive 9.44276 7.65811 30.7639
Full Load Capacitive 20.1222 13.5684 52.2439

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6. Experimental Results

In the following pages oscilloscope plots for a variety of actual loads are
presented. The scaling factor on the high frequency current probe that was used
did not give consistent results and as such, digital multi-meters were used to
measure the RMS current through both the load and the series inductor. Digital
multi-meters were also used to measure the RMS output voltage, the average
DC input current and the DC rail voltage. Inductance and capacitance was
measured and verified using the 1kHz RLC probe in ELWB303.

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 Figure 10 – VAB and ILs at Full Load Resistive Load

Figure 11 - Vout and Iout at Full Load Resistive Load

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 Figure 12 - VAB and ILs at 50% Load Resistive Load

Figure 13 - Vout and Iout at 50% Load Resistive Load

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 Figure 14 - VAB and ILs at 11% Load Resistive Load

Figure 15 - Vout and Iout at 11% Load Resistive Load

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 Figure 16 – VAB and ILs at Full Load Lagging Power Factor

Figure 17 – Vout and Iout at Full Load Lagging Power Factor

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 Figure 18 – VAB and ILs at Full Load Leading Power Factor

Figure 19 – Vout and Iout at Full Load Leading Power Factor

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Summary of Experimental Results and Efficiency

Table 3 - Summary of Experimental Results and Efficiency Calculations

IDC (Amps) VDC (V) Iout (ARMS) Vout (VRMS) Efficiency

Full Load Resistive 4.36 48.10 7.60 24.57 93.64%
50% Load Resistive 2.10 48.00 3.81 24.56 93.61%
11% Load Resistive 0.51 48.10 0.78 24.50 76.09%
Full Load Inductive 3.20 48.00 7.05 19.21 88.17%
Full Load Capacitive 9.30 48.20 12.30 31.59 86.68%

Summary of Load Values

The resistance was measured using an RMS Fluke digital multi-meter (DMM).

Table 4 - Summary of Load Values

Resistance (Ω) Inductance (µH) Capacitance (µF)

Full Load 3.30 5.80 -
50% Load 6.50 8.90 -
11% Load 30.00 41.40 -
Inductive Load 3.30 18.40 -
Capacitive Load 3.30 5.80 3.00

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7. Harmonic Analysis
In the following pages, oscilloscope plots of the Fourier transforms of the output
current and voltage. The input current harmonics were analyzed to try and
obtain an expression for the total harmonic distortion. Harmonic analysis was
only performed on the resistive load as true capacitive loading was not possible.
Nor was true resistive loading possible due to the inherent inductance of the Lab-
Volt resistance boxes.

The power levels were measured relative to the fundamental at 20kHz.

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 Figure 20- Full Load Current Spectrum

Figure 21 - Full Load Voltage Spectrum

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 Figure 22 - 50% Load Current Spectrum

Figure 23 - 50% Load Voltage Spectrum

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 Figure 24 - 11% Load Current Spectrum

Figure 25 - 11% Load Voltage Spectrum

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Current Total Harmonic Distortion for Varied Resistive Loading

Table 5 – Current Total Harmonic Distortion for Varied Resistive Loading

3rd 5th 7th 9th

Fundamental Harmonic Harmonic Harmonic Harmonic THD
Full Load Resistive 0 -31.88 -23.12 -34.36 -39.36 7.75%
50% Load Resistive 0 -35.2 -26.56 -60 -34.68 5.34%
11% Load Resistive 0 -60 -21.25 -60 -60 8.66%

*All values are relative dB.

**All dB levels were measured relative to the fundamental output current.

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8. Discussion
The project was prepared, constructed and tested in the power lab (ELWB303)
under the supervision of Dr. A.K.S. Bhat. Soldering was completed in ELWB303
with a basic soldering iron or in ELWB320 with the lab technicians’ high end
soldering iron. Programming of the ATmega8 microcontroller was complete in
the designated ELEC499 lab on a PC.

This project design was chosen by Dr. A.K.S. Bhat to help us to gain
understanding and familiarity with inverter topologies, power electronic
equipment and test procedures as well as the many obstacles and uncertainties
involved in construction of such a circuit. The LCC topology was given as a
starting point for reasons involving simplicity, stability of the design and
previously explored design curves. Our challenge was two-fold: (1) design a
microcontroller solution to generate gating signals to the MOSFET switches and
(2) choose and optimize an LCC configuration from the design parameters.
There were a number of obstacles to overcome during the design of both
challenges.

Microcontroller Selection and Programming Challenges

Choosing the correct microcontroller for the job was the first obstacle to
overcome. Due to the high frequency of the output signals it was not
immediately clear than standard output pins on the microcontroller IC would be
fast enough. The manual for the microcontroller was exhaustively explored for
an answer to this problem to no avail. Eventually, test algorithms were created to
determine if the microcontroller outputs would be fast enough. Initially, it was
thought that only the PWM output pins would be fast enough but this proved to
be untrue and standard output pins were used to output the gating signals.

The second challenge, and the more pertinent, was choosing an algorithm for the
gating pulse generation. A variety of approaches were explored and finally a
solution was reached using a control signal at double the output gating
frequency. This method is similar to a previously explored method [4]. The rising
edge of the control waveform is used to trigger the gating pulses to one arm of
the H-Bridge while the falling edge is used to trigger the gating pulses to the
other arm of the bridge. By varying the elapsed time between the rising and
falling edge (essentially, manipulating an output compare register value) pulse
width modulation was achieved.

Due to time constraints a method to vary the pulse width modulation externally
(ie. an adjustable reference voltage via a potentiometer) was not completed.

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Further work on this design would begin by first incorporating an external control
leading naturally into a closed loop design.

Choosing of the LCC

The LCC topology was recommended by Dr. A.K.S. Bhat based on previously
published results. The target application for the LCC resonant inverter
constructed here is a high frequency distributed bus. The LCC topology is
advantageous for this design for a number of reasons mentioned above. Choice
of the LCC resonant tank components was a difficult task involving numerous
calculations and recalculations.

The first approach that was taken was to calculate arbitrary values of series
inductance and series capacitance based on the resonant frequency that was
required for this application. After closer inspection of the reference papers it
was realized that a more rigorous method of choosing LCC tank values was
needed. At this point, MathCAD was utilized to calculate the LCC resonant tank
gain and the output voltage at various stages of the circuit. With this in mind, the
remaining LCC tank values were calculated using proven design parameters.
The ratio of Ls (series inductance) to the load resistance for example, is an
important design parameter. Below are the two most important equations for
LCC resonant tank design.

Cs ωr⋅ Ls
Cn := Qs :=
Cp R_load

Once this approach was verified, construction of the LCC resonant tank began.
It soon became clear that the initial capacitances that were calculated would not
be available and some recalculation was necessary. By selecting the capacitors
beforehand and using these values to calculate the gain of the LCC resonant
tank we were able to construct a new set of boundary conditions for the
calculation of the series inductor. Final LCC tank configuration is available in
Table 1.

Exact values of the series and parallel capacitors were not available and they
were constructed from series and parallel combinations of 0.1µF high frequency,
high voltage capacitors. The series inductor was hand wound around a high
frequency magnetic core. The step down transformer was also hand wound
around a similar high frequency magnetic core. Capacitance and inductance
was verified using a 1kHz RLC multi-meter.

Matt Weber, Tyler Nitsch, Sean Clutterbuck, Geoff Lindsay Page

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Concluding Comments

Above all else a high level of confidence with high power equipment and
measurement techniques was gained. The experience in design, redesign,
circuit troubleshooting and simulation was invaluable. The targeted design
constraints, including efficiency, output voltage and output power, were met
successfully. An important factor in the test procedure was the self inductance of
the Lab-Volt resistance boxes. This prohibited measurement of a purely resistive
load and hindered efforts to accurately vary the power factor. Another important
consideration to mention is the disproportionate variation of the inherent
inductance with decreased load. As the load was decreased the inductance
increased dramatically making 11% load results nearly meaningless as the
power factor of the load was so low.

Despite the aforementioned difficulties, high efficiencies were achieved. At full

resistive (partially inductive) load an efficiency of 93.64% was obtained with less
than 7.75% total harmonic distortion (THD). As the load was decreased,
efficiencies remained high. At 11% load the efficiency of the circuit was
measured as 76.09% with THD of 8.66%. The fact that the large inherent
inductance did not significantly affect the result obtained at reduced loads helps
to validate the operation of the LCC resonant tank.

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35
9. Recommendations

The LCC resonant inverter topology constructed for this project serves as a
strong foundation for a marketable high frequency distributed bus inverter.
Before marketing this device there are a number of foreseeable developments
that would need to be first added. First, the LCC resonant inverter would have to
have a closed loop control circuit built in to adjust the pulse width as the load
varied. Second, the LCC topology described in this report needs optimization.
Finally, the LCC resonant inverter could be designed and packaged in a space
efficient manner.

Closed Loop Design

Closed loop design implies that as the load current changes the pulse width
modulation used to control the bridge output voltage would be automatically
adjusted. By varying the output of the bridge the power delivered to the load is
varied thus maintaining the 28VRMS output across the load terminals (also the
parallel capacitor terminals). By programming the gate pulse generation into a
microprocessor this closed loop design would be a simple addition to the inverter
package. A reference voltage take from the output could be monitored and
scaled to control the duty cycle of the control waveform thus varying the duty
cycle of the bridge output voltage.

LCC Resonant Tank Optimization

Due to limitations of available components and measurement equipment the

capacitors and inductors in the LCC tank were subject to some drift from the
ideal. If it were possible to construct the exact components needed then it would
be possible to achieve a more ideal tank gain. Another method of optimizing the
circuit is to adjust the switching frequency slightly to vary the ratio of the resonant
frequency to the switching frequency. This method also varies the values of the
resonant tank and recalculation is again required. A limitation of winding the
inductor and the transformer was realized in the 1kHz test frequency output by
the multi-meter. Ideally, a more precise method of measuring the inductance and
the transformer inductance would have aided in the implementation of the LCC
tank and could be utilized to optimize the design at a later date.

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Packaging

Before finalizing a marketable product some consideration of packaging and

documentation would need to be decided upon. Packaging should be tailored to
suit applications in aerospace and aeronautics where size and weight are
paramount. Documentation should also be compiled listing key operating
parameters of the entire LCC resonant inverter. This last would require more
sophisticated test gear and much more lab time.

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10. References

[1] A.K.S. Bhat, “Fixed Frequency PWM Series-Parallel Resonant Converter”, in

IEEE Transactions on Industrial Electronics. October 1992, Vol. 28, No. 5, pp
1002-1009.

[2]J. A. Sabate, M.M. Jovanic, F.C. Lee, R.T. Gean, “Analysis and Design-
Optimization of LCC Resonant Inverter for High-Frequency AC Distributed Power
System”, in IEEE Transactions on Industrial Electronics. February 1995, Vol. 42,
No. 1, pp 63-71.

[3] A.K.S. Bhat, Shashi B. Dewan, “A Generalized Approach for the Steady-State
Analysis of Resonant Inverters”, in IEEE Transactions on Industrial Electronics.
March/April 1989, Vol. 25, No. 2, pp 326-338.

[4] Dhaval B. Dalal, “A 500kHz Multi-Output Converter with Zero Voltage

Switching”, in Digital Equiptment Corporation, IEEE, 1990. pp 265-274.

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11. Appendices

ATmega8 Microcontroller Code

;-------------------------------------------------------------------------------------------------
;MOSFET Gating Pulse Generation for the ATMEL ATmega8.
;
;Authors: Tyler Nitsch, Sean Clutterbuck, Matt Weber, Geoff Lindsay.
;Date: July 2006.
;
;General Description of Approach:
;
;We are using PORTB1,2,3,4 as our output gating signals
;It must be noted that on an H-bridge we have defined the following;
;
;Starting at the top left switch in the H-bridge we have switch G1
;Moving counter-clockwise through the switches we have G2, G4, and
;finally G3 as the top right-most switch. As labeled on the H-Bridge PCB.
;
;SO! Our Gating pulses come from the following PORTB outputs:
; Switch G1 = PORTB3 = PIN 17
; Switch G2 = PORTB4 = PIN 18
; Switch G3 = PORTB2 = PIN 16
; Switch G4 = PORTB1 = PIN 15
;
;At 100% load, G1 and G4 are in phase as well as G2 and G2
;There must also be a delay between the turn off of G1 and G4
;into the turn on of G2 and G3. This delay is also seen in the
;reverse where G2 and G3 turn off and G1 and G4 turn on.
;-------------------------------------------------------------------------------------------------

.include "m8def.inc"

;Interrupt Service Vectors

.org 0x000
rjmp Reset

.org OC1Aaddr
rjmp T1comA ;timer counter 1 compare match A
.org OC1Baddr
rjmp T1comB ;timer counter 1 compare match B

;Register definitions for variables

.def pwmhi=r16 ;hi time for main control signal

.def pwmlo=r17 ;lo time for main control signal
.def pwmT=r18 ;Period of control signal
.def tf=r19 ;Delay time for rise and fall
.def temp=r20
.def temp2=r21

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;Reset vector - initialize interrupts and service routines

Reset:
ldi temp,low(RAMEND) ;Set stack ptr to ram end
out SPL,temp
ldi temp,high(RAMEND)
out SPH,temp

;Initialize timercounter1 and interrupts

ldi temp,(1<<WGM12)+(1<<CS10) ;WGM12 Clear timer on compare to OCIE1A

out TCCR1B, temp ;CS10 no prescale run at clock speed

ldi temp,(1<<OCIE1A)+(1<<OCIE1B) ;tc1 compare matchA and matchB interrupts

out TIMSK,temp

;-------------------------------------------
;Control signal values are here for Peroid value correspond to # of CPU cycles
;loads max count value for TimerCounter1
;this is our period of control waveform

ldi temp,0x01
out OCR1AH,temp
ldi temp,0x90
out OCR1AL,temp

;This Changes duty cycle change me change me

;loads compare value for duty cycle note must load H before low
ldi temp,0x01 ;100% 0x01 15% 0x00
out OCR1BH,temp
ldi temp,0x90 ;100% 0x90 15% 0x30
out OCR1BL,temp
;---------------------------------------------------
;Initialize outputs
ldi temp,(1<<DDB4)|(1<<DDB3)|(1<<DDB2)|(1<<DDB1) ;sets data direction for pins
out DDRB,temp ;set data direction to out

ldi tf,0x01
sei

loop:
rjmp loop

;Rising of Control signal

T1comA:
sbis PORTB,(PORTB2)
rjmp bit2clear
nop ;these nop’s make both pulses have equivalent duty cycle
nop
nop
cbi PORTB,(PORTB2) ;Clear G3

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 rcall DELAY
sbi PORTB,(PORTB1) ;Set G4
reti
bit2clear:
cbi PORTB,(PORTB1) ;Clear G4
rcall DELAY
sbi PORTB,(PORTB2) ;Set G3
reti

;Falling of Control signal

T1comB:
sbis PORTB,(PORTB4)
rjmp bit4clear
nop ;these nops make both pulses have equivalent duty cycle
nop
nop
cbi PORTB,(PORTB4) ;Clear G2
rcall DELAY
sbi PORTB,(PORTB3) ;Set G1
reti
bit4clear:
cbi PORTB,(PORTB3) ;Clear G1
rcall DELAY
sbi PORTB,(PORTB4) ;Set G2
reti

;Delay subroutine

DELAY:
ldi temp,0x00
loopy:
inc temp
cpse temp,tf
rjmp loopy
ret

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