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    f215 Tut06 27-09

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    desaikaran1997_44873
    This document discusses the implementation of boolean functions using multiplexers. It provides examples of using 4:1 and 2:1 multiplexers to realize boolean functions with up to 4 and 8 variables. It also discusses designing a full adder using two 4:1 multiplexers and a circuit to shift a 4-bit vector right by one position using 2:1 multiplexers. Finally, it discusses designing a 4 to 16 decoder using a minimum number of 2 to 4 decoders and a magnitude comparator for 2-bit binary numbers using a 4 to 16 decoder.

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    f215 Tut06 27-09

    Uploaded by

    desaikaran1997_44873
    56 views10 pages
    This document discusses the implementation of boolean functions using multiplexers. It provides examples of using 4:1 and 2:1 multiplexers to realize boolean functions with up to 4 and 8 variables. It also discusses designing a full adder using two 4:1 multiplexers and a circuit to shift a 4-bit vector right by one position using 2:1 multiplexers. Finally, it discusses designing a 4 to 16 decoder using a minimum number of 2 to 4 decoders and a magnitude comparator for 2-bit binary numbers using a 4 to 16 decoder.

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    This document discusses the implementation of boolean functions using multiplexers. It provides examples of using 4:1 and 2:1 multiplexers to realize boolean functions with up to 4 and 8 variables. It also discusses designing a full adder using two 4:1 multiplexers and a circuit to shift a 4-bit vector right by one position using 2:1 multiplexers. Finally, it discusses designing a 4 to 16 decoder using a minimum number of 2 to 4 decoders and a magnitude comparator for 2-bit binary numbers using a 4 to 16 decoder.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    56 views10 pages

    f215 Tut06 27-09

    Uploaded by

    desaikaran1997_44873
    This document discusses the implementation of boolean functions using multiplexers. It provides examples of using 4:1 and 2:1 multiplexers to realize boolean functions with up to 4 and 8 variables. It also discusses designing a full adder using two 4:1 multiplexers and a circuit to shift a 4-bit vector right by one position using 2:1 multiplexers. Finally, it discusses designing a 4 to 16 decoder using a minimum number of 2 to 4 decoders and a magnitude comparator for 2-bit binary numbers using a 4 to 16 decoder.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 10

    CKV

    Digital Design

    Tutorial 6
    Multiplexers

    Boolean Function implementation

    1. F (X,Y,Z) = (1, 3, 5, 6, 7) using (a) 4:1


    MUX and (b) 2:1 MUX

    2. F (A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)


    Using (a) 8:1 MUX and (b) 4:1 MUX

    9/26/2016 2
    CKV
    Multiplexers

    3. The logic function implemented by the


    circuit below is (Note : Ground implies logic
    0)

    9/26/2016 3
    CKV
    Multiplexers

    4. The Boolean function realized by logic


    function shown is

    (A) F = (0,1,3,5,9,10,14) (B) F = (2,3,5,7,8,12,13)


    (C) F = (1,2,4,5,11,14,15) (D) F = (2,3,5,7,8,9,12)

    9/26/2016 4
    CKV
    (5) Design a Full-adder using two 4:1 Multiplexers

    (6) In digital system it is often necessary to have


    circuits that can shift the bits of a vector by one
    or more bit positions to the right or left.
    Design a circuit that can shift a four bit vector
    W = w3w2w1w0 one bit position to the right
    when a control signal shift is equal to 1.
    Hint : Implement with 2:1 multiplexers and use
    shift signal as the select input to each multiplier

    26-Sep-16 CS/EEE/ECE /INSTR F215 5


    Solution
    Let the outputs of the circuit to be a four bit
    vector Y = y3y2y1y0 and a signal k, such that if shift
    = 1 then y3 = 0, y2 = w3, y1 = w2, y0 = w1 and k = w0

    26-Sep-16 CS/EEE/ECE /INSTR F215 6


    If shift = o then Y = W and k = 0

    26-Sep-16 CS/EEE/ECE /INSTR F215 7


    (7) Design a 4 to 16 decoder by using a
    minimum number of 2 to 4 decoders. The 2
    to 4 decoders have an enable input (1 =
    enabled). Name the inputs A3A2A1A0 and the
    outputs D15D0. Do not draw the internal
    circuit diagrams for the decoders.

    26-Sep-16 CS/EEE/ECE /INSTR F215 8


    (8) Design a magnitude comparator circuit for 2-
    bit binary numbers A = A1A0 and B = B1B0.
    The outputs are G, E and L, where G is 1 if
    A>B, E = 1, if A=B and L=1 if A<B.

    (i) Fill in the truth table for the three


    outputs of the comparator and
    determine their functions as sum of
    minterms

    (ii) Implement the comparator design using


    a 4 to 16 decoder
    26-Sep-16 CS/EEE/ECE /INSTR F215 9
    CKV

    Thank You

    26-Sep-16 EEE C391/ECE C391/CS C391 10

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