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Topic 5 Tutorial Solutions

This document contains a tutorial on instruction set architectures with 10 questions and answers. It discusses concepts like byte ordering in big endian vs little endian systems, addressing modes (direct, indirect, indexed), converting between infix and postfix notation, implementing arithmetic expressions on different machine architectures, instruction format fields like opcode and addressing. The last question determines if a given instruction format can support a specified number of instructions with different address fields.

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Saimo Mghase
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
168 views

Topic 5 Tutorial Solutions

This document contains a tutorial on instruction set architectures with 10 questions and answers. It discusses concepts like byte ordering in big endian vs little endian systems, addressing modes (direct, indirect, indexed), converting between infix and postfix notation, implementing arithmetic expressions on different machine architectures, instruction format fields like opcode and addressing. The last question determines if a given instruction format can support a specified number of instructions with different address fields.

Uploaded by

Saimo Mghase
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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SCM, CSU 201430 ITC161/411

ITC161/544 Computer Systems/Computer Organisation and Architecture


Topic 5 Tutorial (A Closer Look at Instruction Set Architectures)

Answer the following questions.

1. Assume you have a byte-addressable machine that uses 32-bit integers and you are storing the hex value
1234 at address 0.

a. Show how this is stored on a big endian machine.


b. Show how this is stored on a little endian machine.
c. If you wanted to increase the hex value to 123456, which byte assignment would be more
efficient, big or little endian? Explain your answer.

Ans.

a and b.
Address 00 01 10 11
Big Endian 00 00 12 34
Little Endian 34 12 00 00

c. Little endian is more efficient because the additional information simply needs to be appended. With
big endian, the "12" and "34" would need to shift to maintain the correct byte ordering.

2. The first two bytes of a 2M x 16 main memory have the following hex values:
Byte 0 is FE
Byte 1 is 01
If these bytes hold a 16-bit two's complement integer, what is its actual decimal value if:
a. memory is big endian?
b. memory is little endian?

Ans.

a. FE0116 = 1111 1110 0000 00012 = -51110


b. 01FE16 = 0000 0001 1111 11102 = 51010

3. Convert the following expressions from infix to reverse Polish (postfix) notation.
a) (8 – 6) / 2
b) (2 + 3) * 8 / 10
c) (5 × (4 + 3) × 2 – 6)

Ans.
a. 8 6 – 2 /
b. 2 3 + 8 * 10 /
c. 5 4 3 + × 2 × 6 –

4. Convert the following expressions from reverse Polish notation to infix notation.
a. W X Y Z - + *
b. U V W X Y Z + * + * +
c. X Y Z + V W - * Z + +

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SCM, CSU 201430 ITC161/411

Ans.

a. W * (X + Y - Z)
b. U + (V * (W + (X * (Y + Z))))
c. X + ((Y + Z) * (V - W) + Z)

5. What is the difference between using direct and indirect addressing? Give an example.

Ans.

Direct addressing provides the actual memory address of the operand in the instruction, whereas indirect
addressing provides, as part of the instruction, a pointer to a memory location. For example, the
instruction Load X interpreted using direct addressing would go to memory location X and load the value
found there. Using indirect addressing, memory location X would be used as the effective address of
what should actually be loaded. So if a value of 200 were found at location X, the value located at
address 200 would be loaded.

6. Suppose we have the instruction Load 1000. Given memory and register R1 contain the values below:

Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the
accumulator using the following addressing modes:

a. Immediate
b. Direct
c. Indirect
d. indexed

ans:

a. Immediate: 1000
b. Direct: 1400
c. Indirect: 1300
d. Indexed: 1000

7. Write code to implement the expression: A= (B + C) * (D + E) on 3-, 2-, 1- and 0-address machines. In
accordance with programming language practice, computing the expression should not change the values
of its operands.

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SCM, CSU 201430 ITC161/411

8. A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different
operations. All instructions have an operation code part (opcode) and an address part (allowing for only
one address). Each instruction is stored in one word of memory.
a. How many bits are needed for the opcode?
b. How many bits are left for the address part of the instruction?
c. What is the maximum allowable size for memory?
d. What is the largest unsigned binary number that can be accommodated in one word of memory?

Ans.

a. 150 instructions implies 28 (27 will only give us 128 instructions), or 8 bits for the opcode.

b. 24 - 8 = 16

c. 216 or 32M

d. 24 1's or 224 -1

9. The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format
with 4 fields: an opcode field; a mode field to specify 1 of 7 addressing modes; a register address field to
specify one of 60 registers; and a memory address field. Assume an instruction is 32 bits long. Answer the
following:
a. How large must the mode field be?
b. How large must the register field be?
c. How large must the address field be?
d. How large is the opcode field?

Ans.

a. We need to identify 1 of 7 items, so there must be 3 bits (23 = 8)

b. 60 registers implies 6 bits (26 = 64)

c. 256K = 28210 = 218, or 18 bits

d. 32 - (3 + 6 + 18) = 5 bits

10. In a computer instruction format, the instruction length is 11 bits and the size of an address field is 4
bits. Is it possible to have:
5 2-address instructions

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SCM, CSU 201430 ITC161/411

45 1-address instructions
32 0-address instructions
using the specified format? Justify your answer.

Ans.

Yes. The 2-address instructions could be represented 000xxxxxxxx through 100xxxxxxxx (using 000
through 100 for opcodes). The 1-address instructions could use 1010000 through 1011111 (16), 1100000
through 1101111 (16), and 1110000 through 1111100 (13 more, for a total of 45). The 0-address
instructions could use 11111100000 through 11111101111 (16), and 11111110000 through 11111111111
(16). So we have:

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