Up to ten 8-bit digital Input/Output (I/O) ports, P1 to P10
(depending on the MSP430 device);
I/O ports P1 and P2 have interrupt capability;
Each interrupt for these I/O lines can be individually
configured: To provide an interrupt on a rising or falling edge; All interruptible I/O lines source a single interrupt vector.
The available digital I/O pins for the hardware
development tools: eZ430-F2013: 10 pins - Port P1 (8 bits) and Port P2 (2 bits); eZ430-RF2500: 32 pins - Port P1 to P4 (8 bits); Experimenter’s board: 80 pins – Port P1 to P10 (8 bits).
Copyright 2009 Texas Instruments
All Rights Reserved 2 Introduction (2/3)
Each I/O port can be:
Programmed independently for each bit;
Combine input, output, and interrupt functionality;
Edge-selectable input interrupt capability for all 8 bits of
ports P1 and P2;
Read/write access to port-control registers is supported by
Others functions (see specific datasheet for details).
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All Rights Reserved 4 GPIO Inside Inputs/Outputs
Output section
Input section
Each pin is independent
Ports (out) and Pins (in) are
not the same thing!! Copyright 2009 Texas Instruments All Rights Reserved 5 Digital I/O Registers
Independently programmable individual I/Os Port3 Port1 Port2 … Port10 • Each has 8 I/O pins yes yes Function Select Register PxSEL yes no • Each pin can be Interrupt Edge Select Register PxIES
Interrupt Enable Register PxIE yes no configured as input
Interrupt Flag Register PxIFG yes no or output Direction Register PxDIR yes yes
Output Register PxOUT yes yes • P1 and P2 pins can
Input Register PxIN yes yes be configured to assert an interrupt request 7 6 5 4 3 2 1 0
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All Rights Reserved 6 Registers (1/6)
Function Select Registers: (PxSEL) and (PxSEL2):
• Some port pins are multiplexed with other peripheral module functions (see the device-specific datasheet); • These bits: PxSEL and PxSEL2 (see specific device datasheet), are used to select the pin function: – I/O general purpose port; – Peripheral module function. • PxSEL configuration: Bit = 0: I/O Function is selected for the pin; Bit = 1: Peripheral module function enabled for pin.
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All Rights Reserved 7 Registers (2/6)
Function Select Registers: (PxSEL) and (PxSEL2):
• The 2xx family of devices provide the PxSEL2 bit to
configure additional features of the device;
• The PxSEL and PxSEL2 bits in combination provide the
following configuration: – Bit = 0: I/O function is selected for the pin; – Bit = 1: Peripheral module function is selected for the pin.
PxSEL PxSEL2 Pin Function
0 0 Selects general purpose I/O function 0 1 Selects the primary peripheral module function 1 0 Reserved (See device-specific data sheet) 1 1 Selects the secondary peripheral module function Note: P1 and P2 configured as peripheral module function (PxSEL = 1 and/or PxSEL2) -> interrupts disabled. Copyright 2009 Texas Instruments All Rights Reserved 8 Registers (3/6)
Independent of the I/O port type (non-interruptible or
interruptible), the operation of the ports is configured by user software, as defined by the following registers:
Direction Registers (PxDIR):
• Read/write 8-bit registers; • Select the direction of the corresponding I/O pin, regardless of the selected function of the pin (general purpose I/O or as a special function I/O); • For other module functions, must be set as required by the other function.
• PxDIR configuration: Bit = 1: the individual port pin is set as an output; Bit = 0: the individual port pin is set as an input.
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All Rights Reserved 9 Registers (4/6)
Input Registers (PxIN):
• When pins are configured as GPIO, each bit of these read-only registers reflects the input signal at the corresponding I/O pin;
• PxIN configuration: Bit = 1: The input is high; Bit = 0: The input is low;
• Tip: Avoid writing to these read-only registers because
it will result in increased current consumption.
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All Rights Reserved 10 Registers (5/6)
Output Registers (PxOUT):
• Each bit of these registers reflects the value written to the corresponding output pin.
• PxOUT configuration: Bit = 1: The output is high; Bit = 0: The output is low.
– Note: the PxOUT Register is read-write. This means
that the previous value written to it can be read back and modified to generate the next output signal.
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All Rights Reserved 11 Registers (6/6)
Pull-up/down Resistor Enable Registers (PxREN):
• Only available for the 2xx family;
• Each bit of this register enables or disables the pull- up/pull-down resistor of the corresponding I/O pin.
• PxREN configuration: – Bit = 1: Pull-up/pull-down resistor enabled; – Bit = 0: Pull-up/pull-down resistor disabled.
– When pull-up/pull-down resistor is enabled:
– In this case Output Registers (PxOUT) select: » Bit = 1: The pin is pulled up; » Bit = 0: The pin is pulled down.
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All Rights Reserved 12 Interruptible ports (P1 and P2) (1/2)
Each pin of ports P1 and P2 is able to make an interrupt
request;
Pins are configured with additional registers:
Interrupt Enable (PxIE):
• Read-write register to enable interrupts on individual pins;
• PxIE configuration: Bit = 1: The interrupt is enabled; Bit = 0: The interrupt is disabled.
• Each PxIE bit enables the interrupt request associated with
the corresponding PxIFG interrupt flag; • Writing to PxOUT and/or PxDIR can result in setting PxIFG.
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All Rights Reserved 13 Interruptible ports (P1 and P2) (2/2)
Interrupt Edge Select Registers (PxIES):
• Selects the transition on which an interrupt occurs (if PxIE and GIE are set); • PxIES configuration: Bit = 1: Interrupt flag is set on a high-to-low transition; Bit = 0: Interrupt flag is set on a low-to-high transition.
Interrupt Flag Registers (PxIFG)
• Set automatically when an the programmed signal transition (edge) occurs; • PxIFG flag can be set and must be reset by software. • PxIFG configuration: Bit = 0: No interrupt is pending; Bit = 1: An interrupt is pending.
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All Rights Reserved 14 GPIO - Inputs
Avoid floating inputs!!!
Use a pull-up/down resistor, GND, or internal programmable logic
To Input Logic VCC Button VCC Button Button produces either Vcc Port Pin or Floating 5.6K 5.6K input. Adding a pull-down resistor fixes it. Some ports have internal programmable resistors
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All Rights Reserved 15 GPIO - Outputs Open-collector
Many logic chips, output pins, circuits use
open-collector (open-drain)
Simple logic-glue, signal bus
Wired-OR circuits
Interface different voltage levels.
Interface between 5V CMOS logic and a higher voltage
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All Rights Reserved 16 Example - Blinking the LED (1/4)
Configure the I/O ports to use inputs from push buttons
to control the output lines feeding LEDs; Procedure:
Check schematics for LED port location (Consult the Hardware Development Tool User's Guide);
Port control registers:
• Set LED pin port as an output; • Switch the port state between low and high state during program execution.
Configure the watchdog timer to prevent a Power-Up Clear (PUC);
Use an infinite loop to modify the state of the port;
Use a software delay loop to generate the pause interval (a software delay loop with a long time period is used here for simplicity - in real applications a timer would be used). Copyright 2009 Texas Instruments All Rights Reserved 17 Example - Blinking the LED (2/4)
The LED1 is connected to Port 1.1;
Copyright 2009 Texas Instruments
All Rights Reserved 18 Example - Blinking the LED (3/4)
Port control registers:
P1DIR: • Port 1.1 is set as an output: P1DIR |= 0x02 to force the pin setting, an OR operation ( | ) is performed using P1DIR and 0x02. This makes bit 1 -> 1, without affecting any other port pins.
P2OUT: P1OUT ^= 0x02;
• To switch the port state between low and high states, an XOR operation ( ^ ) is performed using P1OUT and 0x02. This reads the value previously written to P1OUT and makes bit 1 change state from 0 -> 1 and 1 -> 0.
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All Rights Reserved 19 Example - Blinking the LED (4/4)
To prevent a PUC, the watchdog timer:
Must be stop and write 0x5A to the eight MSBs of the Watchdog Timer Control Register, WDTCTL:
WDTCTL = WDTHOLD | WDTPW
Since no clock has been defined, the device will use a
32.768 kHz watch crystal: To implement a blinking LED rate of one transition per second, the software delay loop should count to approximately 30000 {30000/32768 1 sec}.
