Institut für Integrierte Systeme

Integrated Systems Laboratory

Department of Information Technology and Electrical Engineering

VLSI II: Entwurf von hochintegrierten Schaltungen

227-0147-00

Exercise 10

Physical Verification
Prof. Dr. H. Kaeslin
Dr. N. Felber

SVN Rev.: 1744

Last Changed: 2016-09-02

Reminder:
With the execution of this training you declare that you understand and accept the regulations about
using CAE/CAD software installations at the ETH Zurich. These regulations can be read anytime at
http://eda.ee.ethz.ch/index.php/Regulations.
1 Overview

We are now in the final stages of the back end design. We started with floorplanning in exercise 5,
and proceeded with the placement and routing which we covered in exercise 8. In the previous
exercise 9 we made several checks and exported the GDSII that will be used for manufacturing the
chip. In this exercise, we will perform one more final check using M ENTOR G RAPHICS C ALIBRE 1 .
Once these checks are complete, the chip is ready to be shipped out.

1.1 About the Style

We will use a number of different styles to identify different types of actions as shown below:

Student Task: Parts of the text that have a gray background, like the current paragraph, indicate
steps required to complete the exercise.

Actions that require you to select a specific menu will be shown like the following:
menu→sub-menu→sub-sub-menu
Whenever there is an option or a tab that can be found in the current view/menu we will use a BUTTON
to indicate such an option.
Throughout the exercise you will be asked to enter certain commands using the command-line2 .
sh > command to be entered on the Linux command line

2 Physical Verification Design Flow

The goal of the back end design is to convert the structural netlist that we obtained through the
front end design into a physical layout database that essentially contains the geometrical design
information for all design layers. This information (also called the mask data) is used by the IC
foundry site as a blueprint for manufacturing. Essentially the IC foundry gets only a large database
that contains a set of geometric shapes (mostly rectangles) in different layers.
Some of the layers in the database are physical layers. That means these layers will be directly man-
ufactured. A good example are the various metal layers used for interconnections. There are some
non-physical layers that are used as part of the design flow to identify certain structures (umcL65
uses a dedicated layer to identify resistors for example), or just for informational purposes (various
text layers)
The IC foundry defines several rules for each of the process layers. In essence the foundry would
say
“If you manage to send me a geometrical database that obeys all the rules I have sent
you, I guarantee that I will be able to manufacture an ASIC that works (with some yield).”

1
At the end of the exercise we will also have a discussion as why there could still be problems, following all the checks
we have seen in exercise 9.
2
There are many reasons for using a command-line. Some functionality can not not be accessed through GUI com-
mands, and in some cases, using the command-line will be much faster. Most importantly, things you enter on the
command-line can be converted into a script and executed repeatedly

2
For example, in the umcL65 technology that we use in our exercises, if you want to draw two parallel
interconnections on metal-1 (the lowest metal layer), you have to make sure that the metal lines are
at least 90 nm wide and are separated by at least 90 nm between them3 . These rules are known as
design rules.
DRC is a rigorous process where the entire physical design database is checked against these design
rules. Over time, the IC manufacturing technology has evolved tremendously. With each technology
step, the design rules have become more complex and numerous. A modern process like umcL65
has many different manufacturing options (In fact there are 57! different metallization options you can
choose from), making DRC an increasingly complex operation. The design rules for the process are
linked under: docs/65nm layout rules.pdf.
As mentioned earlier, the IC foundry receives only geometrical information on the design. Before sub-
mitting this data base, it is important to make sure that the bunch of polygons that we are submitting
indeed represent our circuit. This process is known as the Layout (the physical database that con-
tains polygons) Versus Schematic (the design database that contains a netlist of transistors) check.
During LVS, the tool takes the physical database and identifies transistors and interconnections and
thereby creates a netlist directly from the physical database. In the second step this netlist is com-
pared against the original logical netlist (gate level netlist) that was the basis of our design. If both
netlists match, we can be confident that the physical database that we are sending for manufacturing
contains our design, has no shorts or missing connections4 .
We will be using the Calibre tool from Mentor Graphics for both DRC and LVS in our design flow as
illustrated below:

TCL script for export

encounter/scripts/ Cadence EDI
exportall.tcl

Physical Layout Verilog Netlist

encounter/out/final.gds encounter/out/final.v

SPICE includes

verilog2spice calibre/lvs/spice.inc

Calibre DRV
Verilog includes

calibre/lvs/verilog.inc

SPICE Netlist

calibre/lvs/final.sp

Runset file Runset file

calibre/drc/runset.drc calibre/lvs/runset.lvs

Antenna Runset file Calibre DRC Calibre LVS Labels

calibre/drc/antenna.drc calibre/lvs/lvs_labels.txt

3
For modern technologies, the rules are actually slightly more complex. For example, in the above example the
separation is at least 160 nm if the two parallel running metal-1 lines are wider than 500 nm, and 300 nm if the two
lines are wider than 2.8 µm.
4
Note that this only ensures that the layout corresponds to the final gate-level netlist, whether or not the gate-level
netlist actually does what we expect it to do is an entirely different manner that is handled by design verification.

3
2.1 Getting Started

Student Task 1:
• Start by copying the example files into your directory by issuing the command
sh > cd ˜
sh > /home/vlsi2/ex10/install_ex10

This will create a cockpit hierarchy in the directory ex 10. The design that we will use in this exer-
cise is the one we have used in exercise 4, we have included only the relevant parts of the design
database.

2.2 Accessing the Layout

Selection Type

Hierarchy
Layer
Display Selection

Layout Display

Depth
Display

We will use the M ENTOR G RAPHICS C ALIBRE DesignRev (DRV) tool to access the gdsii file produced
by C ADENCE EDI E NCOUNTER . Start the tool either by clicking on the C ALIBRE DRV button of the
cockpit 5 , or manually change to the directory calibre and use the command line6 :
sh > calibre-2016.2 calibredrv -dl .init/L65.layerprops

5
you can start cockpit by typing icdesign umcL65
6
do not use a ’&’ to run this program in the background, as it needs to access the console

4
The -dl option specifies a configuration file that will load the layer information so that the colors of
the layout looks similar to that you have seen in C ADENCE EDI E NCOUNTER .

Student Task 2:
• Load the final gdsii file. Select File→Open Layout Files.. to bring out a requester.
• Change to the directory ../encounter/out where our outputs are located. You will have to
change the F ILE TYPE at the bottom of the requester to ZIP (*.gz, *.Z, *.z) in order
to be able to see our file example chip.gds.gza .
a
Most tools like Mentor Graphics Calibre will be able to read compressed (∗.gz) files without a problem.

You should now see the layout in the main window as shown in the previous figure 7

2.3 Hierarchy

Physical design tools, like calibredrv we are using in this exercise, rely heavily on hierarchy. The
example design example chip.gds.gz has 10 levels of hierarchy as displayed by the D EPTH indicator
on the bottom right side of the DRV window. By default only the top level of this hierarchy is shown.
All lower levels of the hierarchy are shown as empty boxes with a name in them8 .
In a hierarchical design, you can only edit the physical layout of the top hierarchy only. Frequently
the top layer will contain instances of other cells (called references). These will be included in their
entirety and you will not be able to edit inside these cells directly. In our case these include:
• Standard cells (like ANDs and ORs)
• I/O Drivers
• Macro cells (like the SRAM macro on the top left)
• Via instances, that connect various metal layers.
While you can not modify these instances directly, you can move, copy and delete them in its entirety.
This is important to understand when you start editing. If you want to edit a reference (for example
the physical layout of a NAND gate), you can select the reference from hierarchy browser on the left
side. Note that once you modify the reference all the instances that point to this reference will also be
changed. In most cases this is not what you want to do, and the hierarchy prevents such accidental
changes. One point that is really annoying is that the interconnection between different metal layers
is done by instantiating a couple of via references, which you will not be able to edit directly as well
(as they are in a different hierarchy level). You will have to get used to working with these levels.
You can change how many levels of the hierarchy are displayed by clicking on the numbers on the
D EPTH indicator. If you select the S TART DEPTH as 0, and the E ND DEPTH as 10 you will be able to
see the entire physical layout. However, regardless of how many levels you can see, you will only be
allowed to edit the top-level hierarchy.

7
By default Calibre DRV will draw an outline around each instance and will write its name inside the box, while
this is sometimes very useful, it will make the screen very cluttered. You can disable this, by selecting Options
→Layout View... and deselecting the option Draw reference outlines from the requester that comes up.
8
This behavior can be changed by selecting Options →Layout View....

5
 Student Task 3:
• Familiarize yourself with the editor, try displaying all levels of the hierarchy, zooming, ma-
neuvering, displaying only certain layers.
Note that, unlike in C ADENCE EDI E NCOUNTER you have full access to the layouts you
can examine individual standard cells as well.
• Take a piece of paper, and looking at the layout draw the transistor level schematic of the
following cells including the transistor dimensions similar to the example given below for
INVM2W.: BUFM4W, ND3M1W, ND3M2W, OA211M2WA.

630nm
60nm

A Z

450nm
60nm

In the previous step you have managed to extract the circuit looking at the geometric information, this
is exactly the same way that Calibre will extract your circuit during LVS phase.

Student Task 4:
• View the full chip again.
• You can also extract nets. Try to determine the connectivity of some nets. By default you
can only extract on the top-level, you can change this behavior by by selecting Options
→Nets... and selecting All Levels for the option S EARCH D EPTH a .
• Try this feature. Select one net. Click with the right mouse button to get a small context
menu. You can select E XTRACT N ET from this menub
a
Note that if you select the supply nets, the extraction will take very long. There will be an Abort option visible
during the extraction on the bottom left corner of the DRV.
b
to be able to select a net, make sure that the Polygon is the only option selected on the top right side of the
DRV.

By extracting a net you will have created a new filter for calibredrv. This filter will allow you to see all
the physical components of the net that is electrically connected. You can add this filter on top of the
normal layout to show this particular net. Multiple such filters can be added.
Trying to understand the connections in modern technologies such as the umcL65 is difficult since
they have many layers. This is why it is important to use the tools we have at our disposal.
• hierarchy, use this to examine the circuit only at certain hierarchy levels.
• layers, enable only the layers of interest. I.e. for metal2, enable only via, via2, and metal29 .
• filters allow you to select and highlight interconnected nets (at all layers). This can be useful to
see what is really connected.
9
These are the only layers that are physically interconnected.

6
3 Running DRC

In this section we will perform a DRC on the layout we have just loaded.

Student Task 5: Select Verification →Run nmDRC.. to start the DRC process. This will
bring out a new window titled Calibre Interactive -nmDRC. The cockpit setup we have has sensi-
ble defaults for most of the settings, and the DRC is practically ready to run.

The main DRC window contains four main configuration steps which are available as buttons on the
left hand side10 :

Rules Defines the run file which contains all the design rules and the run directory where the results
will be written (./calibre/drc in the cockpit setup)
Inputs Tells where to find the layout file. The default is to export it from the DRV viewer11
Outputs Specifies where the output will be written (the defaults should be OK)
Run Control Allows you to set some options about the run.

If any of the configurations is not valid you will see the content of the field in red color. At the moment
we are not going to make changes and use the setup as it is.

Student Task 6:
• Run the DRC by pressing on the RUN DRC button on the left hand side of the window. This
will take some time, a progress bar at the bottom will show you how far along you are
• After a few seconds the RVE window will start. This window is used to browse the DRC
errors. You can already browse the error markers while the DRC is running.
• Once DRC is completed, you will see a DRC Summary Report pop up. Now the RVE
should show you all DRC errors and allow you to browse them.

If you scroll to the end of the DRC Summary Report window, you should see a summary like:

--- RULECHECK RESULTS STATISTICS (BY CELL)

---
CELL example_chip ....... TOTAL Result Count = 5 (5)
RULECHECK M1.S1 ..... TOTAL Result Count = 2 (2)
RULECHECK 1XM2.W1 ... TOTAL Result Count = 1 (1)
RULECHECK 1XM2.S1 ... TOTAL Result Count = 1 (1)
RULECHECK 1XM2.A1 ... TOTAL Result Count = 1 (1)
----------------------------------------------------------------------------------
--- SUMMARY
---
TOTAL CPU Time: 168
TOTAL REAL Time: 110
TOTAL Original Layer Geometries: 120475 (24207152)
TOTAL DRC RuleChecks Executed: 4355
TOTAL DRC Results Generated: 5 (5)
10
There is a fifth configuration button, DRC options which is not enabled by default. You will have to go to the menu
Setup and enable the DRC Options. However the default values should be sufficient for most cases
11
If you are not editing the file, it might be a better idea to disable this feature.

7
The summary tells us that there were 120’475 shapes (geometries), and they were checked for 4355
different rules12 , in the end the important part is the last line TOTAL DRC Results Generated,
which tells us there were ”5” violations. The lines above actually tell us which rules were violated,
and how many times. For example M1.S1 (whatever it is) was violated 2 times. Now it is time to figure
out what the problems are, and fix them.

Note: The errors in this particular example were manufactured to show you different types of
errors that can be found during DRC and LVS. As we will discuss later, there are reasons why
errors can still be found in a design that was completed using an automated design flow.

3.1 Fixing DRC Errors

The tool that we will need to fix the errors is the RVE. The following figure shows a screenshot of the
RVE as it should approximately look like after the DRC run.

Errors for selected check

List of Checks
Coordinates
of error

Explanation of error

In this DRC run there are five DRC errors (RVE calls them results) violating four different rules (RVE
calls them checks). In the figure we have selected the first check named M1.S113 and at the bottom
there is an explanation of the design rule:

Minimum spacing and notch of Metal1 region is 0.09

For a given check, multiple results can be listed (like the one in the figure). The RVE window is
connected to the DRV window. Once you double click on any result, you can highlight the error
location on the DRV window, alternatively you can select one result and press H, or use the right
mouse button to show a context menu. The highlighting will be made using a new layer (called rve)
in the DRV window. You can treat this layer just like any other layer and hide it if necessary.
We will now locate and correct all the errors. Since this is an exercise we have made sure that the
errors are easy to locate and fix.
12
For the previous technology we used for the exercises (i.e. the umcL180) there were only 455 rules.
13
The name is listed in the design rule manual. In our case it is on page 55 of the design rule manual accessible under
docs/65nm layout rules.pdf

8
 Student Task 7:
• Let us start with the error M1.S1, select and highlight the first error.
• You will see the error marker, showing the region where the error has been encountered.
However we do not see the complete layout, only the top level of the hierarchy. You can
change the number of hierarchy levels visible by pressing ”>”a . Press > at least three times
to make the first 4 levels of hierarchy visible.
• Currently many layers will be visible, this makes it quite hard to understand what is going
on. We have an error that only concerns metal1. Figure out how you can disable the layers,
and arrange that only metal1 (and the error marker) remains visible.
a
Or as we did earlier by clicking on the number next to the Depth field at the bottom right side of the DRV
window.

Use "Box" to draw rectangles

Use "Move" to move shapes around Selection filters

Use "Ruler" to make measurements

Leave "metal1" visible

and turn all others off

The "rve" layer

is at the very bottom,
Region that causes the error
something is wrong here! you can change
the appearance, visibility etc

make sure "Depth" shows suffcient layers

Now you should see the problem much more easily. The design rule says that metal1 structures
need at least 0.09 µm separation. The current error is what we call a notch. This is essentially when
a small gap exists between structures that belong to the same net (like ’U’ shape). There is one
more error (not highlighted yet) of the same type visible directly above the one that is highlighted (the
structure is symmetric, so you got flagged for the notch below and above separately, essentially an
’H’ shape). In our case the notch is smaller than 0.09 µm.
There are multiple ways you can solve this problem. Basically you can either move the structures
further apart so that the notch does not violate the minimum distance rule, or you can choose to fill-in
the notch.

9
Editing the layout is quite tricky and very error prone. Here are some general suggestions to keep in
mind.

• Prior to manufacturing everything that is on one layer will be merged together, and there will be
a mask for every layer (i.e. metal1). So it does not really matter on what level of the hierarchy
the structure is drawn, if the structures overlap, or if they are drawn on top of each other. In the
end there will be only one combined mask14 .
• Make sure to show always the relevant layers. Note that the relevant layers will also depend on
the type of operation you are doing. In our case, if you plan on adding some metal1 to fill in the
notch, then all you need to see is metal1. However if you decide to move things around, you
have to consider that the metal1 structures might also be connected to other structures. Metal1
can connect down using a contact layer to either poly or active, or up using via layer to metal2.
You have to at least make sure that contact and via is turned on as well, as these are the places
where a connection will take place. If you move things around, take care that the connections
are not broken.
• You can only make edits (add/modify polygons) on the top level of the hierarchy. You will not
be able to modify any structures within the instances, but you will be able to copy/move/delete
these instances as a whole. Look at the H shape in the screenshot above. The left side of the H
shaped metal1 is actually a via instance that connects metal1 to metal2. You can not edit parts
of this instance (for example stretching the right side edge) without changing all via instances
in the design. Similarly almost everything on the right side is part of a standard cell. However
there are two rectangles drawn at the top level. These can be modified directly.
• On the top right corner of the DRV, there are selection filters. These can be toggled to allow
you only to target specific structures. For the most part you will need the following options:
Reference Use this to select instances
Polygon Selects most drawn geometry (layouts from C ADENCE EDI E NCOUNTER will not have
Path structures).
Edge Allows you to only select one edge of a polygon. This is useful for stretching the connec-
tions.
Make sure you select the correct type. Although you could practically enable everything, you
will make fewer mistakes if you only enable the type of structure you want to edit.
• DRV allows you to change the appearance of the layers very easily. Simply, select a layer and
click on the color and shading pattern you want on the right hand side.
• Grid is your friend, try to get used to it. By default you will notice that you can not move the
object by the amount you want. There is a grid setting of 0.1 µm that restricts movements by
this amount. Change this preference by selecting Options →Grid Setting from the menu.
Change this setting as the situation demands it. For example metal1-6 are drawn with a pitch of
0.2 µm. If you are moving vias, if you have the grid at this setting the vias will always magically
jump to the next routing track.
• Investigate the situation and plan ahead before you start hacking away. You are essentially
performing surgery inside the chip. It is very easy to make a mess of the edits. You want to
reduce the number of errors, not create many more while trying to fix one.

14
However, it is very good practice to align the structures that you draw perfectly. Regularity is our most important
friend when drawing layouts. If you get a habit of drawing everything perfectly aligned, mistakes will stand out much
more, every little bit helps.

10
 • DRC will only tell you about the design rules, it will not tell you if two structures on the same layer
should be connected or separated. We will use LVS later on to determine if our connections are
correct.
• In case you make a mistake there is always Edit →Undo:.

Student Task 8:
• Following the tips given above, try fixing the first two DRC errors from check M1.S1.
• Rerun the DRC after fixing the errors. Please note that you have modified the layout, and
make sure that E XPORT FROM LAYOUT VIEWER option is selected in the I NPUT tab of the
DRC window.
If you did everything right, the errors should disappear.

In a lot of cases, one DRC or LVS error may cause a series of others. Furthermore, while fixing one
error, it is possible to introduce more errors. Depending on the run time of DRC, you may decide to
check and correct other errors first or go one by one. No matter which way you choose, fixing DRC
errors requires patience and concentration.
The remaining DRC errors are all common problems that you will encounter:
• Minimum width of structures drawn in layer
• Minimum spacing between two metal structures on the same layer
• Minimum area of a given structure in a given layer must exceed a certain amount.

Student Task 9:
• Correct all errors until you have a clean DRC.
• Make sure that you save the end result, since we will use this for the LVS.

3.2 Antenna DRC

We are almost complete. There are some additional checks we have to complete before we fin-
ish. The DRC rules that we have checked up to now were about physical distance rules related to
manufacturing, if these rules are violated the structures would be too small to manufacture reliably,
potentially causing shorts and opens.
There are other problems during manufacturing as well. One particularly nasty and interesting prob-
lem is related to antennas. During the manufacturing process there are several steps15 (such as
reactive ion etching) that generate charge carriers within the vicinity of the circuit that is still be-
ing manufactured. The long (incomplete) metal connections can act as antennas collecting these
charges. If the long metal is connected to a small gate, this charge may break through the thin gate
oxide causing the device to fail. The antenna rules check the metal structures and calculate the ra-
tio of the charge collecting antennas to the connected gate regions. If the ratio is too high (usually
around 1000) then the long metal connection is marked as a potential antenna.
There is a special ruleset generated for M ENTOR G RAPHICS C ALIBRE to determine if any metal
connections are susceptible to such antenna effects. This check is different than the other geometric

15
These will be covered in detail during VLSI III.

11
checks we have made and a new ruleset file needs to be loaded16 . The runsets are located in
the ./calibre/drc directory and can be loaded by using file→Load Runset... from the Calibre
Interactive window.
Student Task 10: Run a second DRC, this time by using the runset calibre/drc/antenna.drc. You
can load a new runset through the menu File →Load Runset.

Antenna errors are relatively easy to fix. You can either interrupt the long running metal by going up a
level17 , or by inserting antenna diodes18 . This is usually done by C ADENCE EDI E NCOUNTER . The
only problem is that sometimes the way C ADENCE EDI E NCOUNTER determines the antenna ratios
is not exactly the same with M ENTOR G RAPHICS C ALIBRE (which is more accurate), and therefore
sometimes there are cases which C ADENCE EDI E NCOUNTER can not catch. Usually we tune the
values in C ADENCE EDI E NCOUNTER so that they are more conservative, reducing the possibility
of problems at this stage. Still it is very important to perform this test and ensure that there are no
problems19 .
We are now done with DRC, so we can move to the next stage. Make sure that you have saved the
latest corrected version of the layout and you use this layout for the next part of the exercise.

4 Running LVS

In this section we will run LVS on the same design. Note that both DRC and LVS have to be repeated
whenever, there is a change in the layout.
Before we start the LVS, we have to prepare the data. We already have the layout, what we need
is to generate the schematic (the S of LVS). We have the final Verilog netlist that we have saved in
C ADENCE EDI E NCOUNTER . This netlist contains all modifications and additions (clock tree, buffers,
filler cells) of the back end design flow. This netlist does not contain the transistors within the standard
cells. We will use a simple script to generate a transistor level netlist (in SPICE format) that contains
all necessary information for the schematic.

Student Task 11:

• If you still have the DRC window, close it, we will not need it for a while.
• Using a console change to the lvs directory calibre/lvs. You will find the script verilog2spice
there. Execute it using:
sh > ./verilog2spice ../../encounter/out/example_chip_lvs.v \
example.sp

16
The setup we use automatically loads the default ruleset when you start Mentor Graphics Calibre so you did
not have to specifically select a ruleset when you started.
17
Assume that the antenna is on metal4. When this metal is exposed, the higher metal5 would not yet be there. If
you interrupt the metal4 and go up to metal5 for just a little while you do not change the connectivity, but you can
reduce the area of the antenna that is exposed during manufacturing of metal4.
18
This is a reverse biased diode that is only there to give the charges collected by the antenna a discharge path, during
normal operation, the diode will never turn on.
19
Never leave out a chance to make additional tests

12
This procedure will convert the Verilog netlist under ../../encounter/out/example chip lvs.v into a SPICE
netlist named example.sp in the current directory.
You will see a summary of warning messages such as:

Warnings:
Unsupported compiler directive : 4
Duplicate port/net : 0
Module instantiation XXXX has pin mismatches : 0
Calls port VSS not declared in module : 0
Calls port VDD not declared in module : 0

In this simple example there are not many problems. Most of these messages come from instantia-
tions where all defined outputs are not connected to a net. This is not tragic, and can be ignored20 .

Note: You may have noticed that we have two netlists under ./encounter/out, one is called
example chip lvs.v and the other example chip.v. The file with lvs has for all standard cells
the correct power pin connections as well. In our setup this is needed, therefore we will always
use the lvs.v version for LVS, the other netlist will be used for M ENTOR G RAPHICS M ODELSIM
post-layout simulations.

Now we have our schematic we need to start the LVS. Unlike the DRC, there are several additional
files that control the LVS flow. The example.sp file will include the file spice.inc which in turn includes
the SPICE level definitions of all the libraries and macro-cells.
The runset file runset.lvs among other things includes the file lvs labels.txt. This file puts two labels for
VDDIO and VSSIO the power and ground signals for the I/O cells. Throughout the backend design we
have only used VDD and VSS as the only power signals. In reality, there are several other independent
supply nets, and these have to be taken into account for the LVS. The labels are positioned on the
correct I/O supply pads21 and help identify the additional supply nets for the purpose of LVS.

Student Task 12:

• Select Verification →nmLVS..” in the calibre DRV main window to start the LVS. This
should automatically load the the runset file located under calibre/lvs/runset.lvs, and you
should be ready to go.
• Make sure that you either have the correct version of the layout opened in the DRV window,
and export it to the file specified under the I NPUTS configuration, or alternatively disable
the E XPORT FROM LAYOUT VIEWER and make sure that the correct gds file is given under
the F ILE for the L AYOUT tab.
• You will notice that the I NPUTS configuration is still red. You should also notice that there
are multiple tabs in the configuration area. Currently the L AYOUT has been selected. Click
on the N ETLIST and bring up the file browser by pressing .... You should be able to select
the SPICE netlist file that we have created named example.sp.
• make sure that the TOP C ELL : corresponds to your design. In our case, this should be
correct. However if there is a mismatch you can find the correct name from the Verilog

20
For your own designs you should always investigate what these messages are. For this exercise we have made sure
that there are no surprises.
21
Unless you have deviated from the power pin template given.

13
 netlist, from the SPICE netlist, or by browsing the instances within the file by clicking on the
”...” button.
• All other options should remain the same. Start the LVS run by clicking on the RUN LVS
button on the left hand side.
The LVS run will also produce two windows, the RVE and the LVS Report File. Before we start let us
examine the LVS Report File window that popped up at the end of the comparison. Bad news start
with:

CELL COMPARISON RESULTS ( TOP LEVEL )

# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################

Error: Different numbers of nets (see below).

Error: Connectivity errors.

which basically tell us that the LVS did not match22 . If you scroll further down you will see a list of
how the two netlists compare:

NUMBERS OF OBJECTS AFTER TRANSFORMATION

---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 40 40
Nets: 23178 23177 *
Instances: 21491 21491 MN (4 pins)
22254 22254 MP (4 pins)
44 44 R (3 pins)
103 103 D (2 pins)
------ ------
Total Inst: 43892 43892

It is actually not easy for the tool to determine which one of the two inputs: the layout or the schematic
is correct. It can just report that there is a discrepancy. In this case, we see that everything is not
so bad. We have the same number of nMOS and pMOS transistors, resistors and diodes as well as
the same number of top level connections. We have to look at the RVE to really understand what is
going on:

22
Similar to the DRC part of the exercise, the errors have been specifically introduced to show some typical problems
encountered when dealing with LVS. Due to time constraints they are not particularly challenging.

14
 Number of Errors

No SMILEY List of Errors

The problem

As seen from the Layout As seen from the Netlist

If you have not introduced any additional errors during DRC fixing you should have 5 discrepancies
(errors) during the LVS check. Note that we do not have a smiley face but a frowning face. This
is because the layout does not match the schematic. LVS errors are more difficult to locate than
DRC errors, since one error can cause multiple discrepancies. In the figure above, we have chosen
D ISCREPANCY #1. At the bottom you can see the problem. The left hand side is the Layout side
and the right hand side is the Schematic (called Source in DRV). The report can be interpreted as
follows:

In the Layout there is a single net X16/245 but in the Schematic there are two separate
nets Xi_small_example/Xadd_x_1/n12 and Xi_small_example/Xadd_x_1/n11
that match to the single net in the layout.

This is a typical mistake, most probably something in the layout has shorted the two nets in the
schematic. Often one mistake results in multiple discrepancies between the layout and the schematic.
Similarly if you find and correct one problem, sometimes many discrepancies disappear at the same
time. Since some LVS problems are related, it is important to go through all discrepancies, and try to
find one that is more obvious23 .
The RVE tool has many interesting features that will allow you to compare the two netlists. Try clicking
on the net name. You will see two schematic windows appear. In some cases this can make it much
easier to understand what is wrong.

23
Some of the discrepancies may be misleading, keep an open mind, and look at them one by one.

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 Student Task 13:
• Let us start by the easiest problems first. Find the discrepancy where the Rst_RB net in
the Source matches two separate nets in the Layout. This should be easy as there should
be a missing connection between the two disjoint nets in the layout.
• Highlight one of the nets from the RVE. Under the menu Highlight→Clear Existing \
Highlights you can toggle the behavior on highlights, either a new highlight replaces the
old one, or multiple highlights are allowed at the same time. It will help if you allow multi-
ple highlights (deselect Clear Existing Highlights) for this particular error, and highlight the
second net.
• Look for an obvious location where these two nets could be joined. And make the connec-
tion.
• Save your changes and run LVS again. This error should have disappeared.

Note that any modification to the layout might result in a DRC error, so you should run a DRC on the
design as well. Depending on your experience you might prefer to process a couple of LVS errors
before you go on with DRC errors. If you make small modifications, it will be less likely that you
generated new DRC errors, but sooner or later you will have to check for DRC errors again.

Student Task 14:

• Find and correct the LVS errors, you will notice at least one pair of discrepancies that are
related and have to be solved at the same time.
• Make sure that your LVS error free design also passes DRC.

Congratulations, you have successfully corrected all errors.

5 Why should there be DRC/LVS errors in my design?

This is a valid question, after all we have only used EDA software to create the final layout, and
have also performed both a V ERIFY G EOMETRY (essentially the equivalent of a DRC) and V ERIFY
C ONNECTIVITY (basically an LVS) and had no errors there. There are a couple of explanations:

• While we did not use it in our design flow, it is possible or sometimes even necessary to make
additional changes on the layout, after C ADENCE EDI E NCOUNTER . This may be required to
add logos, bonding pads, chip corners, additional process control monitors, including IPs for
which there are no design views (lef, lib) for C ADENCE EDI E NCOUNTER etc. In some cases
these additions will be done manually, which is a very error prone operation.
• C ADENCE EDI E NCOUNTER may produce errors, which it can not detect. This may be a ’bug’
in C ADENCE EDI E NCOUNTER (there is no guarantee that there will be none), or (more likely)
a mistake in one of the technology files used to customize C ADENCE EDI E NCOUNTER for a
given technology.
• C ADENCE EDI E NCOUNTER works with abstract views of macro-cells and standard cells.
These cells only include relevant information for the cells, such as pin locations and obstruc-
tions within the cell but not everything like transistors. Some errors may only show up when
the real cells with full layouts are used. In umcL65, there are some complex DRC rules that

16
 involve metal1 and contacts. Since C ADENCE EDI E NCOUNTER does not have any information
on where the contact layer is, under rare circumstances the routing can generate a DRC error
(which will be very easy to fix).
• IC foundries will only accept data if it passes DRC with a certain tool. In our case we have to
make sure that the Calibre DRC run reports no errors, otherwise the foundry will return the chip
back to us for fixing.
• And last but not least, ASIC design is a very costly process, additional verification by a second
tool would increase our confidence in the overall design.

The next question might be ”So what happens if we actually find an error?”. The obvious answer is to
fix it. But before we start we need to understand the error. Especially modern processes have many
processing options, and many conflicting rules, so the first order of business is to identify the problem
and verify that it actually violates a design rule that needs to be fixed.
In our case, most of the time we will be violating various ”Metal Coverage” rules. However, we
have an agreement with our IC foundry that stipulates that the IC foundry will perform a ”metal filling”
step that will get rid of all problems with ”Metal Coverage”, so we can safely ignore these errors.
The second step is to try to determine what caused the error. If at all possible it is better to find a fix
that can be implemented in earlier stages (i.e. in C ADENCE EDI E NCOUNTER ) rather than fixing the
problem manually24 . Sometimes this will not be possible, the reason may not be clear at the time, or
there might be significant time pressure to finalize the design as soon as possible, and you might be
forced to correct the error manually.

6 Conclusion

DRC and LVS are both an essential part of the design flow. Ideally, the EDA tools should produce
error free designs. However, this is not always the case. In addition having a second opinion from a
different tool is always good.
Especially LVS errors can be tricky to locate and to correct. These exercises are not meant to be a
thorough manual on how to find and correct all types of errors, but to give you an idea on what can
be done.
It is important to run a DRC after you modify the layout, as any edit could potentially also result in
new design rule violations. Similarly, if you modify a layout that was LVS-clean, you should re-run
LVS.
Our design is now ready to be fabricated. The next step will be to send the GDS to the manufacturing
facility. Usually there are some additional post processing steps such as dummy structures to achieve
a minimum density at all layers, adding a seal ring around the chip to prevent cracking due to the
dicing process, drawing identifiers to the chip to help identification etc.

24
As mentioned earlier, manually altering the layout is a very error-prone process. In addition, the design might require
another iteration (for a completely different reason) leaving you to fix the same error over and over for subsequent
iterations.

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