Max 17126

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kr
TION KIT
19-4681; Rev 1; 3/10 EVALUA BLE
AVA A
IL
Multi-Output Power Supplies with VCOM Amplifier

and High-Voltage Gamma Reference for LCD TVs
General Description Features
MAX17126/MAX17126A
The MAX17126/MAX17126A generate all the supply rails S 8.0V to 16.5V IN Supply-Voltage Range
for thin-film transistor liquid-crystal display (TFT LCD) S Selectable Frequency (500kHz/750kHz)
TV panels operating from a regulated 12V input. They
S Current-Mode Step-Up Regulator
include a step-down and a step-up regulator, a positive
and a negative charge pump, an operational amplifier, Fast Load-Transient Response
a high-accuracy high-voltage gamma reference, and High-Accuracy Output Voltage (1.0%)
a high-voltage switch control block. The MAX17126/ Built-In 20V, 4.2A, 100mI MOSFET
MAX17126A can operate from input voltages from 8V High Efficiency
to 16.5V and is optimized for an LCD TV panel running Adjustable Soft-Start
directly from 12V supplies. Adjustable Current Limit
Low Duty-Cycle Operation (13.2VIN - 13.5V AVDD)
The step-up and step-down switching regulators feature
S Current-Mode Step-Down Regulator
internal power MOSFETs and high-frequency opera-
tion allowing the use of small inductors and capacitors, Fast Load-Transient Response
resulting in a compact solution. The step-up regulator Built-In 20V, 3.2A, 100mI MOSFET
provides TFT source driver supply voltage, while the High Efficiency
step-down regulator provides the system with logic sup- 3ms Internal Soft-Start
ply voltage. Both regulators use fixed-frequency current- S Adjustable Positive Charge-Pump Regulator
mode control architectures, providing fast load-transient S Adjustable Negative Charge-Pump Regulator
response and easy compensation. A current-limit func-
S Integrated High-Voltage Switch with Adjustable
tion for internal switches and output-fault shutdown pro-
Turn-On Delay
tects the step-up and step-down power supplies against
fault conditions. The MAX17126/MAX17126A provide S High-Speed Operational Amplifier
soft-start functions to limit inrush current during startup. Q200mA Short-Circuit Current
In addition, the MAX17126/MAX17126A integrate a con- 45V/µs Slew Rate
trol block that can drive an external p-channel MOSFET S High-Accuracy Reference for Gamma Buffer
to sequence power to source drivers. Q1% Feedback Voltage
The positive and negative charge-pump regulators pro- Up to 30mA Load Current
vide TFT gate-driver supply voltages. Both output volt- Low-Dropout Voltage 0.5V at 60mA
ages can be adjusted with external resistive voltage- S External p-Channel Gate Control for AVDD
dividers. A logic-controlled, high-voltage switch block Sequencing
allows the manipulation of the positive gate-driver supply.
S PGOOD Comparator
The MAX17126/MAX17126A include one high-current
S Input Undervoltage Lockout and Thermal-
operational amplifier designed to drive the LCD back-
Overload Protection
plane (VCOM). The amplifier features high output cur-
rent (Q200mA), fast slew rate (45V/Fs), wide bandwidth S 48-Pin, 7mm x 7mm, Thin QFN Package
(20MHz), and rail-to-rail outputs.
Also featured in the MAX17126/MAX17126A is a high- Ordering Information
accuracy, high-voltage adjustable reference for gamma PART TEMP RANGE PIN-PACKAGE
correction. MAX17126ETM+ -40NC to +85NC 48 Thin QFN-EP*
The MAX17126/MAX17126A are available in a small (7mm MAX17126AETM+ -40NC to +85NC 48 Thin QFN-EP*
x 7mm), ultra-thin (0.8mm), 48-pin thin QFN package and +Denotes a lead(Pb)-free/RoHS-compliant package.
operate over the -40NC to +85NC temperature range. *EP = Exposed pad.
Applications
LCD TV Panels Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com. Datasheet pdf - http://www.DataSheet4U.net/
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ABSOLUTE MAXIMUM RATINGS
MAX17126/MAX17126A
INVL, IN2, VOP, EN, FSEL to GND........................-0.3V to +24V VREF_I to GND.......................................................-0.3V to +24V
PGND, OGND, CPGND to GND...........................-0.3V to +0.3V VREF_O to GND........................................-0.3V, (VREF_I + 0.3)V
DLY1, GVOFF, THR, VL to GND...........................-0.3V to +7.5V REF Short Circuit to GND...........................................Continuous
REF, FBP, FBN, FB1, FB2, COMP, SS, CLIM, RMS LX1 Current (total for both pins)..................................3.2 A
PGOOD, VDET, VREF_FB, OUT to GND.........-0.3V, (VL+ 0.3) RMS PGND CURRENT (total for both pins).........................3.2 A
GD, GD_I to GND...................................................-0.3V to +24V RMS IN2 Current (total for both pins)..................................3.2 A
LX1 to PGND..........................................................-0.3V to +24V RMS LX2 Current (total for both pins)..................................3.2 A
OPP, OPN, OPO to OGND.......................... -0.3V to VOP + 0.3V RMS DRVN, DRVP Current...................................................0.8A
DRVP to CPGND....................................... -0.3V to SUPP + 0.3V RMS VL Current...................................................................50mA
DRVN to CPGND....................................... -0.3V to SUPN + 0.3V Continuous Power Dissipation (TA = +70NC)
LX2 to PGND.................................................-0.7 to (IN2 + 0.3V) 48-Pin TQFN
SUPN to GND..............................................-0.3V to (IN2 + 0.3V) (derated 38.5mW/NC above +70NC)........................3076.9mW
SUPP to GND........................................... -0.3V to (GD_I + 0.3V) Junction Temperature......................................................+160NC
BST to VL................................................................-0.3V to +30V Storage Temperature Range............................. -65NC to +165NC
VGH to GND...........................................................-0.3V to +40V Lead Temperature (soldering, 10s).................................+300NC
VGHM, DRN to GND...................................... -0.3V, VGH + 0.3V Soldering Temperature (reflow).......................................+260NC
VGHM to DRN........................................................-0.3V to +40V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VINVL= VIN2 = 12V, VVOP = VVREF_I = 15V, TA = 0°C to +85°C. Typical values are at TA = +25NC, unless oth-
erwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS

GENERAL
INVL, IN2 Input-Voltage Range 8 16.5 V
Only LX2 switching (VFB1 = VFBP = 1.5V, VFBN = 0V)
INVL + IN2 Quiescent Current 8.5 20 mA
EN = VL, FSEL = high
LX2 not switching (VFB1 = VFB2 = VFBP = 1.5V,
INVL + IN2 Standby Current 24 5 mA
VFBN = 0V), EN = VL, FSEL = high
FSEL = INVL or high impedance 630 750 870
SMPS Operating Frequency kHz
FSEL = GND 420 500 580
INVL Undervoltage-Lockout
INVL rising, 150mV typical hysteresis 6.0 7.0 8.0 V
Threshold
VL REGULATOR
IVL = 25mA, VFB1 = VFB2 = VFBP = 1.1V, VFBN = 0.4V
VL Output Voltage 4.85 5 5.15 V
(all regulators switching)
VL Undervoltage-Lockout
VL rising, 50mV typical hysteresis 3.5 3.9 4.3 V
Threshold
REFERENCE
REF Output Voltage No external load 1.2375 1.250 1.2625 V
REF Load Regulation 0V < ILOAD < 50FA 5 mV
REF Sink Current In regulation 10 FA
REF Undervoltage-Lockout
Rising edge, 250mV typical hysteresis 1.0 1.2 V
Threshold
2 _______________________________________________________________________________________
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ELECTRICAL CHARACTERISTICS (continued)
MAX17126/MAX17126A
erwise noted.)
STEP-DOWN REGULATOR
FB2 = GND, no load 0°C < TA = +85°C 3.25 3.3 3.35
OUT Voltage in Fixed Mode V
(Note 1) TA = +25°C 3.267 3.333
FB2 Voltage in Adjustable VOUT = 2.5V, no load 0°C < TA = +85°C 1.23 1.25 1.27
V
Mode (Note 1) TA = +25°C 1.2375 1.2625
FB2 Adjustable Mode
Dual Mode™ comparator 0.10 0.15 0.20 V
Threshold Voltage
Output Voltage Adjust Range 1.5 5 V
FB2 Fault-Trip Level Falling edge 0.96 1.0 1.04 V
FB2 Input Leakage Current VFB2 = 1.25V 50 125 200 nA
DC Load Regulation 0V < ILOAD < 2A 0.5 %
DC Line Regulation No load, 10.8V < VIN2 < 13.2V 0.1 %/V
LX2-to-IN2 nMOS Switch
100 200 mI
On-Resistance
LX2-to-GND2 nMOS Switch
6 10 23 I
On-Resistance
BST-to-VL pMOS Switch
40 30 110 I
On-Resistance
Low-Frequency Operation
LX2 only 0.8 V
OUT Threshold
Low-Frequency Operation FSEL = INVL 125
kHz
Switching Frequency FSEL = GND 83
MAX17126 2.50 3.20 3.90
LX2 Positive Current Limit A
MAX17126A 3.0 3.5 4.0
Soft-Start Ramp Time Zero to full limit 3 ms
Maximum Duty Factor 70 78 85 %
Minimum Duty Factor
10 %
Char/Design Limit Only
STEP-UP REGULATOR
Output Voltage Range VIN 20 V
Oscillator Maximum Duty Cycle 70 78 85 %
FB1 Regulation Voltage FB1 = COMP, CCOMP = 1nF 1.2375 1.25 1.2625 V
FB1 Fault Trip Level Falling edge 0.96 1.0 1.04 V
FB1 Load Regulation 0V < ILOAD < full 0.5 %
FB1 Line Regulation 10.8V < VIN < 13.2V 0.08 %/V
FB1 Input Bias Current VFB1 = 1.25V 30 125 200 nA
FB1 Transconductance DI = Q2.5FA at COMP, FB1 = COMP 150 320 560 FS
FB1 Voltage Gain FB1 to COMP 1400 V/V
LX1 Leakage Current VFB1 = 1.5V, VLX1 = 20V 10 40 FA
Dual Mode is a trademark of Maxim Integrated Products, Inc.
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MAX17126/MAX17126A
erwise noted.)
VFB1 = 1.1V, RCLIM = unconnected 3.6 4.2 4.8
4.2 -
LX1 Current Limit A
VFB1 = 1.1V, with RCLIM at CLIM pin -20% (68k/ +20%
RCLIM)
CLIM Voltage RCLIM = 60.5kI 0.56 0.625 0.69 V
Current-Sense Transresistance 0.19 0.21 0.25 V/A
LX1 On-Resistance 100 185 mI
Soft-Start Period CSS < 200pF 16 ms
SS Charge Current VSS = 1.2V 4 5 6 FA
POSITIVE CHARGE-PUMP REGULATORS
GD_I Input Supply Range 8.0 20 V
GD_I Input Supply Current VFBP = 1.5V (not switching) 0.15 0.3 mA
GD_I Overvoltage Threshold GD_I rising, 250mV typical hysteresis (Note 2) 20.1 21 22 V
FBP Regulation Voltage 1.2375 1.25 1.2625 V
FBP Line Regulation Error VSUP = 11V to 16V, not in dropout 0.2 %/V
FBP Input Bias Current VFBP = 1.5V, TA = +25°C -50 +50 nA
DRVP p-Channel MOSFET
1.5 3 I
On-Resistance
DRVP n-Channel MOSFET
1 2 I
On-Resistance
FBP Fault Trip Level Falling edge 0.96 1.0 1.04 V
7-bit voltage ramp with filtering to prevent high peak
Positive Charge-Pump 4 ms
currents 500kHz frequency
Soft-Start Period
750kHz frequency 3 ms
NEGATIVE CHARGE-PUMP REGULATORS
FBN Regulation Voltage VREF - VFBN 0.99 1.00 1.01 V
FBN Input Bias Current VFBN = 0mV, TA = +25°C -50 +50 nA
FBN Line Regulation Error VIN2 = 11V to 16V, not in dropout 0.2 %/V
DRVN PCH On-Resistance 1.5 3 I
DRVN NCH On-Resistance 1 2 I
FBN Fault Trip Level Rising edge 720 800 880 mV
7-bit voltage ramp with filtering to prevent high peak
Negative Charge-Pump Soft- 3
currents 500kHz frequency ms
Start Period
750kHz frequency 2
AVDD SWITCH GATE CONTROL
GD to GD_I Pullup Resistance EN = GND 25 50 I
GD Output Sink Current EN = VL 5 10 15 FA
GD Done Threshold EN = VL, VGD_I - VGD 5 6 7 V
OPERATIONAL AMPLIFIERS
VOP Supply Range 8 20 V
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MAX17126/MAX17126A
erwise noted.)
VOP Overvoltage Fault
VVOP = rising, hysteresis = 200mV (Note 2) 20.1 21 22 V
Threshold
VOP Supply Current Buffer configuration, VOPP = VOPN = VOP/2, no load 2 4 mA
Input Offset Voltage 2V < (VOPP, VOPN ) < (VVOP - 2V) 3 14 mV
Input Bias Current 2V < (VOPP, VOPN ) < (VVOP - 2V) -1 +1 FA
Input Common-Mode
0 VOP V
Voltage Range
Input Common-Mode
2V < (VOPP, VOPN ) < (VVOP - 2V) 80 dB
Rejection Ratio
VOP - VOP -
Output Voltage Swing High IOPO = 25mA mV
320 150
Output Voltage Swing Low IOPO = -25mA 150 300 mV
Large-Signal Voltage Gain 2V < (VOPP, VOPN ) < (VOP - 2V) 80 dB
Slew Rate 2V < (VOPP, VOPN ) < (VOP - 2V) 45 V/Fs
-3dB Bandwidth 2V < (VOPP, VOPN ) < (VOP - 2V) 20 MHz
Short to VVOP/2, sourcing 200
Short-Circuit Current mA
Short to VVOP/2, sinking 200
HIGH-VOLTAGE SWITCH ARRAY
VGH Supply Range 35 V
VGH Supply Current 150 300 FA
VGHM-to-VGH Switch
VDLY1 = 2V, GVOFF = VL 5 10 I
On-Resistance
VGHM-to-VGH Switch
VVGH - VVGHM > 5V 150 390 mA
Saturation Current
VGHM-to-DRN Switch
VDLY1 = 2V, GVOFF = GND 20 50 I
On-Resistance
VGHM-to-DRN Switch
VVGHM - VDRN > 5V 75 200 mA
Saturation Current
VGHM-to-GND Switch
DLY1 = GND 1.0 2.5 4.0 kI
On-Resistance
GVOFF Input Low Voltage 0.6 V
GVOFF Input High Voltage 1.6 V
GVOFF Input Current VGVOFF = 0V or VL, TA = +25°C -1 +1 FA
1kI from DRN to CPGND, VGVOFF = 0V to VL step, no
GVOFF-to-VGHM Rising
load on VGHM, measured from GVOFF = 2V to VGHM 100 ns
Propagation Delay
= 20%
1kI from DRN to CPGND, VGVOFF = VL to 0V step, no
GVOFF-to-VGHM Falling
load on VGHM, DRN falling, no load on DRN and VGHM, 200 ns
Propagation Delay
measured from VGVOFF = 0.6V to VGHM = 80%
THR-to-VGHM Voltage Gain 9.4 10 10.6 V/V
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MAX17126/MAX17126A
erwise noted.)
SEQUENCE CONTROL
EN Pulldown Resistance 1 MI
VDLY1 = 1V; when DLY1 cap is not used, there is no
DLY1 Charge Current 6 8 10 FA
delay
EN, DLY1 Turn-On Threshold 1.19 1.25 1.31 V
DLY1 Discharge Switch
EN = GND or fault tripped 10 I
On-Resistance
FBN Discharge Switch
(EN = GND and INVL < UVLO) or fault tripped 3 kI
On-Resistance
GAMMA REFERENCE
VREF_I Input-Voltage Range 10 18.0 V
VREF_I Input Bias Current No load 125 250 FA
VREF_O Dropout Voltage IVREF_O = 60mA 0.25 0.5 V
VVREF_I = 13.5V, 1mA P IVREF_O P 30mA, VVREF_O = 9.5V 1.243 1.250 1.256 V
VREF_FB Regulation Voltage
VVREF_I from 10V to 18V, IVREF_O = 20mA, VVREF_O = 9.5V P 0.9 mV/V
VREF_O Maximum Output
60 mA
Current
PGOOD FUNCTION
VDET Threshold VDET rising 1.274 1.3 1.326 V
VDET Hysteresis 50 mV
VDET Input Bias Current 50 175 300 nA
PGOOD Output Voltage VDET = AGND, IPGOOD = 1mA 0.4 V
FAULT DETECTION
Duration-to-Trigger Fault For UVP only 50 ms
0.36 x 0.4 x 0.44 x
Step-Up Short-Circuit Protection FB1 falling edge V
VREF VREF VREF
0.18 x 0.2 x 0.22 x
Adjustable mode FB2 falling
Step-Down Short-Circuit VREF VREF VREF
V
Protection Fixed mode OUT falling, internal feedback divider 0.18 x 0.2 x 0.22 x
voltage VREF VREF VREF
Positive Charge-Pump 0.36 x 0.4 x 0.44 x
FBP falling edge V
Short-Circuit Protection VREF VREF VREF
Negative Charge-Pump
VREF - VFBN 0.4 0.45 0.5 V
Short-Circuit Protection
Thermal-Shutdown Threshold Latch protection +160 NC
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MAX17126/MAX17126A
erwise noted.)
SWITCHING FREQUENCY SELECTION
FSEL Input Low Voltage 500kHz 0.6 V
FSEL Input High Voltage 750kHz 1.6 V
FSEL Pullup Resistance 1 MI
ELECTRICAL CHARACTERISTICS
(VINVL = VIN2 = 12V, VVOP = VVREF_I = 15V, TA = -40NC to +85NC.) (Note 3)
GENERAL
INVL, IN2 Input-Voltage Range 8 16.5 V
FSEL = INVL or high impedance 630 870
SMPS Operating Frequency kHz
FSEL = GND 420 580
INVL Undervoltage-Lockout
INVL rising, 150mV typical hysteresis 6.0 8.0 V
Threshold
VL REGULATOR
IVL = 25mA, VFB1 = VFB2 = VFB = 1.1V, VFBN = 0.4V
VL Output Voltage 4.85 5.15 V
(all regulators switching)
VL Undervoltage-Lockout
VL rising, 50mV typical hysteresis 3.5 4.3 V
Threshold
REFERENCE
REF Output Voltage No external load 1.235 1.265 V
REF Undervoltage-Lockout
Rising edge, 25mV typical hysteresis 1.2 V
Threshold
STEP-DOWN REGULATOR
OUT Voltage in Fixed Mode FB2 = GND, no load (Note 1) 3.267 3.333 V
FB2 Voltage in Adjustable Mode VOUT = 2.5V, no load (Note 1) 1.2375 1.2625 V
FB2 Adjustable Mode
Dual-mode comparator 0.10 0.20 V
Threshold Voltage
Output Voltage Adjust Range 1.5 5 V
FB2 Fault Trip Level Falling edge 0.96 1.04 V
LX2-to-IN2 nMOS Switch
200 mI
On-Resistance
LX2-to-GND2 nMOS Switch
6 23 I
On-Resistance
BST-to-VL pMOS Switch
40 110 I
On-Resistance
MAX17126 2.50 3.90
LX2 Positive Current Limit A
MAX17126A 3.0 4.0
Maximum Duty Factor 70 85 %
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MAX17126/MAX17126A

STEP-UP REGULATOR
Output-Voltage Range VIN 20 V
Oscillator Maximum Duty Cycle 70 85 %
FB1 Regulation Voltage FB1 = COMP, CCOMP = 1nF 1.2375 1.2625 V
FB1 Fault Trip Level Falling edge 0.96 1.04 V
FB1 Transconductance DI = Q2.5FA at COMP, FB1 = COMP 150 560 FS
LX1 Input Bias Current VFB1 = 1.5V, VLX1 = 20V 40 FA
VFB1 = 1.1V, RCLIM = unconnected 3.6 4.8
LX1 Current Limit VFB1 = 1.1V , with RCLIM at CLIM pin, limit = 3.5A - A
-20% +20%
(60.5K/RCLIM)
CLIM Voltage RCLIM = 60.5kI 0.56 0.69 V
Current-Sense Transresistance 0.19 0.25 V/A
LX1 On-Resistance 185 mI
SS Charge Current VSS = 1.2V 4 6 FA
POSITIVE CHARGE-PUMP REGULATORS
GD_I Input Supply Range 8.0 20 V
GD_I Input Supply Current VFBP = 1.5V (not switching) 0.2 mA
GD_I Overvoltage Threshold GD_I rising, 250mV typical hysteresis (Note 2) 20.1 22 V
FBP Regulation Voltage 1.243 1.256 V
FBP Line Regulation Error VSUP = 11V to 16V, not in dropout 0.2 %/V
DRVP p-Channel MOSFET
3 I
On-Resistance
DRVP n-Channel MOSFET
1 I
On-Resistance
FBP Fault Trip Level Falling edge 0.96 1.04 V
NEGATIVE CHARGE-PUMP REGULATORS
FBN Regulation Voltage VREF - VFBN 0.99 1.01 V
FBN Line Regulation Error VIN2 = 11V to 16V, not in dropout 0.2 %/V
DRVN PCH On-Resistance 3 I
DRVN NCH On-Resistance 1 I
FBN Fault Trip Level Rising edge 720 880 mV
AVDD SWITCH GATE CONTROL
GD Output Sink Current EN = VL 5 15 FA
GD Done Threshold EN = VL, VGD_I - VGD 5 7 V
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MAX17126/MAX17126A
OPERATIONAL AMPLIFIERS
VOP Supply Range 8 20 V
VOP Overvoltage Fault Threshold VOP = rising, hysteresis = 200mV (Note 2) 20.1 22 V
VOP Supply Current Buffer configuration, VOPP = VOPN = VOP/2, no load 4 mA
Input Offset Voltage 2V < (VOPP, VOPN ) < (VOP - 2V) 14 mV
Input Common-Mode
0 OVIN V
Voltage Range
VOP -
Output Voltage Swing High IOPO = 25mA mV
320
Output Voltage Swing Low IOPO = -25mA 300 mV
Short to VOPO/2, sourcing 200
Short-Circuit Current mA
Short to VOPO/2, sinking 200
HIGH-VOLTAGE SWITCH ARRAY
VGH Supply Range 35 V
VGH Supply Current 300 FA
VGHM-to-VGH Switch
VDLY1 = 2V, GVOFF = VL 10 I
On-Resistance
VGHM-to-VGH Switch
VVGH - VVGHM > 5V 150 mA
Saturation Current
VGHM-to-DRN Switch
VDLY1 = 2V, GVOFF = GND 50 I
On-Resistance
VGHM-to-DRN Switch
VVGHM - VDRN > 5V 75 mA
Saturation Current
VGHM-to-GND Switch
DLY1 = GND 1.0 4.0 kI
On-Resistance
GVOFF Input Low Voltage 0.6 V
GVOFF Input High Voltage 1.6 V
THR-to-VGHM Voltage Gain 9.4 10.6 V/V
SEQUENCE CONTROL
EN Input Low Voltage 0.6 V
EN Input High Voltage 1.6 V
VDLY1 = 1V; when DLY1 cap is not used,
DLY1 Charge Current 6 10 FA
there is no delay
DLY1 Turn-On Threshold 1.19 1.31 V
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MAX17126/MAX17126A

GAMMA REFERENCE
VREF_I Input Voltage Range 10 18.0 V
VREF_I Undervoltage Lockout VREF_I rising 5.2 V
VREF_I Input Bias Current No load 250 FA
VREF_O Dropout Voltage IVREF_O = 60mA 0.5 V
VREF_I = 13.5V, 1mA ≤ IVREF_O ≤ 30mA 1.2375 1.2625 V
VREF_FB Regulation Voltage
VREF_I from 10V to 18V, IVREF_O = 20mA P 0.9 mV/V
VREF_O Maximum
60 mA
Output Current
PGOOD FUNCTION
VDET Threshold VDET rising 1.274 1.326 V
PGOOD Output Voltage VDET = AGND, IPGOOD = 1mA 0.4 V
FAULT DETECTION
Step-Up Short-Circuit 0.36 x 0.44 x
FB1 falling edge V
Protection VREF VREF
0.18 x 0.22 x
Adjustable mode FB2 falling V
Step-Down Short-Circuit VREF VREF
Protection Fixed mode OUT falling, internal feedback divider 0.18 x 0.22 x
V
voltage VREF VREF
Positive Charge-Pump 0.36 x 0.44 x
FBP falling edge V
Short-Circuit Protection VREF VREF
Negative Charge-Pump
VREF - VFBN 0.4 0.5 V
Short-Circuit Protection
SWITCHING FREQUENCY SELECTION
FSEL Input Low Voltage 500kHz 0.6 V
FSEL Input High Voltage 750kHz 1.6 V
Note 1: When the step-down inductor is in continuous conduction (EN = VL or heavy load), the output voltage has a DC regulation
level lower than the error comparator threshold by 50% of the output voltage ripple. In discontinuous conduction (EN = GND
with light load), the output voltage has a DC regulation level higher than the error comparator threshold by 50% of the output
voltage ripple.
Note 2: Disables boost switching if either GD_I or VOP exceeds the threshold. Switching resumes when no threshold is exceeded.
Note 3: Specifications to TA = -40NC are guaranteed by design, not production tested.
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Typical Operating Characteristics
MAX17126/MAX17126A
(TA = +25°C, unless otherwise noted.)
STEP-DOWN REGULATOR EFFICIENCY STEP-DOWN REGULATOR OUTPUT

vs. LOAD CURRENT VOLTAGE vs. LOAD CURRENT
85 3.350
MAX17126 toc01
MAX17126 toc02
80
750kHz 750kHz
75
OUTPUT VOLTAGE (V)

3.325
EFFICIENCY (%)
70
500kHz
65
3.300
60 500kHz
55
50 3.275
0.10 1.00 10.00 0 0.42 0.80 1.20 1.60 2.00 2.40
LOAD CURRENT (A) LOAD CURRENT (A)
STEP-DOWN REGULATOR LOAD STEP-DOWN REGULATOR HEAVY-LOAD

TRANSIENT RESPONSE (0.3A TO 1.8A) SOFT-START (1A)
MAX17126 toc03 MAX17126 toc04
VIN
5V/div
VOUT
0V (AC-COUPLED) VOUT
200mV/div 0V 1V/div
0V
IL2
IL2 1A/div
0A 1A/div 0A
ILOAD LX2
0A 1A/div 0A 10V/div
20Fs/div 4ms/div
L = 4.7FH
STEP-UP REGULATOR EFFICIENCY STEP-UP REGULATOR OUTPUT

vs. LOAD CURRENT VOLTAGE vs. LOAD CURRENT
100 16.445
MAX17126 toc06
MAX17126 toc05
95
16.440
90
16.435
OUTPUT VOLTAGE (V)
85
500kHz
EFFICIENCY (%)
80 16.430
75 750kHz
16.425
70
65 750kHz 500kHz
16.420
60
16.415
55
50 16.410
0.01 0.10 1.00 10.00 0 0.5 1.0 1.5 2.0 2.5
LOAD CURRENT (A) LOAD CURRENT (A)
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Typical Operating Characteristics (continued)
MAX17126/MAX17126A
STEP-UP REGULATOR LOAD TRANSIENT STEP-UP REGULATOR PULSED LOAD

RESPONSE (0.1A TO 1.1A) TRANSIENT RESPONSE (0.1A TO 1.9mA)
ILOAD 0V ILOAD
0V 1A/div 1A/div
VAVDD VAVDD
0A (AC-COUPLED) 0A (AC-COUPLED)
200mV/div 200mV/div
IL1 IL1
0A 1A/div 0A 1A/div
20Fs/div 10Fs/div
L = 10FH L = 10FH
STEP-UP REGULATOR HEAVY LOAD SWITCHING FREQUENCY

SOFT-START (0.5A) vs. INPUT VOLTAGE
MAX17126 toc09
498
MAX17126 toc10
EN 497
5V/div 496
SWITCHING FREQUENCY (kHz)
0V
VAVDD 495
5V/div 494
0V VGD 493
5V/div
492
491
0V
490
IL1
1A/div 489
0A 488
1ms/div 8 10 12 14 16
VIN (V)
REFERENCE VOLTAGE LOAD GAMMA REFERENCE LINE REGULATION GAMMA REFERENCE LOAD
REGULATION (LOAD = 20mA) REGULATION (VREF = 16V)
1.2490 15.14 15.2
MAX17126 toc13
MAX17126 toc11
MAX17126 toc12
15.1
GAMMA REFERENCE VOLTAGE (V)
GAMMA REFERENCE VOLTAGE (V)
15.09
1.2485
REFERENCE VOLTAGE (V)
15.0
15.04
1.2480 SWITCHING 14.9
14.99
14.8
1.2475
NO SWITCHING 14.94
14.7
1.2470
14.89 14.6
1.2465 14.84 14.5

0 50 100 150 200 15.0 15.5 16.0 16.5 17.0 17.5 18.0 0 50 100 150 200 250
LOAD CURRENT (FA) VOP VOLTAGE (V) LOAD CURRENT (mA)
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MAX17126/MAX17126A
POSITIVE CHARGE-PUMP REGULATOR POSITIVE CHARGE-PUMP REGULATOR

NORMALIZED LINE REGULATION NORMALIZED LOAD REGULATION
2 0.5
MAX17126 toc15
MAX17126 toc14
0
IGON = 0A 0
OUTPUT CURRENT ERROR (%)

-2
VGON ERROR (%)
-0.5
-4
-6 IGON = 25mA
-1.0
-8
-1.5
-10
-12 -2.0
10 11 12 13 14 15 16 17 18 0 50 100 150
SUPP VOLTAGE (V) LOAD CURRENT (mA)
NEGATIVE CHARGE-PUMP REGULATOR

POSITIVE CHARGE-PUMP REGULATOR
NORMALIZED LINE REGULATION
LOAD-TRANSIENT RESPONSE
MAX17126 toc16 0.01
MAX17126 toc17
0
IGON = 25mA
VGOFF ERROR (%)
VGON
0V (AC-COUPLED) -0.01
200mV/div IGON = 0mA
-0.02
60mA
ILOAD -0.03
20mA/div
0A 10mA
-0.04
8 9 10 11 12 13 14 15 16
40Fs/div
SUPN VOLTAGE (V)
NEGATIVE CHARGE-PUMP REGULATOR NEGATIVE CHARGE-PUMP REGULATOR

NORMALIZED LOAD REGULATION LOAD TRANSIENT RESPONSE
MAX17126 toc19
0.2
MAX17126 toc17
0
OUTPUT VOLTAGE ERROR (%)
-0.2
VGOFF
0V (AC-COUPLED)
-0.4 200mV/div
-0.6
60mA
-0.8
ILOAD
20mA/div
-1.0
0A 10mA
-1.2
0 50 100 150 200 250 300 20Fs/div
LOAD CURRENT (mA)
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MAX17126/MAX17126A
POWER-UP SEQUENCE OF ALL OP AMP SUPPLY CURRENT

SUPPLY OUTPUTS vs. SUPPLY VOLTAGE
MAX17126 toc19
2.65
MAX17126 toc20
VIN
0V 2.60
VOUT
VOP SUPPLY CURRENT (mA)

0V 2.55
0V
VGOFF
0V VAVDD 2.50
VGON
2.45
0V
0V VCOM 2.40
VDLY1
0V
0V 2.35
VGHM
0V
2.30
10ms/div 8 9 10 11 12 13 14 15 16 17 18 19 20
VIN = 10V/div VGON = 20V/div
VOUT = 5V/div VCOM = 10V/div VOP VOLTAGE (V)
VGOFF = 10V/div VDLY1 = 5V/div
VAVDD =10V/div VGHM = 50V/div
OPERATIONAL AMPLIFIER RAIL-TO-RAIL OPERATIONAL AMPLIFIER LOAD

INPUT/OUTPUT WAVEFORMS TRANSIENT RESPONSE
VOPP
5V/div
VCOM
0V (AC-COUPLED)
500mV/div
0V
VCOM
5V/div
IVCOM
0A 100mA/div
0V
4Fs/div 1Fs/div
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MAX17126/MAX17126A
OPERATIONAL AMPLIFIER
SMALL-SIGNAL STEP RESPONSE VIN SUPPLY CURRENT vs. VIN VOLTAGE
MAX17126 toc25
7
MAX17126 toc26
ALL OUTPUT SWITCHING
6
INVL CURRENT (mA)

BUCK OUTPUT SWITCHING
VOPP 4
0V (AC-COUPLED) NO OUTPUT SWITCHING
200mV/div 3
2
VCOM
0V (AC-COUPLED) 1
200mV/div
0
100ns/div 8 10 12 14 16
INPUT VOLTAGE (V)
OPERATIONAL AMPLIFIER HIGH-VOLTAGE SWITCH CONTROL

LARGE-SIGNAL STEP RESPONSE FUNCTION (VGHM WITH 470pF LOAD)
VGVOFF
5V/div
0V
VGHM
0V VOPP 10V/div
5V/div
0V
VCOM
0V
5V/div
1Fs/div 4Fs/div
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Pin Description
MAX17126/MAX17126A
PIN NAME FUNCTION

1 VREF_I Gamma Reference Input
2 VOP Operational Amplifier Power Supply
3 OGND Operational Amplifier Power Ground
4 OPP Operational Amplifier Noninverting Input
5 OPN Operational Amplifier Inverting Input
6 OPO Operational Amplifier Output
7 PGOOD Input voltage power-good open-drain output pulled high to VL or 3.3V through 10kI resistor.
High-Voltage Switch-Control Block Timing Control Input. See the High-Voltage Switch Control
8 GVOFF
section for details.
9 EN Enable Input. Enable is high, turns on step-up converter and positive charge pump.
Step-Down Regulator Feedback Input. Connect FB2 to GND to select the step-down converter’s 3.3V
fixed mode. For adjustable mode, connect FB2 to the center of a resistive voltage-divider between the
10 FB2
step-down regulator output (OUT) and GND to set the step-down regulator output voltage. Place the
resistive voltage-divider within 5mm of FB2.
11 OUT Step-Down Regulator Output Voltage Sense. Connect OUT to step-down regulator output.
12 N.C. Not Connected
Step-Down Regulator Switching Node. LX2 is the source of the internal n-channel MOSFET connected
13, 14 LX2 between IN2 and LX2. Connect the inductor and Schottky catch diode to both LX2 pins and minimize
the trace area for lowest EMI.
Step-Down Regulator Bootstrap Capacitor Connection. Power supply for high-side gate driver. Connect
15 BST
a 0.1FF ceramic capacitor from BST to LX2.
Step-Down Regulator Power Input. Drain of the internal n-channel MOSFET connected between IN2
16, 17 IN2
and LX2.
18, 44 GND Analog Ground
Voltage-Detector Input. Connects VDET to the center of a resistor voltage-divider between input voltage
19 VDET
and GND to set the trigger point of PGOOD.
Internal 5V Linear Regulator and the Startup Circuitry Power Supply. Bypass VINVL to GND with 0.22FF
20 INVL
close to the IC.
5V Internal Linear Regulator Output. Bypass VL to GND with 1FF minimum. Provides power for the
internal MOSFET driving circuit, the PWM controllers, charge-pump regulators, logic, and reference
21 VL
and other analog circuitry. Provides 25mA load current when all switching regulators are enabled. VL is
active whenever input voltage is high enough.
Frequency Select Pin. Connect FSEL to VL or INVL or float FSEL pin for 750kHz operation. Connect to
22 FSEL
GND for 500kHz operation.
Boost Current-Limit Setting Input. Connects a resistor from CLIM to GND to set current limit for boost
23 CLIM
converter.
Soft-Start Input. Connects a capacitor from SS to GND to set the soft-start time for the step-up convert-
er. A 5FA current source starts to charge CSS when GD is done. See the Step-Up Regulator External
24 SS
pMOS Pass Switch section for description. SS is internally pulled to GND through 1kI resistance when
EN is low OR when VL is below its UVLO threshold.
Step-Up Regulator Power-MOSFET n-Channel Drain and Switching Node. Connects the inductor and
25, 26 LX1
Schottky catch diode to both LX1 pins and minimizes the trace area for lowest EMI.
27, 28 PGND Step-Up Regulator Power Ground
Step-Up Regulator External pMOS Pass Switch Source Input. Connects to the cathode of the step-up
29 GD_I
regulator Schottky catch diode.
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Pin Description (continued)
MAX17126/MAX17126A
PIN NAME FUNCTION
Step-Up Regulator External pMOS Pass Switch Gate Input. A 10FA P 20% current source pulls down
30 GD
on the gate of the external pFET when EN is high.
Boost Regulator Feedback Input. Connects FB1 to the center of a resistive voltage-divider between the
31 FB1 boost regulator output and GND to set the boost regulator output voltage. Place the resistive voltage-
divider within 5mm of FB1.
Compensation Pin for the Step-Up Regulator Error Amplifier. Connects a series resistor and capacitor
32 COMP
from COMP to ground.
VGHM Low-Level Regulation Set-Point Input. Connects THR to the center of a resistive voltage-divider
33 THR between AVDD and GND to set the VGHM falling regulation level. The actual level is 10 x VTHR. See the
Switch Control section for details.
Positive Charge-Pump Drivers Power Supply. Connects to the output of the boost regulator (AVDD) and
34 SUPP
bypasses to CPGND with a 0.1FF capacitor. SUPP is internally connected to GD_I.
35 CPGND Charge Pump and Buck Power Ground
36 DRVP Positive Charge-Pump Driver Output. Connects DRVP to the positive charge-pump flying capacitor(s).
High-Voltage Switch Array Delay Input. Connects a capacitor from DLY1 to GND to set the delay time
between when the positive charge pump finishes its soft-start and the startup of this high-voltage switch
37 DLY1
array. A 10FA current source charges CDLY1. DLY1 is internally pulled to GND through 50I resistance
when EN is low or when VL is below its UVLO threshold.
Positive Charge-Pump Regulator Feedback Input. Connects FBP to the center of a resistive voltage-
38 FBP divider between the positive charge-pump regulator output and GND to set the positive charge-pump
regulator output voltage. Place the resistive voltage-divider within 5mm of FBP.
39 VGH Switch Input. Source of the internal high-voltage p-channel MOSFET between VGH and VGHM.
Internal High-Voltage MOSFET Switch Common Terminal. VGHM is the output of the high-voltage
40 VGHM
switch-control block.
41 DRN Switch Output. Drain of the internal high-voltage p-channel MOSFET connected to VGHM.
Negative Charge-Pump Drivers Power Supply. Bypass to CPGND with a 0.1FF capacitor. SUPN is inter-
42 SUPN
nally connected to IN2.
Negative Charge-Pump Driver Output. Connects DRVN to the negative charge-pump flying
43 DRVN
capacitor(s).
Negative Charge-Pump Regulator Feedback Input. Connect FBN to the center of a resistive voltage-
45 FBN divider between the negative output and REF to set the negative charge-pump regulator output voltage.
Place the resistive voltage-divider within 5mm of FBN.
Reference Output. Connects a 0.22FF capacitor from REF to GND. All power outputs are disabled until
46 REF
REF exceeds its UVLO threshold.
Gamma Reference Feedback Input. Connect VREF_FB to the center of a resistive voltage-divider
47 VREF_FB between VREF_O and GND to set the gamma reference output voltage. Place the resistive voltage-
divider within 5mm of VREF_FB.
48 VREF_O Gamma Reference Output
Exposed Pad. Connects EP to GND, and ties EP to a copper plane or island. Maximizes the area of this
— EP
copper plane or island to improve thermal performance.
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MAX17126/MAX17126A
VIN
12V
C1
L1
10µH
0.1µF D1
BST
LX1
IN2
LX1 C2
C4 IN2
PGND
PGND
FB1
COMP R2
L2 CCOMP
OUT FSEL RCOMP
LX2 1nF
3.3V, 1.5A 25kI
C5 D2 LX2 CLIM
R1
OUT
GD_I
Q1
GD
VL (OR 3.3V)
FB2
MAX17126 10kI VIN
MAX17126A R7
PGOOD AVDD
68.1kI 16V, 1A
VIN INVL VDET C3
0.1µF
R8
422kI
VL VL VOP
1µF OPP 0.1µF 13.3kI
REF REF OPN
0.22µF
OPO
GND OGND
2.2kI
ON/OFF 1kI
EN
DRN 13.3kI
DLY1 VCOM
0.1uF THR
SS 3Ω
UNCONNECTED OR 150nF
FROM 2.2kI
GVOFF TCON 150µF
AVDD VREF_I VGHM
VGHM
GREF VREF_O
VGH
SUPP 1.61kI
R9
0.1µF
VREF_FB 1.3nF
D3 VGH
SUPN 35V, 50mA
R10 0.1µF
DRVP
1µF
D4 C12
DRVN
VGOFF
-6V, 50mA C14 R3
0.1µF
C11 FBN FBP CPGND
1µF R5 C10 C13 AVDD
0.1µF
D5
C15 R4
R6 33pF
REF
Figure 1. Typical Operating Circuit
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Typical Operating Circuit Detailed Description
MAX17126/MAX17126A
The typical operating circuit (Figure 1) of the MAX17126/ The MAX17126/MAX17126A are multiple-output power
MAX17126A comprise a complete power-supply system supplies designed primarily for TFT LCD TV panels. It
for TFT LCD TV panels. The circuit generates a +3.3V contains a step-down switching regulator to generate the
logic supply, a +16V source driver supply, a +35V posi- supply for system logic, a step-up switching regulator to
tive gate-driver supply, a -6V negative gate-driver supply, generate the supply for source driver, and two charge-
and a P 0.5% high-accuracy, high-voltage gamma refer- pump regulators to generate the supplies for TFT gate
ence. Table 1 lists some selected components and Table drivers, a high-accuracy, high-voltage reference supply
2 lists the contact information for component suppliers. for gamma correction. Each regulator features adjust-
able output voltage, digital soft-start, and timer-delayed
Table 1. Component List fault protection. Both the step-down and step-up regula-
tors use fixed-frequency current-mode control architec-
DESIGNATION DESCRIPTION
ture. The two switching regulators are 180N out of phase
10FF P Q10%, 25V X5R ceramic
to minimize the input ripple. The internal oscillator offers
capacitors (1206)
C1–C4 two pin-selectable frequency options (500kHz/750kHz),
Murata GRM31CR61E106K
allowing users to optimize their designs based on the
TDK C3216X5R1E106M
specific application requirements. The step-up regu-
22FF Q10%, 6.3V X5R ceramic capacitor lator also features adjustable current limit that can
(0805) be adjusted through a resistor at the CLIM pin. The
C5
Murata GRM21BR60J226K
MAX17126/MAX17126A include one high-performance
TDK C2012X5R0J226K
operational amplifier designed to drive the LCD back-
Schottky diodes 30V, 3A (M-flat) plane (VCOM). The amplifier features high-output cur-
D1, D2
Toshiba CMS02 rent (P 200mA), fast slew rate (45V/Fs), wide bandwidth
Dual diodes 30V, 200mA (3 SOT23) (20MHz), and rail-to-rail outputs. The high-accuracy,
D3, D4, D5 Zetex BAT54S high-voltage gamma reference has its error controlled to
Fairchild BAT54S within P 0.5% and can deliver more than 60mA current.
In addition, the MAX17126/MAX17126A feature a high-
Inductor, 10FH, 3A, 45mI inductor
voltage switch-control block, an internal 5V linear regula-
(8.3mm x 9.5mm x 3mm)
tor, a 1.25V reference output, well-defined power-up and
L1 Coiltronics SD8328-100-R
Sumida CDRH8D38NP-100N (8.3mm x
power-down sequences, and fault and thermal-overload
8.3mm x 4mm) protection. Figure 2 shows the MAX17126/MAX17126A
functional diagram.
Inductor, 4.7FH, 3A, 24.7mI inductor
(8.3mm x 9.5mm x 3mm)
L2 Coiltronics SD8328-4R7-R
Sumida CDRH8D38NP-4R7N (8.3mm x
8.3mm x 4mm)
Table 2. Operating Mode

SUPPLIER PHONE FAX WEBSITE
Fairchild Semiconductor 408-822-2000 408-822-2102 www.fairchildsemi.com
Sumida Corp. 847-545-6700 847-545-6720 www.sumida.com
TDK Corp. 847-803-6100 847-390-4405 www.component.tdk.com
Toshiba America Electronic Components, Inc. 949-455-2000 949-859-3963 www.toshiba.com/taec
______________________________________________________________________________________ 19

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MAX17126/MAX17126A
VIN
L1
BST
IN2 LX1
VL
OUT LX2 STEP-UP

STEP-DOWN
REG REG
OSC PGND
FB1
OUT COMP
FSEL
CLIM
GD_I
GD
VL (OR 3.3V) AVDD
FB2 150mV
VIN INVL REF VIN

PGOOD
VL VL
VL VDET
REF REF
REF
GND VOP
VCOM OPP
EN AMP
ON/OFF
SEQUENCE
DLY1 OPN
SS OPO VCOM
OGND
AVDD VREF_I
DRN
GREF VREF_O
GAMMA
REF THR
HIGH- GVOFF
VOLTAGE FROM
VREF_FB SWITCH TCON
VGHM VGHM
BLOCK
VGH
IN2
SUPP
50% GD_I
SUPN OSC
VGH
DRVP
VGOFF NEGATIVE POSITIVE
DRVN
CHARGE CHARGE
PUMP PUMP
CPGND CPGND
FBN FBP
AVDD
REF
Figure 2. Functional Diagram
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Step-Down Regulator Dual-Mode Feedback
MAX17126/MAX17126A
The step-down regulator consists of an internal n-chan- The step-down regulator of the MAX17126/MAX17126A
nel MOSFET with gate driver, a lossless current-sense support both fixed output and adjustable output. Connect
network, a current-limit comparator, and a PWM con- FB2 to GND to enable the 3.3V fixed-output voltage.
troller block. The external power stage consists of a Connect a resistive voltage-divider between OUT and
Schottky diode rectifier, an inductor, and output capaci- GND with the center tap connected to FB2 to adjust the
tors. The output voltage is regulated by changing the output voltage. Choose RB (resistance from FB2 to GND)
duty cycle of the high-side MOSFET. A bootstrap circuit to be between 5kI and 50kI, and solve for RA (resis-
that uses a 0.1FF flying capacitor between LX2 and BST tance from OUT to FB2) using the equation:
provides the supply voltage for the high-side gate driver.
Although the MAX17126/MAX17126A also include a 10I V 
RA = RB ×  OUT - 1
(typ) low-side MOSFET, this switch is used to charge the V
 FB2 
bootstrap capacitor during startup and maintains fixed-
frequency operation at light load and cannot be used as where VFB2 = 1.25V, and VOUT may vary from 1.5V to 5V.
a synchronous rectifier. An external Schottky diode (D2
Because FB2 is a very sensitive pin, a noise filter is gen-
in Figure 1) is always required.
erally required for FB2 in adjustable-mode operation.
PWM Controller Block Place an 82pF capacitor from FB2 to GND to prevent
The heart of the PWM control block is a multi-input, open- unstable operation. No filter is required for 3.3V fixed-
loop comparator that sums three signals: the output- mode operation.
voltage signal with respect to the reference voltage, the
Soft-Start
current-sense signal, and the slope-compensation signal.
The step-down regulator includes a 7-bit soft-start DAC
The PWM controller is a direct-summing type, lacking a
that steps its internal reference voltage from zero to
traditional error amplifier and the phase shift associated
1.25V in 128 steps. The soft-start period is 3ms (typ)
with it. This direct-summing configuration approaches
and FB2 fault detection is disabled during this period.
ideal cycle-by-cycle control over the output voltage.
The soft-start feature effectively limits the inrush current
The step-down controller always operates in fixed-fre- during startup (see the Step-Down Regulator Soft-Start
quency PWM mode. Each pulse from the oscillator sets Waveforms in the Typical Operating Characteristics).
the main PWM latch that turns on the high-side switch
until the PWM comparator changes state. As the high- Step-Up Regulator
side switch turns off, the low-side switch turns on. The The step-up regulator employs a current-mode, fixed-fre-
low-side switch stays on until the beginning of the next quency PWM architecture to maximize loop bandwidth
clock cycle. and provide fast-transient response to pulsed loads
typical of TFT LCD panel source drivers. The integrated
Current Limiting and Lossless Current Sensing MOSFET and the built-in digital soft-start function reduce
The current-limit circuit turns off the high-side MOSFET the number of external components required while
switch whenever the voltage across the high-side controlling inrush currents. The output voltage can be
MOSFET exceeds an internal threshold. The actual cur- set from VIN to 16.5V with an external resistive voltage-
rent limit is typically 3.2A for MAX17126 and 3.5A for divider. The regulator controls the output voltage and the
MAX17126A. power delivered to the output by modulating duty cycle
For current-mode control, an internal lossless sense D of the internal power MOSFET in each switching cycle.
network derives a current-sense signal from the inductor The duty cycle of the MOSFET is approximated by:
DCR. The time constant of the current-sense network is
not required to match the time constant of the inductor VAVDD + VDIODE - VIN
D≈
and has been chosen to provide sufficient current ramp VAVDD + VDIODE - VLX1
signal for stable operation at both operating frequencies.
The current-sense signal is AC-coupled into the PWM where VAVDD is the output voltage of the step-up regu-
comparator, eliminating most DC output-voltage varia- lator, VDIODE is the voltage drop across the diode, and
tion with load current. VLX1 is the voltage drop across the internal MOSFET.
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PWM Controller Block during the output capacitor initial charge, and to provide
MAX17126/MAX17126A
An error amplifier compares the signal at FB1 to 1.25V true shutdown when the step-up regulator is disabled.
and changes the COMP output. The voltage at COMP When EN is low, GD is internally pulled up to the GD_I
sets the peak inductor current. As the load varies, the through a 25I resistor. Once EN is high and the negative
error amplifier sources or sinks current to the COMP charge-pump regulator is in regulation, the GD starts pull-
output accordingly to produce the inductor peak cur- ing down with a 10FA (typ) internal current source. The
rent necessary to service the load. To maintain stabil- external p-channel MOSFET turns on and connects the
ity at high duty cycles, a slope compensation signal is cathode of the step-up regulator Schottky catch diode
summed with the current-sense signal. to the step-up regulator load capacitors when GD falls
On the rising edge of the internal clock, the controller below the turn-on threshold of the MOSFET. When VGD
sets a flip-flop, turning on the n-channel MOSFET and reaches VGD_I - 6V(GD done), the step-up regulator is
applying the input voltage across the inductor. The enabled and initiates a soft-start routine.
current through the inductor ramps up linearly, storing When not using this feature, leave GD high impedance,
energy in its magnetic field. Once the sum of the current- and connect GD_I to the output of the step-up converter.
feedback signal and the slope compensation exceed
Soft-Start
the COMP voltage, the controller resets the flip-flop
The step-up regulator achieves soft-start by linearly
and turns off the MOSFET. Since the inductor current is
ramping up its internal current limit. The soft-start is
continuous, a transverse potential develops across the
either done internally when the capacitance on pin SS is
inductor that turns on diode D1. The voltage across the
< 200pF or externally when capacitance on pin SS is >
inductor then becomes the difference between the out-
200pF. The internal soft-start ramps up the current limit
put voltage and the input voltage. This discharge condi-
in 128 steps in 12ms. The external soft-start terminates
tion forces the current through the inductor to ramp back
when the SS pin voltage reaches 1.25V. The soft-start
down, transferring the energy stored in the magnetic
feature effectively limits the inrush current during startup
field to the output capacitor and the load. The MOSFET
(see the Step-Up Regulator Soft-Start Waveforms in the
remains off for the rest of the clock cycle.
Typical Operating Characteristics).
Step-Up Regulator External pMOS Pass Switch
Positive Charge-Pump Regulator
As shown in Figure 1, a series external p-channel
The positive charge-pump regulator (Figure 3) is typically
MOSFET can be installed between the cathode of the
used to generate the positive supply rail for the TFT LCD
step-up regulator Schottky catch diode and the VAVDD
gate driver ICs. The output voltage is set with an external
filter capacitors. This feature is used to sequence power
resistive voltage-divider from its output to GND with the
to AVDD after the MAX17126/MAX17126A have pro-
midpoint connected to FBP. The number of charge-pump
ceeded through normal startup to limit input surge current
stages and the setting of the feedback divider determine
GD_I SUPP
ERROR OSC C12

P1 D5
AMPLIFIER C14
REF
DRVP
1.25V
C13
N1 D3 VGH
MAX17126
MAX17126A CPGND C15
POSITIVE CHARGE-PUMP REGULATOR

FBP
Figure 3. Positive Charge-Pump Regulator Block Diagram
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the output voltage of the positive charge-pump regula- Negative Charge-Pump Regulator
MAX17126/MAX17126A
tor. The charge pump includes a high-side p-channel The negative charge-pump regulator is typically used to
MOSFET (P1) and a low-side n-channel MOSFET (N1) to generate the negative supply rail for the TFT LCD gate
control the power transfer as shown in Figure 3. driver ICs. The output voltage is set with an external
resistive voltage-divider from its output to REF with the
During the first half cycle, N1 turns on and charges flying
midpoint connected to FBN. The number of charge-pump
capacitors C12 and C13 (Figure 3). During the second
stages and the setting of the feedback divider determine
half cycle, N1 turns off and P1 turns on, level shifting C12
the output of the negative charge-pump regulator. The
and C13 by VSUPP volts. If the voltage across C15 (VGH) charge-pump controller includes a high-side p-channel
plus a diode drop (VD) is smaller than the level-shifted MOSFET (P2) and a low-side n-channel MOSFET (N2) to
flying-capacitor voltage (VC13) plus VSUPP, charge control the power transfer as shown in Figure 4.
flows from C13 to C15 until the diode (D3) turns off. The
During the first half cycle, P2 turns on, and flying capacitor
amount of charge transferred to the output is determined
C10 charges to VSUPN minus a diode drop (Figure 4).
by the error amplifier that controls N1’s on-resistance.
During the second half cycle, P2 turns off, and N2 turns
Each time it is enabled, the positive charge-pump regu- on, level shifting C10. This connects C10 in parallel with
lator goes through a soft-start routine by ramping up its reservoir capacitor C11. If the voltage across C11 minus
internal reference voltage from 0 to 1.25V in 128 steps. a diode drop is greater than the voltage across C10,
The soft-start period is 2ms (typ) and FBP fault detec- charge flows from C11 to C10 until the diode (D4) turns
tion is disabled during this period. The soft-start feature off. The amount of charge transferred from the output is
effectively limits the inrush current during startup. determined by the error amplifier that controls N2’s on-
resistance.
MAX17126 SUPN
IN2
MAX17126A
ERROR OSC
P2
AMPLIFIER
REF C10
DRVN
0.25V
D4
N2 VGOFF
CPGND C11
NEGATIVE CHARGE-PUMP REGULATOR
R5
FBN
REF
R6
Figure 4. Negative Charge-Pump Regulator Block Diagram
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MAX17126/MAX17126A
REF
MAX17126
10µA MAX17126A
DLY1
FAULT
Q4 SHDN
EN
GD DONE
VGH
VREF
Q1
VGHM
9R
1kI
Q2
R
DRN
GVOFF
THR
Figure 5. Switch Control
The negative charge-pump regulator is enabled after The switch control block is disabled and DLY1 is held low
the step-down regulator finishes soft-start. Each time it when the LCD is shut down or in a fault state.
is enabled, the negative charge-pump regulator goes
through a soft-start routine by ramping down its internal Operational Amplifier
reference voltage from 1.25V to 250mV in 128 steps. The The operational amplifier is typically used to drive the
soft-start period is 1.8ms (typ) and FBN fault detection LCD backplane (VCOM). It features Q200mA output
is disabled during this period. The soft-start feature short-circuit current, 45V/Fs slew rate, and 20MHz/3dB
effectively limits the inrush current during startup. bandwidth. The rail-to-rail input and output capability
maximizes system flexibility.
High-Voltage Switch Control
The MAX17126/MAX17126As’ high-voltage switch control Short-Circuit Current Limit and Input Clamp
block (Figure 5) consists of two high-voltage p-channel The operational amplifier limits short-circuit current to
MOSFETs: Q1, between VGH, and VGHM and Q2, between approximately Q200mA if the output is directly shorted
VGHM and DRN. The switch control block is enabled when to VOP or to OGND. If the short-circuit condition persists,
VDLY1 exceeds VREF. Q1 and Q2 are controlled by GVOFF. the junction temperature of the IC rises until it reaches
the thermal-shutdown threshold (+160NC typ). Once
When GVOFF is logic-high, Q1 turns on and Q2 turns the junction temperature reaches the thermal-shutdown
off, connecting VGHM to VGH. When GVOFF is logic- threshold, an internal thermal sensor immediately sets
low, Q1 turns off and Q2 turns on, connecting VGHM to the thermal fault latch, shutting off all the IC’s outputs.
DRN. VGHM can then be discharged through a resistor The device remains inactive until the input voltage is
connected between DRN and GND or AVDD. Q2 turns cycled. The operational amplifiers have 4V input clamp
off and stops discharging VGHM when VGHM reaches structures in series with a 500I resistance and a diode
10 times the voltage on THR. (Figure 6).
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Reference Voltage (REF)
MAX17126/MAX17126A
The reference output is nominally 1.25V, and can source
MAX17126 at least 50FA (see Typical Operating Characteristics). VL
MAX17126A is the input of the internal reference block. Bypass REF
VOP with a 0.22FF ceramic capacitor connected between
REF and GND.
OPP
High-Accuracy,
High-Voltage Gamma Reference
±4V 500
The LDO is typically used to drive gamma-correction

divider string. Its output voltage is adjustable through a
resistor-divider. This LDO features high output accuracy
OPN (Q0.5%) and low-dropout voltage (0.25V typ) and can
OPO supply at least 60mA.
OGND PGOOD Function
PGOOD is an open-drain output that connects to GND
when VDET is below its detection threshold (1.25V typ).
PGOOD is active after VL rises above UVLO threshold.
Frequency Selection and
Figure 6. Op Amp Input Clamp Structure
Out-of-Phase Operation (FSEL)
Driving Pure Capacitive Load The step-down regulator and step-up regulator use
The LCD backplane consists of a distributed series the same internal oscillator. The FSEL input selects
capacitance and resistance, a load that can be easily the switching frequency. Table 3 shows the switching
driven by the operational amplifier. However, if the frequency based on the FSEL connection. High-frequency
operational amplifier is used in an application with a pure (750kHz) operation optimizes the application for the
capacitive load, steps must be taken to ensure stable smallest component size, trading off efficiency due
operation. As the operational amplifier’s capacitive load to higher switching losses. Low-frequency (500kHz)
increases, the amplifier’s bandwidth decreases and gain operation offers the best overall efficiency at the expense
peaking increases. A 5I to 50I small resistor placed of component size and board space.
between OPO and the capacitive load reduces peaking, To reduce the input RMS current, the step-down regulator
but also reduces the gain. An alternative method of and the step-up regulator operate 180N out of phase
reducing peaking is to place a series RC network from each other. The feature allows the use of less input
(snubber) in parallel with the capacitive load. The RC capacitance.
network does not continuously load the output or reduce
the gain. Typical values of the resistor are between 100I Table 3. Frequency Selection
and 200I, and the typical value of the capacitor is 10nF.
SWITCHING FREQUENCY
FSEL
Linear Regulator (VL) (kHz)
The MAX17126/MAX17126A include an internal linear VL, INVL, OR FLOAT 750
regulator. INVL is the input of the linear regulator. The
GND 500
input voltage range is between 8V and 16.5V. The output
voltage is set to 5V. The regulator powers the internal
MOSFET drivers, PWM controllers, charge-pump
regulators, and logic circuitry. The total external load
capability is 25mA. Bypass VL to GND with a minimum
1FF ceramic capacitor.
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Power-Up Sequence The MAX17126/MAX17126A simplify system design
MAX17126/MAX17126A
The step-down regulator starts up when the MAX17126/ by including an internal 12ms soft-start for the step-up
MAX17126As’ internal reference voltage (REF) is above regulator. When the capacitor on the SS pin is less than
its undervoltage lockout (UVLO) threshold. Once the 200pF, the internal 12ms soft-start is in place. This saves
step-down regulator soft-start is done, the FB2 fault- one capacitor from system design. If an external capaci-
detection circuit and the negative charge pump are tor greater than 200pF is used, a 5µA current source
enabled. Negative charge-pump fault protection is charges the SS capacitor pin and when the SS voltage
enabled after its own soft-start is done. reaches 1.25V, soft-start is done. The FB1 fault-detection
When EN goes to logic-high, a 10µA current source circuit is enabled after this soft-start is done.
starts to pull down on GD, turning on the external GD_I- The positive charge pump is also enabled after the
AVDD PMOS switch. When VGD reaches GD-done step-up regulator finishes its soft-start. After the positive
threshold (VGD_I - 6V), the step-up regulator is enabled. charge pump’s soft-start is done, the FBP fault-detection
Gamma reference is enabled at the same time. circuit is enabled, as well as the high-voltage switch
delay block. CDLY1 is charged with an internal 10µA
current source and VDLY1 rises linearly. When VDLY1
reaches REF, the high-voltage switch block is enabled.
IN/INVL
INVL UVLO VL
VL
REF
UVLO
REF EN
UVLO BUCK
OUTPUT
tSS
TIME NEGATIVE
tSS
CHARGE-PUMP
BUCK FAULT BLANK REGULATOR
OUTPUT
NEGATIVE CHARGE-PUMP FAULT BLANK
PGOOD
TIME POSITIVE
CHARGE-PUMP
POSITIVE CHARGE -PUMP FAULT BLANK REGULATOR
BOOST FAULT BLANK OUTPUT
AVDD
GREF
GD
GD SS
DONE
REF
TIME
tSS tSS
DLY1
REF
TIME
VGHM UNCONNECTED VGHM DEPENDS VGHM

ON GVOFF
TIME
Figure 7. Power-Up Sequence
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Power-Down Sequence Fault Protection
MAX17126/MAX17126A
The step-down regulator, step-up regulator, positive During steady-state operation, if any output of the four
charge pump, negative charge pump, and high-voltage regulators’ output (step-down regulator, step-up regulator,
switching block all start to shut down when INVL drops positive charge-pump regulator, and negative charge-pump
below its UVLO threshold. VL stays flat until INVL does regulator) goes lower than its respective fault-detection
not have enough headroom. Reference REF starts to fall threshold, the MAX17126 activates an internal fault timer. If
after VL drops below its UVLO threshold. any condition or the combination of conditions indicates a
continuous fault for the fault timer duration (50ms typ), the
Gamma reference GREF stays flat until AVDD does not MAX17126A latches off all its outputs while the MAX17126
have enough headroom. A pMOS switch turns on after latches off all the outputs except the buck regulator (latched
VL drops below its UVLO threshold to guarantee GREF off only when the fault happens on its output).
does not go over AVDD.
If a short has happened to any of the four regulator
PGOOD is pulled low after its input voltage (buck output outputs, no fault timer is applied; the part latches off
in this case) drops below the designed threshold. After immediately. Pay special attention to shorts on the step-
VL drops below its UVLO threshold, PGOOD gives up up regulator and positive charge pump. Make sure when
control and is resistively pulled up to its input voltage. a short happens, negative ringing on VREF_I (connected
The high-voltage switching block output VGHM falls until to step-up regulator output) and VGH (connected to
VL drops below its UVLO threshold, after which it is in positive charge-pump output) does not exceed Absolute
Maximum Ratings. Otherwise, physical damage of the
high impedance.
part may occur. Cycle the input voltage to clear the fault
latch and restart the supplies.
Thermal-Overload Protection
The thermal-overload protection prevents excessive
power dissipation from overheating the MAX17126/
INVL INVL UVLO MAX17126A. When the junction temperature exceeds
TJ = +160NC, a thermal sensor immediately activates
VL VL UVLO the fault protection that shuts down all the outputs. Cycle
REF the input voltage to clear the fault latch and restart the
MAX17126/MAX17126A.
TIME
The thermal-overload protection protects the controller in
NEGATIVE the event of fault conditions. For continuous operation, do
CHARGE-PUMP
REGULATOR not exceed the absolute maximum junction temperature
OUTPUT TIME rating of TJ = +150NC.
POSITIVE
CHARGE-PUMP
REGULATOR Design Procedure
OUTPUT
AVDD
Step-Down Regulator
GREF
Inductor Selection
Three key inductor parameters must be specified:
inductance value (L), peak current (IPEAK), and DC
TIME resistance (RDC). The following equation includes a
BUCK
OUTPUT constant, LIR, which is the ratio of peak-to-peak inductor
PGOOD ripple current to DC load current. A higher LIR value
TIME allows smaller inductance, but results in higher losses
and higher ripple. A good compromise between size
VGHM DEPENDS
VGHM ON GVOFF VGHM UNCONNECTED and losses is typically found at a 30% ripple current-to-
load current ratio (LIR = 0.3) that corresponds to a peak
TIME inductor current 1.15 times the DC load current:
VOUT × (VIN2 - VOUT )

L2 =
Figure 8. Power-Down Sequence VIN2 × fSW × IOUT(MAX) × LIR
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where IOUT(MAX) is the maximum DC load current, and
MAX17126/MAX17126A
the switching frequency fSW is 750kHz when FSEL is VOUT × (VIN2 - VOUT )
IRMS = IOUT ×
tied to VL, 500kHz when FSEL is tied to GND. The exact VIN2
inductor value is not critical and can be adjusted to
make trade-offs among size, cost, and efficiency. Lower The worst case is IRMS = 0.5 x IOUT that occurs at VIN2
inductor values minimize size and cost, but they also = 2 x VOUT.
increase the output ripple and reduce the efficiency For most applications, ceramic capacitors are used
due to higher peak currents. On the other hand, higher because of their high ripple current and surge current
inductor values increase efficiency, but at some point capabilities. For optimal circuit long-term reliability,
resistive losses due to extra turns of wire exceed the choose an input capacitor that exhibits less than +10NC
benefit gained from lower AC current levels. temperature rise at the RMS input current corresponding
The inductor’s saturation current must exceed the peak to the maximum load current.
inductor current. The peak current can be calculated by:
Output Capacitor Selection
V × (VIN2 - VOUT )
IOUT_RIPPLE = OUT Since the MAX17126/MAX17126As’ step-down regulator
fSW × L 2 × VIN2 is internally compensated, it is stable with any reasonable
amount of output capacitance. However, the actual
I capacitance and equivalent series resistance (ESR)
IOUT_PEAK = IOUT(MAX) + OUT_RIPPLE affect the regulator’s output ripple voltage and transient
2
response. The rest of this section deals with how to
The inductor’s DC resistance should be low for good determine the output capacitance and ESR needs
efficiency. Find a low-loss inductor having the lowest according to the ripple voltage and load-transient
possible DC resistance that fits in the allotted dimensions. requirements.
Ferrite cores are often the best choice. Shielded- The output voltage ripple has two components: variations
core geometries help keep noise, EMI, and switching in the charge stored in the output capacitor, and the
waveform jitter low. voltage drop across the capacitor’s ESR caused by the
Considering the typical operation circuit in Figure 1, the current into and out of the capacitor:
maximum load current IOUT(MAX) is 1.5A with a 3.3V
output and a typical 12V input voltage. Choosing an LIR VOUT_RIPPLE = VOUT_RIPPLE(ESR) + VOUT_RIPPLE(C)
of 0.4 at this operation point:
3.3V × (12V - 3.3V) VOUT_RIPPLE(ESR) = IOUT_RIPPLE × R ESR_OUT
L2 = ≈ 5.3FH
12V × 750kHz × 1.5A × 0.4
IOUT_RIPPLE
Pick L2 = 4.7FH. At that operation point, the ripple current VOUT_RIPPLE(C) =
and the peak current are: 8 × C OUT × fSW
3.3V × (12V - 3.3V) where IOUT_RIPPLE is defined in the Step-Down Regulator

IOUT_RIPPLE = = 0.68A
750kHz × 4.7FH × 12V Inductor Selection section, COUT (C5 in Figure 1) is the
output capacitance, and RESR_OUT is the ESR of the
0.68A output capacitor COUT. In Figure 1’s circuit, the inductor
IOUT_PEAK = 1.5A + = 1.84A
2 ripple current is 0.68A. If the voltage-ripple requirement of
Figure 1’s circuit is P 1% of the 3.3V output, then the total
peak-to-peak ripple voltage should be less than 66mV.
Input Capacitors
Assuming that the ESR ripple and the capacitive ripple
The input filter capacitors reduce peak currents drawn
each should be less than 50% of the total peak-to-peak
from the power source and reduce noise and voltage
ripple, then the ESR should be less than 48.5mI and the
ripple on the input caused by the regulator’s switching.
output capacitance should be more than 3.4FF to meet
They are usually selected according to input ripple
the total ripple requirement. A 22FF capacitor with ESR
current requirements and voltage rating, rather than
(including PCB trace resistance) of 10mI is selected
capacitance value. The input voltage and load current
for the typical operating circuit in Figure 1, which easily
determine the RMS input ripple current (IRMS):
meets the voltage ripple requirement.
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The step-down regulator’s output capacitor and ESR The maximum output current, input voltage, output
MAX17126/MAX17126A
also affect the voltage undershoot and overshoot when voltage, and switching frequency determine the inductor
the load steps up and down abruptly. The undershoot value. Very high inductance values minimize the current
and overshoot also have two components: the voltage ripple, and therefore, reduce the peak current, which
steps caused by ESR, and voltage sag and soar due to decreases core losses in the inductor and I2R losses in
the finite capacitance and inductor slew rate. Use the the entire power path. However, large inductor values
following formulas to check if the ESR is low enough also require more energy storage and more turns of wire
and the output capacitance is large enough to prevent that increase physical size and can increase I2R losses
excessive soar and sag. in the inductor. Low inductance values decrease the
The amplitude of the ESR step is a function of the load physical size, but increase the current ripple and peak
step and the ESR of the output capacitor: current. Finding the best inductor involves choosing the
best compromise between circuit efficiency, inductor
VOUT_ESR_STEP = DIOUT × R ESR_OUT size, and cost.
The equations used here include a constant LIR, which
The amplitude of the capacitive sag is a function of the is the ratio of the inductor peak-to-peak ripple current to
load step, the output capacitor value, the inductor value, the average DC inductor current at the full-load current.
the input-to-output voltage differential, and the maximum The best trade-off between inductor size and circuit
duty cycle: efficiency for step-up regulators generally has an LIR
between 0.3 and 0.5. However, depending on the AC
L 2 × (DIOUT ) 2 characteristics of the inductor core material and ratio of
VOUT_SAG =
(
2 × C OUT × VIN2(MIN) × D MAX - VOUT ) inductor resistance to other power-path resistances, the
best LIR can shift up or down. If the inductor resistance
The amplitude of the capacitive soar is a function of the is relatively high, more ripple can be accepted to
load step, the output capacitor value, the inductor value, reduce the number of turns required and increase the
and the output voltage: wire diameter. If the inductor resistance is relatively low,
increasing inductance to lower the peak current can
L 2 × (DIOUT ) 2 decrease losses throughout the power path. If extremely
VOUT_SOAR = thin high-resistance inductors are used, as is common
2 × C OUT × VOUT
for LCD panel applications, the best LIR can increase to
Keeping the full-load overshoot and undershoot less than between 0.5 and 1.0.
3% ensures that the step-down regulator’s natural integrator Once a physical inductor is chosen, higher and lower
response dominates. Given the component values in the values of the inductor should be evaluated for efficiency
circuit of Figure 1, during a full 1.5A step load transient, the improvements in typical operating regions.
voltage step due to capacitor ESR is negligible. The voltage Calculate the approximate inductor value using the
sag and soar are 76mV and 73mV, respectively. typical input voltage (VIN), the maximum output current
Rectifier Diode (IAVDD(MAX)), the expected efficiency (ETYP) taken
The MAX17126/MAX17126As’ high switching frequency from an appropriate curve in the Typical Operating
demands a high-speed rectifier. Schottky diodes are Characteristics, and an estimate of LIR based on the
recommended for most applications because of their fast above discussion:
recovery time and low forward voltage. In general, a 2A 2
 VIN  VAVDD - VIN  η TYP 
Schottky diode works well in the MAX17126/MAX17126A’s L1 =     
 
step-up regulator.  VAVDD   I AVDD(MAX) × fSW  LIR 
Step-Up Regulator Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input current
Inductor Selection at the minimum input voltage VIN(MIN) using conservation
The inductance value, peak current rating, and series of energy and the expected efficiency at that operating
resistance are factors to consider when selecting the point (EMIN) taken from an appropriate curve in the
inductor. These factors influence the converter’s efficiency, Typical Operating Characteristics:
maximum output load capability, transient response time,
and output voltage ripple. Physical size and cost are also I AVDD(MAX) × VAVDD
IIN(DC,MAX) =
important factors to be considered. VIN(MIN) × η MIN
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Calculate the ripple current at that operating point and the output voltage ripple is typically dominated by
MAX17126/MAX17126A
the peak current required for the inductor: VAVDD_RIPPLE(C). The voltage rating and temperature
I AVDD_RIPPLE =
(
VIN(MIN) × VAVDD - VIN(MIN) ) characteristics of the output capacitor must also be
considered. Note that all ceramic capacitors typically
L AVDD × VAVDD × fSW have large temperature coefficient and bias voltage
coefficients. The actual capacitor value in circuit is
I typically significantly less than the stated value.
I AVDD_PEAK = IIN(DC,MAX) + AVDD_RIPPLE
2
Input Capacitor Selection
The inductor’s saturation current rating and the MAX17126/ The input capacitor reduces the current peaks drawn
MAX17126As’ LX1 current limit should exceed IAVDD_ from the input supply and reduces noise injection
PEAK and the inductor’s DC current rating should exceed into the IC. A 22FF ceramic capacitor is used in the
IIN(DC,MAX). For good efficiency, choose an inductor with typical operating circuit (Figure 1) because of the high
less than 0.1I series resistance. source impedance seen in typical lab setups. Actual
applications usually have much lower source impedance
Considering the typical operating circuit (Figure 1), the since the step-up regulator often runs directly from the
maximum load current (IAVDD(MAX)) is 1A with a 16V output of another regulated supply. Typically, the input
output and a typical input voltage of 12V. Choosing capacitance can be reduced below the values used in
an LIR of 0.3 and estimating efficiency of 90% at this the typical operating circuit.
operating point:
2 Rectifier Diode
 12V   16V - 12V  90%  The MAX17126/MAX17126As’ high switching frequency
L1 =      = 9FH
 16V   1A × 750kHz  0.3  demands a high-speed rectifier. Schottky diodes are
recommended for most applications because of their fast
Using the circuit’s minimum input voltage (8V) and recovery time and low forward voltage. In general, a 2A
estimating efficiency of 85% at that operating point: Schottky diode complements the internal MOSFET well.
1A × 16V Output Voltage Selection
IIN(DC,MAX) = ≈ 2.35A
8V × 85% The output voltage of the step-up regulator can be
adjusted by connecting a resistive voltage-divider from
The ripple current and the peak current are: the output (VAVDD) to GND with the center tap connected
8V × (16V - 8V) to FB1 (see Figure 1). Select R2 in the 10kI to 50kI
I AVDD_RIPPLE = ≈ 0.53A range. Calculate R1 with the following equation:
10FH × 16V × 750kHz
V 
0.53A R1 = R2 ×  AVDD - 1
I AVDD_PEAK = 2.35A + ≈ 2.62A V
 FB1 
2
where VFB1, the step-up regulator’s feedback set point,
Output Capacitor Selection is 1.25V. Place R1 and R2 close to the IC.
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharging Loop Compensation
of the output capacitance, and the ohmic ripple due to Choose RCOMP to set the high-frequency integrator gain
the capacitor’s equivalent series resistance (ESR): for fast-transient response. Choose CCOMP to set the
integrator zero to maintain loop stability.
VAVDD_RIPPLE = VAVDD_RIPPLE(C) + VAVDD_RIPPLE(ESR) For low-ESR output capacitors, use the following
equations to obtain stable performance and good
I V -V 
VAVDD_RIPPLE(C) ≈ AVDD  AVDD IN  transient response:
C AVDD  VAVDDfSW  100 × VIN × VAVDD × C AVDD
R COMP ≈
and: L AVDD × I AVDD(MAX)
VAVDD_RIPPLE(ESR) ≈ I AVDD_PEAKR ESR_AVDD VAVDD × C AVDD
C COMP ≈
10 × I AVDD(MAX) × R COMP
where IAVDD_PEAK is the peak inductor current (see
the Inductor Selection section). For ceramic capacitors,
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To further optimize transient response, vary RCOMP in on the source impedance. A 0.1FF ceramic capacitor
MAX17126/MAX17126A
20% steps and CCOMP in 50% steps while observing works well in most low-current applications. The flying
transient response waveforms. capacitor’s voltage rating must exceed the following:
Charge-Pump Regulators VCX > n POS(NEG) × VSUPP(SUPN)
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest number where nPOS(NEG) is the number of stages in which the
of charge-pump stages that meet the output requirement. flying capacitor appears. It is the same as the number of
charge-pump stages.
The number of positive charge-pump stages is given by:
Charge-Pump Output Capacitor
V + VDROPOUT - VAVDD
n POS = GH Increasing the output capacitance or decreasing the ESR
VSUPP - 2 × VD reduces the output ripple voltage and the peak-to-peak
transient voltage. With ceramic capacitors, the output
where nPOS is the number of positive charge-pump voltage ripple is dominated by the capacitance value.
stages, VGH is the output of the positive charge-pump Use the following equation to approximate the required
regulator, VSUPP is the supply voltage of the charge- capacitor value:
pump regulators, VD is the forward voltage drop of the
charge-pump diode, and VDROPOUT is the dropout ILOAD_CP
margin for the regulator. Use VDROPOUT = 300mV. C OUT_CP R
2 × fSW × VRIPPLE_CP
The number of negative charge-pump stages is given by:
-VGOFF + VDROPOUT where COUT_CP is the output capacitor of the charge
n NEG = pump, ILOAD_CP is the load current of the charge pump,
VSUPN - 2 × VD
and VRIPPLE_CP is the peak-to-peak value of the output
ripple.
where nNEG is the number of negative charge-pump
stages and VGOFF is the output of the negative charge- Output Voltage Selection
pump regulator. Adjust the positive charge-pump regulator’s output
The above equations are derived based on the voltage by connecting a resistive voltage-divider from
assumption that the first stage of the positive charge VGH output to GND with the center tap connected to FBP
pump is connected to VAVDD and the first stage of (Figure 1). Select the lower resistor of divider R4 in the
the negative charge pump is connected to ground. 10kI to 30kI range. Calculate upper resistor R3 with the
Sometimes fractional stages are more desirable for following equation:
better efficiency. This can be done by connecting the
first stage to VOUT or another available supply. If the V 
R3 = R4 ×  VGH - 1
first charge-pump stage is powered from VOUT, then the  VFBP 
above equations become:
V + VDROPOUT - VOUT where VFBP = 1.25V (typ).
n POS = GH
VSUPP - 2 × VD Adjust the negative charge-pump regulator’s output
voltage by connecting a resistive voltage-divider from
VGOFF to REF with the center tap connected to FBN
-VGOFF + VDROPOUT + VOUT (Figure 1). Select R6 in the 20kI to 68kI range. Calculate
nNEG = R5 with the following equation:
VSUPN - 2 × VD
V -V
R5 = R6 × FBN GOFF
Flying Capacitors VREF - VFBN
Increasing the flying capacitor CX (connected to DRVP
and DRVN) value lowers the effective source impedance where VFBN = 250mV, VREF = 1.25V. Note that REF
and increases the output current capability. Increasing can only source up to 50FA, using a resistor less than
the capacitance indefinitely has a negligible effect on 20kI, for R6 results in a higher bias current than REF
output current capability because the internal switch can supply.
resistance and the diode impedance place a lower limit
______________________________________________________________________________________ 31

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High-Accuracy, High-Voltage input loop goes from the positive terminal of the input
MAX17126/MAX17126A
Gamma Reference capacitor to the inductor, to the IC’s LX1 pin, out of
Output-Voltage Selection PGND, and to the input capacitor’s negative terminal.
The output voltage of the high-accuracy LDO is set by The high-current output loop is from the positive ter-
connecting a resistive voltage-divider from the output minal of the input capacitor to the inductor, to the out-
(VREF_O) to AGND with the center tap connected to put diode (D1), to the positive terminal of the output
VREF_FB (see Figure 1). Select R10 in the 10kI to 50kI capacitors, reconnecting between the output capaci-
range. Calculate R9 with the following equation: tor and input capacitor ground terminals. Connect
these loop components with short, wide connections.
V  Avoid using vias in the high-current paths. If vias
R9 = R10 ×  REF_O -1 are unavoidable, use many vias in parallel to reduce
V 
 REF_FB  resistance and inductance.
where VREF_FB, the LDO’s feedback set point, is 1.25V. U Create a power ground island for the step-down
Place R9 and R10 close to the IC. regulator, consisting of the input and output capaci-
tor grounds and the diode ground. Connect all
Input and Output Capacitor Selection these together with short, wide traces or a small
To ensure stability of the LDO, use a minimum of 1FF
ground plane. Similarly, create a power ground island
on the regulator’s input (VREF_I) and a minimum of 2.2FF
(PGND) for the step-up regulator, consisting of the
on the regulator’s output (VREF_O). Place the capacitors
input and output capacitor grounds and the PGND
near the pins and connect their ground connections
pin. Create a power ground island (CPGND) for the
directly together.
positive and negative charge pumps, consisting of
Set the PGOOD Threshold Voltage SUPP and output (VGH, VGOFF) capacitor grounds,
PGOOD threshold voltage can be adjusted by connecting and negative charge-pump diode ground. Connect
a resistive voltage-divider from input VIN to GND with the the step-down regulator ground plane, PGND ground
center tap connected to VDET (see Figure 1). Select R8 in plane, and CPGND ground plane together with wide
the 10kI to 50kI range. Calculate R7 with the following traces. Maximizing the width of the power ground
equation: traces improves efficiency and reduces output volt-
V 
R7 = R8 ×  IN_PGOOD -1 age ripple and noise spikes.
 VDET 
U Create an analog ground plane (GND) consisting of
the GND pin, all the feedback divider ground con-
where VDET = 1.25V is the VDET threshold set point. nections, the COMP, SS, and DLY1 capacitor ground
VIN_PGOOD is the desired PGOOD threshold voltage.
connections, and the device’s exposed backside
Place R7 and R8 close to the IC.
pad. Connect the PGND and GND islands by con-
PCB Layout and Grounding necting the two ground pins directly to the exposed
Careful PCB layout is important for proper operation. Use backside pad. Make no other connections between
the following guidelines for good PCB layout: these separate ground planes.
U Minimize the area of respective high-current loops U Place all feedback voltage-divider resistors as close
by placing each DC/DC converter’s inductor, diode, as possible to their respective feedback pins. The
and output capacitors near its input capacitors and divider’s center trace should be kept short. Placing
its LX_ and PGND pins. For the step-down regulator, the resistors far away causes their FB traces to
the high-current input loop goes from the positive become antennas that can pick up switching noise.
terminal of the input capacitor to the IC’s IN2 pin, out Care should be taken to avoid running any feedback
of LX2, to the inductor, to the positive terminals of the trace near LX1, LX2, DRVP, or DRVN.
output capacitors, reconnecting the output capaci- U Place IN2 pin, VL pin, REF pin, and VREF_O pin
tor and input capacitor ground terminals. The high- bypass capacitors as close as possible to the device.
current output loop is from the inductor to the positive The ground connection of the VL bypass capacitor
terminals of the output capacitors, to the negative should be connected directly to the GND pin with a
terminals of the output capacitors, and to the Schottky wide trace.
diode (D2). For the step-up regulator, the high-current
32 ��

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U Minimize the length and maximize the width of the
MAX17126/MAX17126A
Pin Configuration
traces between the output capacitors and the load for
best transient responses.
U Minimize the size of the LX1 and LX2 nodes while
CPGND
TOP VIEW
COMP
PGND
PGND
DRVP
SUPP
GD_I
THR
FB1
LX1
LX1
keeping them wide and short. Keep the LX1 and LX2
GD
nodes away from feedback nodes (FB1, FB2, FBP, 36 35 34 33 32 31 30 29 28 27 26 25
FBN, and VREF_FB) and analog ground. Use DC DLY1 37 24 SS
traces as shield if necessary.
FBP 38 23 CLIM
Refer to the MAX17126 evaluation kit for an example of VGH 39 22 FSEL
proper board layout.
VGHM 40 21 VL
DRN 41 20 INVL
SUPN 42 19 VDET
DRVN 43 MAX17126 18 GND
MAX17126A
GND 44 17 IN2
FBN 45 16 IN2
Chip Information REF 46 15 BST
PROCESS: BiCMOS VREF_FB 47 14 LX2
VREF_O 48 13 LX2
Package Information 1 2
VOP
3 4 5 6 7 8 9 10 11 12
For the latest package outline information and land patterns, go

VREF_I
OGND
OPP
OPN
OPO
PGOOD
GVOFF
EN
FB2
OUT
N.C.
to www.maxim-ic.com/packages.
PACKAGE PACKAGE OUTLINE LAND PATTERN
THIN QFN
TYPE CODE No. No.
48 TQFN T4877-3 21-0144 90-0129
______________________________________________________________________________________ 33

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Revision History
MAX17126/MAX17126A
REVISION REVISION PAGES

DESCRIPTION
NUMBER DATE CHANGED
0 6/09 Initial release —
1 3/10 MAX17126A added to data sheet 1-33
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
34 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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Multi-Output Power Supplies with VCOM Amplifier

________________________________________________________________ Maxim Integrated Products 1

Multi-Output Power Supplies with VCOM Amplifier

PARAMETER CONDITIONS MIN TYP MAX UNITS

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Multi-Output Power Supplies with VCOM Amplifier

Dual Mode is a trademark of Maxim Integrated Products, Inc.

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Multi-Output Power Supplies with VCOM Amplifier

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Multi-Output Power Supplies with VCOM Amplifier

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Multi-Output Power Supplies with VCOM Amplifier

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Multi-Output Power Supplies with VCOM Amplifier

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Multi-Output Power Supplies with VCOM Amplifier

(VINVL = VIN2 = 12V, VVOP = VVREF_I = 15V, TA = -40NC to +85NC.) (Note 3)

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Multi-Output Power Supplies with VCOM Amplifier

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Multi-Output Power Supplies with VCOM Amplifier

(VINVL = VIN2 = 12V, VVOP = VVREF_I = 15V, TA = -40NC to +85NC.) (Note 3)

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Multi-Output Power Supplies with VCOM Amplifier

STEP-DOWN REGULATOR EFFICIENCY STEP-DOWN REGULATOR OUTPUT

OUTPUT VOLTAGE (V)

STEP-DOWN REGULATOR LOAD STEP-DOWN REGULATOR HEAVY-LOAD

STEP-UP REGULATOR EFFICIENCY STEP-UP REGULATOR OUTPUT

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Multi-Output Power Supplies with VCOM Amplifier

(TA = +25°C, unless otherwise noted.)

STEP-UP REGULATOR LOAD TRANSIENT STEP-UP REGULATOR PULSED LOAD

STEP-UP REGULATOR HEAVY LOAD SWITCHING FREQUENCY

1.2465 14.84 14.5

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Multi-Output Power Supplies with VCOM Amplifier

POSITIVE CHARGE-PUMP REGULATOR POSITIVE CHARGE-PUMP REGULATOR

OUTPUT CURRENT ERROR (%)

NEGATIVE CHARGE-PUMP REGULATOR

NEGATIVE CHARGE-PUMP REGULATOR NEGATIVE CHARGE-PUMP REGULATOR

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Multi-Output Power Supplies with VCOM Amplifier

(TA = +25°C, unless otherwise noted.)

POWER-UP SEQUENCE OF ALL OP AMP SUPPLY CURRENT

VOP SUPPLY CURRENT (mA)

OPERATIONAL AMPLIFIER RAIL-TO-RAIL OPERATIONAL AMPLIFIER LOAD

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Multi-Output Power Supplies with VCOM Amplifier

INVL CURRENT (mA)

OPERATIONAL AMPLIFIER HIGH-VOLTAGE SWITCH CONTROL

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Multi-Output Power Supplies with VCOM Amplifier

PIN NAME FUNCTION

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Multi-Output Power Supplies with VCOM Amplifier

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Multi-Output Power Supplies with VCOM Amplifier

Figure 1. Typical Operating Circuit