Copyright Cirrus Logic, Inc.

2012
(All Rights Reserved)
http://www.cirrus.com
104 dB, 24-Bit, 192 kHz Stereo Audio ADC
A/D Features
Multi-Bit Delta Sigma Modulator
104 dB Dynamic Range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
12 dB Gain, 0.5 dB Step Size
Zero Crossing, Click-Free Transitions
Stereo Microphone Inputs
+32 dB Gain Stage
Low-Noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable Serial Audio Interface Formats
Left-J ustified up to 24-bit
IS up to 24-bit
High-Pass Filter or DC Offset Calibration
System Features
Power-Down Mode
+3.3 V to +5 V Analog Power Supply, Nominal
+3.3 V to +5 V Digital Power Supply, Nominal
Direct Interface with 1.8 V to 5 V Logic Levels
Pin-Compatible with CS4245
General Description
The CS5345 integrates an analog multiplexer, program-
mable gain amplifier, and stereo audio analog-to-digital
converter. The CS5345 performs stereo analog-to-digi-
tal (A/D) conversion of up to 24-bit serial values at
sample rates up to 192 kHz.
A 6:1 stereo input multiplexer is included for selecting
between line-level and microphone-level inputs. The
microphone input path includes a +32 dB gain stage
and a low-noise bias voltage supply. The PGA is avail-
able for line or microphone inputs and provides
gain/attenuation of 12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5th-
order, multi-bit delta sigma modulator and digital filter-
ing/decimation. Sampled data is transmitted by the
serial audio interface at rates from 4 kHz to 192 kHz in
either Slave or Master Mode.
Integrated level translators allow easy interfacing be-
tween the CS5345 and other devices operating over a
wide range of logic levels.
The CS5345 is available in a 48-pin LQFP package in
Commercial (-10 to +70 C) grade. The CDB5345 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. Please re-
fer to Ordering Information on page 42 for complete
details.

1.8 V to 5 V
Low-Latency
Anti-Alias Filter
Internal Voltage
Reference
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Low-Latency
Anti-Alias Filter
High Pass
Filter
High Pass
Filter
Stereo Input 1
Serial
Audio
Output
3.3 V to 5 V 3.3 V to 5 V
MUX
PGA
P
C
M

S
e
r
i
a
l

I
n
t
e
r
f
a
c
e
Register Configuration
L
e
v
e
l
T
r
a
n
s
l
a
t
o
r
Left PGA Output
Right PGA Output
Stereo Input 2
Stereo Input 3
Stereo Input 4 /
Mic Input 1 & 2
Stereo Input 5
Stereo Input 6
PGA
+32 dB
+32 dB
L
e
v
e
l

T
r
a
n
s
l
a
t
o
r
Reset
IC/SPI
Control Data
Interrupt
Overflow
AUG '12
DS658F4
CS5345
2 DS658F4
CS5345
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ......................................................................................................................... 5
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7
SPECIFIED OPERATING CONDITIONS ............................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ....................................................................................................... 7
ADC ANALOG CHARACTERISTICS ................................................................................................... 8
ADC ANALOG CHARACTERISTICS ................................................................................................. 10
ADC DIGITAL FILTER CHARACTERISTICS ..................................................................................... 11
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 12
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 13
PGAOUT ANALOG CHARACTERISTICS .......................................................................................... 14
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 15
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 16
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 17
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ............................................ 20
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 21
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 22
4. APPLICATIONS ................................................................................................................................... 23
4.1 Recommended Power-Up Sequence ............................................................................................. 23
4.2 System Clocking ............................................................................................................................. 23
4.2.1 Master Clock ......................................................................................................................... 23
4.2.2 Master Mode ......................................................................................................................... 24
4.2.3 Slave Mode ........................................................................................................................... 24
4.3 High-Pass Filter and DC Offset Calibration .................................................................................... 24
4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................ 26
4.5 Input Connections ........................................................................................................................... 26
4.6 PGA Auxiliary Analog Output ......................................................................................................... 26
4.7 Control Port Description and Timing ............................................................................................... 27
4.7.1 SPI Mode ............................................................................................................................... 27
4.7.2 IC Mode ................................................................................................................................ 27
4.8 Interrupts and Overflow .................................................................................................................. 29
4.9 Reset .............................................................................................................................................. 29
4.10 Synchronization of Multiple Devices ............................................................................................. 29
4.11 Grounding and Power Supply Decoupling .................................................................................... 29
5. REGISTER QUICK REFERENCE ........................................................................................................ 31
6. REGISTER DESCRIPTION .................................................................................................................. 32
6.1 Chip ID - Register 01h .................................................................................................................... 32
6.2 Power Control - Address 02h ......................................................................................................... 32
6.2.1 Freeze (Bit 7) ......................................................................................................................... 32
6.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 32
6.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 32
6.2.4 Power-Down Device (Bit 0) ................................................................................................... 32
6.3 ADC Control - Address 04h ............................................................................................................ 33
6.3.1 Functional Mode (Bits 7:6) .................................................................................................... 33
6.3.2 Digital Interface Format (Bit 4) .............................................................................................. 33
6.3.3 Mute (Bit 2) ............................................................................................................................ 33
6.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 33
6.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 33
6.4 MCLK Frequency - Address 05h .................................................................................................... 34
6.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 34
6.5 PGAOut Control - Address 06h ...................................................................................................... 34
6.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 34
6.6 Channel B PGA Control - Address 07h .......................................................................................... 34
DS658F4 3
CS5345
6.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 34
6.7 Channel A PGA Control - Address 08h .......................................................................................... 35
6.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 35
6.8 ADC Input Control - Address 09h ................................................................................................... 35
6.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 35
6.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 36
6.9 Active Level Control - Address 0Ch ................................................................................................ 36
6.9.1 Active High/Low (Bit 0) .......................................................................................................... 36
6.10 Interrupt Status - Address 0Dh ..................................................................................................... 36
6.10.1 Clock Error (Bit 3) ................................................................................................................ 37
6.10.2 Overflow (Bit 1) .................................................................................................................... 37
6.10.3 Underflow (Bit 0) .................................................................................................................. 37
6.11 Interrupt Mask - Address 0Eh ....................................................................................................... 37
6.12 Interrupt Mode MSB - Address 0Fh .............................................................................................. 37
6.13 Interrupt Mode LSB - Address 10h ............................................................................................... 37
7. PARAMETER DEFINITIONS ................................................................................................................ 38
8. FILTER PLOTS .................................................................................................................................. 39
9. PACKAGE DIMENSIONS .................................................................................................................... 41
10. THERMAL CHARACTERISTICS AND SPECIFICATIONS ............................................................. 41
11. ORDERING INFORMATION ........................................................................................................ 42
12. REVISION HISTORY .......................................................................................................................... 42
LIST OF FIGURES
Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 18
Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 18
Figure 3.Format 0, Left-J ustified up to 24-Bit Data ................................................................................... 19
Figure 4.Format 1, IS up to 24-Bit Data ................................................................................................... 19
Figure 5.Control Port Timing - IC Format ................................................................................................. 20
Figure 6.Control Port Timing - SPI Format ................................................................................................ 21
Figure 7.Typical Connection Diagram ....................................................................................................... 22
Figure 8.Master Mode Clocking ................................................................................................................ 24
Figure 9.Analog Input Architecture ............................................................................................................ 26
Figure 10.Control Port Timing in SPI Mode .............................................................................................. 27
Figure 11.Control Port Timing, IC Write ................................................................................................... 28
Figure 12.Control Port Timing, IC Read ................................................................................................... 28
Figure 13.Single-Speed Stopband Rejection ............................................................................................ 39
Figure 14.Single-Speed Stopband Rejection ............................................................................................ 39
Figure 15.Single-Speed Transition Band (Detail) ...................................................................................... 39
Figure 16.Single-Speed Passband Ripple ................................................................................................ 39
Figure 17.Double-Speed Stopband Rejection ........................................................................................... 39
Figure 18.Double-Speed Stopband Rejection ........................................................................................... 39
Figure 19.Double-Speed Transition Band (Detail) .................................................................................... 40
Figure 20.Double-Speed Passband Ripple ............................................................................................... 40
Figure 21.Quad-Speed Stopband Rejection ............................................................................................. 40
Figure 22.Quad-Speed Stopband Rejection ............................................................................................. 40
Figure 23.Quad-Speed Transition Band (Detail) ....................................................................................... 40
Figure 24.Quad-Speed Passband Ripple ................................................................................................. 40
LIST OF TABLES
Table 1. Speed Modes .............................................................................................................................. 23
Table 2. Common Clock Frequencies ....................................................................................................... 23
Table 3. MCLK Dividers ............................................................................................................................ 24
Table 4. Slave Mode Serial Bit Clock Ratios ............................................................................................. 24
4 DS658F4
CS5345
Table 5. Device Revision .......................................................................................................................... 32
Table 6. Freeze-able Bits .......................................................................................................................... 32
Table 7. Functional Mode Selection .......................................................................................................... 33
Table 8. Digital Interface Formats ............................................................................................................. 33
Table 9. MCLK Frequency ........................................................................................................................ 34
Table 10. PGAOut Source Selection ......................................................................................................... 34
Table 11. Example Gain and Attenuation Settings ................................................................................... 35
Table 12. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 36
Table 13. Analog Input Multiplexer Selection ............................................................................................ 36
DS658F4 5
CS5345
1. PIN DESCRIPTIONS
Pin Name # Pin Description
SDA/CDOUT 1
Serial Control Data (Input/Output) - SDA is a data I/O in IC

Mode. CDOUT is the output data line for

the control port interface in SPI
TM
Mode.
SCL/CCLK 2 Serial Control Port Clock (Input) - Serial clock for the serial control port.
AD0/CS 3
Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode;
CS is the chip-select signal for SPI format.
AD1/CDIN 4
Address Bit 1 (IC) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in IC Mode;
CDIN is the input data line for the control port interface in SPI Mode.
VLC 5
Control Port Power (Input) - Determines the required signal level for the control port interface. Refer
to the Recommended Operating Conditions for appropriate voltages.
RESET 6 Reset (Input) - The device enters a low-power mode when this pin is driven low.
AIN3A
AIN3B
7
8
Stereo Analog Input 3 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
AIN2A
AIN2B
9
10
Stereo Analog Input 2 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
VLS SDA/CDOUT
A
G
N
D
O
V
F
L
SCL/CCLK
AD0/CS
AD1/CDIN
VLC
RESET
AIN3A
AIN3B
AIN2A
AIN2B
AIN1A
AIN1B
V
A
A
F
I
L
T
B
V
Q
T
S
T
O
F
I
L
T
+
T
S
T
O
A
I
N
4
A
/
M
I
C
I
N
1
A
I
N
4
B
/
M
I
C
I
N
2
A
I
N
5
A
A
I
N
5
B
A
F
I
L
T
A
TSTO
NC
NC
AGND
AGND
VA
PGAOUTB
PGAOUTA
AIN6B
AIN6A
MICBIAS
I
N
T
V
D
D
G
N
D
M
C
L
K
L
R
C
K
S
C
L
K
S
D
O
U
T
N
C
N
C
N
C
T
S
T
I
CS5345
6 DS658F4
CS5345
AIN1A
AIN1B
11
12
Stereo Analog Input 1 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
AGND 13 Analog Ground (Input) - Ground reference for the internal analog section.
VA 14 Analog Power (Input) - Positive power for the internal analog section.
AFILTA 15 Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input.
AFILTB 16 Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input.
VQ 17 Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
TSTO 18 Test Pin (Output) - This pin must be left unconnected.
FILT+ 19 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
TSTO 20 Test Pin - This pin must be left unconnected.
AIN4A/MICIN1
AIN4B/MICIN2
21
22
Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full-scale level is specified in the ADC
Analog Characteristics specification table.
AIN5A
AIN5B
23
24
Stereo Analog Input 5 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
MICBIAS 25
Microphone Bias Supply (Output) - Low-noise bias supply for external microphone. Electrical charac-
teristics are specified in the DC Electrical Characteristics specification table.
AIN6A
AIN6B
26
27
Stereo Analog Input 6 (Input) - The full-scale level is specified in the ADC Analog Characteristics
specification table.
PGAOUTA
PGAOUTB
28
29
PGA Analog Audio Output (Output) - Either an analog output from the PGA block or high impedance.
See PGAOut Source Select (Bit 6) on page 34.
VA 30 Analog Power (Input) - Positive power for the internal analog section.
AGND
31
32
Analog Ground (Input) - Ground reference for the internal analog section.
NC
33
34
No Connect - These pins are not connected internally and should be tied to ground to minimize any
potential coupling effects.
TSTO 35 Test Pin (Output) - This pin must be left unconnected.
VLS 36
Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.
TSTI 37 Test Pin (Input) - This pin must be connected to ground.
NC
38,
39,
40
No Connect - These pins are not connected internally and should be tied to ground to minimize any
potential coupling effects.
SDOUT 41 Serial Audio Data Output (Output) - Output for twos complement serial audio data.
SCLK 42 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK 43
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK 44 Master Clock (Input) - Clock source for the ADCs delta-sigma modulators.
DGND 45 Digital Ground (Input) - Ground reference for the internal digital section.
VD 46 Digital Power (Input) - Positive power for the internal digital section.
INT 47 Interrupt (Output) - Indicates an interrupt condition has occurred.
OVFL 48 Overflow (Output) - Indicates an ADC overflow condition is present.
DS658F4 7
CS5345
2. CHARACTERISTICS AND SPECIFICATIONS
SPECIFIED OPERATING CONDITIONS
AGND=DGND=0V; All voltages with respect to ground.
Notes: 1. Maximum of VA+0.25 V or 5.25 V, whichever is less.
ABSOLUTE MAXIMUM RATINGS
AGND=DGND=0V All voltages with respect to ground. (Note 2)
2. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
3. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause
SCR latch-up.
Parameters Symbol Min Nom Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
VA
VD
VLS
VLC
3.13
3.13
1.71
1.71
5.0
3.3
3.3
3.3
5.25
(Note 1)
5.25
5.25
V
V
V
V
Ambient Operating Temperature (Power Applied) T
A
-10 - +70 C
Parameter Symbol Min Max Units
DC Power Supplies: Analog
Digital
Logic - Serial Port
Logic - Control Port
VA
VD
VLS
VLC
-0.3
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
+6.0
V
V
V
V
Input Current (Note 3) I
in
- 10 mA
Analog Input Voltage V
INA
AGND-0.3 VA+0.3 V
Digital Input Voltage Logic - Serial Port
Logic - Control Port
V
IND-S
V
IND-C
-0.3
-0.3
VLS+0.3
VLC+0.3
V
V
Ambient Operating Temperature (Power Applied) T
A
-50 +125 C
Storage Temperature T
stg
-65 +150 C
8 DS658F4
CS5345
ADC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND =DGND =0 V; VA =3.13 V to 5.25 V; VD =3.13 V to 5.25 V
or VA +0.25 V, whichever is less; VLS =VLC =1.71 V to 5.25 V; T
A
=-10 to +70 C for Commercial; Input test
signal: 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz; Fs =48/96/192 kHz.; All connections as
shown in Figure 7 on page 22.
Line-Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 6) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 6) 40 kHz bandwidth unweighted
98
95
-
92
89
-
104
101
98
98
95
92
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion +Noise (Note 5)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 6) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 6) 40 kHz bandwidth -1 dB
THD+N
-
-
-
-
-
-
-
-
-95
-81
-41
-92
-92
-75
-35
-89
-89
-
-
-
-86
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
(Note 6) 40 kHz bandwidth unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
(Note 6) 40 kHz bandwidth unweighted
93
90
-
89
86
-
101
98
95
95
92
89
-
-
-
-
-
-
dB
dB
dB
dB
dB
dB
Total Harmonic Distortion +Noise (Note 5)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
(Note 6) 40 kHz bandwidth -1 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
(Note 6) 40 kHz bandwidth -1 dB
THD+N
-
-
-
-
-
-
-
-
-92
-78
-38
-84
-89
-72
-32
-81
-86
-
-
-
-83
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
Line-Level Inputs
Parameter Symbol
Commercial Grade
Unit Min Typ Max
Interchannel Isolation - 90 - dB
DS658F4 9
CS5345
4. Valid for the selected input pair.
DC Accuracy
Gain Error - - 10 %
Gain Drift - 100 - ppm/C
Line-Level Input Characteristics
Full-scale Input Voltage 0.51*VA 0.57*VA 0.63*VA V
pp
Input Impedance (Note 4) 6.12 6.8 7.48 kO
Maximum Interchannel Input Impedance
Mismatch
- 5 - %
Line-Level and Microphone-Level Inputs
Parameter Symbol
Commercial Grade
Unit Min Typ Max
DC Accuracy
Interchannel Gain Mismatch - 0.1 - dB
Programmable Gain Characteristics
Gain Step Size - 0.5 - dB
Absolute Gain Step Error - - 0.4 dB
10 DS658F4
CS5345
ADC ANALOG CHARACTERISTICS
(Continued)
5. Referred to the typical line-level full-scale input voltage
6. Valid for Double- and Quad-Speed Modes only.
7. Valid when the microphone-level inputs are selected.
Microphone-Level Inputs
Parameter Symbol Min Typ Max Unit
Dynamic Performance for VA = 4.75 V to 5.25 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
77
74
65
62
83
80
71
68
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion +Noise (Note 5)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
-
-
-
-
-80
-60
-20
-68
-74
-
-
-
dB
dB
dB
dB
Dynamic Performance for VA = 3.13 V to 3.46 V
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
77
74
65
62
83
80
71
68
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion +Noise (Note 5)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
-
-
-
-
-80
-60
-20
-68
-74
-
-
-
dB
dB
dB
dB
Interchannel Isolation - 80 - dB
DC Accuracy
Gain Error - 5 - %
Gain Drift - 300 - ppm/C
Microphone-Level Input Characteristics
Full-scale Input Voltage 0.013*VA 0.017*VA 0.021*VA V
pp
Input Impedance (Note 7) - 60 - kO
DS658F4 11
CS5345
ADC DIGITAL FILTER CHARACTERISTICS

8. Filter response is guaranteed by design.
9. Response shown is for Fs =48 kHz.
10. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 13 to 24) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
Parameter (Notes 8, 10) Symbol Min Typ Max Unit
Single-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.035 dB
Stopband 0.5688 - - Fs
Stopband Attenuation 70 - - dB
Total Group Delay (Fs =Output Sample Rate) t
gd
- 12/Fs - s
Double-Speed Mode
Passband (-0.1 dB) 0 - 0.4896 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5604 - - Fs
Stopband Attenuation 69 - - dB
Total Group Delay (Fs =Output Sample Rate) t
gd
- 9/Fs - s
Quad-Speed Mode
Passband (-0.1 dB) 0 - 0.2604 Fs
Passband Ripple - - 0.025 dB
Stopband 0.5000 - - Fs
Stopband Attenuation 60 - - dB
Total Group Delay (Fs =Output Sample Rate) t
gd
- 5/Fs - s
High-Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 9)
- 1
20
-
-
Hz
Hz
Phase Deviation @ 20 Hz (Note 9) - 10 - Deg
Passband Ripple - - 0 dB
Filter Settling Time
10
5
/Fs s
12 DS658F4
CS5345
PGAOUT ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): AGND =DGND =0 V; VA =3.13 V to 5.25 V; VD =3.13 V to 5.25 V or
VA +0.25 V, whichever is less; VLS =VLC =1.71 V to 5.25 V; T
A
=-10 to +70 C; Input test signal: 1 kHz sine
wave; Measurement bandwidth: 10 Hz to 20 kHz; Fs =48/96/192 kHz; Synchronous mode; All connections as
shown in Figure 7 on page 22.
11. Referred to the typical Line-Level Full-Scale Input Voltage.
VA = 4.75 V to 5.25 V
Parameter Symbol Min Typ Max Unit
Dynamic Performance with PGA Line-Level Input Selected
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
98
95
92
89
104
101
98
95
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion +Noise (Note 11)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-80
-81
-41
-80
-75
-35
-74
-
-
-74
-
-
dB
dB
dB
dB
dB
dB
Dynamic Performance with PGA Mic-Level Input Selected
Dynamic Range
PGA Setting: -12 dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
77
74
65
62
83
80
71
68
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion +Noise (Note 11)
PGA Setting: -12 dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
-
-
-
-
-74
-60
-20
-68
-68
-
-
-
dB
dB
dB
dB
DS658F4 13
CS5345
PGAOUT ANALOG CHARACTERISTICS
(Continued)
VA = 3.13 V to 3.46 V
Parameter Symbol Min Typ Max Unit
Dynamic Performance with PGA Line-Level Input Selected
Dynamic Range
PGA Setting: -12 dB to +6 dB
A-weighted
unweighted
PGA Setting: +12 dB Gain
A-weighted
unweighted
93
90
89
86
101
98
95
92
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion +Noise (Note 11)
PGA Setting: -12 dB to +6 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB Gain
-1 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
-80
-78
-38
-80
-72
-32
-74
-
-
-74
-
-
dB
dB
dB
dB
dB
dB
Dynamic Performance with PGA Mic Level-Input Selected
Dynamic Range
PGA Setting: -12dB to 0 dB
A-weighted
unweighted
PGA Setting: +12 dB
A-weighted
unweighted
77
74
65
62
83
80
71
68
-
-
-
-
dB
dB
dB
dB
Total Harmonic Distortion +Noise (Note 11)
PGA Setting: -12dB to 0 dB
-1 dB
-20 dB
-60 dB
PGA Setting: +12 dB
-1 dB
THD+N
-
-
-
-
-74
-60
-20
-68
-68
-
-
-
dB
dB
dB
dB
14 DS658F4
CS5345
PGAOUT ANALOG CHARACTERISTICS
(Continued)
12. Guaranteed by design.
VA = 3.13 V to 5.25 V
Parameter Symbol Min Typ Max Unit
DC Accuracy with PGA Line Level Input Selected
Interchannel Gain Mismatch - 0.1 - dB
Gain Error - 5 - %
Gain Drift - 100 - ppm/C
DC Accuracy with PGA Mic Level Input Selected
Interchannel Gain Mismatch - 0.3 - dB
Gain Error - 5 - %
Gain Drift - 300 - ppm/C
Analog Output
Frequency Response 10 Hz to 20 kHz (Note 12) -0.1dB - +0.1dB dB
Analog In to Analog Out Phase Shift - 180 - deg
DC Current draw from a PGAOUT pin I
OUT
- - 1 A
AC-Load Resistance R
L
100 - - kO
Load Capacitance C
L
- - 20 pF
DS658F4 15
CS5345
DC ELECTRICAL CHARACTERISTICS
AGND =DGND =0 V, all voltages with respect to ground. MCLK=12.288 MHz; Fs=48 kHz; Master Mode.
13. Power-Down Mode is defines as RESET =Low with all clock and data lines held static and no analog
input.
14. Valid with the recommended capacitor values on FILT+and VQ as shown in the Typical Connection
Diagram.
15. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage
through the electrolytic de-coupling capacitors.
Parameter Symbol Min Typ Max Unit
Power Supply Current VA =5 V
(Normal Operation) VA =3.3 V
VD, VLS, VLC =5 V
VD, VLS, VLC =3.3 V
I
A
I
A
I
D
I
D
-
-
-
-
41
37
39
23
50
45
47
28
mA
mA
mA
mA
Power Supply Current VA =5 V
(Power-Down Mode) (Note 13) VLS, VLC, VD=5 V
I
A
I
D
-
-
0.50
0.54
-
-
mA
mA
Power Consumption
(Normal Operation) VA, VD, VLS, VLC =5 V
VA, VD, VLS, VLC =3.3 V
(Power-Down Mode) VA, VD, VLS, VLC =5 V
-
-
-
-
-
-
400
198
4.2
485
241
-
mW
mW
mW
Power Supply Rejection Ratio (1 kHz) (Note 14) PSRR - 55 - dB
VQ Characteristics
Quiescent Voltage VQ - 0.5 x VA - VDC
DC Current from VQ (Note 15) I
Q
- - 1 A
VQ Output Impedance Z
Q
- 23 - kO
FILT+Nominal Voltage FILT+ - VA - VDC
Microphone Bias Voltage MICBIAS - 0.8 x VA - VDC
Current from MICBIAS I
MB
- - 2 mA
16 DS658F4
CS5345
DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND =DGND =0 V; VLS =VLC =1.71 V to 5.25 V.
16. Serial Port signals include: MCLK, SCLK, LRCK, SDOUT.
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, RESET, INT, OVFL.
17. Guaranteed by design.
Parameters (Note 16) Symbol Min Typ Max Units
High-Level Input Voltage
VL =1.71 V Serial Port
Control Port
VL >2.0V Serial Port
Control Port
V
IH
V
IH
V
IH
V
IH
0.8xVLS
0.8xVLC
0.7xVLS
0.7xVLC
-
-
-
-
-
-
-
-
V
V
V
V
Low-Level Input Voltage Serial Port
Control Port
V
IL
V
IL
-
-
-
-
0.2xVLS
0.2xVLC
V
V
High-Level Output Voltage at I
o
=2 mA Serial Port
Control Port
V
OH
V
OH
VLS-1.0
VLC-1.0
-
-
-
-
V
V
Low-Level Output Voltage at I
o
=2 mA Serial Port
Control Port
V
OL
V
OL
-
-
-
-
0.4
0.4
V
V
Input Leakage Current I
in
- - 10 A
Input Capacitance (Note 17) - - 1 pF
Minimum OVFL Active Time - - s
10
6
LRCK
-----------------
DS658F4 17
CS5345
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
Logic 0 =DGND =AGND =0 V; Logic 1 =VL, C
L
=20 pF. (Note 18)
18. See Figure 1 and Figure 2 on page 18.
Parameter Symbol Min Typ Max Unit
Sample Rate Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
4
50
100
-
-
-
50
100
200
kHz
kHz
kHz
MCLK Specifications
MCLK Frequency fmclk 1.024 - 51.200 MHz
MCLK Input Pulse Width High/Low tclkhl 8 - - ns
Master Mode
LRCK Duty Cycle - 50 - %
SCLK Duty Cycle - 50 - %
SCLK falling to LRCK edge t
slr
-10 - 10 ns
SCLK falling to SDOUT valid t
sdo
0 - 36 ns
Slave Mode
LRCK Duty Cycle 40 50 60 %
SCLK Period
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
t
sclkw
t
sclkw
t
sclkw
-
-
-
-
-
-
ns
ns
ns
SCLK Pulse Width High t
sclkh
30 - - ns
SCLK Pulse Width Low t
sclkl
48 - - ns
SCLK falling to LRCK edge t
slr
-10 - 10 ns
SCLK falling to SDOUT valid t
sdo
0 - 36 ns
10
9
128 ( )Fs
---------------------
10
9
64 ( )Fs
------------------
10
9
64 ( )Fs
------------------
18 DS658F4
CS5345

slr
t
SDOUT
SCLK
Output
LRCK
Output
sdo
t
slr
t
SDOUT
SCLK
Input
LRCK
Input
sdo
t
sclkh
t
sclkl
t
sclkw
t
Figure 1. Master Mode Serial Audio Port Timing
Figure 2. Slave Mode Serial Audio Port Timing
DS658F4 19
CS5345

Figure 3. Format 0, Left-Justified up to 24-Bit Data
LRCK
SCLK


SDATA +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 MSB -1 -2 -3 -4
Channel A - Left Channel B - Right
LSB LSB MSB
Figure 4. Format 1, IS up to 24-Bit Data
LRCK
SCLK
SDATA +3 +2 +1 +5 +4 MSB -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4
Channel A - Left
Channel B - Right
LSB MSB LSB
20 DS658F4
CS5345
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
Inputs: Logic 0 =DGND =AGND =0 V, Logic 1 =VLC, C
L
=30 pF.
19. Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
20. Guaranteed by design.
Parameter Symbol Min Max Unit
SCL Clock Frequency f
scl
- 100 kHz
RESET Rising Edge to Start t
irs
500 - ns
Bus Free Time Between Transmissions t
buf
4.7 - s
Start Condition Hold Time (prior to first clock pulse) t
hdst
4.0 - s
Clock Low time t
low
4.7 - s
Clock High Time t
high
4.0 - s
Setup Time for Repeated Start Condition t
sust
4.7 - s
SDA Hold Time from SCL Falling (Note 19) t
hdd
0 - s
SDA Setup time to SCL Rising t
sud
250 - ns
Rise Time of SCL and SDA (Note 20) t
rc
, t
rd
- 1 s
Fall Time SCL and SDA (Note 20) t
fc
, t
fd
- 300 ns
Setup Time for Stop Condition t
susp
4.7 - s
Acknowledge Delay from SCL Falling t
ack
300 1000 ns
t
buf t
hdst
t
low
t
hdd
t
high
t
sud
Stop Start
SDA
SCL
t
irs
RST
t
hdst
t
rc
t
fc
t
sust
t
susp
Start
Stop
Repeated
t
rd
t
fd
t
ack
Figure 5. Control Port Timing - IC Format
DS658F4 21
CS5345
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 =DGND =AGND =0 V, Logic 1 =VLC, C
L
=30 pF.
21. Data must be held for sufficient time to bridge the transition time of CCLK.
22. For f
sck
<1 MHz.
Parameter Symbol Min Max Units
CCLK Clock Frequency f
sck
- 6.0 MHz
RESET Rising Edge to CS Falling t
srs
500 - ns
CS High Time Between Transmissions t
csh
1.0 - s
CS Falling to CCLK Edge t
css
20 - ns
CCLK Low Time t
scl
66 - ns
CCLK High Time t
sch
66 - ns
CDIN to CCLK Rising Setup Time t
dsu
40 - ns
CCLK Rising to DATA Hold Time (Note 21) t
dh
15 - ns
CCLK Falling to CDOUT Stable t
pd
- 50 ns
Rise Time of CDOUT t
r1
- 25 ns
Fall Time of CDOUT t
f1
- 25 ns
Rise Time of CCLK and CDIN (Note 22) t
r2
- 100 ns
Fall Time of CCLK and CDIN (Note 22) t
f2
- 100 ns
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css
t
pd
CDOUT
t
csh
RST t
srs
Figure 6. Control Port Timing - SPI Format
22 DS658F4
CS5345
3. TYPICAL CONNECTION DIAGRAM
VLS
0.1 F
+1.8V
to +5V
DGND
VLC
0.1 F
+1.8V
to +5V
SCL/CCLK
SDA/CDOUT
AD1/CDIN
RESET
2 kO
See Note 1
AGND
AD0/CS
Note 1: Resistors are required
for IC control port operation
Micro-
Controller
0.1 F
VA
* Capacitors must be C0G or equivalent
Digital Audio
Capture LRCK
SDOUT
MCLK
SCLK
PGAOUTA
PGAOUTB
2.2nF
AFILTA
AFILTB
OVFL
2.2nF
3.3 F
3.3 F
47 F
0.1 F
VQ
FILT+
10 F
AGND
* *
2 kO
INT
47 F


AIN1A Left Analog Input 1
10 F
10 F
1800 pF
1800 pF
100 kO
100 kO
100 O
100 O
AIN1B Right Analog Input 1

AIN2A Left Analog Input 2
10 F
10 F
1800 pF
1800 pF
100 kO
100 kO
100 O
100 O
AIN2B Right Analog Input 2

AIN3A Left Analog Input 3
10 F
10 F
1800 pF
1800 pF
100 kO
100 kO
100 O
100 O
AIN3B Right Analog Input 3

AIN4A/MICIN1 Left Analog Input 4
10 F
10 F
1800 pF
1800 pF
100 kO
100 kO
100 O
100 O
AIN4B/MICIN2 Right Analog Input 4

AIN5A Left Analog Input 5
10 F
10 F
1800 pF
1800 pF
100 kO
100 kO
100 O
100 O
AIN5B Right Analog Input 5

AIN6A Left Analog Input 6
10 F
10 F
1800 pF
1800 pF
100 kO
100 kO
100 O
100 O
AIN6B Right Analog Input 6
MICBIAS
AGND
0.1 F
*
*
*
*
*
*
*
*
*
*
*
*
NC
NC
NC
NC
NC
TSTI
TSTO
TSTO
TSTO
10 F
+3.3V to +5V
0.1 F 10 F 0.1 F
VA VD
+3.3V to +5V
RL
See Note 2
Note 2 The value of RL is
dictated by the microphone
carteridge.
CS5345
Figure 7. Typical Connection Diagram
DS658F4 23
CS5345
4. APPLICATIONS
4.1 Recommended Power-Up Sequence
1. Hold RESET low until the power supply, MCLK, and LRCK are stable. In this state, the Control Port is
reset to its default settings.
2. Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The con-
trol port will be accessible.
3. The desired register settings can be loaded while the PDN bit remains set.
4. Clear the PDN bit to initiate the power-up sequence.
4.2 System Clocking
The CS5345 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three
speed modes as shown in Table 1.
4.2.1 Master Clock
MCLK/LRCK must maintain an integer ratio as shown in Table 2. The LRCK frequency is equal to Fs, the
frequency at which audio samples for each channel are clocked out of the device. The FM bits (See Func-
tional Mode (Bits 7:6) on page 33.) and the MCLK Freq bits (See MCLK Frequency - Address 05h on
page 34.) configure the device to generate the proper clocks in Master Mode, and receive the proper
clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and
LRCK frequencies.
Mode Sampling Frequency
Single-Speed 4-50 kHz
Double-Speed 50-100 kHz
Quad-Speed 100-200 kHz
Table 1. Speed Modes
LRCK
(kHz)
MCLK (MHz)
64x 96x 128x 192x 256x 384x 512x 768x 1024x
32 - - - - 8.1920 12.2880 16.3840 24.5760 32.7680
44.1 - - - - 11.2896 16.9344 22.5792 33.8680 45.1584
48 - - - - 12.2880 18.4320 24.5760 36.8640 49.1520
64 - - 8.1920 12.2880 16.3840 24.5760 32.7680 - -
88.2 - - 11.2896 16.9344 22.5792 33.8680 45.1584 - -
96 - - 12.2880 18.4320 24.5760 36.8640 49.1520 - -
128 8.1920 12.2880 16.3840 24.5760 32.7680 - - - -
176.4 11.2896 16.9344 22.5792 33.8680 45.1584 - - - -
192 12.2880 18.4320 24.5760 36.8640 49.1520 - - - -
Mode QSM
DSM SSM
Table 2. Common Clock Frequencies
24 DS658F4
CS5345
In both Master and Slave Modes, the external MCLK must be divided down based on the MCLK/LRCK
ratio to achieve a post-divider MCLK/LRCK ratio of 256x for SSM, 128x for DSM, or 64x for QSM. Table 3
lists the appropriate dividers.
4.2.2 Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8.
4.2.3 Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x, 48x or 32x Fs, depending on the desired speed mode. Refer to Table 4 for required clock ra-
tios.
4.3 High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS5345, a small DC offset may be driven
into the A/D converter. The CS5345 includes a high-pass filter after the decimator to remove any DC offset
MCLK/LRCK Ratio MCLK Dividers
64x - - 1
96x - - 1.5
128x - 1 2
192x - 1.5 3
256x 1 2 4
384x 1.5 3 -
512x 2 4 -
768x 3 - -
1024x 4 - -
Mode SSM
DSM QSM
Table 3. MCLK Dividers
Single-Speed Double-Speed Quad-Speed
SCLK/LRCK Ratio 32x, 48x, 64x, 128x 32x, 48x, 64x 32x, 48x, 64x
Table 4. Slave Mode Serial Bit Clock Ratios
256
128
64
4
2
1
00
01
10
00
01
10
LRCK
SCLK
000
001
010
1
1.5
2
011
100
3
4
MCLK
FM Bits
MCLK Freq Bits
Figure 8. Master Mode Clocking
DS658F4 25
CS5345
which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-
tichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit (See High-Pass Filter Freeze (Bit 1) on page 33.) is set during normal operation,
the current value of the DC offset for the each channel is frozen and this DC offset will continue to be sub-
tracted from the conversion result. This feature makes it possible to perform a system DC offset calibration
by:
1. Running the CS5345 with the high-pass filter enabled until the filter settles. See the Digital Filter Char-
acteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5345.
26 DS658F4
CS5345
4.4 Analog Input Multiplexer, PGA, and Mic Gain
The CS5345 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier
(PGA). The input multiplexer can select one of six possible stereo analog input sources and route it to the
PGA. Analog inputs 4A and 4B are able to insert a +32 dB gain stage before the input multiplexer, allowing
them to be used for microphone-level signals without the need for any external gain. The PGA stage pro-
vides 12 dB of gain or attenuation in 0.5 dB steps. Figure 9 shows the architecture of the input multiplexer,
PGA, and microphone gain stages. .
The Analog Input Selection (Bits 2:0) on page 36 outlines the bit settings necessary to control the input
multiplexer and mic gain. Channel B PGA Control - Address 07h on page 34 and Channel A PGA Control
- Address 08h on page 35 outline the register settings necessary to control the PGA. By default, line-
level input 1 is selected, and the PGA is set to 0 dB.
4.5 Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject sig-
nals within the stopband of the filter. However, there is no rejection for input signals which are
(n 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram
for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capac-
itors which have a large voltage coefficient (such as general-purpose ceramics) must be avoided since
these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
4.6 PGA Auxiliary Analog Output
The CS5345 includes an auxiliary analog output through the PGAOUT pins. These pins can be configured
to output the analog input to the ADC as selected by the input MUX and gained or attenuated with the PGA,
or alternatively, they may be set to high-impedance. See the PGAOut Source Select (Bit 6) on page 34
for information on configuring the PGA auxiliary analog output.
The PGA auxiliary analog output can source very little current. As current from the PGAOUT pins increases,
distortion will increase. For this reason, a high-input impedance buffer must be used on the PGAOUT pins
to achieve full performance. Refer to the table in PGAOUT Analog Characteristics on page 12 for accept-
able loading conditions.
PGA MUX
+32dB
AIN1A
AIN2A
AIN3A
AIN4A/MICIN1
AIN5A
AIN6A
PGA MUX
+32dB
AIN1B
AIN2B
AIN3B
AIN4B/MICIN2
AIN5B
AIN6B
Analog Input
Selection Bits
Channel A
PGA Gain Bits
Channel B
PGA Gain Bits
Out to ADC
Channel A
Out to ADC
Channel B
Figure 9. Analog Input Architecture
DS658F4 27
CS5345
4.7 Control Port Description and Timing
The control port is used to access the registers, allowing the CS5345 to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample rates. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port has two modes: SPI and IC, with the CS5345 acting as a slave device. SPI Mode is se-
lected if there is a high-to-low transition on the AD0/CS pin, after the RESET pin has been brought high. IC
Mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
4.7.1 SPI Mode
In SPI Mode, CS is the CS5345 chip-select signal; CCLK is the control port bit clock (input into the CS5345
from the microcontroller); CDIN is the input data line from the microcontroller; CDOUT is the output data
line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 10 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indi-
cator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data that will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 kO resistor, if desired.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip ad-
dress and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the
addressed register (CDOUT will leave the high-impedance state).
For both read and write cycles, the memory address pointer will automatically increment following each
data byte in order to facilitate block reads and writes of successive registers.
4.7.2 IC Mode
In IC Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should
MAP
MSB LSB
DATA
byte 1 byte n
R/W R/W
ADDR E S S
C HIP
ADDRESS
C HIP
C DIN
C C L K
CS
C DOUT
MSB LSB MSB LSB
1001111 1001111
MAP =MemoryAddress Pointer, 8bits, MSB first
HighImpedance
Figure 10. Control Port Timing in SPI Mode
28 DS658F4
CS5345
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the
CS5345 is being reset.
The signal timings for a read and write cycle are shown in Figure 11 and Figure 12. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS5345
after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write).
The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS5345, the chip
address field, which is the first byte sent to the CS5345, should match 10011 followed by the settings of
the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is
the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a
read, the contents of the register pointed to by the MAP will be output. Following each data byte, the mem-
ory address pointer will automatically increment to facilitate block reads and writes of successive regis-
ters. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS5345 after each
input byte is read, and is input to the CS5345 from the microcontroller after each transmitted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 12, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1 (chip address & read operation).
Receive acknowledge bit.
4 5 6 7 24 25
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START
ACK
STOP
ACK ACK ACK
1 0 0 1 1 AD1 AD0 0
SDA
6 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0
0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26
DATA +n
Figure 11. Control Port Timing, IC Write
SCL
CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1
START
ACK
STOP
ACK
ACK ACK
1 0 0 1 1 AD1 AD0 0 SDA 1 0 0 1 1 AD1 AD0 1
CHIP ADDRESS (READ)
START
7 6 5 4 3 2 1 0 7 0 7 0 7 0
NO
16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25
ACK
DATA +n
STOP
Figure 12. Control Port Timing, IC Read
DS658F4 29
CS5345
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
4.8 Interrupts and Overflow
The CS5345 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an
active low open-drain driver (see Active High/Low (Bit 0) on page 36). When configured as active low
open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-ups with
multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an external
pull-up resistor must be placed on the INT pin for proper operation.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see Interrupt
Status - Address 0Dh on page 36). Each source may be masked off through mask register bits. In addition,
each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option of level-
sensitive or edge-sensitive modes within the microcontroller, many different configurations are possible, de-
pending on the needs of the equipment designer.
The CS5345 also has a dedicated overflow output. The OVFL pin functions as active low open drain and
has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR
of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register; however, these
conditions do not need to be unmasked for proper operation of the OVFL pin.
4.9 Reset
When RESET is low, the CS5345 enters a low-power mode and all internal states are reset, including the
control port and registers, the outputs are muted. When RESET is high, the control port becomes operation-
al, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Pow-
er Control register will then cause the part to leave the low-power state and begin operation.
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RESET pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+pin. During this
voltage reference ramp delay, SDOUT will be automatically muted.
It is recommended that RESET be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power-glitch-related issues.
4.10 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the master clocks and left/right clocks must be the same for all of the
CS5345s in the system. If only one master clock source is needed, one solution is to place one CS5345 in
Master Mode, and slave all of the other CS5345s to the one master. If multiple master clock sources are
needed, a possible solution would be to supply all clocks from the same external source and time the
CS5345 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on
the same clock edge.
4.11 Grounding and Power Supply Decoupling
As with any high-resolution converter, the CS5345 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 7 shows the recommended power ar-
rangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the
30 DS658F4
CS5345
system logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In this
case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as
near to the CS5345 as possible, with the low value ceramic capacitor being the nearest. All signals, espe-
cially clocks, should be kept away from the FILT+and VQ pins in order to avoid unwanted coupling into the
modulators. The FILT+and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to mini-
mize the electrical path from FILT+and AGND. The CS5345 evaluation board demonstrates the optimum
layout and power supply arrangements. To minimize digital noise, connect the CS5345 digital outputs only
to CMOS inputs.
DS658F4 31
CS5345
5. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values.
Addr Function 7 6 5 4 3 2 1 0
01h Chip ID PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0
1 1 1 0 0 0 0 1
02h Power Control Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC Reserved PDN
0 0 0 0 0 0 0 1
03h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 0 0 0 1 0 0 0
04h ADC Control FM1 FM0 Reserved DIF Reserved Mute HPFFreeze M/S
0 0 0 0 0 0 0 0
05h MCLK
Frequency
Reserved MCLK
Freq2
MCLK
Freq1
MCLK
Freq0
Reserved Reserved Reserved Reserved
0 0 0 0 0 0 0 0
06h PGAOut
Control
Reserved PGAOut Reserved Reserved Reserved Reserved Reserved Reserved
0 1 0 0 0 0 0 0
07h PGA Ch B
Gain Control
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
0 0 0 0 0 0 0 0
08h PGA Ch A
Gain Control
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
0 0 0 0 0 0 0 0
09h Analog Input
Control
Reserved Reserved Reserved PGASoft PGAZero Sel2 Sel1 Sel0
0 0 0 1 1 0 0 1
0Ah -
0Bh
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 0 0 0 0 0 0 0
0Ch Active Level
Control
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Active_H/L
1 1 0 0 0 0 0 0
0Dh Interrupt Status Reserved Reserved Reserved Reserved ClkErr Reserved Ovfl Undrfl
0 0 0 0 0 0 0 0
0Eh Interrupt Mask Reserved Reserved Reserved Reserved ClkErrM Reserved OvflM UndrflM
0 0 0 0 0 0 0 0
0Fh Interrupt Mode
MSB
Reserved Reserved Reserved Reserved ClkErr1 Reserved Ovfl1 Undrfl1
0 0 0 0 0 0 0 0
10h Interrupt Mode
LSB
Reserved Reserved Reserved Reserved ClkErr0 Reserved Ovfl0 Undrfl0
0 0 0 0 0 0 0 0
32 DS658F4
CS5345
6. REGISTER DESCRIPTION
6.1 Chip ID - Register 01h
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID, which is 1110b (0Eh), and the remaining
bits (3 through 0) indicate the device revision as shown in Table 5 below.
6.2 Power Control - Address 02h
6.2.1 Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect
until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the
Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed
in Table 6.
6.2.2 Power-Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
6.2.3 Power-Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
6.2.4 Power-Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and
must be cleared before normal operation can occur. The contents of the control registers are retained
when the device is in power-down.
7 6 5 4 3 2 1 0
PART3 PART2 PART1 PART0 REV3 REV2 REV1 REV0
REV[2:0] Revision
001 A
010 B, C0
011 C1
Table 5. Device Revision
7 6 5 4 3 2 1 0
Freeze Reserved Reserved Reserved PDN_MIC PDN_ADC Reserved PDN
Name Register Bit(s)
Mute 04h 2
Gain[5:0] 07h 5:0
Gain[5:0] 08h 5:0
Table 6. Freeze-able Bits
DS658F4 33
CS5345
6.3 ADC Control - Address 04h
6.3.1 Functional Mode (Bits 7:6)
Function:
Selects the required range of sample rates.
6.3.2 Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface Format
bit. The options are detailed in Table 8 and may be seen in Figure 3 and Figure 4.
6.3.3 Mute (Bit 2)
Function:
When this bit is set, the serial audio output of the both channels is muted.
6.3.4 High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled. The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See High-Pass Filter and DC Offset Calibration on
page 24.
6.3.5 Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
7 6 5 4 3 2 1 0
FM1 FM0 Reserved DIF Reserved Mute HPFFreeze M/S
FM1 FM0 Mode
0 0 Single-Speed Mode: 4 to 50 kHz sample rates
0 1 Double-Speed Mode: 50 to 100 kHz sample rates
1 0 Quad-Speed Mode: 100 to 200 kHz sample rates
1 1 Reserved
Table 7. Functional Mode Selection
DIF Description Format Figure
0 Left-J ustified, up to 24-bit data (default) 0 3
1 IS, up to 24-bit data 1 4
Table 8. Digital Interface Formats
34 DS658F4
CS5345
6.4 MCLK Frequency - Address 05h
6.4.1 Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See Table 9 for the appropriate settings.
6.5 PGAOut Control - Address 06h
6.5.1 PGAOut Source Select (Bit 6)
Function:
This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to
Table 10.
6.6 Channel B PGA Control - Address 07h
6.6.1 Channel B PGA Gain (Bits 5:0)
Function:
See Channel A PGA Gain (Bits 5:0) on page 35.
7 6 5 4 3 2 1 0
Reserved
MCLK
Freq2
MCLK
Freq1
MCLK
Freq0
Reserved Reserved Reserved Reserved
MCLK Divider MCLK Freq2 MCLK Freq1 MCLK Freq0
1 0 0 0
1.5 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
Reserved 1 0 1
Reserved 1 1 x
Table 9. MCLK Frequency
7 6 5 4 3 2 1 0
Reserved PGAOut Reserved Reserved Reserved Reserved Reserved Reserved
PGAOut PGAOutA & PGAOutB
0 High Impedance
1 PGA Output
Table 10. PGAOut Source Selection
7 6 5 4 3 2 1 0
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
DS658F4 35
CS5345
6.7 Channel A PGA Control - Address 08h
6.7.1 Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in twos complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the 12 dB range are reserved and must not be used. See Table 11 for ex-
ample settings.
6.8 ADC Input Control - Address 09h
6.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
See Table 12.
Zero Cross Enable
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel. See Table 12.
Soft Ramp and Zero Cross Enable
Soft Ramp and Zero Cross Enable dictate that signal-level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sam-
ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See Table 12.
7 6 5 4 3 2 1 0
Reserved Reserved Gain5 Gain4 Gain3 Gain2 Gain1 Gain0
Gain[5:0] Setting
101000 -12 dB
000000 0 dB
011000 +12 dB
Table 11. Example Gain and Attenuation Settings
7 6 5 4 3 2 1 0
Reserved Reserved Reserved PGASoft PGAZero Sel2 Sel1 Sel0
36 DS658F4
CS5345
6.8.2 Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 13.
6.9 Active Level Control - Address 0Ch
6.9.1 Active High/Low (Bit 0)
Function:
When this bit is set, the INT pin functions as an active high CMOS driver.
When this bit is cleared, the INT pin functions as an active low open drain driver and will require an exter-
nal pull-up resistor for proper operation.
6.10 Interrupt Status - Address 0Dh
For all bits in this register, a 1 means the associated interrupt condition has occurred at least once since
the register was last read. A 0 means the associated interrupt condition has NOT occurred since the last
reading of the register. Status bits that are masked off in the associated mask register will always be 0 in
this register. This register defaults to 00h.
PGASoft PGAZeroCross Mode
0 0 Changes to affect immediately
0 1 Zero Cross enabled
1 0 Soft Ramp enabled
1 1 Soft Ramp and Zero Cross enabled (default)
Table 12. PGA Soft Cross or Zero Cross Mode Selection
Sel2 Sel1 Sel0 PGA/ADC Input
0 0 0 Microphone-Level Inputs (+32 dB Gain Enabled)
0 0 1 Line-Level Input Pair 1
0 1 0 Line-Level Input Pair 2
0 1 1 Line-Level Input Pair 3
1 0 0 Line-Level Input Pair 4
1 0 1 Line-Level Input Pair 5
1 1 0 Line-Level Input Pair 6
1 1 1 Reserved
Table 13. Analog Input Multiplexer Selection
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Active_H/L
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved ClkErr Reserved Ovfl Undrfl
DS658F4 37
CS5345
6.10.1 Clock Error (Bit 3)
Function:
Indicates the occurrence of a clock error condition.
6.10.2 Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.10.3 Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
6.11 Interrupt Mask - Address 0Eh
Function:
The bits of this register serve as a mask for the Status sources found in the register Interrupt Status - Ad-
dress 0Dh on page 36. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect
the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence
will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Sta-
tus register.
6.12 Interrupt Mode MSB - Address 0Fh
6.13 Interrupt Mode LSB - Address 10h
Function:
The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are
three ways to set the INT pin active in accordance with the interrupt condition. In the Rising-Edge Active
Mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling-Edge Active Mode,
the INT pin becomes active on the removal of the interrupt condition. In Level-Active Mode, the INT pin re-
mains active during the interrupt condition.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved ClkErrM Reserved OvflM UndrflM
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved ClkErr1 Reserved Ovfl1 Undrfl1
Reserved Reserved Reserved Reserved ClkErr0 Reserved Ovfl0 Undrfl0
38 DS658F4
CS5345
7. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full scale. This
technique ensures that the distortion components are below the noise level and do not affect the measure-
ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of J apan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-
bels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
DS658F4 39
CS5345
8. FILTER PLOTS
Figure 13. Single-Speed Stopband Rejection Figure 14. Single-Speed Stopband Rejection
Figure 15. Single-Speed Transition Band (Detail) Figure 16. Single-Speed Passband Ripple
Figure 17. Double-Speed Stopband Rejection Figure 18. Double-Speed Stopband Rejection
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
40 DS658F4
CS5345

Figure 19. Double-Speed Transition Band (Detail) Figure 20. Double-Speed Passband Ripple
Figure 21. Quad-Speed Stopband Rejection Figure 22. Quad-Speed Stopband Rejection
Figure 23. Quad-Speed Transition Band (Detail) Figure 24. Quad-Speed Passband Ripple
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.46 0.47 0.48 0.49 0.50 0.51 0.52
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Fr equency (nor malized t o Fs)
A
m
p
l
i
t
u
d
e

(
d
B
)
DS658F4 41
CS5345
9. PACKAGE DIMENSIONS
10.THERMAL CHARACTERISTICS AND SPECIFICATIONS
1. u
J A
is specified according to J EDEC specifications for multi-layer PCBs.
INCHES MILLIMETERS
DIM MIN NOM MAX MIN NOM MAX
A --- 0.055 0.063 --- 1.40 1.60
A1 0.002 0.004 0.006 0.05 0.10 0.15
B 0.007 0.009 0.011 0.17 0.22 0.27
D 0.343 0.354 0.366 8.70 9.0 BSC 9.30
D1 0.272 0.28 0.280 6.90 7.0 BSC 7.10
E 0.343 0.354 0.366 8.70 9.0 BSC 9.30
E1 0.272 0.28 0.280 6.90 7.0 BSC 7.10
e* 0.016 0.020 0.024 0.40 0.50 BSC 0.60
L 0.018 0.24 0.030 0.45 0.60 0.75

0.000 4 7.000 0.00 4 7.00

* Nominal pin pitch is 0.50 mm *Controlling dimension is mm. *J EDEC Designation: MS022
Parameters Symbol Min Typ Max Units
Package Thermal Resistance (Note 1) 48-LQFP
u
J A
u
J C
-
-
48
15
-
-
C/Watt
C/Watt
Allowable J unction Temperature - - 125 C
48L LQFP PACKAGE DRAWING
E1
E
D1 D
1
e
L

B
A1
A
42 DS658F4
CS5345
11.ORDERING INFORMATION
12.REVISION HISTORY
Product Description Package Pb-Free Grade Temp Range Container Order #
CS5345
24-bit, 192 kHz
Stereo Audio ADC
48-LQFP Yes Commercial -10 to +70 C
Tray CS5345-CQZ
Tape & Reel CS5345-CQZR
CDB5345 CS5345 Evaluation Board No - - - CDB5345
Release Changes
F1
Removed the MAP auto-increment functional description from the Control Port Description and Timing section
beginning on page 27.
Added device revision information to the Chip ID - Register 01h description on page 32.
F2
Added Automotive Grade
Changed MCLK to input only in the Pin Descriptions table on page 5.
Updated the ADC Analog Characteristics table on page 8.
Updated the PGAOUT Analog Characteristics table on page 12.
Updated the DC Electrical Characteristics table on page 15.
Updated the Digital Interface Characteristics table on page 16.
Updated the Switching Characteristics - Serial Audio Port table on page 17.
Updated the Switching Characteristics - Control Port - SPI Format table on page 21.
Updated the Typical Connection Diagram on page 22.
Switched Channel B PGA Control - Address 07h on page 34 and Channel A PGA Control - Address 08h on
page 35.
F3
Removed Automotive Grade
F4
Added Table 3.
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest you, go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (Cirrus) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided AS ISwithout warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
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copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJ URY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-
VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMERS RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMERS CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA-
TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
IC is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.