INSTITUTE OF AERONAUTICAL ENGINEERING

(Autonomous)
Dundigal, Hyderabad - 500043, Telangana.

ELECTRONICS AND COMMUNICATION ENGINEERING

CONTINUOUS INTERNAL ASSESSMENT (CIA)

MULTIPLE CHOICE QUESTIONS FOR QUIZ

Regulations : IARE-R16

Academic Year : 2017-2018

Semester : IV

Course Name : PULSE AND DIGITAL CIRCUITS

Course Code : AEC006

Branch : ECE

Course Coordinator : P Saritha, Associate Professor, Department Of ECE

Team of Instructors : J.Sravana, N.Anusha, P. Saritha, B.Naresh

 UNIT-I
LINEAR WAVE SHAPING CIRCUITS
SYLLABUS:
Linear wave shaping circuits: High pass RC and low pass RC circuits, response to impulse and pulse
inputs with different time constants, high pass RC circuit as a differentiator, low pass RC circuit as an
integrator, switching characteristics of diode; Non-linear wave shaping circuits: Clipping circuits,
diode clippers, shunt clippers, series clippers, clipping at two independent levels; Clamping circuits:
Clamping theorem.
S.No. Question Answer
The response of a high pass RC circuit to a step input of amplitude V is
A. V(1-e-t/RC )
1. B. Ve-t/RC B
C. V
D. Vet/RC
2. The response of a differentiator circuit to a pulse input is
A. Ramp
B. Spikes B
C. Square
D. Sine
3. A High pass RC circuit acts like a differentiator for the condition
( RC = Time constant of the circuit & T= Time period of the input signal
A. RC = T
C
B. RC>>T
C. RC<<T
D. RC=2T
4. The response of a low-pass RC circuit to a step input is
A. Ramp
B. square wave C
C. exponential rise
D. exponential decay
5. A low pass RC circuit acts like an integrator for the condition
( RC = Time constant of the circuit & T= Time period of the input signal )
A. RC = T
C
B. RC << T
C. RC >>T
D. RC=5T
6. The response of an integrator circuit to a square wave input is
A. sine wave
B. triangular wave B
C. pulse
D. ramp
7. The condition for perfect compensation in an attenuator is
A. R1 = R2
B. C1=R2C2/ R1 B
C. C1= C2
D. R1=C1
8. The circuit which passes low frequencies readily , but attenuates high frequency is
called
A. High pass RC circuit
B
B. Low pass RC circuit
C. Attenuator
D. Comparator
9. In a high Pass RC circuit, the output (Vo) is taken across
A. Resistor
B. capacitor A
C. inductor
D. diode
10. The condition for a RLC circuit to ring for many cycles is ( k is damping constant)
 UNIT-II
MULTIVIBRATORS
SYLLABUS:
Multivibrators: Introduction, classification; Bistable multivibrator: Fixed bias, self bias, unsymmetrical
triggering, symmetrical triggering; Schmitt trigger: Upper trigger point, lower trigger point, hysteresis,
applications of schmitt trigger; Monostable multivibrator: Collector coupled, triggering of monostable
multivibrator; Astable multivibrator: Collector coupled, voltage to frequency converter.
S.No. Question Answer
1. In a design of fixed bias binary VCC =VBB =12v ,hfe(min)=20, ic sat=4 ImA,assume n-p-
n(Si) transistor then Rc is =
A. 2.925 kΏ
A
B. 200Ω
C. 0.5 kΩ
D. 100Ω
2. The duration of quasi stable state of a mono shot is-----
A. Fall gate
B. Gate time B
C. Storage time
D. Recovery time
3. The capacitor which assists the binary in making abrupt transition between states are
called
A. Delay
C
B. Storage
C. Commutating
D. Translation
4. Monostable multi vibrators generates
A. Pulse wave form
B. Ramp signal B
C. Sine wave
D. Square wave
5. Are basically regenerative circuits comprising of two cross coupled
active devices [b
] a)filters
A. Filters B
B. Multivibrators
C. Attenuators
D. Clampers
6. Which one of the following circuits converts any arbitrary waveform into a square
wave
A. Monostable Multivibrator
D
B. Bistable Multivibrator
C. Astable Multivibrator
D. Schmitt Trigger
7. The Schmitt Trigger is also called as
A. Emitter coupled binary
B. Collector coupled binary A
C. Self biased
D. Dc restorer
8. The Astable Multivibrator has one of the following applications A
A. Voltage to frequency converter
 B. Gating circuit
C. Comparator
D. Voltage to voltage converter
9. The Monostable Multivibrator has one of the following applications
A. Schmitt trigger
B. Gating circuit B
C. Square wave generator
D. Sine wave generator
10 Basically how many types of multivibrators are there
A. 3
B. 4 A
C. 6
D. 5
11 The time period of the quasi stable state in a Monostable Multivibrator is given by
A. T=0.69RC
B. T=0.63RC A
C. T=1.38RC
D. T=RC
12 The pulse width or gate width of mono shot is
A. RC
B . 2 RC C
C . 0.69 RC
D. 1.38RC
13 If VTP=5.12 and LTP =3.312 then the value of hysterisis in Schmitt trigger is
A. 1.81 V
B. 5.4 V A
C. 4.8 V
D. 3.2V
14 The commutating capacitor are also called
A. speed up capacitor
B. varicap A
C. tuning capacitor
D. delay capacitor
15 Stable state of binary is one in which the current and voltages satisfy kirchoffs laws
and are constant and the condition satisfied that loop gain is
A. =1
B
B. <1
C. >>1
D. >1
16 The Schmitt trigger can be used as a
A. filter
B. attenuator C
C. comparator
D. clamper
17 A ckt which can indefinitely exist in either of two stable state and which can be C
induced to make abrupt transition from one state to other by means of external
excitation
A. monoshot
B. oscillator
 C. binary
D. attenuator

18 Which of the following is the advantage of emitter coupled over collector coupled
multivibrator
A. inherently self starting
C
B. low power dissipation
C. less noisy
D. only one trigger signal is enough
19 No of triggers required for monostable multi to change from stable state to quasi
stable state and vice versa
A. 1
A
B. 2
C. 3
D. 4
20 Monostable multi vibrators generates
A. Square
B. Pulse B
C. Sine
D. Ramp
21 Find the value of collector resistor in a collector coupled stable multi for the
following specifications f=10 KHZ ,Vcc=9 V, ic(max) =2 mA,hfe=20
A. 1Ω
B
B. 4.35 KΩ
C. 3 KΩ
D. 2KΩ
22 The binary is sometimes referred to as
A. Norton’s ckt
B. Eccless Jordon ckt B
C. Thevinins ckt
D. Millimans ckt
23 How to overcome mistriggering on the positive pulse edges in the monostable
circuit?
A. Connect a RC network at the input
C
B. Connect an integrator at the input
C. Connect a differentiator at the input
D. Connect a diode at the input
24 A monostable multivibrator has R = 120kΩ and the time delay T = 1000ms, calculate
the value of C?
A. 0.9µF
C
B. 1.32µF
C. 7.5µF
D. 2.49µF
25 Which among the following can be used to detect the missing heart beat?
A. Monostable multivibrator
B. Astable multivibrator A
C. Schmitt trigger
D. Bistable multivibrator
26 How can a monostable multivibrator be modified into a linear ramp generator? C
 A. Connect a constant current source to trigger input
B. Connect a constant current source to trigger output
C. Replace resistor by constant current source
D. Replace capacitor by constant current source
27 A stable multivibrator operating at 150Hz has a discharge time of 2.5m. Find the
duty cycle of the circuit.
A. 50%
D
B. 75%
C. 95.99%
D. 37.5%
28 How to achieve 50% duty cycle in adjustable rectangular wave generator? (Assume
R1 –> Resistor connected between supply and discharge and R2 –> Resistor
connected between discharge and trigger input.)
A. R1 < R2 C
B. R1 > R2
C. R1 = R2
D. R1 ≥ R2
29 How to obtain symmetrical waveform in Astable multivibrator?
A. Use clocked RS flip-flop
B. Use clocked JK flip-flop B
C. Use clocked D-flip-flop
D. Use clocked T-flip-flop
30 How does a monostable multivibrator used as frequency divider?
A. Using square wave generator
B. Using triangular wave generator A
C. Using sawtooth wave generator
D. Using sine wave generator
31 Which circuit converts irregularly shaped waveform to regular shaped waveforms?
A. Schmitt trigger
B. Voltage limiter A
C. Comparator
D. voltage doubler
32 What happens if the threshold voltages are made longer than the noise voltages in
schmitt trigger?
A. increase the gain
D
B. Enhance the output signal
C. Reduce the transition effect
D. Eliminate false output transition
33 To a Schmitt trigger in non-inverting configuration an input triangular wave of 1V p is
applied. What will be the output waveform, if the upper and lower threshold voltages
are 0.25v?
A. Square waveform A
B. Pulse waveform
C. Saw tooth waveform
D. Cannot be determined
34 In which configuration a dead band condition occurs in Schmitt trigger.
A. Differential amplifier with positive feedback
B. Voltage follower with positive feedback C
C. Comparator with positive feedback
D. Voltage follower with negative feedback
35 How to limit the output voltage swing only to positive direction.
A. Combination of two zener diodes
B. Combination of zener and rectifier diode B
C. with transistors
D. Combination of two rectifier diodes
36 A Schmitt trigger is
A. Comparator with only one trigger point.
B. Comparator with hysteresis. B
C. Comparator with three trigger points.
D. Comparator with two triggering points
37 The output of a Schmitt trigger is a
A. Pulse waveform.
B. Sawtooth waveform. A
C. Sinusoidal waveform.
D. Triangle waveform
38 A comparator with a Schmitt trigger has
A. Two trigger levels.
B. A fast response. A
C. A slow response.
D. One trigger level.
39 In ________, when the input voltage exceeds a specified reference voltage, the
output changes state.
A. Integrator
D
B. Differentiator
C. summing amplifier
D. Comparator
40 A good example of hysteresis is
A. AM radio.
B. Thermostat. B
C. Alarm clock.
D. Rheostat
41 To reduce the effects of noise resulting in erratic switching of output states of a
comparator, you can use
A. The upper trigger point.
D
B. The lower trigger point.
C. Nonzero-level detection.
D. Hysteresis.
42 What is are the necessary components for the design of a bounded comparator?
A. SCR diodes
B. Zener diodes B
C. PN diode
D. Schottky diode
43 What type of circuit is used as comparators?
A. Summer
B. Nonzero-level detector B
C. Averaging amplifier
D. Summer and nonzero-level detector
44 A differentiator is used to measure D
A. The sum of the input voltages.
B. The difference between two voltages.
 C. The area under a curve.
D. The rate of change of the input voltage.
45 ________ is a mathematical process for determining the rate of change of a function.
A. Integration
B. Differentiation B
C. Summing
D. Comparator
46 An integrator circuit
A. Uses a resistor in its feedback circuit.
B. Uses an inductor in its feedback circuit. C
C. Uses a capacitor in its feedback circuit.
D. Uses a resistor in its feedback circuit or uses a capacitor in its feedback circuit.
47 In a comparator with output bounding, what type of diode is used in the feedback
loop?
A. Schottky
C
B. Junction
C. Zener
D. Varactor
48 A comparator with hysteresis is sometimes known as
A. Integrator.
B. Differentiator. C
C. Schmitt trigger.
D. Multivibrator.
49 Depending on the value of input and reference voltage a comparator can be named as

A. Voltage follower
D
B. Digital to analog converter
C. Schmitt trigger
D. Voltage level detector
50 Why clamp diodes are used in comparator?
A. To reduce output offset voltage
B. To increase gain of op-amp D
C. To reduce input offset current
D. To protect op-amp from damage

UNIT-III
SAMPLING GATES AND TIME BASE GENERATORS
SYLLABUS:
Sampling gates: basic operating principle of sampling gate, uni and bi directional sampling gates. Time
base generators: General features of a time base signal; Methods of generating a time base waveform:
Exponential sweep circuits, sweep circuit using uni junction transistor, Miller sweep circuit and Bootstrap
sweep circuit
S.No. Question Answer
1. Bootstrap’s sweep circuit produces _____ type of waveform.
A. Positive going Ramp
B. Negative going Ramp A
C. Square
D. Exponential
2. The gate signal is also called as ___________. C
 A. clock pulse
B. Control pulse
C. triggering pulse
D. gate width
3. Sampling gates are used in _______.
A. logic gates
B. converters C
C. Sample and Hold circuits
D. timers
4. The variations in phase delay occur due to ____.
A. variations in loop gain, supply voltage
B. variations in voltage gain C
C. variations in signal frequency
D. variations in temperature
5. In Miller circuit, the gain A of the inverting amplifier should be ____.
A. Unity
B. Zero C
C. Infinite
D. Ten
6. The time during which the waveform returns to the initial value is called:
A. Fall time
B. Flyback time B
C. Rise time
D. Delay time
7. The circuit which require an amplifier whose gain is nearly infinity
A. Boot strap ckt
B. Miller ckt B
C. Phantastron ckt
D. Inductor ckt
8. A Transmission circuit which allows an input Signal to pass through it during a
selected interval and blocks it passage outside this time interval is called:
A. Sampling gates
A
B. Conventional gates
C. Non-conventional gates
D. Logic gates
9. In unidirectional sampling gate the combination of RC forms a
A. Differentiator
B. Integrator B
C. Coupling elements
D. Multivibrator
10 The ratio of maximum deviation to the sweep amplitude is called
A. Slope error
B. Displacement error B
C. Transmission error
D. Linear error
11 A capacitor is charged linearly from a constant current source is used to generate
A. Sine wave form
B. Pulse wave form C
C. Time base waveform
D. Trapezoidal wave form
12 The several factors which affect phase delay given rise to
A. Phase jitter
B. amplitude jitter A
C. phase distortion
D. frequency jitter
13 The interval of time is selected by means of an externally applied signal termed as
A. Transient signal
B. gating signal B
C. output signal
D. exponential signal
14 To get a saw-tooth out put waveform, the restoration time is
A. Zero
B. Rise time A
C. Storage time
D. Infinity
15 In Miller time base generator, which of the following is used
A. An inverting amplifier with a gain of unity
B. An inverting amplifier with a gain of infinity B
C. Non-inverting amplifier with a gain of unity
D. Non-inverting amplifier with a gain of infinity
16 The time during which the output increases linearly is called
A. Sweep time
B. Flyback time A
C. Return time
D. Restoration time
17 The interval of time of transmission of a signal in a sampling gate is selected by
means of
A. Time delay
C
B. Off time of gate
C. Gating signal
D. Source signal
18 The following all are disadvantages of unidirectional gate, except
A. Interaction between the signal source and control voltage source
B. Limited used of gate D
C. Slow rise of the control voltage
D. Little time delay though the gate
19 A circuit that allows transmission faithfully during a fixed time interval is called
A. Logic gate
B. Flip-flop C
C. Sampling gate
D. Schmitt trigger
20 The duration for which signal transmission takes place in a sampling gate is
described by a:
A. Gating signal
A
B. Exponential signal
C. Sinusoidal signal
D. Ramp
21 A sampling gate that allows the transmission of a signal of only one polarity is B
called:
A. Bidirectional gate
 B. Unidirectional gate
C. Logic gate
D. Flip-flop
22 A sampling gate that allows the transmission of signals of both positive and
negative polarity is called.
A. Bidirectional gate
A
B. Unidirectional gate
C. Logic gate
D. Flip-flop
23 The dc voltage present in the output of a sampling gate along with the desired
signal is termed as.
A. Pedestal
A
B. Noise
C. Gain
D. Error voltage
24 A chopper amplifier is employed to amplify.
A. Small signals with small dV/dt
B. Large signals with large dV/dt C
C. Small signals with large dV/dt
D. Large signals with small dV/dt
25 To display the shape of the waveform, sometimes a sequence of samples delayed
in time with respect to a reference point are used in an instrument named as.
A. Sweep generator
C
B. Television
C. Sampling scope
D. Multivibrator
26 The application of a voltage time base generator is in a measuring instrument like.
A. CRO
B. Frequency counters A
C. Digital voltmeter
D. Multimeter
27 The deflection of the electron beam in a CRO employing a voltage sweep
generator is based on the principle of.
A. Electromagnetic deflection
A
B. Electrostatic deflection
C. Frequency multiplication
D. Counting
28 Errors es, ed and et define:
A. Current gain
B. Voltage gain C
C. Deviation from linearity
D. Bandwidth
29 If in a simple exponential sweep generator, the supply voltage is 200 V and the
required sweep amplitude is 10 V, and then the slope error is.
A. 5 %
A
B. 20 %
C. 200 %
D. 0.5 %
30 In a simple exponential sweep generator, the time constant of the circuit is D
1000 µs and the sweep duration is 100 µ s, then the slope error is.
 A. 5 %
B. 100 %
C. 15%
D. 10 %
31 For the output of a voltage sweep generator to be linear, the capacitor must be
charged with a
A. Constant current
C
B. Linearly varying current
C. Exponentially varying current
D. Zero current
32 A Miller sweep generator produces a
A. Positive-going sweep
B. Negative-going sweep A
C. Constant sweep voltage
D. Infinite output voltage
33 A bootstrap generator produces a
A. Positive-going sweep voltage
B. Negative-going sweep voltage B
C. Constant sweep voltage
D. Infinite sweep voltage
34 The slope error es and the displacement error ed are related as
A. es = 2ed
B. 8 es = ed D
C. es = 4 ed
D. es = 8 ed
35 The displacement error ed and the transmission error et are related as
A. et = 4 ed
B. et = 2 ed A
C. et = ed
D. et = ed
36 The slope error es and the transmission error et are related as
A. es = 2 et
B. es = 0.5et A
C. es = et
D. es = 4et
37. The sweep duration of a UJT sweep generator is given as
A. 0.69 τ
B. τ ln{(VBB − VP)/(VBB − VV)} B
C. τ ln{(VBB − VV)/(VBB − VP)}
D. 1.4 τ
38. ____circuit converts voltage pulse into ramp
A. Bootstrap
B. phantraston B
C. Miller
D. RLC
39 A bootstrap sweep circuit employs
A. No feeedback
B. positive feeedback B
C. Negative feeedback
D. Degenerative feedback
40 A_______ is one that provides an output waveform a portion of which exhibits a
linear variation of voltage or current with time.
A. Linear time-base generator
A
B. Non-linear time-base generator
C. Voltage time-base generator
D. Current time-base generator
41 The most important application of a time-base generator is in
A. TVs
B. Radar displays C
C. CROs
D. Time measurements
42 To get a saw-tooth or ramp output waveform the restoration time must be
A. Zero
B. Infinity A
C. Small
D. Large
43 The ratio of difference in slop at the beginning and end of sweep to the initial
value of slop is called
A. Sweep speed error
A
B. Displacement error
C. Transmission error
D. Difference error
44 The ratio of the maximum difference between the actual sweep and the linear
sweep which passes through the beginning and end points of the actual sweep to
the amplitude of the sweep is called the
A. Sweep speed error B
B. Displacement error
C. Transmission error
D. Difference error
45 The ratio of the difference between the input and the output to the input at the end
of the sweep is called the
A. Sweep speed error
C
B. Displacement error
C. Transmission error
D. Difference error
46 ---------currents are required for magnetic deflection applications
A. Linearly varying
B. Non-linearly varying A
C. Constant
D. Decreasing
47 When resistances are consider to obtain the linear current sweep______ voltage is
to be applied across an inductor.
A. Step
C
B. Ramp
C. Trapezoidal
D. Rectangular
48 The ___________networks may be used to improve the linearty of miller and C
bootstrap circuits
A. RLC series
B. RLC parallel
 C. Compensating
D. Linear
49 A circuit which generates non sinusoidal wave forms is called
A. Relaxation oscillator
B. Square wave generator A
C. Non sinusoidal oscillator
D. Sinusoidal oscillator
50 The time based generator may be ____or _______________
A. Voltage time based generators, current based time generators
B. Relaxation oscillator or sinusoidal oscillator A
C. Non sinusoidal oscillator or square wave oscillator
D. Square wave oscillator or relaxation wave oscillator
 UNIT-IV
SYNCHRONIZATION AND FREQUENCY DIVISION
SYLLABUS:
Synchronization and frequency division: Pulse synchronization of relaxation devices, frequency division
with sweep circuits, other astable relaxation circuits, synchronization of astable multivibrator, monostable
relaxation circuits as dividers, stability of relaxation dividers; Synchronization of a sweep circuit with
symmetrical signals: Sinusoidal synchronization signals and sine wave frequency division with a sweep
circuit.
S.No. Question Answer
1. If synchronisation is achieved with different frequencies , ie., one
Frequency being twice the other then it is termed as
A. No synchronization occurs
A
B. Frequency matching
C. Synchronization
D. Synchronisation with frequency division
2. The variations in phase delay are called as
[ d]
A. Sampling gates
D
B. Phase jitters
C. Phase shifters
D. Blocking jitters
3. When two generators produce waveforms at different frequencies, it is Essential
for proper synchronization that the frequency of one generator is an of that of the
other generator.
A. One-to many C
B. Multiplexing
C. One-to-one basis
D. Many to one
4. When two generators produce waveforms at different frequencies, it is Essential
for proper synchronization that the frequency of one generator is an of that of the
other generator.
A. Odd multiples D
B. Secondary harmonies
C. Even multiples
D. Integral multiple
5 If synchronization is achieved with different frequencies , ie., one
Frequency being twice the other then it is termed as
A. Frequency matching
D
B. No synchronization occurs
C. Synchronization
D. Synchronization with frequency division
6. When two generators with equal frequencies run in synchronism the
Synchronization is said to be on
A. many to one
B
B. one-to-one basis
C. one-to many
D. Multiplexing
7. The biggest advantage of Triggered sweep circuit is B
[ ]
A. slow wave operation
 B. Free running operation
C. Complex operation
D. Fast running operators
8. If synchronization is achieved with different frequencies , ie., one
Frequency being twice the other then it is termed as
A. No synchronization occurs
D
B. Synchronization
C. Frequency matching
D. Synchronization with frequency division
9. A sampling gate is also termed as
[ ]
A. Linear gate
C
B. Time-selection gate
C. Time selection & linear gates
D. Non-linear gate
10 Synchronization of sweep circuit can be obtained by
[ ]
A. Non identical phase signals
C
B. Identical phase signals
C. Symmetrical signals
D. Unsymmetrical signals
11 Monostable relaxation circuit is used as a
[ ]
A. Time division
C
B. Both time and frequency
C. Frequency division
D. Only frequency multiplexing
12 By making —————, a divider circuit with a division factor n can be built
[ ]

A. TO < nTp B
B. TO > nTp
C. TO = 2nTp
D. TO = nTp
13 Sampling gate for which input voltage is
[]
A. dc only
D
B. Sampling of ac signal
C. ac only
D. Either dc or ac
14 If synchronization is achieved such that one frequency is integer multiple
of other ]
A. Frequency matching
D
B. No synchronization occurs
C. Frequency division
D. Synchronization with frequency division
15 Stray signals are B
[]
A. Introducing distortion
B. affects synchronization severely
 C. doesn’t affect synchronization
D. unwanted noisy signals
16 In a Sinusoidal synchronization signal UJT is used as a switch because
[ ]
A. negative resistance voltage controlled device
B
B. negative resistance current controlled device
C. voltage divider
D. Current divider
17 Synchronization of sweep circuit can be obtained by
[ ]
A. Non identical phase signals
D
B. Symmetrical signals
C. identical phase signals
D. unsymmetrical signals
18 Monostable relaxation circuit is used as a
[ ]
A. both time and frequency
D
B. time division
C. only frequency multiplexing
D. frequency division
19. If synchronization is achieved with different frequencies , ie., one Frequency
being twice the other then it is termed as
A. frequency matching
D
B. No synchronization occurs
C. synchronization
D. synchronization with frequency division
20 The biggest disadvantage of sampling gate is
A. Fast rise of control voltage
B. The slow rise of control current C
C. The slow rise of control voltage
D. Rise time , fall time
21 Sweep generators, multivibrators and blocking oscillators are classified as:
A. Relaxation circuits
B. Multistage amplifiers A
C. Sampling gates
D. Clipping and clamping circuits
22 When synchronization with the frequency division is implemented in a pulse or a
digital system, this circuit can be called as a:
A. Scale-of-two circuit
D
B. Counting circuits
C. Schmitt trigger
D. Sweep generator
23 Timing interval in a relaxation circuit is established by the:
A. Charging and discharging of a capacitor
B. Charging of a capacitor A
C. Discharging of a capacitor
D. No effects on capacitor
24 Timing interval in a relaxation circuit is established by the: A
A. Charging and discharging of a capacitor
B. Charging of a capacitor
 C. Discharging of a capacitor
D. No effects on capacitor
25 A relaxation circuit can be synchronized by a train of sync pulses. For
synchronization to take place:
A. Tp > To and the amplitude of the pulses should be reasonably large
B
B. Tp ≤ To and the pulses can have any amplitude
C. Tp ≤ To and the amplitude of the pulses should be reasonably large
D. Tp > To and the pulses can have any amplitude
26 It is possible to synchronize the output of a UJT relaxation circuit with
symmetric sync signals when:
A. T > To
C
B. T < To
C. T ≤ To and T ≥ To
D. T≤ T0
27 The time interval between the instant the input pulse is applied to a frequency
divider to the instant it appears at the output is called:
A. Phase delay
B
B. Resolution
C. Time Propagation delay
D. Storage time
28 The phase delay that varies due to the cumulative effect of the variations in the
device characteristics, supply voltage and noise is termed as:
A. Noise margin
D
B. Resolution
C. Time Propagation delay
D. Phase jitter
29 When synchronizing the output of a UJT relaxation circuit with symmetric
signals, if T > To, the duration of the sweep is:
A. Lengthened
B
B. Shortened
C. Remains unchanged
D. Doubled
30 When synchronizing the output of a UJT relaxation circuit with symmetric
signals, if T < To, the duration of the sweep is:
A. Lengthened
C
B. Shortened
C. Remains unchanged
D. Halfed
31 Two or more generators are said to be running ___ if all of them arrive at
reference point in the cycle at exactly the same instant of time.
A. Synchronously
B
B. Asynchronously
C. Symmetrically
D. Asymmetrically
32 When two generators produce waveforms at different frequencies, it is essential A
for proper synchronization that the frequency of one generator is an ___ of that
of the generator.
A. Integral multiple
 B. Derivative
C. Integral
D. Additive
33 When generators with equal frequencies run in synchronism, the synchronization
is said to be on a
A. One-to-one basis
A
B. Equal basis
C. Any-to-one basis
D. Any-to-any basis
34 If synchronization is achieved with different frequencies, i.e. one frequency being
thrice the other, then it is termed
A. Synchronization with frequency multiplication
B. Synchronization with frequency division B
C. Multiple synchronization
D. Multiple Asynchronization

35 Two or more generators are said to be running ___ provided , all generators arrive
at reference point in the cycle simultaneously.
A. Synchronously
B. Asynchronously A
C. Symmetrically
D. Asymmetrically

36 A divider circuit with a division factor n can be built by making

A. T0 ˂ n Tp
B. T0 = n Tp
C
C. T0 > n Tp
D. T0 ≠ n Tp

37 The time interval between the time of occurrence of the pulse which prematurely
terminates the cycle and the instant of the change of state of the oscillator is
termed as
A. Total phase delay
A
B. Phase jitters
C. Magnitude delay
D. Magnitude jitter

38 The several factors which affect phase delay give rise to

A. Total phase delay
B. Phase jitters
B
C. Magnitude delay
D. Magnitude jitter

39 Synchronization may be on a ____ or may be with ____

A. One-to –one basis, frequency division
B. One-to-many basis, time division
A
C. Many-to-one basis, time
D. Many to-many basis, phase
40 If synchronization is achieved with different frequencies, i.e. N times the other,
then it is termed
A. Synchronization with frequency multiplication
B. Synchronization with frequency division B
C. Multiple synchronization
D. Multiple Asynchronization

41 Counting circuits are example of synchronization with

A. time division
B. frequency division B
C. phase jitter
D. phase delay
42 The circuits in which the timing interval is established through, gradual charging
of a capacitor the timing interval being terminated by sudden discharge of
capacitor are called
A. frequency circuits
C
B. time based circuits
C. relaxation circuits
D. oscillators

43 The multivibrators, time base generators, blocking oscillators are examples of—
A. frequency circuits
B. time based circuits
C
C. relaxation circuits
D. oscillators

44 Synchronization with pulse signals is only possible if

A. Tp≤ T0
B. T0 = Tp A
C. Tp > T0
D. T0 ≠ Tp
45 In case of synchronization with symmetrical signals, synchronization is possible
for both ___ and ___
A Tp≤ T0 & T0 = Tp
B. T0 = Tp A
C. Tp > T0
D. T0 ≠ Tp
46 In pulse synchronization as well as synchronization with symmetrical signals
range of synchronization increase with increasing----
A. Amplitude
B. Time A
C. Frequency
D. Phase

47 Between the instant of occurrence of pulse which pre maturely terminates cycle D
and the instant of change of oscillator, there is a certain time delay this is
termed as
A. Amplitude
B. Time delay
C. Frequency
 D. Phase delay

48 Several factors which effect phase delay gives rise to

A. Phase delay
B. Phase jitter
B
C. Magnitude delay
D. Time delay

49 Any --- controlled negative resistance device can be used as relaxation circuit
A. Current control
B. Voltage control
A
C. Time control
D. Frequency

50 The periodic variations in phase delay due to extraneous signals is termed as

A. Phase delay
B. Phase jitter
B
C. Magnitude delay
D. Time delay
 UNIT- V
DIGITAL LOGIC FAMILIES
SYLLABUS:
Bipolar logic families: RTL, DTL, DCTL, HTL, TTL, ECL, MOS, and CMOS logic families, tristate
logic; Interfacing of CMOS and TTL families.
S.No. Question Answer
1. What is unique about TTL devices such as the 74SXX
A. These devices use Schottky transistors and diodes to prevent them from going
into saturation; this results in faster turn-on and turn-off times, which
translates into higher frequency operation.
B. The gate transistors are silicon (S), and the gates therefore have lower values
of leakage current.
A
C. The gate transistors are silicon (S), and the gates therefore have lower values
of leakage current.
D. The S denotes the fact that a single gate is present in the IC rather than the
usual package of 2–6 gates.
The S denotes a slow version of the device, which is a consequence of its
higher power rating.
2. Which of the following logic families has the shortest propagation delay
A. CMOS
B. Bi CMOS B
C. ECL
D. 74SXX
3. Why must CMOS devices be handled with care
A. So they don’t get dirty
B. Because they break easily C
C. Because they can be damaged by static electricity discharge
D. Because they don’t break easily
4. Special handling precautions should be taken when working with MOS devices.
Which of the following statements is not one of these precautions
A. All test equipment should be grounded.
B. MOS devices should have their leads shorted together for shipment and
D
storage.
C. Never remove or insert MOS devices with the power on.
D. Workers handling MOS devices should not have grounding straps attached to
their wrists
5 What should be done to unused inputs on TTL gates
A. They should be left disconnected so as not to produce a load on any of the
other circuits and to minimize power loading on the voltage source.
B. All unused gates should be connected together and tied to V<sub<cc< sub=""
style="margin: 0px; box-sizing: border-box;"> through a 1 k
D
resistor.</sub<cc<>
C. All unused inputs should be connected to an unused output; this will ensure
compatible loading on both the unused inputs and unused outputs.
D. Unused AND and NAND inputs should be tied to VCC through a 1 k
resistor; unused OR and NOR inputs should be grounded.
6. Assume that a particular IC has a supply voltage (Vcc) equal to +5 V and ICCH = 10 B
mA and ICCL = 23 mA. What is the power dissipation for the chip
A. 50 Mw
B. 82.5 mW
 C. 115 mW
D. 165 mW
7. What is the major advantage of ECL logic
A. Very high speed
B. Wide range of operating voltage A
C. Very low cost
D. Very high power
8. What is the range of invalid TTL output voltage
A. 0.0–0.4 V
B. 0.4–2.4 V B
C. 2.4–5.0 V
D. 0.0–5.0 V
9. What is the difference between the 54XX and 74XX series of TTL logic gates
A. 54XX is faster.
B. 54XX is slower. C
C. 54XX has a wider power supply and expanded temperature range.
D. 54XX has a narrower power supply and contracted temperature range.
10 An open collector output can ________ current, but it cannot ________.
A. sink, source current
B. source, sink current A
C. sink, source voltage
D. source, sink voltage
11 Why is a decoupling capacitor needed for TTL ICs and where should it be
connected
A. to block dc, connect to input pins
C
B. to reduce noise, connect to input pins
C. to reduce the effects of noise, connect between power supply and ground
D. to increase noise, connect to input pins
12 Using the schematic diagram of a TTL NAND gate, determine the state of each
transistor (ON or OFF) when all inputs are high.
A. Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
D
B. Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
C. Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
D. Q1-OFF, Q2-ON, Q3-OFF, Q4-ON
13 If all inputs to a TTL NAND gate are low, what is the ON, OFF condition of each
transistor in the circuit
A. Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
A
B. Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
C. Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
D. Q1-OFF, Q2-ON, Q3-OFF, Q4-ON
14 Which of the following summarizes the important features of emitter-coupled
logic (ECL)
A. low noise margin, low output voltage swing, negative voltage operation, fast,
and high power consumption
B. good noise immunity, negative logic, high-frequency capability, low power
A
dissipation, and short propagation time
C. low propagation time, high-frequency response, low power consumption, and
high output voltage swings
D. poor noise immunity, positive supply voltage operation, good low-frequency
operation, and low power
15 Why is a pull-up resistor needed for an open collector gate
A. To provide Vcc for the IC
B. To provide ground for the IC C
C. To provide the HIGH voltage
D. To provide the LOW voltage
16 Why is a pull-up resistor needed when connecting TTL logic to CMOS logic
A. To increase the output LOW voltage
B. To decrease the output LOW voltage C
C. To increase the output HIGH voltage
D. To decrease the output HIGH voltage
17 The word "interfacing" as applied to digital electronics usually means:
A. A conditioning circuit connected between a standard TTL NAND gate and a
standard TTL OR gate
B. A circuit connected between the driver and load to condition a signal so that it
B
is compatible with the load
C. Any gate that is a TTL operational amplifier designed to condition signals
between NMOS transistors
D. Any TTL circuit that is an input buffer stage
18 The rise time (tr) is the time it takes for a pulse to rise from its ________ point up
to its ________ point. The fall time (tf) is the length of time it takes to fall
from the ________ to the ________ point.
A. 10%, 90%, 90%, 10% A
B. 90%, 10%, 10%, 90%
C. 20%, 80%, 80%, 20%
D. 10%, 70.7%, 70.7%, 10%
19. PMOS and NMOS ________.
A. represent MOSFET devices utilizing either P-channel or N-channel devices
exclusively within a given gate
B. are enhancement-type CMOS devices used to produce a series of high-speed
logic known as 74H
A
C. represent positive and negative MOS-type devices, which can be operated
from differential power supplies and are compatible with operational
amplifiers
D. represent MOSFET devices utilizing either P-channel and N-channel devices
exclusively within a given gate
20 Why is the operating frequency for CMOS devices critical for determining power
dissipation
A. At low frequencies, power dissipation increases
B. At high frequencies, the gate will only be able to deliver 70.7 % of rated
power.
C
C. At high frequencies, charging and discharging the gate capacitance will draw
a heavy current from the power supply and thus increase power dissipation.
D. At high frequencies, the gate will only be able to deliver 70.7 % of rated
power and charging and discharging the gate capacitance will draw a heavy
current from the power supply and thus increase power dissipation.
21 Ten TTL loads per TTL driver is known as:
A. Noise immunity
B. Fan-out B
C. Power dissipation
D. Propagation delay
22 The problem of different current requirements when CMOS logic circuits are
driving TTL logic circuits can usually be overcome by the addition of:
A. CMOS inverting bilateral switch between the stages
D
B. TTL tristate inverting buffer between the stages
C. CMOS non inverting bilateral switch between the stages
D. CMOS buffer or inverting buffer
23 Totem-pole outputs ________ be connected ________ because ________.
A. can, in parallel, sometimes higher current is required
B. cannot, together, if the outputs are in opposite states excessively high currents
can damage one or both devices B
C. should, in series, certain applications may require higher output voltage
D. can, together, together they can handle larger load currents and higher
output voltages
24 The high input impedance of MOSFETs:
A. allows faster switching
B. reduces input current and power dissipation B
C. prevents dense packing
D. creates low-noise reactions
25 The output current capability of a single 7400 NAND gate when HIGH is
called ________.
A. source current
A
B. sink current
C. IOH
D. source current of IOH
26 The time needed for an output to change from the result of an input change is
known as:
A. noise immunity
C
B. fan-out
C. propagation delay
D. rise time
27 The problem of interfacing IC logic families that have different supply voltages
(VCC's) can be solved by using a:
A. level-shifter
A
B. tri state shifter
C. decoupling capacitor
D. pull-down resistor
28 What is the advantage of using low-power Schottky (LS) over standard TTL logic
A. more power dissipation
B. less power dissipation B
C. cost is less
D. cost is more
29 When is a level-shifter circuit needed in interfacing logic
A. A level shifter is always needed.
B. A level shifter is never needed. D
C. when the supply voltages are the same
D. when the supply voltages are different
30 A TTL totem-pole circuit is designed so that the output transistors: D
A. are always on together
B. provide linear phase splitting
C. provide voltage regulation
 D. are never on together
31 The most common TTL series ICs are:
A. E-MOSFET
B. 7400 B
C. Quad
D. AC00
32 Fan-out is determined by taking the ________ result(s) of ________.

A. smaller,

B. larger, C

C. smaller,

D. average,
33 Which family of devices has the characteristic of preventing saturation during
operation
A. TTL
C
B. MOS
C. ECL
D. IIL
34 How many 74LSTTL logic gates can be driven from a 74TTL gate
A. 10
B. 20 B
C. 200
D. 400
35 What is the difference between the 74HC00 series and the 74HCT00 series of
CMOS logic
A. The HCT series is faster.
C
B. The HCT series is slower.
C. The HCT series is input and output voltage compatible with TTL.
D. The HCT series is not input and output voltage compatible with TTL.
36 From the following specifications determine the fan-out for the logic family.

B
A. HIGH state is 16, LOW state is 8
B. HIGH state is 8, LOW state is 16
C. HIGH state is 4, LOW state is 8
D. HIGH state is 8, LOW state is 4
37 Why are the maximum value of VOL and the minimum value of VOH used to
determine the noise margin rather than the typical values for these parameters
A. These are worst-case conditions.
B. These are normal conditions. A
C. These are best-case conditions.
D. It doesn't matter what values are used
38 What is the standard TTL noise margin
A. 5.0 V
B. V D
C. 0.8 V
D. 0.4 V
39 Which logic family is characterized by a multi emitter transistor on the input
A. ECL
B. CMOS C
C. TTL
D. DTL
40 How is the speed–power product of a logic family determined
A. The propagation delay in s is multiplied by the power dissipation in mW.
B. The propagation delay in ms is multiplied by the power dissipation in W.
C. The propagation delay in ns is multiplied by the power dissipation in mW. C
D. The propagation delay in ns is multiplied by the power dissipation in W.

41 The problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit
and meet the CMOS requirement of VIH(min) is usually easily overcome by:
A. adding a fixed voltage-divider bias resistive network at the output of the TTL
device.
B. adding a fixed voltage-divider bias resistive network at the output of the TTL D
device
C. avoiding this condition and only using TTL to drive TTL adding an external
pull-down resistor to ground
D. adding an external pull-up resistor to VCC
42 How does the 4000 series of CMOS logic compare in terms of speed and power
dissipation to the standard family of TTL logic
A. more power dissipation and slower speed
B. more power dissipation and faster speed D
C. less power dissipation and faster speed
D. less power dissipation and slower speed
43 What should be done with unused inputs to a TTL NAND gate
A. let them float
B. tie them LOW C
C. tie them HIGH
D. let them zero.
44 Which of the following digital IC logic families is most susceptible to static
discharge
A. RTL
C
B. ECL
C. MOS
D. TTL
45 Which of the following is a concern when using CMOS type devices
A. mechanical shock
B. electrostatic discharge B
C. fan out
D. under voltage
46 Which of the following is not a solution to interface problems between CMOS
and TTL
A. pull-up resistor
B
B. pull-down resistor
C. level-shifter
D. buffer
47 Which of the following is not a common logic family used today
A. RTL
B. ECL A
C. TTL
D. CMOS
48 The output current for a LOW output is called a(n)
A. exit current.
B. sink current. B
C. ground current.
D. fan-out.
49 Which of the following are not characteristics of TTL logic gates
A. Totem-pole output
B. Bipolar transistors C
C. CMOS transistors
D. Multiemitter transistors
50 Which of the following output levels would not be a valid LOW for a TTL gate
A) 0.3 V
B) 0.5 V D
C) 0.2 V
D) 10V