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    Arhitecturi de Microcalculatoare: - Von Neuman - Caracteristici

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    Ioan Susnea
    The document discusses and compares the Von Neumann and Harvard architectures, as well as some of their characteristics and consequences. It then focuses on the Harvard architecture, explaining features like separate program and data memory buses, pipelining, and instruction sizes. Examples given are the Motorola HC11 and Atmel AVR microcontrollers. Interrupt systems are also covered, including registers, masking, priorities, and initialization of interrupt vectors.

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    Arhitecturi de Microcalculatoare: - Von Neuman - Caracteristici

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    Ioan Susnea
    122 views18 pages
    The document discusses and compares the Von Neumann and Harvard architectures, as well as some of their characteristics and consequences. It then focuses on the Harvard architecture, explaining features like separate program and data memory buses, pipelining, and instruction sizes. Examples given are the Motorola HC11 and Atmel AVR microcontrollers. Interrupt systems are also covered, including registers, masking, priorities, and initialization of interrupt vectors.

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    The document discusses and compares the Von Neumann and Harvard architectures, as well as some of their characteristics and consequences. It then focuses on the Harvard architecture, explaining features like separate program and data memory buses, pipelining, and instruction sizes. Examples given are the Motorola HC11 and Atmel AVR microcontrollers. Interrupt systems are also covered, including registers, masking, priorities, and initialization of interrupt vectors.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    122 views18 pages

    Arhitecturi de Microcalculatoare: - Von Neuman - Caracteristici

    Uploaded by

    Ioan Susnea
    The document discusses and compares the Von Neumann and Harvard architectures, as well as some of their characteristics and consequences. It then focuses on the Harvard architecture, explaining features like separate program and data memory buses, pipelining, and instruction sizes. Examples given are the Motorola HC11 and Atmel AVR microcontrollers. Interrupt systems are also covered, including registers, masking, priorities, and initialization of interrupt vectors.

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    of 18

    Arhitecturi de microcalculatoare

    • Von Neuman
    • Caracteristici:

    • Magistrala comuna
    pentru memoria de
    program si de date
    • Exemplu tipic:
    • Motorola HC11
    • Arhitectura Harvard
    • Caracteristici:
    • magistrale distincte
    pentru program si date

    • Exemplu tipic
    • Atmel AVR
    Consecinte ale arhitecturii Harvard
    – The presence of the second bus makes the following things possible:
    − While an instruction is executed, the next instruction can be fetched
    from the program memory. This technique is called pipelining and
    brings a significant increase of the computer speed.
    − The program memory can be organized in words of a different size,
    usually larger, than the data memory. Wider instructions mean a
    greater data flow to the CPU, and therefore the overall speed is
    higher.
    − Such architecture, along with reducing and optimizing the instruction
    set, allow that most instructions execute in a single machine cycle.
    Since the Harvard architecture is often accompanied by the reduction
    of the size and complexity of the instruction set, the computers with
    this architecture are also called RISC. (Reduced Instruction Set
    Computers) For example, some PIC microcontrollers have an
    instruction set of only 35 instructions, compared to more than 100 of
    HC11. The speed increase is even higher.
    Consecinte asupra organizarii spatiului de adrese

    • Harta memoriei in
    cazul unui
    microcontroller HC11
    • Harta memoriei
    pentru un
    microcontroller
    din seria Atmel
    AVR
    • Se observa ca aici
    exista 3 spatii de
    adrese
    Registrele interne ale CPU

    • HC11 • AVR
    • Doi acumulatori A si B. Pot fi • 32 acumulatori R0-R31
    concatenati pentru a forma un • R26-R27, R28-R29, R30-R31
    registru dublu D can be concatenated to form the
    • Doua registre index X si Y X, Y, Z , registers
    • Stack pointer • Stack pointer SP
    • Registrul de stare CPU denumit • registrul de stare CPU denumit
    CCR SREG
    • Numaratorul de program PC • Numaratorul de program
    Interfetele periferice

    • Any peripheral
    interface contains
    one or more
    control and status
    registers, and one
    or more data
    registers
    • These registers are,
    normally, located
    in the address
    space of the data
    memory, and are
    accessed as RAM
    locations
    Interfete periferice uzuale

    − The I/O (Input/Output) ports.


    − The asynchronous serial interface (SCI, UART)
    − The synchronous serial interfac(SPI)
    − Several types of timers
    The Analog to Digital (A/D) converters
    Sistemul de intreruperi

    Definitie:
    • An interrupt is a mechanism that allows an
    external event to temporarily put on hold the
    normal execution of the program, forcing the
    execution of a specific subroutine. Once the
    interrupt service subroutine completes, the main
    program continues from the point where it was
    interrupted.
    Procesul de tratare a unei intreruperi

    – .The identification of the interrupt source. This is automatically


    done by hardware.
    – .Saving the current value of the PC register, thus providing a
    means to return from the interrupt service routine. The contents of
    PC is saved to the stack, and the operation is also done by
    hardware.
    – .Then, the PC is loaded either with, or from the address of a
    reserved memory area, called interrupt vector. For each possible
    interrupt, a unique vector is assigned. The interrupt vectors are
    hardwired and cannot be modified by user.
    – .At the address of the interrupt vector, the program must contain
    either the address of the interrupt service routine (HC11 uses this
    technique) or an instruction for an unconditional jump to this
    routine (AVR and 8051 work this way).
    Tratarea unei intreruperi - continuare

    • The next step is the execution of the interrupt service routine (ISR).
    This is a program sequence similar to a subroutine, but ended with a
    special instruction called Return from Interrupt (RTI, RETI).
    • Observatie importanta: STAREA masinii trebuie salvata prin soft
    inainte de executia rutinei de intrerupere si restaurata dupa executia
    rutinei de intrerupere.
    • The final step in handling an interrupt is the actual return to the main
    program. This is done by executing a RTI (RETI) instruction as
    mentioned before. When this instruction is encountered, the contents of
    PC, saved in step 2, is retrieved from stack and restored, which is
    equivalent to a jump to the point where the program was interrupted.
    Intreruperi - note importante

    The stack is essential for the interrupt system. Both the PC and the
    CPU status are saved in the stack when handling interrupts.
    Therefore, the SP must be initialized by software before enabling
    the interrupts.
    The interrupt service routine must save the CPU status and restore
    it before returning to the main program.
    If two or more interrupt requests occur simultaneously, they are
    serviced in a predetermined, order according to a hardwired
    priority
    Controlul asupra intreruperilor

    • Exista o dubla conditionare a


    intreruperilor
    • The software control over the
    interrupt system is exerted
    either globally, by
    enabling/disabling all the
    interrupts by means of specific
    instructions, or individually, by
    setting or clearing some control
    bits, called interrupt masks,
    associated with each interrupt.
    Conditionarea intreruperilor

    • The INTERRUPT FLAG is the actual interrupt source, and, usually, is a


    flip-flop set by the external event. This bit is, in most cases, accessible for
    the program as a distinct bit in the status register of the peripheral
    interface.
    • The LOCAL INTERRUPT MASKS are control bits, located in the control
    registers of the interface. When set to 1 by software, the interrupts from
    that specific interface are enabled.
    • The GLOBAL INTERRUPT MASK is a bit located in the CPU status
    register (CCR, SREG,PSW) that enables or disables all interrupts.
    • In some cases, it is required that the CPU is informed immediately about
    some important internal or external events, regardless of the status of the
    global interrupt mask. The solution to this problem is the non-maskable
    interrupt, which is unconditionally transmitted to the CPU. A special case
    of non-maskable interrupt can be considered the RESET. Basically, the
    behavior of the MCU at RESET is entirely similar to the process of
    identification and execution of a non-maskable interrupt.
    Particularitati ale sistemului de intreruperi al HC11

    • Starea masinii este salvata automat in stiva la recunoasterea unei


    intreruperi si este restaurata automat la revenirea din rutina de
    intrerupere
    • Admite intreruperi nemascabile (XIRQ, SWI si TRAP)
    • Controlul global asupra intreruperilor se face cu ajutorul bitului I din
    registrul CCR. Acesta este afectat de intructiunile specifice SEI (Set
    Interrupt Mask - echivalent cu Disable Interrupts) si CLI - (Clear
    Interrupt Mask - echivalent cu Enable Interrupts)
    • Exista un registru denumit HPRIO (Highest Priority Interrupt) cu
    ajutorul caruia se poate alege intreruperea cu prioritate maxima
    • Zona de vectori de intrerupere este plasata la sfarsitul spatiului de
    adrese ($FFC0-$FFFF)
    • Vectorul contine adresa rutinei de intrerupere
    Particularitati ale intreruperilor la AVR

    −The interrupt vector does not contain the address of the


    interrupt service routine, but a jump instruction to that
    routine.
    −The vector area is located at the beginning of the
    program memory address space, between the addresses
    $0000-$0010.
    −There are no non-maskable interrupts besides RESET.
    −The I bit in SREG acts differently, compared to HC11:
    when I=1, the interrupts are enabled.
    −There is no equivalent to the HPRIO register, and no
    other means to modify the hardwired relative priority of
    interrupts.
    Exemplu de initializare a vectorilor de intrerupere la
    HC11

    MAIN ....... ;Program entry point at


    ;RESET
    .......
    ORG $FFFE ;store the value of the
    ;label MAIN at $FFFE-$FFFF
    DW MAIN
    Exemplu de initializare a vectorilor de intrerupere la
    AVR

    .......
    .ORG $000C
    RJMP ANA_COMP ;unconditional jump to the
    ;interrupt handler
    .......
    ANA_COMP:
    .......
    RETI

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