cd74hc4051 PDF
cd74hc4051 PDF
cd74hc4051 PDF
• On Products Compliant to MIL-PRF-38535, (1) For all available packages, see the orderable addendum at
the end of the data sheet.
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production Functional Diagram of HC4051 and HCT4051
Processing Does Not Necessarily Include Testing CHANNEL IN/OUT
16 4 2 5 1 12 15 14 13
2 Applications TG
TG
• Digital Radio S0 11
• Signal Gating TG
• Factory Automation S1 10
TG
A
BINARY 3 COMMON
• Televisions LOGIC
LEVEL
TO
1 OF 8 TG
OUT/IN
DECODER
CONVERSION
• Appliances S2 9
WITH
ENABLE
TG
TG
8 7
GND VEE
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD54HC4051, CD74HC4051
CD54HCT4051, CD74HCT4051, CD54HC4052, CD74HC4052, CD54HCT4052
CD74HCT4052, CD54HC4053, CD74HC4053, CD54HCT4053, CD74HCT4053
SCHS122L – NOVEMBER 1997 – REVISED FEBRUARY 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagrams ..................................... 20
2 Applications ........................................................... 1 8.3 Feature Description................................................. 22
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 22
4 Revision History..................................................... 2 9 Application and Implementation ........................ 23
9.1 Application Information............................................ 23
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 23
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6 10 Power Supply Recommendations ..................... 24
6.2 ESD Ratings ............................................................ 6 11 Layout................................................................... 25
6.3 Recommended Operating Conditions ...................... 6 11.1 Layout Guidelines ................................................. 25
6.4 Thermal Information .................................................. 7 11.2 Layout Example .................................................... 25
6.5 Electrical Characteristics: HC Devices...................... 7 12 Device and Documentation Support ................. 26
6.6 Electrical Characteristics: HCT Devices ................. 10 12.1 Documentation Support ........................................ 26
6.7 Switching Characteristics, VCC = 5 V...................... 12 12.2 Related Links ........................................................ 26
6.8 Switching Characteristics, CL = 50 pF .................... 13 12.3 Receiving Notification of Documentation Updates 26
6.9 Analog Channel Specifications ............................... 16 12.4 Community Resources.......................................... 26
6.10 Typical Characteristics .......................................... 17 12.5 Trademarks ........................................................... 26
7 Parameter Measurement Information ................ 18 12.6 Electrostatic Discharge Caution ............................ 26
12.7 Glossary ................................................................ 27
8 Detailed Description ............................................ 20
8.1 Overview ................................................................. 20 13 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Changed Charged device model (CDM) value from: ±1000 V to: ±200 V ............................................................................. 6
• Added Receiving Notification of Documentation Updates section ...................................................................................... 26
CHANNEL A4 1 16 VCC
IN/OUT A6 2 15 A2
VEE 7 10 S1 ADDRESS
SELECT
GND 8 9 S2
CHANNEL B0 1 16 VCC
IN/OUT B2 2 15 A2
CHANNEL
COM OUT/IN BN 3 14 A1 IN/OUT
VEE 7 10 S0
GND 8 9 S1
B1 1 16 VCC
CHANNEL
B0 2 15 BN COM OUT/IN
IN/OUT
C1 3 14 AN COM OUT/IN
COM OUT/IN CN 4 13 A1
CHANNEL
IN/OUT C0 5 12 A0 IN/OUT
E 6 11 S0
VEE 7 10 S1
GND 8 9 S2
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC – VEE DC supply voltage –0.5 10.5 V
VCC DC supply voltage –0.5 7 V
VEE DC supply voltage 0.5 –7 V
IIK DC input diode current VI < – 0.5 V or VI > VCC + 0.5 V ±20 mA
IOK DC switch diode current VI < VEE – 0.5 V or VI > VCC + 0.5 V ±20 mA
DC switch current (2) VI > VEE – 0.5 V or VI < VCC + 0.5 V ±25 mA
ICC DC VCC or ground current ±50 mA
IEE DC VEE current –20 mA
TJMAX Maximum junction temperature 150 °C
TLMAX Maximum lead temperature Soldering 10 s 300 °C
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to GND unless otherwise specified.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For maximum reliability, nominal operating conditions must be selected so that operation is always within the ranges specified in the
Recommended Operating Conditions table.
(2) All voltages referenced to GND unless otherwise specified.
(3) In certain applications, the external load resistor current may include both VCC and signal line components. To avoid drawing VCC
current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed
0.6 V (calculated from rON values shown in Electrical Characteristics: HC Devices and Electrical Characteristics: HCT Devices tables).
No VCC current will flow through RL if the switch current flows into terminal 3 on the HC and HCT4051; terminals 3 and 13 on the HC
and HCT4052; terminals 4, 14, and 15 on the HC and HCT4053.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) CPD is used to determine the dynamic power consumption, per package. PD = CPD VCC2 fI + ∑ (CL + CS) VCC2 fO , fO = output frequency,
fI = input frequency, CL = output load capacitance, CS = switch capacitance, VCC = supply voltage
Maximum HC 63
TA = –55°C to +125°C
switch turn HCT 66
tPHZ,
OFF delay 4053 ns
tPLZ TA = 25°C HC 36
from S or E
to switch output 0 6 TA = –40°C to +85°C HC 45
TA = –55°C to +125°C HC 54
HC 29
TA = 25°C
HCT 31
HC 36
–4.5 4.5 TA = –40°C to +85°C
HCT 39
HC 44
TA = –55°C to +125°C
HCT 47
TA = 25°C HC 225
0 2 TA = –40°C to +85°C HC 280
TA = –55°C to +125°C HC 340
HC 45
TA = 25°C
HCT 55
HC 56
0 4.5 TA = –40°C to +85°C
HCT 69
Maximum HC 68
TA = –55°C to +125°C
switch turn HCT 83
tPZL,
ON delay 4051 ns
tPZH TA = 25°C HC 38
from S or E
to switch output 0 6 TA = –40°C to +85°C HC 48
TA = –55°C to +125°C HC 57
HC 32
TA = 25°C
HCT 39
HC 40
–4.5 4.5 TA = –40°C to +85°C
HCT 49
HC 48
TA = –55°C to +125°C
HCT 59
Maximum HC 98
TA = –55°C to +125°C
switch turn HCT 105
tPZL,
ON delay 4052 ns
tPZH TA = 25°C HC 55
from S or E
to switch output 0 6 TA = –40°C to +85°C HC 69
TA = –55°C to +125°C HC 83
HC 46
TA = 25°C
HCT 48
HC 58
–4.5 4.5 TA = –40°C to +85°C
HCT 60
HC 69
TA = –55°C to +125°C
HCT 72
TA = 25°C HC 220
0 2 TA = –40°C to +85°C HC 275
TA = –55°C to +125°C HC 330
HC 44
TA = 25°C
HCT 48
HC 55
0 4.5 TA = –40°C to +85°C
HCT 60
Maximum HC 66
TA = –55°C to +125°C
switch turn HCT 72
tPZL,
ON delay 4053 ns
tPZH TA = 25°C HC 37
from S or E
to switch output 0 6 TA = –40°C to +85°C HC 47
TA = –55°C to +125°C HC 56
HC 31
TA = 25°C
HCT 34
HC 39
–4.5 4.5 TA = –40°C to +85°C
HCT 43
HC 47
TA = –55°C to +125°C
HCT 51
TA = 25°C HC, HCT 10
Input (control)
CI TA = –40°C to +85°C HC, HCT 10 pF
capacitance
TA = –55°C to +125°C HC, HCT 10
(1) Adjust input voltage to obtain 0 dBm at VOS for fIN = 1 MHz.
(2) VIS is centered at (VCC – VEE) / 2.
(3) Adjust input for 0 dBm.
8
VCC − GND (V)
6
HCT
4 HC
0
0 2 4 6 8 10 12
VCC − VEE (V)
8
VCC − GND (V)
6
HCT
4 HC
0
0 −2 −4 −6 −8
VEE − GND (V)
0 0
VCC = 4.5 V
−2 GND = −4.5 V −20
VEE = −4.5 V VCC = 2.25 V
RL = 50 Ω GND = −2.25 V
PIN 12 TO 3 VEE = −2.25 V
−4 −40 RL = 50 Ω
VCC = 2.25 V
PIN 12 TO 3
dB
dB
GND = −2.25 V
VEE = −2.25 V
−6 RL = 50 Ω −60
PIN 12 TO 3 VCC = 4.5 V
GND = −4.5 V
−8 −80 VEE = −4.5 V
RL = 50 Ω
PIN 12 TO 3
−10 −100
10K 100K 1M 10M 100M 10K 100K 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 3. Channel ON Bandwidth Figure 4. Channel OFF Feedthrough
(HC and HCT4051) (HC and HCT4051)
0 0
VCC = 2.25 V
VCC = 4.5 V
GND = −2.25 V
−2 GND = −4.5 V −20
VEE = −2.25 V
VEE = −4.5 V
RL = 50 Ω
RL = 50 Ω
PIN 4 TO 3
PIN 4 TO 3
−4 −40
VCC = 2.25 V
dB
dB
GND = −2.25 V
VEE = −2.25 V
−6 −60
RL = 50 Ω
PIN 4 TO 3 VCC = 4.5 V
GND = −4.5 V
VEE = −4.5V
−8 −80
RL = 50 Ω
PIN 4 TO 3
−10 −100
10K 100K 1M 10M 100M 10K 100K 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 5. Channel ON Bandwidth Figure 6. Channel OFF Feedthrough
(HC and HCT4052) (HC and HCT4052)
0
0
VCC = 2.25 V
−20 GND = −2.25 V
VCC = 4.5 V VEE = −2.25 V
−1
GND = −4.5 V RL = 50 Ω
VEE = −4.5 V PIN 5 TO 4
RL = 50 Ω −40
PIN 5 TO 4
dB
−2
dB
VCC = 4.5 V
−60
GND = −4.5 V
−3 VCC = 2.25 V VEE = −4.5 V
GND = −2.25 V RL = 50 Ω
VEE = −2.25 V PIN 5 TO 4
−80
RL = 50 Ω
−4 PIN 5 TO 4
−100
10K 100K 1M 10M 100M 10K 100K 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 7. Channel ON Bandwidth Figure 8. Channel OFF Feedthrough
(HC and HCT4053) (HC and HCT4053)
VCC
tr = 6ns tf = 6ns
90%
SWITCH INPUT 50%
10%
90%
SWITCH OUTPUT 50%
10%
(FIGURE A)
VCC VCC
VIS
VOS R
SWITCH SWITCH
VIS VOS1
ON ON
0.1μF INPUT 0.1µF
dB
50Ω 10pF R C
METER
fIS = 1MHz SINEWAVE
R = 50Ω
VCC /2 VCC /2
C = 10pF
VCC
R
SWITCH
VOS2
OFF
dB
VCC /2 R C
METER
VCC /2
Figure 10. Frequency Response Test Circuit Figure 11. Crosstalk Between Two Switches
Test Circuit
VCC
E
VI = VIH VIS
VCC
SWITCH VP−P
SINE− VOS
ON VOS
WAVE 10µF
VIS 600Ω SWITCH
10kΩ 50pF DISTORTION ALTERNATING VOS
METER ON AND OFF
VCC /2 tr, tf ≤ 6ns
VCC /2 fCONT = 1MHz 600Ω 50pF
fIS = 1kHz TO 10kHz SCOPE
50% DUTY
CYCLE
VCC /2
Figure 12. ¼Sine-Wave Distortion Test Circuit Figure 13. Control to Switch Feedthrough Noise
Test Circuit
VCC /2 VCC /2
IN TG OUT
50pF
8 Detailed Description
8.1 Overview
The CDx4HCx4051 devices are a single 8-channel multiplexer having three binary control inputs, S0, S1, and S2
and an ENABLE input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8
inputs to the output.
The CDx4HCx4052 devices are a differential 4-channel multiplexer having two binary control inputs, S0 and S1,
and an ENABLE input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect
the analog inputs to the outputs.
The CDx4HCx4053 devices are a triple 2-channel multiplexer having three separate digital control inputs, S0, S1,
and S2 and an ENABLE input. Each control input selects one of a pair of channels that are connected in a single-
pole, double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the
COMMON OUT/IN terminals are the inputs.
CHANNEL IN/OUT
VCC A7 A6 A5 A4 A3 A2 A1 A0
16 4 2 5 1 12 15 14 13
TG
TG
S0 11
TG
TG
S1 10 A
BINARY 3 COMMON
TO OUT/IN
LOGIC
1 OF 8 TG
LEVEL
DECODER
CONVERSION
WITH
ENABLE
S2 9
TG
TG
E 6
TG
8 7
GND VEE
A CHANNELS IN/OUT
A3 A2 A1 A0
VCC
11 15 14 12
16
TG
TG
TG
BINARY COMMON A
TG 13
TO OUT/IN
LOGIC
S1 9 1 OF 4
LEVEL
CONVERSION DECODER
COMMON B
WITH TG 3
ENABLE OUT/IN
S0 10
TG
E 6
TG
TG
8 7 1 5 2 4
GND VEE B0 B1 B2 B3
B CHANNELS IN/OUT
BINARY TO IN/OUT
VCC 1 OF 2
C1 C0 B1 B0 A1 A0
LOGIC LEVEL DECODERS
16
CONVERSION WITH ENABLE 3 5 1 2 13 12
TG
A COMMON
14
OUT/IN
S0 11
TG
TG
S1 10 B COMMON
15 OUT/IN
TG
TG
S2 9
C COMMON
4
OUT/IN
TG
E 6
8 7
GND VEE
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Microcontroller
S2 S1 S0 k0
E Ch 0
S2S1S0
000 Ch 1 k1
001
Ch 2 k2
010
Ch 3 k3
011
COM
100 Ch 4 k4
101 k5
VCC Ch 5
110
Ch 6 k6
VEE 111
Ch 7 k7
GND CD74HC4051
Figure 20. CD74HC4051 Being Used to Help Read Button Presses on a Keypad
(1) Unit load is ΔICC limit specified in Specifications, for example, 360-mA MAX at 25°C.
100
ON RESISTANCE (Ω)
80
VCC − VEE = 4.5V
60
VCC − VEE = 6V
40
VCC − VEE = 9V
20
1 2 3 4 5 6 7 8 9
INPUT SIGNAL VOLTAGE (V)
Figure 21. Typical ON Resistance vs Input Signal Voltage
11 Layout
1W min.
W
Figure 22. Trace Example
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 24-Aug-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
5962-8775401EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8775401EA
CD54HC4053F3A
5962-8855601EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8855601EA
CD54HC4052F3A
5962-9065401MEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9065401ME
A
CD54HCT4051F3A
CD54HC4051F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4051F
CD54HC4051F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4051F3A
CD54HC4052F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4052F
CD54HC4052F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8855601EA
CD54HC4052F3A
CD54HC4053F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC4053F
CD54HC4053F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8775401EA
CD54HC4053F3A
CD54HCT4051F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9065401ME
A
CD54HCT4051F3A
CD74HC4051E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4051E
& no Sb/Br)
CD74HC4051EE4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4051E
& no Sb/Br)
CD74HC4051M ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M
& no Sb/Br)
CD74HC4051M96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HC4051M
& no Sb/Br)
CD74HC4051M96E4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M
& no Sb/Br)
CD74HC4051M96G3 ACTIVE SOIC D 16 2500 Green (RoHS CU SN Level-1-260C-UNLIM -55 to 125 HC4051M
& no Sb/Br)
CD74HC4051M96G4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
CD74HC4051ME4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M
& no Sb/Br)
CD74HC4051MT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M
& no Sb/Br)
CD74HC4051NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M
& no Sb/Br)
CD74HC4051NSRE4 ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4051M
& no Sb/Br)
CD74HC4051PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HJ4051
& no Sb/Br)
CD74HC4051PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051
& no Sb/Br)
CD74HC4051PWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051
& no Sb/Br)
CD74HC4051PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4051
& no Sb/Br)
CD74HC4052E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4052E
& no Sb/Br)
CD74HC4052M ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M
& no Sb/Br)
CD74HC4052M96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HC4052M
& no Sb/Br)
CD74HC4052M96E4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M
& no Sb/Br)
CD74HC4052M96G4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M
& no Sb/Br)
CD74HC4052MT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M
& no Sb/Br)
CD74HC4052NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M
& no Sb/Br)
CD74HC4052NSRG4 ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4052M
& no Sb/Br)
CD74HC4052PW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052
& no Sb/Br)
CD74HC4052PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HJ4052
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
CD74HC4052PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052
& no Sb/Br)
CD74HC4052PWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4052
& no Sb/Br)
CD74HC4053E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4053E
& no Sb/Br)
CD74HC4053EE4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4053E
& no Sb/Br)
CD74HC4053M ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M
& no Sb/Br)
CD74HC4053M96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HC4053M
& no Sb/Br)
CD74HC4053M96G3 ACTIVE SOIC D 16 2500 Green (RoHS CU SN Level-1-260C-UNLIM -55 to 125 HC4053M
& no Sb/Br)
CD74HC4053M96G4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M
& no Sb/Br)
CD74HC4053ME4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M
& no Sb/Br)
CD74HC4053MG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M
& no Sb/Br)
CD74HC4053MT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M
& no Sb/Br)
CD74HC4053NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4053M
& no Sb/Br)
CD74HC4053PW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053
& no Sb/Br)
CD74HC4053PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HJ4053
& no Sb/Br)
CD74HC4053PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053
& no Sb/Br)
CD74HC4053PWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4053
& no Sb/Br)
CD74HCT4051E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4051E
& no Sb/Br)
CD74HCT4051M ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
CD74HCT4051M96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M
& no Sb/Br)
CD74HCT4051M96E4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M
& no Sb/Br)
CD74HCT4051M96G4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M
& no Sb/Br)
CD74HCT4051ME4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M
& no Sb/Br)
CD74HCT4051MG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M
& no Sb/Br)
CD74HCT4051MT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M
& no Sb/Br)
CD74HCT4051MTG4 ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4051M
& no Sb/Br)
CD74HCT4052E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4052E
& no Sb/Br)
CD74HCT4052M ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M
& no Sb/Br)
CD74HCT4052M96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M
& no Sb/Br)
CD74HCT4052M96G4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M
& no Sb/Br)
CD74HCT4052ME4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M
& no Sb/Br)
CD74HCT4052MG4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M
& no Sb/Br)
CD74HCT4052MT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4052M
& no Sb/Br)
CD74HCT4053E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4053E
& no Sb/Br)
CD74HCT4053M ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M
& no Sb/Br)
CD74HCT4053M96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M
& no Sb/Br)
CD74HCT4053M96E4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M
& no Sb/Br)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
CD74HCT4053M96G4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M
& no Sb/Br)
CD74HCT4053ME4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M
& no Sb/Br)
CD74HCT4053MT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4053M
& no Sb/Br)
CD74HCT4053PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 HK4053
& no Sb/Br)
CD74HCT4053PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053
& no Sb/Br)
CD74HCT4053PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053
& no Sb/Br)
CD74HCT4053PWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HK4053
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4051, CD54HC4052, CD54HC4053, CD54HCT4051, CD74HC4051, CD74HC4052, CD74HC4053, CD74HCT4051 :
Addendum-Page 6
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2018
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2018
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2018
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4051PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC4051PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HC4051PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC4051PWT TSSOP PW 16 250 367.0 367.0 35.0
CD74HC4052M96 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4052M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC4052M96G4 SOIC D 16 2500 333.2 345.9 28.6
CD74HC4052NSR SO NS 16 2000 367.0 367.0 38.0
CD74HC4052PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HC4052PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC4052PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC4052PWT TSSOP PW 16 250 367.0 367.0 35.0
CD74HC4053M96 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4053M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HC4053M96G3 SOIC D 16 2500 364.0 364.0 27.0
CD74HC4053M96G4 SOIC D 16 2500 333.2 345.9 28.6
CD74HC4053PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HC4053PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC4053PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
CD74HC4053PWT TSSOP PW 16 250 367.0 367.0 35.0
CD74HCT4051M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT4052M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT4053M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT4053PWR TSSOP PW 16 2000 364.0 364.0 27.0
CD74HCT4053PWR TSSOP PW 16 2000 367.0 367.0 35.0
CD74HCT4053PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
CD74HCT4053PWT TSSOP PW 16 250 367.0 367.0 35.0
Pack Materials-Page 3
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