CD54HC4316, CD74HC4316,

CD74HCT4316
Data sheet acquired from Harris Semiconductor
SCHS212D
High-Speed CMOS Logic
February 1998 - Revised October 2003 Quad Analog Switch with Level Translation

Features In addition these devices contain logic-level translation

circuits that provide for analog signal switching of voltages
• Wide Analog-Input-Voltage Range between ±5V via 5V logic. Each switch is turned on by a
VCC - VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V high-level voltage on its select input (S) when the common
[ /Title Enable (E) is Low. A High E disables all switches. The digital
• Low “ON” Resistance
(CD74 inputs can swing between VCC and GND; the analog
- 45Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC = 4.5V
HC431 inputs/outputs can swing between VCC as a positive limit
- 35Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC = 6V and VEE as a negative limit. Voltage ranges are shown in
6, - 30Ω (Typ) . . . . . . . . . . . . . . . . . . . . . . . VCC - VEE = 9V Figures 2 and 3.
CD74
• Fast Switching and Propagation Delay Times Ordering Information
HCT43
16) • Low “OFF” Leakage Current
TEMP. RANGE
/Sub- • Built-In “Break-Before-Make” Switching PART NUMBER (oC) PACKAGE
ject • Logic-Level Translation to Enable 5V Logic to CD54HC4316F3A -55 to 125 16 Ld CERDIP
(High- Accommodate ±5V Analog Signals CD74HC4316E -55 to 125 16 Ld PDIP
Speed • Wide Operating Temperature Range . . . -55oC to 125oC CD74HC4316M -55 to 125 16 Ld SOIC
CMOS
• HC Types CD74HC4316MT -55 to 125 16 Ld SOIC
- 2V to 10V Operation
CD74HC4316M96 -55 to 125 16 Ld SOIC
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V CD74HC4316NSR -55 to 125 16 Ld SOP

• HCT Types CD74HC4316PW -55 to 125 16 Ld TSSOP

- Direct LSTTL Input Logic Compatibility, CD74HC4316PWR -55 to 125 16 Ld TSSOP

VIL= 0.8V (Max), VIH = 2V (Min) CD74HC4316PWT -55 to 125 16 Ld TSSOP
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HCT4316E -55 to 125 16 Ld PDIP

Description CD74HCT4316M -55 to 125 16 Ld SOIC

CD74HCT4316MT -55 to 125 16 Ld SOIC

The ’HC4316 and CD74HCT4316 contain four independent
CD74HCT4316M96 -55 to 125 16 Ld SOIC
digitally controlled analog switches that use silicon-gate
CMOS technology to achieve operating speeds similar to NOTE: When ordering, use the entire part number. The suffixes 96
LSTTL with the low power consumption of standard CMOS and R denote tape and reel. The suffix T denotes a small-quantity
integrated circuits. reel of 250.

Pinout CD54HC4316 (CERDIP)

CD74HC4316 (PDIP, SOIC, SOP, TSSOP)
CD74HCT4316 (PDIP, SOIC)
TOP VIEW
1Z 1 16 VCC

1Y 2 15 1S

2Y 3 14 4S

2Z 4 13 4Z

2S 5 12 4Y
3S 6 11 3Y

E 7 10 3Z

GND 8 9 VEE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
 CD54HC4316, CD74HC4316, CD74HCT4316

Functional Diagram
VCC

16
2
15 1Y
1S
1
1Z
5 3
2S 2Y

LOGIC
LEVEL 4
6
2Z
3S CONV.
11
AND 3Y
CONTROL
14
4S 10
3Z
12
4Y
7
E
13
4Z
8 9

GND VEE

TRUTH TABLE

INPUTS

E S SWITCH

L L OFF

L H ON

H X OFF

H= High Level Voltage

L= Low Level Voltage
X= Don’t Care

Logic Diagram

nY

TO 3 OTHER
SWITCHES VCC

VCC
LOGIC
E LEVEL nZ
CONV.
VEE

nS VEE

FIGURE 1. ONE SWITCH

2
 CD54HC4316, CD74HC4316, CD74HCT4316

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Package Thermal Impedance, θJA (see Note 1):
DC Supply Voltage, VCC - VEE . . . . . . . . . . . . . . . . . . -0.5V to 10.5V E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W
DC Supply Voltage, VEE . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to -7V M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W
DC Input Diode Current, IIK NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W
For VI < -0.5V or VI > VCC 0.5V. . . . . . . . . . . . . . . . . . . . . . . .±20mA PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W
DC Switch Diode Current, IOK Maximum Junction Temperature (Plastic Package) . . . . . . . . . 150o
For VI < VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA Maximum Storage Temperature Range . . . . . . . . . . . -65oC to 150o
DC Switch Diode Current Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . 300o
For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA SOIC - Lead Tips Only
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
Supply Voltage Range, VCC - VEE
HC, HCT Types (Figure 2) . . . . . . . . . . . . . . . . . . . . . . .2V to 10V
Supply Voltage Range, VEE
HC, HCT Types (Figure 3) . . . . . . . . . . . . . . . . . . . . . . . 0V to -6V
DC Input or Output Voltage, VI . . . . . . . . . . . . . . . . . . . GND to VCC
Analog Switch I/O Voltage, VIS . . . . . . . . . . . . . . . . . . . . . VEE (Min)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC (Max)
Input Rise and Fall Time, tr, tf
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating Area as a Function of Supply Voltage

8 8

6 6
VCC - GND HCT VCC - GND HCT
(V) 4 HC (V) 4 HC

2 2

0 0
0 2 4 6 8 10 12 0 -2 -4 -6 -8
VCC - VEE (V) VEE - GND (V)

FIGURE 2. FIGURE 3.

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 CD54HC4316, CD74HC4316, CD74HCT4316

DC Electrical Specifications
-40oC TO -55oC TO
TEST CONDITIONS 25oC 85oC 125oC

PARAMETER SYMBOL VI (V) VIS (V) VEE (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

HC TYPES

High Level Input VIH - - - 2 1.5 - - 1.5 - 1.5 - V

Voltage
4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input VIL - - - 2 - - 0.5 - 0.5 - 0.5 V

Voltage
4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

“ON” Resistance RON VIH or VCC or 0 4.5 - 45 180 - 225 - 270 Ω

IO = 1mA VIL VEE
0 6 - 35 160 - 200 - 240 Ω
(Figures 4, 5)
-4.5 4.5 - 30 135 - 170 - 205 Ω

VCC to 0 4.5 - 85 320 - 400 - 480 Ω

VEE
0 6 - 55 240 - 300 - 360 Ω

-4.5 4.5 - 35 170 - 215 - 255 Ω

Maximum “ON” ∆RON - - 0 4.5 - 10 - - - - - Ω

Resistance Between
0 6 - 8.5 - - - - - Ω
Any Two Channels
-4.5 4.5 - 5 - - - - - Ω

Switch Off Leakage IIZ VIH or VCC - 0 6 - - ±0.1 - ±1 - ±1 µA

Current VIL VEE
-5 5 - - ±0.1 - ±1 - ±1 µA

Control Input Leakage IIL VCC or - 0 6 - - ±0.1 - ±1 - ±1 µA

Current GND

Quiescent Device ICC VCC or When 0 6 - - 8 - 80 - 160 µA

Current GND VIS = VEE,
µA
VOS=VCC -5 5 - - 16 - 160 - 320
IO = 0

When
VIS = VCC,
VOS =VEE
HCT TYPES

High Level Input VIH - - - 4.5 to 2 - - 2 - 2 - V

Voltage 5.5

Low Level Input VIL - - - 4.5 to - - 0.8 - 0.8 - 0.8 V

Voltage 5.5

“ON” Resistance RON VIH or VCC or 0 4.5 - 45 180 - 225 - 270 Ω

IO = 1mA VIL VEE
-4.5 4.5 - 30 135 - 170 - 205 Ω
(Figures 4, 5)
VCC to 0 4.5 - 85 320 - 400 - 480 Ω
VEE
-4.5 4.5 - 35 170 - 215 - 255 Ω

Maximum “ON” ∆RON - - 0 4.5 - 10 - - - - - Ω

Resistance Between
-4.5 4.5 - 5 - - - - - Ω
Any Two Channels

Switch Off Leakage IIZ VIH or VCC - 0 6 - - ±0.1 - ±1 - ±1 µA

Current VIL VEE
-5 5 - - ±0.1 - ±1 - ±1 µA

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 CD54HC4316, CD74HC4316, CD74HCT4316

DC Electrical Specifications (Continued)

-40oC TO -55oC TO
TEST CONDITIONS 25oC 85oC 125oC

PARAMETER SYMBOL VI (V) VIS (V) VEE (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

Control Input Leakage II VCC or - 0 5.5 - - ±0.1 - ±1 - ±1 µA

Current GND

Quiescent Device ICC Any When 0 5.5 - - 8 - 80 - 160 µA

Current Voltage VIS = VEE,
-4.5 5.5 - - 16 - 160 - 320 µA
IO = 0 Be- VOS =
tween VCC,
VCC and When
GND VIS = VCC,
VOS = VEE

Additional Quiescent ∆ICC VCC - - 4.5 to - 100 360 - 450 - 490 µA

Device Current Per (Note 2) -2.1 5.5
Input Pin: 1 Unit Load

NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS
All 0.5
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.

Switching Specifications Input tr, tf = 6ns

-40oC TO -55oC TO
25oC 85oC 125oC
TEST VEE VCC
PARAMETER SYMBOL CONDITIONS (V) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay, tPLH, tPHL CL = 50pF 0 2 - - 60 - 75 - 90 ns
Switch In to Out 0 4.5 - - 12 - 15 - 18 ns
0 6 - - 10 - 13 - 15 ns
-4.5 4.5 - - 8 - 10 - 12 ns
Turn “ON” Time E to Out tPZH, tPZL CL = 50pF 0 2 - - 205 - 255 - 310 ns
0 4.5 - - 41 - 51 - 62 ns
0 6 - - 35 - 43 - 53 ns
-4.5 4.5 - - 37 - 47 - 56 ns
CL = 15pF - 5 - 17 - - - - - ns
Turn “ON” Time nS to Out tPZH, tPZL CL = 50pF 0 2 - - 175 - 220 - 265 ns
0 4.5 - - 35 - 44 - 53 ns
0 6 - - 30 - 37 - 45 ns
-4.5 4.5 - - 34 - 43 - 51 ns
CL = 15pF - 5 - 14 - - - - - ns
Turn “OFF” Time E to Out tPLZ, tPHZ CL = 50pF 0 2 - - 205 - 255 - 310 ns
0 4.5 - - 41 - 51 - 62 ns
0 6 - - 35 - 43 - 53 ns
-4.5 4.5 - - 37 - 47 - 56 ns
CL = 15pF - 5 - 17 - - - - - ns

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 CD54HC4316, CD74HC4316, CD74HCT4316

Switching Specifications Input tr, tf = 6ns (Continued)

-40oC TO -55oC TO
25oC 85oC 125oC
TEST VEE VCC
PARAMETER SYMBOL CONDITIONS (V) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Turn “OFF” Time nS to Out tPLZ, tPHZ CL = 50pF 0 2 - - 175 - 220 - 265 ns
0 4.5 - - 35 - 44 - 53 ns
0 6 - - 30 - 37 - 45 ns
-4.5 4.5 - - 34 - 43 - 51 ns
CL = 15pF - 5 - 14 - - - - - ns
Input (Control) Capacitance CI - - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance CPD - - 5 - 42 - - - - - pF
(Notes 3, 4)
HCT TYPES
Propagation Delay, tPLH, tPHL CL = 50pF 0 4.5 - - 12 - 15 - 18 ns
Switch In to Switch Out -4.5 4.5 - - 8 - 10 - 12 ns
Turn “ON” Time E to Out tPZH CL = 50pF 0 4.5 - - 44 - 55 - 66 ns
-4.5 4.5 - - 42 - 53 - 63 ns
CL = 15pF - 5 - 18 - - - - - ns
tPZL CL = 50pF 0 4.5 - - 56 - 70 - 85 ns
-4.5 4.5 - - 42 - 53 - 63 ns
CL = 15pF - 5 - 24 - - - - - ns
Turn “ON” Time nS to Out tPZH CL = 50pF 0 4.5 - - 40 - 53 - 60 ns
-4.5 4.5 - - 34 - 43 - 51 ns
CL = 15pF - 5 - 17 - - - - - ns
tPZL CL = 50pF 0 4.5 - - 50 - 63 - 75 ns
-4.5 4.5 - - 34 - 43 - 51 ns
CL = 15pF - 5 - 18 - - - - - ns
Turn “OFF” Time E to Out tPLZ CL = 50pF 0 4.5 - - 50 - 63 - 75 ns
-4.5 4.5 - - 46 - 58 - 69 ns
tPLZ, tPHZ CL = 15pF - 5 - 21 - - - - - ns
Turn “OFF” Time nS to Out tPHZ CL = 50pF 0 4.5 - - 44 - 55 - 66 ns
-4.5 4.5 - - 40 - 50 - 60 ns
tPLZ, tPHZ CL = 15pF - 5 - 18 - - - - - ns
Input (Control) Capacitance CI - - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance CPD - - 5 - 47 - - - - - pF
(Notes 3, 4)
NOTES:
3. CPD is used to determine the dynamic power consumption, per package.
4. PD = CPD VCC2 fi + Σ (CL + CS) VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, CS = switch
capacitance, VCC = supply voltage.

Analog Channel Specifications TA = 25oC

TEST
PARAMETER CONDITIONS VCC (V) HC4316 CD74HCT4316 UNITS

Switch Frequency Response Bandwidth at -3dB Figure 9 (Notes 5, 6) 4.5 >200 >200 MHz
(Figure 6)

Crosstalk Between Any Two Switches (Figure 7) Figure 8 (Notes 6, 7) 4.5 TBE TBE dB

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 CD54HC4316, CD74HC4316, CD74HCT4316

Analog Channel Specifications TA = 25oC (Continued)

TEST
PARAMETER CONDITIONS VCC (V) HC4316 CD74HCT4316 UNITS

Total Harmonic Distortion 1kHz, VIS = 4VP-P 4.5 0.078 0.078 %

(Figure 10)

1kHz, VIS = 8VP-P 9 0.018 0.018 %

(Figure 10)

Control to Switch Feedthrough Noise Figure 11 4.5 TBE TBE mV

9 TBE TBE mV

Switch “OFF” Signal Feedthrough (Figure 7) Figure 12 (Notes 6, 7) 4.5 -62 -62 dB

Switch Input Capacitance, CS - - 5 5 pF

NOTES:
5. Adjust input level for 0dBm at output, f = 1MHz.
6. VIS is centered at VCC/2.
7. Adjust input for 0dBm at VIS.

Typical Performance Curves

110
60
100
50
“ON” RESISTANCE, RON (Ω)
“ON” RESISTANCE, RON (Ω)

90 45
VCC = 4.5V, VEE = 0V
80 40
70 35 VCC = 4.5V, VEE = 4.5V
60 30
50 25
40 VCC = 6V, VEE = 0V 20
30 15
20 10

10 5
0
0 1 2 3 4 4.5 5 6 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5
INPUT SIGNAL VOLTAGE, VIS (V) INPUT SIGNAL VOLTAGE, VIS (V)

FIGURE 4. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL FIGURE 5. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL
VOLTAGE VOLTAGE

0
SWITCH OFF SIGNAL FEEDTHROUGH, dB

0
CHANNEL ON BANDWIDTH, dB

CL = 10pF
-20 VCC = 4.5V
CL = 10pF RL = 50Ω
-1
VCC = 9V TA = 25oC
CROSSTALK, dB

RL = 50Ω PIN 4 TO 3
-40
CL = 10pF TA = 25oC
-2 VCC = 4.5V PIN 4 TO 3
RL = 50Ω
TA = 25oC -60 CL = 10pF
PIN 4 TO 3 VCC = 9V
-3 RL = 50Ω
TA = 25oC
-80 PIN 4 TO 3
-4

-100
10K 100K 1M 10M 100M 10K 100K 1M 10M 100M
FREQUENCY (f), Hz FREQUENCY (f), Hz

FIGURE 6. SWITCH FREQUENCY RESPONSE FIGURE 7. SWITCH-OFF SIGNAL FEEDTHROUGH AND

CROSSTALK vs FREQUENCY

7
 CD54HC4316, CD74HC4316, CD74HCT4316

Analog Test Circuits

VIS VCC
VCC
0.1µF
SWITCH
VIS VOS1 R VOS2
ON
SWITCH
R
R C ON

VCC/2 R C
VCC/2 dB
fIS = 1MHz SINEWAVE METER
VCC/2
R = 50Ω
C = 10pF

FIGURE 8. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT

VCC
VCC
SINE VIS
0.1µF VOS WAVE 10µF VI = VIH
SWITCH
SWITCH VIS
VIS ON
ON VOS
10kΩ 50pF
50Ω 10pF
DISTORTION
dB METER
METER VCC/2
VCC/2
fIS = 1kHz TO 10kHz

FIGURE 9. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 10. TOTAL HARMONIC DISTORTION TEST CIRCUIT

fIS ≥ 1MHz SINEWAVE

VCC E VCC R = 50Ω
VC = VIL
VP-P C = 10pF
VOS 0.1µF VOS
600Ω SWITCH
ALTERNATING SWITCH
VIS ON
ON AND OFF VOS
tr, tf ≤ 6ns 600Ω R
VCC/2 R C
fCONT = 1MHz 50pF
50% DUTY dB
CYCLE SCOPE METER
VCC/2 VCC/2 VCC/2

FIGURE 11. CONTROL-TO-SWITCH FEEDTHROUGH NOISE FIGURE 12. SWITCH OFF SIGNAL FEEDTHROUGH
TEST CIRCUIT

8
 CD54HC4316, CD74HC4316, CD74HCT4316

Test Circuits and Waveforms

6ns 6ns VCC (HC)

90% 3V (HCT)
50%
10%
VCC E GND
tPLZ tPZL
tf = 6ns tr = 6ns
90% OUTPUT LOW
TO OFF 50%
SWITCH INPUT 50%
10%
10%
tPHZ tPZH
90%
tPLH tPHL OUTPUT HIGH 50%
VEE TO OFF

SWITCH OUTPUT 50% SWITCH OUTPUTS OUTPUTS

ON DISABLED ENABLED
SWITCH OFF SWITCH ON

FIGURE 13. SWITCH PROPAGATION DELAY TIMES FIGURE 14. SWITCH TURN-ON AND TURN-OFF
PROPAGATION DELAY TIMES WAVEFORMS

9
10
 PACKAGE OPTION ADDENDUM

www.ti.com 29-Jul-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CD54HC4316F3A ACTIVE CDIP J 16 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HC4316F3A Samples
& Green
CD74HC4316E LIFEBUY PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC4316E
CD74HC4316M LIFEBUY SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M
CD74HC4316M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M Samples

CD74HC4316ME4 LIFEBUY SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M
CD74HC4316MG4 LIFEBUY SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M
CD74HC4316NSR LIFEBUY SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC4316M
CD74HC4316PW LIFEBUY TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4316
CD74HC4316PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4316 Samples

CD74HCT4316E LIFEBUY PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT4316E
CD74HCT4316M LIFEBUY SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4316M
CD74HCT4316M96 LIFEBUY SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4316M

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 29-Jul-2023

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC4316, CD74HC4316 :

• Catalog : CD74HC4316
• Military : CD54HC4316

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC4316M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HC4316NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD74HC4316PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD74HCT4316M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4316M96 SOIC D 16 2500 340.5 336.1 32.0
CD74HC4316NSR SO NS 16 2000 356.0 356.0 35.0
CD74HC4316PWR TSSOP PW 16 2000 356.0 356.0 35.0
CD74HCT4316M96 SOIC D 16 2500 340.5 336.1 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC4316E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4316E N PDIP 16 25 506 13.97 11230 4.32
CD74HC4316M D SOIC 16 40 507 8 3940 4.32
CD74HC4316ME4 D SOIC 16 40 507 8 3940 4.32
CD74HC4316MG4 D SOIC 16 40 507 8 3940 4.32
CD74HC4316PW PW TSSOP 16 90 530 10.2 3600 3.5
CD74HCT4316E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4316E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT4316M D SOIC 16 40 507 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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