CD54HC125, CD74HC125,

CD54HCT125, CD74HCT125
Data sheet acquired from Harris Semiconductor
SCHS143C
High-Speed CMOS Logic
November 1997 - Revised August 2003 Quad Buffer, Three-State

Features Description
• Three-State Outputs The ’HC125 and ’HCT125 contain 4 independent three-state
• Separate Output Enable Inputs buffers, each having its own output enable input, which when
[ /Title “HIGH” puts the output in the high impedance state.
(CD74 • Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Ordering Information
HC125
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
,
• Wide Operating Temperature Range . . . -55oC to 125oC TEMP. RANGE
CD74 PART NUMBER (oC) PACKAGE
• Balanced Propagation Delay and Transition Times
HCT12
• Significant Power Reduction Compared to LSTTL CD54HC125F3A -55 to 125 14 Ld CERDIP
5) Logic ICs
CD54HCT125F3A -55 to 125 14 Ld CERDIP
/Sub- • HC Types
ject - 2V to 6V Operation CD74HC125E -55 to 125 14 Ld PDIP
(High - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
CD74HC125M -55 to 125 14 Ld SOIC
at VCC = 5V
Speed
• HCT Types CD74HC125MT -55 to 125 14 Ld SOIC
CMOS
- 4.5V to 5.5V Operation
Logic CD74HC125M96 -55 to 125 14 Ld SOIC
- Direct LSTTL Input Logic Compatibility,
Quad VIL= 0.8V (Max), VIH = 2V (Min) CD74HCT125E -55 to 125 14 Ld PDIP
Buffer, - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HCT125M -55 to 125 14 Ld SOIC
Three-
CD74HCT125MT -55 to 125 14 Ld SOIC
State)
CD74HCT125M96 -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.

Pinout
CD54HC125, CD54HCT125
(CERDIP)
CD74HC125, CD74HCT125
(PDIP, SOIC)
TOP VIEW

1OE 1 14 VCC

1A 2 13 4OE

1Y 3 12 4A

2OE 4 11 4Y

2A 5 10 3OE

2Y 6 9 3A

GND 7 8 3Y

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125

Functional Diagram

1
1OE

2 3 1Y
1A

4
2OE

5 6
2A 2Y

10
3OE
9 8
3A 3Y

13
4OE
12 11
4A 4Y
GND = 7
VCC = 14

TRUTH TABLE

INPUTS OUTPUTS

nA nOE nY

H L H

L L L

X H Z

H= High Voltage Level

L= Low Voltage Level
X= Don’t Care
Z= High Impedance, OFF State

Logic Diagram

P
nA nY
n

nOE

2
 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W)
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86
DC Output Diode Current, IOK Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Drain Current, per Output, IO Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . ±35mA (SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA

Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

HC TYPES

High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V

Voltage
4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V

Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V

Voltage VIL
CMOS Loads -0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V

Voltage
-7.8 6 5.48 - - 5.34 - 5.2 - V
TTL Loads

Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V

Voltage VIL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V

Voltage
7.8 6 - - 0.26 - 0.33 - 0.4 V
TTL Loads

Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA

Current GND

3
 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA

Current GND

Three-State Leakage IOZ VIL or - 6 - - ±0.5 - ±5 - ±10 µA

Current VIH

HCT TYPES

High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V

Voltage 5.5

Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V

Voltage 5.5

High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage VIL
CMOS Loads

High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V

Voltage
TTL Loads

Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage VIL
CMOS Loads

Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V

Voltage
TTL Loads

Input Leakage II VCC to 0 5.5 - - ±0.1 - ±1 - ±1 µA

Current GND

Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA

Current GND

Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA

Device Current Per (Note 2) -2.1 5.5
Input Pin: 1 Unit Load

Three-State Leakage IOZ VIL or - 5.5 - - ±0.5 - ±5 - ±10 µA

Current VIH

NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS

nA, nOE 1

NOTE: Unit Load is ∆ICC limit specified in DC Electrical

Specifications table, e.g., 360µA max at 25oC.

4
 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125

Switching Specifications Input tr, tf = 6ns

25oC -40oC TO 85oC -55oC TO 125oC

TEST
PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS

HC TYPES
Propagation Delay Time tPLH, tPHL CL = 50pF 2 - 100 125 150 ns
nA to nY
4.5 - 20 25 30 ns

CL = 15pF 5 8 - - - ns

CL = 50pF 6 - 17 21 26 ns

Enable Delay Time tPZL, tPZH CL = 50pF 2 - 125 155 190 ns

4.5 - 25 31 38 ns

CL = 15pF 5 10 - - - ns

CL = 50pF 6 - 21 26 32 ns

Disable Delay Time tPLZ, tPHZ CL = 50pF 2 - 125 155 190 ns

CL = 50pF 4.5 - 25 31 38 ns

CL = 15pF 5 10 - - - ns

CL = 50pF 6 - 21 26 32 ns

Output Transition Time tTLH, tTHL CL = 50pF 2 - 60 75 90 ns

4.5 - 12 15 18 ns

6 - 10 13 15 ns

Input Capacitance CI - - - 10 10 10 pF

Three-State Output CO - - - 20 20 20 pF
Capacitance

Power Dissipation CPD - 5 29 - - - pF

Capacitance
(Notes 3, 4)

HCT TYPES
Propagation Delay Time tPLH, tPHL CL = 50pF 4.5 - 25 31 38 ns
nA to nY
CL = 15pF 5 10 - - - ns

Output Enable Time tPZL, tPZH CL = 50pF 4.5 - 25 31 38 ns

CL = 15pF 5 10 - - - ns

Output Disabling Time tPLZ, tPHZ CL = 50pF 4.5 - 28 35 42 ns

CL = 15pF 5 11 - - - ns

Output Transition Times tTLH, tTHL CL = 50pF 4.5 - 12 15 18 ns

Input Capacitance CI - - - 10 10 10 pF

Three-State Output CO - - - 20 20 20 pF
Capacitance

Power Dissipation CPD - 5 34 - - - pF

Capacitance
(Notes 3, 4)

NOTES:
3. CPD is used to determine the dynamic power consumption, per channel.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

5
 CD54HC125, CD74HC125, CD54HCT125, CD74HCT125

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

6ns 6ns tr 6ns tf 6ns

OUTPUT VCC OUTPUT 3V
90% 2.7
DISABLE 50% DISABLE 1.3
10% 0.3
GND GND
tPLZ tPZL tPLZ tPZL

OUTPUT LOW OUTPUT LOW

TO OFF 50% TO OFF
10% 10% 1.3V

tPHZ tPZH tPHZ

tPZH
90% 90%
OUTPUT HIGH 50% OUTPUT HIGH
TO OFF TO OFF 1.3V

OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS

ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED

FIGURE 3. HC THREE-STATE PROPAGATION DELAY FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM WAVEFORM

OTHER OUTPUT
INPUTS IC WITH RL = 1kΩ
TIED HIGH THREE- VCC FOR tPLZ AND tPZL
OR LOW STATE CL GND FOR tPHZ AND tPZH
OUTPUT 50pF
OUTPUT
DISABLE

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

6
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

CD54HC125F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC125F

CD54HC125F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8772101CA
CD54HC125F3A
CD54HCT125F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HCT125F3A

CD74HC125E ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC125E
(RoHS)
CD74HC125EE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC125E
(RoHS)
CD74HC125M ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC125M
& no Sb/Br)
CD74HC125M96 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC125M
& no Sb/Br)
CD74HC125M96E4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC125M
& no Sb/Br)
CD74HC125ME4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC125M
& no Sb/Br)
CD74HC125MG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC125M
& no Sb/Br)
CD74HC125MT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC125M
& no Sb/Br)
CD74HCT125E ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT125E
(RoHS)
CD74HCT125M ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT125M
& no Sb/Br)
CD74HCT125M96 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT125M
& no Sb/Br)
CD74HCT125M96E4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT125M
& no Sb/Br)
CD74HCT125M96G4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT125M
& no Sb/Br)
CD74HCT125MT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT125M
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC125, CD54HCT125, CD74HC125, CD74HCT125 :

• Catalog: CD74HC125, CD74HCT125

• Automotive: CD74HC125-Q1, CD74HC125-Q1

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2014

• Military: CD54HC125, CD54HCT125

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC125M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HC125MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HCT125M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HCT125MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC125M96 SOIC D 14 2500 367.0 367.0 38.0
CD74HC125MT SOIC D 14 250 367.0 367.0 38.0
CD74HCT125M96 SOIC D 14 2500 367.0 367.0 38.0
CD74HCT125MT SOIC D 14 250 367.0 367.0 38.0

Pack Materials-Page 2
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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