CD74HC173,

Data sheet acquired from Harris Semiconductor

SCHS158
CD74HCT173
High Speed CMOS Logic
February 1998 Quad D-Type Flip-Flop, Three-State

Features Description
• Three-State Buffered Outputs The Harris CD74HC173 and CD74HCT173 high speed
• Gated Input and Output Enables three-state quad D-type flip-flops are fabricated with silicon
[ /Title gate CMOS technology. They possess the low power con-
(CD74H • Fanout (Over Temperature Range) sumption of standard CMOS Integrated circuits, and can
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads operate at speeds comparable to the equivalent low power
C173, - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Schottky devices. The buffered outputs can drive 15 LSTTL
CD74H • Wide Operating Temperature Range . . . -55oC to 125oC loads. The large output drive capability and three-state fea-
CT173) • Balanced Propagation Delay and Transition Times ture make these parts ideally suited for interfacing with bus
/Subject lines in bus oriented systems.
• Significant Power Reduction Compared to LSTTL
(High Logic ICs The four D-type flip-flops operate synchronously from a com-
Speed • HC Types mon clock. The outputs are in the three-state mode when
CMOS - 2V to 6V Operation either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their
Logic - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V present states without having to disrupt the clock If either of
Quad D- the 2 input ENABLES are taken to a logic “1” level, the Q
• HCT Types outputs are fed back to the inputs, forcing the flip-flops to
Type - 4.5V to 5.5V Operation remain in the same state. Reset is enabled by taking the
- Direct LSTTL Input Logic Compatibility, MASTER RESET (MR) input to a logic “1” level. The data
VIL= 0.8V (Max), VIH = 2V (Min) outputs change state on the positive going edge of the clock.
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The CD74HCT173 logic family is functionally, as well as pin
compatible with the standard 74LS logic family.
Pinout Ordering Information
CD74HC173, CD74HC173
(PDIP, SOIC) TEMP. RANGE PKG.
TOP VIEW PART NUMBER (oC) PACKAGE NO.

OE 1 16 VCC CD74HC173E -55 to 125 16 Ld PDIP E16.3

OE2 2 15 MR CD74HCT173E -55 to 125 16 Ld PDIP E16.3

Q0 3 14 D0
CD74HC173M -55 to 125 16 Ld SOIC M16.15
Q1 4 13 D1
CD74HCT173M -55 to 125 16 Ld SOIC M16.15
Q2 5 12 D2
Q3 6 11 D3 NOTES:
CP 7 10 E2 1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
GND 8 9 E1
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 1641.1
Copyright © Harris Corporation 1998
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 CD74HC173, CD74HCT173

Functional Diagram
E1

E2
10 9
14
D0 3
13 Q0
D1 4
12 Q1
D2 5
11 Q2
D3 6
7 Q3
CP

15 1 2
MR

OE1

OE2

TRUTH TABLE

INPUTS

DATA ENABLE DATA OUTPUT

MR CP E1 E2 D Qn

H X X X X L

L L X X X Q0

L ↑ H X X Q0

L ↑ X H X Q0

L ↑ L L L L

L ↑ L L H H

NOTE:
When either OE1 or OE2 (or both) is (are) high the output is disabled
to the high-impedance state, however, sequential operation of the
flip-flops is not affected.
H = High Voltage Level
L = Low Voltage Level
X = Irrelevant
↑ = Transition from Low to High Level
Q0 = Level Before the Indicated Steady-State Input Conditions Were
Established

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 CD74HC173, CD74HCT173

Logic Diagram

9
E1

10
E2
VCC
D Q

14 P
D0
3
Q0
7
CP CP Q
N
R
15
MR

1
OE1

2
OE2

13 4
D1 Q1
12 3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT 5
D2 Q2
IN DASHED ENCLOSURE
11 6
D3 Q3

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 CD74HC173, CD74HCT173

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3) θJA (oC/W)
DC Input Diode Current, IIK PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
DC Output Diode Current, IOK Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Output Source or Sink Current per Output Pin, IO Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only)
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA

Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

HC TYPES

High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V

Voltage
4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V

Voltage
4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage VIL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V

Voltage
-7.8 6 5.48 - - 5.34 - 5.2 - V
TTL Loads

Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V

Voltage VIL
CMOS Loads 0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V

Voltage
7.8 6 - - 0.26 - 0.33 - 0.4 V
TTL Loads

Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA

Current GND

Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA

Current GND

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 CD74HC173, CD74HCT173

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

Three-State Leakage IOZ VIL or - 6 - - ±0.5 - ±0.5 - ±10 µA

Current VIH

HCT TYPES

High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V

Voltage 5.5

Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V

Voltage 5.5

High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage VIL
CMOS Loads

High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V

Voltage
TTL Loads

Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage VIL
CMOS Loads

Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V

Voltage
TTL Loads

Input Leakage II VCC to 0 5.5 - - ±0.1 - ±1 - ±1 µA

Current GND

Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA

Current GND

Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA

Device Current Per -2.1 5.5
Input Pin: 1 Unit Load
(Note 4)

Three-State Leakage IOZ VIL or - 5.5 - - ±0.5 - ±5.0 - ±10 µA

Current VIH

NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS

D0-D3 0.15

E1 and E2 0.15

CP 0.25

MR 0.2

OE1 and OE2 0.5

NOTE: Unit Load is ∆ICC limit specified in DC Electrical

Specifications table, e.g., 360µA max at 25oC.

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 CD74HC173, CD74HCT173

Switching Specifications Input tr, tf = 6ns

25oC -40oC TO 85oC -55oC TO 125oC

TEST
PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS
HC TYPES
Propagation Delay, Clock to tPLH, tPHL CL = 50pF 2 - 200 250 300 ns
Output
4.5 - 40 50 60 ns
CL = 15pF 5 17 - - - ns
CL = 50pF 6 - 34 43 51 ns
Propagation Delay, MR to tPHL CL = 50pF 2 - 175 220 265 ns
Output
4.5 - 35 44 53 ns
CL = 15pF 5 12 - - - ns
CL = 50pF 6 - 30 37 45 ns
Propagation Delay Output tPLZ, tPHZ CL = 50pF 2 150 190 225 ns
Enable to Q (Figure 6) tPZL, tPZH
CL = 50pF 4.5 30 38 45 ns
CL = 15pF 5 12 - - - ns
CL = 50pF 6 26 33 38 ns
Output Transition Times tTLH, tTHL CL = 50pF 2 - 60 75 90 ns
4.5 - 12 15 18 ns
6 - 10 13 15 ns
Maximum Clock Frequency fMAX CL = 15pF 5 60 - - - MHz
Input Capacitance CIN - - - 10 10 10 pF
Three-State Output CO - - - 10 10 10 pF
Capacitance
Power Dissipation CPD - 5 29 - - - pF
Capacitance
(Notes 5, 6)
HCT TYPES
Propagation Delay, Clock to tPLH, tPHL CL = 50pF 4.5 - 40 50 60 ns
Output
CL = 15pF 5 17 - - - ns
Propagation Delay, MR to tPHL CL = 50pF 4.5 - 44 55 66 ns
Output
CL = 15pF 5 18 - - - ns
Propagation Delay Output tPZL, tPZH CL = 50pF 2 150 190 225 ns
Enable to Q (Figure 6)
CL = 50pF 4.5 30 38 45 ns
CL = 15pF 5 14 - - - ns
CL = 50pF 6 26 33 38 ns
Output Transition Times tTLH, tTHL CL = 50pF 4.5 - 15 19 22 ns
Maximum Clock Frequency fMAX CL = 15pF 5 60 - - - MHz
Input Capacitance CIN - - - 10 10 10 pF
Power Dissipation CPD - 5 34 - - - pF
Capacitance
(Notes 5, 6)
NOTES:
5. CPD is used to determine the dynamic power consumption, per package.
6. PD = VCC2 fi + ∑ (CL VCC2 + fO) where fi = Input Frequency, fO = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

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 CD74HC173, CD74HCT173

Prerequisite For Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS

HC TYPES
Maximum Clock Frequency fMAX 2 6 - 5 - 4 - MHz

4.5 30 - 24 - 20 - MHz

6 35 - 28 - 24 - MHz

MR Pulse Width tw 2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns

6 14 - 17 - 20 - ns

Clock Pulse Width tw 2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns

6 14 - 17 - 20 - ns

Set-up Time, Data to Clock tSU 2 60 - 75 - 90 - ns

and E to Clock
4.5 12 - 15 - 18 - ns

6 10 - 13 - 15 - ns

Hold Time, Data to Clock tH 2 3 - 3 - 3 - ns

4.5 3 - 3 - 3 - ns

6 3 - 3 - 3 - ns

Hold Time, E to Clock tH 2 0 - 0 - 0 - ns

4.5 0 - 0 - 0 - ns

6 0 - 0 - 0 - ns

Removal Time, MR to Clock tREM 2 60 - 75 - 90 - ns

4.5 12 - 15 - 18 - ns

6 10 - 13 - 15 - ns

HCT TYPES
Maximum Clock Frequency fMAX 4.5 20 - 16 - 13 - MHz

MR Pulse Width tw 4.5 15 - 19 - 22 - ns

Clock Pulse Width tw 4.5 25 - 31 - 38 - ns

Set-up Time, E to Clock tSU 4.5 12 - 15 - 18 - ns

Set-up Time, Data to Clock tSU 4.5 18 - 23 - 27 - ns

Hold Time, Data to Clock tH 4.5 0 - 0 - 0 - ns

Hold Time, E to Clock tH 4.5 0 - 0 - 0 - ns

Removal Time, MR to Clock tREM 4.5 12 - 15 - 18 - ns

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 CD74HC173, CD74HCT173

Test Circuits and Waveforms

I
I tWL + tWH =
tWL + tWH = trCL = 6ns fCL
trCL tfCL fCL tfCL = 6ns

VCC 3V
90% 2.7V
CLOCK 50% CLOCK 1.3V
50% 50% 1.3V 1.3V
10% 10% GND 0.3V 0.3V GND

tWL tWH tWL tWH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%. accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH PULSE WIDTH

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA- FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

trCL tfCL trCL tfCL

VCC 3V
90% CLOCK 2.7V
CLOCK 50% 1.3V
INPUT 10% INPUT 0.3V
GND GND

tH(H) tH(L) tH(H) tH(L)

VCC 3V
DATA DATA
50% INPUT 1.3V 1.3V 1.3V
INPUT
GND GND
tSU(H) tSU(L) tSU(H) tSU(L)

tTLH tTHL tTLH tTHL

90% 90%
90% 90%
50% 1.3V
OUTPUT OUTPUT 1.3V
10% 10%
tPLH tPHL tPLH tPHL

tREM tREM
VCC 3V
SET, RESET 50% SET, RESET 1.3V
OR PRESET OR PRESET
GND GND

IC IC
CL CL
50pF 50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS

8
Test Circuits and Waveforms (Continued)

6ns 6ns tr 6ns tf 6ns

OUTPUT VCC OUTPUT 3V
90% 2.7
DISABLE 50% DISABLE 1.3
10% 0.3
GND GND
tPLZ tPZL tPLZ tPZL

OUTPUT LOW OUTPUT LOW

TO OFF 50% TO OFF
10% 10% 1.3V

tPHZ tPZH tPHZ

tPZH
90% 90%
OUTPUT HIGH 50% OUTPUT HIGH
TO OFF TO OFF 1.3V

OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS

ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED

FIGURE 7. HC THREE-STATE PROPAGATION DELAY FIGURE 8. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM WAVEFORM

OTHER OUTPUT
INPUTS IC WITH RL = 1kΩ
TIED HIGH THREE- VCC FOR tPLZ AND tPZL
OR LOW STATE CL GND FOR tPHZ AND tPZH
OUTPUT 50pF
OUTPUT
DISABLE

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

9
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