CD74HC283,

CD74HCT283
Data sheet acquired from Harris Semiconductor
SCHS176 High Speed CMOS Logic
November 1997 4-Bit Binary Full Adder with Fast Carry

Features Description
• Adds Two Binary Numbers The Harris CD74HC283 and CD74HCT283 binary full
• Full Internal Lookahead adders that add two 4-bit binary numbers and generate a
[ /Title carry-out bit if the sum exceeds 15.
(CD74 • Fast Ripple Carry for Economical Expansion
Because of the symmetry of the add function, this device
HC283 • Operates with Both Positive and Negative Logic can be used with either all active-high operands (positive
, • Fanout (Over Temperature Range) logic) or with all active-low operands (negative logic). When
CD74 - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads using positive logic the carry-in input must be tied low if there
HCT28 is no carry-in.
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
3) • Wide Operating Temperature Range . . . -55oC to 125oC Ordering Information
/Sub-
• Balanced Propagation Delay and Transition Times PKG.
ject
• Significant Power Reduction Compared to LSTTL PART NUMBER TEMP. RANGE (oC) PACKAGE NO.
(High
Logic ICs CD74HC283E -55 to 125 16 Ld PDIP E16.3
Speed
CMOS • HC Types CD74HCT283E -55 to 125 16 Ld PDIP E16.3
Logic - 2V to 6V Operation
CD74HC283M -55 to 125 16 Ld SOIC M16.15
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
4-Bit at VCC = 5V CD74HCT283M -55 to 125 16 Ld SOIC M16.15
Binary
• HCT Types NOTES:
Full
- 4.5V to 5.5V Operation 1. When ordering, use the entire part number. Add the suffix 96 to
Adder - Direct LSTTL Input Logic Compatibility, obtain the variant in the tape and reel.
VIL= 0.8V (Max), VIH = 2V (Min) 2. Wafer and die is available which meets all electrical
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH specifications. Please contact your local sales office or Harris
customer service for ordering information.

Pinout Functional Diagram

CD74HC283, CD74HCT283
(PDIP, SOIC) 5 4
A0 S0
TOP VIEW
6
B0
3 1
S1 1 16 VCC A1 S1
B1 2 15 B2 2
B1
A1 3 14 A2
14 13
A2 S2
S0 4 13 S2
15
A0 5 12 A3 B2
B0 6 11 B3 12 10
A3 S3
CIN 7 10 S3
11
B3
GND 8 9 COUT
7 9
CIN COUT
GND = 8
VCC = 16

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 1848.1
Copyright © Harris Corporation 1997
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 CD74HC283, CD74HCT283

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3) θJA (oC/W)
DC Input Diode Current, IIK PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
DC Output Diode Current, IOK Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Drain Current, per Output, IO Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output - - - - - - - - - V
Voltage
-4 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output - - - - - - - - - V
Voltage
4 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA
Current GND

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 CD74HC283, CD74HCT283

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HCT Types
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIL or VIH - 4.5 4.4 - - 4.4 - 4.4 - V
Voltage
CMOS Loads
High Level Output VOH VIL or VIH - 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or VIL - 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage
CMOS Loads
Low Level Output VOL VIH or VIL - 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC to - 5.5 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or - 5.5 - - 8 - 80 - 160 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per -2.1 5.5
Input Pin: 1 Unit Load
(Note 4)
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS

CIN 1.5

B1, A1, A0 1

B0 0.4

B3, A3, A2, B2 0.5

NOTE: Unit Load is ∆ICC limit specified in DC Electrical

Specifications table, e.g., 360µA max at 25oC.

Switching Specifications Input tr, tf = 6ns

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay tPLH, tPHL CL = 50pF 2 - - 160 - 200 - 240 ns
CIN to S0 4.5 - - 32 - 40 - 48 ns
CL = 15pF 5 - 13 - - - - - ns
CL = 50pF 6 - - 27 - 34 - 41 ns

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 CD74HC283, CD74HCT283

Switching Specifications Input tr, tf = 6ns (Continued)

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
CIN to S1 tPLH, tPHL CL = 50pF 2 - - 180 - 225 - 270 ns
4.5 - - 36 - 45 - 54 ns
CL = 15pF 5 - 15 - - - - - ns
CL = 50pF 6 - - 31 - 38 - 46 ns
CIN to S2, CIN to COUT tPLH, tPHL CL = 50pF 2 - - 195 - 245 - 295 ns
4.5 - - 39 - 49 - 59 ns
CL = 15pF 5 - 16 - - - - - ns
CL = 50pF 6 - - 33 - 42 - 50 ns
CIN to S3 tPLH, tPHL CL = 50pF 2 - - 230 - 290 - 345 ns
4.5 - - 46 - 58 - 69 ns
CL = 15pF 5 - 19 - - - - - ns
CL = 50pF 6 - - 39 - 49 - 59 ns
An, Bn to COUT tPLH, tPHL CL = 50pF 2 - - 195 - 245 - 295 ns
4.5 - - 39 - 49 - 59 ns
CL = 15pF 5 - 16 - - - - - ns
CL = 50pF 6 - - 33 - 42 - 50 ns
An, Bn to Sn tPLH, tPHL CL = 50pF 2 - - 210 - 265 - 315 ns
4.5 - - 42 - 53 - 63 ns
CL = 15pF 5 - 18 - - - - - ns
CL = 50pF 6 - - 36 - 45 - 54 ns
Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF
Power Dissipation CPD - 5 - 70 - - - - - pF
Capacitance, (Notes 5, 6)
HCT TYPES
Propagation Delay
CIN to S0 tPLH, tPHL CL = 15pF 5 - 13 - - - - - ns
CL = 50pF 4.5 - - 31 - 39 - 47 ns
CIN to S1 tPLH, tPHL CL = 15pF 5 - 18 - - - - - ns
CL = 50pF 4.5 - 43 - 54 - 65 ns
CIN to S2, CIN to COUT tPLH, tPHL CL = 15pF 5 - 19 - - - - - ns
CL = 50pF 4.5 - 46 - 58 - 69 ns
CIN to S3 tPLH, tPHL CL = 15pF 5 - 22 - - - - - ns
CL = 50pF 4.5 - 53 - 66 - 80 ns
An, Bn to COUT tPLH, tPHL CL = 15pF 5 - 20 - - - - - ns
CL = 50pF 4.5 - 48 - 60 - 72 ns
An, Bn to Sn tPLH, tPHL CL = 15pF 5 - 21 - - - - - ns
CL = 50pF 4.5 - 49 - 61 - 74 ns
Output Transition Time tTLH, tTHL CL = 50pF 4.5 - 15 - 19 - 22 ns

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 CD74HC283, CD74HCT283

Switching Specifications Input tr, tf = 6ns (Continued)

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Input Capacitance CIN - - - - 10 - 10 - 10 pF
Power Dissipation CPD - 5 - 82 - - - - - pF
Capacitance, (Notes 5, 6)
NOTES:
5. CPD is used to determine the dynamic power consumption, per package.
6. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA- FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

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