MICROPROCESSORS

Useful for IES, GATE & IAS Exams

By
Ram Niwas (IES)
 4
Memory Mapping

4.1 Introduction
Memory is an integral part of a microcomputer system. It is used to store instructions and
data in binary format for the microprocessor. Memory can be of two types i.e. prime (or
main) memory and storage memory. Read/Write Memory (R/W M) and Read Only Memory
(ROM) are examples of main or prime memory and magnetic tapes or hard disk is example
of storage or secondary memory.
58 By Dr. Ram Niwas, IES Microprocessor 8085
The R/W memory consists of registers which are made of group of flip-flops that store bits
of information. These flip-flops are called memory cells. The number of bits stored in a
register is called a memory word. In a memory chip, all registers are arranged in a sequence
and identified by binary numbers called memory addresses. To communicate with memory.
the MPU should be able to
(i) select the chip,
(ii) identify the register, and
(iii) read from or write into the register.
The MPU uses its address bus to send the address of a memory register and uses the data
bus and control lines to read from or write into that register.

4.2 Building Blocks of Memories

A flip-flop or a latch is a basic element of memory. To write or store a bit in the latch, we
need an input data bit (DIN) and an clock or enable signal (EN), as shown in Fig. 4.1.

Fig. 4.1 Latch as memory cell

In the above latch, the stored bit is always available on the output line DOUT. Tri-state
buffers, as shown in Fig. 4.2 , can be used on input and output side of latch to avoid
unintentional change in the input and to control the availability of the output .

Fig. 4.2 Latch with Tristate Buffers

Input data can be written into the latch by enabling the input buffer using active low WR
signal and can be read from it by enabling the output buffer using active low RD signal.
This latch, with read and write enable signals which can store one binary bit, is called a
memory cell.
Fig. 4.3 shows a 8 bit register consisting of eight such cells or latches grouped together. This
register has eight input lines and eight output lines and can store eight bits; thus the size of
the memory word is eight bits. The size of this register is specified either as 8-bit or 1 × 8-
bit, which indicates one register with eight cells or eight I/O lines.

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Memory Mapping By Dr. Ram Niwas, IES 59

Fig. 4.3 Eight Bit Register

Fig.4.4 shows simplified block diagrams of the 8-bit register with input and output buffers.

Fig. 4.4 Simplified Block Diagrams of 8-bit Register

In Fig. 4.5 four registers with eight cells (or an 8-bit memory word) are arranged in a
sequence. It is an example of 4 byte memory. To write into or read from any one of the
registers, a specific register should be enabled. A 2-to-4 decoder can be used for enabling or
giving clock pulse to each register. Two address lines A1 and A0 can be given as input to the
decoder. These two lines can have four different bit combinations (00, 01, 10, 11), and each
combination can identify or enable one of the register from Register 0 to Register 3. Thus,
the Enable signal of the flip-flops in Fig. 4.4 is replaced by two address lines in Fig. 4.5. Two
chips with 4-bit registers can also be connected to make up an 8-bit word memory size as
shown in Fig. 4.6. The size of memory can be further expanded by taking eight registers on
one chip. Three address lines can be used to enable the register in memory chip. Similarly ,
size can be expanded to 16 registers and registers can be enabled by using 4 address lines.
The same concept can be used to further expand the size of memory chip. Eight address
lines will be required to enable memory locations in 256 byte and 16 address lines will be
require to enable memory locations in 64 kbyte memory chip.
60 By Dr. Ram Niwas, IES Microprocessor 8085

Fig. 4.5 Four Byte Memory

Fig.4.6 Four Byte Memory Using two 4 Bits Memories.

Fig.4.7 shows a memory chip of 8 registers with three address lines. More than one chip can
also be used to form larger size of memory. For example two chips with four 8 bit registers
each can be used to construct a memory with eight registers. In such case we need three
address lines, out of which one line is used to select between the two chips and remaining
two lines are used to select a register in the chip.

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Memory Mapping By Dr. Ram Niwas, IES 61

Fig. 4.7 Eight Byte Memory with 3 Address Lines

Fig. 4.8 shows two memory chips, with an additional signal called Chip Select (CS), and A 2
(with an inverter) is used to select between the chips. When A2 is 0 (low), chip 1 is selected,
and when A2 is 1 (high), chip 2 is selected. The addresses on A 1 and A0 determine the
registers to be selected; thus, by combining the logic on A2, A1 and A0, the memory addresses
range from 000 to 111. The concept of the Chip Select signal helps in designing chips and
allows us to expand memory size by using multiple chips.

Fig. 4.8 Two Memory Chips with Chip Select

When we have four address lines and two memory chips with four registers each two
lower order address lines can be used to enable the register of chip and two higher order
62 By Dr. Ram Niwas, IES Microprocessor 8085
lines can be used to generate Chip Select logic as shown in Fig. 4.9. Memory chip 1 is
selected when A3 and A2 are both 0 ; therefore, registers in this chip are identified with the
addresses ranging from 0000 to 0011 (0 to 3).

Fig. 4.9 Addressing Eight Registers with Four Address Lines

Memory chip 2 is selected when A3 is 1 and A2 is 0 ; therefore, registers in this chip are
identified with the addresses ranging from 1000 to 1011 (8 to B).
In above example, we need three lines to identify eight registers, out of which two for
registers and one for Chip Select. However, in case if four address lines are available, fourth
line can also be used for Chip Select . This is called complete or absolute decoding. Another
option is to leave the fourth line as don’t care.

Ex.4.1 Find the address range for 4K RAM used in 8085 microprocessor if CS = A15 A14 A13 is
used as the chip select logic .
Solution :
For 4K RAM (4 1024 = 212) the number of address lines required would be 12. So, out
of 16 address line 12 address line (i.e. A11 to A0) are used for addressing the memory
location in a chip and remaining four(i.e. A15 to A12) are used for selecting the chip. Here,
chip select signal is CS = A15 A14 A13 , so, the address lines A15 = 0 , A14=1 and A13= 1. The
line A12 may be 0 or 1 and accordingly range will be available.
The range of memory location with CS = A15A14 A13 will be as follows,
Case-I : Taking A12 = 0

A15 A14 A13 A12 A11A10 A9 A8 A 7 A 6 A 5 A 4 A 3 A 2 A1 A0

0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0=6000 H
0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1=6FFFH

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Memory Mapping By Dr. Ram Niwas, IES 63
So, address range is 6000H to 6FFFH with A12 = 0
Case-II : Taking A12 = 1

A15 A14 A13A12 A11A10 A 9 A8 A 7 A 6 A5 A 4 A 3 A 2 A1A0

0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 =7000 H
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 =7FFFH

So, address range is 7000H to 7FFFH with A12 = 1

Ex.4.2 The logic circuit used to generate the active low chip select (CS) by an 8085 microprocessor
to address a peripheral is shown in figure below. Find addresses in the range for which the
device will respond.

Solution :
For chip select CS signal to be low, A12 = 0, A13 =1 , A14 =1 , A15 =1 , the address range
with this combination will be as under,
A15 A14 A13 A12 A11 A10 A 9 A8 A 7 A 6 A5 A 4 A 3 A 2 A1A 0
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = E000H
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 = EFFFH
chip select register select

So, address range is E000-EFFF.

Ex.4.3 Which of the following memory address range is NOT represented by chip # 1 and chip #2
in Fig. A0 to A15 in this figure are the address lines and CS means Chip Select.
64 By Dr. Ram Niwas, IES Microprocessor 8085
(a) 0100 – 02FF (b) 1500 – 16FF
(c) F900 – FAFF (d) F800 – F9FF
GATE(EC,05)
Solution : Ans (d)
For 256 bytes memory (256 = 28) the number of address lines required would be 8. So, out
of 16 address lines 8 lines (i.e. A7 to A0) are used for addressing the memory location in a
chip and out of remaining 8 lines, 2 lines (i.e. A9 to A8) are used for selecting the chip and 6
lines (i.e. A10 to A15) are unused.

When chip select signal is CS = A9 A8 , the address lines A9 = 0 and A8 =1. The lines
A10 to A15 are unused and so they are don’t care and lines A0 to A7 may be 0 or 1. The range
of memory locations with CS = A9 A8 will be as follows,

A15 A14 A13 A12 A11A10 A 9 A8 A 7 A6 A 5 A 4 A 3 A 2 A1 A 0

x x x x x x 0 1 0 0 0 0 0 0 0 0
x x x x x x 0 1 1 1 1 1 1 1 1 1
Don't care chip register
select select

The address range covered by above combination of address line may vary from 0100 H to
FDFFH.

When chip select signal is CS = A9 A8 , the address lines A9 = 1 and A8 =0. The lines
A10 to A15 are don’t care and lines A0 to A7 may be 0 or 1. The range of memory locations
with CS = A9 A8 will be as follows,

A15 A14 A13 A12 A11A10 A9 A8 A 7 A6 A5 A 4 A 3 A 2 A1 A 0

x x x x x x 1 0 0 0 0 0 0 0 0 0
x x x x x x 1 0 1 1 1 1 1 1 1 1
Don't care chip register
select select

The address range covered by above combination of address line may vary from 0200 H to
FE00H.
In F800 H address A8 =0 and A9 =0. So, neither of chip is selected for address F800H.
Therefore, the address range F800 – F9FF is NOT represented by chip # 1 and chip #2.

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Memory Mapping By Dr. Ram Niwas, IES 65
4.3 Memory Requirement and Memory Model
1. Address lines are used to identify a register in a memory chip. The number of address
lines required is determined by the number of registers in a chip (2n = Number of registers;
where n is the number of address lines). The 8085 microprocessor has 16 address
lines. Of these 16 lines, the address lines necessary for the memory chip must be connected
to the memory chip.
2. A memory chip requires a Chip Select CS signal to enable the chip. The remaining
address lines of microprocessor which are not connected to address lines of memory
chip can be connected to the CS signal through a chip select logic circuit.
3. The address lines which are neither used for Chip select logic nor used for enabling the
register in a chip should be left as don’t care. Such lines should be used as don’t care for
determining the address range of memory chip.
4. The address lines connected to CS select the chip, and the address lines connected to
the address lines of the memory chip select the register. Thus the memory address of a
register is determined by the logic levels (0/1) of all the address lines (including the
address lines used for CS ).
5. The control signal Read ( RD ) enables the output buffer and data from the selected
register are made available on the output lines. Similarly, the control signal Write ( WR )
enables the input buffer, and data on the input lines are written into memory cells. The
microprocessor can use its Memory Read and Memory Write control signals to enable
the buffers and the data bus to transport the contents of the selected register between
the microprocessor and memory.
6. The memory address range of a given chip can be changed by changing the hardware of
the Chip Select (CS) line. This line is also known as the Chip Enable (CE) line.
The models of a Read and Write Memory and the Read-Only Memory is shown in Fig.
4.10. The only difference between the two as far as addressing is concerned is that
ROM does not need the WR signal.

Fig.4.10 Memory Models

66 By Dr. Ram Niwas, IES Microprocessor 8085
4.4 Memory Address Lines
The number of address lines in a memory chip are determined from the number of registers
in the memory chip. The number of address lines,n, in a M bytes memory is given by,
n = log2 M
4.5 Memory Word Size
Word size of a Memory chip is maximum number of bits stored in one memory location.

4.6 Size of Memory

Size of memory is defined as 2n×m bits, where, ‘m’ is number of data lines and ‘n’ is number
of address lines.
Most of the times ‘m’ is 8 and the size of memory may also be specified in terms of bytes
stored by the memory. For example 4K memory means 4K bytes of memory. That is a
memory with 8 data lines. And 1 K bytes of memory means 1024 bytes of memory.
4 K bytes = 4 × 1024 bytes =4096 bytes
= 212 × 8 bits = 2n×m bits
Thus 12 address lines are required to address a 4K memory.
Ex. 4.4 A memory system of size 16 K bytes is required to be designed using memory chips which
have 12 address lines and 4 data lines each. Then the number of such chips required to
design the memory system is
(a) 2 (b) 4
(c) 8 (d) 16
ISRO (2009)
Answer:
Size of memory is defined as 2n×m bits, where, ‘m’ is number of data lines and ‘n’ is
number of address lines. 1 K bytes of memory means 1024 bytes of memory.
Size of memory required = 16K × 8 bits
= 16×1024× 8 bits
Size of given chip = 212×4
= 4×1024×4 bits
Number of memory chips required ,
16 1024 8
x = 8
4 1024 4
4.7 Memory Interfacing with 8085
A microprocessor needs to access memory quite frequently to read instruction codes
and data stored in memory during execution of a program; the interfacing circuit enables
that access. Memory has certain signal requirements to write into and read from its
register. Similarly, the microprocessor initiates a set of signals when it wants to read
from and write into memory. The interfacing process involves designing a circuit that

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Memory Mapping By Dr. Ram Niwas, IES 67
will match the memory requirements with the microprocessor signals. Microprocessor
8085 has 16 address lines available for memory. That means it is capable of identifying
216 (65536) memory registers, each register with a 16-bit address. The entire memory
addresses can range from 0000 to FFFF in Hex. Memory addresses provide the locations
of various memory devices in the system, and the interfacing logic defines the range of
memory addresses for each memory device.
Let us assume that we have a memory chip with 256 registers. Therefore, we need only 256
numbers (out of 65,536) that require eight address lines (28 = 256), the remaining eight lines
are used for the Chip Select through appropriate logic circuit. The address range of a
memory chip can be modified by modifying the chip select logic.
A group of 1024 registers is designated as 1K memory. Therefore a 1K-byte memory chip
has 1024 registers with 8 bits each. Similarly, a group of 256 registers is defined as one page
and each register is viewed as a line on the page . With this analogy, we can view 1K-byte
memory as a chip with four pages (1024/256 = 4) with each page having 256 registers.

Absolute Vs. Partial Decoding and Multiple Address Ranges

When all the high-order address lines are decoded to select the memory chip, and the memory
chip is selected only for the specified logic levels on these high-order address lines; no other
logic level can select the chip, this is called absolute decoding. This is a desirable design
practice commonly used in large memory systems.
However, when some of address lines may not be decoded, such lines are used as don’t
care while determining the address range.It results in multiple addresses; this is called partial
decoding. In a small system where the total memory space is not needed, such a technique
of partial decoding can be used. The primary advantage of such a technique is in cost saving.
In partial decoding we can use the same decoder for multiple size memory chips.
4.8 Logic Devices for Interfacing
4.8.1 Tri-State Devices
Tri-state logic devices are essential for proper functioning of the bus-oriented system,
in which the same bus lines are shared by several components.
A tri-state logic device has three states: two logic states and one high impedance state.
When the device is not enabled, it remains in high impedance and does not draw any
current from the system.

Fig.4.11 :Tri-State Inverters with Active High and Active Low Enable Lines
68 By Dr. Ram Niwas, IES Microprocessor 8085
A tri-state logic device has a third line called Enable, as shown in Fig.4.11. When this
line is activated, the tri-state device functions the same way as ordinary logic devices,
when the third line is disabled, the logic device goes into the high impedance state-as if
it were disconnected from the system.
In microcomputer systems, peripherals are connected in parallel between the address
bus and the data bus through tri-state interfacing devices, so that peripherals do not
load the system buses. The microprocessor communicates with one device at a time by
enabling the tri-state line of the interfacing device. Tri-state logic is critical to proper
functioning of the microcomputer.
4.8.2 Buffer
The buffer is a logic circuit that amplifies the current or power. It has one input line and
one output line. The logic level of the output is the same as that of the input; logic 1
input provides logic 1 output (the opposite of an inverter). The buffer is used primarily
to increase the driving capability of a logic circuit. It is also known as a driver.

Fig. 4.12 : A Buffer and a Tri-State Buffer

Figure 4.12 shows a tri-state buffer. When the Enable line is low, the circuit function as
a buffer, otherwise it stays in the high impedance state. The buffer is commonly used to
increase the driving capability of the data bus and the address bus.

GATE QUESTIONS
Q.1 A memory system has a total of 8 memory chips, each with 12 address lines and 4 data
lines. The total size of the memory system is
(a) 16 kbytes (b) 32 kbytes
(c) 48 kbytes (d) 64 kbytes
GATE(EE, 03)
Q.2 An 8-bit microcontroller has an external RAM in the memory map from 8000H to 9FFFH.
The number of bytes this RAM can store is
(a) 8193 (b) 8191
(c) 8192 (d) 8000

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Memory Mapping By Dr. Ram Niwas, IES 69
GATE(IN, 05)
Q.3 An I / O peripheral device shown in Fig. (b) below is to be interfaced to an 8085 microproc-
essor. To select the I / O device in the I / O address range D4 H - D7 H, its chip-select
CS should be connected to the output of the decoder shown in Fig. (a) below:

Fig. (b)
(a) output 7 (b) output 5
(c) output 2 (d) output 0
GATE(EC, 06)
Q.4 An 8085 microprocessor based system uses a 4K 8 bit RAM whose starting address is
AA00 H. The address of the last byte in this RAM is
(a) 0FFF H (b) 1000 H
(c) B9FF H (d) BA00 H
GATE(EC, 01)
Q.5 An 8-bit DAC is interfaced with a microprocessor having 16 address lines (A 0 ... A15) as
shown in the adjoining figure. A possible valid address for this DAC is

(a) 3000H (b) 4FFFH

(c) AFFF H (d) C000H
GATE(IN, 10)
Q.6 There are four chips each of 1024 bytes connected to a 16 bit address bus as shown in the
figure below. RAMs 1, 2, 3 and 4 respectively are mapped to addresses
70 By Dr. Ram Niwas, IES Microprocessor 8085

(a) 0C00H-0FFFH, 1C00H-1FFFH, 2C00H-2FFFH, 3C00H-3FFFH

(b) 1800H-1FFFH, 2800H-2FFFH, 3800H-3FFFH, 4800H-4FFFH
(c) 0500H-08FFH, 1500H-18FFH, 3500H-38FFH, 5500H-58FFH
(d) 0800H-0BFFH, 1800H-1BFFH, 2800H-2BFFH, 3800H-3BFFH
GATE (EC, 13)
Q.7 An output device is interfaced with 8-bit microprocessor 8085A. The interfacing circuit is
shown in figure

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Memory Mapping By Dr. Ram Niwas, IES 71

The interfacing circuit makes use of 3 Line to 8 Line decoder having 3 enable lines E1 , E 2 , E3 .
The address of the device is
(a) 50 H (b) 5000 H
(c) A0 H (d) A000 H
GATE (2014/EE-I/2 M)

Answers and Explanations

Q.1 Ans (a)

Size of memory is defined as 2n×m bits, where, ‘m’ is number of data lines and ‘n’ is number
of address lines.
Given , n = 12 and m = 4 , so size of each memory chip will be 212 × 4 bits = 2 kbytes. So, the
total size of 8 chips will be 16 kbytes.
Note : 1 K bytes of memory means 1024 bytes of memory.
Q.2 Ans (c)
Number of bytes which can be stored in RAM in address ranging from 8000 H to 9FFFH will
be equal to( 9FFFH 7FFFH ) or 2000H . 2000H in hexadecimal is equivalent to 8192 locations.
Q.3 Ans.(b)

Fig. (b)

The value of address lines for given range of port address,

A7 A6 A5 A4 A3 A2 A1 A0
D4H : 1 1 0 1 0 1 0 0
D7H : 1 1 0 1 0 1 1 1
The values of decoder inputs for given range,
A4A3A 2 = 1 0 1 = 5
So, pin number 5 of output of decoder should be connected at chip-select CS of I/O device.
Q.4 Ans (c)
Size of 4K 8 memory is 4K bytes or 4096 bytes. In hexadecimal code 4096 bytes = 1000 H
72 By Dr. Ram Niwas, IES Microprocessor 8085
The last address in RAM, with AA00H as starting address, will be AA00H + 0FFF H
= B9FFH
Q.5 Ans. (a)

For enabling the decoder, chip select ( CS ) of decoder should be low and it is low when
address lines A15 is low and for generation of chip select signal ( CS ) of DAC memory, the
output line b2 of decoder should be selected. Line b2 is selected when address lines
A 14 =0 , A13 = 1.
So, for selection of given DAC A 15 =0 , A14 = 0 and A13 = 1.
Since the microprocessor has sixteen address lines then possible address range for Given
DAC can be as under,

A15 A14 A13 A12 A11A10 A9 A8 A 7 A 6 A5 A 4 A 3 A 2 A1A0

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 = 2000 H
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 = 3FFFH
chip
select

So, the range of the address of the DAC can be from 2000 H to 3FFFH.
From the given options the address 3000H lies in the range of address of DAC.
Q.6 Ans (d)

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Memory Mapping By Dr. Ram Niwas, IES 73

To enable RAM its enable line should be high. Only one line of DEMUX with S 0 & S1 select
line is high depending on values of S0 & S1. Input of DEMUX is high only
When A 10 = 0, A11 = 1, A14 = 0, A15 = 0
For lowest Address all address lines of RAM should be ‘0’ and for highest address of RAM
all the address lines should be ‘1’.
Case-I: RAM # 1
RAM # 1 selected when S0 = A12 = 0 and S1 = A13 = 0
The range of address for RAM 1 is as under,

S1 S0
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 : 0800H
0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 : 0BFFH
So, range of RAM # 1 is 0800H to 0BFFH
Case – II: RAM # 2
RAM # 2 selected when S0 = A12 = 1 and S1 = A13 = 0
74 By Dr. Ram Niwas, IES Microprocessor 8085

S1 S0
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 :1800H
0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 :1BFFH
Case-III: RAM # 3
RAM # 3 selected when S0 = A12 = 0 and S1 = A13 = 1
S1 S0
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 : 2800H
0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 : 2BFFH
Case-IV: RAM # 4
RAM # 4 selected when S0 = A12 = 1 and S1 = A13 = 1

S1 S0
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 : 3800H
0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 : 3BFFH
Q.7 Ans. (b)

The data will be transferred from data bus to output device only when the output port is
enabled. The output port is enable when ouput pin ‘2’ of the 3L to 8L decoder is low. The
output pin ‘2’ will be low if decoder is enabled with enable lines E 1 = 0 , E 2 = 0, E 3 = 1 and
inputs lines Io = 0, I1 = 1 & I2 = 0.
Thus for selection of output device, E 1 = IO/ M = 0, E 2 = WR = 0, Io = A13 = 0, I1 = A14=1
& I2 = A15 = 0. Here E 3 = A11A12 = 1 only if A111 = 0, A12=1. The address of the device can
be written as,

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Memory Mapping By Dr. Ram Niwas, IES 75

A15A14 A13A12 A11A10A 9 A 8A 7 A 6A 5A 4A 3A 2 A1A 0

0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 5000H
inputs enable
Thus, the address of the device is 5000H.
Instruction Set of 8085 By Dr. Ram Niwas

6
Instruction Set of 8085
and Programming

6.1 Classification of Instructions

1. Single Byte Instructions
These instructions require one byte of the memory while storing the program in the
memory. Such instruction needs only one byte of memory for storing of Opcode
only. Examples : CMA, RLC, RAL, MOV R, M etc
2. Two Byte Instructions
These instructions require two memory locations while storing a program in the
134 Microprocessor 8085
memory. These instructions have 8 bit data as operand in instruction along with
mnemonics. One byte of memory is required to store Opcode and one byte for 8 bit
data.
Examples : MVI R, 8 bit data; ADI 8 bit data etc.
3. Three Byte Instructions
These instructions require three bytes of memory while storing a program in the
memory. These instructions have 16 bit data as operand in instruction along with
mnemonics. One byte of memory is required to store Opcode and two bytes for 16
bit data.
Examples : LDA 16 bit address; LXI Rp, 16 bit data.
6.2 Addressing Modes of 8085
Every instruction of a microprocessor system has some data on which it performs its
operation. There are many techniques of specifying this data. These techniques of
specifying the data of instruction are called addressing modes. 8085 microprocessor
has five different types of modes which are briefly described as under,
1. Register Addressing Mode
When the data transfer is between two registers the addressing mode is called
register addressing mode. e.g. MOV A,B, PCHL, SPHL , ADD B , SUB B etc.
2. Direct Addressing Mode

When the data transfer is with the memory or I/O device and address of memory or
I/O device is included in the instruction itself, the addressing mode is called direct
addressing mode. e.g. LDA 16 bit address, STA 16 bit address , IN 8bit address,
OUT 8bit address etc.
3. Indirect Addressing Mode
When the data transfer is with the memory or I/O device and address of memory or
I/O device is not included in the instruction rather it is indicated through a memory
pointer, the addressing mode is called indirect addressing mode. e.g. MOV M, R
; LDAX D etc.
4. Implicit or Implied Addressing Mode
When the instruction modifies the contents of accumulator without using any operand
the mode of addressing is called implicit or implied. In implied addressing mode, the
location of the operand is contained within the opcode.e.g. CMA, RLC, etc.
5. Immediate Addressing Mode
When 8 bit or 16 bit data is given in the instruction as operand the addressing mode
is called immediate addressing mode. e.g. ADI 8 bit data; SUI 8bit data; MVI R,
Instruction Set of 8085 135
8 bitdata; LXI Rp, 16 bit data.
Note: i. When ever there is letter ‘I’ at the end in a Mnemonics that indicates immediate
addressing mode.
ii. When one of the operand is letter ‘M’ that indicates the indirect addressing mode.

6.3 Writing, Storing and Execution of Assembly Language Program

6.3.1 Opcode, Operand and Mnemonic
An instruction is divided into two parts: Opcode and Operand. Opcodes are the abbreviated
symbols specified by the manufacturer to indicate the type of operation or function that will
be performed by the machine code.
The operand part of an instruction specifies the item to be processed; it can be 8-or 16-bit
data, a register, or a memory address.
An instruction, called a mnemonic or mnemonic instruction, is formed by combining an opcode
and an operand.
6.3.2 Assembly Language Program
Tasks 8085 Mnemonics
1. Load register C with 8A H MVI C, 8AH
2. ADD content of C to A. ADD C
3. Send the number to the output-port 03 OUT 03H
H.
4. End of the program. HLT
6.3.3 Translation from Assembly Language to Machine Language
Now, to translate the assembly language program into machine language, look up the hexa-
decimal machine codes for each instruction in the 8085 instruction set and write each ma-
chine codes in the sequence, as follows:
8085 Mnemonics Hex Machine Code
1. MVI C, 8AH 0E
8A
2. ADD C 81
3. OUT 03 D3
03
4. HLT 76
This program has six machine codes and will require six bytes of memory to enter the
program into your system. If microcomputer has R/W memory starting at the address 5000H,
this program can be entered in the memory locations 5000H to 5005H.
If the system has R/W memory with the starting address at 5000H and the output port
address 03H, the program will be stored as follows:
136 Microprocessor 8085

The format generally used to write an assembly language program is described in the next
section.
6.3.4 Program Format
Memory Machine Opcode Instruction Comments
Address Code Operand
(Hex) (Hex)
5000 0E MVI C,8AH ; Loads register C with data 8AH
5001 8A
5002 81 ADD C ; Adds (C) to (A)
5003 D3 OUT 03 ; Displays accumulator contents
5004 03 ; at port 03 H
5005 76 HLT ; Ends of the program

This program has five columns: Memory Address, Machine Code, Opcode, Operand, and
comments. Comments are separated by semicolon(;) from the mnemonics.
Machine Codes are the hexadecimal numbers (instruction codes) that are entered (or stored)
in the respective memory addresses through the hexadecimal keyboard of the microcomputer.
The monitor program, which is stored in Read-Only memory (ROM) of the microcomputer,
translates the Hex numbers into binary digits and stores the binary digits in the R/W memory.
The Key Monitor program is a set of instructions that continuously checks whether a key is
pressed and stores the binary equivalent of a pressed key in a memory location. W h e n
the power is turned on, the monitor program stored either in EPROM or ROM comes alive.
The RESET key clears the program counter, and the program counter holds the memory
address 0000H.
As soon as the RESET key is pushed, the program counter places the memory address
0000H on the address bus, the instruction at that location is fetched, and the execution of the
Key Monitor program begins. Therefore, the Key Monitor program is stored on page 00H.

6.3.5 Entering and Execution of a Program

To enter the program:
1. Push the RESET key.
Instruction Set of 8085 137
2. Enter the 16-bit memory address of the first machine code of your program.
3. Enter and store all the machine codes sequentially, using the hexadecimal keyboard on
your system.
4. Reset the system.
5. Enter the memory address where the program begin and push the Execute key.

6.4 Instruction Set

Instructions of the 8085 are classified in.five categories on the basis of function performed.
1. Data Transfer Instructions
This group of instructions copy data from a location called a source to another location
called a destination, without modifying the contents of the source. In technical manuals,
the term data transfer is used for this copying function. However, the term transfer is
misleading; it creates the impression that the contents of the source are destroyed
when, in fact, the contents are retained without any modification.
2. Arithmetic Instructions
These instructions perform arithmetic operations such as addition, subtraction, increment,
and decrement. In addition /subtration operation any 8-bit number, or the contents of a
register or the contents of a memory location can be added/subtracted to/from the contents
of the accumulator and the result is stored in the accumulator. The 8-bit contents of a
register or a memory location can be incremented or decrement by 1. Similarly, the 16-bit
contents of a register pair (such as BC) can be incremented or decrement by 1. These
increment and decrement operations differ from addition and subtraction in an important
way; i.e., they can be performed in any one of the registers or in a memory location.
3. Logical Instructions
These instructions perform various logical operations such as AND,OR, ExOR, NOT,
Rotate, Compare and compliment oeprations with the contents of the accumulator. The
logical operation of AND, OR, ExOR of any 8-bit number, or the contents of a register or the
contents of a memory location is performed with the contents of the accumulator and the
result is stored in the accumulator.
4. Machine Control Operations
These instructions control machine functions such as Halt, Interrupt, or do nothing.
5. Branching Operations
This group of instructions alters the sequence of program execution either conditionally
or unconditionally. Branch instructions of 8085 microprocessor are Jump, Call, Return
and Restart. Conditional jumps instructions use the status of flags for altering the
sequence of execution of the program. Call instuctions are used to call subroutine
conditionally or unconditional and return instructions are used to return to main program
from subroutine conditionally or uncoditionally. Restart instrucitons are software intrupts
which are nothing but calling of subroutine stored at specific memory addresses.
6.4.1 Data Transfer Instructions
1. MOV Rd, Rs i. Copy the data of source register Rs to the
Rs A, B, C, D, E, H&L destination register Rd
138 Microprocessor 8085
Rd A, B, C, D, E, H & L ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4T
v. No flag is affected
Note: No flag is affected by data transfer instructions
Note: OP : Op Code Fetch, MW : Memory write , MR : Memory read, IOR : I/O read, IOW:
I/O write.
2. MOV M, R i. Copy the data of register R to the memory
R A, B, C, D, E, H & L location whose address is stored in HL pair
M Memory address ii. 1-byte instruction
stored in HL pair iii. Register indirect addressing mode
iv. Two machine cycles (OP+MW) & 7T-states.
v. No flag is affected
3. MOV R, M i. Copy the data of memory location whose
R A, B, C, D, E, H & L address is stored in HL pair to the register R
M Memory address ii. 1-byte instruction
stored in HL pair iii. Register indirect addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. No flag is affected

4. MVI R, 8 bit data i. Copy the 8 bit data immediately to the register R
R A, B, C, D, E, H & L ii. 2-byte instruction
iii. Immediate addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. No flag is affected

5. MVI M, 8 bit data i. Copy the 8 bit data immediately to the memory
M Memory address location whose address is stored in HL pair
stored in HL pair ii. 2-byte instruction.
iii. Immediate-indirect addressing mode.
iv. Three machine cycles (OP+MR+MW)&10
T-states.
v. No flag is affected.

6. LXI RP, 16 bit data i. Load the 16 bit data immediately in register
Rp BC, DE, HL & SP pair,Rp
ii. 3-byte instruction
iii. Immediate addressing mode
iv. Three machine cycles (OP+MR+MR)& 10
T-states
v. No flag is affected .
Note : While storing instruction in memory, the lower byte of 16 bit is stored at lower address
Instruction Set of 8085 139
and higher order byte is stored at higher address and at the time of execution the lower
order byte stored at lower address is first read into lower order register of register pair
Rp and higher order byte stored at higher address is read into higher order register.

Ex 6.1 : 2000 LXI B, 3000 H

The given instruction is stored in memory as under,
2000 XX ; Let XX Opcode
2001 00
2002 30
At the time of execution the lower order byte(i.e. 00H) stored at 2001 is moved to
lower order register C and higher order byte (i.e. 30H) is moved to higher order
register, B.
7. LDA 16 bit address i. Load accumulator directly with the contents of
given 16 bit address.
ii. 3-byte instruction
iii. Direct addressing mode
iv. Four machine cycles (OP+MR+MR+MR) &
13 T-states
v. No flag is affected

8. STA 16 bit address i. Store the contents of ‘A’ at given 16 bit address
ii.3-byte instruction
Direct addressing mode
iii.
iv.Four machine cycles (OP+MR+MR+MW) &
13 T-states
v. No flag is affected

9. LDAX RP i. Load accumulator with contents of memory

RP BC & DE location whose address is stored in register RP
ii. 1-byte instruction
iii. Indirect addressing mode
iv. Two machine cycles (OP+MR) & 7 T-states.
v. No flag is affected.

10. STAX R P i. Store the contents of accumulator at memory

RP BC & DE

ii. 1 byte instruction

iii. Indirect addressing mode
iv. Two machine cycles (OP+MW) & 7 T-states.
v. No flag is affected.
140 Microprocessor 8085

11. LHLD 16 bit address i. Load HL pair with the contents of given address
and next address. The contents of given address
are moved to L and contents of next address
are moved to H.
ii. 3 byte instruction
iii. Direct addressing mode
iv. Five machine cycles (OP+MR+MR+MR+MR)
& 16 T-states
v. No flag is affected

Ex.6.2 LHLD 3000 H , load register L with contents of 3000 H and register H with contents
of 3001 H.

12. SHLD 16 bit address i. Store HL pair at given 16 bit address and next
address. The contents of L are moved to given
and contents of H are moved to next address.
ii. 3 byte instruction
iii. Direct addressing mode
iv. Five machine cycles (OP+MR+MR+MW+MW)
& 16 T-states
v. No flag is affected
Ex.6.3 SHLD 3000 H , store the contents of L at 3000H and contents of register H at
3001H.
Ex 6.4 Consider the execution of the following instructions by a 8085 microprocessor :
LXI H, 01FFH
SHLD 2050H
What are the contents of memory locations 2050H and 2051H and the registers H and L
after execution of above instructions.
IES(EE,02)
Solution:
LXI H, 01FFH [ Load H = 01H, L = FFH]
SHLD, 2050H
After the execution of SHLD instruction, the contents of L are stored in 2050 and the
contents of H are stored in next memory location i.e. 2051. The content of H and L are
not altered
2050H = FF
2051H = 01
H = 01
L = FF
Note: The contents of lower order register are always stored at lower address and higher order
Instruction Set of 8085 141
register at higher address.

13. SPHL i. The contents of HL pair are copied in stack

pointer
ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 6 T-states
v. No flag is affected

14. PCHL i. The contents of HL Pair are copied in program

counter.
ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 6 T-states
v. No flag is affected
15. XCHG i. Exchange the contents HL pair with DE pair.
ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. No flag is affected

16. IN 8 bit port address i. Copy the contents of I/O mapped I/O device
connected at given 8 bit port address directly to
accumulator .
ii. 2-byte instruction
iii. Direct addressing mode
iv. Three machine cycles (OP+MR+IOR) & 10
T-states
v. No flag is affected
17. OUT 8 bit port address i. Copy the contents of accumulator directly to I/
O mapped I/O device connected at given 8 bit
port address
ii. 2-byte instruction
iii. Direct addressing mode
iv. Three machine cycles (OP+MR+IOW) & 10
T-states
v. No flag is affected

6.4.2 Arithmetic Instructions

1. ADD R i. Add the contents of R to A and store the result

142 Microprocessor 8085
R A, B, C, D, E, H & L in A
ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected

2. ADD M i. Add the contents of memory location, whose

M Memory address address is stored in HL pair to A & store result
stored in HL pair in A
ii. 1-byte instruction
iii. Register indirect addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected

3. ADI 8bit data i. Add the 8 bit data immediately to A and store
the result in A
ii. 2-byte instruction
iii. Immediate addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected

4. ADC R i. Add the contents of R along with carry flag to

R A, B, C, D, E, H & L contents of A and store the result in A
ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected
5. ADC M i. Add the contents of M along with carry flag to
M Memory address contents of A and store the result in A
stored in HL pair ii. 1-byte instruction
iii. Indirect addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected

6. ACI 8 bit data i. Add the 8 bit data along with carry flag to
contents of A & store result in A
ii. 2-byte instruction
iii. Immediate addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected

7. DAD RP i. Add the contents of register pair Rp to contents

RP BC, DE, SP & HL of HL pair and store the result in HL pair.
Instruction Set of 8085 143
ii. 1-byte instruction
iii. Register addressing mode
iv. Three machine cycles & 10 T-states
v. Only CY flag is set if result is more than 16 bits.
No other flag is affected.

Ex.6.5 An 8085 executes the following instructions.

2710 LXI H, 30A0H
2713 DAD H
2714 PCHL
All addresses and constants are in Hex. What are contents of PC and HL just after executing
PCHL?
GATE(EC,08)
Solution:
2710 LXI H, 30A0H ; Loads HL pair with 30A0 H. So, H = 30 H and L = A0 H
2713 DAD H ; Adds the contents of HL pair(i.e. 30A0H) to HL pair
(i.e. 30A0H) and store result in HL pair.
HL : 0011 0000 1010 0000
+HL : 0011 0000 1010 0000
HL : 0110 0001 0100 0000
6 1 4 0
After addition, HL = 6140 H
2714 PCHL ; Moves the contents of HL (i.e 6140H) pair to Program
Counter. So, PC = 6140 H.
So, after execution of PCHL , HL = 6140 H and PC = 6140 H.

8. DAA i. Decimal Adjust Accumulator. Binary contents

of accumulator are changed to its two digit BCD
equivalent
ii. 1-byte instruction
iii. Implicit or Implied addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected
Note: DAA instruction changes the binary values of contents of accumulator to its two digit
equivalent BCD number. This instruction makes use of status of CY and AC flags. It
performs the operation as follows,
I. If value of lower order four bits (D3-D0) in the accumulator is greater than 9 or if
AC flag is set , the instruction adds 0110 to low order four bits.
II. If value of higher order four bits (D7-D4) in the accumulator is greater than 9 or if CY
flag is set , the instruction adds 0110 to higher order four bits.
Note: DAA is used for BCD addition only not for BCD subtraction.

Ex6.6 The following instructions have been executed by an 8085 microprocessor,

ADDRESS (HEX) INSTRUCTION
6010 LXI H, 8A79 H
144 Microprocessor 8085
6013 MOV A, L
6014 ADD H
6015 DAA
6016 MOV H, A
6017 PCHL
What will be address of the next instruction be fetched?
GATE(EC,97)
Solution :
6010 LXI H, 8A79 H ; Loads HL pair with 8A79H . With H = 8AH and
L = 79H
6013 MOV A, L ; Moves the contents of L (i.e. 79H ) to A. So, A = 79H
6014 ADD H ; Adds the content of H(i.e. 8AH ) to contents of A and
store the result in A.

79H = 0111 1001

8AH =1000 1010
1111
1 0000 0011
CY 0 3H

6015 DAA ; As both AC and CY flags are set during execution of

ADDH, So, DAA, adds 0110H to lower order bits and
0110H to higher order bits to A to adjust binary result
to Binary coded decimal.
03H = 0000 0011
0110 0110
0110 1001=69H
So, A = 69H
6016 MOV H, A ; Moves the contents of A ( i.e. 69H ) to H.So, H = 69H
6017 PCHL ; Copies the contents of HL pair ( i.e. H = 69H and
L = 79H) to program counter. So, PC = 6979H
After the execution of PCHL the program counter has 6979H . So, the address of next
instruction to be fetched will be 6979H.

9. SUB R i. Subtract contents of R from contents of A and

R A, B, C, D, E, H & L store result in A
ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected
Instruction Set of 8085 145
10. SU B M i. Subtract contents of M from A and store result
M Memory address in A
stored in HL pair ii. 1-byte instruction
iii. Indirect addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected
11. SUI 8bit data i. Subtract the 8 bit data immediately from
contents of A and store the result in A
ii. 2-byte instruction
iii. Immediate addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected

12. SBB R i. Subtract the contents of R along with carry flag

R A, B, C, D, E, H & L from contents of A and store the result in A
ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected

13. SBB M i. Subtract the contents of M along with carry

M Memory address flag from A and store the result in A
stored in HL pair ii. 1-byte instruction
iii. Indirect addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected

14. SBI 8 bit data i. Subtract the 8 bit data along with carry flag
from contents of A & store result in A
ii. 2-byte instruction
iii. Immediate addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected

15. INR R i. Increment contents of R by 1

R A, B, C, D, E, H & L ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected except CY flag

16. INR M i. Increment contents of M by 1

M Memory address ii. 1-byte instruction
stored in HL pair iii. Indirect addressing mode
146 Microprocessor 8085
iv. Three machine cycles (OP+MR+MW) & 10
T-states
v. All flags are affected except CY flag

17. DCR R i. Decrement contents of R by 1

R A, B, C, D, E, H & L ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected except CY flag

18. DCR M i. Decrement contents of M by 1

M Memory address ii. 1-byte instruction
stored in HL pair iii. Indirect addressing mode
iv. Three machine cycles (OP+MR+MW) & 10
T-states
v. All flags are affected except CY flag
19. INX RP i. Increment contents of register pair RP by 1
Rp BC, DE, HL & SP ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 6 T-states
v. No flag is affected

20. DCX RP i. Decrement contents of register pair RP by 1

Rp BC, DE, HL & SP ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 6 T-states
v. No flag is affected

Ex6.7 In an 8085 system containing 8 KB of ROM and 8 KB of RAM, the ROM is selected when
A15 is 1. A13 and A14 are unused. The CPU executes the following program
Prog 1
MVI A, 00H
STA 8080 H
DCR A
STA C080H
RET
What are the content of memory location 8080 H after the execution of the RETURN
instruction?
GATE(IN,03)
Solution:
MVI A, 00 H ; Moves 00H to register A. So, A = 00H
STA 8080H ; Stores the contents of register A at memory location
8080H. So the contents of 8080H becomes 00H .
DCR A ; Decrements the contents of A by one. So the contents
Instruction Set of 8085 147
of A after decrement becomes FFH.
STA C080H ; Stores the contents of register A at memory location
C080H. So the contents of C080H becomes FFH .
RET ; Returns to the main program.
The content of memory location 8080H after the execution of the RETURN instruction is
00H.
Ex6.8 MVI B, 00H
MVI A, 1CH
DCR B
DAA
STA TEMP
HLT
What is the content of TEMP location after the execution of the above program ?
IAS(2008)
Solution:
MVI B, 00H ; Moves 00H to register B.
So, B = 00H
MVI A, 1CH ;
Moves 1C H to register A.
So, A = 1CH
DCR B ; Decrements the contents of B (i.e. 00H) by one. So,
B = FFH
DAA ; DAA instruction changes the binary values of contents
of accumulator to BCD. This instruction makes use of
status of CY and AC flags. It performs the operation
as follows,
I. If value of lower order four bits (D 3-D 0) in the
accumulator is greater than 9 or if AC flag is set ,
the instruction adds 0110H to low order four bits.
II. If value of higher order four bits (D7-D4) in the
accumulator is greater than 9 or if CY flag is set ,
the instruction adds 0110H to higher order four bits.
Here , lower order nibble of A is more than 9 but AC
flag is set by DCR B and upper nibble is less than 9 ,
therefore, DAA, adds 0110H to lower order nibble of
A to adjust binary result to Binary coded decimal.
A : 1C H = 0001 1100
+0110
0010 0010
So, A = 22H
STA TEMP ; Stores the contents of Accumulator at memory location
TEMP.
HLT ; Halts the execution of program.
Thus contents of TEMP are 22H.
148 Microprocessor 8085

6.4.3 Logical Instructions

1. ANA R i.Contents of R are ANDed with contents of A
R A, B, C, D, E, H & L and result is stored in A
ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected. CY flag is reset and AC
flag is set.
Note: ANA A does not affect the contents of accumulator but resets the carry flag and sets
auxiliary carry flag.
2. ANA M i. Contents of M are ANDed with contents of A
M Memory address and result is stored in A
stored in HL pair ii. 1-byte instruction
iii. Indirect addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected. CY flag is reset and AC
flag is set.

3. ANI 8bit data i. 8 bit data is ANDed with contents of A and

result is stored in A
ii. 2-byte instruction
iii. Immediate addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected. CY flag is reset and AC
flag is set.
4. ORA R i. Contents of R are ORed with contents of A
R A, B, C, D, E, H & L and result is stored in A
ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected. Both CY and AC flag
are reset.
Note: ORA A does not affect the contents of accumulator but resets the carry and auxillary
carry flags.
5. ORA M i. Contents of M are ORed with contents of A
M Memory address and result is stored in A
stored in HL pair ii. 1-byte instruction
iii. Indirect addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected. Both CY and AC flag
are reset.

6. ORI 8bit data i. 8 bit data is ORed with contents of A and result
Instruction Set of 8085 149
is stored in A
ii. 2-byte instruction
iii. Immediate addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected. Both CY and AC flag
are reset.

7. XRA R i. Contents of R are Ex-ORed with contents of A

R A, B, C, D, E, H & L and result is stored in A
ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected. Both CY and AC flag
are reset.
Note: XRA A clears the contents of accumulator but resets the carry and auxiliary carry
flags.
8. XRA M i. Contents of M are Ex-ORed with contents of A
and result is stored in A
ii. 1-byte instruction
iii. Indirect addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected. Both CY and AC flag
are reset.
9. XRI 8bit data i. 8 bit data is Ex-ORed with contents of A and
result is stored in A
ii. 2-byte instruction
iii. Immediate addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected. Both CY and AC flag
are reset.

10. CMA i. Compliment the contents of Accumulator

ii. 1-byte instruction
iii. Implicit or Implied addressing mode
iv. One machine cycle (OP) & 4 T-states
v. No flag is affected
Note: CMA performs the logical NOT operation.
11. C M C i. Compliment the Carry flag
ii. 1-byte instruction
iii. No addressing mode
iv. One machine cycle (OP) & 4 T-states
v. CY flag is complemented. No other flag is
affected.
150 Microprocessor 8085
12. STC i. Set the Carry flag
ii. 1-byte instruction
iii. No addressing mode
iv. One machine cycle (OP) & 4 T-states
v. CY flag is set. No other flag is affected.

13. RLC i. Rotate the contents of Accumulator to left

without Carry(CY) flag. The contents of bit D7
are shifted to CY flag as well as D0 bit.

ii. 1-byte instruction

iii. Implicit or Implied addressing mode
iv. One machine cycle (OP) & 4 T-states
v. Only CY flag is affected.

14. RAL i. Rotate the contents of Accumulator to left

through Carry flag. The contents of bit D 7 are
shifted to CY flag and CY flag shifted to D0.

ii. 1-byte instruction

iii. Implicit or Implied addressing mode
iv. One machine cycle (OP) & 4 T-states
v. Only CY flag is affected.

15. RRC i. Rotate the contents of Accumulator to right

without Carry flag. The contents of bit D0 are
shifted to CY flag as well as D7 bit.

ii. 1-byte instruction

Instruction Set of 8085 151
iii. Implicit or Implied addressing mode
iv. One machine cycle (OP) & 4 T-states
v. Only CY flag is affected.

16. RAR i. Rotate the contents of Accumulator to right

through Carry flag. The contents of bit D0 are
shifted to CY flag and CY flag shifted to D7.

ii. 1-byte instruction

iii. Implicit or Implied addressing mode
iv. One machine cycle (OP) & 4 T-states
v. Only CY flag is affected.

17. CMP R i. Compare the contents of R with contents of A.

ii. 1-byte instruction
iii. Register addressing mode
iv. One machine cycle (OP) & 4 T-states
v. All flags are affected.
Note: Comparison is made by subtracting the contents of register R from contents of
Accumulator. The contents of A and R remain unaltered after comparison. The result
of operation is reflected by status of flags as under,
If A – R > 0 then S = 0 ; Z = 0 ; CY = 0.
If A – R = 0 then S = 0 ; Z = 1 ; CY = 0.
If A – R < 0 then S = 1 ; Z = 0 ; CY = 1.
18. CMP M i. Compare the contents of M with contents of A.
ii. 1-byte instruction
iii. Indirect addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
v. All flags are affected.
Note: Comparison is made by subtracting the contents of memory location M from contents
of Accumulator. The contents of A and M remain unaltered after comparison. The
result of operation is reflected by status of flags as under,
If A – M > 0 then S = 0 ; Z = 0 ; CY = 0.
If A – M = 0 then S = 0 ; Z = 1 ; CY = 0.
If A – M < 0 then S = 1 ; Z = 0 ; CY = 1.
19. CPI 8-bit data i. Compare the 8-bit data with contents of A.
ii. 2-byte instruction
iii. Immediate addressing mode
iv. Two machine cycles (OP+MR) & 7T-states
152 Microprocessor 8085
v. All flags are affected.
Note: Comparison is made by subtracting the 8-bit data from contents of Accumulator. The
contents of A remain unaltered after comparison. The result of operation is reflected by
status of flags as under,
If A – (8-bit data) > 0 then S = 0 ; Z = 0 ; CY = 0.
If A – (8-bit data) = 0 then S = 0 ; Z = 1 ; CY = 0.
If A – (8-bit data) < 0 then S = 1 ; Z = 0 ; CY = 1.
Ex.6.9 An 8085 assembly language program is given below.
Line 1 : MVI A, B5H
2 : MVI B, 0EH
3 : XRI 69H
4 : ADD B
5 : ANI 9BH
6 : CPI 9FH
7 : STA 3010H
8 : HLT
What is the status of the CY and Z flags after execution of line 7 of the program?
GATE(EC,07)
Solution:
Line 1 : MVI A, B5H ; Moves B5 H to accumulator, A. So , A = B5H
2: MVI B, 0EH ; Moves 0E H to B. So, B = 0EH
3: XRI 69H ; Contents of A are ExORed with 69H and result is stored
in A.
A : 1011 0101 (B5H)
69H : 0110 1001
1101 1100 = DCH
So, A = DCH
4: ADD B ; Adds contents of B to contents of A and result is stored
in A.
A : 1101 1100
B : 0000 1110
1110 1010 = EAH
So, A = EAH
5: ANI 9BH ; Contents of A are ANDed with 9BH and result is stored
in A.
A : 1110 1010
9BH : 1001 1011
1000 1010 = 8AH
So, A = 8AH
6: CPI 9FH ; Compares 9FH with contents of A. The contents of A
remains unaffected but status of result is reflected by
flags.
Instruction Set of 8085 153
A :1000 1010
9F H :1001 1111
1 1111 1011
So, CY = 1 & Z = 0
7: STA 3010H ; Stores the contents of A at memory location 3010H.
8: HLT ; Halts the execution of program.
Thus, after execution of line 7 of the program, the CY flag is’1’ and Z flag is ‘0’.
Ex 6.10 Consider the following set of instruction:
STC
CMC
MOV A, B
RAL
MOV B, A
Find the function performed by this set of instructions.
IES(EE,97)
Solution :
Let the contents of register B are 92H.
92 H = 10010010
STC ; Set carry is CY = 1.
CMC ; Complements of carry i.e. CY = 0
MOV A, B ; Copies the contents of B (i.e. 92H) into accumulator.
So, A = 92 H
RAL ; Rotates the contents of accumulator to left through carry
Before rotation -

CY 0
A=
1 0 0 1 0 0 1 0
A = 92H
After rotation :
CY 1
A=
0 0 1 0 0 1 0 0
A = 24H
MOV B,A ; Copies contents of accumulater A in register B.
Doubling the contents of register B before execution
of RAL instruction,
10010010 : 92 H
10010010 : 92 H
100100100 : 124 H
Thus result after execution of RAL is double of contents of register B before execution of
154 Microprocessor 8085
RAL . Hence this program doubles the contents of register B.
Ex.6.11 Read the following Assembly Language Program Segment of 8085 Microprocessor :
LXI H, 2501H
MOV A, L
ORI F0H
MOV L, A
MOV A,H
ANI F0H
MOV H, A
HLT
What are the contents of A, H and L registers after executing the above set of instructions
in sequence?
IES(EE,07)
Solution :
LXI H, 2501H ; Loads HL pair with 2501H. With H =25H and L = 01H
MOV A, L ; Moves the contents of L (i.e. 01H ) to A.
So, A = 01H
ORI F0H ; Contents of A are ORed with F0H and result is stored
in A.
A : 0000 0001
F0H : 1111 0000
1111 0001 = F1 H
So, A = F1 H
MOV L, A ; Moves the contents of A (i.e. F1H ) to L.
So, L = F1H
MOV A,H ; Moves the contents of H (i.e. 25H ) to A.
So, A = 25H
ANI F0 H ; Contents of A are ANDed with F0H and result is stored
in A.
A : 0010 0101
F0H : 1111 0000
0010 0000 = 20 H
So, A = 20 H
MOV H, A ; Moves the contents of A (i.e. 20H ) to H.
So, H = 20H
HLT ; Halts the execution of program.
So, after executing the above set of instructions in sequence the contents of A, H and L
registers are 20H, 20H and F1H respectively.
Ex. 6.12 The following program is written for an 8085 microprocessor to add two bytes located at
memory addresses 1FFEH and 1FFFH
LXI H, 1FFEH
MOV B, M
Instruction Set of 8085 155
INR L
MOV A,M
ADD B
INR L
MOV M, A
XRA A
What is memory location at which the result of addition is found on completion of the
execution of the above program.
GATE(EE,03)
Solutions:

LXI H, 1FFEH ; Loads HL pair with 1FFEH. So, H= 1FH and L = FEH
MOV B, M ; Moves the contents of memory location whose address
is stored in HL pair (i.e 1FFEH ) to register, B.
INR L ; Increases the contents of register L by one. So,
L = FFH.
MOV A,M ; Moves the contents of memory location whose address
is stored in HL pair (i.e 1FFFH ) to register, A.
ADD B ; Adds the contents of register B to register A and stores
the result in A. So the contents of memory location
1FFEH that are in register B are added to contents of
memory location 1FFFH that are in register A and sum
is stored in A only.
INR L ; Increases the contents of register L by one. So,L =
00H.
MOV M, A ; Moves the contents of accumulator A to memory
location whose address is stored in HL pair (i.e 1F00H).
XRA A ; The contents of A are Ex-ORed either with contents of
A itself and result is stored in A only. This instruction
will clear the accumulator and set the zero flag and
reset the carry flag.
So, the sum of two bytes stored at 1FFEH and 1FFFH will be stored at memory location
1F00H.
Ex.6.13 The following 8085 instructions are executed sequentially
XRA A
MOV L, A
MOV H, L
INX H
DAD H
What the contents of HL pair after execution of above program?
GATE(IN,04)
Solution:
XRA A ; Performs ExOR operation on the contents of A and
stores the r esult in A. The operation clears the
156 Microprocessor 8085
accumulator.
MOV L, A ; Copy the contents of A (i.e.00H) into L. So,L =00H
MOV H, L ; Copies the contents of L (i.e.00H) into H. So. H =00H
INX H ; Increment the contents of HL pair by one. So,
HL=0001H.
DAD H ; Adds the contents of HL pair (i.e. 0001H) to contents
of HL pair(i.e.0001H) and stores the result in HL pair.
HL: 0000 0000 0000 0001
HL :0000 0000 0000 0001
0000 0000 0000 0010
0 0 0 2
So, now contents of HL pair after the execution of program becomes 0002H.
Ex.6.14 The following program starts at location 0100H.
LXI SP, 000FH
LXI H, 0701H
MVI M, 00H
MVI A, 20H
SUB M
If in addition following code exists from 0109H onwards,
ORI 40H
ADD M
What will be the result in the accumulator after the last instruction is executed?
GATE(EC,05)
Solution:
0100H LXI SP, 000FH ; Initializes the stack pointer with 000F H address
0103H LXI H, 0701H : Loads HL pair with 0701H. So, H = 07H and L = 01H
0106H MVI M, 00H ; Moves 8 bit data 00H to memory location whose address
is stored in HL pair. So, 00H is moved to memory
location 0701H.
0108H MVI A, 20H ; Moves 8-bit data 20H to accumulator. So, A= 20H
So, the contents of A is 20H when program counter
reaches 0109H
010AH ORI 40H ; The contents of A(i.e.20H) are ORed with 8-bit data
40H.
20H : 00100000
40H : 01000000
01100000

A 60H
010CH ADD M ; Adds the contents of memory location, whose address
is stored in HL pair (i.e. 0701H) to the contents of
Instruction Set of 8085 157
A(i.e. 60H) and stores the result in A.
60 H : 01100000
00 H : 00000000
01100000
A 60H
The content of accumulator after the last instruction is executed is 60H
6.4.4 Machine Control Instructions

1. HLT Halt the execution of program

i.
1-byte instruction
ii.
No addressing mode
iii.
Two or more machine cycles & 5 or more T-
iv.
states
v. No flag is affected.
Note: When HLT statement is given , the microprocessor completes the execution of
current instruction and halts further execution. The microprocessor enters into Halt
acknowledgment machine cycle and Wait states are inserted in every clock cycle.
All the address and data buses are tri-stated (High impedance state) and contents
of registers are unaffected during execution of HLT instruction. The processor
can be brought out of the wait state either by pressing RESET key or by giving an
interrupt.
2. NOP i. No operation is performed.
ii. 1-byte instruction
iii. No addressing mode
iv. One machine cycle (OP) & 4 T-states
v. No flag is affected.
Note: NOP instruction is used to introduce a delay of 4 T states between two successive
instructions.
Ex.6.15. In 8085 with 2 MHz clock frequency, what is the time delay obtained after execution of
4 NOP instructions ?
IAS(2007)
Solution:
The instruction NOP require only Opcode fetch machine cycle.
No. of T-states in opcode fetch machinecycle = 4
No. of T-states required in 4 NOP instructions = 16
One T state is precisely equal to one time period of clock signal.
1
So,Time of one T-state, T = s
2
1
Time of 16 T-states = 16T = 16 =8 s
2
158 Microprocessor 8085
So, execution of 4 NOP instructions introduces a time delay of 8 s.
6.4.5 Jump Instructions
I. Unconditional jump instruction:
1. JMP 16 bit address i. Jump execution of program immediately at the
given 16-bit address
ii. 3-byte instruction
iii. Immediate addressing mode
iv. Three machine cycles (OP+MR+MR) &10 T-
states
v. No flag is affected.
II. Conditional jump instruction.
1. JC 16 bit address - Jump if CY = 1
2. JN C 16 bit address - Jump if CY = 0
3. JZ 16 bit address - Jump if Z = 1
4. JNZ 16 bit address - Jump if Z = 0
5. JP 16 bit address - Jump if plus i.e. S = 0
6. JM 16 bit address - Jump if minus i.e S = 1
7. JPE 16 bit address - Jump if P = 1
8. JPO 16 bit address - Jump if P = 0
i. Jump execution of program immediately at the
given 16-bit address if condition is true
ii. 3-byte instruction
iii. Immediate addressing mode
iv. a. Three machine cycles (OP+MR+MR) & 10
T-states if condition is true
b. Two machine cycles & 7 T-states if condition
is false
v. No flag is affected
Note : When jump instruction is executed by microprocessor it takes total three machine cycles.
During first machine cycle it fetches the Opcode of instruction. During second and third
machine cycles it reads the address which is operand of the instruction and stores it in
temporary register pair WZ. Then microprocessor places the address of from WZ pair on
address lines to transfer the execution to new address. The program counter is then loaded
with WZ +1 i.e address of next byte to be fetched and thereafter normal execution is
resumed through program counter. In conditional return microprocessor checks the conditon
during first two machine cycles and does not go for third machine cycle if the condition fails.

Ex.6.16 Consider the program given below, which transfers a block of data from one place in
memory to another :
MVI C, 0BH
Instruction Set of 8085 159
LXI H, 2400H
LXI D, 3400H
L1 : MOV A, M
STAX D
INR L
INR E
DCR C
JNZ LI
What is the total number of memory accesses (including instruction fetches) carried out ?
IES(EE,05)
Solution:
Mnemonic Operand No. of machine cycles/memory accesses
MVI C, 0BH 2
LXI H,2400H 3
LXI D, 3400H 3
L1 : MOV A, M 2
STAX D 2
INR L 1
INR E 1
DCR C 1
JNZ LI 3 or 2
Instructions before L1 needs 8 memory accesses and L1 to JNZ L1 requires 10 memory
accesses during each iteration upto last iteration but 9 machine cycles in last iteration when
Z = 0. The loop is executed 11 times till the contents of C becomes zero. So, the total number
of memory accesses are 8 + 10*10 + 9 = 117. JNZ requires 2 machine cycles when
condition is false. So total machine cycles will be 117.
Ex.6.17 Consider the following program intended to transfer a block of 5 bytes from A000H to
9000H:
START: LXI B, 9000H
LXI H, A000H
MVI C, 05H
LOOP: MOV A, M
STAX B
INX B
INX H
DCR C
JNZ LOOP
HLT
The above program will not work properly. Find out the reason.
IES(E&T,04)
Solution:
START: LXI B, 9000H
LXI H, A000H
MVI C, 05H
160 Microprocessor 8085
LOOP: MOV A, M
STAX B
INX B
INX H
DCR C
JNZ LOOP
HLT
The above program is intended to transfer a block of 5 bytes from A000H to 9000H, will not
work because the instruction INX B in the loop increases the BC pair by ‘1’ , the instruction
DCR C again restore same contents in BC pair as before execution of INX B. So, the
contents of register ‘C’ will never become Zero and instruction DCR C will not set the zero
flag and program will enter into infinite loop. The program will work properly if another
register such as D is used as counter instead of register C.
The correct program will as under,
START: LXI B, 9000H
LXI H, A000H
MVI D, 05H
LOOP: MOV A, M
STAX B
INX B
INX H
DCR D
JNZ LOOP
HLT
Ex.6.18 Consider the following assembly language program,
MVI B,87H
MOV A, B
START: JMP NEXT
MVI B, 00H
XRA B
OUT PORT 1
HLT
NEXT: XRA B
JP START
OUT PORT 2
HLT
What is result after execution of the above program in an 8085 microprocessor.
GATE(EC,02)
Solution:
The Sequence of execution of above program will be as under,
MVI B,87H ; Moves 87 H to B
MOV A, B ; Moves the contents of B (i.e. 87 H) to A. So, A = 87
H
Instruction Set of 8085 161
START:JMP NEXT ; Jumps to NEXT unconditionally
NEXT: XRA B ; Contents of B (i.e. 87H) are ExORed with contents of
A(i.e. 87H) and result is stored in A.
A B : 10000111
10000111
00000000
A = 00H
JP START ; Jumps to START if sign flag is reset. As XRA B in
previous step resets the sign flag so the program jumps
back to START.
START: JMP NEXT ; Jumps to NEXT unconditionally
NEXT: XRA B ; Contents of B (i.e. 87H) are ExORed with contents of
A(i.e. 00H) and result is stored in A.
A B : 00000000
10000111
10000111
A = 87H
As D7 bit of A is high so sign(S) flag is set.
JP START ; Jumps to START if sign flag is reset.
As XRA B in previous step sets the sign flag so the
program comes out of loop.
OUT PORT 2 ; Sends contents of A(i.e. 87H) to I/O device of PORT2
HLT ; Halts the execution of program.
Thus, program displays 87 H at port 2.

Ex.6.19 An Intel 8085 processor is executing the program given below.

MVI A, 10H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
What is the number of times that the instruction NOP will be executed?
IAS(2006)
Solution:
MVI A, 10H ; Moves data 10H to A.
MVI B, 10H ; Moves data 10H to register B.
BACK : NO P ; No operation
162 Microprocessor 8085
ADD B ; Adds contents of register B(i.e. 10H) to A(i.e. 10H)
and store result in A.
10H : 00010000
10H : 00010000
00100000

A 20 H and CY = 0
RLC ; Rotates contents of accumulator to left without carry
flag.
Before rotation:
CY 0
0 0 1 0 0 0 0 0
After rotation:
CY 0
0 1 0 0 0 0 0 0

A 40H and CY = 0
JNC BACK ; Jumps to BACK if CY = 0
HLT ; Halts the execution
After execution of RLC instruction 3 times CY flag will be set. So, the instruction NOP will
be executed three times in the given program.

Ex.6.20 How many time will the following loop be executed?

LXI B, 0010 H
LOOP: DCX B
MOV A,B
ORA C
JNZ LOOP
IES(EE,06)
Solution :
LXI B, 0010 H ; Loads BC pair with 0010H. So, B = 00H and C = 10H.
LOOP: DCX B ; Decreases the contents of BC pair by 1.
MOV A,B ; Moves the contents B (i.e. 00H) to A.
ORA C ; Contents of C are ORed with contents of A and results
are stored in A.
A OR C : 00000000
00001111
00001111
Instruction Set of 8085 163
A 0 FH
JNZ LOOP ; Jumps to LOOP until Z = 1
During the first execution of loop C=0FH and during last execution of loop C =00H . As C
is decremented by 1 every time so , the loop will be executed 16 times before the execution
comes out of loop.
Ex.6.21 A software delay subroutine is written as given below :
DELAY: MVI H, 255 D ; 255 D is in decimal
MVI L, 255 D ; 255 D is in decimal
LOOP: DCR L
JNZ LOOP
DCR H
JNZ LOOP
How many times DCR L instruction will be executed ?
GATE(EE,06)
Solution :
DELAY: MVI H, 255 D ; Moves decimal number 255 in register H.
MVI L, 255 D ; Moves decimal number 255 in register L.
LOOP: DCR L ; Decrements L by ‘1’
JNZ LOOP ; First time DCR L runs for 255 times and second time
onward DCR L is executed 256 times as because
second time onward contents of L also changes from
00H to FF H .
DCR H ; Decrements H by ‘1’
JNZ LOOP ; Jumps to LOOP until contents of H becomes zero. It
will run the loop 255 times.
During first run DCR L is executed 255 times. From second run onward DCR L is executed
256 times.
So, total number times DCR L will be executed will be 255 + 254*256 = 65279

Ex.6.22 8-bit signed integers in 2’s complement form are read into the accumulator of an 8085 micro-
processor from an I/O port using the following assembly language program segment with sym-
bolic addresses
BEGIN : IN PORT
RAL
JNC BEGIN
RAR
END: HLT
What is final outcome of above program?
GATE(IN,07)
Solution :
BEGIN : IN PORT ; Reads the data into accumulator from IO device
connected at PORT.
164 Microprocessor 8085
RAL ;Rotates the contents of accumulator to left through carry
flag.
JNC BEGIN ; Jumps to BEGIN if CY is not set.
RAR ; Rotates the contents of accumulator to right through
carry flag.
END: HLT ; Halts the execution of program.
When number read from IO device is negative number , the bit D7 of accumulator is ‘1’. So
the instruction RAL will set the carry flag and program execution will not jump to BEGIN
when it executes JNC BEGIN instruction as CY=1. So, the execution will continue with
RAR instruction and at end the program execution will halt after execution of HLT instruction.

Ex.6.23 A part of a program written for an 8085 microprocessor is shown below.

SUB A
MOV C,A
LOOP 1: INR A
DAA
JC LOOP2
INR C
JNC LOOP 1
LOOP 2: NOP
When the program execution reaches LOOP2, what are contents of register C?
GATE(IN,08)
Solution:
SUB A ; Subtracts the contents of A from A and store the result
in A. Instruction clears the accumulator , A. So, A = 00
H.
MOV C,A ; Moves the contents of A to register C. So, C = 00H
LOOP 1: INR A ; Increments the contents of A by one.
DAA ; Converts the contents of A to BCD equivalent.
JC LOOP2 ; Jumps to LOOP2 if carry flag is set.
INR C ; Increments the contents of C by one.
JNC LOOP 1 ; Jumps to LOOP1 if carry flag is reset.
LOOP 2: NO P ; No operation.
The program will remain in LOOP1 till BCD equivalent in A is less than 100. When BCD
equivalent in A becomes 100 carry flag is generated and execution is transferred to LOOP2,
The contents of C by that time will be Hexadecimal equivalent of 99 which is 63 H.

6.4.6 Stack and Its Related Instructions

Stack is the group of memory locations used by the microprocessor or programmer to
store the data temporarily during the execution of a program. The stack can be used to
store the contents of program counter (PC) by the microprocessor automatically when
a subroutine is called. The stack can also be used by the programmer for storing the
contents of register pairs of BC, DE, HL & PSW (Program Status word). Program
Status Word indicates the contents of Accumulator and Flag register. Here Accumulator
Instruction Set of 8085 165
is considered as higher order and Flag register is considered as lower order register.
Top of the stack is pointed by a 16 bit register called stack pointer(SP). The stack
pointer is the programmable register which always stores the address of top most location
of the stack. The stack pointer can be initiated by the instruction, LXI SP, 16 bit data.
The contents of a register pair can be stored on the top of the stack by using PUSH
instruction and contents from the top of the stack can be loaded in to a regster pair
using POP instruction. Stack pointer is always decremented by 2 after the execution of
each PUSH instruction and it is incremented by 2 after the execution of each POP
instructions. It works on the principle of last-in first-out. The information on stack is not
destroyed until new information is stored in those locations.
Note: The data storage on the stack begins from the address next to the address with which
stack pointer is initiated. For example when SP is initiated with 2000H the data storage
will begin from 1FFF H.
Note: Stack pointer must be initiated before using PUSH, POP or Call instructions.
The Instructions Related to Stack :
1. PUSH RP i. Store the contents of register pair Rp on two
Rp BC, DE, HL & PSW top locations of stack.
ii. 1-byte instruction
iii. Register indirect addressing mode
iv. Three machine cycles (OP+MW+MW) & 12
T-states
v. No flag is affected
Note: PSW (Program Status Word) represents the contents of the accumulator and the flag
regiser; the accumulator is high order register and the flag register is low order register.
Note: PUSH instruction first decrements the SP by one and then copies the contents of
higher order register of pair Rp on the location shown by stack pointer . Then stack
pointer register is again decremented by one and the content of lower order register of
pair Rp are copied on the location shown by stack pointer. Thus stack pointer is
decremented by two after execution of PUSH instruction.

2. POP RP i.Retrieve the contents of two top locations of

Rp BC, DE, HL & PSW stack to register pair Rp .
ii. 1-byte instruction
iii. Register indirect addressing mode
iv. Three machine cycles (OP+MR+MR) & 10 T-
states
v. No flag is affected
Note: POP instruction first copies the contents of memory location indicated by stack pointer
(SP) to lower order register of pair Rp and then increment stack pointer by one . It again
copies the contents of memory location indicated by SP to higher order register of pair
Rp and then increment stack pointer by one. Thus stack pointer is incremented by two
after execution of each POP instruction.
3. XTHL i. Exchange the contents of two top locations of stack
166 Microprocessor 8085
with contents of HL pair.
ii. 1-byte instruction
iii. Register indirect addressing mode
iv. Five machine cycles (OP+MR+MR + MW + MW)
&16 T-states
v. No flag is affected.
Note: The contents of L are exchanged with location indicated by SP and contents of H are
exchanged with memory location (SP+1). However , the contents of SP remains
unaltered.
Note: All instructions related to stack have indirect addressing mode.
Ex.6.24 Consider the following Assembly Language program :
MVI A, 30H
ADI 30H
XRA A
POP H
What are the contents of A at the end of program.
IES(EE,98)
Solutions:
MVIA, 30H ; Moves data 30H to A
ADI 30H ; Adds 30H to contents of A and store result in A.
A A : 00110000
00110000
01100000
A = 60H
XRA A ; Performs ExOR operation the contents of A and store
result in A.
A A : 01100000
01100000
00000000
A = 00H
POP H ; Moves the contents of top of stack to HL pair.
Thus, the contents of A after the execution of program will be A = 00H
Ex.6.25 In a 8085 microprocessor the value of the stack pointer (SP) is 2010H and that of
DE register pair is 1234H before the following code is executed.
LXI H, 0000H
PUSH H
PUSH H
POP B
DAD SP
XCHG
Instruction Set of 8085 167
What are contents of the DE register pair after the execution of above program?
GATE(IN,05)
Solution:
Given, Contents of DE =1234H
Contents of SP =2010H
LXI H, 0000H ; Loads HL pair with 0000 H. So, H= 00H and L = 00H
PUSH H ; Stores the contents of HL pair on the top of the stack.
The stack pointer is first decremented by one from
2010H to 200FH and then contents of H(i.e.00H) are
stored at 200FH, the stack pointer is again decremented
by one from 200FH to 200EH and then contents of
L(i.e.00H) are stored at 200EH. So at end of instruction,
contents of SP are 200EH, contents of 200EH are 00H
and contents of 200FH are 00H.
PUSH H ; Stores the contents of HL pair on the top of the stack.
The stack pointer is first decremented by one from
200EH to 200DH and then contents of H(i.e.00H) are
stored at 200DH, the stack pointer is again decremented
by one from 200DH to 200CH and then contents of
L(i.e.00H) are stored at 200CH. So at end of instruction,
contents of SP are 200CH, contents of 200CH are 00H
and contents of 200DH are 00H.
POP B ; Stores the contents of top of stack in BC pair. The
contents of 200CH(i.e.00H) are store in C and then
stack pointer is incremented by one from 200CH to
200DH and then contents of 200DH(i.e.00H) are stored
in B, the stack pointer is again incremented by one from
200DH to 200EH. So at end of instruction, contents of
SP are 200EH, contents of B are 00H and contents of
C are 00H.
DAD SP ; Adds the contents of stack pointer(i.e. SP=200EH) to
contents of HL pair(i.e.0000H) and store the result in
HL pair and contents of SP remains unaltered.
HL : 0000 0000 0000 0000
SP : 0010 0000 0000 1110
0010 0000 0000 1110
2 0 0 E
So, now contents of HL pair becomes 200EH
XCHG ; Exchanges the contents of HL pair(i.e. 200EH) with
contents of DE pair(i.e.1234H). At end of instruction
HL=1234H and DE = 200EH.
168 Microprocessor 8085
The value of the DE register pair after the execution of program is 200EH.

6.4.7 Call Instructions

Call instructions are used to call a subroutine during execution of a main program. A
subroutine is a set of instructions used to perform a task repeatedly.
I. Unconditional Call Instruction
1. CALL 16 bit address i. Call immediately the subroutine stored at the
given 16- bit address
ii. 3-byte instruction
iii. Immediate/Register Indirect addressing mode
iv. Five machine cycles (OP+MR+MR+MW+MW)
& 18 T-states
v. No flag is affected.
II. Conditional Call Instructions
1. CC 16 bit address - Call if CY = 1
2. CNC 16 bit address - Call if CY = 0
3. CZ 16 bit address - Call if Z = 1
4. CNZ 16 bit address - Call if Z = 0
5. CP 16 bit address - Call if plus i.e. S = 0
6. C M 16 bit address - Call if minus i.e S = 1
7. CPE 16 bit address - Call if P = 1
8. CPO 16 bit address - Call if P = 0
i. Call immediately the subroutine stored at the
given 16- bit address if condition is true.
ii. 3-byte instruction
iii. Immediate/Register Indirect addressing mode
iv. a. Five machine cycles (OP+MR+MR + MW
+ MW) &18 T-states if condition is true.
b. Two machine cycles & 9T-states if condition
is false.
v. No flag is affected
Note : When CALL instruction is executed by microprocessor it takes total five machine cycles.
During first machine cycle it fetches the Opcode of instruction. During second and third
machine cycles it reads the address of subroutine and stores in temporary register pair WZ.
In the 4th and 5th machine cycles the microprocessor saves the contents of Program
Counter(PC), which has address of next instruction is to be executed, on the top of stack.
So, stack pointer must be initiated in the main program before calling of subroutine.After
saving the contents of program counter on the top of stack the microprocessor places the
address of subroutine, from WZ pair, on address lines to transfer the execution to subroutine.
The program counter is then loaded with WZ +1 i.e address of next byte to be fetched.
Note : During execution of conditional call instructions if condition is true the number of machines
cycles are same as in case of unconditional call but if condition is false only two machines
cycles are required.
Instruction Set of 8085 169

Ex.6.26 The following sequence of instructions are executed by an 8085 microprocessor:

1000 LXI SP, 27FFH
1003 CALL 1006H
1006 POP H
What will be contents of the stack pointer (SP) and the HL, register pair on completion of
execution of these instructions?
GATE(EC,96)
Solution:
1000 LXI SP, 27FFH ; Initializes the stack pointer with 27FFH.
1003 CALL 1006H ; Saves the contents of program counter (i.e. address of
next instruction, 1006H) on top of stack and call the
subroutine stored at address 1006H . During the saving
the contents of program counter the stack pointer is
decremented by one and 10H is saved at 27FEH and
stack pointer is again decremented by one& 06H is
saved at 27FDH.
1006 POP H ; Retrieves the contents of top of stack in HL pair. During
poping up of stack the contents of 27FDH (i.e.06H )
are stored in L and stack pointer is incremented by one
to 27FEH. Then the contents of next memory location
27FEH (i.e. 10H)are stored in H and stack pointer is
again incremented by one to 27FFH.
Therefore, the contents of the stack pointer (SP) and the HL register pair on completion of
execution of these instructions are SP = 27FFH and HL = 1006H.
Ex.6.27 The stack pointer of an 8085A microprocessor contains ABCDH.
PUSH PSW
XTHL
PUSH D
JMP EC75H
At the end of the execution of the above instructions, what would be the content of the stack
pointer?
IES(EE,08)
Solution :
Given, SP = ABCDH
PSW stands for Program Status Word. It is a 16 bit combination of Accumulator and flag
register. Accumulator is higher order and flag register is lower order register.
PUSH PSW ; This instruction first decrements the SP by one from
ABCDH to ABCCH and then copies the contents of
accumulator on the location shown by stack pointer
register(i.e. ABCCH). Then stack pointer register is
decremented by one and the content of flag register
170 Microprocessor 8085
are copied on the next memory location(i.e.ABCBH).
The contents of SP becomes ABCBH
XTHL ; Exchanges the contents of HL pair with top of
stack.Contents of ABCBH are exchanged with L and
contents of ABCCH are exchanged with H. But after
execution of XTHL the stack pointer points at ABCBH.
So, the contents of SP remain ABCBH.
PUSH D ; Pushes the contents of DE pair on top of stack. First
stack pointer is decrement by one to ABCA H and
then contents of D are store at ABCAH . The stack
pointer is again decremented by one to ABC9H and
then contents of E are stored at ABC9H
JMP EC75H ; The program execution jumps to memory location
EC75H , unconditionally.
At the end of execution of above instruction the contents of Stack pointer are ABC9H.

6.4.8 Return Instructions

Return instructions are used at the end of the subroutine. When microprocessor encounters
a return instruction , the execution of the program is returned to the main program.
I. Unconditional Return Instruction
1. RET i. Return to main program unconditionally
ii. 1-byte instruction
iii. Register Indirect addressing mode
iv. Three machine cycles (OP+MR+MR) & 10
T-states
v. No flag is affected.

II. Conditional Return Instructions

1. RC - Return if CY = 1
2. RNC - Return if CY = 0
3. RZ - Return if Z = 1
4. RNZ - Return if Z = 0
5. RP - Return if plus i.e. S = 0
6. RM - Return if minus i.e S = 1
7. RPE - Return if P = 1
8. RPO - Return if P = 0
i. Return to main program if condition is true.
ii. 1-byte instruction
iii. Register Indirect addressing mode
iv. a. Three machine cycles (OP+MR+MR) &12
T-states if condition is true.
b. One machine cycles & 6 T-states if condition
is false.
Instruction Set of 8085 171
v. No flag is affected.
Note 1: When RET instruction is executed by microprocessor it takes three machines cycles. During
first machine cycle miroprocessor fetches the Opcode and during second and third machines
it reads the contents of top of stack and stores in temporary register pair WZ. The contents
of WZ pair are ,then, placed on address lines and program counter is loaded with WZ +1
i.e. address of next byte to be fetched.
Note 2 : During execution of conditional return instructions if condition is true the number of machines
cycles are same as in case of unconditional return but if condition is false only one machines
cycle is required.
Ex.6.28 In an 8085 based system the subroutine TEST given below is called by another program.
TEST: MVI A, 00H
CALL TEST1
TEST1: INR A
RET
What are the contents of the accumulator when the processor returns from the subroutine
TEST?
GATE(IN,02)
Solution :
TEST: MVI A, 00H ; Moves 00H to register A. So, A = 00H
CALL TEST1 ; Calls the subroutine TEST1.
TEST1: INR A ; Increments the contents of A by one.
RET ; Returns to main program.
In the above program the instructions INR A is executed twice. Once by calling of TEST1
by Subroutine TEST and once by subroutine TEST itself. So, the contents of accumulator
are incremented twice. Therefore, the contents of A after returning from subroutine TEST
will be 02H.
Ex.6.29 Following is the segment of a 8085 assembly language program:
LXI SP, EFFF H
CALL 3000 H
:
:
3000 H : LXI H, 3CF4 H
PUSH PSW
SPHL
POP PSW
RET
What are the contents of SP on completion of RET execution?
GATE (EC,06)
Solution :
LXI SP, EFFF H ; Loads SP with EFFFH
CALL 3000 H ; Calls a subroutine stored at address 3000H. The
contents of program counter are stored on top of stack
at memory location EFFE and EFFD respectively.
172 Microprocessor 8085
:
:
:
3000 H : LXI H, 3CF4 H ; Loads HL pair with 3CF4 H
PUSH PSW ; This instruction first decrement the SP by one from
EFFD to EFFC and then copies the contents of
accumulator on the location shown by stack pointer
register(i.e. EFFC H). Then stack pointer register is
decremented by one and the content of flag register
are copied on the next memory location(i.e. EFFB H).
The contents of SP becomes EFFB H
SPHL ; Moves the copy of contents of HL pair(i.e. 3CF4 ) in
SP pointer. So, contents of SP becomes 3CF4.
POP PSW ; Stores the contents of location indicated by stack pointer
(i.e. 3CF4) in F and and and stack pointer is then
incremented by one to 3CF5 and then contents of 3CF5
are stored in A register. So the contents of 3CF4 are
stored in flag register and contents of 3CF5 in
Accumulator and stack pointer is updated to 3CF6.
RET ; Reads the contents of top of stack in temporary register
pair WZ. The contents of 3CF6 goes to Z and that of
3CF7 goes to W register and stack pointer is updated
to 3CF8 H.
Thus , contents of SP are 3CF8 H after execution of RET instruction.

GATE QUESTIONS
Q.1 The total number of memory accesses involved (inclusive of the op-code fetch) when an
8085 processor executes the instruction LDA 2003 is
(a) 1 (b) 2
(c) 3 (d) 4
GATE(EC.96)
Q.2 In an 8085 microprocessor, the instruction CMP B has been executed while the content of
the accumulator is less than that of register B. As a result
(a) Carry flag will be set but Zero flag will be reset
(b) Carry flag will be reset but Zero flag will be set
(c) Both Carry flag and Zero flag will be reset
(d) Both Carry flag and Zero flag will be set
GATE(EC,03)
Instruction Set of 8085 173
Q.3 The number of memory cycles required to execute the following 8085 instructions
(I) LDA 3000 H
(II) LXI D, F0F1 H
would be
(a) 2 for (I) and 2 for (II) (b) 4 for (I) and 3 for (II)
(c) 3 for (I) and 3 for (II) (d) 3 for (I) and 4 for (II)
GATE(EC,04)
Q.4 Consider the sequence of 8085 instructions given below.
LXI H, 9258
MOV A, M
CMA
MOV M, A
Which one of the following is performed by this sequence?
(a) Contents of location 9258 are moved to the accumulator
(b) Contents of location 9258 are compared with the contents of the accumulator
(c) Contents of location 8529 are complemented and stored in location 8529
(d) Contents of location 5892 are complemented and stored in location 5892
GATE(EC,04)
Q.5 If the HLT instruction of a 8085 microprocessor is executed,
(a) the microprocessor is disconnected from the system bus till the Reset is pressed
(b) the microprocessor enters into a Halt state and the buses are tri-stated
(c) the microprocessor halts execution of the program and returns to monitor
(d) the microprocessor reloads the program from the locations 0024 and 0025 H.
GATE(EE,92)
Q.6 The contents of the accumulator in an 8085 microprocessor is altered after the execution of
the instruction.
(a) CMPC (b) CPI 3 A
(c) ANI 5 C (d) ORA A
GATE(EE,94)
Q.7 In an 8085 microprocessor, after the execution of XRA A instruction
(a) the carry flag is set
(b) the accumulator contains FFH
(c) the zero flag is set
(d) the accumulator contents are shifted left by one bit
GATE(EE,95)
Q.8 The 8085 assembly language instruction that stores the contents of H and L registers into
the memory locations 2051 H and 2050H, respectively, is
(a) SPHL 2050H (b) SPHL 2051H
(c) SHLD 2050H (d) STAX 2050H
GATE(EE,05)
Q.9 In 8085 microprocessor, CY flag may be set by the instruction
(a) SUB (b) INX
(c) CMA (d) ANA
GATE(IN,01)
Q.10 For an 8085 microprocessor, the Stack Pointer (SP) and Program Counter (PC) registers
174 Microprocessor 8085
contain the number 2400H and F000H in Hex respectively. The contents of the register
after execution of the instruction CALL E000H would be
(a) PC : F003H SP : 2400H (b) PC : E000H SP : 2400H
(c) PC : E000H SP : 2401H (d) PC : E000H SP : 23FEH
GATE(IN,00)
Q.11 Find the correct match among the following pair in the context of an 8085 microprocessor.

a. DAA e. Program control instruction

b. LXI f. Data movement instruction
c. RST g. Interrupt instruction
d. JMP h. Arithmetic instruction

(a) a-e, b-f, c-g, d-h (b) a-h, b-f, c-g, d-e
(c) a-h, b-g, c-f, d-e (d) a-f, b-h, c-g, d-e
GATE(IN,00)
Q.12 A memory mapped I / O device has an address of 00F0H. Which of the following 8085
instructions outputs the content of the accumulator to the I/O device?
(a) LXI H, 00F0H (b) LXI H, OOFOH
MOV M, A OUT M
(c) LXI H, 00F0H (d) LXI H, 00F0H
OUT F0H MOV A, M
GATE(IN,06)
Q.13 In an 8085 A microprocessor based system, it is desired to increment the contents of memory
location whose address is available in (D,E) register pair and store the result in same location.
The sequence of instructions is
(a) XCHG (b) XCHG
INR M INX H
(c) INX D (d) INR M
XCHG XCHG
GATE(EE,06)
Q.14 An 8085 assembly language program is given below.
Line 1 : MVI A, B5H
2 : MVI B, 0EH
3 : XRI 69H
4 : ADD B
5 : ANI 9BH
6 : CPI 9FH
7 : STA 3010H
8 : HLT
The contents of the accumulator just after execution of the ADD instruction in line 4 will be
(a) C3H (b) EAH
(c) DCH (d) 69H
GATE(EC,07)
Instruction Set of 8085 175
Q.15 In an 8085 microprocessor, the contents of the Accumulator, after the following instructions
are executed will become
XRA A
MVI B, F0H
SUB B
(a) 01 H (b) 0F H
(c) F0 H (d) 10 H
GATE(EE,09)
Q.16 The following is an assembly language program for 8085 microprocessors
Address Instruction Code Mnemonic
1000H 3E 06 MVI A,06H
1002H C6 70 ADI 70 H
1004H 32 07 10 STA 1007H
1007H AF XRA A
1008H 76 HLT
When this program halts, the accumulator contains
(a) 00H (b) 06H
(c) 70H (d) 76H
GATE(IN,09)
Q.17 For the 8085 assembly language program given below, the content of the accumulator after
the execution of the program is
3000 MVI A , 45 H
3002 MOV B, A
3003 STC
3004 CMC
3005 RAR
3006 XRA B
(a) 00H (b) 45H
(c) 67 H (d) E7H
GATE(EC,10)
Q.18 When a “CALL Addr” instruction is executed, the CPU carries out the following sequential
operations internally :
Note :–
(R) means content of register R
((R)) means content of memory location pointed to by R
PC means Program Counter
SP means Stack Pointer
(a) (SP) incremented (b) (PC) Addr
(PC) Addr ((SP)) (PC)
((SP)) (PC) (SP) incremented
(c) (PC) Addr (d) ((SP)) (PC)
(SP) incremented (SP) incremented
((SP)) (PC) (PC) Addr
GATE(EE,10)
Q.19 In an 8085 processor, the main program calls the subroutine SUB1 given below. When the
176 Microprocessor 8085
program returns to the main program after executing SUB1, the value in the accumulator is
Address Opcode Mnemonic
2000 3E 00 SUB1 : MVI A,00H
2002 CD 05 20 CALL SUB2
2005 3C SUB2 : INR A
2006 C9 RET
(a) 00 H (b) 01 H
(c) 02 H (d) 03 H
GATE(IN,10)
Q.20 The subroutine SBX given below is executed by an 8085 processor. The value in the
accumulator immediately after the execution of the subroutine will be.
SBX : MVI A, 99 H
ADI 11H
MOV C,A
RET
(a) 00 H (b) 11 H
(c) 99 H (d) AA H
GATE(IN,10)
Q.21 An 8085 assembly language program is given below. Assume that the carry flag is initially
unset. The contents of the accumulator after the execution of the program is
MVI A,07H
RLC
MOV B,A
RLC
RLC
ADD B
RRC
(a) 8CH (b) 64 H
(c) 23H (d) 15H
GATE(EC,11)
Q.22 A portion of the main program to call a subroutine SUB in an 8085 environment is given
below.
:
:
LXI D, DISP
LP : CALL SUB
:
:
It is desired that control be returned to LP + DISP + 3 when the RET instruction is executed
in the subroutine. The set of instruction that precede the RET instruction in the subroutine
are
(a) POP D (b) POP H
DAD H DAD D
PUSH D INX H
INX H
Instruction Set of 8085 177
INX H
PUSH H
(c) POP H (d) XTHL
DAD D INX D
PUSH H INX D
INX D
XTHL
GATE(EE,11)
Q.23 The contents (in Hexadecimal) of some of the memory locations in an 8085A based system
are given below:

Address Contents

26FF 00
26FF 01
2700 02
2701 23
2702 04

The contents of stack pointer (SP), program counter (PC) and (HL) are 2700H, 2100H and
0000H respectively. When the following sequence of instructions are executed.
2100 H: DAD SP
2101 H: PCHL
The contents of (SP) and (PC) at the end of execution will be
(a) (PC) = 2102H, (SP) = 2700H. (b) (PC) = 2700H, (SP) = 2700H.
(c) (PC) = 2800H, (SP) = 26FEH. (d) (PC) = 2A02H, (SP) = 2702H.
GATE(EE,08)
Q.24 An input device is interfaced with Intel 8085A microprocessor as memory mapped I/O. The
address of the device is 2500H. In order to input data from the device to accumulator, the
sequence of instructions will be
(a) LXI H, 2500H (b) LXI H,2500H
MOV A, M MOV M, A
(c) LHLD 2500H (d) LHLD 2500H
MOV A, M MOV M, A
GATE(EE,08)
Q.25 For 8085 microprocessor, the following program is executed.
MVI A, 05H;
MVI B, 05H;
PTR: ADD B;
DCR B;
JNZ PTR;
178 Microprocessor 8085
ADI 03H;
HLT;
At the end of program, accumulator contains
(A) 17 H (B) 20 H (C) 23 H (D) 05 H
GATE (EC, 13)
Q.26 In 8085 A microprocessor, the operation performed by the instruction LHLD 2100 H is
(a) (H) 21H, (L) 00H (b) (H) M(2100H), (L) M(2100H)
(c) (H) M(2101H), (L) M(2100H) (d) (H) 00H, (L) 21H
GATE (2014/EE-III/1 M)
Q.27 In an 8085 microprocessor, the following program is executed
2000 H XRA A
2001 H MVI B,04H
2003 H MVI A, 03H
2005 H RAR
2006 H DCR B
2007 H JNZ 2005
200 AH HLT
At the end of program, register A contains
(a) 60 H (b) 30 H
(c) 06 H (d) 03 H
GATE (2014/EE-II/2 M)
Q.28 In an 8085 microprocessor, the shift registers which store the result of an addition and the
overflow bit are, respectively
(a) B and F (b) A and F
(c) H and F (d) A and C
GATE (2015/EC-I/1 M)
Q.29 Which one of the following 8085 microprocessor programs correctly calculates the product
of two 8-bit numbers stored in registers B and C?
(a) MVI A, 00H (b) MVI A, 00H
JNZ LOOP CMP C
CMP C LOOP DCR B
LOOP DCR B JNZ LOOP
HLT HLT

(c) MVI A, 00H (d) MVI A, 00H

LOOP ADD C ADD C
DCR B JNZ LOOP
JNZ LOOP LOOP INR B
HLT HLT
GATE (2015/EC-III/1 M)
Q.30 In an 8085 microprocessor, which one of the following instructions changes the content of
the accumulator?
(a) MOV B, M (b) PCHL
Instruction Set of 8085 179
(c) RNZ (d) SBI BEH
GATE (2015/EC-II/1 M)
Q.31 In an 8085 system, a PUSH operation requires more clock cycles than a POP operation.
Which one of the following options is the correct reason for this?
(a) For POP, the data transceivers remain in the same direction as for instruction fetch
(memory to processor), whereas for PUSH their direction has to be reversed.
(b) Memory write operations are slower than memory read operations in an 8085 based
system.
(c) The stack pointer needs to be pre-decremented before writing registers in a PUSH,
whereas a POP operation uses the address already in the stack pointer.
(d) Order of registers has to be interchanged for a PUSH operation, whereas POP uses
their natural order.
GATE (2016/EC-I/2 M)
Q.32 In an 8085 microprocessor, the contents of the accumulator and the carry flag are A7 (in
hex) and 0, respectively. If the instruction RLC is executed, then the contents of the accu-
mulator (in hex) and the carry flag, respectively, will be
(a) 4E and 0 (b) 4E and 1
(c) 4F and 0 (d) 4F and 1
GATE (2016/EC-III/1 M)
Q.33 The following FIVE instructions were executed on an 8085 microprocessor.
MVI A, 33H
MVI B, 78H
ADD B
CMA
ANI 32H
The Accumulator value immediately after the execution of the fifth instruction is
(a) 00H (b) 10H
(c) 11H (d) 32H
GATE (EC-I/2017/ 2 M)
)

Answers & Explanations

Q.1 Ans (d)

LDA 2003 requires 13 T states and 4 machines cycles, out of which one is opcode fetch
and two memory read cycles for reading lower byte and higher byte of 16 bit operand and
one memory read for reading 2003 memory location.
Q.2 Ans (a)
The instruction CMP B, compares the contents of B with contents of accumulator. The
comparison is made by subtracting the contents of B from the contents of A. Depending
upon results of comparison various flags are affected as under,
I. A < B CY = set and Z = reset
180 Microprocessor 8085
II. A = B CY = reset and Z = set
III. A > B CY = reset and Z = reset
Given, A < B, so Carry flag will be set and Zero flag will be reset.
Q.3 Ans (b)
(I) LDA 3000 H ; This instruction load the accumulator with contents of
memory location 3000H. It needs 4 memory cycles out
of which one is opcode fetch and 3 memory read cycles.
(II) LXI D, F0F1 H ; This instruction load the DE pair with 16 bit F0F1H. It
needs 3 memory cycles out of which one is opcode
fetch and 2 memory read cycles.
Q.4 Ans (a)
LXI H, 9258H ; Loads HL pair with 16 bit data 9258H . So, H = 92H and
L = 58H.
MOV A, M ; Moves contents of memory location, whose address is
stored in HL pair, to accumulator. So the contents of
9258H are moved to A.
CMA ; Complements the contents of A.
MOV M, A ; Moves the contents of A to memory location , whose
address is stored in HL pair. So, the contents of A are
moved to 9258H.
The above program moves the contents of memory location 9258H. to accumulator and
compliments it and stores the result back to 9258 H..
Q.5 Ans (b)
If the HLT instruction of an Intel 8085A microprocessor is executed the microprocessor enters
into a HALT state and the buses are tri-stated
Q.6 Ans (c)
ANI 5C: 8 bit data 5C is ANDed with contents of A and result is stored in A , so, contents
of accumulator get modified.
CMP C : This instruction compares the contents of register C with the contents of
accumulater but contents of A and C remains unchanged.
CPI 3A : This instruction compares the 8 bit data 3A with the contents of accumulater but
contents of A and C remains unchanged.
ORA A: Contents of A are ORed with contents of A itself and result is stored in
A , but result of operation is same as contents before execution of ORA A. So,
contents of accumulator remains unchanged.
Q.7 Ans (c)
Let contents of A are 60 H
XRA A : Performs XOR operation the contents of A and store result in A.
A A : 01100000
01100000
00000000
Instruction Set of 8085 181
A 00 H
Since the contents of A are 00H after execution of XRA A instruction so zero flag is set.
Note : XRA A instruction can be used to reset CY & AC flags and set Z flag.
Q.8 Ans (c)
I. SPHL : Copies the contents of HL pair to stack pointer. No operand is required
in instruction. So the given instruction is incorrect.
II. SHLD 2050H : Stores the contents of HL pair directly on memory locations 2050H and
2051H . The contents of lower order register (i.e. L )are moved to
lower address (i.e. 2050 H ) and contents of higher order register(i.e.
H) are moved to higher address (i.e. 2051H)
III.STAX 2050H : Stores the contents of A directly at memory locations 2050H directly.
Q.9 Ans (a)
SUB may set or reset the CY flag and INX , CMA does not affect the any flag including
CY flag. The instruction ANA always reset the CY flag.
Q.10 Ans (d)
Given, Contents of PC = F000H
Contents of SP =2400H
CALL instruction requires five machine cycles. During the execution of CALL E000H,
microprocessor stores the address E000H in 16 bit temporary register WZ pair during
second and third machine cycles of CALL instruction. During fourth and fifth machine
cycles processor saves contents of program counter (i.e. address of next instruction, F003H)
on top of stack. During the saving the contents of program counter the stack pointer is
decremented by one from 2400H to 23FFH and then higher order byte of PC i.e. E0H is
saved at 23FFH and stack pointer is again decremented by one to 23FEH & then lower
byte of PC i.e. 03H is saved at 23FEH . So, after execution of CALL E000H , the program
counter contains F003H and stack pointer contains 23FEH. And address E000H is placed
by WZ pair on address line at the end of CALL instruction. The program counter is then
updated with contents WZ pair plus one. From the given options option (d) is nearest answer
but not correct.
Q.11 Ans (b)
I. DAA is an arithmetic instruction
II. LXI is a data movement instruction
III. RST is an interrupt instruction
IV. JMP is a program control instruction
Q.12 Ans.(a)
Facts about memory mapped I/O:
1. I/O devices are identified with 16-bit addresses just like a memory location.
2. I/O devices are accessed using same instructions which are used to access memory
locations. IN and OUT instructions are used to access I/O mapped I/O devices.
3. There can be maximum of 216 or 64 K memory mapped I/O devices which can be
identified with 8085 microprocessor.
4. Arithmetic and logic operations can be directly performed with the I/O data in memory
mapped I/O devices. But in case of I/O mapped I/O devices data is first store in
182 Microprocessor 8085
accumulator and only then arithmetic or logical operation can be performed.
For transferring the contents of accumulator to a memory mapped device, connected at
address 00F0 H, following instructions can be used,
LXI H, 00F0H : Load the HL pair with 00F0H .
MOV M, A : Moves the contents of accumulator to the I/O device whose address is
stored in HL pair.
Q.13 Ans.(a)
The sequence of instructions to increment the contents of memory location whose address is
available in (D,E) register pair and store the result in same location is as under,
XCHG : Exchanges the contents of HL-pair with contents of DE-pair.
INR M : Increments the contents of memory location whose address is stored in HL pair
and store the result at same memory location.
Q.14 Ans.(b)
Line 1: MVI A, B5H ; Moves B5 H to accumulator, A. So, A = B5 H
2: MVI B, 0EH ; Moves 0E H to B. So, B = 05 H
3 : XRI 69H ; Contents of A are ExORed with 69H and result is stored
in A.
A : 1011 0101
69H : 0110 1001
1101 1100 = DC H
So, A = DC H
4: ADD B ; Adds contents of B to contents of A and result is stored
in A.
A : 1101 1100
B : 0000 1110
1110 1010 = EA H
So, A = EA H
5. ANI 9BH ; Contents of A are ANDed with 9BH and result is stored
in A.
A : 1110 1010
9BH : 1001 1011
1000 1010 = 8A H
So, A = 8A H
6. CPI 9FH ; Compares 9FH with contents of A. The contents of A
remains unaffected but status of result is reflected by
flags.
A : 1000 1010
9F H : 1001 1111
1 1110 1011
7. STA 3010H ; Stores the contents of A at memory location 3010H.
8. HLT ; Halts the execution of program.
Thus, contents of A after execution of line 4 are EAH.
Q.15 Ans. (d)
XRA A ; The instruction XRA A performs ExOR operation on
Instruction Set of 8085 183
contents of A with contents of A only and store the
result in A. The instruction clears the contents of A.
So, after execution of XRA A the zero flag is set by the
instruction, sign flag is reset , parity flag is set, CY and
AC flags are reset.
MVI B, F0 H ; Moves data F0 H to register B.
So, contents of B = F0 H
SUB B ; Subtracts the contents of B(i.e. F0H) from contents
of A (i.e.00H)and store the result in A.
A : 00000000
B : 11110000
1 00010000
A = 10H and CY = 1
Q.16 Ans. (d)
Addr. Instruction Mnemonic Comments
Code
1000H 3E 06 MVI A,06H ; Moves data 06 H to register A. So, contents
of A = 06H
1002H C6 70 ADI 70H ; Adds 70 H to contents of A.
A: 00000110
B : 01110000
0 01110110
So, A = 76H and CY =0
1004H 32 07 10 STA 1007H ; Stores the contents of A(i.e. 76H) directly
to memory location 1007H. So, the contents
of 1007H becomes 76H. So, program code
AF H stored at 1007H is changed to 76 H
which is code of HLT statement.
1007H AF XRA A ; Since new contents of 1007H are 76 H
which is code of HLT statement so, the
program execution comes to an Halt without
executing XRA A and contents of A remains
76 H.
1008H 76 HLT ; This instruction will not be executed as
program execution has already come to an
Halt.
So, the contents of accumulator at the end of execution of above program are 76 H.
Q.17 Ans (c)
3000 MVI A, 45 H ; Moves 45 H to accumulator A. So, contents
of A = 45 H
3002 MOV B, A ; Moves contents of A, ie. 45 H to B.
184 Microprocessor 8085
So contents of B = 45 H
3003 STC ; Set carry flag , CY =1
3004 CMC ; Compliment CY flag . So, CY=0
3005 RAR ; Rotates content of A to right through carry
flag.
Before rotation:

After rotation:

So, content of A = 22 H
3006 XRA B ; Performs XOR operation between contents
of A & B and store the result in accumulator.
A :0 0 1 0 0 0 1 0
B:0 1 0 0 0 1 0 1
A B : 01 1 0 0 111
6 7
So, contents of A after execution of program are 67 H.
Q.18 Ans (d)
When a “CALL Addr” instruction is executed, the CPU carries out the following
sequential operations internally,
Step-I : Contents of Program counter are moved to on top of stack pointed by stack
pointer.
Step-II : The stack pointer is incremented.
Step-III : The address Addr is moved to program counter.
Note : In 8085 the contents of SP are decremented automatically by two when contents are moved
on top of stack because the stack pointer in 8085 is initiated with high address and data
storage begins from address lower than the address stored in SP. But in the given question
there is no such option.
Q.19 Ans. (c)
SUB1 : MVI A,00H ; Moves data 00 H to accumulator , A. So, contents of
A = 00H
CALL SUB2 ; Calls the subroutine SUB2
SUB2 : INR A ; Increases the contents of A by one.
RET ; Returns to calling subroutine.
Instruction Set of 8085 185
In the above program the instructions INR A is executed twice. Once by calling of SUB2
by Subroutine SUB1 and once by subroutine SUB1 itself. So, the contents of accumulator
are incremented twice. Therefore, the contents of A after returning from subroutine SUB1
will be 02H.
Q.20 Ans. (d)
SBX : MVI A, 99 H ; Moves data 99H to accumulator A.
ADI 11H ; Adds 11 H to contents of A(i.e. 99H).
A : 10011001
11H : 00010001
10101010
A = AA H and CY = 0
MOV C,A ; Moves contents of A to register C.
RET ; Returns to main program.
So, at the end of the program the contents of A are AA H.
Q.21 Ans(c)
Given contents of CY flag, CY = 0
MVI A,07H ; Moves data 07H to accumulator , A. So, A = 07H.
RLC ; Rotates contents of accumulator to left without carry flag.
Before rotation:

CY 0

0 0 0 0 0 1 1 1
After rotation:

CY 0
0 0 0 0 1 1 1 0
A = 0E Hand Cy = 0
MOV B,A ; Moves the contents of A(i.e. 0EH) to B . So B = 0EH.
RLC ; Rotates contents of accumulator to left without carry
flag.
Before rotation:
CY 0
0 0 0 0 1 1 1 0
After rotation:
CY 0

0 0 0 1 1 1 0 0
A = 1CHand Cy = 0
186 Microprocessor 8085
RLC ; Rotates contents of accumulator to left without carry
flag.
Before rotation:
CY 0
0 0 0 1 1 1 0 0
After rotation:
CY 0

0 0 1 1 1 0 0 0
A = 38Hand CY = 0
ADD B ; Adds the contents of B(i.e. 0EH) to the contents of
A(i.e. 38H).
0EH : 00001110
38H : 00111000
01000110
A = 46H and CY = 0
RRC ; Rotates contents of accumulator to right without carry
flag.
Before rotation:

CY 0

0 1 0 0 0 1 1 0

After rotation:

CY 0
0 0 1 0 0 0 1 1
A = 23 Hand CY = 0
Q.22 Ans (c)
Let,
Disp = 1000 H
L p = 2000 H
SUB = 5000 H
Main program :
:
:
LXI D, DISP
LP : CALL SUB
:
Instruction Set of 8085 187
:
Subroutine:
POP H
DAD D
PUSH H
RET
Program Description :
The segment of main programme given above first stores the 16 bit data (i.e. 1000 H) in DE
pair and than call the subroutins stored at add begining with SUB (i.e. 5000 H).
In last two machine cycles of CALL instruction the processor saves the contents of PC on
top of stack. So, before transferring the control of execution to subroutine the processor
saves the contents of program counter (i.e. LP + 3) on top of stack.
In sub routine during last three instruction preceding the RET instruction, the processor first
copies the contents of top of stack (i.e. 4 + 3) in HL pair, then adds contents of DE pair
(i.e. DISP) to contents of HL pair. After execustion of DAD D instruction the contents of
HL pair becomes LP + DISP + 3. Then processor saves the contents of HL pair on top of
stack. Now when RET instruction is executated the processor first copies the contents of
top of stack (i.e. LP + DISP + 3) in the program counter and then returns to main program.
So, program execution is transferred to LP + DISP + 3 after execution of RET instruction.
Main Program
.
.
LXI D, DISP ; Loads DE pair with 16-bit data ‘DISP’ . So, the contents
of DE pair are ‘DISP’
LP: CALL SUB ; Calls the subroutine stored at address ‘SUB’. During
last two machine cycles of CALL, the miroprocessor
saves address of next instruction (i.e. LP + 3) on top of
stack.
Subroutine SUB :
POP H ; Moves the contents of top of stack (i.e. LP + 3) in HL
pair. So contents of HL pair become LP + 3.
DAD D ; Adds contents of DE pair (i.e. DISP) to contents of
HL pair (i.e. LP + 3 ) and saves the result in HL pair.
So, contents of HL pair become LP + DISP + 3.
PUSH H ; Moves the contents of HL pair (i.e. LP + DISP + 3) on
top of stack.
RET ; Returns the execution to address stored on top of stack
(i.e. LP + DISP + 3). When return instruction is executed
the microprocessor moves contents of top of stack to
program counter. So the execution is transferred to the
address LP + DISP + 3.
Q.23 Ans.(b)
Given, SP =2700 H PC =2100 H and HL = 0000H
188 Microprocessor 8085
2100 H: DAD SP ; Adds the contents of SP pair(i.e. 2700H) to HL pair
(i.e. 0000H) and store result in HL pair.
HL :0000 0000 0000 0000
+SP :0010 0111 0000 0000
HL :0010 0111 0000 0000
2 7 0 0
After addition, HL = 2700 H
2101 H: PCHL ; Moves the contents of HL (i.e 2700H) pair to Program
Counter. So, PC = 2700 H.
The contents of (SP) and (PC) at the end of execution will be , PC = 2700H and SP = 2700H.
Q.24 Ans.(a)
Memory mapped I/O devices are indentified with 16-bit addresses just like a memory
location. Memory mapped I/O devices are accessed using same instructions which are used
to access memory locations. So, for reading the data into accumulator from I/O device
connected at 2500 H, following instructions can be used,

LXI H, 2500H ; Load HL pair with 2500 H. So, H = 25 H and L = 00 H

MOV A, M ; Moves the contents of memory location, whose address
is stored in HL pair, to accumulator.
Q.25 Ans (a)
MVI A, 05 H ; Moves 05 H to Accumulator.So, A = 05 H
MVI B, 05 H ; Moves 05 H to Register ‘B’ . So, B = 05 H
PTR : ADDB ; Adds the contents of B to A and stores result in ‘A’.
DCR B ; Decrements contents of B by one.
JNZ PTR ; Jumps to PTR until content of ‘B’ becomes zero.
ADI 03 H ; Adds 03 H to contents of ‘A’.
HLT ; Halts the program execution.
Above program adds contents of ‘B’ five times to ‘A’ and contents of ‘B’ are decremented
everytime and at last 03H is added to A.
The result shall be as under,
A = 05 + 05H + 04H + 03H + 02H + 01H + 03H = 17H
Q.26 Ans (c)
The instruction LHLD 2100H , loads register L with contents of 2100 H and register H
with contents of 2101H.
Q.27 Ans. (a)
2000 H XRA A ; Performs ExOR operation the contents
of A and store result in A. Result in A after operation becomes 00H. Resets the carry
flag, i.e. CY = 0
2001 H MVI B,04H ; Moves 04 H in register B. So B = 04 H
2003 H MVI A, 03H ; Moves 03 H in accumulator A. So, A = 03 H
2005 H RAR ; Rotates the contents of A to right through carry flag.
Before rotation:
Instruction Set of 8085 189

CY 0

0 0 0 0 0 0 1 1
After rotation:

CY 1
0 0 0 0 0 0 0 1

A = 01 H and CY = 1
2006 H DCR B ; Decreases the content of register B by one and all
flags are affected except carry flag. The contents of
B after decrement, B = 03 H. As contents of B are
non-zero so zero flag is reset. i.e. Z = 0.
2007 H JNZ 2005 ; Jump the execution to address 2005 if zero flag is not
set. Excecution jumbs of 2005 H till zero flag is set.
200AH HLT ; Halt the execution of program.

Here, the execution jumps back to address 2005 H thrice till the contents of B become zero.
Thus instruction RAR is executed four times and the contents of A are rotated to four times
through carry flag in total. In first run contents are A = 01H, CY = 1 and B = 03H as shown
above. In second run the contents become A = 80H, CY= 1 and B = 02H. During third run
A = C0H, CY= 0 and B = 01H. and in last and fourth run, A = 60H, CY= 0 and B = 00H and
Z = 1. Thus execution goes to HLT when zero flag is set.
Q.28 Ans. (b)
In an 8085 microprocessor, the shift registers which store the result of an addition and the
overflow bit are accumulator (A) and flag (F), respectively.
Q.29 Ans. (c)
Programme used for multiplication of two 8-bit numbers stored in registers B and C is,
MVI A, 00H ; Moves 00H to accumulator. So, A = 00H.
LOOP ADD C ; Adds the contents of register C to A.
DCR B ; Decrements the contents of B by one.
JNZ LOOP ; Jumps back to LOOP till the zero flag is set.
HLT ; Halts the execution.
In the above program first accumulator is loaded with 00H. The execution enters into loop
till the contents of B become zero. Thus the contents of C are added to A for a number of
times equal to number stored in B. Thus the results stored in A at the end of the program are
equal to the product of contents of B and C.
Q.30 Ans. (d)
MOV B, M ; Moves the contents of memory location M whose address is stored
in HL pair to register B.
PCHL ; Moves the contents of HL pair to the program counter
190 Microprocessor 8085
RNZ ; Return the execution to the calling subroutine if zero flag is not set.
SBI BEH ; Subtracts 8-bit data BEH from contents of accumulator along with
borrow.
Thus, the instruction which changes the content of the accumulator is SBI BEH.
Q.31 Ans. (c)
In an 8085 system, a PUSH operation requires more clock cycles than a POP operation
because the the stack pointer needs to be pre-decremented before writing registers in a
PUSH, whereas a POP operation uses the address already in the stack pointer.
Q.32 Ans. (d)
Given contents of accumulator and carry flag, A = A7 = 10100111; CY = 0
RLC ; Rotates contents of accumulator to left without carry
flag.
Before rotation:
CY 0
1 0 1 0 0 1 1 1
After rotation:
CY 1

0 1 0 0 1 1 1 1

A 4FH and CY = 1
Q.33 Ans.(b)
MVI A, 33H ; Moves 33 H to A
MVI B, 78H ; Moves 78 H to B
ADD B ; Adds the contents of B to A and stores result in A.
The contents of A after addition,
A : 00110011 or 33 H
+B : 01111000 or 78 H
________________
` A : 10101011 or AB H
CMA ; Complitments the contents of A. Contents of A after
complimenting becomes,
A : 01010100 or 54 H
ANI 32H ; Performs AND operation of 32 H with contents of A and
stores result in A.
A : 01010100 or 54 H
AND 00110010 or 32 H
________________
` A : 00010000 or 10 H
Thus the contents of A after execution of the fifth instruction is 10 H.
 About the Author
Dr. Ram Niwas is from Indian Railways Services of Electrical Engineers. He
obtained BE degree in Electronics and Power Engineering from NIT(VRCE),
Nagpur in 1998, ME degree in Control and Instrumentation Engineering in 2003
from DCE, Delhi and PhD from IIT, Delhi in 2015. He worked with TATA
Infotech from January 2000 to June 2000. From August 2000 to
December 2001 he worked as lecturer in the Department of Electronics and
Communication Engineering in KIET, Ghaziabad. From December 2001 to August 2002 he
worked with BSNL as Junior Telecom Officer(JTO). From September 2002 onward he is
serving Indian Railways as IRSEE officer. He has vast experience of analytical approach to
competitive examinations. Author qualified IES examination twice in year 2001 and 2004. He
has published 13 research papers in international journals including 3 IEEE transactions and 4
IET journals.

v Purely competitive examination oriented book.

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v Fully solved objective questions of GATE & IES from 1993
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v Solutions of IES conventional questions from 1989 to 2017

v Solutions of IAS Mains questions from 2001 to 2016

v Helpful for University Examinations also.
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