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Computer Architecture Important Topics

This document lists important topics and recommended reading for the course CS6303 - Computer Architecture. It includes five units covering topics such as addressing modes, components of computer systems, instruction representation, performance, pipelining, parallel processing, memory hierarchy, I/O, and more. For each topic, it recommends sections from textbooks by authors like Patterson, Hamacher, Stallings, and Godse to refer to for more details on the topic.

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102 views

Computer Architecture Important Topics

This document lists important topics and recommended reading for the course CS6303 - Computer Architecture. It includes five units covering topics such as addressing modes, components of computer systems, instruction representation, performance, pipelining, parallel processing, memory hierarchy, I/O, and more. For each topic, it recommends sections from textbooks by authors like Patterson, Hamacher, Stallings, and Godse to refer to for more details on the topic.

Uploaded by

Greenkings
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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CS6303 - Computer Architecture

Important Topics
T1: David A. Patterson and John L. Hennessey, “Computer organization and design”, Morgan
Kauffman , Fifth edition.
R1: V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, “Computer Organisation and
Embedded Systems”, Sixth edition, McGraw-Hill Inc.
R2: William Stallings, “Computer Organization and Architecture”, Eighth Edition, Pearson Education.
R3: John P. Hayes, “Computer Architecture and Organization”, Third Edition, Tata McGraw Hill.
R4: A.P. Godse, “Computer Architecture”, Seventh Edition, Technical Publications.

S.No Topic Tech. Publn. Recommended Book


(Godse)
UNIT - I Pg. No Pg. No.
1$ Addressing modes 1.29 – 1.33 R4: 1.29 – 1.33
T1: 116 - 117
2$ Components of computer system 1.3 – 1.6 R1 3-6
3$ Representing instructions - T1 80 - 84
4$ Performance – CPU Performance 1.11 – 1.18 T1 28 - 39
5 Eight ideas of computer architecture. 1.2 – 1.3 T1 11 - 12
6 MIPS Instruction MIPS Instruction set - T1 63 – 66
Logical operations - T1 87 - 89
Control Operations - T1 90 - 95
7 Technology 1.8 – 1.11 R4 1.8 – 1.11
8 Power wall 1.18 – 1.19 T1 40 - 42
9 Uniprocessors to mulitprocessors 1.20 T1 43 - 45
10$ Instructions – operations and operands 1.21 – 1.29 T1 62 - 72
11$ Problems 1.12 – 1.16, T1 31, 34 – 38, 40,
1.19, 1.33, 41
S.1 – S.2
UNIT - II
1$ Multiplication Booth’s algorithm 2.22 – 2.33 R1 348 - 353
(H/W,
flowchart, Ex)
Sequential multiplication 2.20 – 2.21 R1 346 -347
algorithm (H/W,
flowchart, Ex)
2$ Division (Restoring & Non-restoring) 2.34 – 2.47 R1 360 - 363
(H/W,
flowchart, Ex)
3 Floating point operations Addition & subtraction 2.54 – 2.60 R1 367 - 371
(H/W,
flowchart, Ex)
Multiplication & division 2.60 – 2.62 R1 367 - 368
4$ Carry Look ahead adder 2.14 – 2.19 R1 339 - 344
5 Addition & subtraction 2.7 – 2.13 R1 336 - 339
6 Subword parallelism 2.63 T1 222 - 223
7 IEEE 754 (floating point) standard 2.47 – 2.55 R1 363 – 368
8 Problems Multiplication 2.22 – 2.25, - -
2.29 – 2.33
Division 2.37 – 2.41, - -
2.44 – 2.46

1
$ - Repeated University Questions
S.No Topic Tech. Publn. Recommended Book
(Godse)
UNIT - III
1$ Data path Building datapath 3.5 – 3.11 T1 251 – 271
Control implementation 3.11 – 3.17
operation 3.17 – 3.22
2$ Hazard - Pipeline hazards 3.26 – 3.29 T1 277 - 284
3$ Pipelining - Pipelined data path and control 3.23 – 3.25, T1 272 – 276,
3.34 – 3.40 286 - 303
4$ Basic MIPS implementation 3.2 – 3.5 T1 244 - 247
5 Exceptions 3.49 - 3.50 T1 325 – 330
6 Handling Data hazards (Operand forwarding) 3.40 – 3.42 T1 303 - 316
7 Handling control hazards (Branch prediction) 3.43 – 3.48 T1 316 - 322
UNIT - IV
1$ Flynn’s classification 4.15 – 4.18 R2 630 – 631
T1 509 - 511
2$ Instruction Level Parallelism - Parallel processing 4.4 – 4.14 R4 4.4 – 4.14
challenges
3$ Multicore Processor 4.24 – 4.26 R4 4.24 – 4.26
T1 519 – 520
4$ Hardware Multithreading 4.18 – 4.23 R2 646 – 651
T1 516
5$ Shared memory multiprocessor 4.25 – 4.26 T1 519 – 520,
T1: 519 – 520, 531 - 532
531 - 532
6$ Problems R4: 4.12 – 4.14
UNIT - V
1$ Cache memory – Mapping Techniques R1: 289 - 296 R1 289 - 296
2$ Virtual memory - TLB R1: 305 - 310 R1 305 - 310
3$ DMA R3: 511 - 515 R3 511 - 515
4$ Bus Arbitration techniques in DMA 5.80 – 5.83 R3 498 - 501
5 Memory Technologies 5.11 – 5.21 R1 270 - 285
6 Memory Hierarchy 5.8 – 5.10 R1 288 - 289
7 Interrupt Interrupt 5.65 – 5.69 R3 515 – 519
Parallel priority interrupt 5.68 – 5.69 R4: 5.68 – 5.69
8 I/O Processor R3: 523 - 526 R3 523 - 526
9$ Programmed I/O R3: 505 - 506 R3 505 - 506
10 Standard I/O interfaces R1: 247 – 250 (USB), 258 – 259 (PCI) / Web
11 Problems 5.33 – 5.36, T1: 390 – 391,
5.43 400 – 402,
410 - 411

2
$ - Repeated University Questions

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