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Computer Organization and Architecture: GATE CS Topic Wise Questions
Computer Organization and Architecture: GATE CS Topic Wise Questions
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YEAR 2001
Question. 1
SOLUTION
Cache is the small memory which has a very less access time. So it is
used for temporal locality of reference whereas virtual memory is for
spatial locality of reference.
Hence (A) is correct option.
Question. 2
SOLUTION
Question. 3
Suppose a processor does not have any stack pointer register. Which
of the following statements is true ?
(A) It cannot have subroutine call instruction
(B) It can have subroutine call instruction, but no nested subroutine
calls.
(C) Nested subroutine calls are possible, but interrupts are not.
(D) All sequences of subroutine calls and also interrupts are possible
SOLUTION
Stack pointer register holds the address of top of stack, which is the
location of memory at which the CPU should resume its execution
after servicing some interrupt or subroutine call.
So if SP register not available then no subroutine call instructions
are possible.
Hence (A) is correct option.
Question. 4
A processor needs software interrupt to
(A) Test the interrupt system of the processor.
(B) Implement co-routines.
(C) Obtain system services which need execution of privileged
instructions.
(D) Return from subroutine.
SOLUTION
Question. 5
A CPU has two modes-privileged and non-privileged. In order to
change the mode from privileged to non-privileged.
(A) A hardware interrupt is needed.
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SOLUTION
Question. 6
SOLUTION
Question. 7
SOLUTION
Question. 8
Which is the most appropriate match for the items in the first column
with the items in the second column
(X.) Indirect Addressing (I.) Array implementation
(Y.) Indexed Addressing (II.) Writing re-locatable code
(Z.) Base Register Addressing (III.) Passing array as parameter
(A) (X, III) (Y, I) (Z, II) (B) (X, II) (Y, III) (Z, I)
(C) (X, III) (Y, II) (Z, I) (D) (X, I) (Y, III) (Z, II)
SOLUTION
Question. 9
SP ! SP − 1
How many CPU clock cycles are needed to execute the “push r”
instruction ?
(A) 2 (B) 3
(C) 4 (D) 5
SOLUTION
Push ‘r’
Consist of following operations
M [SP] !r
SP ! SP − 1
‘r’ is stored at memory at address stack pointer currently is, this take
2 clock cycles.
SP is then decremented to point to next top of stack.
So total cycles = 3
Hence (B) is correct option.
Question. 10
SOLUTION
YEAR 2002
Question. 11
A device employing INTR line for device interrupt puts the CALL
instruction on the data bus while
(A) INTA is active (B) HOLD is active
(C) READY is active (D) None of the above
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SOLUTION
Question. 12
In 8085 which of the following modifies the program counter ?
(A) Only PCHL instruction
(B) Only ADD instructions
(C) Only JMP and CALL instructions
(D) All instructions
SOLUTION
Program counter is the register which has the next location of the
program to be executed next. JMP & CALL changes the value of PC.
PCHL instruction copies content of registers H & L to PC.
ADD instruction after completion increments program counter. So
program counter is modified in all cases.
Hence (D) is correct option.
Question. 13
In serial data transmission, every byte of data is padded with a ‘0’ in
the beginning and one or two ‘1’s at the end of byte because
(A) Receiver is to be synchronized for byte reception
(B) Receiver recovers lost ‘0’s and ‘1’ from these padded bits
(C) Padded bits are useful in parity computation.
(D) None of the above
SOLUTION
Question. 14
SOLUTION
Question. 15
In the C language
(A) At most one activation record exists between the current
activation record and the activation record for the main.
(B) The number of activation records between the current activation
record and the activation record for the main depends on the
actual function calling sequence.
(C) The visibility of global variables depends on the actual function
calling sequence.
(D) Recursion requires the activation record for the recursive function
to be saved on a different stack before the recursive fraction can
be called.
SOLUTION
Question. 16
SOLUTION
Question. 17
SOLUTION
Question. 18
Horizontal microprogramming
(A) Does not require use of signal decoders
(B) Results in larger sized microinstructions than vertical
microprogramming
(C) Uses one bit for each control signal
(D) All of the above
SOLUTION
Question. 19
For a pipelined CPU with a single ALU, consider the following
situations
1. The j + 1 − st instruction uses the result of j − th instruction as
an operand
2. The execution of a conditional jump instruction
3. The j − th and j + 1 − st instructions require the ALU at the same
time
Which of the above can cause a hazard?
(A) 1 and 2 only (B) 2 and 3 only
(C) 3 only (D) All the three
SOLUTION
Question. 20
Consider an array multiplier for multiplying two n bit numbers. If
each gate in the circuit has a unit delay, the total delay of the
multiplier is
(A) Θ (1) (B) Θ (log n)
(C) Θ (n) (D) Θ (n2)
SOLUTION
Question. 21
SOLUTION
This is the ckt to add two numbers in 2’s complement form. K & C 0
are set to 1. So A + B & A − B using bit adders can be done. Also
since C 0 = 1 & in case B 0, B1 ........ all are 0 then it gives A + 1.
Hence (D) is correct option.
Question. 22
SOLUTION
Question. 23
SOLUTION
YEAR 2004
Question. 24
SOLUTION
Question. 25
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SOLUTION
We require f = T + R
We have MUX equation
f = Z'x + zy
Now if we make following ckt
Truth table So X = R Y = 1 Z = T
R T F Z
f = T'R + T
0 0 0 0
= (T + T') (T + R)
0 1 1 1
f = T+R
1 0 1 0
1 1 1 1
Question. 26
Consider that the memory is byte addressable with size 32 bits, and
the program has been loaded starting from memory location 1000
(decimal). If an interrupt occurs while the CPU has been halted after
executing the HALT instruction, the return address (in decimal)
saved in the stack will be
(A) 1007 (B) 1020
(C) 1024 (D) 1028
SOLUTION
Question. 27
SOLUTION
Question. 28
SOLUTION
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Architecture
After than 12 & 8 are referred but this does not cause any miss
So no. of miss = 3
This stars ()) shows the misses.
Hence (B) is correct option.
Question. 29
How many bits are there in the X and Y fields, and what is the size
of the control memory in number of words?
(A) 10, 3, 1024 (B) 8, 5, 256
(C) 5, 8, 2048 (D) 10, 3, 512
SOLUTION
Question. 30
SOLUTION
Transfer rate = 10 MB ps
Data = 20 KB
10
Time = 20 # 220 = 2 # 10− 3
10 # 2
= 2 ms
Processor speed = 600 MHz
= 600 cycles/sec.
Cycles required by CPU = 300 + 900
For DMA = 1200
So time = 1200 6 = .002 ms
600 # 10
% = .002 # 100
2
= 0.1%
Hence (D) is correct.
Question. 31
A 4-stage pipeline has the stage delays as 150, 120, 160 and 140
nanoseconds respectively. Registers that are used between the stages
have a delay of 5 nanoseconds each. Assuming constant clocking rate,
the total time taken to process 1000 data items on this pipeline will
be
(A) 120.4 microseconds (B) 160.5 microseconds
(C) 165.5 microseconds (D) 590.0 microseconds
SOLUTION
Delay = 5 ns/stage
Total delay in pipline.
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= 165.5 microseconds.
Hence (C) is correct option
YEAR 2005
Question. 32
Which one of the following is true for a CPU having a single interrupt
request line and a single interrupt grant line?
(A) Neither vectored interrupt nor multiple interrupting devices are
possible
(B) Vectored interrupts are not possible but multiple interrupting
devices are possible
(C) vectored interrupts and multiple interrupting devices are both
possible
(D) vectored interrupt is possible but multiple interrupting devices
are not possible
SOLUTION
Here multiple request can be given to CPU but CPU interrupts only
for highest priority interrupt so option (A) & (D) are wrong.
But here in case of single interrupt lines definitely vectored interrupts
are not possible.
Hence (B) is correct option.
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Question. 33
Normally user programs are prevented from handing I/O directly by I/O
instructions in them. For CPUs having explicit I/O instructions, such
I/O protection is ensured by having the I/O instructions privileged. In
a CPU with memory mapped I/O, there is no explicit I/O instruction.
Which one of the following is true for a CPU with memory mapped
I/O?
(A) I/O protection is ensured by operating system routine(s)
(B) I/O protection is ensured by a hardware trap
(C) I/O protection is ensured during system configuration
(D) I/O protection is not possible
SOLUTION
Question. 34
What is the swap apace in the disk used for?
(A) Saving temporary html pages
(B) Saving process data
(C) Storing the super-block
(D) Storing device drivers
SOLUTION
Swap space is the memory pre allowed to store process’s data. This
can be compared with virtual memory. The data required to complete
process is kept here.
Hence (B) is correct option.
Question. 35
Increasing the RAM of a computer typically improves performance
because
(A) Virtual memory increases
(B) Larger RAMs are faster
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SOLUTION
Due to increase in RAM size all the pages required by CPU are
available in RAM so page fault chance are less, so virtual memory
access chances are less and latency is reduced for secondary memory.
Hence (C) is correct option.
Question. 36
SOLUTION
ADD A [R 0], @B
This is instruction has 3 computational parts. ADD instruction
requires 1 machine cycle, A [R 0] here R 0 is index register which has
starting address of index then this index has the block address.
This whole operation require 3 machine cycles. Now @ B is indirect
addressing. This takes 2 machine cycles. So overall 1 + 3 + 2 = 6
machine cycles.
Hence (D) is correct option.
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Question. 37
Match List-I with List-II and select the correct answer using the
codes given below the lists:
List-I List-II
A. A [1] = B [j]; 1. Indirect addressing
B. while [* A ++]; 2. Indexed addressing
C. int temp=*x ; 3. Auto increment
Codes:
A B C
(A) 3 2 1
(B) 1 3 2
(C) 2 3 1
(D) 1 2 3
SOLUTION
LIST-I LIST-II
A. A [1] = B [J]; 2 Indexed addressing here the
indexing is used
B. While [) A ++] 3. Auto increment the
memory locations is A are
automatically incriminated.
C. int temp = ) X
1. Indirect addressing here
temp is assigned the value of
int type stored at the address
contained in X
A2
B3
C1
Hence (C) is correct option.
Question. 38
Consider a direct mapped cache of size 32 KB with block size 32 bytes.
The CPU generates 32 bit addresses. The number of bits needed for
cache indexing and the number of tag bits are respectively
(A) 10,17 (B) 10,22
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SOLUTION
So, 10, 17
Hence (A) is correct option.
Question. 39
(A) 8 (B) 10
(C) 12 (D) 15
SOLUTION
Total cycles = 10
Hence (B) is correct option.
Question. 40
A device with data transfer rate 10 KB/sec is connected to a CPU.
Data is transferred byte-wise. Let the interrupt overhead be 4 μ sec .
The byte transfer time between the device interface register and CPU
or memory is negligible. What is the minimum performance gain of
operating the device under interrupt mode over operating it under
program controlled mode?
(A) 15 (B) 25
(C) 35 (D) 45
SOLUTION
Question. 41
SOLUTION
, 26%
The, ALU, the bus and all the registers in the data path are of
identical size. All operations including incrementation of the PC and
the GPRs are to be carried out in the ALU. Two clock cycle are
needed for memory read operation-the first one for loading data from
the memory but into the MDR.
Question. 42
The instruction “add R0, R1” has the register transfer in terpretation
R0 <= R0 + R1. The minimum number of clock cycles needed for
execution cycle of this instruction is
(A) 2 (B) 3
(C) 4 (D) 5
SOLUTION
R 0 ! R 0 + R1
First cycle require to fetch operands two cycles required for this.
The next cycle required to use ALU to perform ADD operation.
So total cycles required = 3
Question. 43
The instruction “call Rn , sub” is a two word instruction. Assuming
that PC is incremented during the fetch cycle of the first word of the
instruction, its register transfer interpretation is
Rn <= PC = 1;
PC <= M [PC];
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SOLUTION
Rn ! PC + 1
PC = M [PC]
Program outer is itself a register so incremented in 1 cycle.
Now fetching the memory at PC & the value of at address stored in
PC takes 2 cycles.
So total 1 + 2 = 3 cycles.
Hence (B) is correct option.
Question. 44
A CPU has 24-bit instructions. A program starts at address 300(in
decimal). Which one of the following is a legal program counter (all
values in decimal)?
(A) 400 (B) 500
(C) 600 (D) 700
SOLUTION
YEAR 2006
Question. 45
A CPU has a cache with block size 64 bytes. The main memory has
k banks, each bank being c bytes wide. Consecutive c-bute chunks
are mapped on consecutive banks with warp-around. All the k banks
can be accessed in parallel, but two accesses to the same bank must
be serialized. A cache block access may involve multiple iterations of
parallel bank accesses depending on the amount of data obtained by
accessing all the k banks in parallel. Each iteration requires decoding
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SOLUTION
Question. 46
A CPU has five-stages pipeline and runs at 1GHz frequency.
Instruction fetch happens in the first stage of the pipeline. A
conditional branch instruction computes the target address and
evaluates the condition in the third stage of the pipeline. The processor
stops fetching new instructions following a conditional branch until
the branch outcome is known. A program executes 109 instructions
out of which 20% are conditional branches. If each instruction takes
one cycle to complete on average, then total execution time of the
program is
(A) 1.0 second (B) 1.2 seconds
(C) 1.4 seconds (D) 11.6 seconds
SOLUTION
Given that 80% of 109 instruction require single cycle i.e. no conditional
branching & for 20% an extra cycle required.
Time taken by 1 cycle = 10− 9 sec.
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= 10− 9 # 109 b 4 + 2 l
5 5
= 6 = 1.2 seconds.
5
Hence (B) is correct option.
Question. 47
Consider a new instruction named branch-on-bit-set (mnemonic bbs).
The instruction “bbs reg, pos, labbel” jumps to label if bit in position
pos of register operand reg is one. a register is 32 bits wide and the
bits are numbered 0 to 31, bit in position 0 being the least significant.
Consider the following emulation of this instruction on a processor
that does not have bbs implemented.
temp!reg and mask
Branch to label if temp is non-zero
The variable temp is a temporary register. For correct emulation the
variable mask must be generated by
(A) mask ! 0x1 << pos (B) musk ! 0x ffffffff >> pos
(C) mask ! pos (D) msdk ! 0xf
SOLUTION
Given instruction
bbs reg, pos, Label
Here pos bit decided whether to jump to label. So all other bits in
temp set to 0.
Temp ! reg and mask.
So of temp is not zero branch to label.
So shifting left over.
Mask ! 0 # 1 << pos
Hence (D) is correct option.
Data for Q. 48 & Q. 49 are given below. Solve the problem and
choose the correct answers.
Consider two cache organizations: The first one is 32 KB 2-way set
associative with 32-bytes block size. The second one is of the same
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size but direct mapped. The size of an address is 32 bits in both cases
A2-to-1 multiplexes has latency of 0.6 ns where a k -bit comparator
has a latency of k/10ns . The hit latency of the set associative
organization is h1 while that of the direct mapped one is h2 .
Question. 48
The value of h1 is
(A) 2.4ns (B) 2.3ns
(C) 1.8ns (D) 1.7ns
SOLUTION
Tag index
h1 = 18 + 0.6 ns
10
= 2.4 ns.
Question. 49
The value of h2 is
(A) 2.4ns (B) 2.3ns
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SOLUTION
17 10 5
h2 = 17 + 0.6
10
= 2.3 ns
Hence (B) is correct option.
Question. 50
The value of M1 is
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SOLUTION
Given loop P1 accesses array A row wise & P2 access column wise.
M1 = ?
Cache Capacity = 215 B.
1 element = 23 B
Total elements 512 # 512
Total data = 512 # 512 # 8 B
= 221 B
Block size = 128 B
1 block can have = 128 = 16 elements
8
= 1638 blocks
Since the memory is initially empty so all blocks are required at least
once.
So, M1 = 16384
Hence (C) is correct option.
Question. 51
The value of the ratio M1 /M2 is
(A) 0 (B) 1/16
(C) 1/8 (D) −16
SOLUTION
Now M2 = ?
In the case (P2 loop) the array is accessed column wise, so even the
block brought for A [0] [0] − A [0] [15] would not be used for second
column wise access i.e. A [1] [0] So new block need to swap, similarly
for A [3] [0] & So on. This would continue for every element, since
memory is contiguous.
So M2 = 512 # 512 = 262144
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& M1 = 16384 = 1
M2 262144 16
YEAR 2007
Question. 52
SOLUTION
9 5 6
Question. 53
Consider a disk pack with 16 surfaces, 128 tracks per surface and 256
sectors per track. 512 bytes of data are stored in a bit serial manner
in a sector. The capacity of the disk pack and the number of bits
required to specify a particular sector in the disk are respectively
(A) 256 Mbytes, 19 bits (B) 256 Mbyte, 28 bits
(C) 512 Mbytes, 20 bits (D) 64 Gbyte, 28 bits
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SOLUTION
Surface = 6
Tracks = 16 # 128
Sectors = 16 # 128 # 256
= 2 4 # 27 # 28 = 219
So 19 lines are required to address all sectors.
Bytes = 219 # 512 B
= 219 # 29
B = 228
= 256 MB
Hence (A) is correct option.
Question. 54
SOLUTION
R2 ! R1 ! R 0 IF ID EX WB
R 4 ! R3 ! R2 IF ID EX EX EX WB
R6 ! R5 ! R 4 IF ID - - EX WB
Represent wait in pipeline due to result dependently.
Clock cycles require = 8
Hence (B) is correct option.
Consider the following program segment. Here R1, R2 and R3 are the
general purpose registers.
Question. 55
SOLUTION
Question. 56
SOLUTION
Program stores results from 2000 to 2010. It stores 110, 109, 108......100
at 2010 location.
DEC R1
Hence (A) is correct option.
Question. 57
Assume that the memory is byte addressable and the word size is 32
bits. If an interrupt occurs during the execution of the instruction
“INC R3”, what return address will be pushed on to the stack?
(A) 1005 (B) 1020
(C) 1024 (D) 1040
SOLUTION
Question. 58
How many data cache misses will occur in total?
(A) 48 (B) 50
(C) 56 (D) 59
SOLUTION
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Question. 59
Which of the following lines of the data cache will be replaced by new
blocks in accessing the array
(A) line 4 to line 11 (B) line 4 to line 12
(C) line 0 to line 7 (D) line 0 to line 8
SOLUTION
YEAR 2008
Question. 60
For a magnetic disk with concentric circular track, the latency is not
linearly proportional to the seek distance due to
(A) non-uniform distribution of requests
(B) arm starting and stopping inertia
(C) higher capacity of tracks on the periphery of the platter
(D) use of unfair arm scheduling policies.
SOLUTION
Question. 61
Which of the following is/are true of the auto increment addressing
mode?
1. It is useful in creating self relocating code
2. If it is included in an Instruction Set Architecture, then an
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SOLUTION
In auto increment addressing mode the address where next data block
to be stored is generated automatically depending upon the size of
single data item required to store. So statement 3 is correct.
Statement says that this mode is used for self relocating code, but
this is false since self relocating code, takes always some address in
memory.
Statement 2 is also incorrect since no additional ALV is required.
Hence (C) is correct option.
Question. 62
Which of the following must be true for the RFE (Return from
Expectation) instruction on a general purpose processor.
1. It must be a trap instruction
2. It must be a privileged instruction
3. An exception can not be allowed to occur during execution of
an RFE instruction.
(A) 1 only (B) 2 only
(C) 1 and 2 only (D) 1, 2 and 3 only
SOLUTION
Question. 63
For inclusion to hold between two cache level L1 and L2 in a multilevel
cache hierarchy, which of the following are necessary?
1. L1 must be a write-through cache
2. L2 must be write-through cache
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SOLUTION
Level 1 (L1) & Level 2 (L2) cache are placed between CPV & they
can be both write through cache but this is not necessary.
Associativity has no dependence but L2 cache must be at least as
large as L1 cache, since all the words in L1 are also is L2.
Hence (A) is correct option.
Question. 64
SOLUTION
Question. 65
3. Instruction fetches
(A) 1 only (B) 2 only
(C) 3 only (D) 1,2 and 3
SOLUTION
Question. 66
In an instruction execution pipeline, the earliest that the data TLB
(Translation Look aside Buffer) can be accessed is
(A) before effective address calculation has started
(B) during effective address calculation
(C) after effective address calculation has completed
(D) after data cache lookup has completed
SOLUTION
Question. 67
The total size of the tags in the cache directory is
(A) 32 kbits (B) 34 kbits
(C) 64 kbits (D) 68 kbits
SOLUTION
17 11 4
CPV address
Size of tags = There are 217 bytes of tags in every set of cache.
So total = 17 # 2 # 1024
= 34 KB.
Hence (B) is correct option.
Question. 68
Which of the following array elements has the same cache index as
APR [0][0]?
(A) APR[0][4] (B) APR[4][0]
(C) APR[0][5] (D) APR[5][0]
SOLUTION
Elements stored in row major order. Two elements should have same
cache index (15 bits) & their tags may be different (17 bits).
So APR [%] [%] the MSB 17 bits will be changed.
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So on.
This is virtual memory storage.
So 15 LSB of APR [%] [%] & APR [%] [%] are same so same index APR
[%] & APR [4] 17 MSB are different so tags differ.
Hence (B) is correct option.
Question. 69
SOLUTION
= 1024 = 1 = 0.5
1024 + 1024 2
or = 50%
Hence (C) is correct option.
Question. 70
SOLUTION
Question. 71
SOLUTION
YEAR 2009
Question. 72
SOLUTION
Question. 73
A CPU generally handles are interrupt by executing an interrupt
service routine
(A) As soon as an interrupt is raised
(B) By checking the interrupt register at the end of fetch cycle
(C) By checking the interrupt register after finishing the execution of
the current instruction
(D) By checking the interrupt register at fixed time intervals
SOLUTION
Question. 74
Consider a 4 stage pipeline processor. The number of cycles needed
by the four instructions 11, 12, 13, 14 in stages S1, S2, S3, S4 is
shown below:
S1 S2 S3 S4
I1 2 1 1 1
I2 2 3 2 2
I3 2 1 1 3
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I4 1 2 2 2
SOLUTION
We can see a single iteration of given for loop according to the cycles
required.
Cycle S1 S2 S3 S4 Completion
1 I1
2 I1
3 I2 I1
4 I3 I2 I1
5 I3 I2 I1 I1
6 I4 I2
7 I3 I2
8 I4 I2
9 I4 I3 I2
10 I4 I2 I2
11 I4 I3
12 I3
13 I3 I3
14 I4
15 I4 I4
Question. 75
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155
Which one of the following memory block will NOT be in the cache
if LRU replacement policy is used ?
(A) 3 (B) 8
(C) 129 (D) 216
SOLUTION
Question. 76
SOLUTION
Question. 77
SOLUTION
Question. 78
A main memory unit with a capacity of 4 megabytes is build using
1M # 1 − bit DRAM chips. Each DRAM chip has 1K rows of cells with
1 K cells in each row. The time taken for a single refresh operation is
100 nanoseconds. The time required to perform one refresh operation
on all the cells in the memory unit is
(A) 100 nanoseconds (B) 100)210 nanoseconds
(C) 100)220 nanoseconds (D) 3200)220 nanoseconds
SOLUTION
= 32
1 DRAM has 1 K rows
1 ROW has 1 K cells
Total cells in 1 DRAM = K2 = 220
In 32 DRAM = 32 # 220 Cells
1 cell refresh take 100 ns.
So total refresh time
= 32 # 100 # 220 ns
= 3200 # 220 ns.
Question. 79
A-5 stage pipelined processor has Instruction Fetch. (IF), Instruction
Decode (ID), Operand Fetch (OF), Perform Operation (PO) and
Write Operand (WO) stages. The IF, ID, OF and WO stages take 1
clock cycle each for any instruction. The PO stage takes 1 clock cycle
for ADD and SUB instruction. The PO stage takes 1 stake clock cycle
for ADD and SUB instructions 3 clock cycles for MUL instruction, and
6 clock cycles for DIV instruction respectively. Operand forwarding
is used in the pipeline. What is the number of clock cycles needed to
execute the following sequence of instructions ?
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(A) 13 (B) 15
(C) 17 (D) 19
SOLUTION
Figure
Here A = (R 3 /R 4) + R2, R6
Question. 80
The program below uses six temporary variables a, b, c, d, e, f
a=1
b = 10
c = 20
d = a+b
e = c+d
f = c+e
b = c+e
e = b+f
d = 5+e
Assuming that all operations take their operands from register, what
is the minimum number of registers needed to execute this program
without spilling ?
(A) 2 (B) 3
(C) 4 (D) 6
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Architecture
SOLUTION
Replacement
R1 R2 R3
a b c
d b c
d e c
f e c
f b c
f e c
f e d
So all the operations done using 3 registers only.
Hence (B) is correct option.
Question. 81
SOLUTION
required.
4 # 2 + 4 # 20
8 + 80
88 ns
Hence (D) is correct option.
Question. 82
SOLUTION
Miss in both L1 & L2. Cause main memory to transfer that block in
both cache.
1 block of Main memory has 16 words but data bus of L2 has only 4
words. So 4 access of Main memory & 4 access of L2 Cache required
to update L2
4 # 20 + 4 # 200
80 + 800 = 880 ns
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