UNIT-3

GATE LEVEL DESIGN

Introduction

The module (integrated circuit) is implemented in terms of logic gates and interconnections between these
gates. Designer should know the gate-level diagram of the design. In general, gate-level modeling is used
for implementing lowest level modules in a design like, full-adder, multiplexers, etc.

Boolean algebra is used to represent logical(combinational logic) functions of digital circuits. A

combinational logic expression is a mathematical formula which is to be interpreted using the laws of
Boolean algebra. Now the goal of logic design or optimization is to find a network of logic gates that
together compute the combinational logic function we want.

For example, given the expression a+b , we can compute its truth value for any given values of a and b ,
and also we can evaluate relationships such as a+b = c. but logic design is difficult for many reasons:

• We may not have a logic gate for every possible function, or even for every function of n
inputs.
• Not all gate networks that compute a given function are alike-networks may differ greatly
in their area and speed.
• Thus combinational logic expressions are the specification,
Logic gate networks are the implementation,
Area, delay, and power are the costs.
• A logic gate is an idealized or physical device implementing a Boolean function, that is,
it performs a logical operation on one or more logic inputs and produces a single logic
output.
• Logic gates are primarily implemented using diodes or transistors acting as electronic
switches, but can also be constructed using electromagnetic relays (relay logic), fluidic
logic, pneumatic logic, optics, molecules, or even mechanical elements.
• With amplification, logic gates can be cascaded in the same way that Boolean functions
can be composed, allowing the construction of a physical model of all of Boolean logic.
• simplest form of electronic logic is diode logic. This allows AND and OR gates to be
built, but not inverters, and so is an incomplete form of logic. Further, without some kind
of amplification it is not possible to have such basic logic operations cascaded as required
for more complex logic functions.
• To build a functionally complete logic system, relays, valves (vacuum tubes), or
transistors can be used.
• The simplest family of logic gates using bipolar transistors is called resistor-transistor
logic (RTL). Unlike diode logic gates, RTL gates can be cascaded indefinitely to produce
more complex logic functions. These gates were used in early integrated circuits. For
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 higher speed, the resistors used in RTL were replaced by diodes, leading to diode-
transistor logic (DTL).
• Transistor-transistor logic (TTL) then supplanted DTL with the observation that one
transistor could do the job of two diodes even more quickly, using only half the space.
• In virtually every type of contemporary chip implementation of digital systems, the
bipolar transistors have been replaced by complementary field-effect transistors
(MOSFETs) to reduce size and power consumption still further, thereby resulting in
complementary metal–oxide–semiconductor (CMOS) logic. that can be described with
Boolean logic.
CMOS logic gates and other complex gates

General logic circuit Any Boolean logic function (F) has two possible values, either logic 0 or
logic 1. For some of the input combinations, F = 1 and for all other input combinations, F = 0. So
in general, any Boolean logic function can be realized using a structure as shown in figure.

• The switch S1 is closed and switch S2 is open for input combinations that produces F = 1.
• The switch S1 is open and switch S2 is closed for input combinations that produces F = 1.
• The switch S1 is open and switch S2 is open for input combinations that produces F = 0.
Thus the output (F) is either connected to V DD or the ground, where the logic 0 is represented by
the ground and the logic 1 is represented by V DD. So the requirement of digital logic design is to
implement the pull-up switch(S1) and the pull-down switch(S2).

CMOS static logic

A generalized CMOS logic circuit consists of two transistor nets nMOS and pMOS. The pMOS
transistor net is connected between the power supply and the logic gate output called as pull-up
network , Whereas the nMOS transistor net is connected between the output and ground called as
pull-down network. Depending on the applied input logic, the PUN connects the output node to
VDD and PDN connects the output node to the ground.

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The transistor network is related to the Boolean function with a straight forward design
procedure:

• Design the pull down network (PDN) by realizing,

AND(product) terms using series-connected nMOSFETs.

OR (sum) terms using parallel-connected nMOSFETS.

• Design the pull-up network by realizing,

AND(product) terms using parallel-connected nMOSFETs.

OR (sum) terms using series-connected nMOSFETS.
• Add an inverter to the output to complement the function. Some functions are inherently
negated, such as NAND,NOR gates do not need an inverter at the output terminal.

CMOS inverter
A CMOS inverter is the simplest logic circuit that uses one nMOS and one pMOS
transistor. The nMOS is used in PDN and the pMOS is used in the PUN as shown in
figure.

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 Working operation

1) When the input Vin is logic HIGH, then the nMOS transistor is ON and the pMOS
transistor is OFF. Thus the output Y is pulled down to ground (logic 0) since it is
connected to ground but not to source VDD.

2) When the input Vin is logic LOW, then nMOS transistor is OFF and the pMOS
transistor is ON, Thus the output Y is pulled up to V DD(logic 1) since it is connected
to source via pMOS but not to ground.

CMOS NAND gate

The two input NAND function is expressed by Y=A.B

Step 1 Take complement of Y

Y= A.B = A.B

Step 2 Design the PDN

In this case, there is only one AND term, so there will be two nMOSFETs in series as shown in
figure.
Step 3 Design the PUN. In PUN there will be two pMOSFETs in parallel , as shown in figure

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Finally join the PUN and PDN as shown in figure which realizes two –input NAND gate. Note
that we have realized y, rather tat Y because the inversion is automatically provided by the nature
of the CMOS circuit operation,

Working operation

1) Whenever at least one of the inputs is LOW, the corresponding pMOS transistor will
conduct while the corresponding nMOS transistor will turn OFF. Subsequently, the output
voltage will be HIGH.
2) Conversely, if both inputs are simultaneously HIGH, then both pMOS transistors will
turn OFF, and the output voltage will be pulled LOW by the two conducting nMOS
transistors.
CMOS NOR gate
The two input NOR function is expressed by Y=A+B

Step 1 Take complement of Y

Y= A+B = A+B

Step 2 Design the PDN

In this case, there is only one OR term, so there will be two nMOSFETs connected in parallel, as
shown in figure.
Step 3 Design the PUN

In PUN there will be two pMOSFETs in series , as shown in figure

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Finally join the PUN and PDN as shown in figure which realizes two –input NAND gate. Note
that we have realized y, rather tat Y because the inversion is automatically provided by the nature
of the cMOS circuit operation,

Working operation

1) Whenever at least one of the inputs is LOW, the corresponding pMOS transistor will
conduct while the corresponding nMOS transistor will turn OFF. Subsequently, the output
voltage will be HIGH.
2) Conversely, if both inputs are simultaneously HIGH, then both pMOS transistors will
turn OFF, and the output voltage will be pulled LOW by the two conducting nMOS
transistors.

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Complex gates in CMOS logic

A complex logic gate is one that implements a function that can provide the basic NOT, AND
and OR operation but integrates them into a single circuit. CMOS is ideally suited for creating
gates that have logic equations by exhibiting the following,

1) AND-OR-INVERT - AOI form

2) OR-AND-INVERT - OAI form

An AOI logic equation is equivalent to a complemented SOP from, while an AOI equation is
equivalent to a complemented POS structure. In CMOS, output always produces NOT operation
acting on input variable.
1) AOI Logic Function (OR) Design of XOR gate using CMOS logic.

AND-OR-INVERT logic function(AOI) implements operation in the order

AND,OR,NOT. For example ,
let us consider the function Y = AB+CD i.e., Y = NOT((A AND B)OR (C AND D))

The AOI logic gate implementation for Y

CMOS implementation for Y

Step 1: Draw A.B (AND) function first by connecting 2 nMOS transistors in series.

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Step 2: Draw C.D implementation, by using 2 nMOS transistors in series.

Step 3: Y = A.B+C.D , In this function A.B and C.D are added, for addition , we have to draw
parallel connection. So, A.B series connected in parallel with C.D as shown in figure.

Step 4: Draw pMOS connection,

I. In nMOS A,B connected in series. So, in pMOS side, A.B should be connected in
parallel.
II. In nMOS C,D connected in series. So, in pMOS side, C.D should be connected in
parallel.
III. A.B and C.D networks are connected in parallel in nMOS side. So, in pMOS side,
A.B and C.D networks should be connected in series.
IV. In pMOS multiplication should be drawn in parallel, then addition should be
drawn in series as shown in figure.

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Step 5: Take output at the point in between nMOS and pMOS networks.

1) OAI Logic Function (OR) Design of XNOR gate using CMOS logic.

OR-AND-INVERT logic function(AOI) implements operation in the order

OR,AND,NOT. For example ,
let us consider the function Y = (A+B).(C+D) i.e., Y = NOT((A OR B)AND (C OR D))

The OAI logic gate implementation for Y

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CMOS implementation for Y

SWITCH LOGIC
1) Switch logic is mainly based on pass transistor or transmission gate.

2) It is fast for small arrays and takes no static current from the supply, V DD. Hence
power dissipation of such arrays is small since current only flows on switching.

3) Switch (pass transistor) logic is analogous to logic arrays based on relay contacts,
where in path through each switch is isolated from the logic levels activating the
switch.

PASS TRANSISTOR

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 1) This logic uses transistors as switches to carry logic signals from node to node instead
of connecting output nodes directly to VDD or ground(GND)
2) If a single transistor is a switch between two nodes, then voltage degradation.equal to
vt (threshold voltage) for high or low level depends up on nMOS or pMOS logic.

3) When using nMOS switch logic no pass transistor gate input may be driven through
one or more pass transistors as shown in figure.

4) Since the signal out of pass transistor T1 does not reach a full logic 1 by threshold
voltage effects signal is degraded by below a true logic 1, this degraged voltage
would not permit the output of T2 to reach an acceptable logic 1 level.

Advantages

They have topological simplicity.

1) Requires minimum geometry.

2) Do not dissipate standby power, since they do not have a path from supply to ground.

Disadvantages

1) Degradation in the voltage levels due to undesirable threshold voltage effects.

2) Never drive a pass transistor with the output of another pass transistor.

TRANSMISSION GATE

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 1) It is an electronic element, good non-mechanical relay built with CMOS technology.

2) It is made by parallel combination of an nMOS and pMOS transistors with the input
at gate of one transistor being complementary to the input at the gate of the other as
shown in figure.

3) Thus current can flow through this element in either direction.

4) Depending on whether or not there is a voltage on the gate, the connection between
the input and output is either low resistance or high-resistance, respectively Ron =
100Ω and Roff > 5 MΩ.

Operation

• When the gate input to the nMOS transistor is ‘0’ and the complementary ‘1’ is gate input
to the pMOS , thus both are turned off.
• When gate input to the nMOS is ‘1’ and its complementary ‘0’ is the gate input to the
pMOS , both are turned on and passes any signal ‘1’ and ‘0’ equally without any
degradation.
• The use of transmission gates eliminates the undesirable threshold voltage effects which
give rise to loss of logic levels in pass-transistors as shown in figure.

Advantages

1) Transmission gates eliminates the signal degradation in the output logic levels.
2) Transmission gate consists of two transistors in parallel and except near the positive and
negative rails.
Disadvantages

1) Transmission gate requires more area than nMOS pass circuitry.

2) Transmission gate requires complemented control signals.

“ Transmission gate logic can be used to design multiplexers(selector functions)”.

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 Design a 2-input multiplexer using CMOS transmission gates.

Figure shows a 2-input multiplexer circuit using CMOS transmission gate.

If the control input S is low, the TG0 conducts and the output F is equal to A. On the
other hand, if the control input S is high the TG1 conducts and the output F is equal to B.
ALTERNATIVE GATE CIRCUITS

CMOS suffers from increased area and correspondingly increased capacitance and delay, as the
logic gates become more complex. For this reason, designers developed circuits (Alternate gate
circuits) that can be used to supplement the complementary type circuits . These forms are not
intended to replace CMOS but rather to be used in special applications for special purposes.
PSEUDO nMOS Logic

Pseudo nMOS logic is one type of alternate gate circuit that is used as a supplement for the
complementary MOS logic circuits. In the pseudo-nMOS logic, the pull up network (PUN) is
realized by a single pMOS transistor. The gate terminal of the pMOS transistor is connected to
the ground. It remains permanently in the ON state. Depending on the input combinations, output
goes low through the PDN. Figure shows the general building block of logic circuits that follows
pseudo nMOS logic.

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Here, only the nMOS logic (Qn) is driven by the input voltage, while the gate of p-transistor(Qp)
is connected to ground or substrate and Qp acts as an active load for Qn. Except for the load
device, the pseudo-nMOS gate circuit is identical to the pull-down network(PDN) of the
complementary CMOS gate.

The realization of logic circuits using pseudo-nMOS logic is as shown in figure.

Advantages
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 1) Uses less number of transistors as compared to CMOS logic.

2) Geometrical area and delay gets reduced as it requires less transistors.

3) Low power dissipation.

Disadvantages

1) The main drawback of using a pseudo nMOS gate instead of a CMOS gate is that the
always on PMOS load conducts a steady current when the output voltage is lower than
VDD.

2) Layout problems are critical.

DYNAMIC CMOS LOGIC

A dynamic CMOS logic uses charge storage and clocking properties of MOS transistors to
implement logic operations. Figure shows the basic building block of dynamic CMOS logic.
Here the clock ø drives nMOS evaluation transistor and pMOS precharge transistor. A logic is
implemented using an nFET array connected between output node and ground.

The gate (clock ø) defines two phases, evaluation and precharge phase during each clock cycle.

Working

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• When clock ø = 0 the circuit is in precharge phase with the pMOS device Mp ON and the
evaluation nMOS Mn OFF. This establishes a conducting path between VDD and the
output allowing Cout to charge to a voltage V out = VDD. Mp is often called the precharge
FET.

• When clock ø = 1 the circuit is in evaluation phase with the pMOS device Mp OFF and
the evaluation nMOS Mn ON. If the logic block acts like a closed switch the C out can
discharge through logic array and Mn, this gives a final result of V out = VDD, logically
this is an output of F = 1. Charge leakage eventually drops the output to Vout = 0 Vwhich
could be an incorrect logic value.

The logic formation is formed by three series connected FETs (3-input NAND gate) is
shown in figure.

The dynamic CMOS logic circuit has a serious problem when they are cascaded. In the
precharged phase (ø = 0) , output of all the stages are pre-charged to logic high. In the
evaluation phase (ø = 1), the output of all stages are evaluated simultaneously. Suppose in
the first stage, the inputs are such that the output is logic low after the evaluation. In the
second stage, the output of the first stage is one input and there are other inputs. If
theouther inputs of the second stage are such that output of it discharges to logic low, then
the evaluated output of the first stage can never make the output of the second stage logic
high. Ths is because, by the time the first stage is being evaluated, output of the second.
Stage is discharged, since evaluation happens simultaneously. Remember that the output
cannot be charged to logic high in the evaluation phase (ø = 1, pMOSFET in PUN is
OFF), it can only be retained in the logic high depending on the inputs.

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 Advantages

1) Low power dissipation.

2) Large noise margin.

3) Small area due to less number of transistors.\

DOMINO CMOS LOGIC

Standard CMOS logic gates need a PMOS and an NMOS transistor for each logic input. The
pMOS transistors require a greater area tan the nMOS transistors carrying the same current. So, a
large chip area is necessary to perform complex logic operations. The package density in CMOS
is improved if a dynamic logic circuit, called the domino CMOS logic circuit, is used.

Domino CMOS logic is slightly modified version of the dynamic CMOS logic circuit. In this
case, a static inverter is connected at the output of each dynamic CMOS logic block. The
addition of the inverter solves the problem of cascading of dynamic CMOS logic circuits.

The circuit diagram of domino CMOS logic structures as shown in figure as follows
A domino CMOS AND-OR gate that realizes the function y = AB + CD is depicted in fugure .
The left hand part of the circuit containing Mn, Mp, T1,T2,,T3,and T4 forms and AND-OR-
INVERTER (AOI) gate. It derives the static CMOS inverter formed by N2 and P2 in the right-
hand part of the circuit. The domino gate is activated by the single phase clock ø applied to the
NMOS (Mn) and the PMOS (Mp) transistors. The load on the AOI part of the circuits is the
parasitic load capacitance.
Working

• When ø = 0, is ON and Mn is OFF, so that no current flows in the AND-OR paths of the
AOI. The capacitor CL is charged to VDD through Mp since the latter is ON. The input to
the inverter is high, and drives the output voltage V0 to logic-0.

• When ø = 1, Mp is turned OFF and Mn is turned ON. If either (or both) A and B or C and
D is at logic-1, CL discharges through either T2,T1 and Mn or T3,T4 and Mp. So , the
inverter input is driven to logic-0 and hence the output voltage V 0 to logic-1. The
Boolean expression for the output voltage is Y = AB + CD.

Note : Logic input can change only when ø = 0. No changes of the inputs are permitted
when ø = 1 since a discharge path may occur.

Advantages

1) Smaller areas compared to conventional CMOS logic.

2) Parasitic capacitances are smaller so that higher operating speeds are possible.

3) Operation is free of glitches since each gate can make one transition.

disadvantages

1) Non inverting structures are possible because of the presence of inverting buffer.

2) Charge distribution may be a problem.

CLOCKED CMOS LOGIC

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The clocked CMOS logic is also referred as C MOS logic. Figure shows the general
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arrangement of a clocked CMOS (C MOS) logic. A pull-up p-block and a complementary n-
block pull-down structure represent p and n-transistors respectively and are used as implement
clocked CMOS logic shown in figure. However, the logic in this case is connected to the output
only during the ON period of the clock. Figure shows a clocked inverter circuit which is also
belongs to clocked CMOS logic family. The slower rise times and fall times can be expected due
to owing of extra transistors in series with the output.

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Working

• When ø = 1 the circuit acts an inverter , because transistors Q3 and Q4 are ‘ON’ . It is
said to be in the “evaluation mode”. Therefore the output Z changes its previous value.

• When ø = 0 the circuit is in hold mode, because transistors Q3 and Q4 becomes ‘OFF’ . It
is said to be in the “precharge mode”. Therefore the output Z remains its previous value.

NORA CMOS LOGIC:

This design is alternative to DOMINO CMOS logic, eliminates the output buffer without
causing race problems between clock and data that arise when cascading dynamic gates. NORA
CMOS (No Race CMOS) avoids these race problems by cascading alternate nMOS & pMOS
blocks for logic evaluation

.
Fig.NORA CMOS logic
Note that the precharge-and-evaluate timing of nMOS logic stages is accomplished by the clock
signal GC, whereas the pMOS logic stages are controlled by the inverted clock signal, .
The operation of the NORA CMOS circuit is as follows:
• When the clock(GC) signal is low( is high), the output nodes of nMOS logic blocks are
precharged to VDD through the pMOS precharge transistors, whereas the output nodes of pMOS
logic blocks are pre-discharged to 0V through the nMOS discharge transistors, driven by GC bar(
) . When clock changes gates are in the evaluate state.
• When the clock signal makes a low-to-high transition (note that the inverted clock signal GC
bar( ) makes a high-to-low transition simultaneously), all cascaded nMOS and pMOS logic
stages evaluate one after the other, much like the domino CMOS examined earlier.

Fig: NORA CMOS logic circuit example

Disadvantages

Here, the p-tree blocks are slower than the n-tree modules, due to the lower current drive of the
pMOS transistors in the logic network.
DCVS Logic :

Fig: Structure of a DCVSL gate

 Fig: An example for DCVSL gate circuit

Differential cascode voltage switch logic (DCVSL) is a static logic family that, like pseudo-
nMOS logic, does not have a complementary pullup network, but it has a very different structure.
It uses a latch structure for the pullup which both eliminates non-leakage static power
consumption and provides true and complement outputs.

The structure of a generic DCVSL gate is shown in Figure . There are two pulldown networks
which are the duals of each other, one for each true/complement output. Each pulldown network
has a single p-type pullup, but the pullups are cross-coupled. Exactly one of the pulldown
networks will create a path to ground when the gate’s inputs change, causing the output nodes to
switch to the required values. The cross-coupling of the pullups helps speed up the transition—
for example, the complementary network forms a path to ground, the complementary output goes
toward VSS, which turns on the true output’s pullup, raising the true output, which in turn lowers
the gate voltage on the complementary output’s pullup. This gate consumes no DC power (except
due to leakage current), since neither side of the gate will ever have both its pullup and pulldown
network on at once.