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Mtech Vlsi Short Answer Questions

The document contains short answer questions about CMOS VLSI design. It discusses concepts like channel length modulation effect, hierarchy, noise margin, MOS device design equations, threshold voltage-body effect, CMOS inverter characteristics, field programmable gate arrays, effects of varying transistor width-to-length ratio, packaging technologies, modularity, sheet resistance, pseudo-NMOS logic, sources of power dissipation in CMOS circuits like static and dynamic dissipation, short circuit power dissipation, advantages and limitations of pass transistor logic, and drawbacks of dynamic CMOS logic that can be overcome using domino logic.

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Rachit Nema
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
662 views

Mtech Vlsi Short Answer Questions

The document contains short answer questions about CMOS VLSI design. It discusses concepts like channel length modulation effect, hierarchy, noise margin, MOS device design equations, threshold voltage-body effect, CMOS inverter characteristics, field programmable gate arrays, effects of varying transistor width-to-length ratio, packaging technologies, modularity, sheet resistance, pseudo-NMOS logic, sources of power dissipation in CMOS circuits like static and dynamic dissipation, short circuit power dissipation, advantages and limitations of pass transistor logic, and drawbacks of dynamic CMOS logic that can be overcome using domino logic.

Uploaded by

Rachit Nema
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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CMOS VLSI Design

Short Answer Questions

1. What is channel length modulation effect?


Ans--It is assumed that channel length remains constant as the drain voltage is increased
appreciably beyond the on set of saturation. As a consequence, the drain current remains
constant in the saturation region. In practice, however the channel length shortens as the
drain voltage is increased. For long channel lengths, say more than 5 m, this variation of
length is relatively very small compared to the total length and is of little consequence.
However, as the device sizes are scaled down, the variation of length becomes more and
more predominant and should be taken into consideration. As a consequence, the drain
current increases with the increase in drain voltage even in the saturation region.
Leff = L-Lshort
IDS =
2. Discuss the concept of hierarchy.
Ans -- The use of hierarchy, or divide and conquer technique involves dividing a module
into sub- modules and then repeating this operation on the sub-modules until the complexity
of the smaller parts becomes manageable. This approach is very similar to the software case
where large programs are split into smaller and smaller sections until simple subroutines,
with well-defined functions and interfaces, can be written.

3. What is noise margin?


Ans -- An important parameter called noise margin is associated with the input-output
voltage characteristics of a gate. It is defined as the allowable noise voltage on the input of a
gate so that the output is not affected.
NMH VOH - VIH noise margin high
NML VIL - VOL

noise margin low

4. What are the MOS device design equations


Ans

(Cutoff)

(Linear )

(Saturation)
5. What is Threshold voltage-body effect?
Ans -- All MOS transistors are usually fabricated on a common substrate and substrate
(body) voltage of all devices is normally constant. However, when circuits are realized using
a number of MOS devices, several devices are connected in series. This results in different
source potentials for different devices. It may be noted that the threshold voltage Vt is not
constant with respect to the voltage difference between the substrate and the source of the
MOS transistor. This is known as the substrate-bias effect or body effect. Increasing the Vsb
causes the channel to be depleted of charge carries and this leads to increase in the threshold
voltage.

6. Draw the dc characteristics of a CMOS inverter.


Ans

7. What is Field Prograammable Gate Array(FPGA)?


Ans -- Fully fabricated FPGA chips containing thousands of logic gates or even more, with
programmable interconnects, are available to users for their custom hardware programming
to realize desired functionality. This design style provides a means for fast prototyping and
also for cost-effective chip design, especially for low-volume applications. A typical field
programmable gate array (FPGA) chip consists of I/O buffers, an array of configurable logic
blocks (CLBs), and programmable interconnect structures.

8. Explain the effect of varying (W/L) ratio of transistor on voltage transistor char.
Ans The invertor threshold voltage VTH shifts to lower values with increasing W/L ratio.

9. What are packaging technologies?


Ans -- Packaging technology is critical to the success of the chip development. It ensures
sufficient design margins to accommodate the parasitics of the package.
Some common IC packages are
(a)
(b)
(c)
(d)
(e)

Dual in-line packages (DIP)


Pin grid array (PGA) packages
Chip carrier packages (CCP)
Quad flat packages (QFP)
Multi-chip modules (MCM)

10. Discuss the concept of modularity.


Ans -- Modularity in design means that the various functional blocks which make up the
larger system must have well-defined functions and interfaces. Modularity allows that each
block or module can be designed relatively independently from each other, since there is no
ambiguity about the function and the signal interface of these blocks. All of the blocks can be
combined with ease at the end of the design process, to form the large system. The concept of
modularity enables the parallelisation of the design process. It also allows the use of generic
modules in various designs - the well-defined functionality and signal interface allow plugand-play design.

Unit 2
1. What is sheet resistance? Find out the expression of the resistance of rectangular
sheet in terms of sheet resistance.
Ans -- The sheet resistance is defined as the resistance per unit area of a sheet of material.
Consider a rectangular sheet of material with
Resistivity = ,
Width = W,
Thickness = t
and Length = L.
Then, the resistance between the two ends is

Where
2. How do you realize pseudo nMOS logic circuits. Compare its advantage and
disadvantages with respect to standard static CMOS circuits.
Ans -- In the pseudo-nMOS realization, the pMOS network of the static CMOS realization is
replaced by a single pMOS transistor with its gate connected to GND. An n-input pseudo
nMOS requires n+1 transistors compared to 2n transistors of the corresponding static CMOS
gates. This leads to substantial reduction in area and delay in pseudo nMOS realization. As
the pMOS transistor is always ON, it leads to static power dissipation when the output is
LOW.

3. What are the sources of power dissipation in a CMOS circuit.


Ans There are two components that establish the amount of power dissipation in a CMOS
circuit
(a) Static dissipation due to leakage current or other current drawn continuously from the
power supply.
(b) Dynamic dissipation due to
charging and discharging of load capacitances
short circuit current while both PMOS and NMOS networks are partially ON
Ptotal = Pstatic + Pdynamic
4. What is short circuit power dissipation?
Ans -- As input changes slowly, power dissipation takes place even when there is no load or
parasitic capacitor. When the input is greater than Vtn and less than (Vdd Vtp), both the
nMOS and pMOS transistors are ON. The supply voltage is now shorted to GND through
the two transistors. This leads to the short circuit power dissipation.
5. What are the advantages and limitations of pass transistor logic circuits?
Ans -- Pass transistor realization is ratioless, i.e. there is no need to have L:W ration in the
realization. All the transistors can be of minimum dimension. Lower area due to smaller
number of transistors in pass transistor realization compared to static CMOS realization. Pass
transistor realization also has lesser power dissipation because there is no static power and
short-circuit power dissipation in pass transistor circuits. The limitations are
(a) Higher delay in long chain of pass transistors
(b) Multi-threshold Voltage drop (Vout = Vdd Vtn)
(c) Complementary control signals and
(d) Possibility of sneak path because of the presence of path to Vdd and GND.
6. What is the drawback of dynamic CMOS logic.
Ans -- In Dynamic logic, problem arises when cascading one gate to the next. The precharge
"1" state of the first gate may cause the second gate to discharge prematurely, before the first
gate has reached its correct state. This uses up the "precharge" of the second gate, which
cannot be restored until the next clock cycle, so there is no recovery from this error.

7. How domino CMOS logic can overcome the drawback of dynamic cmos logic?
Ans -- Domino CMOS is a special form of precharge and evaluate CMOS with an inverting
buffer at the output. Problem with faulty discharge of precharged nodes in CMOS dynamic
logic circuits can be solved by placing an inverter in series with the output of each gate: All
inputs to N logic blocks therefore will be at zero volts during precharge and will remain at
zero until the evaluation stage has logic inputs to discharge the precharged node. However,
all circuits only provide non-inverted outputs.

During precharge phase (when = 0) the output node of the dynamic CMOS stage is
precharged to a high level, and the output of the CMOS inverter becomes low. During
evaluation phase (when = 1) there are two possibilities:
The output node either discharged to a low level through nMOS circuitry, or
It remains high

8.

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