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    Low - Power - VLSI - JUNE 2023

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    1ms21ec132
    The document is an exam paper for the course Low Power VLSI Design. It contains 10 questions across 5 units: 1. The first unit covers sources of power dissipation and limits to low power design at the material, device and circuit levels. Questions assess derivation of power equations and calculating power dissipation on a data bus. 2. The second unit covers precomputation logic, transistor network restructuring, gate sizing, pin reordering and power latches. 3. Unit three questions compare adder circuits and covers Manchester carry chains and clock gating for power reduction. 4. Unit four examines delay balancing multiplier cells, Baugh-Wooley multiplication and Wallace tree multipliers.

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    Low - Power - VLSI - JUNE 2023

    Uploaded by

    1ms21ec132
    32 views2 pages
    The document is an exam paper for the course Low Power VLSI Design. It contains 10 questions across 5 units: 1. The first unit covers sources of power dissipation and limits to low power design at the material, device and circuit levels. Questions assess derivation of power equations and calculating power dissipation on a data bus. 2. The second unit covers precomputation logic, transistor network restructuring, gate sizing, pin reordering and power latches. 3. Unit three questions compare adder circuits and covers Manchester carry chains and clock gating for power reduction. 4. Unit four examines delay balancing multiplier cells, Baugh-Wooley multiplication and Wallace tree multipliers.

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    low_power_VLSI_JUNE 2023

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    The document is an exam paper for the course Low Power VLSI Design. It contains 10 questions across 5 units: 1. The first unit covers sources of power dissipation and limits to low power design at the material, device and circuit levels. Questions assess derivation of power equations and calculating power dissipation on a data bus. 2. The second unit covers precomputation logic, transistor network restructuring, gate sizing, pin reordering and power latches. 3. Unit three questions compare adder circuits and covers Manchester carry chains and clock gating for power reduction. 4. Unit four examines delay balancing multiplier cells, Baugh-Wooley multiplication and Wallace tree multipliers.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    32 views2 pages

    Low - Power - VLSI - JUNE 2023

    Uploaded by

    1ms21ec132
    The document is an exam paper for the course Low Power VLSI Design. It contains 10 questions across 5 units: 1. The first unit covers sources of power dissipation and limits to low power design at the material, device and circuit levels. Questions assess derivation of power equations and calculating power dissipation on a data bus. 2. The second unit covers precomputation logic, transistor network restructuring, gate sizing, pin reordering and power latches. 3. Unit three questions compare adder circuits and covers Manchester carry chains and clock gating for power reduction. 4. Unit four examines delay balancing multiplier cells, Baugh-Wooley multiplication and Wallace tree multipliers.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    ECE644

    USN 1 M S
    (Autonomous Institute, Affiliated to VTU)
    (Approved by AICTE, New Delhi & Govt. of Karnataka)
    Accredited by NBA & NAAC with ‘A+’ Grade

    SUPPLEMENTARY SEMESTER EXAMINATIONS – JULY 2023

    Created by trial version of DocuFreezer


    B.E. - Electronics and Communication
    Program : Semester : VI
    Engineering
    Course Name : Low Power VLSI Design Max. Marks : 100
    Course Code : ECE644 Duration : 3 Hrs

    Instructions to the Candidates:


     Answer one full question from each unit.

    UNIT - I
    1. a) Explain in detail: CO1 (10)
    i. The sources of power dissipation
    ii. Need for low power VLSI circuits
    b) Explain the following in detail: CO1 (10)
    i. Material limits
    ii. Device limits
    iii. Circuit limits.

    2. a) Using the concept of charging and discharging of capacitance CO1 (10)


    i. Derive expression P=CLV2f
    ii. A 32 bit off-chip bus operating at 5V and 66MHz clock rate is driving
    a capacitance of 25pF/bit. Each bit is estimated to have a toggling
    probability of 0.25 at each clock cycle. What is the power dissipation in
    operating the bus?
    b) Explain the effect of short circuit current and sub threshold current on CO1 (06)
    power dissipation.
    c) Explain need for low power VLSI Design. CO1 (04)

    UNIT - II
    3. a) Explain the design issues related to precomputation logic technique. CO2 (10)
    b) With four different implementations, explain transistor network CO2 (10)
    restructuring for the expression Y=AB+C.

    4. a) With suitable example explain the following: CO2 (10)


    i. Gate sizing
    ii. Pin reordering.
    b) Discuss the operation flow power latches. CO2 (05)
    c) Explain about transistor gating. CO2 (05)

    UNIT - III
    5. a) Write a note on conditional sum adders. CO3 (10)
    b) Compare Ripple carry adder, Carry skip adder and conditional sum CO3 (10)
    adder.

    6. a) Discuss the operation of Manchester carry chain. CO3 (10)


    b) What is meant by Clock gating? Explain how it is used to reduce power CO3 (10)
    consumption.

    UNIT- IV
    7. a) Explain Delay balancing multiplier cell. CO4 (10)
    b) Explain Baugh-Wooley multiplier with 2’s complement generator. CO4 (10)

    Page 1 of 2
    ECE644
    8. a) Explain Wallace tree multiplier with neat diagram. CO4 (10)
    b) Explain bit-line precharge and equalization using nMOS and pMOS loads. CO4 (10)

    UNIT - V
    9. a) Schedule and map the dataflow graph to the hardware architecture for CO5 (10)

    Created by trial version of DocuFreezer


    the function Yn=anbn+6an-1
    b) Write an note on: CO5 (10)
    i) Guarded Evaluation ii) Bus Multiplexing.

    10. a) Explain power optimization using operator reduction and substitution CO5 (10)
    with examples.
    b) Explain the different architectures are used for voltage scaling. CO5 (10)

    ********************************

    Page 2 of 2

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