EE46

USN 1 M S
(Autonomous Institute, Affiliated to VTU)
(Approved by AICTE, New Delhi & Govt. of Karnataka)
Accredited by NBA & NAAC with ‘A+’ Grade

EXAMINATIONS SEPTEMBER /OCTOBER 2021

SUPPLEMENTARY SEMESTER / GRADE IMPROVEMENT/ RE –REGISTERED CANDIDATES
Program : B.E. : Electrical and Electronics Engineering Semester : IV
Fundamentals of Modern VLSI Devices
Course Name : Max. Marks : 100
and Fabrication
Course Code : EE46 Duration : 3 Hrs

Instructions to the Candidates:

 Answer any five full questions.

1. a) Write a brief note on the evolution of VLSI device technology. CO1 (05)
b) What are the two mechanisms that determine the carrier transport in CO1 (08)
Silicon? Explain in brief.
c) Draw the band diagram of a pn junction at thermal equilibrium and CO1 (07)
derive the expression for built in potential.

2. a) How are energy bands formed in Silicon? Draw the energy band CO1 (06)
diagram and explain the significance of forbidden gap.
b) Derive the Poisson’s equation with relevance to the operation of VLSI CO1 (07)
devices.
c) A sample of Si at 300K of length 2.5 cm and a cross sectional area of CO1 (07)
2mm2 is doped with 1017/cm3 of phosphorous and 9x1016/cm3 of Boron.
Determine the (i) the conductivities of sample due to electrons and
that due to holes (ii) the resistance of the sample. Given µ n=
2
626cm /Vs and µp= 292cm /Vs 2

3. a) With relevant diagram explain the Czochralski method for crystal CO2 (06)
growth and purification.
b) With necessary band diagram explain why Fermi level is pinned at CO2 (08)
inversion in a MOSCAP made of Aluminium gate, SiO2 insulator and
p stype Si substrate.
c) What are the advantages of Silicon over other materials that it still CO2 (06)
drives the semiconductor industry?

4. a) Write the process flow and explain the fabrication process of a pn CO2 (08)
junction diode.
b) Determine the flat band voltage and the threshold voltage for a MOS CO2 (07)
device that has a Silicon p substrate with N A = 1016cm-3 and uses Al as
the gate. Given Qi = 5x1010 qC/cm2 , εr for oxide =3.9 and tox =200
Angstroms, εr for Si=11.8, ni =1x1010cm-3, Eg= 1.12eV and Ψs =4.15V
c) Define flat band voltage. Discuss how it affects the computation of CO2 (05)
threshold voltage.

5. a) Illustrate with the help of a plot, what happens in a nMOS transistor CO3 (07)
when the applied drain potential is increased from 0V to VDD max,
keeping gate to source potential just above threshold value. Why is the
current not dropping to zero after pinch off? Which carrier transport

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 EE46
mechanism accounts for the continuity of the drain current beyond
pinch off?
b) With relevant band diagram compare the effect of different bias CO3 (09)
voltage on a n channel MOSFET (i) Vgs = VFB,ii) Vgs˃0 iii) Vgs˂0
c) Write a brief note on oxide charges present in a MOSFET. CO3 (04)

6. a) Consider an n-channel MOSFET with substrate doping NA = 10 -14 /cm3. CO3 (08)
The oxde thickness is 500Å with a parasitic charge
density = 1010 /cm2. If Фms = -0.83 V, compute threshold voltage.
Given: kT/q = 0.025V, Ni = 1.5 x 1010/cm3, Єrsi = 12, єrox = 3.9.
b) Draw the drain characteristics of a typical MOSFET and explain the CO3 (06)
condition for Pinch-Off.
c) Explain the different types of MOSFETs with relevant sketches. CO3 (06)

7. a) Compare and contrast the two types of isolation procedures in CMOS CO4 (08)
fabrication by showing the different photolithography steps.
b) Explain how a CMOS INVERTER is realized. Verify its truth table for CO4 (07)
different input conditions.
c) Taking any example, explain the concept of modularity and regularity CO4 (05)
in transistor design methodology.

8. a) Explain with relevant sketches the process flow for getting a n channel CO4 (08)
device in p well (twin wells are already existing in the substrate).
b) Write a brief note on the design abstraction levels in vlsi technology. CO4 (06)
c) Differentiate between “through hole” and “surface mount” chips CO4 (06)
highlighting their advantages.

9. a) Draw the structure of a NPN BJT as fabricated in an IC. Based on the CO5 (08)
CMOS process flow that you have studied suggest a process flow
(through flow chart only) to fabricate a BJT.
b) Why is MOSFET considered as a surface channel device in comparison CO5 (07)
with BJT which is a bulk device? Discuss with relevant diagrams.
c) Differentiate between the active and inverse active mode of operation CO5 (05)
of BJT.

10. a) Isolation is an important step in transistor fabrication. Compare the CO5 (08)
isolation procedure followed during the fabrication of BJTs and
MOSFETs with relevant sketches.
b) Highlight the advantage of placing the devices in “tubs” with relevance CO5 (06)
to BJT fabrication.
c) Sketch the symbol of a PNP and NPN transistor showing the current CO5 (06)
direction and explain the terminology.

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