EKT 303 – PRINCIPLES OF COMPUTER ARCHITECTURE

LAB 1: Introduction to Verilog and Quartus II design software

Student Name(s) Matrix No. Programme

1. Mohamad Azmeer Bin Kamarudin 171081317 RK53
2.

Task 1:

Mark Rubrics
DESIGN
4 Correct Verilog design with comments
3 Correct Verilog design without comment
2 Verilog design is partially correct
1 Totally wrong Verilog design
RESULT
3 Correct and neat presented waveform and RTL informative label.
2 Waveform and RTL partially correct or correct waveform and RTL but without label.
1 Waveform and RTL consist mistakes and badly presented.
DISSCUSIONS
5 Excellent and detail discussion by relate to design and result of each & every figures provided. Convincing
and smooth explanation
2 Simple discussion with acceptable explanation
1 The discussion did not provide any information related to the experiment. Poorly presented discussion.

Task 2:
Mark Rubrics
DESIGN
4 Correct Verilog design with comments
3 Correct Verilog design without comment
2 Verilog design is partially correct
1 Totally wrong Verilog design
RESULT
3 Correct and neat presented waveform and RTL informative label.
2 Waveform and RTL partially correct or correct waveform and RTL but without labelling.
1 Waveform and RTL consist mistakes and badly presented.
DISSCUSIONS
5 Excellent and detail discussion by relate to design and result of each & every figures provided. Convincing
and smooth explanation
2 Simple discussion with acceptable explanation
1 The discussion did not provide any information related to the experiment. Poorly presented discussion.

Penalty:
Mark Rubrics
0 Plagiarism
0 Late submission

SCHOOL OF COMPUTER AND COMMUNICATION ENGINEERING

Sem2-2018/2019
 EKT 303 – PRINCIPLES OF COMPUTER ARCHITECTURE

TASK 1:

Full Adder:
a) Verilog of Full Adder:

b) Waveform of Full Adder:

c) Truth Table of Full Adder:

INPUTS OUTPUTS
X Y Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

The waveform of the full adder that have been simulated in the Quartus II is correct since it
shows the same result as the truth table of the full adder

SCHOOL OF COMPUTER AND COMMUNICATION ENGINEERING

Sem2-2018/2019
 EKT 303 – PRINCIPLES OF COMPUTER ARCHITECTURE

4-Bit Ripple Carry Adder:

a) Verilog of 4-Bit Ripple Carry Adder:

b) Waveform of 4-Bit Ripple Carry Adder:

c) Truth Table of 4-Bit Ripple Carry Adder:

X Y OUTPUTS
X3 X2 X1 X0 Y3 Y2 Y1 Y0 C S3 S2 S1 S0
0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 1 0 0 0
1 0 0 0 1 0 0 0 1 0 0 0 0
1 0 1 0 1 0 1 0 1 0 1 0 0
1 1 0 0 1 1 0 0 1 1 0 0 0
1 1 1 0 1 1 1 0 1 1 1 0 0
1 1 1 1 1 1 1 1 1 1 1 1 0

The waveform of 4-bit ripple carry adder that have been simulated in the Quartus II is correct
since it shows the same result as the truth table of the 4-bit ripple carry adder. The truth table above was
obtained from the internet.

SCHOOL OF COMPUTER AND COMMUNICATION ENGINEERING

Sem2-2018/2019
 EKT 303 – PRINCIPLES OF COMPUTER ARCHITECTURE

d) RTL of 4-Bit Ripple Carry Adder:

Sum and Cout of the Full Adder 1 is valid only after the propagation delay of Full Adder 1. In
the same way, Sum of the Full Adder 4 is valid only after the joint propagation delays of Full Adder 1
to Full Adder 4. Thus, the final result of the ripple carry adder is valid only after the joint propagation
delays of all full adder circuits inside it.

TASK 2:

4-Bit Adder/ Subtractor:

a) Verilog of 4-Bit Adder/Subtractor:

SCHOOL OF COMPUTER AND COMMUNICATION ENGINEERING

Sem2-2018/2019
 EKT 303 – PRINCIPLES OF COMPUTER ARCHITECTURE

b) Waveform of 4-Bit Adder/Subtractor:

c) RTL of 4-Bit Adder/Subtractor:

The operations of both addition and subtraction can be performed by a one common binary
adder. Such binary circuit can be designed by adding an Ex-OR gate with each full adder. The figure
above shows the 4-bit binary adder/subtractor which has two 4 bit inputs as X3 X2 X1 X0 and Y3 Y2
Y1 Y0.

SCHOOL OF COMPUTER AND COMMUNICATION ENGINEERING

Sem2-2018/2019