Plasma TV: Service Manual

Internal Use Only
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Europe/Africa http://eic.lgservice.com
Asia/Oceania http://biz.lgservice.com
PLASMA TV
SERVICE MANUAL
CHASSIS : PA31A
MODEL : 50PN4500 50PN4500-TA
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL67687001 (1212-REV00) Printed in Korea

CONTENTS
CONTENTS . ............................................................................................. 2
SAFETY PRECAUTIONS ......................................................................... 3
SPECIFICATION........................................................................................ 4
ADJUSTMENT INSTRUCTION................................................................. 6
BLOCK DIAGRAM................................................................................... 14
EXPLODED VIEW .................................................................................. 15
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright © LG Electronics. Inc. All rights reserved. -2- LGE Internal Use Only
Only for training and service purposes
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.
AC Volt-meter
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed

metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical Good Earth Ground
such as WATER PIPE,
shock.
To Instrument's CONDUIT etc.
exposed
Leakage Current Cold Check(Antenna Cold Check)
METALLIC PARTS
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range
This spec sheet is applied all of the PDP TV with PA31A chassis.
2. Requirement for Test

Each part is tested as below without special appointment.
(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

(2) Relative Humidity: 65 % ± 10 %
(3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
(4) Specification and performance of each parts are followed each drawing and specification by part number in accordance with
BOM.
(5) The receiver must be operated for about 5 minutes prior to the adjustment.
3. Test method
(1) Performance: LGE TV test method followed
(2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC
4. Module General Specification

- 50" 2D HD
No Item Specification Remark
1 Display Screen Device 127 cm (50 inch) wide Color Display Module PDP
2 Aspect Ratio 16:9
3 PDP Module PDP50T5####,
RGB Closed (Well) Type, Glass Filter (38%)
Pixel Format: 1024 horiz. By 768 ver.
4 Operating Environment 1) Temp. : 0 ~ 40 deg LGE SPEC
2) Humidity : 20 ~ 80%
5 Storage Environment 1) Temp. : -20 ~ 60 deg
2) Humidity : 10 ~ 90 %
6 Input Voltage AC100 ~ 240V, 50/60Hz Maker LG
5. Model General Specification
No Item Specification Remark
1 Market Albania, Austria, Belgium, Bosnia, Bulgaria, Coratia, 36 Country
Czech, Denmark, Estonia, Finland, France, Germany,
Greece, Hungary, Ireland, Italy, Kazakhstan, Latvia,
Lithuania, Luxembourg, Morocco, Netherlands,
Norway, Poland, Portugal, Romania, Russia, Serbia,
Slovenia, Spain, Sweden, Slovakia, Switzerland,
Turkey, Ukraine, UK
Australia, New Zealand, Malaysia, Indonesia, Non-EU
Singapore, South Africa, Israel, Iran, Vietnam, Kenya,
Asia,Non-EU analog, CHINA(cormmercial)
2 Broadcasting system 1) PAL/SECAM BG Programme Coverage (EU)
2) PAL/SECAM DK Digital TV
3) PAL I / II - PD31B/C are not support SECAM L/L`
4) SECAM L/L’ - Only PD31B support DVB-T2
5) DVB T - Only PD31C support DVB-S2
6) DVB C Analogue TV
7) DVB T2 VHF: E2 to E12, UHF: E21 to E69,
8) DVB S2 CATV: S1 to S20, HYPER: S21 to S47
1) PAL/SECAM BG Programme Coverage (NON-EU)
2) PAL/SECAM DK Digital TV
3) PAL I VHF 04 to 13, UHF 27 to 69
4) NTSC M Analogue TV
5) DVB T VHF/UHF 1 to 78, CATV 01 to 71
3 Receiving system Analog : Upper Heterodyne
Digital : COFDM
4 Scart Jack (1EA) PAL, SECAM EU ONLY
5 Component Input (1EA) Y/Cb/Cr, Y/ Pb/Pr
6 RGB Input (1EA) RGB-PC Commercial Model ONLY
7 RS232C (1EA) SVC Commercial Model ONLY
8 AV (2EA) CVBS ( Hybrid :1) EU model have 1 AV ( Hybrid)
9 HDMI Input (2 or 3EA) HDMI-PC HDMI/PC 1, HDMI2
HDMI-DTV
10 Audio Input (1EA) DVI Audio, Component L/R Input
11 SPDIF Out (1 EA) SPDIF Out
12 USB (1EA) for SVC, S/W Download, DivX
13 LAN only DVB-T2 (UK, Irend) Model
14 PCMCI (1EA) DVB-T/C Decryption Interface, CI+ EU ONLY
ADJUSTMENT INSTRUCTION
1. Application Range 3. Main PCB check process
This spec. sheet applies to PA31A chassis applied PDP TV all * APC - After Manual-Insult, executing APC
models manufactured in TV factory.
* Boot file Download
(1) Execute ISP program “Mstar ISP Utility” and then click
2. Designation “Config” tab.
(1) T he adjustment is according to the order which is (2) Set as below, and then click “Auto Detect” and check “OK”
designated and which must be followed, according to the message
plan which can be changed only on agreeing. If “Error” is displayed, Check connection between computer,
(2) Power adjustment : Free Voltage. jig, and set.
(3) Magnetic Field Condition: Nil. (3) Click “Read” tab, and then load download file (XXXX.bin)
(4) Input signal Unit: Product Specification Standard. by clicking “Read”
(5) Reserve after operation: Above 5 Minutes (Heat Run)
Temperature : at 25 °C ± 5 °C
Relative humidity : 65 % ± 10 %
Input voltage : 220V, 60Hz
(6) A djustment equipments : Color Analyzer (CA-210 or
CA-110), DDC Adjustment Jig equipment, SVC remote
controller.
(7) The receiver must be operated for about 5 minutes prior to
the adjustment when module is in the circumstance of over
15
(4) Click “Connect” tab. If “Can’t ” is displayed, Check
- In case of keeping module is in the circumstance of 0°C, it connection between computer, jig, and set.
should be placed in the circumstance of above 15°C for 2
hours.
- In case of keeping module is in the circumstance of below
-20°C, it should be placed in the circumstance of above
15°C for 3 hours.
■ After RGB Full White in HEAT-RUN Mode, the receiver must

be operated prior to the adjustment.
■ Enter into HEAT-RUN MODE
1) Press the POWER ON KEY on R/C for adjustment.
2) OSD display and screen display PATTERN MODE. (5) Click “Auto” tab and set as below.
● Set is activated HEAT run without signal generator in this (6) Click "Run".
mode. (7) After downloading, check "OK" message.
● Single color pattern ( WHITE ) of HEAT RUN MODE uses to
check panel.
● Caution : If you turn on a still screen more than 20 minutes
(Especially digital pattern, cross hatch pattern), an
after image may be occur in the black level part of
the screen.
(8) Push The “IN STOP KEY” – For memory initialization.
Case1 : Software version up
1) After downloading S/W by USB , Multi-vision set will reboot
automatically
2) Push “In-stop” key
3) Push “Power on” key
4) Function inspection
5) After function inspection, Push “In-stop” key.
Case2 : Function check at the assembly line

1) When TV set is entering on the assembly line, Push “In-
stop” key at first.
2) Push “Power on” key for turning it on.
-> If you push “Power on” key, TV set will recover channel
information by itself.
3) After function inspection, Push “In-stop” key.
* USB DOWNLOAD(*.epk file download) 3.1. ADC Process
(1) Put the USB Stick to the USB socket 3.1.1. ADC
(2) Automatically detecting update file in USB Stick ■ Enter Service Mode by pushing “ADJ” key,
- If your downloaded program version in USB Stick is Low, ■ Enter Internal ADC mode by pushing “►” key at “5. ADC
it didn’t work. Calibration”
- B ut your downloaded version is High, USB data is
automatically detecting
(3) Show the message “Copying files from memory”
(4) Updating is staring. * Caution : Using ‘power on’ button of the Adjustment R/C ,
power on Multi-vision.
* ADC Calibration Protocol (RS232)

NO Enter ADC adjust
Adjust MODE
Item Adjust ‘Mode In’ ADC Adjust
CMD 1 A A
CMD 2 A D
Data 0 0 1
(5) U pdating Completed, The Multi-vision will restart
automatically. 0 0
(6) I f your Multi-vision is turned on, check your updated When transfer the Automatically adjustment
version and Tool option. (explain the Tool option, next ‘Mode In’, (The use of a internal
stage) Carry the command. pattern)
* After downloading, have to adjust TOOL OPTION again. - Adjust Sequence

1) Push "IN-START" key in service remote controller. ▪aa 00 00 [Enter Adjust Mode]
2) Select "Tool Option 1" and Push “OK” button. ▪xb 00 40 [Component1 Input (480i)]
3) P unch in the number. (Each of models has their ▪ad 00 10 [Adjust 480i Comp1]
number.) ▪aa 00 90 End Adjust mode
4) Completed selecting Tool option. * Required equipment : Adjustment R/C.
50PN4500-TA
3.2. Function Check
HD/FHD HD
3.2.1. Check display and sound
Tool option 1 36864 ■ Check Input and Signal items. (cf. work instructions)
Tool option 2 5392 1) TV
2)AV (SCART/ CVBS)
Tool option 3 3313 3) COMPONENT (480i)
Tool option 4 51398 4) HDMI
5) PC Audio In
Tool option 5 10
* Display and Sound check is executed
by Remote controller.
* Caution : Not to push the INSTOP KEY after completion if

the function inspection.
4. Total Assembly line process 4.2. Adjustment Preparation
● Required Equipment
4.1. POWER PCB Assy voltage adjustment - Remote controller for adjustment
(Vs voltage adjustment)
- Color Analyzer ( CS-1000, CA-100,100+,CA-210 or same
product : CH 11 (PDP)
4.1.1.Test equipment : D.M.M 1EA * Please adjust CA-210, CA-100+ by CS-1000 before measur-
ing
4.1.2. Condition for adjustment - Auto W/B adjustment instrument(only for Auto adjust-
- No signal with the snow noise in RF mode ment)
- 9 Pin D-Sub Jack(RS232C) is connected to the AUTO
4.1.3. Connection Diagram for Measuring W/B EQUIPMENT.
: refer to fig.7
Before Adjust of White Balance, Please press
4.1.4. Adjustment method POWER ONLY key
4.1.4.1 Vs adjustment
(1) Connect + terminal of D. M..M. to Vs TP, connect -terminal - Adjust Process will start by execute RS232C Command.
to GND. ● Color temperature standards according to CSM and Module
(2) After turning VR901, voltage of D.M.M adjustment as same CSM PLASMA
as Vs voltage which on label of panel right/top ( deviation
; ±0.5V) Cool 11000K
Medium 9300K
4.1.4.2 Va adjustment
(1) Connect + terminal of D. M..M. to Va TP, connect -terminal Warm 6500K
to GND.
(2) After turning VR502, voltage of D.M.M adjustment as same ● CS-1000/CA-100+/CA-210(CH 10) White balance adjust-
as Va voltage which on label of panel right/top ( deviation ment coordinates and color temperature.
; ±0.5V) CSM Color Coordination Temp ± Color
x y Coordination
COOL 0.276 0.283 11000K 0.002

MEDIUM 0.285 0.293 9300K 0.002
WARM 0.313 0.329 6500K 0.002
* Connecting picture of the measuring instrument (On Auto-

matic control)
- Inside PATTERN is used when W/B is controlled. Con-
nect to auto controller or push Adjustment R/C POWER-
ON -> Enter the mode of White-Balance, the pattern will
come out.
* Auto-control interface and directions * After You finish all adjustments, Press “In-start” button and
1) Adjust in the place where the influx of light like floodlight compare Tool option and Area option value with its BOM, if it
around is blocked. (Illumination is less than 100Lux). is correctly same then unplug the AC cable.
2) Adhere closely the Color Analyzer ( CA210 ) to the If it is not same, then correct it same with BOM and unplug
module less than 10cm distance, keep it with the surface AC cable.
of the Module and Color Analyzer’s Prove vertically. For correct it to the model’s module from factory JIG model.
(80~100°). *P ush The “IN STOP KEY” after completing the function
3) Aging time inspection. And Mechanical Power Switch must be set “ON”
- After aging start, keep the power on (no suspension of * To check the coordinates of White Balance, you have to
power supply) and heat-run over 5 minutes. measure at the below conditions.
- Using ‘no signal’ or ‘full white pattern’ or the others, - Picture mode : Vivid, Energy Saving : Off, Below the Ad-
check the back light on. vanced control, Dynamic Contrast : Off, Dynamic Colour : Off
Colour Temp.
■ Auto adjustment Map(RS-232C)
RS-232C COMMAND Cool 30
[ CMD ID DATA ] Medium 0
Wb 00 00 White Balance Start
Warm 30
Wb 00 ff White Balance End
-> Picture Mode change : Vivid -> Vivid(User)
RS-232C M CENTER M
COMMAND I (DEFAULT) A
[CMD ID DATA] N X 4.3. DDC EDID Write (HDMI 256Byte)
Cool Mid Warm Cool Mid Warm -> Not used any more, Use Auto D/L
■ Connect HDMI Signal Cable to HDMI Jack.
R Gain jg Ja jd 00 172 192 192 192
■ Write EDID DATA to EEPROM(24C02) by using DDC2B
G Gain jh Jb je 00 172 192 192 192 protocol.
B Gain ji Jc jf 00 192 192 172 192 ■ Check whether written EDID data is correct or not.
* For SVC main Ass’y, EDID have to be downloaded to Insert
R Cut 64 64 64 128 Process in advance.
G Cut 64 64 64 128
B Cut 64 64 64 128 4.4. EDID DATA
(1) All Data : HEXA Value
(2) Changeable Data :
* Caution * : Serial No : Controlled / Data:01
- Color Temperature : COOL, Medium, Warm. ** : Month : Controlled / Data:00
- One of R Gain/G Gain/ B Gain should be kept on 0xC0, *** : Year : Controlled
and adjust other two lower than C0. (when R/G/B Gain **** : Check sum
are all C0, it is the FULL Dynamic Range of Module)
* Manual W/B process using adjusts Remote control. 4.5. EDID DATA Auto Download
■ After enter Service Mode by pushing “ADJ” key, (1) Press Adj. key on the Adj. R/C,
■ Enter White Balance by pushing “►” key at “6. White (2) Select EDID D/L menu.
Balance”. (3) By pressing Enter key, EDID download will begin
■ Stick the sensor to the center of the screen and select (4) If Download is successful, OK is display, but If Download is
each items(Red/Green/Blue Gain) using ▲/▼(CH +/-) failure, NG is displayed.
key on R/C. (5) If Download is failure, Re-try downloads.
■ Adjust R/G/B Gain using◄/►(VOL +/-) key on R/C.
■ Adjust three modes all(Cool/Medium/Warm) : Fix the one
of R/G/B Gain and Change the others.
■ When the adjustment is completed, Enter “COPY ALL”.
■ Exit adjustment mode using EXIT key on R/C.
4.6 LNB voltage and 22KHz tone check ■ Edid data and Model option download (RS232 Zender)
(1) Test method NO Enter EDID data and
1) Press "Power on" button of a service R/C.(Baud rate : download MODE Model option download
115200 bps)
Item download ‘Mode In’ download
2) Connect cable between satellite ANT and test JIG.
3) Connect RS232-C Signal Cable. CMD 1 A A
4) Write LNB ON control command through RS-232-C. CMD 2 A E
5) check LED light ‘ON’ at 18V menu.
6) check LED light ‘ON’ at 22KHz tone menu. Data 0 0 00
7) Write LNB OFF control command through RS-232-C. 0 10
8) check LED light ‘OFF’ at 18V menu.
When transfer the Automatically download
9) check LED light ‘OFF’ at 22KHz tone menu.
‘Mode In’, (The use of a internal
Carry the command. Data)
(2) RS-232 command for test LNB
Command Set ACK - Manual Download
LNB On [A][I][ ][Set ID][ ][30][Cr] [O][K][x] or NG : [N][G][x] * Caution
● Use the proper signal cable for EDID Download
LNB Off [A][I][ ][Set ID][ ][40][Cr] [O][K][x] or NG : [N][G][x]
- Digital EDID : Pin3 exists
(3) Test result
- After send LNB On command, ‘18V LED’ and ‘22KHz * Caution
tone LED’ should be ON. - Never connect HDMI & D-sub Cable at the same time.
- After send LNB Off command, ‘18V LED’ and ‘22KHz tone - Use the proper cables below for EDID Writing.
LED’ should be OFF. - Download HDMI1, HDMI2 separately because HDMI1 is dif-
ferent from HDMI2.
4;Y 46Y k}iTzYGG For HDMI EDID
DVI-D to HDMI or HDMI to HDMI
tGi
{
55NK}# 55NK}
Wrqh RQ Wrqh#Rii
ck}iGGGqpnGGe
<Remark>
After the measurement conditions witnessed in the last state.
No. Item Condition Hex Data

1 Manufacturer ID GSM 1E6D
2 Version Digital : 1 01
3 Revision Digital : 3 03
* Caution : Never connect HDMI & D-sub Cable when EDID

downloaded.
Copyright © LG Electronics. Inc. All rights reserved. - 10 - LGE Internal Use Only
* 2D HD EDID data 4.7. GND & Hi-pot test
- 2D HD HDMI1 EDID data ■ GND TEST = P OWER CORD GND and SIGNAL CABLE
GND
■ Hi-pot TEST = POWER CORD GND and LIVE&NUETRAL
■ Test Process
1. Check the POWER CABLE and SIGNAL CABLE
insertion condition.
2. Connect the AV JACK Tester
3. Controller(GWS103-4) on
4. GND TEST(Auto)
- If Test is failed, Buzzer operate
- If Test is passed, execute next process(HI-pot test)
- Remove A/V CORD from A/V JACK BOX
5. HI-POT test(Auto)
- If Test is failed, Buzzer operate
- If Test is passed, GOOD Lamp on and move to next
process automatically.
■ Checkpoint
(1) Test voltage
1) 3 Poles
- GND: 1.5KV/min at 100mA
- SIGNAL: 3KV/min at 100mA
2) 2 Poles
- 2D HD HDMI2 EDID data - SIGNAL: 3KV/min at 100mA
(2) TEST time: 1 second
(3) TEST POINT
1) 3 Poles
- GND Test = P OWER CORD GND and SIGNAL
CABLE GND.
- Hi-pot Test = POWER CORD GND and LIVE &
NEUTRAL.
2) 2 Poles
- Hi-pot Test = Accessible Metal and LIVE & NEUTRAL.
(4) LEAKAGE CURRENT: At 0.5mArms
* Vender ID
Input HEX
HDMI1 10
HDMI2 20
HDMI3 30
* Checksum: Changeable by total EDID data.

EDID C/S data 2D-HD
HDMI
check sum Block 0 0x3E
(Hex) Block 1 0x24(HDMI1)
0x14(HDMI2)
5. Model name & Serial number Download 1) Press the ‘instart’ key of ADJ remote controller.
2) Go to the menu ‘5.Model Number D/L’ like below photo.
5.1. Model name & Serial number D/L 3) Input the Factory model name or Serial number like
■ Press “Power on” key of service remocon.(Baud rate : photo.
115200 bps)
■ Connect RS232 Signal Cable to RS-232 Jack.
■ Write Serial number by use RS-232.
■ Must check the serial number at signal test of customer sup-
port. (Refer to below).
4) Check the model name Instart menu -> Factory name

displayed.
5) Check the Diagnostics (DTV country only) -> Buyer
model displayed
5.2. Signal TABLE

CMD LENGTH ADH ADL DATA_1 ... Data_n CS DELAY
CMD: A0h
LENGTH : 85~94h (1~16 bytes)
ADH : EEPROM Sub Address high (00~1F)
ADL : EEPROM Sub Address low (00~FF)
Data : Write data
CS : CMD + LENGTH + ADH + ADL + Data_1 + … + Data_n
Delay : 20ms
5.3. Command Set

* Description
No. 1
Adjust mode EEPROM WRITE
CMD(hex) A0h 6. Download CI+ Key (EU model only)
* Connect TV SET and PC which download keys Writing pro-
LENGTH(hex) 84h+n gram by RS232C-Cable
Description n-bytes Write (n = 1~16) (1) Start “CIKeyl.exe”Program and Click (3) Button to connect
TV and PC.
FOS Default write : <7mode data> write (2) Click (5) to download CI+ Key.
Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart, (3) When download succeed, you can see “OK” on (6)
0, Phase
Data write : Model Name and Serial Number write in EEP-
ROM,.
5.4. Method & Notice

(1) Serial number D/L is using of scan equipment.
(2) Setting of scan equipment operated by Manufacturing
Technology Group.
(3) Serial number D/L must be conformed when it is produced
in production line, because serial number D/L is mandatory
by D-book 4.0
* Manual Download (Model Name and Serial Number)

If the TV set is downloaded By OTA or Service man,
Sometimes model name or serial number is initialized.( Not
always)
There is impossible to download by bar code scan, so It need

Manual download.
■ Check the method of RS232C Command (3) result value
(1) into the main ass’y mode (RS232 : aa 00 00) - normally status for download : OKx
CMD1 CMD2 Data 0 - abnormally status for download : NGx
A A 0 0
(2) c heck the key download for transmitted command 8. SW Download Guide.
(RS232 : ci 00 10) * Put a *.bin to USB Stick and Turn on TV
CMD1 CMD2 Data 0 (1) Put the USB Stick to the USB socket
C 1 1 0 (2) Automatically detecting update file in USB Stick
* If your downloaded program version in USB Stick is Low,
(3) result value it didn’t work.
- normally status for download : OKx B
ut your downloaded version is High, USB data is auto-
- abnormally status for download : NGx matically detecting.
(3) Show the message “Copying files from memory”
■ Check the method of CI+ Key value (RS232) (4) Updating is staring.
(1) into the main ass’y mode (RS232 : aa 00 00) (5) Updating Completed, The TV will restart automatically.
After turn on TV, Please press ‘IN-STOP’ button on ADJ
CMD1 CMD2 Data 0 Remote-control.
A A 0 0 * IF you don’t have ADJ R/C, enter ‘Factory Reset’ in OP-
TION MENU.
(2) check the mothed of CI+ key by command (6) When TV turn on, check the Updated version on Diagnos-
(RS232 : ci 00 20) tics MENU.
CMD1 CMD2 Data 0

C 1 1 0
(3) result value

i 01 OK 1d1852d21c1ed5dcx
└──> CI+ Key Value
7. Download MAC Address, CI+ Key

and widevine Key.
- Check whether the key was downloaded or not at ‘In Start’
menu. (Refer to below).
-> MAC Address need only DVB-T2 Model (ex.50PA650T-ZA).
* C onnect TV SET and PC which download keys Writing

program by RS232C-Cable
1) Start “MAC+CIKeyl.exe”Program and Click (3) Button to
connect TV and PC.
2) Click (4) to download MAC Address.
3) Click (5) to download CI+ Key.
4) When download succeed, you can see “OK” on (6)
* Each Chassis has it’s own MAC Address. Please be careful

of download.
■ Check the method of RS232C Command

(1) into the main ass’y mode (RS232 : aa 00 00)
CMD1 CMD2 Data 0
A A 0 0
(2) c heck the key download for transmitted command

(RS232 : ci 00 10)
CMD1 CMD2 Data 0
C 1 1 0
BLOCK DIAGRAM
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
570
300
303
601
LV1
304
205
520
305
203
301
580
A12
201
302
A10
200
202
120
204
A21
A2
240
900
400
910
+5V
<Full SCART>
EU
JK100
PSC008-02
+3.3V
R104
10K
L103
120-ohm
EU
PDP L13
23
SHIELD
R105
1K
AV/SC1_DET
AV_DET
R129
0
EU
SC1_SOG_IN C
E
C Q103
B
MMBT3906(NXP)
R144
470
EU
R146
18K
EU
EAX65071305
AV/SC1_CVBS_IN B
AV_DET EU
C
R117 C109 C111 R136
22 Q100 330
COM_GND 75 27pF 220pF E EU B
MMBT3904(NXP)
EU 50V 50V
21 EU
SYNC_IN EU EU C116 DTV/MNT_VOUT
E Q104 10uF
20 SC1_VOUT MMBT3904(NXP) R147 16V
SYNC_OUT EU 10K EU
19 R113 R135 R141 EU
SYNC_GND2 R118 R134 220 R143
75 C102 0 180
18 EU 470K 100uF 100 EU EU
16V 1/4W EU
SYNC_GND1 EU
EU EU
17
RGB_IO
SC1_FB
16 R123
R_OUT R119 33
SC1_R+/COMP1_Pr+ 75
15 EU
RGB_GND EU R106 EU
0 75
14 R122
R_GND SC1_ID
JP112
JP113
JP114
JP115
13 R114 R120
D100
D2B_OUT 10K 2.7K

20V
12 EU EU
G_OUT
SC1_G+/COMP1_Y+
11
D2B_IN R108 AV/SC1_L_IN
75
10 R115 R121 R126
G_GND 10K 12K
470K
9 AV_L_IN
ID
8
B_OUT
SC1_B+/COMP1_Pb+ AV/SC1_R_IN
7 R124
AUDIO_L_IN R107 R116 10K R127
6 75
AV_R_IN
470K
12K
IC101
B_GND AZ4580MTR-E1 P_17V
5
AUDIO_GND
4 OUT1 VCC
AUDIO_L_OUT 1 8
3 C107 R138 C114 R149
AUDIO_R_IN 5600pF 2K C113 27pF 15K
2 50V EU 10uF 50V EU IN1- 2 7 OUT2
AUDIO_R_OUT EU 16V EU
Q101 EU
1 C108
5600pF
50V
MMBT3904(NXP)
EU R137
R145
6.8K
SCART1_Lout
IN1+ 3 6 IN2- JIG_GND
470 EU R154
EU EU
EU 5.6K 5.6K
EU VEE 4 5 IN2+ R153
SCART1_Rout
C115
27pF R148 R152
50V 15K 6.8K
DTV_R_OUT EU EU EU
R139
2K C112
EU 10uF
16V
Q102 EU
MMBT3904(NXP) +3.3V_ST
EU R140
470
READY
EU R189
1K
SCART1_MUTE
<CI SLOT> +5V_CI_ON CI POWER ENABLE CONTROL

+5V +5V_CI_ON
Q114
ZXMP3F30FHTA L100
EU 120-ohm
EU
D
C100 C101
22uF 0.1uF
10V 16V C131 C104 R198
EU EU R184 R187 G 0.1uF 0.1uF 10K
10K 10K 16V 16V READY
READY EU READY EU
+5V
+3.3V_CI
JK102 +3.3V_CI
10067972-000LF
R151
10K R102 EU AR103
EU 100 35
EU 33 EU
/CI_CD1 36 EU PCM_D[3] IC100 EU
R165 C105
37 3 PCM_D[4] 10K TC74LCX244FT 0.1uF
EU C
AR100 33 38 4 PCM_D[5] 16V
CI_TS_DATA[4]
PCM_D[6] R133 B Q113
CI_TS_DATA[5] 39 5 10K
1OE
1
EU 20
VCC
PCM_5V_CTL MMBT3904(NXP)
EU CI_DET R181 EU
40 6 PCM_D[7] 1A1 2OE
BUF1_FE_TS_DATA[0-7] CI_TS_DATA[6] PCM_A[0] 2 19 10K
R130 33 EU EU E
CI_TS_DATA[7] 41 7 /PCM_CE CI_ADDR[7]
2Y4
3 18
1Y1
CI_ADDR[0]
R131 33 EU
BUF1_FE_TS_DATA[0-7]
BUF1_FE_TS_DATA[7] BUF2_FE_TS_DATA[7] 42 8 PCM_A[1]

1A2
4 17
2A4
PCM_A[7]
BUF1_FE_TS_DATA[6] BUF2_FE_TS_DATA[6] R111 43 9 CI_ADDR[10] 2Y3
5 16
1Y2
10K CI_OE CI_ADDR[6] CI_ADDR[1]

BUF1_FE_TS_DATA[5] BUF2_FE_TS_DATA[5] EU 44 10 CI_ADDR[11] 1A3
6 15
2A3
CI_IORD PCM_A[2] PCM_A[6]
BUF1_FE_TS_DATA[4] BUF2_FE_TS_DATA[4] 45 11 CI_ADDR[9] 2Y2
7 14
1Y3
CI_IOWR CI_ADDR[5] CI_ADDR[2]
EU 33 CI_ADDR[8]
AR109 46 12 PCM_A[3]
1A4
8 13
2A2
PCM_A[5]
BUF2_FE_TS_SYN
47 13 CI_ADDR[13] 2Y1
9 12
1Y4
CI_ADDR[4] CI_ADDR[3]
BUF2_FE_TS_DATA[0-7]
BUF1_FE_TS_DATA[3] BUF2_FE_TS_DATA[3] BUF2_FE_TS_DATA[0] CI_ADDR[14]

48 14 GND
10 11
2A1
PCM_A[4]
BUF2_FE_TS_DATA[2] BUF2_FE_TS_DATA[1]
BUF1_FE_TS_DATA[2] 49 15 CI_WE
BUF1_FE_TS_DATA[1] BUF2_FE_TS_DATA[1] BUF2_FE_TS_DATA[2] READY R132 100
50 16 /PCM_IRQA
BUF2_FE_TS_DATA[0] BUF2_FE_TS_DATA[3] R112 EU
BUF1_FE_TS_DATA[0] 51 17
EU 33 0 R128 0 EU
AR108 52 18
AR105 33
53 19 READY CI_OE /PCM_OE
BUF2_FE_TS_DATA[0-7] BUF2_FE_TS_VAL_ERR
BUF2_FE_TS_DATA[4]
AR110 54 20 BUF2_FE_TS_CLK CI_WE /PCM_WE +5V
33 BUF2_FE_TS_DATA[5] IC102
EU R109 55 21 CI_ADDR[12] CI_IORD /PCM_IORD AP2151WG-7
BUF1_FE_TS_SYN BUF2_FE_TS_SYN BUF2_FE_TS_DATA[6] 10K +5V
EU 56 22 CI_ADDR[7] CI_IOWR /PCM_IOWR
BUF1_FE_TS_VAL_ERR BUF2_FE_TS_VAL_ERR BUF2_FE_TS_DATA[7] CI_ADDR[6]
BUF2_FE_TS_DATA[0-7] 57 23
EU IN OUT
BUF1_FE_TS_CLK BUF2_FE_TS_CLK R100 EU 33 58 24 CI_ADDR[5] AR106 33 5 1
PCM_RST CI_ADDR[12] PCM_A[12]
R101 EU 33 59 25 CI_ADDR[4]
/PCM_WAIT CI_ADDR[13] PCM_A[13] READY
CI_ADDR[3] READY
REG 60 26 GND C103
CI_ADDR[14] PCM_A[14] R125 2
R155 EU 100 61 27 CI_ADDR[2] 4.7K 4.7uF
CI_TS_CLK /PCM_REG READY 10V
R156 EU 33 CI_ADDR[1] REG
CI_TS_VAL 62 28
R157 EU 33 EN FLG
63 29 AR104 CI_ADDR[0] 4 3
CI_TS_SYNC 33 EU
R110 EU PCM_D[0] AR107 33
0 64 30
READY CI_ADDR[8] PCM_A[8]
65 31 PCM_D[1]
3.3V_CI CI_TS_DATA[0]
AR102 33 CI_ADDR[9] PCM_A[9]
EU 66 32 PCM_D[2]
CI_ADDR[10] PCM_A[10]
CI_TS_DATA[1] 67 33
+3.3V +3.3V_CI CI_ADDR[0-14] CI_ADDR[11] PCM_A[11]
CI_TS_DATA[2] 68 34
CI_TS_DATA[3]
L101 G2
2 69 G1
1
120-ohm R150
EU 10K
EU R103
+5V 100
EU PCM_D[0-7]
/CI_CD2 PCM_D[0-7]
C136 C137
0.1uF 0.1uF
16V 16V
READY EU
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L13 2012-09-20
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART,CI Slot 1 7
Copyright © 2012 LG Electronics Inc. All rights reserved. LGE Internal Use Only
<HDMI> <IN/OUT>
SWITCH ADDED +3.3V
+3.3V
<COMPONENT> <SIDE USB> IC204
+5V
VA211
BD82020FVJ
JK208 R264
PPJ234-02 10K OUT_3 GND
8 1 R270
VA208
<HDMI1_SIDE> <HDMI2_REAR> [GN]E-LUG +3.3V 10K
VA212
R251 OUT_2
7 2
IN_1 READY
6A 75 JK209 OUT_1 IN_2
[GN]O-SPRING
COMP2_Y+ R259
3AU04S-305-ZC-(LG) C212 C213 R258
6 3
R271
5A 10K R266 0.1uF 10uF 33 OC
5 4
EN 33
AV2_DET 16V 10V USB1_CTL
1
[GN]CONTACT 1K
+5V 5V_DET_HDMI_3 USB1_OCD
USB DOWN STREAM

C201
+5V 5V_DET_HDMI_1 4A
VA210
0.1uF
[BL]E-LUG-S
R252 16V
2
BODY_SHIELD MMBT3904(NXP) R265 SIDE_USB_DM
R237 7B 75 10K
1K
[BL]O-SPRING COMP2_DET
20 C R209 SHIELD MMBT3904(NXP)
10K R200 COMP2_Pb+
3
5B SIDE_USB_DP
B 1K C R202 R267
20
VA209
Q202 HPD3 10K [RD]E-LUG-S 1K
19 R238 R232
1.8K 10K B R253
HPD1 7C 75
4
18 E 19 R201 Q200 R217
R244 [RD]O-SPRING_1
3.3K 1.8K 10K COMP2_Pr+
5
R288 R289 18 R204 E 5C
17 R231
10K 10K 33 3.3K [RD]CONTACT_1
DDC_SDA_3 R281 R282 R207 10mm
16 JP207 17 33
10K 10K 4C
DDC_SCL_3 DDC_SDA_1 R256 10K COMP2_L_IN
15 R246 16 JP201
VA216
33 5D
DDC_SCL_1 [WH]O-SPRING R254 R262
14 JP208 15 R208 470K 12K
33
CEC_REMOTE 14 JP202 4E
13 [RD]CONTACT_2
R257 10K COMP2_R_IN
CK-_HDMI3 CEC_REMOTE
13
<ETHERNET (T2 UK)> <SPDIF>
VA217
12
5E [RD]O-SPRING_2
CK-_HDMI1 R255 R263
11 12 470K 12K
CK+
10 CK+_HDMI3 6E [RD]E-LUG
11 +2.5V
D0- CK+
9 10 CK+_HDMI1
D0-_HDMI3
D0_GND D0- JK210 JK204
8 9 D0-_HDMI1 XRJV-01V-0-D12-080 JST1223-001
D0+ D0_GND
7 8 1 GND
D0+_HDMI3
1
1 +5V
Fiber Optic
D1- D0+ TP
6 7 D0+_HDMI1
D1-_HDMI3
2
D1-
D1_GND
6
<AV (Growth & SCA)> 2 VCC
2
5 D1-_HDMI1
D1+ D1_GND C219
3 0.1uF R285
4 5 3
D1+_HDMI3 TN VINPUT 16V 100
D1+ GROWTH
3
D2- SPDIF_OUT
3 4 D1+_HDMI1 4
D2-_HDMI3
4
JK202 4 RP C220
D2_GND D2-
2 3 PPJ231-01 10pF
D2-_HDMI1 FIX_POLE 50V
5
D2+ D2_GND ET_NET 5
1 2 4 AV_R_IN
D2+_HDMI3
D2+ 6
1 D2+_HDMI1 6
5 RN
AV_L_IN
JK201 R203 7 C200
0 7 0.1uF D200 D204 D205 D206
HDMI1_SIDE 7
AV_DET
16V 5.6V 5.6V 5.6V 5.6V
JK200 GROWTH R234
ET_NET ET_NET ET_NET ET_NET ET_NET
HDMI2_REAR 0 8
8
8
AV/SC1_CVBS_IN
GROWTH 9
R230 R273 R291
6 0 0
75 ET_NET ET_NET
GROWTH 9
For CEC
R280 R290
0 0
ET_NET ET_NET
R268
100
CEC_REMOTE CEC_REMOTE_S7
<FOR COMMERCIAL>
NON_Commercial
+3.3V_ST
P602
12507WS-04L
+3.3V_ST 3
<RS232C> JP241 4 <PHONE JACK> <RGB PC> <WIRED IR>

5
R278 R279
10K 10K
READY
R275
VA203
VA200
0
PM_TXD
READY R283 22 +3.3V_ST
VA204
R274 MAX3232
0 C229
VA205
R284 22 PM_RXD 0.1uF JK205
VA201
JK203 IC206
VA206
16V +5V_ST
SPG09-DB-009 SPG09-DB-010
VA207
MAX3232CDR Commercial
Commercial
VA202
R297 R298
1 10K 10K
VCC MAX3232
C1+
16 1 MAX3232
C228 JK206 RED_GND
6 MAX3232 PEJ027-04 6 JK207
R276 100 0.1uF GND_2 PEJ027-04
GND V+ 16V PHONE JACK 3 E_SPRING R214
2 1 US_Commercial 3 E_SPRING
15 2 11 RED 75
MAX3232 DSUB_R+
Commercial
+5V_ST R277 C225 T_TERMINAL1 GREEN_GND
7 6A T_TERMINAL1
100 DOUT1 C1- 0.1uF Commercial 7 DDC_DATA R215
6A
14 3 16V RGB_DDC_SDA IR
3
MAX3232 B_TERMINAL1
R220
10K
2 12 GREEN 75
7A DSUB_G+ B_TERMINAL1
R228 PC_R_IN BLUE_GND 7A
8 8 R205
VA213
10K RIN1 C2+

Commercial
Commercial
Commercial
Commercial 13 4 MAX3232 R_SPRING R218 R222 H_SYNC 33 R216

4 DSUB_HSYNC R_SPRING
4 C226 470K 12K 3 13 BLUE 75 +3.3V 4 R213
TX 0.1uF DSUB_B+ 0
9 C R229 ROUT1 C2- 16V T_SPRING NC NON_Commercial
12 5 5 9 R206 T_SPRING
100K 33 5
Commercial V_SYNC
Q204 BCommercial R221 4 14 R224 DSUB_VSYNC
Commercial
5 GND_1 C202 C203 R225
MMBT3904(NXP) DIN1 V- 7B B_TERMINAL2 10K 10K
R233 10pF 10pF 1K 7B B_TERMINAL2
10 Commercial 11 6 PC_L_IN SYNC_GND 50V 50V
100K 10 TX
Commercial
E DSUB_DET
VA214
Commercial
Commercial
Commercial T_TERMINAL2 R219 R223 DDC_CLOCK R210

6B RGB_DDC_SCL T_TERMINAL2 10
DIN2 DOUT2 470K 12K 5 15 DDC_GND 6B US_Commercial
10 7 PC_SER_DATA
R212
10
ROUT2 RIN2 PC_SER_CLK
9 8 16 R211
10
MAX3232
C227
0.1uF
(1) NON-OS Normal : O (RS232 Debug) SHILED
NON_Commercial
P603
12507WS-04L
16V
(2) NON-OS Commercial : O (PC Audio) 1
P_JACK TO RS232C
(3) OS Normal : X GND
2
3
RGB_DDC_SDA
R226 RGB_DDC_SCL
0 (4) OS Commercial : O (PC Audio) 4
5
P_JACK TO RS232C
R227
0

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. JACK INTERFACE
2 7
TUNER OPT1 OPT2 OPT3 OPT4
TU301 TDSS-G501D DVB-T/C HNIM X W/O AD
TDSH-G501D China HNIM X W/O AD
TU302
TU303 TDSS-H501F ATSC HNIM X W/O AD
TU304 TDSN-T501F DVB-T_SCA HNIM RF_SW W/O AD

TU305 TDSN_B601F SBTVD FNIM RF_SW With AD
TU306 TDSQ_G605D DVB_T2 FNIM X With AD RF_SWITCH
R310
1K
C307 RF_SWITCH_CTL
0.1uF
16V
RF_SWITCH
Close to Tuner Pin
+3.3V_TU
+3.3V_TU
+1.8V_TU
TU306 TU305 TU304 TU303 TU302 TU301
TDSN-B601F TDSH-T101F TDSS-H501F TDSH-G501D TDSS-G201D
TDSQ-G605D
CO_PANAMA ATSC CHINA
DVB_T2 SBTVD DVB_T/C
R308 R309 R311
NC_1 RF_S/W_CTL RF_S/W_CTL NC NC NC_1 1.5K 1.5K 10K
1 1 1 1 1 1
RESET RESET_TUNER RESET RESET RESET RESET TUNER_RESET
R301100
2 2 2 2 2 2
SCL SCL SCL SCL SCL SCL TU_SCL
3 3 3 3 3 R307 22
3
SDA SDA SDA SDA SDA SDA R306 22 TU_SDA
4 4 4 4 4 4
+B1[3.3V] +B1[3.3V] +B1[3.3V] +B1[3.3V] +B1[3.3V] +B1[3.3V]
5 5 5 5 5 5 C310 C304 C305 C311
C302 C303 0.1uF 68pF 68pF 0.1uF
SIF SIF SIF ALIF_[N] SIF NC_2 0.1uF 10uF 16V 50V 50V
6 6 6 6 6 6 16V
16V 16V
+B2[1.8V] +B2[1.8V] +B2[1.8V] +B2[1.8] +B2[1.8V] +B2[1.8V]
7 7 7 7 7 7
8
CVBS
8
CVBS
8
CVBS
8
ALIF_[P]
8
CVBS
8
NC_3 Close to Tuner Pin
NC_2 NC_1 IF_AGC IF_AGC IF_AGC IF_AGC H_NIM 0 R303
9 9 9 9 9 9 IF_AGC_MAIN
NC_3 NC_2 DIF[P] DIF[P] DIF[P] DIF[P]
10 10 10 10 10 10 IF_P_MSTAR
NC_4 NC_3 DIF[N] DIF[N] DIF[N] DIF[N]
11 11 11 11 11 11 IF_N_MSTAR
NC_5 +B3[3.3V] R336
12 12 B1 A1 B1 A1 B1 A1 B1 A1 16V
0 SBTVD B1 A1 B1 A1 B1 A1 B1 A1
NC_6
13
+B4[1.23V] 0.1uF Close to Tuner Pin
13 C306
TU_GND
R335 0 R320
NC_7 RESET_DEMOD SBTVD 12 12 B2 A2 12 2K
14 14
+5V
B2
A2
GND GND SHIELD SHIELD SHIELD DVB_T/C OPT A-DEMODE OPT
15 15
TU_GND
ERROR ERROR 430 430 R316
TU_GND
16 16 R319 R317
R322 470 TU_SIF
SYNC C308 82
SYNC
TU_GND
17 17 FE_TS_SYN 0.1uF E
VALID 16V
VALID
18 18 FE_TS_VAL_ERR
R312 MMBT3906(NXP)
MCLK MCLK 4.7K B
19 19 FE_TS_CLK Q301
D0 D0 FE_TS_DATA[0] FE_TS_DATA[0-7] C
20 20
R339 0
D1 D1 FE_TS_DATA[1]
21 21 BUF1_FE_TS_DATA[0-7] A_DEMODE
TU_CVBS
D2 D2 FE_TS_DATA[2]
22 22 BUF1_FE_TS_DATA[0]
FE_TS_DATA[0] R323 0 FNIM
D3
23
D3 FE_TS_DATA[3]
FE_TS_DATA[1] R324 0 DVB_T2
BUF1_FE_TS_DATA[1] Close to Tuner Pin
23 BUF1_FE_TS_DATA[2] +3.3V_TU
D4 D4 FE_TS_DATA[4] FE_TS_DATA[2] R326 0 DVB_T2
D5 D5 FE_TS_DATA[5]
25 25
D6 D6 FE_TS_DATA[6]
D7 D7 FE_TS_DATA[7] BUF1_FE_TS_DATA[5] R340 R341
27 27 FE_TS_DATA[5] R328 0 DVB_T2 220 220
BUF1_FE_TS_DATA[6]
+1.25V_TU GND_1 FE_TS_DATA[6] R330 0 DVB_T2 READY READY
28 B1 A1 BUF1_FE_TS_DATA[7]
B1 A1 FE_TS_DATA[7] R329 0 DVB_T2
GND_2 +3.3V_TU
29 28
TU_GND
+B3[1.23V] FE_TS_DATA[0-7]
R305 E
30
SHIELD R304 10K R331 0 FNIM
C314 C315 T2_RESET FNIM FE_TS_SYN BUF1_FE_TS_SYN Q302
100
0.1uF 31 DEMOD_RESET R333 0 FNIM B MMBT3906(NXP)
10uF FE_TS_VAL_ERR BUF1_FE_TS_VAL_ERR
FNIM +B4[3.3V] FNIM R332 0 FNIM READY
FNIM 16V 32 FE_TS_CLK BUF1_FE_TS_CLK C
6.3V
NC_8
33
T2_SCL
34
+3.3V_TU
T2_SDA
35 R313 R314
1.5K TU_GND
1.5K
B1 A1
T2_SCL
0
B1 A1 22
R315
R337
R338
36 TU_GND
22 T2_SDA
R318
SHIELD C316 C317
68pF 68pF
50V 50V
DVB-T2 OPT

Tuner block 3 7
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
TUNER
<GPIO& LVDS> <HDMI& SOUND> <VCC &GND>
<ANALOG & DIGITAL INPUT> IC400
LGE2111C-MS (PDP_13_MS10) IC400 IC400
+1.26V_VDDC
IC400 LGE2111C-MS (PDP_13_MS10) LGE2111C-MS (PDP_13_MS10)
LGE2111C-MS (PDP_13_MS10) MS10
AA22 W24 MS10
RXB4- MS10
MS10 PWM0 PWM0/GPIO66 LVB0M F2 P17 A15
Y22 V23 VDDC_1
R435 RXB4+ D0-_HDMI1 A_RX0N GND_1
68 C414 0.047uF M1 A2
PWM1
V24
PWM1/GPIO67 LVB0P
W23 G1 AUDIO IN R17 A17
COMP2_DET PWM2/GPIO68 LVB1M RXB3- D0+_HDMI1 A_RX0P VDDC_2 GND_2
RIN0M RN RN U23 W25 G2 Y3 C403 2.2uF R18 A20
R436 33 C415 0.047uF M2 B2 D1-_HDMI1 AV/SC1_L_IN VDDC_3 GND_3
DSUB_R+ RIN0P RP RP PWM3/GPIO69 LVB1P RXB3+ A_RX1N AUL1 T17 B14
R437 68 C416 0.047uF L3 B1 T22 Y24 G3 AA2 C404 2.2uF
PWM4/GPIO70 LVB2M RXBCK- D1+_HDMI1 A_RX1P AUR1 AV/SC1_R_IN VDDC_4 GND_4
GIN0M TN TN C7 Y25 H2 AA1 C405 2.2uF T18 B16
R438 33 C417 0.047uF L2 C2 D2-_HDMI1 COMP2_L_IN VDDC_5 GND_5
DSUB_G+ GIN0P TP TP LED_RED PWM_PM/GPIO199 LVB2P RXBCK+ A_RX2N AUL3 U18 B18
R428 68 C418 0.047uF K2 AA24 H3 AA3 C406 2.2uF
LVBCKM RXB2- D2+_HDMI1 A_RX2P AUR3 COMP2_R_IN VDDC_6 GND_6
BIN0M R448 R449 R454 R455 *H/W opt : E7 Y23 F3 W3 C407 2.2uF J9 B21
R429 33 C419 0.047uF K1 A3 49.9 49.9 49.9 49.9 CK-_HDMI1 PC_L_IN VDDC_7 GND_7
DSUB_B+ BIN0P LED0/GPIO55 KEY1 SAR0/GPIO31 LVBCKP RXB2+ A_RXCN AUL4 J11 C11
C420 1000pF K3 C3 ETHERNET D7 AB24
CK+_HDMI1
F1 Y2 C408 2.2uF
PC_R_IN VDDC_8 GND_8
SOGIN0 LED1/GPIO56 KEY2 SAR1/GPIO32 LVB3M RXB1- A_RXCP AUR4 P8 C12
R422 22 J2 J6 AA23 H5
DSUB_HSYNC AV/SC1_DET C450 C454 SAR2/GPIO33 LVB3P RXB1+ DDC_SCL_1 DDCDA_CK/GPIO23 VDDC_9 GND_9
HSYNC0 D1 AB23 H4 R8 C13
R423 22 J3 0.1uF 0.1uF DDC_SDA_1 DDCDA_DA/GPIO24 VDDC_10 GND_10
DSUB_VSYNC VSYNC0 17V_DET SAR3/GPIO34 LVB4M RXB0- U11 C20
C1 AB25 H6 AA9
R420 10K R439 VS_DET SAR4/GPIO35 LVB4P RXB0+ HPD1 HOTPLUGA/GPIO19 EARPHONE_OUTL VDDC_11 GND_11
68 AB9 V10 C23
R421 2.4K C421 0.047uF R3 AE9 VDDC_12 GND_12
RIN1M USB1_DM EARPHONE_OUTR C25
R440 33 C422 R1 AD9 33 R407 A5 AC6
0.047uF SPI_SCK D0-_HDMI3 C_RX0N GND_13
SC1_R+/COMP1_Pr+ RIN1P USB1_DP PM_SPI_SCK/GPIO1 AD7 U17 D23
R441 68 C423 0.047uF R2 B5 AC24 AUDIO OUT
SPI_SDI PM_SPI_SDI/GPIO2 LVA0M RXA4- D0+_HDMI3 C_RX0P AVDDLV GND_14
GIN1M B4 AC25 AC7 AB4 E17
R442 33 C424 0.047uF P3 33 R413 D1-_HDMI3 SCART1_Lout GND_15
SC1_G+/COMP1_Y+ GIN1P SPI_SDO PM_SPI_SDO/GPIO3 LVA0P RXA4+ C_RX1N AUOUTL2 P18 E18
R430 68 C425 0.047uF N3 SIDE_USB_DM 33 R414 C4 AD24 AD8 AB5
/SPI_CS RXA3- D1+_HDMI3 C_RX1P AUOUTR2 SCART1_Rout +1.26V_VDDC DVDD_DDR GND_16
BIN1M PM_SPI_SCZ1/GPIO_PM[6]/GPIO12 LVA1M AE8 E20
R431 33 C426 0.047uF N2 SIDE_USB_DP 22 EU R412 B3 AD25
SC1_B+/COMP1_Pb+ SCART1_MUTE PM_SPI_SCZ2/GPIO_PM[10]/GPIO16 LVA1P RXA3+ D2-_HDMI3 C_RX2N GND_17
BIN1P D3 AC23 AC8 Y8 E23
C427 1000pF P2 D2+_HDMI3 AVDD2P5 AVDD25_LAN GND_18
SC1_SOG_IN SOGIN1 AMP_MUTE PM_SPI_CZ0/GPIO_PM[12]/GPIO0 LVA2M RXACK- C_RX2P AA8 F4
R432 R7 R473 AE24 AE6 Y5
SC1_ID LVA2P RXACK+ CK-_HDMI3 C_RXCN AUVRP AVDD2P5_DADC GND_19
READY R5
HSYNC1
K4 R415 0 22 E2 AD23 AD6 AA4 AB8 F5
0 SC1_FB RGB_DDC_SCL DDCA_CK/UART0_RX LVACKM RXA2- CK+_HDMI3 C_RXCP AUVAG AVDD_MOD GND_20
VSYNC1 HWRESET SOC_RESET D2 AE23 AC5 AA5 F6
R416 22 DDC_SCL_3 10uF GND_21
R443 RGB_DDC_SDA DDCA_DA/UART0_TX LVACKP RXA2+ DDCDC_CK/GPIO27 AUVRM 4.7uF 1uF 0.1uF
68 E5 AD22 AE5 C412 AB1 F7
C428 0.047uF V1 C6 DDC_SDA_3 C409 C410 C411 AVDD25_PGA AVDD25_PGA GND_22
RIN2M IRIN/GPIO4 TX UART_RXD UART1_RX/GPIO44 LVA3M RXA1- DDCDC_DA/GPIO28 AB2 F18
R444 33 C429 V2 E4 AC22 AD5 AVSS_PGA
COMP2_Pr+ 0.047uF UART_TXD RXA1+ HPD3 HOTPLUGC/GPIO21 L408 AVSS_PGA GND_23
RIN2P UART1_TX/GPIO43 LVA3P G4
R445 68 C430 0.047uF U3 U24 AD21 BLM18SG121TN1D
PM_RXD UART2_RX/GPIO64 LVA4M RXA0- GND_24
GIN2M U25 AC21 G5
R446 33 C433 0.047uF U2 AE4 C451 10pF GND_25
COMP2_Y+ GIN2P XIN PM_TXD UART2_TX/GPIO65 LVA4P RXA0+ G6
R433 68 C437 0.047uF T2 AD4 D4 K6 C10
PM_TXD PM_UART_TX/GPIO_PM[1]/GPIO7 HOTPLUGD/GPIO22 I2S_IN_BCK/GPIO150 T2_SCL GND_26
R434 33 C439 0.047uF T1
BIN2M XOUT
GND_2 X-TAL_2 D5 B10 R401 22 DVB_T2 T2_I2C W4 G7
4
I2S_IN_SD/GPIO151 T2_SDA AVDD_NODIE AVDD_NODIE GND_27

R447
COMP2_Pb+ BIN2P PM_RXD PM_UART_RX/GPIO_PM[5]/GPIO11 B9 22 DVB_T2 W5 G10

C443 1000pF T3 R402
1M
X400 I2S_IN_WS/GPIO149 P_SCL AVDD_DMPLL GND_28

SOGIN2 24MHz R404 22 G12
GND_29
X-TAL_1 GND_1
1
AA21 A9 G15
I2C_SCL I2C_SCKM2/DDCR_CK/GPIO72 I2S_OUT_BCK/GPIO156 AUD_SCK GND_30
C452 10pF AB21 N5 B8 W6 G19
A_DEMODE I2S_OUT_MCK/GPIO154 AUD_MASTER_CLK VDD33 AVDD_DVI_USB_MPLL GND_31
A_DEMODE I2C_SDA I2C_SDAM2/DDCR_DA/GPIO71 GPIO36 5V_DET_HDMI_1 A8 Y6 G20
R424 33 C447 0.047uF T5 A6 AVDD_AU33
TU_CVBS GPIO37 DEMOD_RESET I2S_OUT_WS/GPIO155 AUD_LRCK GND_32
CVBS0 M6 C9 AA6 G24
AV/SC1_CVBS_IN
R425 33 C448 0.047uF T4 for SYSTEM EEPROM GPIO38 5V_DET_HDMI_3 I2S_OUT_SD/GPIO157 AUD_LRCH VDDP GND_33
CVBS1 R4 R6 W7 H7
R426 33 C449 0.047uF T6 CEC_REMOTE_S7 AVDD_PLL GND_34
COMP2_Y+ CVBS2 GPIO39 CEC/GPIO5 H10
P5
GND_35
100 R417 M5
GPIO40
D6 I2S_I/F C466 1uF Y4 H12
AC_DET GPIO_PM[0]/GPIO6 GPIO41 AMP_RESET_N DVDD_NODIE GND_36
L409 L7 M4 B6 H13
R427 68 C413 0.047uF U4 R418 100 GND_37
VCOM DISP_EN GPIO_PM[2]/GPIO8 GPIO42 TUNER_RESET P_SDA SPDIF_IN/GPIO152 J14 H14
R411 J4 C8 22 R406 AVDD_MIU AVDD_DDR0_C GND_38
GPIO_PM[4]/GPIO10 GPIO45 PCM_5V_CTL M7 J15 H15
T7 1K RL_ON L5 C5 R419
DTV/MNT_VOUT GPIO_PM[8]/GPIO14 GPIO46 CI_DET SPDIF_OUT SPDIF_OUT/GPIO153 AVDD_DDR0_D_1 GND_39
CVBSOUT2 L6 E6 22 J16 H19
VS_ON EU AVDD_DDR0_D_2 GND_40
GPIO_PM[9]/GPIO15 GPIO49 AMP_SCL K16 H25
/FLASH_WP L4 E3
GPIO_PM[11]/GPIO17 GPIO50 AMP_SDA AVDD_DDR0_D_3 GND_41
5V_ON K5 J1
GPIO51 MODEL_OPT_1 GND_42
B7 J17 J7
GPIO52 RF_SWITCH_CTL AVDD_DDR1_C GND_43
K7 L16 J12
GPIO53 AV2_DET AVDD_DDR1_D_1 GND_44
J5 L17 J13
GPIO54 DSUB_DET AVDD_DDR1_D_2 GND_45
M16 J19
AVDD_DDR1_D_3 GND_46
J20
GND_47
J24
GND_48
J8 K12
GND_EFUSE GND_49
K8 K13
<PCM & CI> R19
TEST GND_50
GND_51
K14
K15
#POWER FOR MAIN# IC400

R23
T23
GND_91
GND_92
GND_52
GND_53
K18
K19
LGE2111C-MS (PDP_13_MS10) U5
GND_93 GND_54
K25
PCM_D[0-7] GND_94 GND_55
Internal demod out U6 L8
<VDDC 1.05V> <Normal Power 3.3V> PCM_D[0-7]
PCM_D[0]
MS10
BUF1_FE_TS_DATA[0]
V3
GND_95
GND_96
GND_56
GND_57
L12
+1.26V_VDDC +1.26V_VDDC AB17 Y14 V4 L13
PCMDATA0/GPIO126 TS1DATA0/GPIO88 BUF1_FE_TS_DATA[0-7] GND_97 GND_58
VDDC : 2026mA +3.3V VDD33 DECAP FOR SOC PCM_D[1] AB19 AA14 BUF1_FE_TS_DATA[1] V11 L14
DECAP FOR SOC (HIDDEN - UCC) PCMDATA1/GPIO127 TS1DATA1/GPIO89 GND_98 GND_59
(HIDDEN - UCC) PCM_D[2] BUF1_FE_TS_DATA[2]
Y16 AD13 V15
READY
L15
PCM_D[3] PCMDATA2/GPIO128 TS1DATA2/GPIO90 BUF1_FE_TS_DATA[3] GND_99 GND_60
READY READY READY L401 AD15 Y13 V16 L18
0.1uF
0.1uF
0.1uF
BLM18PG121SN1D
0.1uF
0.1uF
AE15 AA13 V17 L19

0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF
10uF
10uF

0.1uF
4V
0.1uF
0.1uF
1uF
1uF
AD14 AD12 V18

4V
L20
0.1uF
0.1uF
0.1uF
0.1uF
4V
0.1uF

4V
10uF
C435 10uF
4V
4V
AB15 AC12 V19 L24

PCMDATA6/GPIO117 TS1DATA6/GPIO94 GND_103 GND_64
C455
C457
C465
PCM_D[7] BUF1_FE_TS_DATA[7]
C4000
C474
C478
C480
AC16 W10 V20 M3

C4005
C4006
C492
PCM_A[0-14]
C472
C467
C482
C484
C487
C490
C493
PCMDATA7/GPIO116 TS1DATA7/GPIO95 GND_104 GND_65

C491
AB13 V21 M8
C4002
C434
TS1CLK/GPIO98 BUF1_FE_TS_CLK GND_105 GND_66

C438
C440
C441
PCM_A[0]
C431
Y17 AC14 W1 M12

PCM_A[1] PCMADR0/GPIO125 TS1VALID/GPI96 BUF1_FE_TS_VAL_ERR GND_106 GND_67
AA16 W13 W2 M13
PCM_A[2] PCMADR1/GPIO124 TS1SYNC/GPIO97 BUF1_FE_TS_SYN GND_107 GND_68
C4000,C4005,C4006 IS CAP FOR REPAIR AB16 W11 M14
SHOULD BE BOTTOM SIDE PCM_A[3] PCMADR2/GPIO122 GND_108 GND_69
C4002 SHOULD NEAR MAIN IC AD16 W15 M15
PCM_A[4] PCMADR3/GPIO121 CI_TS_DATA[0-7] GND_109 GND_70
Y18 AB12 CI_TS_DATA[0] W17 M17
PCM_A[5] PCMADR4/GPIO99 TS0DATA0/GPIO77 GND_110 GND_71
AE20 AD11 CI_TS_DATA[1] W18 M18
PCM_A[6] PCMADR5/GPIO101 TS0DATA1/GPIO78 CI_TS_DATA[2] GND_111 GND_72
Y19 W9 W20 M19
<DDR3 1.5V> <Normal 2.5V> <STby 3.3V> PCM_A[7]

PCM_A[8]
AC20
AB18
PCMADR6/GPIO102
PCMADR7/GPIO103
TS0DATA2/GPIO79
TS0DATA3/GPIO80
AE11 CI_TS_DATA[3]
AB11 CI_TS_DATA[4]
W21
W22
GND_112
GND_113
GND_73
GND_74
M24
N1
AD17 AE12 CI_TS_DATA[5] Y7 N7
AC15 AC13 CI_TS_DATA[6] AA7 N13
+2.5V AVDD2P5 PCM_A[11] PCMADR10/GPIO114 TS0DATA6/GPIO83 GND_116 GND_77
AE17 AB14 CI_TS_DATA[7] AB6 N14
C4001 IS CAP FOR REPAIR PCMADR11/GPIO112 TS0DATA7/GPIO84 GND_117 GND_78
PCM_A[12] AA19 AA11 AB7 N15
AVDD2P5:172mA SHOULD BE BOTTOM SIDE
L405 PCM_A[13] PCMADR12/GPIO104 TS0CLK/GPIO87 CI_TS_CLK GND_118 GND_79
+1.5V_DDR AVDD_DDR0:55mA BLM18PG121SN1D AA18 Y11 N16
+5V PCM_A[14] PCMADR13/GPIO107 TS0VALID/GPIO85 CI_TS_VAL GND_80
AVDD_MIU AC19 AC11 N17
READY PCMADR14/GPIO106 TS0SYNC/GPIO86 CI_TS_SYNC GND_81
C489 C4001 AVDD_NODIE:7.362mA EU N18
L402 DECAP READY FOR TEST DECAP FOR SOC C485 R458 C458 GND_82
AVDD25_PGA 0.1uF 0.1uF AA17 N19
EU
(HIDDEN - UCC) 0.1uF AVDD_NODIE 10K 2pF
BLM18PG121SN1D 4V 4V
+3.3V_ST
PCM_RST
AD20
PCM_RESET/GPIO129 from CI SLOT GND_83
N20
50V
/PCM_IRQA PCMIRQA_N/GPIO105 GND_84
L406 L400 AC18 N25
READY BLM18PG121SN1D BLM18PG121SN1D /PCM_IOWR PCMIOWR_N/GPIO109 100pF GND_85
C4003
C4004
0.1uF
0.1uF
AE14 P13
C436
10uF
C442
C444
C445
C446
C453 DECAP FOR SOC (HIDDEN - UCC) C463

0.1uF
1uF
/PCM_OE PCMOE_N/GPIO113 GND_86

C432
0.1uF AD18 READY P14

0.1uF
0.1uF
0.1uF
C401
4V 0.1uF
/PCM_IORD
AC17
PCMIORD_N/GPIO111 Close to MSTAR 100pF GND_87
P19
C477 /PCM_CE PCMCE_N/GPIO115 C462 C464 DTV_IF
R466 100 0.1uF READY GND_88
0.1uF AD19 P21
L407 /PCM_WE PCMWE_N/GPIO197 IF_P_MSTAR GND_89
BLM18SG121TN1D R457 22 AE21 AC3 H_NIM C461 H_NIM P24
C453 IS CAP FOR REPAIR AVSS_PGA R460 /CI_CD1 PCMCD_N/GPIO130 IP R465 100 0.1uF GND_90
AVDD_DDR1:55mA
SHOULD BE BOTTOM SIDE 10K C456EU AE18 AD2 IF_N_MSTAR
/PCM_REG PCMREG_N/GPIO123 IM H_NIM H_NIM
Close to IC with width trace 0.1uF W16
EU /PCM_WAIT 16V PCMWAIT_N/GPIO100
EU A_DEMODE A_DEMODE
Y21 C459 0.1uF R467 47
PCM2_CD_N/GPIO135 TU_SIF
/CI_CD2 Y20 C460 0.1uF R468 47
R456 22 EU PCM2_RESET/GPIO134
AA20 AD1
USB1_OCD PCM2_CE_N/GPIO131 SIFP A_DEMODE A_DEMODE
AB22 AD3 ANALOG SIF
USB1_CTL PCM2_IRQA_N/GPIO132 SIFM
AB20 Close to MSTAR
+3.3V
<HW_OPT> <SOC_RESET> AR400
22 OS
AD10
PCM2_WAIT_N/GPIO133
IF_AGC
AC2
+3.3V
B51_no_EJ : 4’b0000 Boot from 8051 with SPI flash NF_ALE/GPIO141
+3.3V Y9
SB51_WOS : 4’b0001 Secure B51 without scramble /PF_WP NF_WPZ/GPIO198
SB51_WS : 4’b0010 Secure B51 with scramble AA10 AB3
/PF_CE0 NF_CEZ/GPIO137 GPIO73
BLM18PG121SN1D
MIPS_SPE_NO_EJ : 4’b0100 Boot from MIPS with SPI flash Y10 AC4
1K
MIPS_SPI_EJ_1 : 4’b0101 Boot from MIPS with SPI flash +3.3V_ST /PF_CE1 NF_CLE/GPIO136 GPIO74
AB10 AE3
H_NIM
MIPS_SPI_EJ_2 : 4’b0110 Boot from MIPS with SPI flash /PF_OE NF_REZ/GPIO139 I2C_SCKM1/GPIO75 TU_SCL
L410
AC9 AE2
OS
MIPS_WOS : 4’b1001 Secure MIPS without scramble

1K
/PF_WE NF_WEZ/GPIO140 I2C_SDAM1/GPIO76 TU_SDA

1K
MIPS_WS : 4’b1010 Scerur MIPS with SCRAMBLE AC10

R462
PF_ALE NF_RBZ/GPIO142 TUNER_I2C

READY
FHD
/F_RB
LED_RED AR401
0.1uF
OS
R409
H_NIM
R475
22 NON_A_DEMODE
C468
AUD_SCK MODEL_OPT_1 C497 AGC 1.25V
10uF R408 +3.3V
AUD_MASTER_CLK RF_SWITCH_CTL MODEL OPTION 10V 10 100 OHM SERIAL
SOC_RESET
A_DEMODE 0ohm
1K
1K
PWM1 D400
PIN NAME PIN NO. LOW HIGH BAW56 GEANDE H_NIM
PWM0 C402 R469
HD
R403 10K
MODEL_OPT_0
1K
1K
1K
1K
1K
AB3 FHD HD 100K 0.1uF

H_NIM
NON_OS
R405
R410
MODEL_OPT_1 R464 R474 R450 R451 R471 100

F4 2.2K 2.2K 2.2K 2.2K R452 R453 IF_AGC_MAIN
2.2K 2.2K
R461
R463
R459
R470
R472
C469
I2C_SDA 0.047uF
I2C_SCL 25V
H_NIM
P_SDA
<CHIP Config> P_SCL
(I2S_OUT_BCK,I2S_OUT_MCK,PAD_PWM1PAD_PWM0)
UART_RXD Close to MSTAR
<CHIP Config(LED_R/BUZZ)> UART_TXD
Boot from SPI CS1N(EXT_FLASH) 1’b0
Boot from SPI_CS0N(INT_FLASH) 1’b1

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN 4 7
NAND Flash IC504
Key/IR LVDS 1GBit H27U1G8F2CTR-BC
+3.3V_ST +5V
+5V +3.3V
Commercial P501
12507WR-06L NC_1 NC_29
R515 1 48
4.7K
R512
4.7K
R513
4.7K
+3.3V
R577
4.7K
R518 NC_2 NC_28
100 2 47
IR 1
NC_3 NC_27
3 46 PCM_A[0-7]
+3.3V_ST C517 OS
D502
20V
10pF NC_4 NC_26 AR518

50V 2 4 45
22
A1
A2
R540 R542 NC_5 I/O7 PCM_A[7]
10K 10K R517 LD500 OS OS 5 44
100
KEY1 3 D500 R565 R568 NC_6 I/O6 PCM_A[6]
MMBD6100 C 1K 4.7K 6 43
C
B
R516 R/B I/O5 PCM_A[5]
100 2K /F_RB 7 42
KEY2 4
R579 E Q500
RE I/O4
MMBT3904(NXP) 8 41 PCM_A[4]
20V
20V
@optio /PF_OE
P500 CE NC_25
C535 C534 5 47K 9 40
R578 /PF_CE0
0.1uF 0.1uF 104060-8017
D504
D503
16V 16V P503 NC_7 NC_24

TF05-51S 10 39
C554 OS
6 OS NC_8 NC_23 10uF10V
1 1 11 38
C550
R514 2 2 0.1uF VCC_1 VCC_2
22 7 12 37
LED_RED
3
3 R519 0
UART_RXD VSS_1 VSS_2 OS C555
4
4 R520 0 13 36 0.1uF
C520 UART_TXD
D505
5
20V
10pF 5 NC_9 NC_22

50V 6 14 35
6
7 NC_10 NC_21
7 15 34
8 OS
8 CLE NC_20 AR519
9 16 33
/PF_CE1 22
10 9
+3.3V_ST ALE I/O3 PCM_A[3]
11 10 PF_ALE 17 32 IC504-*1
RXA0- TC58NVG0S3ETA0BBBH
12 11 WE I/O2 PCM_A[2] Toshiba_OS
RXA0+ 18 31 NC_1
1 48
NC_29
D501
/PF_WE
20V
NC_2 NC_28
C547 13
12
2 47
0.1uF RXA1- WP I/O1

NC_3
3 46
NC_27
16V 14 19 30 PCM_A[1] NC_4

4 45
NC_26
RXA1+ 13 /PF_WP NC_5
NC_6
5 44
I/O8
I/O7
6 43
15
14 NC_11 I/O0 PCM_A[0]
RY/BY
7 42
I/O6
16 20 29 RE
8 41
I/O5
RXA2- 15
CE
9 40
NC_25
17 R556 OS R567 NC_12 NC_19 NC_7

10 39
NC_24
RXA2+ 16 OS 3.3K 1K 21 28 NC_8
VCC_1
11 38
NC_23
VCC_2
12 37
18 VSS_1 VSS_2
17 NC_13 NC_18 NC_9

13
14
36
35
NC_22
19 22 27
RXACK- NC_10
15 34
NC_21
20 18 CLE
16 33
NC_20
RXACK+ NC_14 NC_17 ALE

17 32
I/O4
21 19 23 26 WE
18 31
I/O3
RXA3- WP
19 30
I/O2
22 20 NC_15 NC_16 NC_11

20 29
I/O1
RXA3+ 24 25 NC_12
NC_13
21 28
NC_19
NC_18
22 27
23
RXA4- 21 NC_14
23 26
NC_17
NC_15 NC_16
24 25
24
RXA4+ 22
25
23
26
HD
24
27
RXB0- 25
28
RXB0+ 26
29
RXB1-
30 27
RXB1+
31 28
32
RXB2- 29 SERIAL FLASH
33
RXB2+ 30
34
31
35
RXBCK- 32
36
RXBCK+ 33
37
RXB3- +3.3V_ST +3.3V_ST Winbond_OS +3.3V_ST
38
34
RXB3+ 35 IC505
39
RXB4-
36
W25Q80BVSSIG
40
RXB4+ R564 R569
41 37 10K 4.7K
READY C556
42 38 CS VCC 0.1uF
/SPI_CS 1 8
43
39
44
40 RXA0-
45
DO[IO1] HOLD[IO3]
41 SPI_SDO 2 7
46
RXA0+
47
FHD 42 RXA1-
43 %WP[IO2] CLK
48 RXA1+ 3 6
/FLASH_WP SPI_SCK
44
49 OS:8MB
45 R575
50 RXA2- GND DI[IO0] 33
51 46 IC505-*1 4 5 SPI_SDI
RXA2+
NON OS 52 47
48
MX25L8006EM2I-12G
MX_OS
CS# VCC
READY RXACK-
1 8
IC506 49 RXACK+
SO/SIO1
2 7
HOLD#
+3.3V_ST MX25L6406EMI-12G 50 RXA3- WP# SCLK

3 6
51 RXA3+ GND SI/SIO0
READY 52
4 5
RXA4-
R580 HOLD# SCLK 53
1 16 SPI_SCK RXA4+
10K 54
READY R581
0.1uF VCC SI/SIO0 55
33
2 15 SPI_SDI 56 RXB0-
READY
57 NON_OS:64MB
C557 RXB0+
NC_1 NC_8 58
3 14 RXB1- IC505-*2 IC505-*3
59 RXB1+ W25Q64FVSSIG MX25L6406EM2I-12G
NC_2 NC_7 60 Winbond_NON-OS

CS VCC
MX_NON-OS
CS VCC
1 8 1 8
4 13 61 RXB2- DO[IO1] %HOLD[IO3] SO/SIO1 HOLD
2 7 2 7
62 RXB2+
NC_3 NC_6 63 WP[IO2]
3 6
CLK WP
3 6
SCLK
5 12
64 RXBCK- GND
4 5
DI[IO0] GND
4 5
SI/SIO0
NC_4 NC_5 65 RXBCK+

6 11 66 RXB3-
67 RXB3+
CS# GND 68
/SPI_CS 7 10 RXB4-
69 RXB4+
SO/SIO1 WP# 70
SPI_SDO 8 9 71
/FLASH_WP
72
73
74
75 P_SDA NVRAM
76 DISP_EN
77
78
P_SCL OS:256KB
PC_SER_DATA
79 PC_SER_CLK IC503-*1 IC503-*2
AT24C256C-SSHL-T(Cu)
80 M24256-BRMN6TP +3.3V
C518 C519 ATMEL_OS
A0
1 8
VCC ST_OS
E0 VCC
1 8
470pF 470pF
81
READY READY A1
2 7
WP
E1
2 7
WC
A2 SCL
3 6 E2 SCL
3 6
C552
GND
4 5
SDA
VSS SDA
0.1uF
4 5
IC503
M24512-RMN6TP
READY
E0 VCC
R521 1 8
0
P_SDA PC_SER_DATA NON_OS:512KB E1 WC
2 7
P_SCL PC_SER_CLK IC503-*3
0 AT24C512C-SSHD-T
ST_NON_OS R573
R522 E2 SCL 22
3 6 I2C_SCL
READY ATMEL_NON-OS
A0
1 8
VCC
R574
A1 WP VSS SDA 22
2 7 4 5 I2C_SDA
A2 SCL
3 6
GND SDA
4 5
* LCI: LVDS Connection Indicator

Memory.LVDS,IR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 5 7
POWER & AMP <ST-BY>
<Power Wafer> 1.26V Core +5V_ST --> 3.3Vst 5V_STBY --> MULTI 5V
+5V
+5V_ST
+3.3V_ST
+5V_ST +5V
Q604
P600 ZXMP3F30FHTA L604
3A 120
SMAW200-H18S1 P_17V
D
C613 C620 C621
R624
READY
10uF 10uF 0.1uF

15K
25V 25V 50V
READY
READY IC603 R667 R670 R671
5%
1/16W
1 2 +5V_ST R607 +5V_ST +3.3V_ST R657 R664 G 0.1uF 0.1uF 10K
+3.3V_ST L600 10K TPS54327DDAR [EP]GND 300mA 10K 10K 16V 16V READY
3 4 READY READY
120 IC600
5 6 AP2121N-3.3TRE1
7 8 VS_DET C608 C610 EN VIN
R609 10uF 0.1uF RL_ON 1 8 +1.26V_VDDC VIN 3 VOUT
9 10 C606 10V 16V 2 READY
100 R648
READY
THERMAL
0.1uF R617 100 C602
R601 R600 11 12 16V VS_ON 33K R1 1
10K 10K 1% VFB VBST C600 C601 C604 C634 2.2uF
9
13 14 2 7 10uF 0.1uF 1uF 10uF 10V
17V_DET 10V 16V GND 6.3V 6.3V
RL_ON 15 16 AC_DET C628
C623 0.1uF L605
17 18 C607 C633 100pF VREG5 SW 25V 2.2uH C
5V_ON 0.1uF 1000pF 50V 3 6
R606
4.7K
16V
10K
4.7K
R639
50V B Q603
R604
3A C650 C629 C630 C609 C603 RL_ON MMBT3904(NXP)

19 R2 SS GND 10uF 10uF 0.1uF 10uF 10uF R659
R619 4 5 16V 16V 16V 16V 16V 10K
51K E
1%
C624 C626
1uF 3300pF
10V 50V
Vout=0.765*(1+R1/R2)
<MUTI>
+5V->+3.3V_DDR --> +1.5V_DDR +5V->+2.5V +5V->+3.3V +5V->+1.8V_TU +5V->+1.25V_TU

->+3.3V_TU 80mA 400mA
+5V +1.25V_TU
600mA +5V R2 IC602
+5V IC604
+3.3V_DDR 400mA IC608 AZ1117BH-ADJTRE1
AP1117EG-13
FNIM
IC613
R614 R613
600mA R2 +5V 200mA +2.5V AP1117E33G-13
220 100
5%
+5V AZ1117BH-ADJTRE1 +1.8V_TU
IC605 +3.3V_DDR IC601 +3.3V +3.3V_TU IN OUT
R674 R673
AP1117E33G-13 +1.5V_DDR TJ1118S-2.5

200
INPUT ADJ/GND
1%
IN ADJ/GND ADJ/GND
5%
INPUT ADJ/GND IN OUT OUTPUT
3 2 OUT L606 R620
IN ADJ/GND OUTPUT 120-ohm C615 R1 1
1%
R1 R2
1K
1 C616 2A 10uF C614 FNIM

OUT C618 R612 10uF 10V 10uF
10uF R1 1 10V 10V R618 C625
R615
FNIM
C611 6.3V C605 GND R621 FNIM 240 10uF
10uF 10uF R662 1 FNIM 6.3V
D600
READY
10V R675 10V C612 1 FNIM
1
5V
1 10uF
R608 6.3V C631
1 C617 10uF
C619 10uF 6.3V
10uF 6.3V
C627 6.3V
10uF
6.3V Vout=1.25*(1+R2/R1)
Vout=1.25*(1+R2/R1)
<AUDIO AMP> L609

10.0uH
Coil_GET
L611
NC_12
NC_11
NC_10
10.0uH
NC_9
NC_8
NC_7
NC_6
NC_5
NC_4
NC_3
NC_2
NC_1
+3.3V_AMP SPK_L+
Coil_TAIYO C691 C696
+3.3V +3.3V_AMP 0.22uF 1000pF
R632 R636 L602 C688 50V 50V
24
23
22
21
20
19
18
17
16
15
14
13
39 39 10.0uH
0.22uF
L601 12 GND_REG C678 SPEAKER_L
0.1uF Coil_GET 50V
BLM18PG121SN1D NC_13 25 C684 C692 C697
11 VDD_REG 16V L612
C672 26 330pF 10.0uH 0.22uF 1000pF
NC_14 10 OUT1A
0.1uF 50V 50V 50V
NC_15 27 SPK_L-
16V 9 GND1
Coil_TAIYO
VDDDIG1 28 P601
8 VCC1
29 L603 WAFER-ANGLE
GNDDIG1 7 OUT1B 10.0uH
FFX3A 30 IC606 6 OUT2A
31 Coil_GET
FFX3B STA380BWF 5 VCC2 L614
EAPD/FFX4A 32 10.0uH SPK_L+
C673 4 GND2 4
2.2uF TWARNEXT/FFX4B 33 SPK_R+
3 OUT2B C685 C693 C698
10V 34 49 Coil_TAIYO
VREGFILT THERMAL 2 VSS_REG 330pF 0.22uF 1000pF
C679 SPK_L-
AGNDPLL 35 50V C689 50V 50V 3
1 VCC_REG 0.1uF
36 50V 0.22uF SPEAKER_R
MCLK R633 R637 Coil_TAIYO
37
38
39
40
41
42
43
44
45
46
47
48
39 39 50V
AR600 L615 C694 C699 SPK_R+
2
0.22uF 1000pF
SDI
RESET
PWDN
INTLINE
SDA
SCL
SA
TESTMODE
GNDDIG2
VDDDIG2
[EP]
BICKI
LRCKI
100 10.0uH
50V 50V
SPK_R-
AUD_MASTER_CLK SPK_R-
1
+3.3V_AMP L610 P_17V
AUD_SCK 10.0uH
AUD_LRCK
Coil_GET
AUD_LRCH
L616
READY
C632 CIS21J121
2pF
50V C677
0.1uF
16V
R611 C680 C681 C686 C687 C690 C695
33 0.1uF 1uF 1uF 0.1uF 0.1uF 68uF
AMP_MUTE 50V 50V 50V 50V 50V 35V
+3.3V_AMP
+3.3V_AMP
R628
4.7K
AMP_RESET_N
R641
C622 R640
0.1uF 4.7K
4.7K
R652
22
AMP_SDA R653
22
AMP_SCL
READY READY
C674 C675
33pF 33pF
50V 50V

THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Power,AMP 6 7
AVDD_DDR0 AVDD_DDR0 AVDD_DDR0 AVDD_DDR0
+1.5V_DDR AVDD_DDR0
R1227
R1201
R1224
R1204
1K 1%
1K 1%
OS
OS
1K 1%
1K 1%
L1202
CIC21J501NE
A-MVREFDQ B-MVREFCA B-MVREFDQ
0.1uF
A-MVREFCA
OS 1000pF
0.1uF
1000pF
0.1uF
OS 1000pF
0.1uF
1000pF
1%
1%
1%
1%
C1250
R1228
C1218
C1219
C1238
C1241
R1202
R1225
R1205
10uF
C1247
C1248
C1249
C1251
OS
OS
C1202
C1201
C1204
1K
C1203
1uF
1uF
1uF
1uF
1K
1K
OS
OS
1K
CLose to DDR3
CLose to DDR3 CLose to Saturn7M IC CLose to Saturn7M IC CLose to DDR3
EAN61836301 IC400 EAN61836301

IC1201 LGE2111C-MS (PDP_13_MS10) IC1202
K4B1G1646G-BCK0 K4B1G1646G-BCK0
IC1201-*1
H5TQ1G63EFR-PBC
SS_1G_1600 MS10F9 E22 OS_SS_1G_1600
N3 M8
P7
A0
A1
VREFCA
A_MA0 A_DDR3_A0 B_DDR3_A0 B_MA0
M8 N3 P3
N2
A2
H1 E10 G21 N3 M8 IC1202-*1
H5TQ1G63EFR-PBC
A-MVREFCA VREFCA A0 A-MA0 P8
P2
A3
A4
VREFDQ
A_MA1 A_DDR3_A1 B_DDR3_A1 B_MA1 B-MA0 A0 VREFCA B-MVREFCA
P7 R8
A5
A6 ZQ
L8 G9 F20 P7 N3 M8
A1 A-MA1 R2
T8
A7 A_MA2 A_DDR3_A2 B_DDR3_A2 B_MA2 B-MA1 A1 P7
A0
A1
VREFCA
P3 R3
L7
A8
A9 VDD_1
B2
D9
C14 E24 P3 P3
N2
A2
H1
A2 A-MA2 R7
A10/AP
A11
VDD_2
VDD_3
G7 A_MA3 A_DDR3_A3 B_DDR3_A3 B_MA3 B-MA2 A2 P8
P2
A3
A4
VREFDQ
H1 N2 N7
T3
A12/BC VDD_4
K2
K8 F11 K20 N2 H1 R8
A5
A6 ZQ
L8
A-MVREFDQ VREFDQ A3 A-MA3 M7

NC_7 VDD_5
VDD_6
N1
N9
A_MA4 A_DDR3_A4 B_DDR3_A4 B_MA4 B-MA3 A3 VREFDQ B-MVREFDQ R2
T8
A7
P8 NC_5 VDD_7
VDD_8
R1 A14 F24 P8 R3
L7
A8
A9 VDD_1
B2
D9
A4 A-MA4 M2
N8
BA0 VDD_9
R9
A_MA5 A_DDR3_A5 B_DDR3_A5 B_MA5 B-MA4 A4 R7
A10/AP
A11
VDD_2
VDD_3
G7
P2 M3
BA1
BA2
A1
F10 J21 P2 OS N7
T3
A12/BC VDD_4
K2
K8
R1203 A5 A-MA5 J7
CK
VDDQ_1
VDDQ_2
A8 A_MA6 A_DDR3_A6 B_DDR3_A6 B_MA6 B-MA5 A5 R1226 M7
NC_7 VDD_5
VDD_6
N1
N9
L8 R8 K7
K9
CK VDDQ_3
C1
C9 C15 F23 R8 L8 NC_5 VDD_7
VDD_8
R1
ZQ A6 A-MA6 L2
CKE VDDQ_4
VDDQ_5
D2
E9
A_MA7 A_DDR3_A7 B_DDR3_A7 B_MA7 B-MA6 A6 ZQ M2
N8
BA0 VDD_9
R9
240 R2 K1
CS
ODT
VDDQ_6
VDDQ_7
F1 D11 H22 R2 240
M3
BA1
BA2
A1
A7 A-MA7 J3
K3
RAS VDDQ_8
H2
H9 A_MA8 A_DDR3_A8 B_DDR3_A8 B_MA8 B-MA7 A7 J7
CK
VDDQ_1
VDDQ_2
A8
AVDD_DDR0 1% T8 L3
CAS
WE
VDDQ_9
J1
C16 G23 T8 1% AVDD_DDR0 K7
K9
CK VDDQ_3
C1
C9
A8 A-MA8 T2
RESET
NC_1
NC_2
J9 A_MA9 A_DDR3_A9 B_DDR3_A9 B_MA9 B-MA8 A8 L2
CKE VDDQ_4
VDDQ_5
D2
E9
B2 R3 NC_3
L1
L9 G13 L21 R3 B2 K1
CS
ODT
VDDQ_6
VDDQ_7
F1
VDD_1 A9 A-MA9 F3
DQSL
NC_4
NC_6
T7
A_MA10 A_DDR3_A10 B_DDR3_A10 B_MA10 B-MA9 A9 VDD_1 J3
K3
RAS VDDQ_8
H2
H9
OS C1227 10uF
G3
C1205 10uF D9 L7 DQSL

E11 G22 L7 D9 L3
CAS
WE
VDDQ_9
J1
VDD_2 A10/AP A-MA10 C7

B7
DQSU VSS_1
A9
B3 A_MA11 A_DDR3_A11 B_DDR3_A11 B_MA11 B-MA10 A10/AP VDD_2 T2
NC_1
J9
OS C1228 0.1uF RESET NC_2
C1207 0.1uF G7 R7 E7
DQSU VSS_2
VSS_3
E1
G8
F12 J22 R7 G7 NC_3
L1
L9
VDD_3 A11 A-MA11 D3

DML VSS_4
J2 A_MA12 A_DDR3_A12 B_DDR3_A12 B_MA12 B-MA11 A11 VDD_3 F3
DQSL
NC_4
NC_6
T7
OS C1229 0.1uF
DMU VSS_5 G3
C1208 0.1uF K2 N7 E3
VSS_6
J8
M1 B15 G25 N7 K2 DQSL
VDD_4 A12/BC A-MA12 F7

DQL0
DQL1
VSS_7
VSS_8
M9
A_MA13 A_DDR3_A13 B_DDR3_A13 B_MA13 B-MA12 A12/BC VDD_4 C7
B7
DQSU VSS_1
A9
B3
OS C1230 0.1uF
F2 P1
C1210 0.1uF K8 T3 F8
DQL2
DQL3
VSS_9
VSS_10
P9 D10 H20 T3 K8 E7
DQSU VSS_2
VSS_3
E1
G8
VDD_5 A13 A-MA13 H3

H8
DQL4 VSS_11
T1
T9 A_MA14 A_DDR3_A14 B_DDR3_A14 B_MA14 B-MA13 A13 VDD_5 D3
DML VSS_4
J2
OS C1231 0.1uF DMU VSS_5
C1211 0.1uF N1 G2
H7
DQL5
DQL6
VSS_12
B23 P23 N1 E3
VSS_6
J8
M1
VDD_6 DQL7
B1 A-MDQL0 A_DDR3_DQL0 B_DDR3_DQL0 B-MDQL0 VDD_6 F7
DQL0
DQL1
VSS_7
VSS_8
M9
OS C1232 0.1uF
VSSQ_1 F2 P1
C1212 0.1uF N9 M7 D7
C3
DQU0 VSSQ_2
B9
D1 B19 L25 M7 N9 F8
DQL2
DQL3
VSS_9
VSS_10
P9
VDD_7 NC_5 C8
DQU1
DQU2
VSSQ_3
VSSQ_4
D8
A-MDQL1 A_DDR3_DQL1 B_DDR3_DQL1 B-MDQL1 NC_5 VDD_7 H3
H8
DQL4 VSS_11
T1
T9
OS C1233 0.1uF
C2 E2
C1213 0.1uF R1 A7
DQU3
DQU4
VSSQ_5
VSSQ_6
E8 A23 R24 R1 G2
H7
DQL5
DQL6
VSS_12
VDD_8 A2
B8
DQU5 VSSQ_7
F9
G1 A-MDQL2 A_DDR3_DQL2 B_DDR3_DQL2 B-MDQL2 VDD_8 DQL7
B1
OS C1234 0.1uF VSSQ_1
C1214 0.1uF R9 M2 A3
DQU6
DQU7
VSSQ_8
VSSQ_9
G9
C19 K23 M2 R9 D7
C3
DQU0 VSSQ_2
B9
D1
VDD_9 BA0 A-MBA0 A-MCK A-MDQL3 A_DDR3_DQL3 B_DDR3_DQL3 B-MDQL3 B-MBA0 BA0 VDD_9 C8
DQU1 VSSQ_3
D8
R1235
DQU2 VSSQ_4
OS C1235 0.1uF C2 E2
C1215 0.1uF N8 B24 T25 B-MCK N8 A7

DQU3
DQU4
VSSQ_5
VSSQ_6
E8
A-MBA1 A-MDQL4 B-MDQL4 B-MBA1

1%
A2 F9
BA1 A_DDR3_DQL4 B_DDR3_DQL4 BA1
OS
DQU5 VSSQ_7
B8 G1
M3 C18 J23 M3 OS C1236 0.1uF
56
R1237
DQU6 VSSQ_8
A3 G9
56
C1216 0.1uF A-MBA2 A-MDQL5 B-MDQL5 B-MBA2

DQU7 VSSQ_9
BA2 A_DDR3_DQL5 B_DDR3_DQL5 BA2
1%
A1 C1209 A24 T24 OS C1240 A1
VDDQ_1 A-MDQL6 A_DDR3_DQL6 B_DDR3_DQL6 B-MDQL6 VDDQ_1
R1236
A8 J7 A18 K24 J7 A8
0.01uF A-MDQL7 B-MDQL7
1%
VDDQ_2 CK A_DDR3_DQL7 B_DDR3_DQL7 0.01uF CK VDDQ_2

C1 K7 50V D15 N21 K7 C1
56
R1238
56
A-MDQU0 B-MDQU0 50V

VDDQ_3 CK A_DDR3_DQU0 B_DDR3_DQU0 CK VDDQ_3
1%
OS
C9 K9 F17 P22 K9 C9
VDDQ_4 CKE A-MCKE A-MDQU1 A_DDR3_DQU1 B_DDR3_DQU1 B-MDQU1 B-MCKE CKE VDDQ_4
D2 F14 L22 B-MCKB D2
VDDQ_5 A-MCKB A-MDQU2 A_DDR3_DQU2 B_DDR3_DQU2 B-MDQU2 VDDQ_5
E9 L2 E16 R21 L2 E9
VDDQ_6 CS A-MDQU3 A_DDR3_DQU3 B_DDR3_DQU3 B-MDQU3 CS VDDQ_6
F1 K1 D14 P20 K1 F1
VDDQ_7 ODT A-MODT A-MDQU4 A_DDR3_DQU4 B_DDR3_DQU4 B-MDQU4 B-MODT ODT VDDQ_7
H2 J3 D16 R22 J3 H2
VDDQ_8 RAS A-MRASB AVDD_DDR0 A-MDQU5 A_DDR3_DQU5 B_DDR3_DQU5 B-MDQU5 AVDD_DDR0 B-MRASB RAS VDDQ_8
H9 K3 E14 M22 K3 H9
VDDQ_9 CAS A-MCASB R1231 A-MDQU6 A_DDR3_DQU6 B_DDR3_DQU6 B-MDQU6 B-MCASB CAS VDDQ_9
L3 F16 N22 L3
WE A-MWEB 10K A-MDQU7 A_DDR3_DQU7 B_DDR3_DQU7 B-MDQU7 R1232 B-MWEB WE
J1 A12 D24 10K J1
NC_1 A_MCASB A_DDR3_CASZ B_DDR3_CASZ B_MCASB NC_1
J9 T2 B11 B25 T2 J9
NC_2 RESET A-MRESETB A_MRASB A_DDR3_RASZ B_DDR3_RASZ B_MRASB OS B-MRESETB RESET NC_2
L1 E9 F22 L1
NC_3 A_MWEB A_DDR3_WEZ B_DDR3_WEZ B_MWEB NC_3
L9 B20 L23 L9
NC_4 A-MDML A_DDR3_DQML B_DDR3_DQML B-MDML NC_4
T7 F3 D17 R20 F3 T7
A-MA14 NC_6 DQSL A-MDQSL A-MDMU A_DDR3_DQMU B_DDR3_DQMU B-MDMU B-MDQSL DQSL NC_6 B-MA14
G3 A11 C24 G3
DQSL A-MDQSLB A_MODT A_DDR3_ODT B_DDR3_ODT B_MODT B-MDQSLB DQSL
B12 D25
A_MBA0 A_DDR3_BA0 B_DDR3_BA0 B_MBA0
A9 C7 G11 K22 C7 A9
VSS_1 DQSU A-MDQSU A_MBA1 A_DDR3_BA1 B_DDR3_BA1 B_MBA1 B-MDQSU DQSU VSS_1
B3 B7 B13 E25 B7 B3
VSS_2 DQSU A-MDQSUB A_MBA2 A_DDR3_BA2 B_DDR3_BA2 B_MBA2 B-MDQSUB DQSU VSS_2
E1 G8 E21 E1
VSS_3 A_MRESETB A_DDR3_RESET B_DDR3_RESET B_MRESETB VSS_3
G8 E7 F13 M20 E7 G8
VSS_4 DML A-MDML A_MCKE A_DDR3_MCLKE B_DDR3_MCLKE B_MCKE B-MDML DML VSS_4
J2 D3 B17 H23 D3 J2
VSS_5 DMU A-MDMU A-MCK A_DDR3_MCLK B_DDR3_MCLK B-MCK B-MDMU DMU VSS_5
J8 C17 H24 J8
VSS_6 A-MCKB A_DDR3_MCLKZ B_DDR3_MCLKZ B-MCKB VSS_6
M1 E3 B22 P25 E3 M1
VSS_7 DQL0 A-MDQL0 A-MDQSL A_DDR3_DQSL B_DDR3_DQSL B-MDQSL B-MDQL0 DQL0 VSS_7
M9 F7 C22 N23 F7 M9
VSS_8 DQL1 A-MDQL1 A-MDQSLB A_DDR3_DQSBL B_DDR3_DQSBL B-MDQSLB B-MDQL1 DQL1 VSS_8
P1 F2 A21 N24 F2 P1
VSS_9 DQL2 A-MDQL2 A-MDQSU A_DDR3_DQSU B_DDR3_DQSU B-MDQSU B-MDQL2 DQL2 VSS_9
P9 F8 C21 M23 F8 P9
VSS_10 DQL3 A-MDQL3 A-MDQSUB A_DDR3_DQSBU B_DDR3_DQSBU B-MDQSUB B-MDQL3 DQL3 VSS_10
T1 H3 H3 T1
VSS_11 DQL4 A-MDQL4 B-MDQL4 DQL4 VSS_11
T9 H8 H8 T9
VSS_12 DQL5 A-MDQL5 B-MDQL5 DQL5 VSS_12
G2 G2
DQL6 A-MDQL6 B-MDQL6 DQL6
H7 H7
DQL7 A-MDQL7 B-MDQL7 DQL7
B1 B1
VSSQ_1 VSSQ_1
B9 D7 D7 B9
VSSQ_2 DQU0 A-MDQU0 B-MDQU0 DQU0 VSSQ_2
D1 C3 C3 D1
D8 C8 C8 D8
E2 C2 C2 E2
E8 A7 A7 E8
F9 A2 A2 F9
G1 B8 B8 G1
G9 A3 A3 G9
<NONE MS10>
NONE_MS10
IC400-*1 IC400-*1
AR1224 56 AR1217 56 AR1211 56 AR1206 56 IC400-*1
LGE2111C (PDP_13_None MS10)
IC400-*1
LGE2111C (PDP_13_None MS10) LGE2111C (PDP_13_None MS10)
IC400-*1
IC400-*1
F2 P17 A15
F9 E22 AB17 Y14 A_RX0N AA22 W24 VDDC_1 GND_1
A_DDR3_A0 B_DDR3_A0 PCMDATA0/GPIO126 TS1DATA0/GPIO88 G1 PWM0/GPIO66 LVB0M M1 A2 R17 A17
E10 G21 AB19 AA14 A_RX0P Y22 V23 RIN0M RN VDDC_2 GND_2
A_DDR3_A1 B_DDR3_A1 PCMDATA1/GPIO127 TS1DATA1/GPIO89 G2 Y3 PWM1/GPIO67 LVB0P M2 B2 R18 A20
G9 F20 Y16 AD13 A_RX1N AUL1 V24 W23 RIN0P RP VDDC_3 GND_3
A_DDR3_A2 B_DDR3_A2 PCMDATA2/GPIO128 TS1DATA2/GPIO90 G3 AA2 PWM2/GPIO68 LVB1M L3 B1 T17 B14
A-MA12 A_MA12 A-MA13 A_MA13 B-MA12 B_MA12 B-MA13 B_MA13 C14
F11
A_DDR3_A3 B_DDR3_A3
E24
K20
AD15
AE15
PCMDATA3/GPIO120 TS1DATA3/GPIO91
Y13
AA13
H2
A_RX1P
A_RX2N
AUR1
AUL3
AA1
U23
T22
PWM3/GPIO69 LVB1P
W25
Y24
L2
K2
GIN0M
GIN0P
TN
TP
C2 T18
VDDC_4
VDDC_5
GND_4
GND_5
B16
OS OS A14
A_DDR3_A4
A_DDR3_A5
B_DDR3_A4
B_DDR3_A5
F24 AD14
PCMDATA4/GPIO119
PCMDATA5/GPIO118
TS1DATA4/GPIO92
TS1DATA5/GPIO93
AD12
H3
F3
A_RX2P AUR3
AA3
W3
C7
PWM4/GPIO70
PWM_PM/GPIO199
LVB2M
LVB2P
Y25
K1
BIN0M
A3
U18
J9
VDDC_6 GND_6
B18
B21
A-MBA1 A_MBA1 A-MA9 A_MA9 B-MBA1 B_MBA1 B-MA9 B_MA9 F10

C15
A_DDR3_A6
A_DDR3_A7
B_DDR3_A6
B_DDR3_A7
J21
F23
AB15
AC16
PCMDATA6/GPIO117
PCMDATA7/GPIO116
TS1DATA6/GPIO94
TS1DATA7/GPIO95
AC12
W10
F1
H5
A_RXCN
A_RXCP
AUL4
AUR4
Y2
E7
SAR0/GPIO31
LVBCKM
LVBCKP
AA24
Y23
K3
J2
BIN0P
SOGIN0
HSYNC0
LED0/GPIO55
LED1/GPIO56
C3 J11
P8
VDDC_7
VDDC_8
GND_7
GND_8
C11
C12
D11 H22 AB13 DDCDA_CK/GPIO23 D7 AB24 VDDC_9 GND_9
A_DDR3_A8 B_DDR3_A8 TS1CLK/GPIO98 H4 SAR1/GPIO32 LVB3M J3 R8 C13
C16 G23 Y17 AC14 DDCDA_DA/GPIO24 J6 AA23 VSYNC0 VDDC_10 GND_10
A_DDR3_A9 B_DDR3_A9 PCMADR0/GPIO125 TS1VALID/GPI96 H6 AA9 SAR2/GPIO33 LVB3P U11 C20
G13 L21 AA16 W13 HOTPLUGA/GPIO19 EARPHONE_OUTL D1 AB23 VDDC_11 GND_11
A_DDR3_A10 B_DDR3_A10 PCMADR1/GPIO124 TS1SYNC/GPIO97 AB9 SAR3/GPIO34 LVB4M R3 AE9 V10 C23
E11 G22 AB16 EARPHONE_OUTR C1 AB25 RIN1M USB1_DM VDDC_12 GND_12
A_DDR3_A11 B_DDR3_A11 PCMADR2/GPIO122 AC6 SAR4/GPIO35 LVB4P R1 AD9 C25
F12 J22 AD16 C_RX0N RIN1P USB1_DP GND_13
A_DDR3_A12 B_DDR3_A12 PCMADR3/GPIO121 AD7 R2 U17 D23
B15 G25 Y18 AB12 C_RX0P A5 GIN1M AVDDLV GND_14
P3
AR1223 56 AR1216 56 AR1207 56 AR1210 56 D10
B23
A_DDR3_A13
A_DDR3_A14
B_DDR3_A13
B_DDR3_A14
H20
P23
AE20
Y19
PCMADR4/GPIO99
PCMADR5/GPIO101
TS0DATA0/GPIO77
TS0DATA1/GPIO78
AD11
W9
AC7
AD8
C_RX1N
C_RX1P
AUOUTL2
AUOUTR2
AB4
AB5
B5
B4
PM_SPI_SCK/GPIO1
PM_SPI_SDI/GPIO2 LVA0M
AC24
AC25
N3
N2
GIN1P
BIN1M
P18
DVDD_DDR
GND_15
GND_16
E17
E18
A_DDR3_DQL0 B_DDR3_DQL0 PCMADR6/GPIO102 TS0DATA2/GPIO79 AE8 PM_SPI_SDO/GPIO3 LVA0P E20
B19 L25 AC20 AE11 C_RX2N C4 AD24 BIN1P GND_17
A_DDR3_DQL1 B_DDR3_DQL1 PCMADR7/GPIO103 TS0DATA3/GPIO80 AC8 PM_SPI_SCZ1/GPIO_PM[6]/GPIO12 LVA1M P2 Y8 E23
A23 R24 AB18 AB11 C_RX2P B3 AD25 SOGIN1 AVDD25_LAN GND_18
A_DDR3_DQL2 B_DDR3_DQL2 PCMADR8/GPIO108 TS0DATA4/GPIO81 AE6 Y5 PM_SPI_SCZ2/GPIO_PM[10]/GPIO16 LVA1P R7 AA8 F4
C19 K23 AD17 AE12 C_RXCN AUVRP D3 AC23 HSYNC1 AVDD2P5_DADC GND_19
A_DDR3_DQL3 B_DDR3_DQL3 PCMADR9/GPIO110 TS0DATA5/GPIO82 AD6 AA4 PM_SPI_CZ0/GPIO_PM[12]/GPIO0 LVA2M R5 K4 AB8 F5
B24 T25 AC15 AC13 C_RXCP AUVAG AE24 VSYNC1 HWRESET AVDD_MOD GND_20
A_DDR3_DQL4 B_DDR3_DQL4 PCMADR10/GPIO114 TS0DATA6/GPIO83 AC5 AA5 LVA2P F6
C18 J23 AE17 AB14 DDCDC_CK/GPIO27 AUVRM E2 AD23 GND_21
A_DDR3_DQL5 B_DDR3_DQL5 PCMADR11/GPIO112 TS0DATA7/GPIO84 AE5 DDCA_CK/UART0_RX LVACKM V1 C6 AB1 F7
A-MA10 A_MA10 A-MA0 A_MA0 B-MA10 B_MA10 B-MA0 B_MA0 A24

A18
A_DDR3_DQL6
A_DDR3_DQL7
B_DDR3_DQL6
B_DDR3_DQL7
T24
K24
AA19
AA18
PCMADR12/GPIO104
PCMADR13/GPIO107
TS0CLK/GPIO87
TS0VALID/GPIO85
AA11
Y11
AD5
DDCDC_DA/GPIO28
HOTPLUGC/GPIO21
D2
E5
DDCA_DA/UART0_TX
UART1_RX/GPIO44
LVACKP
LVA3M
AE23
AD22
V2
U3
RIN2M
RIN2P
IRIN/GPIO4
AB2
AVDD25_PGA
AVSS_PGA
GND_22
GND_23
F18
G4
OS OS D15
F17
A_DDR3_DQU0 B_DDR3_DQU0
N21
P22
AC19
PCMADR14/GPIO106 TS0SYNC/GPIO86
AC11 E4
U24
UART1_TX/GPIO43 LVA3P
AC22
AD21
U2
GIN2M
GIN2P XIN
AE4 GND_24
GND_25
G5
A-MCKE A_MCKE A-MWEB A_MWEB B-MCKE B_MCKE B-MWEB B_MWEB F14

E16
A_DDR3_DQU1
A_DDR3_DQU2
B_DDR3_DQU1
B_DDR3_DQU2
L22
R21
AA17
AD20
PCM_RESET/GPIO129
K6
HOTPLUGD/GPIO22 I2S_IN_BCK/GPIO150
I2S_IN_SD/GPIO151
C10
B10
U25
D4
UART2_RX/GPIO64
UART2_TX/GPIO65
LVA4M
LVA4P
AC21
T2
T1
BIN2M
BIN2P
XOUT
AD4
W4
AVDD_NODIE
GND_26
GND_27
G6
G7
A_DDR3_DQU3 B_DDR3_DQU3 PCMIRQA_N/GPIO105 B9 PM_UART_TX/GPIO_PM[1]/GPIO7 T3 W5 G10
D14 P20 AC18 I2S_IN_WS/GPIO149 D5 SOGIN2 AVDD_DMPLL GND_28
A_DDR3_DQU4 B_DDR3_DQU4 PCMIOWR_N/GPIO109 PM_UART_RX/GPIO_PM[5]/GPIO11 G12
D16 R22 AE14 GND_29
A_DDR3_DQU5 B_DDR3_DQU5 PCMOE_N/GPIO113 A9 G15
E14 M22 AD18 I2S_OUT_BCK/GPIO156 GND_30
A_DDR3_DQU6 B_DDR3_DQU6 PCMIORD_N/GPIO111 B8 W6 G19
F16 N22 AC17 I2S_OUT_MCK/GPIO154 AA21 AVDD_DVI_USB_MPLL GND_31
A_DDR3_DQU7 B_DDR3_DQU7 PCMCE_N/GPIO115 A8 I2C_SCKM2/DDCR_CK/GPIO72 T5 Y6 G20
A12 D24 AD19 I2S_OUT_WS/GPIO155 AB21 N5 CVBS0 AVDD_AU33 GND_32
A_DDR3_CASZ B_DDR3_CASZ PCMWE_N/GPIO197 C9 I2C_SDAM2/DDCR_DA/GPIO71 GPIO36 T4 AA6 G24
AR1222 56 AR1214 56 AR1203 56 AR1205 56 B11
E9
A_DDR3_RASZ
A_DDR3_WEZ
B_DDR3_RASZ
B_DDR3_WEZ
B25
F22
AE21
AE18
PCMCD_N/GPIO130
PCMREG_N/GPIO123
IP
IM
AC3
AD2
R6
CEC/GPIO5
I2S_OUT_SD/GPIO157
GPIO37
GPIO38
A6
M6
T6
CVBS1
CVBS2
W7
VDDP
AVDD_PLL
GND_33
GND_34
H7
H10
B20 L23 W16 R4 GND_35
OS D17
A11
A_DDR3_DQML
A_DDR3_DQMU
A_DDR3_ODT
B_DDR3_DQML
B_DDR3_DQMU
B_DDR3_ODT
R20
C24 Y21
PCMWAIT_N/GPIO100
PCM2_CD_N/GPIO135
B6
SPDIF_IN/GPIO152 M5
GPIO_PM[0]/GPIO6
GPIO39
GPIO40
GPIO41
P5
D6
U4
VCOM
Y4
J14
DVDD_NODIE GND_36
GND_37
H12
H13
H14
B12 D25 Y20 L7 M4 AVDD_DDR0_C GND_38
A_DDR3_BA0 B_DDR3_BA0 PCM2_RESET/GPIO134 M7 GPIO_PM[2]/GPIO8 GPIO42 T7 J15 H15
G11 K22 AA20 AD1 SPDIF_OUT/GPIO153 J4 C8 CVBSOUT2 AVDD_DDR0_D_1 GND_39
A_DDR3_BA1 B_DDR3_BA1 PCM2_CE_N/GPIO131 SIFP GPIO_PM[4]/GPIO10 GPIO45 J16 H19
B13 E25 AB22 AD3 L5 C5 AVDD_DDR0_D_2 GND_40
A-MA6 A_MA6 A-MA5 A_MA5 B-MA6 B_MA6 B-MA5 B_MA5 G8
F13
A_DDR3_BA2
A_DDR3_RESET
B_DDR3_BA2
B_DDR3_RESET
E21
M20
AB20
PCM2_IRQA_N/GPIO132
PCM2_WAIT_N/GPIO133
SIFM
AC2
L6
L4
GPIO_PM[8]/GPIO14
GPIO_PM[9]/GPIO15
GPIO46
GPIO49
E6
E3
K16
AVDD_DDR0_D_3 GND_41
GND_42
H25
J1
OS B17
A_DDR3_MCLKE
A_DDR3_MCLK
B_DDR3_MCLKE
B_DDR3_MCLK
H23 AD10
NF_ALE/GPIO141
IF_AGC GPIO_PM[11]/GPIO17 GPIO50
GPIO51
K5
J17
L16
AVDD_DDR1_C GND_43
J7
J12
A-MA4 A_MA4 A-MA7 A_MA7 B-MA4 B_MA4 B-MA7 B_MA7 C17
B22
A_DDR3_MCLKZ
A_DDR3_DQSL
B_DDR3_MCLKZ
B_DDR3_DQSL
H24
P25
Y9
AA10
NF_WPZ/GPIO198
NF_CEZ/GPIO137 GPIO73
AB3
GPIO52
GPIO53
B7
K7
L17
M16
AVDD_DDR1_D_1
AVDD_DDR1_D_2
GND_44
GND_45
J13
J19
C22 N23 Y10 AC4 J5 AVDD_DDR1_D_3 GND_46
A_DDR3_DQSBL B_DDR3_DQSBL NF_CLE/GPIO136 GPIO74 GPIO54 J20
A21 N24 AB10 AE3 GND_47
A_DDR3_DQSU B_DDR3_DQSU NF_REZ/GPIO139 I2C_SCKM1/GPIO75 J24
C21 M23 AC9 AE2 GND_48
A_DDR3_DQSBU B_DDR3_DQSBU NF_WEZ/GPIO140 I2C_SDAM1/GPIO76 J8 K12
AC10 GND_EFUSE GND_49
NF_RBZ/GPIO142 K8 K13
TEST GND_50
K14
AR1221 56 AR1218 56 AR1212 56 AR1209 56 R19

R23
GND_91
GND_92
GND_51
GND_52
GND_53
K15
K18
T23 K19
GND_93 GND_54
U5 K25
GND_94 GND_55
U6 L8
GND_95 GND_56
V3 L12
GND_96 GND_57
V4 L13
GND_97 GND_58
V11 L14
A-MA11 A_MA11 A-MRESETB A_MRESETB B-MA11 B_MA11 B-MRESETB B_MRESETB V15
GND_98
GND_99
GND_59
GND_60
L15
OS OS V16
V17
GND_100 GND_61
L18
L19
A-MA8 A_MA8 A-MA2 A_MA2 B-MA8 B_MA8 B-MA2 B_MA2 V18

V19
GND_101
GND_102
GND_62
GND_63
L20
L24
GND_103 GND_64
V20 M3
GND_104 GND_65
V21 M8
GND_105 GND_66
W1 M12
GND_106 GND_67
W2 M13
GND_107 GND_68
W11 M14
GND_108 GND_69
AR1220 56 AR1213 56 AR1202 56 AR1225 56 W15
W17
GND_109
GND_110
GND_70
GND_71
M15
M17
W18 M18
GND_111 GND_72
W20 M19
GND_112 GND_73
W21 M24
GND_113 GND_74
W22 N1
GND_114 GND_75
Y7 N7
GND_115 GND_76
AA7 N13
A-MRASB A_MRASB A-MCASB A_MCASB B-MRASB B_MRASB B-MCASB B_MCASB AB6

AB7
GND_116
GND_117
GND_77
GND_78
N14
N15
OS OS GND_118 GND_79
GND_80
N16
A-MODT A_MODT A-MBA0 A_MBA0 B-MODT B_MODT B-MBA0 B_MBA0 GND_81

GND_82
N17
N18
N19
GND_83
N20
GND_84
N25
GND_85
P13
GND_86
P14
GND_87
P19
GND_88
P21
GND_89
AR1219 56 AR1215 56 AR1204 56 AR1208 56 GND_90
P24
A-MA1 A_MA1 A-MBA2 A_MBA2 B-MA1 B_MA1 B-MBA2 B_MBA2

OS OS
A-MA14 A_MA14 A-MA3 A_MA3 B-MA14 B_MA14 B-MA3 B_MA3

FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS GP4L_S7LR2 2011/06/03
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. DDR_256 12
L13 T
Training
i i Manual
M l
Table of contents
1. L13 Concept(’12 Vs. ’13)

2. L13 Power On/Off sequence
3. L13 Power Block
4. L13 I2C MAP
5. L13 Front End
1. L13 Concept(’12 Vs. ’13)
42PA4500/50PA4500 42PN4500/50PN4500
50PA6500/60PA6500 50PN6500/60PN6500
3 3
1 1
141.5mm
141.5mm
S7LR3 S7LR3
5
4
2 4 2
4 42PN4500/50PN4500
50PN6500/60PN6500
5
206mm 206mm
1 Main processor, DDR, NAND Jack ERRC
2 Tuner 1) RGB ,RS-232C and PC-Audio is removed
2) Comp./Comp. Hybrid Æ Comp. Hybrid (EU: 1ea)
3 LVDS Wafer 3) HDMI 1 Jack is removed
4 HDMI Block 4) Non-EU use Video(AV Jack) intead of SCART Jack
5 Tact Key+LED+EYE+IR
Copyright © 2012 LG Electronics Inc. All rights reserved. 1/11 LGE Internal Use Only
2. Power On/Off sequence (AC)
Signal Spec.(min) Measure Graph Remark
RL_On 40ms 0
M_On 80ms 700ms
VS_On 250ms 260ms
VS_DET -
VS_On 0 40ms
RL_On 200ms 335ms
M_On 30ms 56ms
2. Power On/Off sequence (DC)
RL_On
M_On 80ms 87ms
VS_On 250ms 280ms
VS_DET
M_On 2500ms 3000ms

RL_On 30ms 56ms
2. Screen On/Off sequence
VS_On 250ms 247ms

VS_DET 400ms -
M_On 2530ms 2600ms
3. Power Block.
Spec) 850mV↓
20mVrms
356mVpp
17 17 07V
17.07V OP-Amp
OP Amp
V for SC
Spec) 850mV↓
12mVrms
116mVpp
L616
120 Ohm 17.07V Audio
5A C680 C690 C695 C686 C681 AMP
2012 0.1uF 0.1uF 68uF 1uF 1uF
50V 50V 35V 50V 50V
1608 1608 8PI/6.3H
3. Power Block. Spec) 165mV↓
73.58Vrms
Input Input
418mVpp
STBY DTV Comp
p HDMI DTV p
Comp HDMI +3.3V_ST _
AVDD_NODIE
8.3mA 1.07A 1.12A 1.14A Spec) 250mV↓ 33mA 33mA 33mA
50Vrms
L600 244mVpp IC600 L400
5.07V 5V to 3.3V 3.29V 3.29V
120 Ohm
AP2121N-3.3
120 Ohm LM1
5A C608 C600 (0.3A) C604 2A
5.10V 5.08V C610 C601 C401
2012 10uF 10uF 1uF 1608
0.1uF 0.1uF 0.1uF
10V 16V 10V 16V 6.3V
Spec) 250mV↓
69Vrms
245mVpp
RS232C
Spec) 165mV↓ C229
73.58Vrms 0.1uF
164mVpp 16V
1005
3.29V Serial Flash
C556
+5 0.1uF
16V
V_
1005
ST Input
Spec) 65mV↓ 3.29V SUB Ass’y
17Vrms C547
DTV Comp HDMI 60mVpp
Spec) 250mV↓ 0.1uF Input
230mA 220mA 220mA
68Vrms STBY
Spec) 250mV↓ +1.10V_Vddc
_ 16V
248mVpp Spec) 250mV↓ 0 2mA
0.2mA
27Vrms 1005
88Vrms
169mVpp5.02V 5.03V 5.08V
L604 249mVpp
Q604 IC603 1.26V
120 Ohm MOFET 5.07V 5V to 1.23V
ZXMP3F30 TPS54231D LM1
2A (3.0A) C620 C621 (2A) X3 x7 X2
C601 1608 10uF 0.1uF 10uF 0.1uF 1uF
0.1uF Input 25V 50V 10V 16V 10V
Input
16V DTV Comp HDMI 2012 1005 1005
DTV Comp HDMI
910mA 900mA 850mA
750mA 630mA 650mA
+5V
3. Power Block.
Input
Spec) 250mV↓ Spec) 125mV↓
16Vrms +2.5V
+2 5V DTV Comp HDMI
27Vrms
102mA 102mA 102mA
169mVpp 99mVpp Spec) 125mV↓
L405 16Vrms
IC601
5.00V 2.486V 120 Ohm 2.476V 99mVpp
5V to 2.5V
TJ3940S-2.5V 2A
C605 (714mW) C612 C485 AVDD2P5
1608
10uF 10uF 0.1uF
10V Input 6.3V 16V LM1
DTV Comp HDMI 1608 전류안흐름?? 1005
102mA 102mA 102mA Spec) 125mV↓
L406 16Vrms
120 Ohm 2.478V 99mVpp
2A
C477 AVDD25_PGA
1608
Spec) 250mV↓ 0.1uF
27Vrms Spec) 90mV↓+1.8V_TU 16V
169mVpp 5.6Vrms 1005
IC604 89mVpp
+5 5 00V
5.00V 5V to 1
1.8V
8V
AP1117BH-ADJ Tuner
V C615 (850mW) C631 1.81V C311
10uF 10uF 0.1uF
Input
10V 6.3V 16V
DTV Comp HDMI
1608 1005
150mA 164mA 164mA
+1.25V_TU
5.00V IC602 1.245V T2/SBTV

5V to 1.25V
C614 AP1117EG-13 C625 C315 C314 Tuner
(850mW)
10uF 10uF 0.1uF 10uF
10V 6.3V 16V 6.3V
1608 1005 1608
3. Power Block.
Spec) 250mV↓ Spec) 165mV↓ Spec) 165mV↓

26Vrms 5Vrms +3.3V
+3.3V_TU 5Vrms
169mVpp 69mVpp 69mVpp
IC608 L606
5.02V 5.0V to 3.3V 3.26V 3.255V
AP1117E33G 120 Ohm Tuner
(850mW) 2A
C616 C617 Input C302 C303
10 F
10uF 1608 DTV ATV Comp HDMI 01 F
0.1uF 10 F
10uF
0.1uF
168mA 194mA 197mA 197mA
10V 6.3V 16V 16V
1005
+3.3V_AMP
Spec) 165mV↓
L601 8Vrms
89mVpp
3 275V 120 Ohm
3.275V 3 273V
3.273V Audio
2A
C677 C672
AMP
1608 Input(STA380 not working)
DTV Comp HDMI 0.1uF 0.1uF
30mA 30mA 30mA 16V 16V
Spec) 165mV↓
+5 7Vrms Spec) 75mV↓
79mVpp 7.5Vrms +1.5V_DDR Spec) 75mV↓
V 74mVpp 10Vrms
L1202
IC605 IC613 74mVpp
5.01V 5.0V to 3.3V
3.27V 3.26V 1.507V 500 Ohm 1.50V
3.3V to 1.5V
AP1117E33G AP1117BH-ADJ 3A
DDR
(850mW) C618 (850mW) C619 C1251 X4
C611 C627 10uF 2012(?) 10uF 1uF
10uF
0.1uF 10uF 6.3V 6.3V Input
10V 6.3V DTV Comp HDMI
Input
140mA 85mA 85mA
DTV Comp HDMI
285mA 185mA 185mA
Spec) 75mV↓
L402 9.8Vrms
1.50V 74mVpp
120 Ohm
LM1
2A
C432 1608 C436 X3 C446
0.1uF 10uF 0.1uF 1uF
16V 10V 16V 10V
1005 2012 1005 1005
Input
DTV Comp HDMI
Copyright © 2012 LG Electronics Inc. All rights reserved. 145mA 105mA 105mA
LGE Internal Use Only
3. Power Block.
In Out Current type
17V 17V(1.1A) 5Vst 5Vst 2mA STBY
ULDO
5V ST 5Vst (2mA) 5Vst 3.3Vst 35mA
0.3A
60mW
ULDO
3.3Vst(33mA) 17V 17V 1.1A Multi
DC-
1 1V(750mA)
1.1V(750mA) FET
F DC 5Vst 5V 910mA + 1A
3A
E
T
5V(?) 5V 5V 1A Multi USB 1A
((Input 220mA)) DCDC

5Vst 1 1V
1.1V 1/4
750mA 3A
LDO 2.5V(102mA)
LDO
5V 2.5V 102mA 255mW
714mW
LDO 1.8V(164mA) 5V 1.8V 164mA

LDO
525mW
850mW
LDO
5V 1.25V 400mA(?) 1500mW
LDO(T2) 1.25V(400mA) 850mW
LDO
5V 3.3V 300mA 510mW
850mW
LDO 3.3V(300mA)
LDO
5V 3.3V 300mA 510mW
850mW
LDO LDO 1.5V(300mA) LDO
3.3V 3.3V 1.5V 300mA
850mW
480mW
4. L13 I2C MAP
+3.3V_TU
R308 2.2K R309 2.2K
AE3 TU_SCL
I2C_SCKM1/GPIO75 TU301
AE2 TU_SDA
I2C_SDAM1/GPIO76 TDSS-G201D (0x)
+3.3V_TU
R313 2.2K R314 2.2K
AE3 T2_SCL
IC400 GPIO39 TU306
AE2 T2 SDA
T2_SDA
GPIO40 TDSQ-G605D (0x)
+3.3V_AMP
R640 4.7K R641 4.7K
H6 AMP_SCL
AMP SCL
GPIO49 IC606
E6 AMP_SDA
GPIO50 STA380BW (0x)
+3.3V
R450 3.3K R451 3.3K P500
B9 P_SCL
I2S_IN_WS/GPIO149 LVDS
B6 P_SDA
SPDIF_IN/GPIO152 (module
0 1C)
0x1C)
+3.3V
R452 2.2K R453 2.2K
AA21 I2C_SCL
I2C_SCKM2/DDCR_CK/GPIO72
AB21 I2C SDA
I2C_SDA IC503 EEPROM (0xA0)
I2C SDAM2/DDCR DA/GPIO71
I2C_SDAM2/DDCR_DA/GPIO71
5. L13 Front End
NetCast 4.0 Low model (Mstar) use three kind of tuner as below
B t we apply
But l 2
2ea PCB(T/C
PCB(T/C_T2/C,S2),
T2/C S2) ffor eachh tuner
t and
d distinguish
di ti i h by
b circuit
i it option
ti and
d tool
t l option
ti
T/C T2/C T/C/S2
2013
Tuner
Figure
Diagram
g Diagram
g Diagram
g
ATV / ATV /
ATV / DVB-T/C SIF/IF
DVB-T/C
DVB-T/C DVB-T2 Si2178 Si2158
Si2156 SIF/IF CVBS/SIF
2013 IF
DVB-S DVB-S DVB-S
DVB-S
Tuner Si2169 RDA
Si2166B TS_ [0:7]
UseMstar TS [0:7]
TS_ 5815S
Block A.Demod
Demod
Tuner Tuner Tuner
Diagram TDSS-G201D L13 Mstar TDSQ-G605D L13 Mstar TDSQ-G501D L13 Mstar
SI2178 : PLL + With Analog Demod Si2166B : DVB-S/S2 Demod

SI2156 : PLL + With out Analog Demod SI2169 : DVB-T2/C/S/S2 Demod RDA5815S : DVB-S/S2 PLL
L13 : DVB-T/C Demod , A.Demod L13 : DVB-T/C Demod, A.Demod
Diagram Diagram
ATV /
ATV /
DVB-T/C SI2176
DVB-T/C SIF/IF CVBS/SIF
SI2156 DVB-T2 IF
2012 Demod
UseMstar
Tuner A.Demod CXD2834 TS_ [0:7]
Compare Tuner Tuner
TDSS-G201D L13 Mstar TDSN-G301D L13 Mstar
SI2156 : PLL + ATV Demod

L13 : DVB-T/C Demod CXD2834 : DVB-T/C/T2 Demod
5. L13 Front End
Use 2ea PCB for each tuner and apply different circuit option and tool option
Tool option4
-T/C
Digital
g Demod-S : DVB_S7
Digital Demod-T/C : DEFAULT
Analog Demod : MSTAR_56
-T2/C
T2/C
Digital Demod-S : NO_DEMOD
Digital Demod-T/C : DVBS_SI2169
Analog Demod : SI2176
EU/AU/JA
-T/C/S2
Digital Demod-S : DVB_S7
Digital Demod-T/C : DVBS_SI2166B
Analogg Demod : MSTAR_58
T/C/S Tuner Area

T2/C Tuner Area
T/C Tuner Area
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Plasma TV: Service Manual

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Internal Use Only

North/Latin America http://aic.lgservice.com

MODEL : 50PN4500 50PN4500-TA

P/NO : MFL67687001 (1212-REV00) Printed in Korea

SAFETY PRECAUTIONS ......................................................................... 3

EXPLODED VIEW .................................................................................. 15

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

IMPORTANT SAFETY NOTICE

General Guidance Leakage Current Hot Check (See below Figure)

always perform an AC leakage current check on the exposed

2. Requirement for Test

(1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C

4. Module General Specification

■ After RGB Full White in HEAT-RUN Mode, the receiver must

Case2 : Function check at the assembly line

* ADC Calibration Protocol (RS232)

* After downloading, have to adjust TOOL OPTION again. - Adjust Sequence

* Caution : Not to push the INSTOP KEY after completion if

COOL 0.276 0.283 11000K 0.002

* Connecting picture of the measuring instrument (On Auto-

No. Item Condition Hex Data

* Caution : Never connect HDMI & D-sub Cable when EDID

* Checksum: Changeable by total EDID data.

4) Check the model name Instart menu -> Factory name

5.2. Signal TABLE

5.3. Command Set

5.4. Method & Notice

* Manual Download (Model Name and Serial Number)

There is impossible to download by bar code scan, so It need

CMD1 CMD2 Data 0

(3) result value

7. Download MAC Address, CI+ Key

* C onnect TV SET and PC which download keys Writing

* Each Chassis has it’s own MAC Address. Please be careful

■ Check the method of RS232C Command

(2) c heck the key download for transmitted command

D2B_OUT 10K 2.7K

<CI SLOT> +5V_CI_ON CI POWER ENABLE CONTROL

BUF1_FE_TS_DATA[7] BUF2_FE_TS_DATA[7] 42 8 PCM_A[1]

10K CI_OE CI_ADDR[6] CI_ADDR[1]

BUF1_FE_TS_DATA[3] BUF2_FE_TS_DATA[3] BUF2_FE_TS_DATA[0] CI_ADDR[14]

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

USB DOWN STREAM

<RS232C> JP241 4 <PHONE JACK> <RGB PC> <WIRED IR>

10K RIN1 C2+

Commercial 13 4 MAX3232 R_SPRING R218 R222 H_SYNC 33 R216

Commercial T_TERMINAL2 R219 R223 DDC_CLOCK R210

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

TU303 TDSS-H501F ATSC HNIM X W/O AD

TU304 TDSN-T501F DVB-T_SCA HNIM RF_SW W/O AD

ERROR ERROR 430 430 R316

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES

I2S_IN_SD/GPIO151 T2_SDA AVDD_NODIE AVDD_NODIE GND_27

COMP2_Pb+ BIN2P PM_RXD PM_UART_RX/GPIO_PM[5]/GPIO11 B9 22 DVB_T2 W5 G10

X400 I2S_IN_WS/GPIO149 P_SCL AVDD_DMPLL GND_28

#POWER FOR MAIN# IC400

AE15 AA13 V17 L19

PCM_D[5] PCMDATA4/GPIO119 TS1DATA4/GPIO92 BUF1_FE_TS_DATA[5] GND_101 GND_62

AD14 AD12 V18

■ After RGB Full White in HEAT-RUN Mode, the receiver must

* Caution : Not to push the INSTOP KEY after completion if

* Connecting picture of the measuring instrument (On Auto-

* Caution : Never connect HDMI & D-sub Cable when EDID

4) Check the model name Instart menu -> Factory name

7. Download MAC Address, CI+ Key

* C onnect TV SET and PC which download keys Writing

* Each Chassis has it’s own MAC Address. Please be careful

(2) c heck the key download for transmitted command