Asynchronous Circuit Design. Chris J.

Myers
Copyright  2001 by John Wiley & Sons, Inc.
ISBNs: 0-471-41543-X (Hardback); 0-471-22414-6 (Electronic)

Asynchronous
Cikuit Design

Chris J. Myers

A Wilcplnterscience Publication
JOHN WILEY 8z SONS, INC.
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Copyright  2001 by John Wiley and Sons, Inc., New York. All rights
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To Ching and John
 Asynchronous Circuit Design. Chris J. Myers
Copyright  2001 by John Wiley & Sons, Inc.
ISBNs: 0-471-41543-X (Hardback); 0-471-22414-6 (Electronic)

Contents

Preface xiii
Acknowledgments xvii

I Introduction 1
I. 1 Problem Specification 1
1.2 Communication Channels 2
1.3 Communication Protocols 4
1 .,J Graphical Representations 8
1.5 Delay-Insensitive Circuits 10
1.6 Hujjfman Circuits 13
I. 7 Muller Circuits 16
1.8 Timed Circuits 17
1.9 Verification 20
1.10 Applications 20
1.11 Let’s Get Started 21
1.12 Sources 21
Problems 22

2 Communication Channels 23
2.1 Basic Structure 24
 ...
VIII CONTENTS

2.2 Structural Modeling in VHDL 27

2.3 Control Structures 31
2.3.1 Selection 31
2.3.2 Repetition 32
2.4 Deadlock 34
2.5 Probe 35
2.6 Parallel Communication 35
2.7 Example: MiniMIPS 36
2.7.1 VHDL Specification 38
2.7.2 Op timixed MiniMIPS 48
2.8 Sources 52
Problems 53

3 Communication Protocols 57
3.1 Basic Structure 57
3.2 Active and Passive Ports 61
3.3 Handshaking Expansion 61
3.4 Reshufling 65
3.5 State Variable Insertion 66
3.6 Data Encoding 67
3.7 Example: Two Wine Shops 71
3.8 Syntax-Directed Translation 73
3.9 Sources 80
Problems 82

4 Graphical Representations 85
4.1 Graph Basics 85
4.2 Asynchronous Finite State Machines 88
42.1 Finite State Machines and Flow Tables 88
42.2 Burst-Mode State Machines 91
4.2.3 Extended Burst-Mode State Machines 93
4.3 Petri Nets 100
43.1 Ordinary Petri Nets 100
4.3.2 Signal Transition Graphs 111
,J .d Timed Event/Level Structures 116
4.5 Sources 120
Problems 121
 CONTENTS ix

5 Hunman Circuits 131

5.1 Solving Covering Problems 132
5.1.1 Matrix Reduction Techniques 134
5.1.2 Bounding 137
5.1.3 Termination 137
5.1 .d Branching 138
5.2 State Minimization 140
5.2.1 Finding the Compatible Pairs 141
5.2.2 Finding the Maximal Compatibles 143
5.2.3 Finding the Prime Compatibles 145
5.2.4 Setting Up the Covering Problem 148
5.2.5 Forming the Reduced Flow Table 154
5.3 State Assignment 154
5.3.1 Partition Theory and State Assignment 155
5.3.2 Matrix Reduction Method 157
5.3.3 Finding the Maximal Intersectibles 158
5.34 Setting Up the Covering Problem 161
5.3.5 Fed-Back Outputs as State Variables 163
5.4 Hazard-Free Two-Level Logic Synthesis 165
54.1 Two-Level Logic Minimization 165
5.4.2 Prime Implicant Generation 166
54.3 Prime Implicant Selection 168
5.4 4 Combinational Hazards 169
5.5 Extensions for MIC Operation 171
5.5.1 Transition Cubes 172
5.5.2 Function Hazards 172
5.5.3 Combinational Hazards 173
5.54 Burst-Mode Transitions 176
5.5.5 Extended Burst-Mode Transitions 177
5.5.6 State Minimization 180
5.5.7 State Assignment 183
5.5.8 Hazard-Free Two-Level Logic Synthesis 183
5.6 Multilevel Logic Synthesis 188
5.7 Technology Mapping 189
5.8 Generalized C-Element Implementation 193
5.9 Sequential Hazards 194
5.10 Sources 196
Problems 199
 CONTENTS

6 Muller Circuits 207

6.1 Formal Definition of Speed Independence 208
61.1 Subclasses of Speed-Independent Circuits 210
6.1.2 Some Useful Definitions 212
6.2 Complete State Coding 216
6.2.1 Transition Points and Insertion Points 217
6.2.2 State Graph Coloring 219
6.2.3 Insertion Point Cost Function 220
6.2.4 State Signal Insertion 222
6.2.5 Algorithm for Solving CSC Violations 223
6.3 Hazard- Free Logic Synthesis 223
6.3.1 Atomic Gate Implementation 225
6.3.2 Generalized C-Element Implementation 226
6.3.3 Standard C-Implementation 230
6.3.4 The Single- Cube Algorithm 238
6.4 .Hazard-Free Decomposition 243
6.4.1 Insertion Points Revisited 245
6.4.2 Algorithm for Hazard-Free Decomposition 246
6.5 Limitations of Speed-Independent Design 248
6.6 Sources 249
Problems 251

7 Timed Circuits 259

7.1 Modeling Timing 260
7.2 Regions 262
7.3 Discrete time 265
7.4 Zones 267
7.5 POSET Timing 280
7.6 Timed Circuits 289
7.7 Sources 292
Problems 293

8 Verification 295
8.1 Protocol Verification 296
8.1.1 Linear- Time Temporal Logic 296
8.1.2 Time- Quantified Requirements 300
8.2 Circuit Verification 303
8.2.1 Trace Structures 303
 CONTENTS xi

8.2.2 Composition 305

8.2.3 Canonical Trace Structures 308
8.2.4 Mirrors and Verification 310
8.2.5 Strong Conformance 312
8.2.6 Timed Trace Theory 314
8.3 Sources 315
Problems 316

9 Applications 321
9.1 Brief History of Asynchronous Circuit Design 322
9.2 An Asynchronous Instruction-Length Decoder 325
9.3 Performance Analysis 329
94 Testing Asynchronous Circuits 330
9: 5 The Synchronization Problem 332
9.5.1 Probability of Synchronixation Failure 334
9.5.2 Reducing the Probability of Failure 335
9.5.3 Eliminating the Probability of Failure 336
95.4 Arbitration 340
9.6 The Future of Asynchronous Circuit Design 341
9.7 Sources 342
Problems 346

Appendix A VHDL Packages 347

A. 1 nondeterminism.vhd 347
A.2 channel.vhd 348
A.3 handshake.vhd 355

Appendix B Sets and Relations 359

B.i Basic Set Theory 360
B.2 Relations 362

References 365

Index 393
 Preface

An important scientific innovation rarely makes its way by gradually winning

over and converting its opponents: it rarely happens that Saul becomes Paul.
What does happen is that its opponents gradually die out and that the growing
generation is familiarized with the idea from the beginning.
-Max Planck

I must govern the clock, not be governed by it.

-Golda Meir

All pain disappears, it’s the nature of my circuitry.

-nine inch nails

In 1969, Stephen Unger published his classic textbook on asynchronous circuit

design. This book presented a comprehensive look at the asynchronous design
methods of the time. In the 30 years hence, there have been numerous techni-
cal publications and even a few books [37, 57, 120, 203, 224, 267, 363, 3931, but
there has not been another textbook. This book attempts to fill this void by
providing an updated look at asynchronous circuit design in a form accessible
to a student who simply has some background in digital logic design.
An asynchronous circuit is one in which synchronization is performed with-
out a global clock. Asynchronous circuits have several advantages over their
synchronous counterparts, including:

...
XIII
xiv PREFACE

1. Elimination of clock skeul problems. As systems become larger, increas-

ing amounts of design effort is necessary to guarantee minimal skew in
the arrival time of the clock signal at different parts of the chip. In an
asynchronous circuit, skew in synchronization signals can be tolerated.

2. Average-case performance. In synchronous systems, the performance

is dictated by worst-case conditions. The clock period must be set to
be long enough to accommodate the slowest operation even though the
average delay of the operation is often much shorter. In asynchronous
circuits, the speed of the circuit is allowed to change dynamically, so the
performance is governed by the average-case delay.

3. Adaptivity to processing and environmental variations. The delay of a

VLSI circuit can vary significantly over different processing runs, supply
voltages, and operating temperatures. Synchronous designs have their
clock rate set to allow correct operation under some allowed variations.
Due to their adaptive nature, asynchronous circuits operate correctly
under all variations and simply speed up or slow down as necessary.

4. Component modularity and reuse. In an asynchronous system, compo-

nents can be interfaced without the difficulties associated with synchro-
nizing clocks in a synchronous system.

5. Lower system power requirements. Asynchronous circuits reduce syn-

chronization power by not requiring additional clock drivers and buffers
to limit clock skew. They also automatically power-down unused compo-
nents. Finally, asynchronous circuits do not waste power due to spurious
transitions.

6. Reduced noise. In a synchronous design, all activity is locked into a very

precise frequency. The result is nearly all the energy is concentrated
in very narrow spectral bands at the clock frequency and its harmon-
ics. Therefore, there is substantial electrical noise at these frequencies.
Activity in an asynchronous circuit is uncorrelated, resulting in a more
distributed noise spectrum and a lower peak noise value.

Despite all these potential advantages, asynchronous design has seen lim-
ited usage to date. Although there are many reasons for this, perhaps the
most serious is a lack of designers with experience in asynchronous design.
This textbook is a direct attempt at addressing this problem by providing a
means for graduate or even undergraduate courses to be created that teach
modern asynchronous design methods. I have used it in a course which
includes both undergraduates and graduates. Lectures and other material
used in this and future courses will be made available on our Web site:
http : //www . async. elen. Utah. edu/book/. This book may also be used for
self-study by engineers who would like to learn about modern asynchronous
 PREFACE xv

design methods. Each chapter includes numerous problems for the student to
try out his or her new skills.
The history of asynchronous design is quite long. Asynchronous design
methods date back to the 1950s and to two people in particular: Huffman
and Muller. Every asynchronous design methodology owes its roots to one of
these two men. Huffman developed a design methodology for what is known
today as fundamental-mode circuits [1701. Muller developed the theoretical
underpinnings of speed-independent circuits [279]. Unger is a member of the
“Huffman School,” so his textbook focused primarily on fundamental-mode
circuit design with only a brief treatment of Muller circuits. Although I am a
student of the “Muller School,” in this book we present both design methods
with the hope that members of both schools will grow to understand each
other better, perhaps even realizing that the differences are not that great.
Since the early days, asynchronous circuits have been used in many in-
teresting applications. In the 1950s and 1960s at the University of Illinois,
Muller and his colleagues used speed-independent circuits in the design of
the ILLIAC and ILLIAC II computers [46]. In the early days, asynchronous
design was also used in the MU-5 and Atlas mainframe computers. In the
1970s at Washington University in St. Louis, asynchronous macromodules
were developed [87]. These modules could be plugged together to create nu-
merous special-purpose computing engines. Also in the 1970s asynchronous
techniques were used at the University of Utah in the design of the first oper-
ational dataflow computer [102, 1031 and at Evans and Sutherland in design
of the first commercial graphics system.
Due to the advantages cited above, there has been a resurgence of inter-
est in asynchronous design. There have been several recent successful de-
sign projects. In 1989, researchers at Caltech designed the first fully asyn-
chronous microprocessor [251, 257, 2581. Since that time, numerous other
researchers have produced asynchronous microprocessors of increasing com-
plexity [lo, 13, 76, 134, 135, 138, 191, 259, 288, 291, 324, 379, 4061. Commer-
cially, asynchronous circuits have had some recent success. Myranet uses asyn-
chronous circuits coupled with pipeline synchronization [348] in their router
design. Philips has designed numerous asynchronous designs targeting low
power [38, 136, 192, 1931. Perhaps the most notable accomplishment to come
out of this group is an asynchronous 8OC51 microcontroller, which is now used
in a fully asynchronous pager being sold by Philips. Finally, the RAPPID
project at Intel demonstrated that a fully asynchronous instruction-length
decoder for the x86 instruction set could achieve a threefold improvement
in speed and a twofold improvement in power compared with the existing
synchronous design [141, 142, 143, 144, 330, 3671.
In the time of Unger’s text, there were perhaps only a handful of pub-
lications each year on asynchronous design. As shown in Figure 0.1, this
rate of publication continued until about 1985, when there was a resurgence
of interest in asynchronous circuit design [309]. Since 1985, the publication
rate has grown to well over 100 technical publications per year. Therefore,
xvi PREFACE

170

160

L.
150

140

130
4
120

iii 110
E 4
g 100

2 90
5
b 80 ! 1
e 70

ii 60

50

40
El
30

20

10

0
1960 1970 1980 1990 2000

Year of publication

Fig. 0.1 Number of asynchronous publications per year.

although Unger did a superb job of surveying the field, this author has his
work cut out for him. In the sources section at the end of each chapter, the
interested reader is pointed to an extensive bibliography (over 400 entries)
to probe deeper. Although an attempt has been made to give a flavor of the
major design methodologies being developed and used, it is impossible even to
reference every paper published on asynchronous design, as the number of en-
tries in the asynchronous bibliography [309] now exceeds 1400. The interested
reader should consult this bibliography and the proceedings from the recent
symposiums on asynchronous circuits and systems [14, 15, 16, 17, 18, 19, 201.
The book is organized as follows. In Chapter 1 we introduce the asyn-
chronous design problem through a small example illustrating the differences
among the various timing models used. In Chapter 2 we introduce the con-
cept of asynchronous communication and describe a methodology for spec-
ifying asynchronous designs using VHDL. In Chapter 3 we discuss various
asynchronous protocols. In Chapter 4 we introduce graphical representations
that are used for asynchronous design. In Chapter 5 we discuss Huffrnan cir-
cuits and in Chapter 6 we describe Muller circuits. In Chapter 7 we develop
techniques for timing analysis and optimization which can lead to significant
improvements in circuit quality. In Chapter 8 we introduce methods for the
analysis and verification of asynchronous circuits. Finally, in Chapter 9 we
give a brief discussion of issues in asynchronous application.

CHRIS J. MYERS
Salt Lake City, Utah
 Acknowledgments

I am indebted to Alain Martin and Chuck Seitz of Caltech, who turned me

onto asynchronous design as an undergraduate. I would also like to thank
my graduate advisors, Teresa Meng and David Dill of Stanford University,
who taught me alternative ways of looking at asynchronous design. My for-
mer officemate, Peter Beerel (USC), through numerous heated discussions
throughout the years, has taught me much.
I would like to thank Erik Brunvand (Utah), Steve Nowick (Columbia), Pe-
ter Beerel (USC), Wendy Belluomini (IBM), Ganesh Gopalakrishnan (Utah),
Ken Stevens (Intel), Charles Dike (Intel), Jim Frenzel (U. of Idaho), Steven
Unger (Columbia), Dong-Ik Lee (K JIST) , and Tomohiro Yoneda (Titech) for
their comments and advice on earlier versions of this manuscript. I’m also
grateful to the comments and ideas that I received from my graduate students:
Brandon Bachman, Jie Dai, Hans Jacobson, Kip Killpack, Chris Krieger,
Scott Little, Eric Mercer, Curt Nelson, Eric Peskin, Robert Thacker, and Hao
Zheng. I would like to thank the students in my course on asynchronous cir-
cuit design in the spring of 2000 for putting up with the rough version of this
text. I am grateful to Sanjin Piragic for drawing many of the figures in the
book. Many other figures are due to drawastg by Jordi Cortadella (UPC)
and dot by Eleftherios Koutsofios and Stephen North (AT&T).
I would like especially to thank my family, Ching and John, for being
patient with me while I wrote this book. Without their love and support, the
book would not have been possible.

C.J.M.

xvii
Asynchronous
Circuit Design