MC74HC74A

Dual D Flip-Flop with Set

and Reset
High−Performance Silicon−Gate CMOS
The MC74HC74A is identical in pinout to the LS74. The device http://onsemi.com
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock SOIC−14 NB TSSOP−14
D SUFFIX DT SUFFIX
input. Both Q and Q outputs are available from each flip−flop. The Set CASE 751A CASE 948G
and Reset inputs are asynchronous.
PIN ASSIGNMENT
Features
• Output Drive Capability: 10 LSTTL Loads RESET 1 1 14 VCC
• Outputs Directly Interface to CMOS, NMOS, and TTL DATA 1 2 13 RESET 2
• Operating Voltage Range: 2.0 to 6.0 V CLOCK 1 3 12 DATA 2
• Low Input Current: 1.0 mA SET 1 4 11 CLOCK 2
• High Noise Immunity Characteristic of CMOS Devices Q1 5 10 SET 2
• In Compliance with the JEDEC Standard No. 7.0 A Requirements Q1 6 9 Q2
• Chip Complexity: 128 FETs or 32 Equivalent Gates GND 7 8 Q2
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable MARKING DIAGRAMS
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
14
HC74AG
LOGIC DIAGRAM AWLYWW
1
RESET 1 1

2 5 SOIC−14 NB
DATA 1 Q1
3 6
CLOCK 1 Q1 14
HC
4 74A
SET 1
ALYWG
G
13
RESET 2 1

12 9 TSSOP−14
DATA 2 Q2
11 8 A = Assembly Location
CLOCK 2 Q2
L, WL = Wafer Lot
10 Y, YY = Year
SET 2 W, WW = Work Week
PIN 14 = VCC G or G = Pb−Free Package
PIN 7 = GND
(Note: Microdot may be in either location)

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

August, 2014 − Rev. 14 MC74HC74A/D
 MC74HC74A

FUNCTION TABLE
Inputs Outputs
Set Reset Clock Data Q Q
L H X X H L
H L X X L H
L L X X H* H*
H H H H L
H H L L H
H H L X No Change
H H H X No Change
H H X No Change

*Both outputs will remain high as long as Set

and Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.

MAXIMUM RATINGS
Symbol Parameter Value Unit This device contains protection
VCC DC Supply Voltage (Referenced to GND) –0.5 to + 7.0 V circuitry to guard against damage
Vin DC Input Voltage (Referenced to GND) –0.5 to VCC + 0.5 V due to high static voltages or electric
fields. However, precautions must
Vout DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V be taken to avoid applications of any
Iin DC Input Current, per Pin ±20 mA voltage higher than maximum rated
Iout DC Output Current, per Pin ±25 mA voltages to this high−impedance cir-
cuit. For proper operation, Vin and
ICC DC Supply Current, VCC and GND Pins ±50 mA
Vout should be constrained to the
PD Power Dissipation in Still Air, SOIC Package† 500 mW range GND v (Vin or Vout) v VCC.
TSSOP Package† 450 Unused inputs must always be
Tstg Storage Temperature –65 to +150 _C tied to an appropriate logic voltage
level (e.g., either GND or VCC).
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
Unused outputs must be left open.
(SOIC or TSSOP Package) 260
300
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types –55 +125 _C
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns
(Figures 1, 2, 3) VCC = 3.0 V 0 600
VCC = 4.5 V 0 500
VCC = 6.0 V 0 400
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

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 MC74HC74A

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC –55 to
Symbol Parameter Test Conditions V 25_C v 85_C v 125_C Unit
VIH Minimum High−Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
Voltage |Iout| v 20 mA 3.0 2.1 2.1 2.1
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
VIL Maximum Low−Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.5 0.5 0.5 V
Voltage |Iout| v 20 mA 3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8
VOH Minimum High−Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| v 20 mA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin = VIH or VIL |Iout| v 2.4 mA 3.0 2.48 2.34 2.2
|Iout| v 4.0 mA 4.5 3.98 3.84 3.7
|Iout| v 5.2 mA 6.0 5.48 5.34 5.2
VOL Maximum Low−Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| v 20 mA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| v 2.4 mA 3.0 0.26 0.33 0.4
|Iout| v 4.0 mA 4.5 0.26 0.33 0.4
|Iout| v 5.2 mA 6.0 0.26 0.33 0.4
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 2.0 20 80 mA
Current (per Package) Iout = 0 mA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit
VCC – 55 to
Symbol Parameter V 25_C v 85_C v 125_C Unit
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6.0 4.8 4.0 MHz
(Figures 1 and 4) 3.0 15 10 8.0
4.5 30 24 20
6.0 35 28 24
tPLH, Maximum Propagation Delay, Clock to Q or Q 2.0 100 125 150 ns
tPHL (Figures 1 and 4) 3.0 75 90 120
4.5 20 25 30
6.0 17 21 26
tPLH, Maximum Propagation Delay, Set or Reset to Q or Q 2.0 105 130 160 ns
tPHL (Figures 2 and 4) 3.0 80 95 130
4.5 21 26 32
6.0 18 22 27
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 4) 3.0 30 40 55
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance — 10 10 10 pF

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Flip−Flop)* 32 pF
* Used to determine the no−load dynamic power consumption: P D = CPD VCC 2f + ICC VCC .

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 MC74HC74A

TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)

Guaranteed Limit

VCC –55 to
Symbol Parameter V 25_C v 85_C v 125_C Unit
tsu Minimum Setup Time, Data to Clock 2.0 80 100 120 ns
(Figure 3) 3.0 35 45 55
4.5 16 20 24
6.0 14 17 20
th Minimum Hold Time, Clock to Data 2.0 3.0 3.0 3.0 ns
(Figure 3) 3.0 3.0 3.0 3.0
4.5 3.0 3.0 3.0
6.0 3.0 3.0 3.0
trec Minimum Recovery Time, Set or Reset Inactive to Clock 2.0 8.0 8.0 8.0 ns
(Figure 2) 3.0 8.0 8.0 8.0
4.5 8.0 8.0 8.0
6.0 8.0 8.0 8.0
tw Minimum Pulse Width, Clock 2.0 60 75 90 ns
(Figure 1) 3.0 25 30 40
4.5 12 15 18
6.0 10 13 15
tw Minimum Pulse Width, Set or Reset 2.0 60 75 90 ns
(Figure 2) 3.0 25 30 40
4.5 12 15 18
6.0 10 13 15
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns
(Figures 1, 2, 3) 3.0 800 800 800
4.5 500 500 500
6.0 400 400 400

ORDERING INFORMATION
Device Package Shipping†
MC74HC74ADG SOIC−14 NB 55 Units / Rail
(Pb−Free)

NLV74HC74ADG* SOIC−14 NB 55 Units / Rail

(Pb−Free)

MC74HC74ADR2G SOIC−14 NB 2500 / Tape & Reel

(Pb−Free)

NLV74HC74ADR2G* SOIC−14 NB 2500 / Tape & Reel

(Pb−Free)

MC74HC74ADTR2G TSSOP−14 2500 / Tape & Reel

(Pb−Free)

NLV74HC74ADTR2G* TSSOP−14 2500 / Tape & Reel

(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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 MC74HC74A

SWITCHING WAVEFORMS

tw
tf tr VCC
VCC SET OR 50%
90%
CLOCK 50% RESET GND
10% GND tPHL
tw
1/fmax Q OR Q 50%

tPLH tPHL
tPLH
90%
50%
Q or Q 10% Q OR Q 50%
trec
tTLH tTHL
VCC
CLOCK 50%
GND

Figure 1. Figure 2.

TEST POINT
VALID
VCC
DATA 50% OUTPUT
GND DEVICE
tsu th UNDER
VCC TEST CL*
50%
CLOCK GND
*Includes all probe and jig capacitance

Figure 3. Figure 4.

4, 10
SET

2, 12 5, 9
DATA Q

3, 11
CLOCK

6, 8
Q

1, 13
RESET

Figure 5. EXPANDED LOGIC DIAGRAM

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 MC74HC74A

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G
ISSUE B

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE
−U− N DAMBAR PROTRUSION. ALLOWABLE
PIN 1 DAMBAR PROTRUSION SHALL BE 0.08
IDENT. F (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
0.15 (0.006) T U S
A K DETERMINED AT DATUM PLANE −W−.

ÉÉÉ
ÇÇÇ
−V− K1 MILLIMETERS INCHES
DIM MIN MAX MIN MAX

ÇÇÇ
ÉÉÉ
A 4.90 5.10 0.193 0.200
J J1 B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
SECTION N−N F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
−W− J 0.09 0.20 0.004 0.008
C J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
0.10 (0.004) K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
−T− SEATING D G H DETAIL E M 0_ 8_ 0_ 8_
PLANE

SOLDERING FOOTPRINT

7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

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 MC74HC74A

PACKAGE DIMENSIONS

SOIC−14 NB
CASE 751A−03
ISSUE K
D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
b DIM MIN MAX MIN MAX
0.25 M B M 13X
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h D 8.55 8.75 0.337 0.344
A X 45 _ E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
M L 0.40 1.25 0.016 0.049
e A1
SEATING M 0_ 7_ 0_ 7_
C PLANE

SOLDERING FOOTPRINT*
6.50 14X
1.18
1

1.27
PITCH

14X
0.58

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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