MC14043B, MC14044B

CMOS MSI
Quad R−S Latches
The MC14043B and MC14044B quad R−S latches are constructed
with MOS P−Channel and N−Channel enhancement mode devices in
a single monolithic structure. Each latch has an independent Q output http://onsemi.com
and set and reset inputs. The Q outputs are gated through three−state
buffers having a common enable input. The outputs are enabled with
a logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs. SOIC−16 SOEIAJ−16
D SUFFIX F SUFFIX
Features CASE 751B CASE 966

• Double Diode Input Protection

MARKING DIAGRAMS
• Three−State Outputs with Common Enable
• Outputs Capable of Driving Two Low−power TTL Loads or One
16
Low−Power Schottky TTL Load Over the Rated Temperature
Range 140xxBG
AWLYWW
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• NLV Prefix for Automotive and Other Applications Requiring 1
Unique Site and Control Change Requirements; AEC−Q100 SOIC−16
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant 16

MC14043B
MAXIMUM RATINGS (Voltages Referenced to VSS) ALYWG
Symbol Parameter Value Unit
1
VDD DC Supply Voltage Range −0.5 to +18.0 V SOEIAJ−16
Vin, Vout Input or Output Voltage Range −0.5 to VDD + 0.5 V
(DC or Transient)
xx = Specific Device Code
Iin, Iout Input or Output Current ± 10 mA A = Assembly Location
(DC or Transient) per Pin WL, L = Wafer Lot
YY, Y = Year
PD Power Dissipation, per Package 500 mW WW, W = Work Week
(Note 1) G = Pb−Free Indicator
TA Ambient Temperature Range −55 to +125 °C
Tstg Storage Temperature Range −65 to +150 °C ORDERING INFORMATION
See detailed ordering and shipping information in the package
TL Lead Temperature 260 °C dimensions section on page 5 of this data sheet.
(8−Second Soldering)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:

August, 2014 − Rev. 10 MC14043B/D
 MC14043B, MC14044B

PIN ASSIGNMENT

MC14043B MC14044B
Q3 1 16 VDD Q3 1 16 VDD
Q0 2 15 R3 NC 2 15 S3
R0 3 14 S3 S0 3 14 R3
S0 4 13 NC R0 4 13 Q0
E 5 12 S2 E 5 12 R2
S1 6 11 R2 R1 6 11 S2
R1 7 10 Q2 S1 7 10 Q2
VSS 8 9 Q1 VSS 8 9 Q1

NC = NO CONNECTION

MC14043B MC14044B
4 4
S0 2 R0 13
Q0 Q0

3 3
R0 S0
6 6
S1 9 R1 9
Q1 Q1

7 VDD = PIN 16 7 VDD = PIN 16

R1 S1
VSS = PIN 8 VSS = PIN 8
12 NC = PIN 13 12 NC = PIN 2
S2 10 R2 10
Q2 Q2

11 11
R2 S2
14 14
S3 1 TRUTH TABLE R3 1 TRUTH TABLE
Q3 Q3
S R E Q S R E Q
X X 0 High X X 0 High
15 Impedance Impedance
15
R3 0 0 1 No Change S3 0 0 1 0
0 1 1 0 0 1 1 1
5 1 0 1 1 5 1 0 1 0
ENABLE 1 1 1 1 1 1 1 No Change
ENABLE
X = Don’t Care X = Don’t Care

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 MC14043B, MC14044B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

− 55_C 25_C 125_C

VDD Typ
Characteristic Symbol Vdc Min Max Min (Note 2) Max Min Max Unit
Output Voltage “0” Level VOL 5.0 − 0.05 − 0 0.05 − 0.05 Vdc
Vin = VDD or 0 10 − 0.05 − 0 0.05 − 0.05
15 − 0.05 − 0 0.05 − 0.05
“1” Level VOH 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc
Vin = 0 or VDD 10 9.95 − 9.95 10 − 9.95 −
15 14.95 − 14.95 15 − 14.95 −
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 − 1.5 − 2.25 1.5 − 1.5
(VO = 9.0 or 1.0 Vdc) 10 − 3.0 − 4.50 3.0 − 3.0
(VO = 13.5 or 1.5 Vdc) 15 − 4.0 − 6.75 4.0 − 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 − 3.5 2.75 − 3.5 −
(VO = 1.0 or 9.0 Vdc) 10 7.0 − 7.0 5.50 − 7.0 −
(VO = 1.5 or 13.5 Vdc) 15 11 − 11 8.25 − 11 −
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 –3.0 − –2.4 –4.2 − –1.7 −
(VOH = 4.6 Vdc) 5.0 –0.64 − –0.51 –0.88 − –0.36 −
(VOH = 9.5 Vdc) 10 –1.6 − –1.3 –2.25 − –0.9 −
(VOH = 13.5 Vdc) 15 –4.2 − –3.4 –8.8 − –2.4 −
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc
(VOL = 0.5 Vdc) 10 1.6 − 1.3 2.25 − 0.9 −
(VOL = 1.5 Vdc) 15 4.2 − 3.4 8.8 − 2.4 −
Input Current Iin 15 − ±0.1 − ±0.00001 ±0.1 − ±1.0 mAdc
Input Capacitance Cin − − − − 5.0 7.5 − − pF
(Vin = 0)
Quiescent Current IDD 5.0 − 1.0 − 0.002 1.0 − 30 mAdc
(Per Package) 10 − 2.0 − 0.004 2.0 − 60
15 − 4.0 − 0.006 4.0 − 120
Total Supply Current (Notes 3 & 4) IT 5.0 IT = (0.58 mA/kHz) f + IDD mAdc
(Dynamic plus Quiescent, 10 IT = (1.15 mA/kHz) f + IDD
Per Package) 15 IT = (1.73 mA/kHz) f + IDD
(CL = 50 pF on all outputs all
buffers switching)
Three−State Output Leakage ITL 15 − ±0.1 − ±0.0001 ±0.1 − ±3.0 mAdc
Current
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.004.

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 MC14043B, MC14044B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VDD Typ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min (Note 6) Max Unit
Output Rise Time tTLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (1.35 ns/pF) CL + 32.5 ns 5.0 − 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH = (0.60 ns/pF) CL + 20 ns 10 − 50 100
tTLH = (0.40 ns/pF) CL + 20 ns 15 − 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Fall Time tTHL ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (1.35 ns/pF) CL + 32.5 ns 5.0 − 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL = (0.60 ns/pF) CL + 20 ns 10 − 50 100
tTHL = (0.40 ns/pF) CL + 20 ns 15 − 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.90 ns/pF) CL + 130 ns 5.0 − 175 350
tPLH = (0.36 ns/pF) CL + 57 ns 10 − 75 175

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH = (0.26 ns/pF) CL + 47 ns 15 − 60 120

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.90 ns/pF) CL + 130 ns tPHL 5.0 − 175 350 ns
tPHL = (0.90 ns/pF) CL + 57 ns 10 − 75 175

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL = (0.26 ns/pF) CL + 47 ns
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set, Set Pulse Width tW
15
5.0
−
200
60
80
120
− ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 40 −
15 70 30 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset, Reset Pulse Width tW 5.0 200 80 − ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 100 40 −
15 70 30 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Three−State Enable/Disable Delay
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLZ,
tPHZ,
5.0
10
−
−
150
80
300
160
ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZL, 15 − 55 110
tPZH
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

AC WAVEFORMS

MC14043B MC14044B
20 ns 20 ns 20 ns 20 ns
VDD VDD
90% 90%
50% 50%
SET 10% SET 10%
VSS VSS
20 ns 20 ns 20 ns 20 ns
VDD
90% 90% VDD
50% 50%
RESET 10% RESET 10%
VSS VSS
tTHL tTLH
tTLH tTHL
VOH VOH
90% 90%
Q 10% 50% Q 50%
VOL 10% VOL
tPHL tPLH
tPLH tPHL

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 MC14043B, MC14044B

THREE−STATE ENABLE/DISABLE DELAYS

Set, Reset, Enable, and Switch Conditions for 3−State Tests VDD
MC14043B MC14044B

Test Enable S1 S2 Q S R S R
tPZH Open Closed A VDD VSS VSS VDD S1

tPZL Closed Open B VSS VDD VDD VSS TO

1k
OUTPUT
tPHZ Open Closed A VDD VSS VSS VDD UNDER CL
TEST 50 pF
tPLZ Closed Open B VSS VDD VDD VSS
S2

VSS

VDD
ENABLE 50%
VSS

tPZH VDD
90%
QA 10%
tPHZ VOL
tPZL
tPLZ VOH
QB
10%
VSS

ORDERING INFORMATION
Device Package Shipping†
MC14043BDG SOIC−16 48 Units / Rail
(Pb−Free)
NLV14043BDG* SOIC−16 48 Units / Rail
(Pb−Free)
MC14043BDR2G SOIC−16 2500 Units / Tape & Reel
(Pb−Free)
NLV14043BDR2G* SOIC−16 2500 Units / Tape & Reel
(Pb−Free)
MC14043BFELG SOEIAJ−16 2000 Units / Tape & Reel
(Pb−Free)

MC14044BDG SOIC−16 48 Units / Rail

(Pb−Free)
NLV14044BDG* SOIC−16 48 Units / Rail
(Pb−Free)
MC14044BDR2G SOIC−16 2500 Units / Tape & Reel
(Pb−Free)
NLV14044BDR2G* SOIC−16 2500 Units / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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 MC14043B, MC14044B

PACKAGE DIMENSIONS

SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
−A− NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
16 9 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
−B− P 8 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
1 8
0.25 (0.010) M B S SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
G A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F F 0.40 1.25 0.016 0.049
K R X 45 _
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
C K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
−T− SEATING P 5.80 6.20 0.229 0.244
PLANE
M J R 0.25 0.50 0.010 0.019
D 16 PL

0.25 (0.010) M T B S A S

SOLDERING FOOTPRINT*
8X
6.40
16X 1.12
1 16

16X
0.58

1.27
PITCH

8 9

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 MC14043B, MC14044B

PACKAGE DIMENSIONS

SOEIAJ−16
F SUFFIX
CASE 966
ISSUE A

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
16 9 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 8 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
D RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
e A MILLIMETERS INCHES
c DIM MIN MAX MIN MAX
A --- 2.05 --- 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.10 0.20 0.007 0.011
A1 D 9.90 10.50 0.390 0.413
b E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z --- 0.78 --- 0.031

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7