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MC14070B, MC14077B Cmos Ssi: Quad Exclusive "OR" and "NOR" Gates

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MC14070B, MC14077B

CMOS SSI

Quad Exclusive “OR” and “NOR” Gates


The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P–channel and
N–channel enhancement mode devices in a single monolithic http://onsemi.com
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired. MARKING
• Supply Voltage Range = 3.0 Vdc to 18 Vdc DIAGRAMS
• All Outputs Buffered 14
PDIP–14
• Capable of Driving Two Low–Power TTL Loads or One Low–Power P SUFFIX MC140XXBCP
AWLYYWW
Schottky TTL Load Over the Rated Temperature Range CASE 646
• Double Diode Protection on All Inputs 1
• MC14070B — Replacement for CD4030B and CD4070B Types 14
• MC14077B — Replacement for CD4077B Type SOIC–14
140XXB
D SUFFIX AWLYWW
CASE 751A
1

MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) 14


Symbol Parameter Value Unit SOEIAJ–14
F SUFFIX MC140XXB
VDD DC Supply Voltage Range – 0.5 to +18.0 V CASE 965 AWLYWW
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V
1
(DC or Transient)
Iin, Iout Input or Output Current ± 10 mA XX = Specific Device Code
(DC or Transient) per Pin A = Assembly Location
WL or L = Wafer Lot
PD Power Dissipation, 500 mW
YY or Y = Year
per Package (Note 3.)
WW or W = Work Week
TA Ambient Temperature Range – 55 to +125 °C
Tstg Storage Temperature Range – 65 to +150 °C
TL Lead Temperature 260 °C ORDERING INFORMATION
(8–Second Soldering)
Device Package Shipping
2. Maximum Ratings are those values beyond which damage to the device
may occur. MC140XXBCP PDIP–14 2000/Box
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C MC140XXBD SOIC–14 2750/Box

This device contains protection circuitry to guard against damage due to high MC140XXBDR2 SOIC–14 2500/Tape & Reel
static voltages or electric fields. However, precautions must be taken to avoid
MC140XXBF SOEIAJ–14 See Note 1.
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) vVDD.
MC140XXBFEL SOEIAJ–14 See Note 1.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., 1. For ordering information on the EIAJ version of
either VSS or VDD). Unused outputs must be left open. the SOIC packages, please contact your local
ON Semiconductor representative.

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:


March, 2000 – Rev. 3 MC14070B/D
MC14070B, MC14077B

PIN ASSIGNMENT
IN 1A 1 14 VDD
IN 2A 2 13 IN 2D
OUTA 3 12 IN 1D
OUTB 4 11 OUTD
IN 1B 5 10 OUTC
IN 2B 6 9 IN 2C
VSS 7 8 IN 1C

MC14070B MC14077B
QUAD Exclusive OR QUAD Exclusive NOR
Gate Gate
1 1
3 3
2 2
5 5
4 4
6 6
8 8
10 10
9 9
12 12
11 11
13 13
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)

20 ns 20 ns
VDD VDD
90%
50%
Vin 10%
IDD VSS
1/f
Vin * 50% DUTY CYCLE
CL

*Inverted output on MC14077B only.

Figure 1. Power Dissipation Test Circuit and Waveform

VDD 20 ns 20 ns
VDD
PULSE 90%
* INPUT 50%
GENERATOR 10%
# VSS
CL tPHL tPLH
VSS 90% VOH
OUTPUT 50%
10% VOL
tTHL tTLH
*Inverted output on MC14077B only.
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.

Figure 2. Switching Time Test Circuit and Waveforms

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2
MC14070B, MC14077B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ ÎÎÎ
Î
ÎÎÎÎÎ ÎÎ
ÎÎÎ VDD
– 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ
Vin = 0 or VDD ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VOH 5.0
10
4.95
9.95


4.95
9.95
5.0
10


4.95
9.95


Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
15 14.95 — 14.95 15 — 14.95 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(VOL = 0.4 Vdc)

ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc

ÎÎ
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Iin 15 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
Quiescent Current

ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
(Per Package)

ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
IDD 5.0
10


0.25
0.5


0.0005
0.0010
0.25
0.5


7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30
Total Supply Current (5.) (6.) IT = (0.3 µA/kHz) f + IDD µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
IT 5.0
(Dynamic plus Quiescent, 10 IT = (0.6 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
Per Package) 15 IT = (0.9 µA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ ÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
Output Rise and Fall Times (5.)

ÎÎÎ
ÎÎÎ
tTLH, ns

ÎÎ
(CL = 50 pF) tTHL

ÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns

ÎÎÎÎ
5.0

ÎÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎÎ
100

ÎÎÎ
200

ÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ
tTLH, tTHL = (0.60 ns/pF) CL + 20 ns

ÎÎÎ
ÎÎÎ
tTLH, tTHL = (0.40 ns/pF) CL + 20 ns
10
15






50
40
100
80



ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
Propagation Delay Times (5.) tPLH, ns
(CL = 50 pF) tPHL

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎ
ÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎ
tPLH, tPHL = (0.90 ns/pF) CL + 130 ns

ÎÎÎ
ÎÎÎ
tPLH, tPHL = (0.36 ns/pF) CL + 57 ns
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
5.0
10
15









175
75
55
350
150
110






4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

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MC14070B, MC14077B

PACKAGE DIMENSIONS

P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE M NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
N F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
–T– J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING
PLANE L 0.290 0.310 7.37 7.87
K J M ––– 10_ ––– 10_
H G D 14 PL M N 0.015 0.039 0.38 1.01

0.13 (0.005) M

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MC14070B, MC14077B

PACKAGE DIMENSIONS

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
–A– Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

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5
MC14070B, MC14077B

PACKAGE DIMENSIONS

F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 965–01
ISSUE O NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
14 8 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 7 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
D BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
A MILLIMETERS INCHES
e DIM MIN MAX MIN MAX
c A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
b A1 D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
0.13 (0.005) M 0.10 (0.004) e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
0.50 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 1.42 ––– 0.056

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MC14070B, MC14077B

Notes

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MC14070B, MC14077B

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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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