CHAPTER 1

EVOLUTION TOWARDS PROJECT IDEA

Encryption has long been used by militaries and governments to facilitate secret
communication. It is now commonly used in protecting information within many kinds of
civilian systems. Encryption is also used to protect data in transit, for example data being
transferred via networks (e.g., the Internet, e Commerce), mobile telephones, wireless
microphones, wireless intercom systems, Bluetooth devices and bank automatic teller machines.
The encryption standards such as DES (Data Encryption Standard), AES (Advanced Encryption
Standard) and EES (Escrowed Encryption Standard) are widely used to solve the problem of
communication over an insecure channel. First, the encryption and decryption procedures are
much simpler, and consequently, much faster. Second, the security level is higher due to the
inherent poly alphabetic nature of the substitution mapping method used here, together with the
translation and transposition operations performed in the algorithm.
When digital data is transmitted or stored in nonvolatile memory, it is crucial to have a
mechanism that can detect and correct a certain number of errors. Error correction code (ECC)
encodes data in such a way that a decoder can identify and correct errors in the data. Typically,
data strings are encoded by adding a number of redundant bits to them. When the original data is
reconstructed, a decoder examines the encoded message to check for any errors.
1.1 Block codes
These codes are referred to as “n” and “k” codes. A block of k data bits is encoded to
become a block of n bits called a code word. In block codes, code words do not have any
dependency on previously encoded messages. NAND Flash memory devices typically use block
codes.
1.2 Convolution codes
These codes produce code words that depend on both the data message and a given
number of previously encoded messages. The encoder changes state with every message
processed. Typically, the length of the code word is constant.
The transfers of data in the present days invariably necessitate the use of encryption.
Besides its uses in Military and Government’s secret communication, Encryption is also used for
protecting many kinds of civilian systems such as Internet e-commerce, Mobile networks,

1
automatic teller machine transactions, copy protection (especially protection against reverse
Engineering and Software piracy), and many more. Data encryption is achieved by following a
systematic algorithm called encryption algorithm. An encryption algorithm provides
Confidentiality, Authentication, Integrity and Non-repudiation. Confidentiality is the
requirement that the information is kept secret from people who are not authorized to access it.
Authentication is the certainty that the message indeed originates from the supposed
sender. Integrity is the requirement that the information is unaltered and complete, or, that
information “is modified only by those users who have the right to do so.” Non-repudiation
means that the sender or receiver of a message cannot deny having sent or received the message .
Encryption is usually done just before sending data. To utilize the channel resources completely
encryption algorithm must have a speed at least equivalent to data transmission speed. Achieving
high throughput for encryption algorithm for a communication channel of high data rate is a
challenging task.

1.3 INTRODUCTION TO TECHNOLOGY

VLSI stands for "Very Large Scale Integration". This is the field which involves packing
more and more logic devices into smaller and smaller areas.

 Simply we say Integrated circuit is many transistors on one chip.

 Design/manufacturing of extremely small, complex circuitry using modified
semiconductor material
 Integrated circuit (IC) may contain millions of transistors, each a few mm in size
 Applications wide ranging: most electronic logic devices

In olden days, when huge computers made of vacuum tubes could occupy an entire
dedicated rooms and could do about 360 multiplications of 10 digit numbers in a second. Modern
day computers are getting smaller, faster, and cheaper and more power efficient for every
progressing second. The electronic miniaturizing started when the occurrence of semiconductor
transistor by Bardeen (1947-48) and then the Bipolar Transistor by Shockley (1949) in the Bell
Laboratory.

2
 The first IC (Integrated Circuit) was invented by Jack Kilby in 1958, in the form of a Flip
Flop our ability to pack more and more transistors onto a single chip has doubled roughly every
18 months, in accordance with the Moore’s Law. Such exponential or increasing development
had never been seen in any other field and still it is continuing in major areas of research work .

1.4 FUTURE OF VLSI:

Generally, VLSI technology is used in the devices like computers, cell phones, digital
cameras and any electronic gadget. There are certain key issues that serve as active areas of
research and are constantly improving as the field continues to mature. VLSI is dominated by the
CMOS technology and much like other logic families, this too has its limitations which have
been battled and improved upon since years. By taking the example of a processor, the process
technology has rapidly shrunk from 180 nm in 1999 to 60nm in 2008 and now it stands at 45nm
and attempts are being made to reduce it for 32nm. As the number of transistors increase, the
power dissipation is increasing and also the noise. Heat is generated per unit area. New
alternatives like Gallium Arsenide technology are becoming an active area of research; future of
VLSI seems to change for every little moment.

History of Scale Integration

 Late 40s Transistor invented at Bell Labs

 Late 50s First IC (JK-FF by Jack Kelby at TI)
 Early 60s Small Scale Integration (SSI)
 10s of transistors on a chip
 Late 60s Medium Scale Integration (MSI)
 100s of transistors on a chip
 Early 70s Large Scale Integration (LSI)
 1000s of transistor on a chip
 Early 80s VLSI 10,000s of transistors on a Chip (later 100,000s & now 1,000,000s)
 Ultra LSI is sometimes used for 1,000,000s
 SSI - Small-Scale Integration (0-102)
 MSI - Medium-Scale Integration (102-103)
 LSI - Large-Scale Integration (103-105)
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  VLSI - Very Large-Scale Integration (105-107)
 ULSI - Ultra Large-Scale Integration (>=107)

1.5 ADVANTAGES

These advantages of integrated circuits translate into advantages at the system level are

 Smaller physical size: Smallness is often an advantage in itself-consider portable

televisions or handheld cellular telephones.
 Lower power consumption: Replacing a handful of standard parts with a single chip
reduces total power consumption.
 Reduced cost: Reducing the number of components, the power supply requirements,
cabinet costs, and so on, will inevitably reduce system cost.

Understanding why integrated circuit technology has such profound influence on the
design of digital systems requires understanding both the technology of IC manufacturing and
the economics of ICs and digital systems.

1.6 APPLICATIONS OF VLSI

VLSI is having applications in various domains such as electronic systems, medical,

communication, digital signal processing. Some of them are listed as below

1.6.1 Electronic system in cars:

Electronic systems now perform a wide variety of tasks in daily life. Electronic systems
in some cases have replaced mechanisms that operated mechanically, hydraulically, or by other
means; electronics are usually smaller, more flexible, and easier to service. In other cases
electronic systems have created totally new applications. Electronic systems perform a variety of
tasks, some of them are visible while some are hidden. Personal entertainment systems such as
portable MP3 players and DVD players perform sophisticated algorithms with remarkably little
energy.

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1.6.2 Digital electronics control VCRs:

Digital electronics compress and decompress video, even at high-definition data rates,
on-the-fly in consumer electronics. Low-cost terminals for Web browsing still require
sophisticated electronics, despite their dedicated function.

1.6.3 Transaction processing system, ATM

Electronic systems in cars operate stereo systems and displays; they also control fuel
injection systems, adjust suspensions to varying terrain, and perform the control functions
required for anti-lock braking systems.

1.6.4 Personal computers and Workstations

Personal computers and workstations provide word-processing, financial analysis, and

games. Computers include both central processing units and special-purpose hardware for disk
access, faster screen display, etc.

1.6.5 Medical electronic systems:

Medical electronic systems measure bodily functions and perform complex processing
algorithms to warn about unusual conditions. The availability of these complex systems, far from
overwhelming consumers, only creates demand for even more complex systems.

1.7 EXISTING SYSTEM

The necessity of providing security to files on the desktop has been essential since many
of them implemented different algorithms and techniques to provide security. At present there
are many algorithms such as DES, IDEA, and RSA. The main disadvantage is the above
algorithms are breakable at certain point. There exists the problem for decrypting the file unless
the secret key entered for encryption and decryption are similar. After encryption of files, there is
no security of file deletion using right click menu. In this case the encrypted files can be easily
deleted. To avoid these drawbacks, the proposed system has few enhancements in securing the
information in the disk.

5
 AES is the Advanced Encryption Standard, a United States government standard
algorithm for changing the plain text to cipher text i.e. encrypting and decrypting the data. The
National Institute of Standards and Technology (NIST) published a request for comments for the
“Development of a Federal Information Processing Standard for Advanced Encryption Standard”
on January 2, 1997. NIST searched for alternatives that have higher level of security than that
offered by the other algorithms such as DES, IDEA and RSA. Data Encryption Standard (DES)
which grew vulnerable to brute-force attacks due to its 56-bit effective key length. AES
candidates were required to support a symmetric block cipher that supported multiple key
lengths. The algorithm had to be publicly defined, free to use, and able to run efficiently in both
hardware and software. The central design principle of the AES algorithm is the adoption of
symmetry at different platforms and the efficiency of processing. After a 5-year standardization
process, the NIST adopted the Rijndael algorithm as the Advance Encryption Standard (AES).
AES is a symmetric block cipher with a block size of 128 bits. Key lengths can be 128bits, 192
bits, or 256 bits;8 called AES-128, AES- 192 and AES-256 respectively.

DES (Data Encryption Standard) algorithm purpose is to provide a standard method for
protecting sensitive commercial and unclassified data. In this same key used for encryption and
decryption process [7]. DES algorithm consists of the following steps Encryption.

1 DES accepts an input of 64-bit long plaintext and 56-bitkey (8 bits of parity) and produce
output of 64 bit block.
2 The plaintext block has to shift the bits around.
3 The 8 parity bits are removed from the key by subjecting the key to its Key Permutation.
4 The plaintext and key will process by following.
 The key is split into two 28 halves.
 Each half of the key is shifted (rotated) by one or two bits, depending on the
round.
 The halves are recombined and subject to a compression permutation to reduce
the key from 56 bits to 48 bits. This compressed keys used to encrypt this round’s
plaintext block.
 The rotated key halves from step 2 are used in next round.
 The data block is split into two 32-bit halves.

6
  One half is subject to an expansion permutation to increase its size to 48 bits.
 Output of step 6 is exclusive-OR with the 48- it compressed key from step 3.
 Output of step 7 is fed into an S-box, which substitutes key bits and reduces the
48-bit block back down to 32-bits.
 Output of step 8 is subject to a P-box to permute the bits.
 The output from the P-box is exclusive-OR with other half of the data block. k.
 The two data halves are swapped and become the next round’s input.

1.8 PROPOSED SYSTEM

In this paper, we propose an optimized VLSI implementation of encryption and

decryption system using hamming code algorithm. In the present field of communication has got
many applications, and in every field the data is encoded at the transmitter and transfer on a
communication channel and receive at the receiver after data is decoded. During the broadcast of
data it might get degraded because of some noise on the channel. So it is crucial for the receiver
to have some function which can recognize and correct the error in the received data. Hamming
code is one of such forward error correcting code which has got many applications. In this paper
the algorithm for hamming code is discussed and then implementation of it in Verilog is done to
get the results. Hamming code is an upgrading over parity check method. Here a code is
implemented in Verilog in which 8-bit of information data is transmitted with 4-redundancy bits.
In order to do that the proposed method uses a Field Programmable Gate Array (FPGA). It is
known that FPGA provides quick implementation and fast hardware verification. It gives
facilities of reconfiguring the design construct unlimited number of times.

The proposed design will work in error detection and correction using crypto system. The
Advanced Encryption Standard (AES) based on the Rijndael algorithm is an efficient
cryptographic technique that includes generation of ciphers for encryption and inverse ciphers
for decryption. Higher security and speed of encryption /decryption is ensured by operations like
Sub Bytes(S-box) and Inverse Sub Byte operation, Mix Column and Inverse Mix Column
operations are designed as Look Up Tables (LUTs). In encryption side error detection and
correction will be done. Its gives more security mainly in wireless communication system,
Hardware implementation of cryptographic algorithms are physically secure than software

7
implementations since outside attackers cannot modify them. In order to achieve higher
performance in today’s heavily loaded communication networks hardware implementation is a
wise choice in terms of better speed and security.

This project explains the implementation of data encryption and decryption algorithm
using hamming code and arithmetic operations with the help of Verilog HDL. As the days are
passing the old algorithms are not remained so strong cryptanalyst are familiar with them.
Hamming code is one of forward error correcting code which has got many applications. In this
paper hamming code algorithm was discussed and the implementation of it was done with
arithmetic operations. For high security some arithmetic operations are added with hamming
code process. A 8-bit data will be encrypted as 26-bit and using decryption process again we will
receives 8-bit original data.

Fig1.1: Block Diagram of Hamming Code Data Encryption and Decryption System

8
 CHAPTER 2

PROJECT DESCRIPTION

2.1 Proposed Circuit of Hamming Encoder and Decoder

Proposed circuits of hamming code are designed for 9 bit data word. Thus we require 4
parity bits to form 13 bit code word. There has an encoder and a decoder in the proposed circuit
to encode and decode the data for error detection and correction.

2.1.1 Encoder Circuit

Data word is applied as an input in the encoder circuit which performs XOR operations
on the given data word and thus the required parity bits are generated from the parity generator.
Parity bits and data bits together form the code word. An encoder circuit of hamming code for 9
bit data word is shown below.

Fig. 2.1 Encoder Circuit of Hamming Code for 9-Bit Data

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2.2. Decoder Circuit

In the decoder circuit, code word is applied as input. Then check bits are generated by the
checker bit generator to check the parity bits. These check a bit locates the error in the code word
by means of decoder circuit. The Output of decoder enables a demultiplexer which is connected
to the input code words. If no error occurs then the select line of demultiplexer flows the input
form line I0 and the I1 is set to logic ‘1’. So from the logic OR gate we can obtain the data. Now
if an error occur then the select line of the demultiplexer flows the code word from line I1 and I0
is set to logic ‘0’. Thus inverting the bits, the error bit is corrected and thus we can obtain the
error free data. A decoder circuit of hamming code for 9 bit data word is also shown below

Fig. 2.2 Decoder Circuit of Hamming Code for 9-Bit Data

2.3 System model and operation

This encryption and decryption process is divided in to two parts. In first part the 8-bit
data and key will be converted in to 9-bit data. For this we are using the arithmetic operation
addition between 8-bit data and key. 8-bit key will be converted in to 9-bit key by performing ex-
or operation between the key bits. In second step the 9-bit addition data and key data will be
converted in to 13-bit data using the hamming code process. Finally these two 13-bit data will be
clubbed to form a 26-bit data. This final encrypted 26-bit data will be transmitted. In this 26 bit a

10
0 to 12 bits are key and 13 to 26 bits are data. Figure 4 shows the encryption process. Figure 5
shows the decryption process. This system will receive total 26-bit encrypted data. First it will
check the whether the received data is free of error or not. If there is not error in the data then
next step will start. In first step total 26-bit data will be divided into two 13-bit data i.e. 13-bit
information data and 13-bit key, by using hamming code technique we will get a 9-bit
information data and 9-bit key. In second step 8-bit key will be subtracted from 9-bit information
data.

8-bit data 8-bit key

xor
Add 9-Bit data 9- Bit key
datadata
er
Hamming Hamming
encoder encoder
13-bit 13-Bit
data key

26-bit data
Fig. 2.3 encryption process

11
 Fig.2.3 Data encryption process
Transmitted data(26-Bit)

Splitting

13-Bit data 13-Bit key

Hamming Hamming
decoder decoder

9-Bit data
9-Bit key data

8-Bit key Subtract or

XOR
Original data

Received
data 8-Bit key data

Fig .2.4 data decryption process

2.4 Data encryption

2.4.1 Definition of Data encryption
Data encryption translates data into another form, or code, so that only people with access
to a secret key (formally called a decryption key) or password can read it. Encrypted data
is commonly referred to as cipher text, while unencrypted data is called plaintext. Currently,
encryption is one of the most popular and effective data security methods used by organizations.

12
Two main types of data encryption exist - asymmetric encryption, also known as public-key
encryption, and symmetric encryption.

2.4.2 The Primary Function of Data Encryption

The purpose of data encryption is to protect digital data confidentiality as it is stored on

computer systems and transmitted using the internet or other computer networks. The outdated
data encryption standard (DES) has been replaced by modern encryption algorithms that play a
critical role in the security of IT systems and communications. These algorithms provide
confidentiality and drive key security initiatives including authentication, integrity, and non-
repudiation. Authentication allows for the verification of a message’s origin, and integrity
provides proof that a message’s contents have not changed since it was sent. Additionally, non-
repudiation ensures that a message sender cannot deny sending the message.

2.4.3 The Process of Data Encryption

Data, or plaintext, is encrypted with an encryption algorithm and an encryption key. The
process results in cipher text, which only can be viewed in its original form if it is decrypted with
the correct key. Symmetric-key ciphers use the same secret key for encrypting and decrypting a
message or file. While symmetric-key encryption is much faster than asymmetric encryption, the
sender must exchange the encryption key with the recipient before he can decrypt it. As
companies find themselves needing to securely distribute and manage huge quantities of keys,
most data encryption services have adapted and use an asymmetric algorithm to exchange the
secret key after using a symmetric algorithm to encrypt data.

On the other hand, asymmetric cryptography sometimes referred to as public-key

cryptography, uses two different keys, one public and one private. The public key, as it is named,
may be shared with everyone, but the private key must be protected. The Rivest-Sharmir-
Adleman (RSA) algorithm is a cryptosystem for public-key encryption that is widely used to
secure sensitive data, especially when it is sent over an insecure network like the internet. The
RSA algorithm’s popularity comes from the fact that both the public and private keys can
encrypt a message to assure the confidentiality, integrity, authenticity, and non-reputability of
electronic communications and data through the use of digital signatures

13
2.4.4 Data Encryption Solutions

Data protection solutions for data encryption can provide encryption of devices, email,
and data itself. In many cases, these encryption functionalities are also met with control
capabilities for devices, email, and data. Companies and organizations face the challenge of
protecting data and preventing data loss as employees use external devices, removable media,
and web applications more often as a part of their daily business procedures. Sensitive data may
no longer be under the company’s control and protection as employees copy data to removable
devices or upload it to the cloud. As a result, the best data loss prevention solutions prevent data
theft and the introduction of malware from removable and external devices as well as web and
cloud applications. In order to do so, they must also ensure that devices and applications are used
properly and that data is secured by auto-encryption even after it leaves the organization.

As we mentioned, email control and encryption is another critical component of a data

loss prevention solution. Secure, encrypted email is the only answer for regulatory compliance, a
remote workforce, BYOD, and project outsourcing. Premier data loss prevention solutions allow
your employees to continue to work and collaborate through email while the software and tools
proactively tag, classify, and encrypt sensitive data in emails and attachments. The best data loss
prevention solutions automatically warn, block, and encrypt sensitive information based on
message content and context, such as user, data class, and recipient.

While data encryption may seem like a daunting, complicated process, data loss
prevention software handles it reliably every day. Data encryption does not have to be something
your organization tries to solve on its own. Choose top data loss prevention software that offers
data encryption with device, email, and application control and rest assured that your data is safe.

We propose an optimized VLSI implementation of encryption and decryption system

using hamming code algorithm. In the present field of communication has got many applications,
and in every field the data is encoded at the transmitter and transfer on a communication channel
and receive at the receiver after data is decoded. During the broadcast of data it might get
degraded because of some noise on the channel. So it is crucial for the receiver to have some
function which can recognize and correct the error in the received data. Hamming code is one of

14
such forward error correcting code which has got many applications. In this paper the algorithm
for hamming code is discussed and then implementation of it in Verilog is done to get the results.
Hamming code is an upgrading over parity check method. Here a code is implemented in Verilog
in which 9-bit of information data is transmitted with 4-redundancy bits.

2.5 Data decryption

Decryption is the process of taking encoded or encrypted text or other data and
converting it back into text that you or the computer can read and understand. This term could be
used to describe a method of un-encrypting the data manually or with un-encrypting the data
using the proper codes or keys.
Data may be encrypted to make it difficult for someone to steal the information. Some
companies also encrypt data for general protection of company data and trade secrets. If this data
needs to be viewable, it may require decryption. If a decryption pass code or key is not available,
special software may be needed to decrypt the data using algorithms to crack the decryption and
make the data readable.

2.5.1 Definition of Decryption

Decryption is the process of transforming data that has been rendered unreadable through
encryption back to its unencrypted form. In decryption, the system extracts and converts the
garbled data and transforms it to texts and images that are easily understandable not only by the
reader but also by the system. Decryption may be accomplished manually or automatically. It
may also be performed with a set of keys or passwords.

One of the foremost reasons for implementing an encryption-decryption system is

privacy. As information travels over the World Wide Web, it becomes subject to scrutiny and
access from unauthorized individuals or organizations. As a result, data is encrypted to reduce
data loss and theft. Some of the common items that are encrypted include email messages, text
files, images, user data and directories. The person in charge of decryption receives a prompt or
window in which a password may be entered to access encrypted information.

Hamming codes are the most widely used linear block codes. Typically, a Hamming code
is defined as (2n - 1, 2n - n - 1), where:

 n is equal to the number of overhead bits.

15
  2n - 1 is equal to the block size.

 2n - n - 1 is equal to the number of data bits in the block.

All Hamming codes can detect three errors and one correct one. Common hamming code
sizes are (7, 4), (15, 11), and (31, 26). All have the same hamming distance. The hamming
distance and the hamming weight are useful in encoding. When the hamming distance is known,
the capability of a code to detect and correct errors can be determined.

In the data transmission side, this system allows only a 8-bit input data by using this input
data a 9-bit Code data bits will be generated and it will added with 4 bit input data, lastly 13 bit
hamming coded data will come out.

In the receiving face, a 8-bit check data (A) will be generated by using the receiving 13-
bit hamming code data. If A = “01101111” received data is correct and system will decoded
original transmitted 9-bit word data from the received 13-bit hamming code bits. This is shown
in the equations from 6 to 8. If there is only one bit error in the received 13-bit hamming code
„A‟ will show some value with respect to this value, appropriate one hamming code data bit
logic will toggle (0 to 1 or 1 to 0). Error detection and correction of hamming code data using
error detection data bits. From this corrected 13-bit hamming code data, system will generate
original transmitted 9-bit data.

Hamming codes are valid only when the hamming distance between the bits is less then
or equal to one. By contrast, the simple parity code cannot correct errors, and can only detect an
odd number of errors. They are the type of binary codes. The idea of hamming distance is the
central concept in coding the error control. The hamming distance between the two words (of the
same size) is the number of differences between the corresponding bits. The hamming distance
can easily be found if we apply the Xor operation on the two words and count the number of 1s
in the result. The hamming distance is a value always greater Than Zero. If we find the hamming
distance between any two words it will be the result of the Xoring of the two bits. Like the
hamming distance between d(000,011) is 2 because 000 xor 011 is 011(two 1s) and the hamming
distance between d(10101,11110) is 3 because 10101 xor 11110 is 01011(three 1s).

Hamming code method works only on two methods (even parity, odd parity) for
generating redundancy bits. The number of redundancy bits are generated using a formula. The
number of redundancy depends on the number of information data bits.

16
 The formula is: 2^r = D+r+1………………………………………………... (1)

Here, r = number of redundancy bits.

D = number of information data bits.

If we calculate the number of redundancy bits for An 9 bit of information then it comes to
be 4 redundancy bit. Redundancy bits are those extra bits which are required to detect and
correct errors. The redundancy bits are added to the information bit at the transmitter and
removed at the receiver. The receiver is able to detect the error and correct it because of the
redundancy bits. Hamming codes are used as forward error correcting codes in the Bluetooth
standard, and to protect data stored in semiconductor memories. Hamming codes are generally
used in computing, telecommunication, and other applications including data compression, and
turbo codes. They are also used for low cost and low power applications.

17
 CHAPTER 3

TOOLS & SOFTWARE

3.1 XILINX ISE 13.1:

Xilinx is the most important tool and in this tool we can perform both simulation and
synthesis.

3.1.1 Simulation:

In this process we are going to verify our required output to get the simulation process
firstly we have to implement a top module (combination of all modules) and then in the
simulation behavior we can simulate the results.

3.1.2 Synthesis:

Synthesis process defines converting Verilog code into gate level which creates a net list.

3.1.3 Procedure:

 Click project navigator

 Create new project
 Selection of FPGA

Create new source

 Select source type (Verilog module)

 Coding
 Declaration of inputs and output
 Sources for implementation

Synthesize – XST

 Check syntax
 View design summary
 View RTL schematic

18
  View technology schematic
 Sources for behavioral simulation

Create new source

 Select source type(Verilog text fixture)

 Write test bench code
 Xilinx ISE simulator
 Behavioral check syntax
 Simulate behavioral model

3.1.4 Xilinx snapshots:

1.To create new project in xilinx we should open the filemenu,click on new project then
it will open the dialogbox as below in that typethe filename click on next

19
 2.Then it isplays one more dialogbox which will give us the specifications of the
project,click on next

3.Then it again displays a dialogue box as shown below with the created project
description and click finish to compelte the process of creating new project

20
 4.Now project with specifyed name is created then create the verilog files in the project.
To create filesr, right click on the project that will show options like as shown below

5.From the given options select new source then it diaplays dialogbox which is
containing of list of fileformat now we want to create verlogfile so select veilog module,and give
the name to the file. Then click on next

21
 6.Then it will ask us to select inputs,outputs and inouts. We can specify our inputs and
outputs here else we may also specify as part of programme depend upon the user requirement,
click on next

7.It will again displays a dilagbox by fiving details of filename etc, click on next

22
 8. It will open a whitespace in the project window containing filename the double click
on the file name so that it will displays respective file window, where we should write the code

9.After completion writing code select the file name and click on synthesis which will
check for errors, if there are any errors in syntax or design errors are checked and shown in the
below of file widow

23
 10.After sucessful synthesis we should have to create tesh bench file with extension as
test,for that again riht click on the file name as shown below,give filename

11. If there are list files then select file for which we are creating the test bench. Click on
next

24
 12. It again gives a testbench file in the project window, then give reqired inputs

13. select simulation from the view bar in the project window above the hiearchy
window as follows.

25
 14. Double click on Ism Simulator it will expand as follows click on behavioral check
syntax and it will check for syntax errors in test bench file

15. Click on simulate behavioral model, it will displays wave form for in response to the
inputs given in the test bench file

26
 16. That wave form window having option to zoom out, zoom in to analyze the wave
form clearly in order to understand behavior of design

3.2 LANGUAGES

Verilog HDL is one of the two most common Hardware Description Languages (HDL)
used by integrated circuit (IC) designers.. HDL’s allows the design to be simulated earlier in the
design cycle in order to correct errors or experiment with different architectures. Designs
described in HDL are technology-independent, easy to design and debug, and are usually more
readable than schematics, particularly for large circuits.
Verilog is used to describe the any digital logic circuit is an interconnection of ports. The
modeling techniques are
 Structural
 Behavioral
 Dataflow.

27
3.3 MODELING TECHNIQUES
3.3.1 DATA FLOW:
In this model we will describe the components directly by the relation between them.
Module and1_gate (input a, b, output c);
Assign c=a & b;
endmodule
Module which denotes the connection between different elements inside of it. The
module name is and gate which is having inputs and outputs are declared as in the parenthesis.
The assign statement is a keyword which denotes performs the operation specified. Then
it will store the value in the left hand side operand. Endmodule statement denotes that
completion of module
3.3.2 BEHAVIORAL:
This is the modeling technique which is used to define the component without knowing
it. We can model the behavior. We will design the component by its behavior only. The below
program models a circuit which is having the behavior as shown below.
Module ha( input a,b, output c,d);
always@(a,b)
begin
if(a==0 &&b==0)
c=1;d=0
elseif(a==0 && b==1)
c=1;d=0;
elseif(a==1&&b==0)
c=0; d=1;
end
endmodule
The always keyword indicates a free-running process. This indicates that zero running
simulator. Once an always block has reached its end, it is rescheduled (again).
Parameters in the Parenthesis is called sensitivity list. The sensitivity list which indicates when
inputs are evaluated then always block will be executed.

28
The if else statement is similar like as in C. When the respective statement is correct
corresponding results will be executed.
3.3.3 STRUCTURAL MODELING:
This is used to design a complex modules using simple sub module of it. The sub
modules or the components which can be used frequently in the larger programs. This techniques
will make complex programs yet simple design.
Module ha(input a,b, output s,c);
Assign c=a&b;
Assign s=a^b;
End module

Module fa(input u,v,w, output x,y);

Wire s1,c1;
Ha n1(a,b,s1,c1);
Ha n2( s1,w,x,c2);
or(y,c1,c2);
endmodule
The above module is shown here is with the name ha is half adder. The module can be
called into another program module “fa”. To facilitate this option we should write both the
programs in single project. Then only we will write the program in structural model

3.4 MODULES

In Verilog, circuit components are designed inside a module. Modules can contain both
structural and behavioral statements. Structural statements represent circuit components like
logic gates, counters, and microprocessors. Behavioral level statements are programming
statements that have no direct mapping to circuit components like loops, if-then statements, and
stimulus vectors which are used to exercise a circuit. Below code shows an example of a circuit
and a test bench module. A module starts with the keyword module followed by an optional
module name and an optional port list. The key word endmodule ends a module.

`timescale 1ns / 1ps

29
//create a NAND gate out of an AND and an Invertor
modulesome_logic_component (c, a, b);
// declare port signals
output c;
input a, b;
// declare internal wire
wire d;
//instantiate structural logic gates
and a1(d, a, b); //d is output, a and b are inputs
not n1(c, d); //c is output, d is input
endmodule
//test the NAND gate
moduletest_bench; //module with no ports
reg A, B;
wire C;
//instantiate your circuit
some_logic_component S1(C, A, B);

//Behavioral code block generates stimulus to test circuit

initial
begin
A = 1'b0; B = 1'b0;
#50 $display("A = %b, B = %b, Nand output C = %b \n", A, B, C);
A = 1'b0; B = 1'b1;
#50 $display("A = %b, B = %b, Nand output C = %b \n", A, B, C);
A = 1'b1; B = 1'b0;
#50 $display("A = %b, B = %b, Nand output C = %b \n", A, B, C);
A = 1'b1; B = 1'b1;
#50 $display("A = %b, B = %b, Nand output C = %b \n", A, B, C);
end
endmodule

30
3.5 STRUCTURAL DESIGN WITH GATE AND DELAY OPERATOR

Verilog defines some basic logic gates as part of the language. In Figure 1, module
some_logic_component instantiates two gate primitives: the not gate and the andgate. The output
of the gate is the first parameter, and the inputs are the rest of the parameters. These primitives
are scalable so you can get multiple input gates just by adding inputs into the parameter list. For
example:

nand a1(out1, in1, in2); //2-input NAND gate

nand a2(out1, in1, in2, in3, in4, in5); //5-input NAND gate
By default the timing delay for the gate primitives is zero time. You can define the
rising delay, falling delay using the #(rise, fall) delay operator. And for tri-state gates you can
also define the turn-off delay (transition to high impedance state Z) by using the #(rise, fall, off)
delay operator.

For example
notif0 #(10,11,27) inv2(c,d,control) //rise=10, fall=11, off=27(not if control=0)
nor #(10,11) nor1(c,a,b); //rise=10, fall=11 (nor gate)
xnor #(10) xnor1(i,g,h); //rise=10, fall=10 (xnor gate)

Also each of the 3 delays can be defined to have minimum, typical, and a maximum
value using the a colon to separate the values like 8:10:12 instead of 10 in the above examples.
At run time, the Verilog simulator looks for to see if the + mindelay, + typdelay, or +
maxdelay option has been defined so that it will know which of the 3 time values to use. In
VeriLogger these options are set using the Project > Project Preferences menu. If none of the
options are specified then the typical value is used.

// min: typ: max values defined for the (rise, fall) delays
or #(8:10:12, 10:11:13) or1(c,a,b);

The delay operator has one subtle side effect: it swallows narrow input pulses. Normally,
the delay operator causes the output response of a gate to be delayed a certain amount of time.

31
However if the input pulse width is shorter than the overall delay of the gate then the change will
not be shown on the output. Here is a list of logic primitives defined for Verilog

Gate Parameter List Examples

scalable, requires at and a1(C,A,B);nand na1(out1,in1,in2,in3,in4);nor #(5)

nand nor and least 2 inputs(output, n1(D,A,B);//delay = 5 time unitsxor #(3,4,5)
or xorxnor input1, input2, � , x1(E,A,B);//rise,fall,offdelaysnor #(3:4:5)
inputx) n2(F,A,B);//min:typ:max of delays

not buf (output, input) not inv1(c,a);

control signal active

notif0bufif0 low(output, input, notif0 inv2(c,a, control);
control)

control signal active

notif1bufif1 high(output, input, not inv1(c,a, control);
control)

Table 3.1 list of logic primitives

3.6 STRUCTURAL DESIGN WITH ASSIGNMENT STATEMENTS

If you have a lot of random logic, the gate primitives of the previous section are tedious
to use because all the internal wires must be declared and hooked up correctly. Sometimes it is
easier to just describe a circuit using a single Boolean equation. In Verilog, Boolean equations

32
which have similar timing properties as the gate primitives are defined using a continuous
assignment statement. For example, the following code excerpt from Figure 1:

wire d;
and a1(d, a, b);
not n1(c, d);

can be replaced with one statement:

assign c = !(a && b); //notice that wire d was not used here

Assignments can also be made during the declaration of a wire. In this case the assign keyword is
implicitly assumed to be there for example:

wire d;
assign d = a || b; //continuous assignment

wire d = a || b; //implicit continuous assignment

By default the timing delay for assignment statements is zero time. You can define a
propagation delay using the #delay operator just like we did for the gate primitives. The
following examples have the exact same timing.

wire c;
assign #5 c = a && b; //delay in the continuous assignment

wire #5 c = a && b; //delay in the implicit assignment

wire #5 c; //delay in the wire declaration

assign c = a && b;

To demonstrate the pulse swallowing effect of the delays operator, consider the following
scenario. In the above examples, if input a changed value at time 10 (and held its value for at
least 5 time units), then the output c would change values at time 15. If input a had a value pulse

33
that was shorter then the propagation delay of the assignment then the value on a would not be
passed to the output. The delay operator can also use the full rise, fall, and off delays and each
delay can have a minimum: typical: maximum value. The following is a valid line of code,and
#(8:10:12, 10:11:13, 26:27:29) a1(c,a,b); //min:typ:max of (rise,fall,off)

3.7 STRUCTURAL DESIGN

By default the timing inside a module is controlled by the module itself. However,
modules can be defined to have parameterized delays similar to the #(4, 5) delay operator used
with gate primitives. In the module definition, use the parameter keyword to create delay
variables. Parameters can also be used to change other scalar values in the module. When the
module is instantiated then you can choose to override the delay values using the #(parameter)
notation. For example:

modulesome_logic_component (c, a, b);

... //some code
parameter and Delay = 2; //default delays
parameterinv Delay = 2;
and #andDelay a1(d, a, b); //using parameter delays
not #invDelay n1(c, d);
endmodule

moduletest_bench; //module with no ports

...
some_logic_component#(5,4) S3(E, A, B); //override and Delay=5, invDelay=4
some_logic_component #(5) S2(D, A, B); //override and Delay=5, invDelay=2
some_logic_component S1(C, A, B); //uses default delays
....
endmodule

Modules also support a special kind of timing called specify blocks which can be used in
conjunction with SDF analyzers. Specify blocks also support continuous setup and hold
checking.

34
3.8 BEHAVIORAL DESIGN WITH INITIAL AND ALWAYS BLOCKS

Behavioral code is used to describe circuits at a more abstract level then the structural
level statements we have studied. All Behavioral code occurs within either an initial block or in
an always block. A module can contain several initial and always blocks. These behavioral
blocks contain statements that control simulation time, data flow statements (like if-then and case
statements), and blocking and non-blocking statements.

 An initial block executes once during a simulation. Initial blocks are usually used to
initialize variables and to describe stimulus waveforms which exercise which drive the
simulation.
 An always block continuously repeats its execution during a simulation. Always blocks
usually contain behavioral code that models the actual circuit operation.

During a simulation each always and each initial block begin to execute at time zero. Each
block executes concurrently with each structural statement and all the other behavioral blocks.
The following example shows a behavioral SRAM model. The initial block sets the memory
cells to zero at startup. The always block executes each time there is a change on the write
control line, the chip select line, or the address bus. As an exercise, copy and paste this code into
a Verilog file and write a test bench to exercise the model. If you are using VeriLogger Pro then
you can draw a test bench.

//SRAM Model
modulesram(CSB,WRB,ABUS,DATABUS);
input CSB; // active low chip select
input WRB; // active low write control
input [11:0] ABUS; // 12-bit address bus
inout [7:0] DATABUS; // 8-bit data bus
//** internal signals
reg [7:0] DATABUS_driver;
wire [7:0] DATABUS = DATABUS_driver;
reg [7:0] ram[0:4095]; // memory cells

35
integeri;

initial //initialize all RAM cells to 0 at startup

begin
DATABUS_driver = 8'bzzzzzzzz;
for (i=0; i< 4095; i = i + 1)
ram[i] = 0;
end
always @(CSB or WRB or ABUS)
begin
if (CSB == 1'b0)
begin
if (WRB == 1'b0) //Start: latch Data on rising edge of CSB or WRB
begin
DATABUS_driver<= #10 8'bzzzzzzzz;
@(posedge CSB or posedge WRB);
$display($time," Writing %m ABUS=%b DATA=%b",ABUS,DATABUS);
ram[ABUS] = DATABUS;
end
if (WRB == 1'b1) //Reading from sram (data becomes valid after 10ns)
begin
#10 DATABUS_driver= ram[ABUS];
$display($time," Reading %m ABUS=%b DATA=%b",ABUS,DATABUS_driver);
end
end
else //sram unselected, stop driving bus after 10ns
begin
DATABUS_driver<= #10 8'bzzzzzzzz;
end
end
endmodule

36
3.9 STRUCTURAL DATA TYPES: WIRE AND REG

Verilog supports structural data types called nets which model hardware connections
between circuit components. The two most common structural data types are wire and reg.
The wire nets act like real wires in circuits. The reg type hold their values until another value is
put on them, just like a register hardware component. The declarations for wire and reg signals
are inside a module but outside any initial or always block. The initial state of
a reg is x unknown, and the initial state of a wire is z. Ports: Modules communicate with each
other through ports, the signals listed in the parameter list at the top of the module. Ports can be
of type in, out, and inouts. Here are 3 simplistic rules for matching the structural data type to the
type of port:

 Use reg as the outputs of Behavioral blocks. If you us a wire then the value will never be
seen by other blocks.
 Use wire for all inputs, inouts, and most outputs of Structural elements.
 If you need a special strength type operation use special net keyword wand, wor, tir,
triand, trior, trireg.

3.10 BEHAVIORAL DATA TYPES: INTEGER, REAL, AND TIME

The types in integer and real are convenient data types to use for counting in behavioral
code blocks. These data types act like their counter parts in other programming languages. If you
eventually plan to synthesize your behavioral code then you would probably want to avoid using
these data types because they often synthesize large circuits. The data type time can hold a
special simulator value called simulation time which is extracted from the system function $time.
The time information can be used to help you debug your simulations.

..... //code fragment from inside a module

integeri, y;

real a;

37
real b = 3.5;

real c = 4;

timesimulationTime;

initial

begin

y = 4;

i = 5 + y;

c = c + 3.5;

a = 5.3e4;

simulationTime = $time;

$display("integer y = %d, i = %f \n", y, i);

$display("reals c = %f, a = %e, b= %g \n", c, a, b);

$display("time simulationTime = %t \n", simulationTime);

End

3.11 NUMBER SYNTAX

Numbers in Verilog are in the following format The size is always specified as a decimal
number. If no is specified then the default size is at least 32bits and may be larger depending on
the machine. Valid base formats are 'b , 'B , 'h , 'H 'd , 'D , 'o , 'O for binary, hexadecimal,
decimal, and octal. Numbers consist of strings of digits (0-9, A-F, a-f, x, X, z, Z). The X's mean
unknown, and the Z's mean high impedance If no base format is specified the number is assumed
to be a decimal number. Some examples of valid numbers are:

38
 2'b10 // 2 bit binary number

'b10 // at least a 32-bit binary number

3 // at least a 32-bit decimal number

8'hAf // 8-bit hexadecimal

-16'd47 // negative decimal number

3.12BEHAVIORAL DESIGN WITH BLOCKING AND NON-BLOCKING

STATEMENTS

There are 2 kinds of assignment statements: blocking using the = operator, and non-
blocking using the <= operator. Blocking assignments act like sequential code statements and
execute when they are called. Non-blocking schedule events to happen at some time in the
future. This can be confusing because lines that appear after a non-blocking statement execute at
the same time as the non-blocking statement. Here are some examples:

#5 x = 1'b0; // blocks for 5 time units, applies value to x, then next line goes

y = 1'b1; // blocks, sets y to 1 now, then next statement goes

y <= #3 1'b0; // evaluates now, schedules apply y=0 in 3 time units, and next line goes

#5 x <= y; // waits for 5 time units, evaluates,

// schedules apply at end of current time, and next line goes

The following two code blocks are not equivalent:

// Section 1: Blocking statements execute sequentially

#5 a = b; // waits 5 time units, evaluates and applies value to a

c = d; // evaluates and applies value to c

39
// Section 2: Non-Blocking statements execute concurrently

#5 a <= b; // waits 5 time units, evaluates, schedules apply for end of current time

c <= d; // evaluate, schedules apply for end of current time

// At end of current time both a and c receive their values

3.13ARRAYS, VECTORS, AND MEMORIES

Verilog supports three similar data structures called Arrays, Vectors, and Memories.
Arrays are used to hold several objects of the same type. Vectors are used to represent multi-bit
busses. And Memories are arrays of vectors which are accessed similar to hardware memories.
Read the following examples to determine how to reference and use the different data structures.

//*** Arrays for integer, time, reg, and vectors of reg ***************

integeri[3:0]; //integer array with a length of 4

time x[20:1]; //time array with length of 19

reg r[7:0]; //scalar reg array with length of 8

c = r[3]; //the 3rd reg value in array r is assigned to c

//*** Vectors are multi-bit words of type reg or net (wire)************

reg [7:0] MultiBitWord1; // 8-bit reg vector with MSB=7 LSB=0

wire [0:7] MultiBitWord2; // 8-bit wire vector with MSB=0 LSB=7

reg [3:0] bitslice;

40
reg a; // single bit vector often referred to as a scalar

.... //referencing vectors

a = MultiBitWord1[3]; //applies the 3rd bit of MultiBitWord1 to a

bitslice = MultiBitWord1[3:0]; //applies the 3-0 bits of MultiBitWord1 to bitslice

//*** Memories are arrays of vector reg ********************************

reg [7:0] ram[0:4095]; // 4096 memory cells that are 8 bits wide

//code excerpt from Chapter 2 SRAM model

input [11:0] ABUS; // 12-bit address bus to access all 4096 memory cells

inout [7:0] DATABUS; // 8-bit data bus to wite into and out of a memory cell

reg [7:0] DATABUS_driver;

wire [7:0] DATABUS = DATABUS_driver; //inout must be driven by a wire

....

for (i=0; i< 4095; i = i + 1) // Setting individual memory cells to 0

ram[i] = 0;

end

ram[ABUS] = DATABUS; //writing to a memory cell

DATABUS_driver = ram[ABUS]; //reading from a memory cell

41
3.14 OPERATORS

Here is a small selection of the Verilog Operators which look similar but have different
effects. Logical Operators evaluate to TRUE or FALSE. Bitwise operators act on each bit of the
operands to produce a multi-bit result. Unary Reduction operators perform the operation on all
bits of the operand to produce a single bit result.

Operator Name Examples

! logical negation

~ bitwise negation

&& logical and

& bitwise and abus = bbus&cbus;

& reduction and abit = &bbus;

~& reduction nand

|| logical or

| bitwise or

| reduction or

~| reduction nor

^ bitwise xor

^ reduction xor

~^ ^~ bitwise xnor

~^ ^~ reduction xnor

== logical equality, result may be unknown if x or z in the input if (a == b)

=== logical equality including x and z

!= logical inequality, result may be unknown if x or z in the input

!== logical inequality including x and z

> relational greater than

42
>> shift right by a number of positions a = shiftvalue>> 2;

>= relational greater than or equal

< relational less than

<< shift left by a number of positions

<= relational less than or equal if (a <= b)

Table 3.2. list of operators and its description

43
 CHAPTER 4

SIMULATION RESULTS

4.1 Encryption

Fig 4.1 encryption process output

8 bit data is added with 8 bit key by using the adder circuit. This gives the 9 bit data. This
9 bit data is passed through hamming encoder in which 4 parity bits are added. Thus, output of
hamming encoder is 13 bit data. On the other hand,8 bit key is converted into 9bit key y using
the xor gate. This 9 bit after passing through hamming encoder gives 13bit key .this 13bit data
and 13bit key are combined to give 26bit cipher text.

Example : 8 bit data= 0 0 1 1 0 0 1 1

8 bit key= 1 1 0 0 1 1 0 0
+
9 bit data = 0 1 1 1 1 1 1 1 1
Hamming encoder for data:

44
D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 1 1 1 1 1 1 1

2^k > n+k+1

2^4 > 9+4+1

16 13

4-parity bits are added

2^n positions = 1, 2, 4, 8

D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 1 1 1 1 P4 1 1 1 P3 1 P2 P1

P1 = d0 xor d1 xor d3 xor d4 xor d6 = 1 xor 1 xor 1 xor 1 xor 1 = 1

P2= d0 xor d2 xor d3 xor d5 xor d6 = 1 xor 1 xor 1 xor 1 xor 1 = 1

P3= d1 xor d2 xor d3 xor d7 xor d8 = 1 xor 1 xor 1 xor 1 xor 0 = 0

P4= d4 xor d5 xor d6 xor d7 xor d8 = 1 xor 1 xor 1 xor 1 xor 0 = 0

Hamming encoder:

13 bit data = 0 1 1 1 1 0 1 1 1 0 1 1 1

Key conversion:

8bit key = 1 1 0 0 1 1 0 0

9bit key = 1 0 1 0 1 0 1 0 0

Hamming encoder for key:

4parity bits are added since 24>9+4+1.

P1 = k0 xor k1 xor k3 xor k4 xor k6 = 0 xor 0 xor 0 xor 1 xor = 1

45
P2 = k0 xor k2 xor k3 xor k5 xor k6 = 0 xor 1 xor 0 xor 0 xor 1 = 0

P3 = k1 xor k2 xor k3 xor k7 xor k8 = 0 xor 1 xor 0 xor 0 xor 1 = 0

P4= k4 xor k5 x0r k6 xor k7 xor k8 xor = 1 xor 0 xor 1 xor 1 xor = 1

Hamming key.

10100001

So, 26 bit cipher text = 0 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 1 0 1 0 0 0 0 1.

4.2 Decryption

Fig 4.2 decryption process output

In this, 26 bit cipher text is split into 13bit data and 13bit key. This 13bit data is passed
through hamming decoder in which parity bits are removed by using decoder and de multiplexer.
Which gives 9bit data .the 8bit key is subtracted from this 9bit to give the original data. On the
other hand, this 13bit key is passed through hamming decoder in which parity bits are removed
by using decoder and de multiplexer which gives 9bit key. The original key is obtained by
performing xor operation between individual 9bit key. Which gives original key

46
 01111011101111010110100001 split into

0111101110111 1010110100001

By using error detection circuit

For 13 bit data

d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0

0 1 1 1 1 0 1 1 1 0 1 1 1

C1=d0 xor d2 xor d4 xor d6 xor d8 xor d10 xor d12=1 xor 1 xor 1 xor 1 xor 1 xor 1 xor 0=0

C2=d1 xor d2 xor d5 xor d6 xor d9 xor d10=1 xor 1 xor 1 xor 1 xor 1 xor 1=0

C3=d3 xor d4 xor d5 xor d6 xor d11 xor d12=0 xor 1 xor 1 xor 1 xor 1 xor 0=0

C4=d7 xor d8 xor d9 xor d10 xor d11 xor d12=0 xor 1 xor 1 xor 1 xor 1 xor 0=0

C4C3C2C1=0000

This means data received is appropriate as checker bits are 0000.

This checker bits are given to 4:16 decoder

Y0=1

0. Y1=1

0 4:16 •

Decoder •

0 •

•
47
Y15=0
We are ignoring y0; y14; y15 so the remaining information is given to the selection line of 1:2
demultiplexer. As all are 0, it selects the 1st line. It selects the only necessary information and
neglects the parity bits.

Thus the output is 00110011.

For key

k12 k11 k10 k9 k8 k7 k6 k5 k4 k3 k2 k1 k0

1 0 1 0 1 1 0 1 0 0 0 0 1

C1=k0 xor k2 xor k4 xor k6 xor k8 xor k10 xor k12=1 xor 0 xor 0 xor 0 xor 1 xor 1 xor 1=0

C2=k1 xor k2 xor k5 xor k6 xor k9 xor k10=0 xor 0 xor 1 xor 0 xor 0 xor 1=0

C3=k3 xor k4 xor k5 xor k6 xor k11 xor k12=0 xor 0 xor 1 xor 0 xor 0 xor 1=0

C1=k7 xor k8 xor k9 xor k10 xor k11 xor k12=1 xor 1 xor 0 xor 1 xor 0 xor 1=0

Thus the key received is appropriate as checker bits are 0000.

This checker bits are given to 4:16 decoder .

We are ignoring y0; y14; y15 so the remaining information is given to the selection line of 1:2
demultiplexer. As all are 0, it selects the 1st line. It selects the only necessary information and
neglects the parity bits.

Thus the output is 101010100.

This output is given to key deconversion circuit.

Example : 9-bit key 1 0 1 0 1 0 1 0 0

8-bit key 1 1 0 0 1 1 0 0

Thus the output is 11001100.

48
4.3 Encryption and Decryption

Fig 4.3 combine encryption & decryption process output

Transmit the encrypted data to the receiver it decrypted the data message will sent the
receiver

49
4.4ADVANTAGES

4.4.1 Low power consumption

By using instantiation technique we will implement this project. So modules will be decreased
and automatically power will be reduced.

4.4.2 Occupies less area

In VLSI, we will implementing the blocks and it’s area is very less, if we will do fabrication or
dump in a FPGA the maximum area will reduced.

4.4.3 High speed

The speed of the system is very high and execution time is less for this system.

50
4.5APPLICATIONS

4.5.1 For security

In cryptography data is hiding by means of steganography. It is process of hiding

information. The data can be hided beside image, video and audio. We need to secure the data
with high protection. We can use this technique using Verilog.

4.5.2 Image steganography

Least Significant Technique is use for image steganography. If the LSB is changed then that
causes the small change to the original value. If the image is of 24 -bit, there is 3 byte of data to
present RGB values for every pixel which shows that the 3 bits can be stored in every pixel.

4.5.3 Audio steganography

In case of audio steganography, the data will be hide at the back of audio file to hide the data
behind audio is somewhat matches to image steganography. In audio steganography the data is
hiding behind samples. For samples, the sampling technique is follow.

51
 CHAPTER -5

5.1 CONCLUSION

We have implemented the VLSI design of hamming code data encryption and decryption
design. The present data encryption and decryption process is implemented using Verilog HDL
with the help of Xilinx ISE Design Suite. In this project we implemented hamming code in
Verilog language and shown the output results. Hamming codes have improved the way of
communication by detecting and correcting errors.

5.2 FUTURE SCOPE

In this project we designed encryption and decryption standard for 8 bits of transmission
data with 8 bits key. In future we will implement this standard with increase the size of
transmission data. We will design it as an IP core and it will act like high security to the signals.

52
 REFERENCES

1. VinodShokeen, NiranjanYadav, “Encryption and Decryption Technique for Message

Communication”, International Journal of Electronics & Communication Technology,
Vol. 2, Issue 2, June 2011, pp. 80-83.
2. Obaida Mohammad Awad Al-Hazaimeh, “A New Approach For Complex Encrypting
and Decrypting Data”, International Journal Of Computer Networks & Communications
(IJCNC) Vol.5, No.2, March 2013, pp. 95- 103.
3. Prakash G L ,Dr. Manish Prateek and Dr. Inder Singh, “Data Encryption and Decryption
Algorithms using Key Rotations for Data Security in Cloud System”, International
Journal Of Engineering And Computer Science, Volume 3 Issue 4 April, 2014 Page No.
5215-522

Reference books
1. Brute Force: Cracking the Data Encryption Standard, By Matt Curtin
2. Differential Cryptanalysis of the Data Encryption Standard, By Eli Biham, Adi Shamir
3. Computer security and the data encryption standard ..., Volume 500, Issues 1-6
4. By United States Civil Service Commission, United States. National Bureau of Standards
5. Validating the correctness of hardware implementations of the NBS data By Jason Gait,
6. United States. National Bureau of Standards
7. Applied Cryptography: Protocols, Algorithms, and Source Code in C, by Bruce Schneier.
8. Understanding Cryptography: A Textbook for students and Practitioners by christof Paar,
Jan Pelzl, Bart Preneel
9. Public-Key Cryptography Arto Salomaa, second edition, Springer, 1996. ISBN 3-540-
61356-0.

Reference web sites

RC6 http://www.rsasecurity.com/rsalabs/faq/3-6-4.html
Secure Sockets Layer (SSL) http://home.netscape.com/eng/ssl3/draft302.txt

53
 APPENDIX
SOURCE CODE.
module adder9_bit(d,k,s);
input [7:0] d,k;
output [8:0] s;
wire [6:0] c;
fa a1(d[0],k[0],1'b0,s[0],c[0]);
fa a2(d[1],k[1],c[0],s[1],c[1]);
fa a3(d[2],k[2],c[1],s[2],c[2]);
fa a4(d[3],k[3],c[2],s[3],c[3]);
fa a5(d[4],k[4],c[3],s[4],c[4]);
fa a6(d[5],k[5],c[4],s[5],c[5]);
fa a7(d[6],k[6],c[5],s[6],c[6]);
fa a8(d[7],k[7],c[6],s[7],s[8]);
endmodule
module ham_encoder1(d,he);
input [8:0] d;
wire [3:0] p;
wire [12:0] w;
output [12:0] he;
xor a1(w[0],d[0],d[1]);
xor a2(w[1],w[0],d[3]);
xor a3(w[2],w[1],d[4]);
xor a4(w[3],w[2],d[6]);
xor a5(p[0],w[3],d[8]);
xor a6(w[4],d[0],d[2]);
xor a7(w[5],w[4],d[3]);
xor a8(w[6],w[5],d[5]);
xor a9(p[1],w[6],d[6]);
xor a10(w[7],d[1],d[2]);
xor a11(w[8],w[7],d[3]);
xor a12(w[9],w[8],d[7]);
xor a13(p[2],w[9],d[8]);
xor a14(w[10],d[4],d[5]);
xor a15(w[11],w[10],d[6]);
xor a16(w[12],w[11],d[7]);
xor a17(p[3],w[12],d[8]);
buf a18(he[0],p[0]);
buf a19(he[1],p[1]);
buf a20(he[2],d[0]);
buf a21(he[3],p[2]);
buf a22(he[4],d[1]);
buf a23(he[5],d[2]);
buf a24(he[6],d[3]);
buf a25(he[7],p[3]);
buf a26(he[8],d[4]);
buf a27(he[9],d[5]);
buf a28(he[10],d[6]);

54
buf a29(he[11],d[7]);
buf a30(he[12],d[8]);
endmodule
module key_convrsion(key,y);
input [7:0] key;
output [8:0] y;
buf a1(y[0],key[0]);
xor a2(y[1],key[1],key[0]);
xor a3(y[2],key[2],key[1]);
xor a4(y[3],key[3],key[2]);
xor a5(y[4],key[4],key[3]);
xor a6(y[5],key[5],key[4]);
xor a7(y[6],key[6],key[5]);
xor a8(y[7],key[7],key[6]);
xor a9(y[8],key[7],key[0]);
endmodule
module combine(x,y,z);
input [12:0] x,y;
output [25:0] z;
reg[25:0] z;
always@(*)
begin
z[0]<=y[0];
z[1]<=y[1];
z[2]<=y[2];
z[3]<=y[3];
z[4]<=y[4];
z[5]<=y[5];
z[6]<=y[6];
z[7]<=y[7];
z[8]<=y[8];
z[9]<=y[9];
z[10]<=y[10];
z[11]<=y[11];
z[12]<=y[12];
z[13]<=x[0];
z[14]<=x[1];
z[15]<=x[2];
z[16]<=x[3];
z[17]<=x[4];
z[18]<=x[5];
z[19]<=x[6];
z[20]<=x[7];
z[21]<=x[8];
z[22]<=x[9];
z[23]<=x[10];
z[24]<=x[11];
z[25]<=x[12];
end
endmodule
module encryption(data,key,encry_out);
input [7:0] data,key;
wire [8:0] adder_data,key_conversion;

55
wire [12:0] he_data,he_key;
output [25:0] encry_out;
adder9_bit a1(data,key,adder_data);
ham_encoder1 a2(adder_data,he_data);
key_convrsion a3(key,key_conversion);
ham_encoder1 a4(key_conversion,he_key);
combine a5(he_data,he_key,encry_out);
endmodule
module splitting(z,x,y);
input [25:0] z;
output [12:0] x,y;
reg [12:0] x,y;
always@(z)
begin
y[0]<=z[0];
y[1]<=z[1];
y[2]<=z[2];
y[3]<=z[3];
y[4]<=z[4];
y[5]<=z[5];
y[6]<=z[6];
y[7]<=z[7];
y[8]<=z[8];
y[9]<=z[9];
y[10]<=z[10];
y[11]<=z[11];
y[12]<=z[12];
x[0]<=z[13];
x[1]<=z[14];
x[2]<=z[15];
x[3]<=z[16];
x[4]<=z[17];
x[5]<=z[18];
x[6]<=z[19];
x[7]<=z[20];
x[8]<=z[21];
x[9]<=z[22];
x[10]<=z[23];
x[11]<=z[24];
x[12]<=z[25];
end
endmodule
module ham_decoder(d,dec_data);
input [12:0] d;
output [8:0] dec_data;
wire [15:0] y;
wire [3:0] c;
wire [25:0] w;
error_detection a1(d,c);
dec4_16 a2(c,y);
demux a3(d[0],y[1],w[0],w[1]);
demux a4(d[1],y[2],w[2],w[3]);
demux a5(d[2],y[3],w[4],w[5]);

56
demux a6(d[3],y[4],w[6],w[7]);
demux a7(d[4],y[5],w[8],w[9]);
demux a8(d[5],y[6],w[10],w[11]);
demux a9(d[6],y[7],w[12],w[13]);
demux a10(d[7],y[8],w[14],w[15]);
demux a11(d[8],y[9],w[16],w[17]);
demux a12(d[9],y[10],w[18],w[19]);
demux a13(d[10],y[11],w[20],w[21]);
demux a14(d[11],y[12],w[22],w[23]);
demux a15(d[12],y[13],w[24],w[25]);
buf a16(dec_data[0],w[4]);
buf a17(dec_data[1],w[8]);
buf a18(dec_data[2],w[10]);
buf a19(dec_data[3],w[12]);
buf a20(dec_data[4],w[16]);
buf a21(dec_data[5],w[18]);
buf a22(dec_data[6],w[20]);
buf a23(dec_data[7],w[22]);
buf a24(dec_data[8],w[24]);
endmodule
module dec4_16(a,y);
input [3:0] a;
output [15:0] y;
reg [15:0] y;
always@(a)
begin
case(a)
4'b0000:begin y<=16'b0000000000000001;end
4'b0001:begin y<=16'b0000000000000010;end
4'b0010:begin y<=16'b0000000000000100;end
4'b0011:begin y<=16'b0000000000001000;end
4'b0100:begin y<=16'b0000000000010000;end
4'b0101:begin y<=16'b0000000000100000;end
4'b0110:begin y<=16'b0000000001000000;end
4'b0111:begin y<=16'b0000000010000000;end
4'b1000:begin y<=16'b0000000100000000;end
4'b1001:begin y<=16'b0000001000000000;end
4'b1010:begin y<=16'b0000010000000000;end
4'b1011:begin y<=16'b0000100000000000;end
4'b1100:begin y<=16'b0001000000000000;end
4'b1101:begin y<=16'b0010000000000000;end
4'b1110:begin y<=16'b0100000000000000;end
4'b1111:begin y<=16'b1000000000000000;end
endcase
end
endmodule
module demux(i,s,y0,y1);
input i,s;
output y0,y1;
reg y0,y1;
always@(*)
begin
if(s==0)

57
 begin
y0<=i;
end
else
begin
y1<=i;
end
end
endmodule
module subtractor_9bit(a,b,d);
input [8:0] a,b;
output [8:0] d;
wire [17:0] w,c;
xor a1(w[0],1'b1,b[0]);
xor a2(w[1],1'b1,b[1]);
xor a3(w[2],1'b1,b[2]);
xor a4(w[3],1'b1,b[3]);
xor a5(w[4],1'b1,b[4]);
xor a6(w[5],1'b1,b[5]);
xor a7(w[6],1'b1,b[6]);
xor a8(w[7],1'b1,b[7]);
xor a9(w[8],1'b1,b[8]);
fa a10(a[0],w[0],1'b1,d[0],c[9]);
fa a11(a[1],w[1],c[9],d[1],c[10]);
fa a12(a[2],w[2],c[10],d[2],c[11]);
fa a13(a[3],w[3],c[11],d[3],c[12]);
fa a14(a[4],w[4],c[12],d[4],c[13]);
fa a15(a[5],w[5],c[13],d[5],c[14]);
fa a16(a[6],w[6],c[14],d[6],c[15]);
fa a17(a[7],w[7],c[15],d[7],c[16]);
fa a18(a[8],w[8],c[16],d[8],c[17]);
endmodule
module sub_8bit(a,b,d);
input [7:0] a,b;
output [7:0] d;
wire [15:0] w,c;
xor a1(w[0],1'b1,b[0]);
xor a2(w[1],1'b1,b[1]);
xor a3(w[2],1'b1,b[2]);
xor a4(w[3],1'b1,b[3]);
xor a5(w[4],1'b1,b[4]);
xor a6(w[5],1'b1,b[5]);
xor a7(w[6],1'b1,b[6]);
xor a8(w[7],1'b1,b[7]);
fa a9(a[0],w[0],1'b1,d[0],c[8]);
fa a10(a[1],w[1],c[8],d[1],c[9]);
fa a11(a[2],w[2],c[9],d[2],c[10]);
fa a12(a[3],w[3],c[10],d[3],c[11]);
fa a13(a[4],w[4],c[11],d[4],c[12]);
fa a14(a[5],w[5],c[12],d[5],c[13]);
fa a15(a[6],w[6],c[13],d[6],c[14]);
fa a16(a[7],w[7],c[14],d[7],c[15]);
endmodule

58
module key_deconversion(key,y);
input [8:0] key;
output [7:0] y;
buf a1(y[0],key[0]);
xor a2(y[1],key[1],y[0]);
xor a3(y[2],key[2],y[1]);
xor a4(y[3],key[3],y[2]);
xor a5(y[4],key[4],y[3]);
xor a6(y[5],key[5],y[4]);
xor a7(y[6],key[6],y[5]);
xor a8(y[7],key[7],y[6]);
endmodule
module decryption(encry_out,data,key);
input [25:0] encry_out;
output [7:0] data,key;
wire [3:0] check_data,check_key;
wire [12:0] split_data,split_key;
wire [8:0] dec_data,dec_key;
splitting a1(encry_out,split_data,split_key);
error_detection a2(split_data,check_data);
ham_decoder a3(split_data,dec_data);
subtractor_9bit_final a4(dec_data,key,data);
error_detection a5(split_key,check_key);
ham_decoder a6(split_key,dec_key);
key_deconversion a7(dec_key,key);
endmodule

Encrypation&decrypation
module encry_decry(data,key,rx_data);
input [7:0] data,key;
output [7:0] rx_data;
wire [25:0] encry_out;
wire [7:0] key,rx_key;
encryption a1(data,key,encry_out);
decryption a2(encry_out,rx_data,rx_key);
endmodule

59
 Synthesis report
Release 14.7 - xst P.20131013 (nt64)

Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to xst/projnav.tmp

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.13 secs

--> Parameter xsthdpdir set to xst

Total REAL time to Xst completion: 0.00 secs

Total CPU time to Xst completion: 0.13 secs

--> Reading design: encry_decry.prj

TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

9) Final Report

9.1) Device utilization summary

9.2) Partition Resource Summary

9.3) TIMING REPORT

60
=====================================================================
====

* Synthesis Options Summary *

=====================================================================
====

---- Source Parameters

Input File Name : "encry_decry.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "encry_decry"

Output Format : NGC

Target Device : xa3s100e-4-vqg100

---- Source Options

Top Module Name : encry_decry

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

Safe Implementation : No

FSM Style : LUT

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

61
Decoder Extraction : YES

Priority Encoder Extraction : Yes

Shift Register Extraction : YES

Logical Shifter Extraction : YES

XOR Collapsing : YES

ROM Style : Auto

Mux Extraction : Yes

Resource Sharing : YES

Asynchronous To Synchronous : NO

Multiplier Style : Auto

Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 100000

Add Generic Clock Buffer(BUFG) : 24

Register Duplication : YES

Slice Packing : YES

Optimize Instantiated Primitives : NO

Use Clock Enable : Yes

Use Synchronous Set : Yes

Use Synchronous Reset : Yes

Pack IO Registers into IOBs : Auto

Equivalent register Removal : YES

62
---- General Options

Optimization Goal : Speed

Optimization Effort :1

Keep Hierarchy : No

Netlist Hierarchy : As_Optimized

RTL Output : Yes

Global Optimization : AllClockNets

Read Cores : YES

Write Timing Constraints : NO

Cross Clock Analysis : NO

Hierarchy Separator :/

Bus Delimiter : <>

Case Specifier : Maintain

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

Verilog 2001 : YES

Auto BRAM Packing : NO

Slice Utilization Ratio Delta :5

=====================================================================
====

=====================================================================
====

* HDL Compilation *

=====================================================================
====

63
Compiling verilog file "fa.v" in library work

Compiling verilog file "error_detection.v" in library work

Module <fa> compiled

Compiling verilog file "demux.v" in library work

Module <error_detection> compiled

Compiling verilog file "dec4_16.v" in library work

Module <demux> compiled

Compiling verilog file "subtractor_9bit_final.v" in library work

Module <dec4_16> compiled

Compiling verilog file "splitting.v" in library work

Module <subtractor_9bit_final> compiled

Compiling verilog file "key_deconversion.v" in library work

Module <splitting> compiled

Compiling verilog file "key_convrsion.v" in library work

Module <key_deconversion> compiled

Compiling verilog file "ham_decoder.v" in library work

Module <key_convrsion> compiled

Compiling verilog file "combine.v" in library work

Module <ham_decoder> compiled

Compiling verilog file "adder9_bit.v" in library work

Module <combine> compiled

Compiling verilog file "encryption.v" in library work

Module <adder9_bit> compiled

Compiling verilog file "decryption.v" in library work

Module <encryption> compiled

64
Compiling verilog file "encry_decry.v" in library work

Module <decryption> compiled

Module <encry_decry> compiled

No errors in compilation

Analysis of file <"encry_decry.prj"> succeeded.

=====================================================================
====

* Design Hierarchy Analysis *

=====================================================================
====

Analyzing hierarchy for module <encry_decry> in library <work>.

Analyzing hierarchy for module <encryption> in library <work>.

Analyzing hierarchy for module <decryption> in library <work>.

Analyzing hierarchy for module <adder9_bit> in library <work>.

Analyzing hierarchy for module <ham_encoder1> in library <work>.

Analyzing hierarchy for module <key_convrsion> in library <work>.

Analyzing hierarchy for module <combine> in library <work>.

Analyzing hierarchy for module <splitting> in library <work>.

65
Analyzing hierarchy for module <error_detection> in library <work>.

Analyzing hierarchy for module <ham_decoder> in library <work>.

Analyzing hierarchy for module <subtractor_9bit_final> in library <work>.

Analyzing hierarchy for module <key_deconversion> in library <work>.

Analyzing hierarchy for module <fa> in library <work>.

Analyzing hierarchy for module <error_detection> in library <work>.

Analyzing hierarchy for module <dec4_16> in library <work>.

Analyzing hierarchy for module <demux> in library <work>.

=====================================================================
====

* HDL Analysis *

=====================================================================
====

Analyzing top module <encry_decry>.

Module <encry_decry> is correct for synthesis.

Analyzing module <encryption> in library <work>.

Module <encryption> is correct for synthesis.

66
Analyzing module <adder9_bit> in library <work>.

Module <adder9_bit> is correct for synthesis.

Analyzing module <fa> in library <work>.

Module <fa> is correct for synthesis.

Analyzing module <ham_encoder1> in library <work>.

Module <ham_encoder1> is correct for synthesis.

Analyzing module <key_convrsion> in library <work>.

Module <key_convrsion> is correct for synthesis.

Analyzing module <combine> in library <work>.

Module <combine> is correct for synthesis.

Analyzing module <decryption> in library <work>.

Module <decryption> is correct for synthesis.

Analyzing module <splitting> in library <work>.

Module <splitting> is correct for synthesis.

Analyzing module <error_detection> in library <work>.

Module <error_detection> is correct for synthesis.

Analyzing module <ham_decoder> in library <work>.

67
Module <ham_decoder> is correct for synthesis.

Analyzing module <dec4_16> in library <work>.

Module <dec4_16> is correct for synthesis.

Analyzing module <demux> in library <work>.

Module <demux> is correct for synthesis.

Analyzing module <subtractor_9bit_final> in library <work>.

Module <subtractor_9bit_final> is correct for synthesis.

Analyzing module <key_deconversion> in library <work>.

Module <key_deconversion> is correct for synthesis.

=====================================================================
====

* HDL Synthesis *

=====================================================================
====

Performing bidirectional port resolution...

Synthesizing Unit <ham_encoder1>.

Related source file is "hamming_encoder.v".

Found 4-bit xor2 for signal <p>.

Found 13-bit xor2 for signal <w>.

Unit <ham_encoder1> synthesized.

Synthesizing Unit <key_convrsion>.

68
 Related source file is "key_convrsion.v".

Found 8-bit xor2 for signal <y<8:1>>.

Unit <key_convrsion> synthesized.

Synthesizing Unit <combine>.

Related source file is "combine.v".

Unit <combine> synthesized.

Synthesizing Unit <fa>.

Related source file is "fa.v".

Found 1-bit xor2 for signal <s>.

Found 1-bit xor2 for signal <cout$xor0000> created at line 25.

Unit <fa> synthesized.

Synthesizing Unit <splitting>.

Related source file is "splitting.v".

Unit <splitting> synthesized.

Synthesizing Unit <error_detection>.

Related source file is "error_detection.v".

Found 4-bit xor2 for signal <c>.

Found 17-bit xor2 for signal <w>.

Unit <error_detection> synthesized.

Synthesizing Unit <key_deconversion>.

Related source file is "key_deconversion.v".

WARNING:Xst:647 - Input <key<8>> is never used. This port will be preserved and left
unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of
this sub-block is preserved.

Found 7-bit xor2 for signal <y<7:1>>.

69
Unit <key_deconversion> synthesized.

Synthesizing Unit <dec4_16>.

Related source file is "dec4_16.v".

Found 1-of-16 decoder for signal <y>.

Summary:

inferred 1 Decoder(s).

Unit <dec4_16> synthesized.

Synthesizing Unit <demux>.

Related source file is "demux.v".

WARNING:Xst:737 - Found 1-bit latch for signal <y0>. Latches may be generated from
incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD
designs, as they may lead to timing problems.

WARNING:Xst:737 - Found 1-bit latch for signal <y1>. Latches may be generated from
incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD
designs, as they may lead to timing problems.

Unit <demux> synthesized.

Synthesizing Unit <adder9_bit>.

Related source file is "adder9_bit.v".

Unit <adder9_bit> synthesized.

Synthesizing Unit <ham_decoder>.

Related source file is "ham_decoder.v".

WARNING:Xst:646 - Signal <y<15:14>> is assigned but never used. This unconnected signal
will be trimmed during the optimization process.

WARNING:Xst:646 - Signal <y<0>> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

WARNING:Xst:646 - Signal <w<25>> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

70
WARNING:Xst:646 - Signal <w<23>> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

WARNING:Xst:646 - Signal <w<21>> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

WARNING:Xst:646 - Signal <w<19>> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

WARNING:Xst:646 - Signal <w<17>> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

WARNING:Xst:646 - Signal <w<15:13>> is assigned but never used. This unconnected signal
will be trimmed during the optimization process.

WARNING:Xst:646 - Signal <w<11>> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

WARNING:Xst:646 - Signal <w<9>> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

WARNING:Xst:646 - Signal <w<7:5>> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

WARNING:Xst:646 - Signal <w<3:0>> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

Unit <ham_decoder> synthesized.

Synthesizing Unit <subtractor_9bit_final>.

Related source file is "subtractor_9bit_final.v".

WARNING:Xst:646 - Signal <c<17:16>> is assigned but never used. This unconnected signal
will be trimmed during the optimization process.

WARNING:Xst:1780 - Signal <c<7:0>> is never used or assigned. This unconnected signal will
be trimmed during the optimization process.

Unit <subtractor_9bit_final> synthesized.

Synthesizing Unit <encryption>.

Related source file is "encryption.v".

71
Unit <encryption> synthesized.

Synthesizing Unit <decryption>.

Related source file is "decryption.v".

WARNING:Xst:646 - Signal <check_key> is assigned but never used. This unconnected signal
will be trimmed during the optimization process.

WARNING:Xst:646 - Signal <check_data> is assigned but never used. This unconnected signal
will be trimmed during the optimization process.

Unit <decryption> synthesized.

Synthesizing Unit <encry_decry>.

Related source file is "encry_decry.v".

WARNING:Xst:646 - Signal <rx_key> is assigned but never used. This unconnected signal will
be trimmed during the optimization process.

Unit <encry_decry> synthesized.

=====================================================================
====

HDL Synthesis Report

Macro Statistics

# Latches : 52

1-bit latch : 52

# Decoders :2

1-of-16 decoder :2

# Xors : 167

1-bit xor2 : 167

72
=====================================================================
====

=====================================================================
====

* Advanced HDL Synthesis *

=====================================================================
====

WARNING:Xst:524 - All outputs of the instance <a3> of the block <demux> are unconnected in
block <ham_decoder>.

This instance will be removed from the design along with all underlying logic

WARNING:Xst:524 - All outputs of the instance <a4> of the block <demux> are unconnected in
block <ham_decoder>.

This instance will be removed from the design along with all underlying logic

WARNING:Xst:524 - All outputs of the instance <a6> of the block <demux> are unconnected in
block <ham_decoder>.

This instance will be removed from the design along with all underlying logic

WARNING:Xst:524 - All outputs of the instance <a10> of the block <demux> are unconnected
in block <ham_decoder>.

This instance will be removed from the design along with all underlying logic

WARNING:Xst:1290 - Hierarchical block <a2> is unconnected in block <a2>.

It will be removed from the design.

WARNING:Xst:1290 - Hierarchical block <a15> is unconnected in block <a3>.

It will be removed from the design.

WARNING:Xst:1290 - Hierarchical block <a17> is unconnected in block <a4>.

It will be removed from the design.

WARNING:Xst:1290 - Hierarchical block <a5> is unconnected in block <a2>.

It will be removed from the design.

73
WARNING:Xst:1290 - Hierarchical block <a15> is unconnected in block <a6>.

It will be removed from the design.

=====================================================================
====

Advanced HDL Synthesis Report

Macro Statistics

# Latches : 36

1-bit latch : 36

# Decoders :2

1-of-16 decoder :2

# Xors : 167

1-bit xor2 : 167

=====================================================================
====

=====================================================================
====

* Low Level Synthesis *

=====================================================================
====

WARNING:Xst:2677 - Node <a2/a3/a15/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a3/a14/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a3/a13/y1> of sequential type is unconnected in block

<encry_decry>.

74
WARNING:Xst:2677 - Node <a2/a3/a12/y1> of sequential type is unconnected in block
<encry_decry>.

WARNING:Xst:2677 - Node <a2/a3/a11/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a3/a9/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a3/a8/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a3/a7/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a3/a5/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a6/a15/y0> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a6/a15/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a6/a14/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a6/a13/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a6/a12/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a6/a11/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a6/a9/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a6/a8/y1> of sequential type is unconnected in block

<encry_decry>.

WARNING:Xst:2677 - Node <a2/a6/a7/y1> of sequential type is unconnected in block

<encry_decry>.

75
WARNING:Xst:2677 - Node <a2/a6/a5/y1> of sequential type is unconnected in block
<encry_decry>.

Optimizing unit <encry_decry> ...

WARNING:Xst:1294 - Latch <a2/a3/a15/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a14/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a13/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a12/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a11/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a9/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a8/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a7/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a5/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a14/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a13/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a12/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a11/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a9/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a8/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a7/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a5/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a15/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a14/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a13/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a12/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a11/y0> is equivalent to a wire in block <encry_decry>.

76
WARNING:Xst:1294 - Latch <a2/a3/a9/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a8/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a7/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a3/a5/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a14/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a13/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a12/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a11/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a9/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a8/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a7/y0> is equivalent to a wire in block <encry_decry>.

WARNING:Xst:1294 - Latch <a2/a6/a5/y0> is equivalent to a wire in block <encry_decry>.

Optimizing unit <adder9_bit> ...

Optimizing unit <subtractor_9bit_final> ...

Mapping all equations...

Building and optimizing final netlist ...

Found area constraint ratio of 100 (+ 5) on block encry_decry, actual ratio is 1.

Final Macro Processing ...

=====================================================================
====

Final Register Report

Found no macro

=====================================================================
====

=====================================================================
====

77
* Partition Report *

=====================================================================
====

Partition Implementation Status

-------------------------------

No Partitions were found in this design.

-------------------------------

=====================================================================
====

* Final Report *

=====================================================================
====

Final Results

RTL Top Level Output File Name : encry_decry.ngr

Top Level Output File Name : encry_decry

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : No

Design Statistics

# IOs : 24

Cell Usage :

# IO Buffers : 16

# IBUF :8

# OBUF :8

=====================================================================
====

Device utilization summary:

78
---------------------------

Selected Device : xa3s100evqg100-4

Number of Slices: 0 out of 960 0%

Number of IOs: 24

Number of bonded IOBs: 16 out of 66 24%

---------------------------

Partition Resource Summary:

---------------------------

No Partitions were found in this design.

---------------------------

=====================================================================
====

TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT

GENERATED AFTER PLACE-and-ROUTE.

Clock Information:

------------------

No clock signals found in this design

Asynchronous Control Signals Information:

----------------------------------------

No asynchronous control signals found in this design

Timing Summary:

---------------

Speed Grade: -4

79
 Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 4.910ns

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

=====================================================================
====

Timing constraint: Default path analysis

Total number of paths / destination ports: 8 / 8

-------------------------------------------------------------------------

Delay: 4.910ns (Levels of Logic = 2)

Source: data<7> (PAD)

Destination: rx_data<7> (PAD)

Data Path: data<7> to rx_data<7>

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 1 1.218 0.420 data_7_IBUF (rx_data_7_OBUF)

OBUF:I->O 3.272 rx_data_7_OBUF (rx_data<7>)

----------------------------------------

Total 4.910ns (4.490ns logic, 0.420ns route)

(91.4% logic, 8.6% route)

=====================================================================
====

80
Total REAL time to Xst completion: 7.00 secs

Total CPU time to Xst completion: 6.87 secs

-->

Total memory usage is 291656 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 82 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

81