Fully Reused VLSI Architecture of FM0 / Manchester Encoding Using SOLS Technique For DSRC Applications Chapter-1

IMPLEMENTATION OF VLSI ARCHITECTURE OF FM0/MANCHESTER ENCODING
USING SOLS TECHNIQUE FOR DSRC APPLICATIONS
Fully Reused VLSI Architecture of FM0 / Manchester Encoding

Using SOLS Technique for DSRC Applications
Chapter-1
INTRODUCTION
The dedicated short-range communication (DSRC) [1] is a protocol for one- or two-way medium
range communication especially for intelligent transportation systems. The DSRC can be briefly
classified into two categories: automobile-to-automobile and automobile-to-roadside. In
automobile-to-automobile, the DSRC enables the message sending and broadcasting among
automobiles for safety issues and public information announcement [2], [3]. The safety issues
include blind-spot, intersection warning, inter cars distance, and collision-alarm Moreover, the
ETC can be extended to the payment for parking-service, and gas-refueling. Thus, the DSRC
system plays an important role in modern automobile industry. The upper and bottom parts are
dedicated for transmission and receiving, respectively.
This transceiver is classified into three basic modules: microprocessor, baseband

processing, and RF front-end. The microprocessor interprets instructions from media access
control to schedule the tasks of baseband processing and RF front-end. The baseband processing
is responsible for modulation, error correction, clock synchronization, and encoding. The RF
frontend transmits and receives the wireless signal through the antenna. The DSRC standards
have been established by several organizations in different countries. The data rate individually
targets at 500 kb/s, 4 Mb/s, and 27 Mb/s with carrier frequency of 5.8 and 5.9 GHz. The
modulation methods incorporate amplitude shift keying, phase shift keying, and orthogonal
frequency division multiplexing. Generally, the waveform of transmitted signal is expected to
have zero mean for robustness issue, and this is also referred to as dc-balance. The transmitted
signal consists of arbitrary binary sequence, which is difficult to obtain dc-balance. The purposes
of FM0 and Manchester codes can provide the transmitted The literature [4] proposes a VLSI
architecture of Manchester encoder for optical communications.
M.TECH(VLSI-SD) 1 ECE,CMREC
This design adopts the CMOS inverter and the gated inverter as the switch to construct
Manchester encoder. It is implemented by 0.35-μm CMOS technology and its operation
frequency is 1 GHz. The literature [5] further replaces the architecture of switch in [4] by the n
MOS device. It is realized in 90-nm CMOS technology, and the maximum operation frequency
is as high as 5 GHz. The literature [6] develops a high-speed VLSI architecture almost fully
reused with Manchester and Miller encodings for radio frequency identification (RFID)
applications. This design is realized in 0.35-μm CMOS technology and the maximum operation
frequency is 200 M Hz. The literature [7] also proposes a Manchester encoding architecture for
ultrahigh frequency (UHF) RFID tag emulator. This hardware architecture is conducted from the
finite state machine (FSM) of Manchester code, and is realized into field-programmable gate
array (FPGA) prototyping system. The maximum operation frequency of this design is about 256
M Hz. The similar design methodology is further applied to individually construct FM0 and
Miller encoders also for UHF RFID Tag emulator [8] . Its maximum operation frequency is
about 192 MHz. Furthermore, [9] combines frequency shift keying (FSK) modulation and
demodulation with Manchester codec in hardware realization.
VLSI DESIGN:
The company was founded in 1979, by a trio from Fairchild Semiconductor by way of Synertek
– Jack Balletto, Dan Floyd, and Gunnar Wetlesen – and by Doug Fairbairn of Xerox PARC and
Lambda (later VLSI Design) magazine. Alfred J. Stein became the CEO of the company in 1982.
Subsequently VLSI built its first fab in San Jose; eventually a second fab was built in San
Antonio, Texas. VLSI had its initial public offering in 1983, and was listed on the stock
market as (NASDAQ: VLSI). The company was later acquired by Philips and survives to this
day as part of NXP Semiconductors.
Figure 3.1 A VLSI VL82C106 Super I/O chip
The original business plan was to be a contract wafer fabrication company, but the venture
investors wanted the company to develop IC (Integrated Circuit) design tools to help fill the
foundry. Thanks to its Caltech and UC Berkeley students, VLSI was an important pioneer in
the electronic design automation (EDA) industry. It offered a sophisticated package of tools,
originally based on the 'lambda-based' design style advocated by Carver Mead and Lynn
Conway. VLSI became an early vendor of standard cell (cell-based technology) to the merchant
market in the early 1980s where the other ASIC-focused company, LSI Logic, was a leader
in gate arrays. Prior to VLSI's cell-based offering, the technology had been primarily available
only within large vertically integrated companies with semiconductor units such
as AT&T and IBM. VLSI's design tools included not only design entry and simulation but
eventually also cell-based routing (chip compiler), a data path compiler, SRAM and ROM
compilers, and a state machine compiler. The tools were an integrated design solution for IC
design and not just point tools, or more general purpose system tools. A designer could edit
transistor-level polygons and/or logic schematics, then run DRC and LVS, extract parasitics from
the layout and run Spice simulation, then back-annotate the timing or gate size changes into the
logic schematic database. Characterization tools were integrated to generate Frame Maker Data
Sheets for Libraries. VLSI eventually spun off the CAD and Library operation into Compass
Design Automation but it never reached IPO before it was purchased by Avanti Corp. VLSI's
physical design tools were critical not only to its ASIC business, but also in setting the bar for
the commercial electronic design automation (EDA) industry. When VLSI and its main ASIC
competitor, LSI Logic, were establishing the ASIC industry, commercially-available tools could
not deliver the productivity necessary to support the physical design of hundreds of ASIC
designs each year without the deployment of a substantial number of layout engineers. The
companies' development of automated layout tools was a rational "make because there's nothing
to buy" decision. The EDA industry finally caught up in the late 1980s when Tangent Systems
released its TanCell and TanGate products. In 1989, Tangent was acquired by Cadence Design
Systems (founded in 1988).
ENCODER AND DECODER:
1.1.1 ENCODER: In digital electronics, a decoder can take the form of a multiple-input,
multiple-output logic circuit that converts coded inputs into coded outputs, where the input and
output codes are different e.g. n-to-2n , binary-coded decimal decoders. Decoding is necessary in
applications such as data multiplexing, 7 segment display and memory address decoding. The
example decoder circuit would be an AND gate because the output of an AND gate is "High" (1)
only when all its inputs are "High." Such output is called as "active High output". If instead of
AND gate, the NAND gate is connected the output will be "Low" (0) only when all its inputs are
"High". Such output is called as "active low output". A slightly more complex decoder would be
the n-to-2n type binary decoders. These types of decoders are combinational circuits that convert
binary information from 'n' coded inputs to a maximum of 2n unique outputs. In case the 'n' bit
coded information has unused bit combinations, the decoder may have less than 2n outputs. 2-to-
4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.
The input to a decoder is parallel binary number and it is used to detect the presence of a
particular binary number at the input. The output indicates presence or absence of specific
number at the decoder input.
Table 1.1.1 encoder
Figure 1.1.1 Encoder
1.1.2 DECODER:
Combine two or more small decoders with enable inputs to form a larger decoder e.g. 3-to-8-line
decoder constructed from two 2-to-4-line decoders.
Decoder with enable input can function as de-multiplexer.
3:8 Decoder:
It uses all AND gates, and therefore, the outputs are active- high. For active- low outputs,
NAND gates are used. It has 3 input lines and 8 output lines. It is also called as binary to octal
decoder it takes a 3-bit binary input code and activates one of the 8(octal) outputs corresponding
to that code. The truth table is as follows:
Figure 1.1.2 Decoder
1.1.3 Octal to binary encoder:

Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3-to-8
decoder does. At any one time, only one input line has a value of 1. The figure below shows the
truth table of an Octal-to-binary encoder.
Table 1.1.3: Truth Table of octal to binary encoder

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are:
Y0 = I1 + I3 + I5 + I7
Y1= I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 +I7
Fig 1.1.3: Logic Diagram of octal to binary encoder
1.1.4 Priority encoder:

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller
number of outputs. The output of a priority encoder is the binary representation of the ordinal
number starting from zero of the most significant input bit. They are often used to control
interrupt requests by acting on the highest priority request. It includes priority function. If 2 or
more inputs are equal to 1 at the same time, the input having the highest priority will take
precedence. Internal hardware will check this condition and priority is set.
Table1.1.4: Truth Table of 4 bit priority encoder
Fig 1.1.4 : Logic Diagram of 4 bit priority encoder
IC 74148 is an 8-input priority encoder. 74147 is 10:4 priority encoder
1.1.5 Multiplexer:
In electronics, a multiplexer or MUX is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select
lines, which are used to select which input line to send to the output. An electronic multiplexer
can be considered as a multiple-input, single-output switch i.e. digitally controlled multi-position
switch. The digital code applied at the select inputs determines which data inputs will be
switched to output.
A common example of multiplexing or sharing occurs when several peripheral devices share a
single transmission line or bus to communicate with computer. Each device in succession is
allocated a brief time to send and receive data. At any given time, one and only one device is
using the line. This is an example of time multiplexing since each device is given a specific time
interval to use the line.
In frequency multiplexing, several devices share a common line by transmitting at different
frequencies.
Table 1. 5: Truth Table of 8:1 MUX
Fig 1.1.5: Logic Diagram of 8:1 MUX

1. 1.6 De-multiplexer:
A de multiplexer (or de-mux) is a device taking a single input signal and selecting one of many
data-output-lines, which is connected to the single input. A multiplexer is often used with a
complementary de multiplexer on the receiving end. A De-multiplexer is a single-input,
multiple-output switch. De-multiplexers take one data input and a number of selection inputs,
and they have several outputs. They forward the data input to one of the outputs depending on
the values of the selection inputs.
De multiplexers are sometimes convenient for designing general purpose logic, because if the de
multiplexer's input is always true, the de-multiplexer acts as a decoder. This means that any
function of the selection bits can be constructed by logically OR-ing the correct set of outputs.
Table1.1.6: Truth Table of 1:8 DEMUX
Figure 1.1.6 De-multiplexer
Forward Error Correction (FEC) schemes are an essential component of wireless communication
systems. Present wireless standards such as Third generation (3G) systems, GSM, 802.11A,
802.16 utilize some configuration of convolution coding. Convolution encoding with Viterbi
decoding is a powerful method for forward error correction. The Viterbi algorithm is the most
extensively employed decoding algorithm for convolutional codes which comprises of minimum
path and value calculation and retracing the path. The efficiency of error detection and correction
increases with constraint length. In this paper the convolutional encoder and viterbi decoder are
implemented on FPGA for constraint length of 9 and bit rate ½. Forward error correction (FEC)
codes have long been a powerful tool in the advancement of information storage and
transmission. By introducing meaningful redundancy into a stream of information, systems gain
the ability not only to detect data errors, but also to correct them. Convolution coding is a
popular error-correcting coding method used in digital communications. It is used in
communications such as satellite and space communication to improve communication
efficiency. To detect and correct errors occurred while transmitting digital data through a noisy
channel, the original data is Convolutionally encoded by using convolutional encoder. The
encoder adds some redundancy to the information and then transmits through a noisy channel.
The transmitted data is received at the receiver and is given to viterbi decoder. The viterbi
decoder evaluates the corrupted data and corrects the errors in the bit streams occurred during
transmission. Forward Error Correction is a process of error control for data transmission by
adding some redundant symbols to the transmitted information to facilitate error detection and
error correction at receiver end. Forward Error Correction (FEC) in digital communication
system improves the error detection as well as error correction capability of the system at the
cost of increased system complexity. Using FEC the need for retransmission of data can be
avoided. Hence, it is applied in situations where applied in situations where retransmissions are
relatively costly or impossible. FEC codes can be classified into two categories namely block
codes and convolution codes. Block codes work on fixed size blocks of bits where as
convolution codes work on sequential and as well as blocks of data. In this, the encoding
operation may be viewed as discrete time convolution of input sequence with the impulse
response of the encoder. Error detection and correction or error control is a technique that
enables reliable delivery of digital data over unreliable communication channels. Many
communication channels are subject to channel noise, and thus errors may be introduced during
transmission from the source to the receiver. Error detection techniques allow detecting such
errors, while error correction enables reconstruction of the original data. It consist of four blocks:
the branch metric unit (BMU), which computes metrics, the path metric unit (PMU), which
computes the path metric, the add–compare– select unit (ACSU), which selects the survivor
paths for each trellis state, also finds the minimum path metric of the survivor paths and the
survivor management unit (SMU), that is responsible for selecting the output based on the
minimum path metric.
The received data bits are given to the branch metric block which calculates the possible
branch metrics at that particular state. Any state from stage three in the trellis diagram can be
reached from two possible previous states thus two error metrics are obtained. The Add compare
select unit finds both the path metrics and compares, whichever is minimum that path metric is
chosen as the new path metrics. The new path metrics are stored in path metric unit. Above two
steps are repeated until the trellis ends and the entire path metric and next state metrics are
obtained. Using these above metrics the survivor path traces the optimum path from last values
of the next state matrix and then the data is decoded.
1.1.7 FLIP-FLOP:
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to
store state information. A flip-flop is a bi-stable multi vibrator. The circuit can be made to
change state by signals applied to one or more control inputs and will have one or two outputs. It
is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building
block of digital electronics systems used in computers, communications, and many other types of
systems. Flip-flops and latches are used as data storage elements. A flip-flop stores a
single bit (binary digit) of data; one of its two states represents a "one" and the other represents a
"zero". Such data storage can be used for storage of state, and such a circuit is described
as sequential logic. When used in a finite-state machine, the output and next state depend not
only on its current input, but also on its current state (and hence, previous inputs). It can also be
used for counting of pulses, and for synchronizing variably-timed input signals to some reference
timing signal.
Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-

triggered). Although the term flip-flop has historically referred generically to both simple and
clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for
discussing clocked circuits; the simple ones are commonly called latches.[1][2] Using this
terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch
is enabled it becomes transparent, while a flip flop's output only changes on a single type
(positive going or negative going) of clock edge.
The D ﬂip-ﬂop is widely used. It is also known as a "data" or "delay" flip-flop.
The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as
the rising edge of the clock). That captured value becomes the Q output. At other times, the
output Q does not change.[22][23] The D flip-flop can be viewed as a memory cell, a zero-order
hold, or a delay line.[citation needed]
Truth table:
Clock D Qnext
Rising edge 0 0
Rising edge 1 1
Non-Rising X Q
('X' denotes a Don't care condition, meaning the signal is irrelevant)
Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which
ignores the D and clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1
condition is resolved in D-type flip-flops. By setting S = R = 0, the flip-flop can be used as
described above. Here is the truth table for the others S and R possible configurations:
Inputs Outputs
S R D > Q Q'
0 1 X X 0 1
1 0 X X 1 0
1 1 X X 1 1
These flip-flops are very useful, as they form the basis for shift registers, which are an essential
part of many electronic devices. The advantage of the D flip-flop over the D-type "transparent
latch" is that the signal on the D input pin is captured the moment the flip-flop is clocked, and
subsequent changes on the D input will be ignored until the next clock event. An exception is
that some flip-flops have a "reset" signal input, which will reset Q (to zero), and may be either
asynchronous or synchronous with the clock.
The above circuit shifts the contents of the register to the right, one bit position on each active
transition of the clock. The input X is shifted into the leftmost bit position.
Classical positive-edge-triggered D flip-flop[edit]
1.1.7 A positive-edge-triggered D flip-flop
This circuit[24] consists of two stages implemented by SR NAND latches. The input stage (the
two latches on the left) processes the clock and data signals to ensure correct input signals for the
output stage (the single latch on the right). If the clock is low, both the output signals of the input
stage are high regardless of the data input; the output latch is unaffected and it stores the
previous state. When the clock signal changes from low to high, only one of the output voltages
(depending on the data signal) goes low and sets/resets the output latch: if D = 0, the lower
output becomes low; if D = 1, the upper output becomes low. If the clock signal continues
staying high, the outputs keep their states regardless of the data input and force the output latch
to stay in the corresponding state as the input logical zero (of the output stage) remains active
while the clock is high. Hence the role of the output latch is to store the data only while the clock
is low.
The circuit is closely related to the gated D latch as both the circuits convert the two D input
states (0 and 1) to two input combinations (01 and 10) for the output SR latch by inverting the
data input signal (both the circuits split the single D signal in two
complementary S and R signals). The difference is that in the gated D latch simple NAND
logical gates are used while in the positive-edge-triggered D flip-flop SR NAND latches are used
for this purpose. The role of these latches is to "lock" the active output producing low voltage (a
logical zero); thus the positive-edge-triggered D flip-flop can also be thought of as a gated D
latch with latched input gates.
1.1.8 Master–slave edge-triggered D flip-flop[edit]
1.1.8 A master–slave D flip-flop.
implementation of a master–slave D flip-flop that is triggered on the rising edge of the clock
A master–slave D flip-flop is created by connecting two gated D latches in series, and inverting
the enable input to one of them. It is called master–slave because the second latch in the series
only changes in response to a change in the first (master) latch.
For a positive-edge triggered master–slave D flip-flop, when the clock signal is low (logical 0)
the "enable" seen by the first or "master" D latch (the inverted clock signal) is high (logical 1).
This allows the "master" latch to store the input value when the clock signal transitions from low
to high. As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes low (1
to 0) and the value seen at the input to the master latch is "locked". Nearly simultaneously, the
twice inverted "enable" of the second or "slave" D latch transitions from low to high (0 to 1) with
the clock signal. This allows the signal captured at the rising edge of the clock by the now
"locked" master latch to pass through the "slave" latch. When the clock signal returns to low (1
to 0), the output of the "slave" latch is "locked", and the value seen at the last rising edge of the
clock is held while the "master" latch begins to accept new values in preparation for the next
rising clock edge.
By removing the leftmost inverter in the circuit at side, a D-type flip-flop that strobes on
the falling edge of a clock signal can be obtained. This has a truth table like this:
D Q > Qnext
0 X Falling 0
1 X Falling 1
A CMOS IC implementation of a "true single-phase edge-triggered flip-flop with reset"
1. 2. FM0 AND MANCHESTER ENCODING TECHNIQUES
1.2.1 FM0 encoding

FM0 encoding is also called as bi-phase space encoding scheme. In FM0 encoding, the signal to
be transmitted and done according (Figure 2), to the following rules, • It inverts the phase of the
base band signal at the boundary of each symbol. • For representing logic ‘0’ level, it inverts the
signal at the mid of the symbol. • For representing logic ‘1’ level, it constant voltage occupying
an entire bit window
Figure 1.2.1 FMO Encoding
1.2.2 Manchester Encoding
Manchester code be first developed by G.E.Thomas at 1949. It is also called as phase encoding
scheme. In Manchester encoding, the signal to be transmitted and done according (Figure 3) to
the following rules, • A ‘1’ is noted, when low to high transition occurs. • A ‘0’ is noted, when
high to low transition occurs.
Figure 1.2.2 Manchester Encoding

To make an analysis on hardware utilization of FM0 and Manchester encoders, the hardware
architectures of both are conducted first. As mentioned earlier, the hardware architecture of
Manchester encoding is as simple as a XOR operation. However, the conduction of hardware
architecture for FM0 is not as simple as that of Manchester. How to construct the hardware
architecture of FM0 encoding should start with the FSM of FM0 first. As shown in Fig. 5(a), the
FSM of FM0 code is classified into four states. A state code is individually assigned to each
state, and each state code consists of A and B, as shown in Fig. 2. According to the coding
principle of FM0, the FSM of FM0 is shown in Fig. 5(b). Suppose the initial state is S1, and its
state code is 11 for A and B, respectively. If the X is logic-0, the state-transition must follow both
rules 1 and 3. The only one next-state that can satisfy both rules for The hardware architecture of
Manchester encoding is as simple as XOR operation. However, the hardware architecture for
FM0 is not as simple as that of Manchester Initial hardware architecture of FM0 and Manchester
encoder is shown in the (Figure 5). The top part is the hardware architecture of FM0 encoder and
the bottom part is hardware architecture of Manchester encoder. The Qa and Qb store the state
code of the FM0 code. The Mux_1 is to switch Qa and Qb through selection of clock (CLK)
signal. The determination of which coding is adopted depends on the mode selection of Mx_2,
where the mode=0 is for FM0 code and mode=1 is for Manchester code.
• FM0 Encoding equation is T1 = CLKbar.Qa + CLK.Qb (1) • Manchester Encoding equation is

T2 = X ⊕ CLK = X.CLKbar +Xbar.CLK (2) The Finite State Machine (FSM) of FM0 encoding
has classified into four states are S0, S1, S2 and S3. The FSM of FM0 has conduct the state
diagram of each state, as shown in (Figure 6). From the state diagram, transition table to be
formed, as shown in Table.
the X of logic-0 is S3. If the X is logic-1, the state-transition must follow both rules 2 and 3. The
only one next-state that can satisfy both rules for the X of logic-1 is S4. Thus, the state-transition
of each state can be completely constructed. The FSM of FM0 can also conduct the transition
table of each state, as shown in Table II. A(t) and B(t) represent the discrete-time state code of
current-state at time instant t. Their previous-states are denoted as the A(t − 1) and the B(t − 1),
respectively. With this transition table, the Boolean functions
With both A(t) and B(t), the Boolean function of FM0 code is denoted as CLK A(t) + CLK B(t).
(4) With (1) and (4), the hardware architectures of FM0 and Manchester encoders are shown in
Fig. 6. The top part is the hardware architecture of FM0 encoder, and the bottom part is the
hardware architecture of Manchester encoder. As listed in (1), the Manchester encoder is as
simple as a XOR operation for X and CLK. Nevertheless, the FM0 encoding depends not only on
the X but also on the previous-state of the FM0 code. The DFFA and DFFB store the state code
of the FM0 code. The MUX−1 is to switch A(t) and B(t) through the selection of CLK signal.
Both A(t) and B(t) are realized by (2) and (3), respectively. The determination of which coding is
adopted depends on the Mode selection of the MUX−2, where the Mode = 0 is for FM0 code,
and the Mode = 1 is for Manchester code. To evaluate the hardware utilization, the hardware
utilization rate (HUR) is defined as The component is defined as the hardware to perform a
specific logic function, such as AND, OR, NOT, and flipflop. The active components mean the
components that work for FM0 or Manchester encoding. The total components are the number of
components in the entire hardware architecture no matter what encoding method is adopted. The
HUR For both encoding methods, the total components are 7, including MUX−2 to indicate
which coding method is activated. For FM0 encoding, the active components are 6, and its HUR
is 85.71%. For Manchester encoding, the active components are 2, comprising XOR−2 and
MUX−2, and its HUR is as low as 28.57%. On average, this hardware architecture has a poor
HUR of 57.14%, and almost half of total components are wasted. The transistor count of the
hardware architecture without SOLS technique is 98, where 86 transistors are for FM0 encoding
and 26 transistors are for Manchester coding. On average, only 56 transistors can be reused, and
this is consistent with its HUR. The coding-diversity between the FM0 and Manchester codes
seriously limits the potential to design a fully reused VLSI architecture. The purpose of SOLS
technique is to design a fully reused VLSI architecture for FM0 and Manchester encodings. The
SOLS technique is classified into two parts: area-compact retiming and balance logic-operation
sharing. Each part is individually described as follows. Finally, the performance evaluation of the
SOLS technique is given.
is stored into DFFA and DFFB. According to (2) and (3), the transition of state code only
depends on B(t − 1) instead of both A(t − 1) and B(t − 1). Thus, the FM0 encoding just requires a
single 1-bit flip-flop to store the B(t−1). If the DFFA is directly removed, a non synchronization
between A(t) and B(t) causes the logic fault of FM0 code. To avoid this logic-fault, the DFFB is
relocated right after the MUX−1, as shown in Fig. 7(b), where the DFFB is assumed to be
positive-edge triggered. At each cycle, the FM0 code, comprising A and B, is derived from the
logic of A(t) and the logic of B(t), respectively. The FM0 code is alternatively switched between
A(t) and B(t) through the MUX−1 by the control signal of the CLK. In Fig. 7(a), the Q of DFFB
is directly updated from the logic of B(t) with 1-cycle latency. In Fig. 7(b), when the CLK is
logic-0, the B(t) is passed through MUX−1 to the D of DFFB. Then, the upcoming positive-edge
of CLK updates it to the Q of DFFB. As shown in Fig. 8, the timing diagram for the Q of DFFB
is consistent whether the DFFB is relocated or not. Suppose the logic components of FM0
encoder are realized with the logic-family of static CMOS, and the total transistor count is shown
in Table IV. The transistor count of the FM0 encoding architecture without area-compact
retiming is 72, and that with area-compact retiming is 50. The area-compact retiming technique
reduces 22 transistors. Fig. 9. Concept of balance logic-operation sharing for FM0 and
Manchester encodings. (a) Manchester encoding in multiplexer. (b) Combines the logic
operations of Manchester and FM0 encodings. Fig. 10. Balance logic-operation sharing of A(t)
and X.
B. Balance Logic-Operation Sharing
As mentioned previously, the Manchester encoding can be derived from X ⊕ CLK, and it is also
equivalent to
X ⊕ CLK = X CLK + X CLK. (6)
This can be realized by the multiplexer, as shown in Fig. 9(a). It is quite similar to the Boolean
function of FM0 encoding in (4). By comparing with (4) and (6), the FM0 and Manchester logics
have a common point of the multiplexerlike logic with the selection of CLK. As shown in Fig.
9(b), the concept of balance logic-operation sharing is to integrate the X into A(t) and X into B(t),
respectively. The logic for A(t)/X is shown in Fig. 10. The A(t) can be derived from an inverter of
B(t − 1), and X is obtained by an inverter of X. The logic for A(t)/X can share the same inverter,
and then a multiplexer is placed before the inverter to switch the operands of B(t − 1) and X. The
Mode indicates either FM0 or Manchester encoding is adopted. The similar concept can be also
applied to the logic for B(t)/X, as shown in Fig. 11(a). Nevertheless, this architecture exhibits a
drawback that the XOR is only dedicated for FM0 encoding, and is not shared with Manchester
encoding. Therefore, the HUR of this architecture is certainly limited. The X can be also
interpreted as the X ⊕ 0, and thereby the XOR operation can be shared with Manchester and
FM0 encodings. As a result, the logic for B(t)/X is shown in Fig. 11(b), where the multiplexer
iresponsible to switch the operands of B(t−1) and logic-0. This architecture shares the XOR for
both B(t) and X, and thereby increases the HUR. Furthermore, the multiplexer in Fig. 11(b)
1.2.3 Miller Encoding Technique:
Miller encoding is also known as delay encoding. It can be used for higher operating frequency
and it is similar to Manchester encoding except that the transition occurs in the middle of an
interval when the bit is 1. While using the Miller delay, noise interference can be reduced.
The block diagram has a d flip flop, t flip flop, NOT gate, and XOR gate. Where the input is
A_in and CLK, then the output is a Miller output. For example, if the input is 0 and the clock,
given the XOR operation has done that, is A_in CLK , therefore 0 plus a positive edge clock
produces the output as 0. Given to d flip flop, the clock has inverted, and after that output is
given to t flip flop it inputs and flip flop output, which is 0. Then the TFF is toggle FF, which
produces the Miller output as 1.
1.2.3 Block Diagram Of Miller Encoding

Design of FMO Manchester and Miller in One Module:
From the previous logics of FMO/Manchester was taken as same architecture for this we add a
Miller Encoding by adding another MUX to it. SO the user can select the type of encoding he
wants with the Two selection lines. The selection truth table was shown below
Mode1 Mode2 Clear Output
0 0 1 FMO
1 0 0 Manchester
1 X X Miller
Table 1.2.3
Chapter-2
Literature survey
2.1 Dedicated Short-Range Communications (DSRC) Standards in the United
States:
Wireless vehicular communication has the potential to enable a host of new applications,
the most important of which are a class of safety applications that can prevent collisions and save
thousands of lives. The automotive industry is working to develop the dedicated short-range
communication (DSRC) technology, for use in vehicle-to-vehicle and vehicle-to-roadside
communication. The effectiveness of this technology is highly dependent on cooperative
standards for interoperability. This paper explains the content and status of the DSRC standards
being developed for deployment in the United States. Included in the discussion are the IEEE
802.11p amendment for wireless access in vehicular environments (WAVE), the IEEE 1609.2,
1609.3, and 1609.4 standards for Security, Network Services and Multi-Channel Operation, the
SAE J2735 Message Set Dictionary, and the emerging SAE J2945.1 Communication Minimum
Performance Requirements standard. The paper shows how these standards fit together to
provide a comprehensive solution for DSRC. Most of the key standards are either recently
published or expected to be completed in the coming year. A reader will gain a thorough
understanding of DSRC technology for vehicular communication, including insights into why
specific technical solutions are being adopted, and key challenges remaining for successful
DSRC deployment. The U.S. Department of Transportation is planning to decide in 2013
whether to require DSRC equipment in new vehicles.
2.2 Design of 5.9 G Hz DSRC-based vehicular safety communication:
The automotive industry is moving aggressively in the direction of advanced active safety.
Dedicated short-range communication (DSRC) is a key enabling technology for the next
generation of communication-based safety applications. One aspect of vehicular safety
communication is the routine broadcast of messages among all equipped vehicles. Therefore,
channel congestion control and broadcast performance improvement are of particular concern
and need to be addressed in the overall protocol design. Furthermore, the explicit multichannel
nature of DSRC necessitates a concurrent multichannel operational scheme for safety and non-
safety applications. This article provides an overview of DSRC based vehicular safety
communications and proposes a coherent set of protocols to address these requirements.
2.3 A Manchester code generator running at 1 GHz:
A new Manchester code generator designed at transistor level is presented in this paper. This
generator uses 32 transistors and has the same complexity as a standard D flip-flop. It is intended
to be used in a complex optical communication system. The main benefit of this design is to use
a clock signal running at the same frequency as the data. Output changes on the rising edge and
falling edge of the clock. Simulations results show a correct behavior up to 1 Gbit/s data rate
with a 0.35 μ CMOS technology within a commercial temperature range.
2.4 A 90nm Manchester Code Generator with CMOS Switches Running at

2.4GHz and 5GHz:
A Manchester code generator designed at transistor level with NMOS switches is presented. This
generator uses 26 transistors and has the same complexity as a standard D flip-flop. It is intended
to be used in a complex optical communication system. The main benefit of this design is the use
of a clock signal running at the same frequency as the data. Output changes on the rising edge
and falling edge of the clock. The circuit has been designed in a 90 nm UMC CMOS technology
to evaluate the efficiency of the proposed approach and experimental results show a correct
behavior up to 5 G Bit/s data rate.
2.5 High-Speed CMOS Chip Design for Manchester and Miller Encoder:
In this paper, we propose a modified Manchester and Miller encoder that can operate
in high frequency without a sophisticated circuit structure. Based on the previous proposed
architecture, the study has adopted the concept of parallel operation to improve data throughput.
In addition, the technique of hardware sharing is adopted in this design to reduce the number of
transistors. The study uses TSMCCMOS 0.35-mum 2P4M technology. The simulation result of
HSPICE indicates that it functions successfully and works at 200-MHz speed. The average
power consumption of the circuit under room temperature is 549 muW. The total core area is
70.7 mumtimes72.2 mum. As expected, the circuit can be easily integrated into radio frequency
identification (RFID) application.
2.6 FSM based Manchester encoder for UHF RFID tag emulator: The radio
frequency identification system (RFID) is becoming one of the most popular system in wireless
technologies. The UHF RFID tag emulator is a part of RFID testing tools. The UHF RFID tag
emulator would be imitating the behavior of RFID Tag. The UHF RFID tag emulator (860 MHz
to 960 MHz) is aimed for testing the RFID systems and also acts as a general-purpose data
transport device for other RFID systems. The tag emulator belongs to the EPC class-III (semi-
passive) tags, but it implements the Class-1Generation II (C1G2) air interface protocol for
communicating with the reader. In this work, we have presented RTL design
of Manchester encoder. As motivated by Finite State Machine (FSM) and RTL implementations
of encoder are discussed with particular focus to use the RFID Emulator as data transport device
and debugging tool. The synthesis result shows that FSM design is efficient (less area and high
speed) and it operates at a maximum frequency of 256.54 M Hz.
2.7 Top down design of joint MODEM and CODEC detection schemes for
DSRC coded-FSK systems over high mobility fading channels:
The joint detection and verification of frequency shift keying (FSK) modulation and
demodulation (MODEM), Manchester coding and decoding (CODEC) schemes are proposed for
dedicated short range communication (DSRC) systems over high mobility fading channels. The
proposed joint coded-FSK detection scheme with low complexity benefit can outperform the
conventional separated coded-FSK detection scheme. It is due to the joint scheme with time
diversity gain to enhance the detection performance. Moreover, the proposed joint algorithms
with floating-point and fixed-point designs are verified in the software-defined-ratio (SDR)
platform. Based on the measurement results via SDR equipments, it is confirmed that the
implementation of VHDL hardware circuit design of the proposed joint detection scheme can
provide robust performance over high mobility Rician multipath fading channel environment.
2.8 Simultaneous Routing and Buffer Insertion algorithm for interconnect

delay optimization in VLSI layout design:
The design of VLSI circuits today has become very challenging indeed. The main factor
affecting system performance is the interconnect delay. Many algorithms have been proposed to
solve the interconnect timing optimization problem. Research has shown that techniques
like buffer insertion and wire-sizing have been proven to be very effective in reducing
interconnect delay. This paper describes a graph-based routing algorithm to solve the
interconnect delay optimization problem in a deep submicron VLSI layout routing. The
algorithm finds the optimal delay routing paths with simultaneous consideration
of buffer insertions and wire-sizing, while taking into account wire or buffer obstacles. The
proposed algorithm, called S-RABILA (Simultaneous Routing and Buffer Insertion with Look-
Ahead), utilizes a novel look-ahead technique that significantly contributes to the computational
efficiency of the proposed algorithm. In this paper, the performance of S-RABILA is presented,
which shows the effectiveness of the look-ahead scheme. Experimental results also indicate that
the proposed algorithm provide significant improvements over similar existing VLSI routing
algorithms.
Chapter 3
EXISTING SYSTEM
The dedicated short-range communication (DSRC)is an emerging technique to push the

intelligent transportation system into our daily life. The DSRC standards generally adopt FM0
and Manchester codes to reach dc-balance, enhancing the signal reliability. Nevertheless, the
coding-diversity between the FM0 and Manchester codes seriously limits the potential to design
a fully reused VLSI architecture for both. In this paper, the similarity-oriented logic
simplification (SOLS) technique is proposed to overcome this limitation. The SOLS technique
improves the hardware utilization rate from 57.14%to 100% for both FM0 and Manchester
encodings. The performance of this project is evaluated on the post layout simulation in Taiwan
Semiconductor Manufacturing Company (TSMC)0.18-μm 1P6M CMOS technology. The
maximum operation frequency is 2 GHz and 900 MHz for Manchester and FM0 encodings,
respectively. The power consumption is 1.58 mW at2 GHz for Manchester encoding and
1.14mW at 900 MHz forFM0 encoding. The core circuit area is 65.98 × 30.43 μm2. The
encoding capability of this paper can fully support the DSRC standards of America, Europe, and
Japan. This project not only develops a fully reused VLSI architecture, but also exhibits an
efficient performance compared with the existing works.
The dedicated short-range communication (DSRC) [1] is a protocol for one- or two-way
medium range communication especially for intelligent transportation systems. The DSRC can
be briefly classified into two categories: automobile-to-automobile and automobile-to-roadside.
In automobile-to-automobile, the DSRC enables the message sending and broadcasting among
automobiles for safety issues and public information announcement [2], [3]. The safety issues
include blind-spot, intersection warning, inter cars distance, and collision-alarm. The
automobile-to-roadside on the intelligent transportation service, such as electronic toll collection
(ETC) system. With ETC, the toll collecting is electrically accomplished with the contactless IC-
card platform. Moreover, the ETC can be extended to the payment for parking-service, and gas-
refueling. Thus, the DSRC system plays an important role in modern automobile industry.The
upper and bottom parts are dedicated for transmission and receiving, respectively. This
transceiver is classified into three basic modules: micro processor, baseband processing, and RF
front-end. The microprocessor interprets instructions from media access control to schedule the
tasks of baseband processing and RF front-end. The baseband processing is responsible for
modulation, error correction, clock synchronization, and encoding. The RF frontend transmits
and receives the wireless signal through the antenna .The DSRC standards have been established
by several organizations in different countries.The data rate individually targets at 500 kb/s, 4
Mb/s, and 27 Mb/s with carrier frequency of 5.8 and 5.9 GHz. The modulation methods
incorporate amplitude shift keying, phase shift keying, and orthogonal frequency division
multiplexing. Generally, the waveform of transmitted signal is expected to have zero mean for
robustness issue, and this is also referred to as dc-balance.
The transmitted signal consists of arbitrary binary sequence, which is difficult to obtain
dc-balance. The purposes of FM0 and Manchester codes can provide the transmitted signal with
dc-balance. Both FM0 and Manchester codes are widely adopted in encoding for downlink. The
VLSI architectures of FM0 and Manchester encoders are review as follows. A. Review of VLSI
Architectures for FM0 Encoder and Manchester Encoder The literature [4] proposes a VLSI
architecture of Manchester encoder for optical communications. This design adopts the CMOS
inverter and the gated inverter as the switch to construct Manchester encoder switch to construct
Manchester encoder. It is implemented by0.35-μm CMOS technology and its operation
frequency is 1 GHz. The literature [5] further replaces the architecture of switch in [4] by the
nMOS device. It is realized in 90-nm CMOS technology, and the maximum operation frequency
is as high as 5 GHz. The literature [6] develops a high-speed VLSI architecture almost fully
reused with Manchester and Miller encodings for radio frequency identification (RFID)
applications.
This design is realized in 0.35-μm CMOS technology and the maximum operation
frequency is 200 mHz. The literature [7] also proposes a Manchester encoding architecture for
ultrahigh frequency (UHF) RFID tag emulator. This hardware architecture is conducted from the
finite state machine (FSM) of Manchester code, and is realized into field-programmable gate
array (FPGA) prototyping system. The maximum operation frequency of this design is about 256
MHz. The similar design methodology is further applied individually construct FM0 and Miller
encoders also for UHF RFID Tag emulator [8] . Its maximum operation frequency is about 192
MHz. Furthermore, [9] combines frequency shift keying (FSK) modulation and demodulation
with Manchester codec in hardware realization.
However, the coding-diversity between both seriously limits the potential to design a
VLSI architecture that can be fully reused with each other. This paper proposes a VLSI
architecture design using similarity-oriented logic simplification (SOLS) technique. The SOLS
consists of two core methods. area-compact retiming and balance logic-operation sharing.The
area-compact retiming relocates the hardware resource to reduce 22 transistors. The balance
logic-operation sharing efficiently combines FM0 and Manchester encodings with the fully
reused hardware architecture. With SOLS technique, this paper constructs a fully reused VLSI
architecture of Manchester and FM0 encodings for DSRC applications. The experiment results
reveal that this design achieves an efficient performance compared with sophisticated works.
Chapter 4
PROPOSED SYSTEM
• In this implementing SOLS techniques based FMO/Manchester
• The SOLS consists of two core methods:
– area-compact retiming
– balance logic operation sharing.
The area-compact retiming relocates the hardware resource to reduce 5 transistors. The balance
logic operation sharing efficiently uses reused VLSI architecture.
Figure 4.1
• Manchester Logic: Look like XOR operation
• X ⊕ CLK.
• The Manchester encoding is realized with a XOR operation for CLK and X.
• The clock always has a transition within one cycle, and so does the Manchester code no
matter what the X is.
4.2Manchester Logic
• FM0 Logic: FM0 code consists of two parts
• one for former-half cycle of CLK, A
• Other one for later-half cycle of CLK, B
• FM0 is listed as the following three rules
• Rule1:X is the logic-0, the FM0 code must exhibit a transition between A and B
• Rule2:X is the logic-1, no transition is allowed between A and B.
• Rule3:The transition is allocated among each FM0 code no matter what the X is
4.3 FMO Logic
Hardware utilization of FM0 and Manchester encoders. Manchester encoding is as simple

as a XOR operation. Hardware architecture for FM0 is not as simple as that of
Manchester. Hardware architecture of FM0 encoding should start with the FSM of FM0
first classified into four states A state code is individually assigned to each state, and each
state code consists of A and B.state is S1, and its state code is 11 for A and B .If the X is
logic-0, the state-transition must follow both X is logic-1, the state-transition must follow
both rules 2 and 3. The only one next-state that can satisfy both rules for the X of logic-1
is S4.Thus, the state-transition of each state can be completely constructed rules 1 and 3.
The only one next-state that can satisfy both rules for the X of logic-0 is S3
Transition Table:
HUR OF FM0 AND MANCHESTER ENCODINGS
• HUR->hardware utilization ration
Transistor Count for FM0 and Manchester Encode :
The transistor count of the hardware architecture without SOLS technique is 98,86 transistors
are for FM0 encoding,26 transistors are for Manchester coding. average, only 56 transistors can
be reused, and this is consistent with its HUR. The coding-diversity between the FM0 and
Manchester codes seriously limits the potential to design a fully reused VLSI architecture .
Reduced FM0/Manchester Diagram:
The total numbers of components are reduced from 7 to 5 using SOLS technique.
Without SOLS technique, the individual hardware Architecture of both coding with a
poor HUR of 57.14%. The transistor count of the FM0 encoding architecture without
area-compact retiming is 72,and that with area-compact retiming is 50. The area-compact
retiming technique reduces 22 transistors. Total number of hardware utilization is
reduced after sols techniques Only one Flip-Flop is used to store. The DFF1 is directly
remove d, a non synchronization effect causes between A(t),B(t) and gives fault in the
output. To avoid this logic-fault, the DFFB is relocated right after the MUX−1.This
causes unbalance computation time between A(t)/ X ,B(t)/X.As the result, there is
glitches in MUX1 and causing logic fault on coding. To alleviate above, the Architecture
of the balance computation time between A(t)/ X ,B(t)/X. total numbers of components
are reduced from 7 to 5 using SOLS technique. Without SOLS technique, the individual
hardware Architecture of both coding with a poor HUR of 57.14%.
CHAPTER 5
HARDWARE DESCRIPTIVE LANGUAGE (HDL)&
SOFTWARE
5.1 Why (V) HDL?

 Interoperability
 Technology independence
 Design reuse
 Several levels of abstraction
 Readability
 Standard language
 Widely supported
What is Verilog:
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to
model electronic systems. It is most commonly used in the design and verification of digital
circuits at the register-transfer level of abstraction. It is also used in the verification of analog
circuits and mixed-signal circuits.
Hardware description languages such as Verilog differ from software programming languages
because they include ways of describing the propagation time and signal strengths (sensitivity). There are
two types of assignment operators; a blocking assignment (=), and a non-blocking (<=) assignment. The
non-blocking assignment allows designers to describe a state-machine update without needing to declare
and use temporary storage variables. Since these concepts are part of Verilog's language semantics,
designers could quickly write descriptions of large circuits in a relatively compact and concise form. At the
time of Verilog's introduction (1984), Verilog represented a tremendous productivity improvement for circuit
designers who were already using graphical schematic capture software and specially written software
programs to document and simulate electronic circuits.
The designers of Verilog wanted a language with syntax similar to the C programming
language, which was already widely used in engineering software development. Like C, Verilog
is case-sensitive and has a basic preprocessor (though less sophisticated than that of ANSI
C/C++). Its control flowkeywords (if/else, for, while, case, etc.) are equivalent, and its operator
precedence is compatible with C. Syntactic differences include: required bit-widths for variable
declarations, demarcation of procedural blocks (Verilog uses begin/end instead of curly braces
{}), and many other minor differences. Verilog requires that variables be given a definite size. In
C these sizes are assumed from the 'type' of the variable (for instance an integer type may be 8
bits).A Verilog design consists of a hierarchy of modules. Modules encapsulate design
hierarchy, and communicate with other modules through a set of declared input, output, and
bidirectional ports. Internally, a module can contain any combination of the following:
net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks,
and instances of other modules (sub-hierarchies). Sequential statements are placed inside a
begin/end block and executed in sequential order within the block. However, the blocks
themselves are executed concurrently, making Verilog a dataflow language.
Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating,
undefined") and signal strengths (strong, weak, etc.). This system allows abstract modeling of
shared signal lines, where multiple sources drive a common net. When a wire has multiple
drivers, the wire's (readable) value is resolved by a function of the source drivers and their
strengths.Asubset of statements in the Verilog language aresynthesizable. Verilog modules that
conform to a synthesizable coding style, known as RTL (register-transfer level), can be
physically realized by synthesis software. Synthesis software algorithmically transforms the
(abstract) Verilog source into a netlist, a logically equivalent description consisting only of
elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that are available in a specific
FPGA or VLSI technology. Further manipulations to the netlist ultimately lead to a circuit
fabrication blueprint (such as a photo mask set for an ASIC or a bitstream file for an FPGA).
Example:
modulemain;
initial
begin
$display("Hello world!");
$finish;
end
endmodule
The Verilog Procedural Interface (VPI), originally known as PLI 2.0, is an interface
primarily intended for the Cprogramming language. It allows behavioral Verilog code to invoke
C functions, and C functions to invoke standard Verilog system tasks. The Verilog Procedural
Interface is part of the IEEE 1364 Programming Language Interface standard; the most recent
edition of the standard is from 2005. VPI is sometimes also referred to as PLI 2, since it replaces
the deprecatedProgram Language Interface (PLI).
While PLI 1 was depreciated in favor of VPI (aka. PLI 2), PLI 1 is still commonly used over VPI
due to its much more widely documented tf_put, tf_get function interface that is described in
many verilog reference books.
moduletoplevel(clock,reset);
inputclock;
inputreset;
regflop1;
regflop2;
always@(posedgeresetorposedgeclock)
if(reset)
begin
flop1<=0;
flop2<=1;
end
else
begin
flop1<=flop2;
flop2<=flop1;
end
endmodule
The definition of constants in Verilog supports the addition of a width parameter. The basic
syntax is:
<Width in bits>'<base letter><number>
Examples:
 12'h123 - Hexadecimal 123 (using 12 bits)

 20'd44 - Decimal 44 (using 20 bits - 0 extension is automatic)
 4'b1010 - Binary 1010 (using 4 bits)
 6'o77 - Octal 77 (using 6 bits)
5.2 SOFTWARE INFORMATION:

Create a New Project Create a new ISE project which will target the FPGA device on the
Spartan-3 Startup Kit demo board. To create a new project: 1. Select File > New Project... The
New Project Wizard appears. 2. Type tutorial in the Project Name field. 3. Enter or browse to a
location (directory path) for the new project. A tutorial subdirectory is created automatically. 4.
Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the
device properties page. 6. Fill in the properties in the table as shown below:
♦ Product Category: All
♦ Family: Spartan3
♦ Device: XC3S200
♦ Package: FT256
♦ Speed Grade: -4
♦ Top-Level Source Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Preferred Language: Verilog (or VHDL)
♦ Verify that Enable Enhanced Design Summary is selected.

Leave the default values in the remaining fields. When the table is complete, your project
properties will look like the following:
5.3 Creating a Verilog Source:

Create the top-level Verilog source file for the project as follows: 1. Click New Source in
the New Project dialog box. 2. Select Verilog Module as the source type in the New Source
dialog box. 3. Type in the file name counter. 4. Verify that the Add to Project checkbox is
selected. 5. Click Next. 6. Declare the ports for the counter design by filling in the port
information as shown below:
The source file containing the counter module displays in the Workspace, and the counter displays in the
Sources tab, as shown below:
Using Language Templates (Verilog):

The next step in creating the new source is to add the behavioral description for counter.
Use a simple counter code example from the ISE Language Templates and customize it for the
counter design. 1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement.
2. Open the Language Templates by selecting Edit → Language Templates… Note: You can tile
the Language Templates and the counter file by selecting Window → Tile Vertically to make
them both visible. 3. Using the “+” symbol, browse to the following code example: Verilog →
Synthesis Constructs → Coding Examples → Counters → Binary → Up/Down Counters →
Simple Counter.4. With Simple Counter selected, select Edit → Use in File, or select the Use
Template in File toolbar button. This step copies the template into the counter source file.
5. Close the Language Templates
5.4 Design Simulation :
Verifying Functionality using Behavioral Simulation Create a test bench waveform

containing input stimulus you can use to verify the functionality of the counter module. The test
bench waveform is a graphical view of a test bench. Create the test bench waveform as follows:
1. Select the counter HDL file in the Sources window. 2. Create a new test bench source by
selecting Project → New Source. 3. In the New Source Wizard, select Test Bench WaveForm as
the source type, and type counter_tbw in the File Name field. 4. Click Next. 5. The Associated
Source page shows that you are associating the test bench waveform with the source file counter.
Click Next. 6. The Summary page shows that the source will be added to the project, and it
displays the source directory, type, and name. Click Finish. 7. You need to set the clock
frequency, setup time and output delay times in the Initialize Timing dialog box before the test
bench waveform editing window opens. The requirements for this design are the following:
♦ The counter must operate correctly with an input clock frequency = 25 MHz.
♦ The DIRECTION input will be valid 10 ns before the rising edge of CLOCK
♦ The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. The
design requirements correspond with the values below. Fill in the fields in the Initialize Timing
dialog box with the following information:
♦ Clock High Time: 20 ns.
♦ Clock Low Time: 20 ns.
♦ Input Setup Time: 10 ns.
♦ Output Valid Delay: 10 ns. ♦ Offset: 0 ns.
♦ Global Signals: GSR (FPGA) Note: When GSR(FPGA) is enabled, 100 ns. is added to
the Offset value automatically.
♦ Initial Length of Test Bench: 1500 ns.
8. Click Finish to complete the timing initialization. 9. The blue shaded areas that precede the
rising edge of the CLOCK correspond to the Input Setup Time in the Initialize Timing dialog
box. Toggle the DIRECTION port to define the input stimulus for the counter design as follows:
♦ Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that the count
Chapter 6
Simulation Results:
Fully reused VLSI architecture of FM0/ Manchester Encoding Using SOLS technique for DSRC
Applications. In this The SOLS technique eliminates the limitation on hardware utilization by
two core techniques: area – compact retiming and balance logic-operation sharing. The SOL
technique improves the hardware utilization rate for both FM0 and Manchester encodings.
Tools:
Xilinx 10.1
Model SIM 6.4e
Results:
Existing FMO/Manchester Encoder:
6.1 RTL schematic of FMO/Manchester Encoding
This is top module for existing systems, it is the block diagram which has (left side has inputs)
“clk, mode and x’. the output is “y” (right side has output).
6.2 RTL schematic Internal Modules
In this picture, it is the internal block diagram of the top module. This contain three sub block,
“aaa” is for FM0 coding ,”Manchester” is for Manchester coding and multiplexer is the third
block which is used for selecting the any one output at any time.
The “aaa’ or FM0 coding is constructed by using Finite state machine (FSM) and Manchester
coding is constructed by XOR Gate.
6.3 Technology Schematic of Existing
This is internal diagram of top module, it will show how many LUTs, multiplexers, basic gates
and flip-flops are there and how they are connected with each other. The all devices are
connected through logic. On FPGA it will show how they are working. Input is connected
through input buffer and output is connected through output buffer.
6.4 Synthesis report
This is the design summary for exciting circuit it, in this summary we can see how many number
of slices, number of slice flipflop and number of luts.
Number of slices : 6
Number of slice flipflops : 7
Number of 4 input luts : 11
6.5 This is the timing summary of exciting circuit, it contain minimum time period, setup time, hold time
and combinational delays
Minimum time period : 2.336ns
Minimum input arriaval time before clock : 2.848ns
Maximum output required time after clock : 6.739ns
Maximum combinational path delay : 7.289ns
6.6 Simulation waveform of Existing Encoder
The above figure shows the simulation of Existing Encoder where we apply different x inputs
and mode inputs depend upon this the Encoding data was done.
When Mode=’0’ was selected then the input X was encoded with FMO coding.
When Mode=’1’ was selected then the input x was encoded with Manchester Coding
FMO/Macnchester Encoder with SOLS technique:
6.7 RTL top Module of Proposed Encoder
This is top module for proposed systems, it is the block diagram which has (left side has inputs)
“clk, clrk, mode and x’. the output is “y” (right side has output).
6.8 Internal Blocks of Proposed Encoder
In this picture, it is the internal block diagram of the top module1. This contain sub block, XOR,
inverter D fliplop and multiplexer is the third block which is used for selecting the any one
output at any time.
6.9 Synthesis Report
This is the design summary for proposed circuit it, in this summary we can see how many
number of slices, number of slice flipflop and number of luts.
Number of 4 input luts :
6.10 Timing Summary
This is the timing summary of proposed circuit, it contain minimum time period, setup time, hold
time and combinational delays
Minimum input arriaval time before clock : 3.206ns
6.11 Simulation Waveform of Proposed Encoder
The Proposed Encoder Encodes the data(X) depend Upon the “Mode” and “Clr”.
If Mode=’0’ and Clr=’1’ the input data was encoded with the FMO coder
If Mode=’1’ and Clu=’0’ then the input data was encoded with Manchester Encoding
Design of FMO/Manchester/Miller Encoder:
6.12 RTL of Encoder with Miller
This is the extension circuit with miller coding and it has two modes. The topmodule is shown, it
has input “clk, clr, mode1, mode2, x” and output “y”.
6.13 Synthesis Report of Extended Encoder
This is the design summary for proposed circuit it, in this summary we can see how many
number of slices, number of slice flipflop and number of luts.
Number of 4 input luts : 6
6.14 Timing Summary of Extension Encoder
This is the timing summary of proposed circuit, it contain minimum time period, setup time,
hold time and combinational delays
Minimum input arriaval time before clock : 3.455 ns
6.15 Simulation Waveform of Extension Encoder
In this encoder the data was encoded depend upon the Mode1,Mode2 and Clr.
If Mode1=’0’, Clr=’1’ and Mode2=’0’ then the input data was encoded with the FMO coder
If Mode1=’1’, Clr=’0’ and Mode2=’0’ then the input data was encoded with Manchester
Encoding
If Mode1=’x’, Clr=’x’ and Mode2=’1’ then the input data was encoded with Miller Encoding
CHAPTER 7
CONCLUTION
In this project, the totally reused VLSI auxiliary designing using SOLS technique for
both FM0 and Manchester encodings with clock gating techniques will be proposed The timing
investigation are confirmed on Xilinx test system. The Xilinx10.1 ISE programming is used in
the venture and code is composed on Verilog HDL. The objective FPGA prototyping gadget is
fits in with Spartan3E family and the gadget is XC3S200E which has speed evaluation of - 5.
The force utilization is 1.48mW and the postponement is 5.776ns. The SOLS procedure gives
superior when contrasted with existing articles. In future the configuration might actualized
utilizing superior FPGA gadgets and the Nanometer might be diminished from 45nm to 32 nm
CMOS innovation.
References
[1] F. Ahmed-Zaid, F. Bai, S. Bai, C. Basnayake, B. Bellur, S. Brovold, et al., “Vehicle safety
communications—Applications (VSC-A) final report,” U.S. Dept. Trans., Nat. Highway Traffic
Safety Admin., Washington, DC, USA, Rep. DOT HS 810 591, Sep. 2011.
[2] J. B. Kenney, “Dedicated short-range communications (DSRC) standards in the United

States,” Proc. IEEE, vol. 99, no. 7, pp. 1162–1182, Jul. 2011.
[3] J. Daniel, V. Taliwal, A. Meier, W. Holfelder, and R. Herrtwich, “Design of 5.9 GHz DSRC-
based vehicular safety communication,” IEEE Wireless Commun. Mag., vol. 13, no. 5, pp. 36–
43, Oct. 2006.
[4] P. Benabes, A. Gauthier, and J. Oksman, “A Manchester code generator running at 1 GHz,”
in Proc. IEEE, Int. Conf. Electron., Circuits Syst., vol. 3. Dec. 2003, pp. 1156–1159.
[5] A. Karagounis, A. Polyzos, B. Kotsos, and N. Assimakis, “A 90nm Manchester code

generator with CMOS switches running at 2.4 GHz and 5 GHz,” in Proc. 16th Int. Conf. Syst.,
Signals Image Process., Jun. 2009, pp. 1–4.
[6] Y.-C. Hung, M.-M. Kuo, C.-K. Tung, and S.-H. Shieh, “High-speed CMOS chip design for
Manchester and Miller encoder,” in Proc. Intell. Inf. Hiding Multimedia Signal Process., Sep.
2009, pp. 538–541.
[7] M. A. Khan, M. Sharma, and P. R. Brahmanandha, “FSM based Manchester encoder for
UHF RFID tag emulator,” in Proc. Int. Conf. Comput., Commun. Netw., Dec. 2008, pp. 1–6.
[8] M. A. Khan, M. Sharma, and P. R. Brahmanandha, “FSM based FM0 and Miller encoder for
UHF RFID tag emulator,” in Proc. IEEE Adv. Comput. Conf., Mar. 2009, pp. 1317–1322.
[9] J.-H. Deng, F.-C. Hsiao, and Y.-H. Lin, “Top down design of joint MODEM and CODEC
detection schemes for DSRC coded-FSK systems over high mobility fading channels,” in Proc.
Adv. Commun. Technol. Jan. 2013, pp. 98–103.
[10] I.-M. Liu, T.-H. Liu, H. Zhou, and A. Aziz, “Simultaneous PTL buffer insertion and sizing
for minimizing Elmore delay,” in Proc. Int. Workshop Logic Synth., May 1998, pp. 162–168.
[11] H. Zhou and A. Aziz, “Buffer minimization in pass transistor logic,” IEEE Trans. Comput.
Aided Des. Integr. Circuits Syst., vol. 20, no. 5, pp. 693–697, May 2001.
[12] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems

Perspective, 2nd ed., Upper Saddle River, NJ, USA: Pearson Educ. Ltd., 1993, pp. 98–103.

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IMPLEMENTATION OF VLSI ARCHITECTURE OF FM0/MANCHESTER ENCODING

USING SOLS TECHNIQUE FOR DSRC APPLICATIONS

Fully Reused VLSI Architecture of FM0 / Manchester Encoding

This transceiver is classified into three basic modules: microprocessor, baseband

Figure 3.1 A VLSI VL82C106 Super I/O chip

ENCODER AND DECODER:

Table 1.1.1 encoder

Figure 1.1.1 Encoder

Figure 1.1.2 Decoder

1.1.3 Octal to binary encoder:

Table 1.1.3: Truth Table of octal to binary encoder

Fig 1.1.3: Logic Diagram of octal to binary encoder

1.1.4 Priority encoder:

Table1.1.4: Truth Table of 4 bit priority encoder

Fig 1.1.4 : Logic Diagram of 4 bit priority encoder

IC 74148 is an 8-input priority encoder. 74147 is 10:4 priority encoder

Table 1. 5: Truth Table of 8:1 MUX

Fig 1.1.5: Logic Diagram of 8:1 MUX

Table1.1.6: Truth Table of 1:8 DEMUX

Figure 1.1.6 De-multiplexer

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-

The D ﬂip-ﬂop is widely used. It is also known as a "data" or "delay" flip-flop.

('X' denotes a Don't care condition, meaning the signal is irrelevant)

Classical positive-edge-triggered D flip-flop[edit]

1.1.7 A positive-edge-triggered D flip-flop

1.1.8 Master–slave edge-triggered D flip-flop[edit]

1.1.8 A master–slave D flip-flop.

A CMOS IC implementation of a "true single-phase edge-triggered flip-flop with reset"

1. 2. FM0 AND MANCHESTER ENCODING TECHNIQUES

1.2.1 FM0 encoding

Figure 1.2.1 FMO Encoding

1.2.2 Manchester Encoding

Figure 1.2.2 Manchester Encoding

• FM0 Encoding equation is T1 = CLKbar.Qa + CLK.Qb (1) • Manchester Encoding equation is

1.2.3 Miller Encoding Technique:

1.2.3 Block Diagram Of Miller Encoding

Mode1 Mode2 Clear Output

2.2 Design of 5.9 G Hz DSRC-based vehicular safety communication:

2.3 A Manchester code generator running at 1 GHz:

2.4 A 90nm Manchester Code Generator with CMOS Switches Running at

2.8 Simultaneous Routing and Buffer Insertion algorithm for interconnect

The dedicated short-range communication (DSRC)is an emerging technique to push the

• In this implementing SOLS techniques based FMO/Manchester

• The SOLS consists of two core methods:

– balance logic operation sharing.

• Manchester Logic: Look like XOR operation

• FM0 Logic: FM0 code consists of two parts

• one for former-half cycle of CLK, A

• Other one for later-half cycle of CLK, B

• FM0 is listed as the following three rules

• Rule2:X is the logic-1, no transition is allowed between A and B.

4.3 FMO Logic

Hardware utilization of FM0 and Manchester encoders. Manchester encoding is as simple

HUR OF FM0 AND MANCHESTER ENCODINGS

• HUR->hardware utilization ration

Transistor Count for FM0 and Manchester Encode :

Reduced FM0/Manchester Diagram:

5.1 Why (V) HDL?

<Width in bits>'<base letter><number>