ATPG and Fault Simulation

Alberto Bosio
bosio@lirmm.fr

1
 What is a test?
Fault activation
Combinational circuit Fault effect
X
1
0
Primary 1/0 1/0
0 Primary outputs
inputs 1 (PO)
(PI) 0
1
X
Path sensitization
Stuck-at-0 fault
2
 What is a test?
Fault activation
Combinational circuit Fault effect
X
1
0
Primary 1/0 1/0
0 Primary outputs
inputs 1 (PO)
(PI) 0
1
X Test Response
Test Vector Path sensitization
Stuck-at-0 fault
3
 Example
n  Generate a test for e stuck-at-1

Sa1
a

b e
c
g

d f

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 Example
n  1) Activate the fault

a 0
b e
c
g

d f

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 Example
n  1) Activate the fault

a 0/1
b e
c
g

d f

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 Example
n  1) Activate the fault

Fault Effect
a 0/1
b e
c
g

d f

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 Example
n  1) Propagate the fault effect

a 0/1
0/1
b e
c
g

d f

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 Example
n  1) Propagate the fault effect

a 0/1
0/1
b e
c
g

d f

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 Example
n  1) Propagate the fault effect

a 0/1
0/1
b e 0/1
c
g

0
d f

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 Example
n  1) Propagate the fault effect

a 0/1
0/1
b e 0/1
c
g

0
d f

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 Example
n  Justification

a 0/1
0/1
b e 0/1
c
g
0
0
d f

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 Example
n  Justification

a 0/1
1 0/1
b e 0/1
c
g
1 0
0
d f

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 Example
n  Justification

0
a 0/1
1 0/1
b e 0/1
c
g
1 0
0
d f

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Some Considerations
n  Test is easy
n  But….

15
 Some problems (the
complexity)

2.2 Billion Transistors

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 Some problems (the circuit)
n  Generate a test for c stuck-at-1

Sa1
a

b e
c
g

d f

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 Some problems (the circuit)
n  c stuck-at-1 is an untestable fault

1
a 0/1
0/1
0 0/1
b
c
e 1
g
0 1
1
d f

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Goals
n  You must use the appropriate tool
n  Automatic Test Pattern Generator (ATPG)

19
 ATPG Architecture
Reduced
Circuit
Fault Manager Fault List
description

TPG
Fault Simulator
Algorithm

Fault Test
Coverage Pattern

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 ATPG Architecture
Reduced
Circuit
Fault Manager Fault List
description
Fault Coverage (FC) = # Detected Faults/#Total Faults

TPG
Fault Simulator
Algorithm

Fault Test
Coverage Pattern

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The test plan
n  Step 1:
n  Identify the set of target faults (complete
fault list).

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 The test plan
n  Step 1:
n  Tools – Fault list generator
n  (One of the components of the Fault Manager).

Circuit Fault List

description Generator
Complete
Fault List

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The test plan (cont’d)
n  Step 1:
n  Identify the set of target faults (complete
fault list).
n  Step 2:
n  Identify the minimum set of distinct target
faults (fault collapsing)

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The test plan
n  Step 2:
n  Tools – Fault collapser (One of the
components of the Fault Manager).

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 Fault Manager

Circuit Fault List

description Generator
Complete
Fault List

Reduced
Fault Collapser
Fault List

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 Fault Manager

Circuit Reduced
description Fault Manager
Fault List

Test Pattern
Generator

Test Fault
Pattern Coverage 27
The test plan (cont’d)
n  Step 2:
n  Identify the minimum set of distinct target
faults (fault collapsing)
n  Step 3:
n  Generate, at no charge, an initial set of
patterns (manually, from design validation,
randomly, ...)

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The test plan (cont’d)
n  Step 3:
n  Generate, at no charge, an initial set of
patterns (manually, from design validation,
randomly, ...)
n  Step 4:
n  Update the list of detected faults (fault
simulation)

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Step 4
n  Tools
n  Fault Simulators: identify the set of faults
covered by each test pattern.

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 Fault Simulator
Circuit Reduced
description Fault List

Fault Simulator Update

Detected
Fault Test Faults
Coverage Pattern
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The test plan (cont’d)
n  Step 4:
n  Update the list of detected faults (fault
simulation)
n  Step 5:
n  Generate a set of patterns to cover the
uncovered faults (TPG)

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Step 5
n  Tools
n  ATPG: Automatic Test Pattern Generator

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 TPG
Circuit Reduced
description Fault List

TPG
Fault Simulator Fault Selector
Algorithm

Fault Test Target

Coverage Pattern Fault

Detected
Faults 34
n  They cycle through three sub-phases:
n  target fault selection
n  Pattern generation
n  Covered fault list updating.

35
The test plan (cont’d)
n  Step 5:
n  Generate a set of patterns to cover the
uncovered faults (TPG)
n  Step 6 (optional):
n  Testability analysis
n  Step 7 (optional):
n  Compact test pattern set.

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Step 6
n  Goal
n  Estimate the effort needed to test the UUT:
n  Pattern length
n  Fault coverage
n  CPU time
n  ...
n  Identify hard-to-test areas
n  Tools
n  Testability Analyzer
n  Experience.
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The test plan (cont’d)
n  Step 5:
n  Generate a set of patterns to cover the
uncovered faults (TPG)
n  Step 6 (optional):
n  Testability analysis
n  Step 7 (optional):
n  Compact test pattern set.

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Testability Analyzer
n  High trade-off between result accuracy
and CPU time.

n  A Circuit is testable when you ATPG can

manage it!!!!!

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 Fault Simulation*
n  Problem and motivation
n  Fault simulation algorithms
n  Serial
n  Parallel
n  Deductive

*The lecture has been taken from Prof. Agrawal VLSI test course
(http://www.eng.auburn.edu/~agrawvd/COURSE/E7250_06/
course.html) 40
Problem and Motivation
n  Given
n  A circuit
n  A sequence of test vectors
n  A fault model
n  Determine
n  Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
n  Set of undetected faults

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Problem and Motivation
n  Motivation
n  Determine test quality and in turn product
quality
n  Find undetected fault targets to improve

tests

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Fault Simulation Scenario
n  Circuit model: mixed-level
n  Mostly logic with some switch-level for high-impedance (Z) and
bidirectional signals
n  High-level models (memory, etc.) with pin faults
n  Signal states: logic
n  Two (0, 1) or three (0, 1, X) states for purely Boolean logic
circuits
n  Four states (0, 1, X, Z) for sequential MOS circuits
n  Timing:
n  Zero-delay for combinational and synchronous circuits
n  Mostly unit-delay for circuits with feedback

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Fault Simulation Scenario
(Continued)
n  Faults:
n  Mostly single stuck-at faults
n  Sometimes stuck-open, transition, and path-delay
faults; analog circuit fault simulators are not yet in
common use
n  Equivalence fault collapsing of single stuck-at faults
n  Fault-dropping -- a fault once detected is dropped
from consideration as more vectors are simulated;
fault-dropping may be suppressed for diagnosis
n  Fault sampling -- a random sample of faults is
simulated when the circuit is large
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Fault Simulation Algorithms
n  Serial
n  Parallel
n  Deductive
n  ....

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Serial Algorithm
n  Algorithm: Simulate fault-free circuit and save responses.
Repeat following steps for each fault in the fault list:
n  Modify netlist by injecting one fault

n  Simulate modified netlist, vector by vector, comparing

responses with saved responses

n  If response differs, report fault detection and suspend

simulation of remaining vectors

n  Advantages:
n  Easy to implement; needs only a true-value simulator,

less memory
n  Most faults, including analog faults, can be simulated

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Serial Algorithm
n  Disadvantage: Much repeated computation;
CPU time prohibitive for VLSI circuits
n  Alternative: Simulate many faults together

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Serial Algorithm

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Serial algorithm
n  + very simple
n  - not efficient
n  Intel I7 is about ~10M gates
n  20M faults, 1 simulation = 1s
n  20Ms ~= 231 days

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Parallel Fault Simulation
n  Compiled-code method; best with two-states (0,1)
n  Exploits inherent bit-parallelism of logic operations on
computer words
n  Storage: one word per line for two-state simulation
n  Multi-pass simulation: Each pass simulates w-1 new
faults, where w is the machine word length
n  Speed up over serial method ~ w-1
n  Not suitable for circuits with timing-critical and non-
Boolean logic

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Parallel Fault Simulation

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Parallel algorithm
n  + still very simple
n  + more efficient than serial
n  Intel I7 is about ~10M gates
n  20M faults, 1 simulation = 1s
n  20Ms ~= 231 days
n  Using a 64bits machine
n  231/63 ~= 4 days

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Deductive Fault Simulation
n  One-pass simulation
n  Each line k contains a list Lk of faults detectable on it
n  Following true-value simulation of each vector, fault lists
of all gate output lines are updated using set-theoretic
rules, signal values, and gate input fault lists
n  PO fault lists provide detection data
n  Limitations:
n  Set-theoretic rules difficult to derive for non-Boolean

gates
n  Gate delays are difficult to use

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Deductive Fault Simulation

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Deductive algorithm
n  - complex
n  ++ more efficient than parallel
n  Intel I7 is about ~10M gates
n  20M faults, 1 simulation = 1s
n  20Ms ~= 1s
n  - it requires a lot of memory

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Exercice
which faults are detected by the input “01110”?

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 In practice
n  Use of Synopsys© Tetramax
Technology_library.v Test_vectors.stil

Fault List
Circuit.v
TMAX

FaultCoverage 57
 Invoking TetraMax
n  source /soft/Synopsys/source_config/.config_tetramax_standalone_vI-2013.12
n  tmax

You can
enter
commands
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Step1
n  Read and Compile the circuit description

read_verilog C35.v –library!

read_verilog exo1.v!
run_build_model!
Run_drc!

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Step 2
n  Generate the fault list

set_faults -model stuck!

add_faults -all!

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Step 3
n  Specify the test vectors to be simulated
n  We have to use the stil syntax
n  Look in the example

Pattern "_pattern_" {!
W "_default_WFT_";!
"precondition all Signals": C
{ "_pi"=0000; "_po"=XX; }!
!
"pattern 0": Call "capture" { !
"_pi"=1010; "_po”=LL; }!
}! 61
Step 3
n  Import the test vector file
set_patterns -external example_exo1.stil!
n  Now we can run a simulation
run_simulation!
You will got errors:
n 

TEST-T> run_simulation !
Begin good simulation of 1 external
patterns.!
0 S2 (exp=0, got=1)!
Simulation completed: #patterns=1,
#fail_pats=1(0), #failing_meas=1(0),
CPU time=0.00! 62
Step 3
n  Tmax has to calculate the gold outputs
before running the fault simulation
run_simulation -override_differences!
n  Now you can run the fault simulation
run_fault_sim!

63