ATPG (Automatic Test Pattern Genrator)
ATPG (Automatic Test Pattern Genrator)
ATPG (Automatic Test Pattern Genrator)
DEPARTMENT OF ECE
JAYPEE INSTITUTE OF INFORMATION TECHNOLOGY,
NOIDA
TABLE OF CONTENTS
Digital testing starts with the development of the specifications for the system from
the set of requirements, which includes functional characteristics, operating
characteristics,physical and environmental and other constraints like area, pin count,
etc. This is followed by an architectural design to produce a system level structure
of realizable blocks for the functional specifications. These blocks are then
implemented at resister transfer level (RTL) using some hardware definition
language like Verilog or VHDL.Depending on the type of circuit and the nature of
testing required, some additional circuitry, pin out, etc. need to be added with the
original circuit so that hardware testing becomes efficient in terms of fault coverage,
test time, etc. this is called design for testability (DFT).After logic synthesis, test
patterns are generated that need to be applied to the circuit after it gets manufactured.
Test patters are generally applied and analyzed using automatic test equipment
(ATE). Figure shows the picture of an ATE from Teradyne.
D-Algorithm:
The D algorithm was the first true algorithm for ATPG. We can use it to generate
tests by combining what we know about the primitive elements of the circuit with
what we know about their interconnection network. The method that Roth proposed
is based on the intersection of dcubes, a notation for the difference calculus. Breuer
and Friedman’ give a good background treatment of the testing aspects of the D
algorithm in their text, while Roth offers a complete mathematical analysis in his
original paper. For our discussion, we examine Roths algorithm as a search of a
state space. We begin with the binary values 0 and 1 and add three new values. The
first added value is X, which denotes an unassigned node value. To describe the
difference between the good and faulty circuits,D and are introduced, denoting a
difference and a difference bar, respectively.
Path Sensitization Methods:
Path sensitization at the logic gate level of representation is currently the preferred
ATPG method. The approach consists of three steps:
1. Fault sensitization, in which a stuck-at fault is activated by forcing the signal
driving it to an opposite value from the fault value. This is necessary to ensure a
behavioral difference between the good circuit and the faulty circuit. Fault
sensitization is also known as fault activation or fault excitation.
2. Fault propagation, in which the fault effect is propagated through one or more
paths to a PO of the circuit. For some faults, it is necessary to simultaneously
propagate the fault effect over multiple paths to test it. In general, the number of
paths may rise exponentially in the number of logic gates in the circuit. Fault
propagation is also known as path sensitization.
3. Line justification, in which the internal signal assignments previously made to
sensitize a fault or propagate its effect are justified by setting PIs of the circuit.
PODEM:
In 1981, Goel proposed another way of looking at the search problem in ATPG. He
called the algorithm Podem, short for path-oriented decision making.3 Goel noticed
that the search graph used by the D algorithm includes every node in the circuit. For
combinational circuits, however, we really need to consider only nodes that are
primary inputs. All other nodes are a function of some set of the primary input nodes.
Thus, when we choose inputs as nodes in the search space, we will have no hidden
conflicts and each node can be assigned independently. Further, suppose that we
already have a set of primary input assignments and another primary input has been
assigned a value that causes a conflict. We would have to try only one other value
at that input (the complement of the current value) to determine if the current
assignment will ever be compatible with the goal. If the complementary value also
conflicts, then the goal cannot be achieved with the existing input assignments, and
we will need to backtrack further. Since we do not have to try any assignments
below this point, we can prune a large portion of the search graph and never search
it when such conflicts arise. The savings in computer time is enhanced because the
total search space is smaller than that of the D algorithm.
FAN:
The Fan-out Oriented (FAN) algorithm is a further improvement to PODEM with some
additional features. For instance, it utilizes circuit topology information to increase search
efficiency. FAN differs from PODEM in several ways, including the following: it stops
backtracking at certain internal lines; it performs multiple back-tracing; it allows both
backward and forward implications; and it immediately assigns uniquely-determined signals.
The test pattern generation algorithmic methods discussed in previous paragraphs are all
computation-intensive and can be quite expensive, not to mention the numerous difficulties
that may be encountered in complex cases.In fact, in some complex circuits, the use of such
algorithms is no longer feasible or practical.
Pseudo-random test:
Pseudo-random test pattern generation coupled with fault simulation is a simpler alternative to
algorithmic methods. This involves the generation of input vectors using a relatively
inexpensive pseudo random number generator and the performance of fault simulations to
determine if these vectors will lead to the detection of the target fault. The characteristics of
the target fault has a great influence on how well pseudo-random test generation will work.
It is typically used in the beginning of the test generation process to cover easy-to-detect
faults from the list of faults to be covered.Faults that were not covered by the pseudo-
random test generation may be covered by algorithmic methods.
Refrences